[
  {
    "path": ".clang-format",
    "content": "# Language part removed. With clang-format >=20.1, the C and Cpp are separately handled,\n# so either there is no language at all, or we need to create 2 formats for C and Cpp, separately\n\n---\n# Language: Cpp\n# BasedOnStyle:  LLVM\nAccessModifierOffset: -2\nAlignAfterOpenBracket: Align\nAlignArrayOfStructures: None\nAlignConsecutiveMacros:\n  Enabled: true\n  AcrossEmptyLines: true\n  AcrossComments: true\nAlignConsecutiveAssignments: None\nAlignConsecutiveBitFields:\n  Enabled: true\n  AcrossEmptyLines: true\n  AcrossComments: true\nAlignConsecutiveDeclarations: None\nAlignEscapedNewlines: Right\nAlignOperands: Align\nSortIncludes: true\nInsertBraces: true # Control statements must have curly brackets\nAlignTrailingComments: true\nAllowAllArgumentsOnNextLine: true\nAllowAllParametersOfDeclarationOnNextLine: true\nAllowShortEnumsOnASingleLine: true\nAllowShortBlocksOnASingleLine: Empty\nAllowShortCaseLabelsOnASingleLine: true\nAllowShortFunctionsOnASingleLine: All\nAllowShortLambdasOnASingleLine: All\nAllowShortIfStatementsOnASingleLine: Never\nAllowShortLoopsOnASingleLine: false\nAlwaysBreakAfterDefinitionReturnType: None\nAlwaysBreakAfterReturnType: AllDefinitions\nAlwaysBreakBeforeMultilineStrings: false\nAlwaysBreakTemplateDeclarations: Yes\nAttributeMacros:\n  - __capability\nBinPackArguments: true\nBinPackParameters: true\nBraceWrapping:\n  AfterCaseLabel: false\n  AfterClass: false\n  AfterControlStatement: Never\n  AfterEnum: false\n  AfterFunction: false\n  AfterNamespace: false\n  AfterObjCDeclaration: false\n  AfterStruct: false\n  AfterUnion: false\n  AfterExternBlock: false\n  BeforeCatch: false\n  BeforeElse: false\n  BeforeLambdaBody: false\n  BeforeWhile: false\n  IndentBraces: false\n  SplitEmptyFunction: true\n  SplitEmptyRecord: true\n  SplitEmptyNamespace: true\nBreakBeforeBinaryOperators: NonAssignment\nBreakBeforeConceptDeclarations: true\nBreakBeforeBraces: Attach\nBreakBeforeInheritanceComma: false\nBreakInheritanceList: BeforeColon\nBreakBeforeTernaryOperators: true\nBreakConstructorInitializersBeforeComma: false\nBreakConstructorInitializers: BeforeColon\nBreakAfterJavaFieldAnnotations: false\nBreakStringLiterals: true\nColumnLimit: 120\nCommentPragmas: \"^ IWYU pragma:\"\nQualifierAlignment: Leave\nCompactNamespaces: false\nConstructorInitializerIndentWidth: 4\nContinuationIndentWidth: 4\nCpp11BracedListStyle: true\nDeriveLineEnding: true\nDerivePointerAlignment: false\nDisableFormat: false\nEmptyLineAfterAccessModifier: Never\nEmptyLineBeforeAccessModifier: LogicalBlock\nExperimentalAutoDetectBinPacking: false\nPackConstructorInitializers: BinPack\nBasedOnStyle: \"\"\nConstructorInitializerAllOnOneLineOrOnePerLine: false\nAllowAllConstructorInitializersOnNextLine: true\nFixNamespaceComments: true\nForEachMacros:\n  - foreach\n  - Q_FOREACH\n  - BOOST_FOREACH\nIfMacros:\n  - KJ_IF_MAYBE\nIncludeBlocks: Preserve\nIncludeCategories:\n  - Regex: \"^<(.*)>\"\n    Priority: 0\n  - Regex: '^\"(.*)\"'\n    Priority: 1\n  - Regex: \"(.*)\"\n    Priority: 2\nIncludeIsMainRegex: \"(Test)?$\"\nIncludeIsMainSourceRegex: \"\"\nIndentAccessModifiers: false\nIndentCaseLabels: true\nIndentCaseBlocks: false\nIndentGotoLabels: true\nIndentPPDirectives: None\nIndentExternBlock: AfterExternBlock\nIndentRequires: true\nIndentWidth: 4\nIndentWrappedFunctionNames: false\nInsertTrailingCommas: None\nJavaScriptQuotes: Leave\nJavaScriptWrapImports: true\nKeepEmptyLinesAtTheStartOfBlocks: true\nLambdaBodyIndentation: Signature\nMacroBlockBegin: \"\"\nMacroBlockEnd: \"\"\nMaxEmptyLinesToKeep: 1\nNamespaceIndentation: None\nObjCBinPackProtocolList: Auto\nObjCBlockIndentWidth: 2\nObjCBreakBeforeNestedBlockParam: true\nObjCSpaceAfterProperty: false\nObjCSpaceBeforeProtocolList: true\nPenaltyBreakAssignment: 2\nPenaltyBreakBeforeFirstCallParameter: 19\nPenaltyBreakComment: 300\nPenaltyBreakFirstLessLess: 120\nPenaltyBreakOpenParenthesis: 0\nPenaltyBreakString: 1000\nPenaltyBreakTemplateDeclaration: 10\nPenaltyExcessCharacter: 1000000\nPenaltyReturnTypeOnItsOwnLine: 60\nPenaltyIndentedWhitespace: 0\nPointerAlignment: Left\nPPIndentWidth: -1\nReferenceAlignment: Pointer\nReflowComments: false\nRemoveBracesLLVM: false\nSeparateDefinitionBlocks: Always\nShortNamespaceLines: 1\nSortJavaStaticImport: Before\nSortUsingDeclarations: true\nSpaceAfterCStyleCast: false\nSpaceAfterLogicalNot: false\nSpaceAfterTemplateKeyword: true\nSpaceBeforeAssignmentOperators: true\nSpaceBeforeCaseColon: false\nSpaceBeforeParens: ControlStatements\nSpaceBeforeParensOptions:\n  AfterControlStatements: true\n  AfterForeachMacros: true\n  AfterFunctionDefinitionName: false\n  AfterFunctionDeclarationName: false\n  AfterIfMacros: true\n  AfterOverloadedOperator: false\n  BeforeNonEmptyParentheses: false\nSpaceAroundPointerQualifiers: Default\nSpaceBeforeRangeBasedForLoopColon: true\nSpaceInEmptyBlock: false\nSpaceInEmptyParentheses: false\nSpacesBeforeTrailingComments: 1\nSpacesInAngles: Never\nSpacesInConditionalStatement: false\nSpacesInContainerLiterals: true\nSpacesInCStyleCastParentheses: false\nSpacesInLineCommentPrefix:\n  Minimum: 1\n  Maximum: -1\nSpacesInParentheses: false\nSpacesInSquareBrackets: false\nSpaceBeforeSquareBrackets: false\nBitFieldColonSpacing: Both\nStandard: Latest\nStatementAttributeLikeMacros:\n  - Q_EMIT\nStatementMacros:\n  - Q_UNUSED\n  - QT_REQUIRE_VERSION\nTabWidth: 8\nUseCRLF: false\nUseTab: Never\nWhitespaceSensitiveMacros:\n  - STRINGIZE\n  - PP_STRINGIZE\n  - BOOST_PP_STRINGIZE\n  - NS_SWIFT_NAME\n  - CF_SWIFT_NAME\nSpaceBeforeCpp11BracedList: false\nSpaceBeforeCtorInitializerColon: true\nSpaceBeforeInheritanceColon: true\n---\n\n"
  },
  {
    "path": ".gitattributes",
    "content": "# Auto detect text files and perform LF normalization\n* text=auto\n\n# Custom for Visual Studio\n*.cs \tdiff=csharp\n\n# Standard to msysgit\n*.doc\tdiff=astextplain\n*.DOC\tdiff=astextplain\n*.docx \tdiff=astextplain\n*.DOCX \tdiff=astextplain\n*.dot  \tdiff=astextplain\n*.DOT  \tdiff=astextplain\n*.pdf  \tdiff=astextplain\n*.PDF \tdiff=astextplain\n*.rtf\tdiff=astextplain\n*.RTF\tdiff=astextplain"
  },
  {
    "path": ".github/FUNDING.yml",
    "content": "# These are supported funding model platforms\n\ncustom: ['paypal.me/tilz0R']\n"
  },
  {
    "path": ".github/workflows/release.yml",
    "content": "name: Release workflow\n\non:\n  push:\n    # Sequence of patterns matched against refs/tags\n    tags:\n      - 'v*' # Push events to matching v*, i.e. v1.0, v20.15.10\n\njobs:\n  # Create the release from the tag\n  create-release:\n    name: Create Release\n    runs-on: ubuntu-latest\n    steps:\n      - name: Checkout code\n        uses: actions/checkout@v2\n      - name: Create Release\n        id: create_release\n        uses: actions/create-release@v1\n        env:\n          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} \n        with:\n          tag_name: ${{ github.ref }}\n          release_name: Release ${{ github.ref }}\n          body: |\n            See the [CHANGELOG](CHANGELOG.md)\n          draft: false\n          prerelease: false\n\n  # Publish package to PlatformIO\n  publish-platformio:\n    runs-on: ubuntu-latest\n    steps:\n      - name: Checkout code\n        uses: actions/checkout@v4\n\n      - name: Set up Python\n        uses: actions/setup-python@v5\n        with:\n          python-version: \"3.x\"\n\n      - name: Install PlatformIO\n        run: pip install platformio\n\n      - name: Publish to PlatformIO\n        env:\n          PLATFORMIO_AUTH_TOKEN: ${{ secrets.PLATFORMIO_AUTH_TOKEN }}\n        run: pio pkg publish --type library --non-interactive\n"
  },
  {
    "path": ".gitignore",
    "content": "#Build Keil files\n*.rar\n*.o\n*.d\n*.crf\n*.htm\n*.dep\n*.map\n*.bak\n*.axf\n*.lnp\n*.lst\n*.ini\n*.scvd\n*.iex\n*.sct\n*.MajerleT\n*.tjuln\n*.tilen\n*.dbgconf\n*.uvguix\n*.uvoptx\n*.__i\n*.i\n*.txt\n!docs/*.txt\n!CMakeLists.txt\nRTE/\n\n*debug\n\n# IAR Settings\n**/settings/*.crun\n**/settings/*.dbgdt\n**/settings/*.cspy\n**/settings/*.cspy.*\n**/settings/*.xcl\n**/settings/*.dni\n**/settings/*.wsdt\n**/settings/*.wspos\n\n# IAR Debug Exe\n**/Exe/*.sim\n\n# IAR Debug Obj\n**/Obj/*.pbd\n**/Obj/*.pbd.*\n**/Obj/*.pbi\n**/Obj/*.pbi.*\n\n*.TMP\n/docs_src/x_Doxyfile.doxy\n\n.DS_Store\n\n## Ignore Visual Studio temporary files, build results, and\n## files generated by popular Visual Studio add-ons.\n##\n## Get latest from https://github.com/github/gitignore/blob/master/VisualStudio.gitignore\n\n# User-specific files\n*.suo\n*.user\n*.userosscache\n*.sln.docstates\n\n# User-specific files (MonoDevelop/Xamarin Studio)\n*.userprefs\n\n# Build results\n[Dd]ebug/\n[Dd]ebugPublic/\n[Rr]elease/\n[Rr]eleases/\n[Dd]ebug*/\nx64/\nx86/\nbld/\n[Bb]in/\n[Oo]bj/\n[Ll]og/\n_build/\nbuild/\n__build__/\n\n# Visual Studio 2015/2017 cache/options directory\n.vs/\n# Uncomment if you have tasks that create the project's static files in wwwroot\n#wwwroot/\n\n# Visual Studio 2017 auto generated files\nGenerated\\ Files/\n\n# MSTest test Results\n[Tt]est[Rr]esult*/\n[Bb]uild[Ll]og.*\n\n# NUNIT\n*.VisualState.xml\nTestResult.xml\n\n# Build Results of an ATL Project\n[Dd]ebugPS/\n[Rr]eleasePS/\ndlldata.c\n\n# Benchmark Results\nBenchmarkDotNet.Artifacts/\n\n# .NET Core\nproject.lock.json\nproject.fragment.lock.json\nartifacts/\n**/Properties/launchSettings.json\n\n# StyleCop\nStyleCopReport.xml\n\n# Files built by Visual Studio\n*_i.c\n*_p.c\n*_i.h\n*.ilk\n*.meta\n*.obj\n*.pch\n*.pdb\n*.pgc\n*.pgd\n*.rsp\n*.sbr\n*.tlb\n*.tli\n*.tlh\n*.tmp\n*.tmp_proj\n*.log\n*.vspscc\n*.vssscc\n.builds\n*.pidb\n*.svclog\n*.scc\n*.out\n*.sim\n\n# Chutzpah Test files\n_Chutzpah*\n\n# Visual C++ cache files\nipch/\n*.aps\n*.ncb\n*.opendb\n*.opensdf\n*.sdf\n*.cachefile\n*.VC.db\n*.VC.VC.opendb\n\n# Visual Studio profiler\n*.psess\n*.vsp\n*.vspx\n*.sap\n\n# Visual Studio Trace Files\n*.e2e\n\n# TFS 2012 Local Workspace\n$tf/\n\n# Guidance Automation Toolkit\n*.gpState\n\n# ReSharper is a .NET coding add-in\n_ReSharper*/\n*.[Rr]e[Ss]harper\n*.DotSettings.user\n\n# JustCode is a .NET coding add-in\n.JustCode\n\n# TeamCity is a build add-in\n_TeamCity*\n\n# DotCover is a Code Coverage Tool\n*.dotCover\n\n# AxoCover is a Code Coverage Tool\n.axoCover/*\n!.axoCover/settings.json\n\n# Visual Studio code coverage results\n*.coverage\n*.coveragexml\n\n# NCrunch\n_NCrunch_*\n.*crunch*.local.xml\nnCrunchTemp_*\n\n# MightyMoose\n*.mm.*\nAutoTest.Net/\n\n# Web workbench (sass)\n.sass-cache/\n\n# Installshield output folder\n[Ee]xpress/\n\n# DocProject is a documentation generator add-in\nDocProject/buildhelp/\nDocProject/Help/*.HxT\nDocProject/Help/*.HxC\nDocProject/Help/*.hhc\nDocProject/Help/*.hhk\nDocProject/Help/*.hhp\nDocProject/Help/Html2\nDocProject/Help/html\n\n# Click-Once directory\npublish/\n\n# Publish Web Output\n*.[Pp]ublish.xml\n*.azurePubxml\n# Note: Comment the next line if you want to checkin your web deploy settings,\n# but database connection strings (with potential passwords) will be unencrypted\n*.pubxml\n*.publishproj\n\n# Microsoft Azure Web App publish settings. Comment the next line if you want to\n# checkin your Azure Web App publish settings, but sensitive information contained\n# in these scripts will be unencrypted\nPublishScripts/\n\n# NuGet Packages\n*.nupkg\n# The packages folder can be ignored because of Package Restore\n**/[Pp]ackages/*\n# except build/, which is used as an MSBuild target.\n!**/[Pp]ackages/build/\n# Uncomment if necessary however generally it will be regenerated when needed\n#!**/[Pp]ackages/repositories.config\n# NuGet v3's project.json files produces more ignorable files\n*.nuget.props\n*.nuget.targets\n\n# Microsoft Azure Build Output\ncsx/\n*.build.csdef\n\n# Microsoft Azure Emulator\necf/\nrcf/\n\n# Windows Store app package directories and files\nAppPackages/\nBundleArtifacts/\nPackage.StoreAssociation.xml\n_pkginfo.txt\n*.appx\n\n# Visual Studio cache files\n# files ending in .cache can be ignored\n*.[Cc]ache\n# but keep track of directories ending in .cache\n!*.[Cc]ache/\n\n# Others\nClientBin/\n~$*\n*~\n*.dbmdl\n*.dbproj.schemaview\n*.jfm\n*.pfx\n*.publishsettings\norleans.codegen.cs\n\n# Including strong name files can present a security risk\n# (https://github.com/github/gitignore/pull/2483#issue-259490424)\n#*.snk\n\n# Since there are multiple workflows, uncomment next line to ignore bower_components\n# (https://github.com/github/gitignore/pull/1529#issuecomment-104372622)\n#bower_components/\n\n# RIA/Silverlight projects\nGenerated_Code/\n\n# Backup & report files from converting an old project file\n# to a newer Visual Studio version. Backup files are not needed,\n# because we have git ;-)\n_UpgradeReport_Files/\nBackup*/\nUpgradeLog*.XML\nUpgradeLog*.htm\n\n# SQL Server files\n*.mdf\n*.ldf\n*.ndf\n\n# Business Intelligence projects\n*.rdl.data\n*.bim.layout\n*.bim_*.settings\n\n# Microsoft Fakes\nFakesAssemblies/\n\n# GhostDoc plugin setting file\n*.GhostDoc.xml\n\n# Node.js Tools for Visual Studio\n.ntvs_analysis.dat\nnode_modules/\n\n# TypeScript v1 declaration files\ntypings/\n\n# Visual Studio 6 build log\n*.plg\n\n# Visual Studio 6 workspace options file\n*.opt\n\n# Visual Studio 6 auto-generated workspace file (contains which files were open etc.)\n*.vbw\n\n# Visual Studio LightSwitch build output\n**/*.HTMLClient/GeneratedArtifacts\n**/*.DesktopClient/GeneratedArtifacts\n**/*.DesktopClient/ModelManifest.xml\n**/*.Server/GeneratedArtifacts\n**/*.Server/ModelManifest.xml\n_Pvt_Extensions\n\n# Paket dependency manager\n.paket/paket.exe\npaket-files/\n\n# FAKE - F# Make\n.fake/\n\n# JetBrains Rider\n.idea/\n*.sln.iml\n\n# CodeRush\n.cr/\n\n# Python Tools for Visual Studio (PTVS)\n__pycache__/\n*.pyc\n\n# Cake - Uncomment if you are using it\n# tools/**\n# !tools/packages.config\n\n# Tabs Studio\n*.tss\n\n# Telerik's JustMock configuration file\n*.jmconfig\n\n# BizTalk build output\n*.btp.cs\n*.btm.cs\n*.odx.cs\n*.xsd.cs\n\n# OpenCover UI analysis results\nOpenCover/\n\n# Azure Stream Analytics local run output\nASALocalRun/\n\n# MSBuild Binary and Structured Log\n*.binlog\n\nlog_file.txt\n.metadata/\n.mxproject\n.settings/\nproject.ioc\nmx.scratch\n*.tilen majerle\n\n\n# Altium\nProject outputs*\nHistory/\n*.SchDocPreview\n*.$$$Preview\n\n# VSCode projects\nproject_vscode_compiled.exe"
  },
  {
    "path": ".gitmodules",
    "content": ""
  },
  {
    "path": ".readthedocs.yaml",
    "content": "version: 2\nbuild:\n  os: ubuntu-22.04\n  tools:\n    python: \"3.11\"\n\n# Build documentation in the docs/ directory with Sphinx\nsphinx:\n  configuration: docs/conf.py\n\n# Python configuration\npython:\n  install:\n    - requirements: docs/requirements.txt\n\nformats:\n  - pdf\n  - epub\n"
  },
  {
    "path": ".vscode/c_cpp_properties.json",
    "content": "{\n    \"version\": 4,\n    \"configurations\": [\n        {\n            /*\n             * Full configuration is provided by CMake plugin for vscode,\n             * that shall be installed by user\n             */\n            \"name\": \"Win32\",\n            \"intelliSenseMode\": \"${default}\",\n            \"configurationProvider\": \"ms-vscode.cmake-tools\"\n        }\n    ]\n}"
  },
  {
    "path": ".vscode/extensions.json",
    "content": "{\n    \"recommendations\": [\n        \"ms-vscode.cpptools\",\n        \"ms-vscode.cmake-tools\",\n        \"twxs.cmake\",\n    ]\n}"
  },
  {
    "path": ".vscode/launch.json",
    "content": "{\n    \"version\": \"0.2.0\",\n    \"configurations\": [\n        {\n            /* GDB must in be in the PATH environment */\n            \"name\": \"(Windows) Launch\",\n            \"type\": \"cppdbg\",\n            \"request\": \"launch\",\n            \"program\": \"${command:cmake.launchTargetPath}\",\n            \"args\": [],\n            \"stopAtEntry\": false,\n            \"cwd\": \"${fileDirname}\",\n            \"environment\": []\n        }\n    ]\n}"
  },
  {
    "path": ".vscode/settings.json",
    "content": "{\n    \"files.associations\": {\n        \"*.lcdjson\": \"json\",\n        \"lwevt_types.h\": \"c\",\n        \"lwevt_type.h\": \"c\",\n        \"lwevt.h\": \"c\",\n        \"string.h\": \"c\",\n        \"lwevt_opt.h\": \"c\",\n        \"cli.h\": \"c\",\n        \"windows.h\": \"c\",\n        \"lwesp_private.h\": \"c\",\n        \"lwesp_ll.h\": \"c\",\n        \"lwesp.h\": \"c\",\n        \"lwesp_includes.h\": \"c\",\n        \"lwesp_pbuf.h\": \"c\",\n        \"lwesp_opt.h\": \"c\",\n        \"LWESP_TYPES.h\": \"c\",\n        \"lwesp_opts.h\": \"c\",\n        \"lwesp_buff.h\": \"c\",\n        \"lwesp_debug.h\": \"c\",\n        \"lwesp_utils.h\": \"c\",\n        \"stdlib.h\": \"c\",\n        \"lwesp_unicode.h\": \"c\",\n        \"lwesp_ping.h\": \"c\",\n        \"lwesp_threads.h\": \"c\",\n        \"lwesp_int.h\": \"c\",\n        \"lwesp_sta.h\": \"c\",\n        \"lwesp_mqtt_client_api.h\": \"c\",\n        \"lwesp_cayenne.h\": \"c\",\n        \"lwesp_http_server.h\": \"c\",\n        \"lwesp_apps.h\": \"c\",\n        \"lwesp_mqtt_client.h\": \"c\",\n        \"lwesp_mqtt_client_evt.h\": \"c\",\n        \"lwesp_parser.h\": \"c\",\n        \"lwesp_debug_types.h\": \"c\",\n        \"lwesp_conn.h\": \"c\",\n        \"lwesp_flash.h\": \"c\",\n        \"lwesp_mem.h\": \"c\",\n        \"http_server.h\": \"c\",\n        \"cayenne.h\": \"c\",\n        \"examples_common_lwesp_callback_func.h\": \"c\",\n        \"*.hex\": \"c\",\n        \"lwesp_netconn.h\": \"c\",\n        \"netconn_client.h\": \"c\",\n        \"lwesp_sntp.h\": \"c\",\n        \"utils.h\": \"c\",\n        \"lwesp_flash_partitions.h\": \"c\",\n        \"math.h\": \"c\"\n    },\n    \"esbonio.sphinx.confDir\": \"\"\n}"
  },
  {
    "path": ".vscode/tasks.json",
    "content": "{\n\t\"version\": \"2.0.0\",\n\t\"tasks\": [\n        {\n            \"type\": \"cppbuild\",\n            \"label\": \"Build project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"-j\", \"8\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": [\"$gcc\"],\n            \"group\": {\n                \"kind\": \"build\",\n                \"isDefault\": true\n            }\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Re-build project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"--clean-first\", \"-v\", \"-j\", \"8\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": [\"$gcc\"],\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Clean project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"--target\", \"clean\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Run application\",\n            \"command\": \"${command:cmake.launchTargetPath}\",\n            \"args\": [],\n            \"problemMatcher\": [],\n        },\n        {\n            \"label\": \"Docs: Install python plugins from requirements.txt file\",\n            \"type\": \"shell\",\n            \"command\": \"python -m pip install -r requirements.txt\",\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}/docs\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"label\": \"Docs: Generate html\",\n            \"type\": \"shell\",\n            \"command\": \".\\\\make html\",\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}/docs\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"label\": \"Docs: Clean build directory\",\n            \"type\": \"shell\",\n            \"command\": \".\\\\make clean\",\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}/docs\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"label\": \"Build all WIN32 examples\",\n            \"type\": \"shell\",\n            \"command\": \"python\",\n            \"args\": [\n                \"build_all_examples.py\"\n            ],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}/examples/win32\"\n            },\n            \"problemMatcher\": []\n        }\n    ]\n}"
  },
  {
    "path": "AUTHORS",
    "content": "Tilen Majerle <tilen.majerle@gmail.com>\nAdrian Carpenter <adrian.carpenter@me.com>\nMiha Cesnik <cesnik.91@gmail.com>\nEvgeny Ermakov <evgeny.v.ermakov@gmail.com>\nMichal Převrátil <michprev@gmail.com>\nEvgeny Ermakov <>\nTom van der Geer <t.vandergeer@sping.nl>\nTilen Majerle <tilen@majerle.eu>\nturmary <turmary@126.com>\nBert <mail@bertlammers.com>\nniedong <niedong0816@126.com>\nneo <xiongyu0523@gmail.com>\nTakashiKusachi <aisiars@gmail.com>\nimi415 <imi415.public@gmail.com>\nlisekt84 <lisek84@interia.pl>"
  },
  {
    "path": "CHANGELOG.md",
    "content": "# Changelog\n\n## Develop\n\n- Change license year to 2022\n- MQTT: Improve module implementation\n- MQTT: Add optional SSL connection type\n- MQTT: Add cayenne async demo, publish-mode only through ring buffer\n- MQTT CAYENNE: Completely reworked with asynchronous MQTT instead. Improves performance to transmit more data in one shot\n- MQTT client: Add poll periodic event for event callback\n- Port: Improve ThreadX port\n- CONN: Enable manual TCP receive by default, to improve system stability\n- Timeout: module returns ERRMEM if no memory to allocate block\n- Add esp_at_binaries from Espressif, used for library verification (official AT firmware)\n- Add optional `AT+CMD?` command at reset/restore process, for debug purpose for the moment, only\n- Add function to get ESP device used for AT command communication\n- Fix `lwesp_get_min_at_fw_version` to return min AT version for detected ESP device\n- SNTP: Improve module comments, change timezone variable to `int16_t`\n- SNTP: Implement global callback when command is to obtain current time\n- SNTP: Add synchronization interval config, available with ESP AT `2.3.0` or later (ESP32-C3 only for the moment)\n- SNTP: Add option for readin current SNTP configuration\n- SNTP: Add option to automatically read SNTP data on `+TIME_UPDATED` event (requires ESP-AT v3.x or newer)\n- ERR: Add option to get response to `ERR CODE:` message if command doesn't exist and put it to result of command execution\n- Fix min at version for ESP32 to `2.2.0`\n- Add `LWESP ` prefix for debug messages\n- Update code style with astyle\n- Add `.clang-format` draft - remove astyle support\n- SSL: Added experimental support\n- FS: Added support for erase and write operation\n- Code improvement: Change multiple local variables to single structure\n- Date&Time `lwesp_datetime_t` and use generic `struct tm` instead\n- CONN: Add validation counter to ensure netconn object matches connection object and that there was no connection close/re-open in between\n- Minimum supported AT version is now `v3.2.0 (ESP32, ESP32-C3)` to support new MFG write operations\n- Added support for `ESP32-C2` and `ESP32-C6` AT commands\n- SYSFLASH: Split System flash and Manufacturing data to separate commands, following new breaking changes for ESP-AT firmware\n- WPS: Break API compatibility to configure the feature, by adding minimum security level parameter in the `lwesp_wps_set_config` function\n- Rework library CMake with removed INTERFACE type\n\n## 1.1.2-dev\n\n- Add POSIX-compliant low-level driver (thanks to community to implement it)\n- Prohibit transmission of too long UDP packets (default), can be disabled with configuration option\n- Split CMakeLists.txt files between library and executable\n- Move `esp_set_server` function to separate file `lwesp_server.c`\n- Use `AT+GMR` command just after reset/restore to determine ESP device being connected on AT port\n- Minimum required AT binaries are now `2.3.0` for `ESP32/ESP32C3` and `2.2.1` for `ESP8266`\n- Connection status is acquired with `AT+CIPSTATE` or `AT+CIPSTATUS`, depends on Espressif connected device\n- Add optional full fields for access point scan with `LWESP_CFG_ACCESS_POINT_STRUCT_FULL_FIELDS` config option\n- Add optional keep-alive periodic timeout to system event callback functions. Can be used to act as generic timeout event\n- Improve station manager snippet with asynchronous mode\n\n## v1.1.1-dev\n\n- Update to support library.json for Platform.IO\n\n## v1.1.0-dev\n\n- Add support for SDK v2.2\n- Extend number of information received on AP scan\n  - Add option for `WPA3` and `WPA2_WPA3_PSK` authentication modes\n  - Add bgn and wps readings\n- Add support for IPv6\n- Add option to disconnect all stations from Soft-AP\n- TODO: Add DNS for IPv6 support (Optional)\n- TODO: Add support for WIFI GOT IP to parse IPv6\n- Update CMSIS OS driver to support FreeRTOS aware kernel\n\n## v1.0.0\n\n- First stable release\n- Works with *esp-at* version `v2.1.0`\n- Implements all basic functionality for ESP8266 and ESP32\n- Added operating system-based sequential API\n- Other bug fixes and docs updates\n\n## v0.6.1\n\n- Fixed inadequate MQTT RX data handling causing possible overflow of memory\n- Added support for zero-copy MQTT RX data\n\n## v0.6.0\n\n- Added support for ESP32 & ESP8266\n- Official support for ESP32 AT firmware v1.2 & ESP8266 AT firmware v2.0\n- Added examples to main repository\n- Preparation for BLE support in ESP32\n- Removed AT commands with `_CUR` and `_DEF` suffixes\n- Renamed some event names, such as `ESP_EVT_CONN_CLOSE` instead of `ESP_EVT_CONN_CLOSED`\n- Added DHCP/static IP support\n- Added CMSIS-OS v2 support\n- Added LwMEM port for dynamic memory allocation\n- Other bug fixes\n\n## v0.5.0\n\n- Remove `_t` for every struct/enum name\n- Fully use ESP_MEMCPY instead of memcpy\n- When connection is in closing mode, stop sending any new data and return with error\n- Remove `_data` part from event helper function for connection receive\n- Implement semaphores in internal threads\n- Add driver for NUCLEO-F429\n- Implement timeout callback for major events when device does not reply in given time\n- Add callback function support to every API function which directly interacts with device\n- Replace all files to CRLF ending\n- Replace `ESP_EVT_RESET` to `ESP_EVT_RESET_DETECTED`\n- Replace `ESP_EVT_RESET_FINISH` to ESP_EVT_RESET`\n- Replace all header files guards with ESP_HDR_ prefix\n- Add espERRBLOCKING return when function is called in blocking mode when not allowed\n- Other bug fixes to stabilize AT communication\n\n## v0.4.0\n\n- Add sizeof for every memory allocation\n- Function typedefs suffix has been renamed to `_fn` instead of `_t`\n- Merge events for connection data send and data send error\n- Send callback if sending data is not successful in any case (timeout, ERROR, etc)\n- Add functions for IP/port retrieval on connections\n- Remove goto statements and use deep if statements\n- Fix MQTT problems with username and password\n- Make consistent variable types across library\n\n## v1.3.0\n\n- Rename all cb annotations with evt, replacing callbacks with events,\n- Replace built-in memcpy and memset functions with `ESP_MEMCPY` and `ESP_MEMSET` to allow users to do custom implementation\n- Added example for Server RTOS\n- Added API to unchain first pbuf in pbuf chain\n- Implemented first prototype for manual TCP receive functionality.\n\n## v0.2.0\n\n- Fixed netconn issue with wrong data type for OS semaphore\n- Added support for asynchronous reset\n- Added support for tickless sleep for modern RTOS systems\n\n## v0.1.0\n\n- Initial release\n"
  },
  {
    "path": "CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.22)\n\n# Setup project\nproject(LwLibPROJECT)\n\nif(NOT PROJECT_IS_TOP_LEVEL)\n    add_subdirectory(lwesp)\nelse()\n    add_executable(${PROJECT_NAME})\n    target_sources(${PROJECT_NAME} PRIVATE\n        ${CMAKE_CURRENT_LIST_DIR}/dev/main.c\n\n        # Development additional files\n        ${CMAKE_CURRENT_LIST_DIR}/lwesp/src/system/lwesp_mem_lwmem.c\n        ${CMAKE_CURRENT_LIST_DIR}/../lwmem/lwmem/src/lwmem/lwmem.c\n        ${CMAKE_CURRENT_LIST_DIR}/../lwmem/lwmem/src/system/lwmem_sys_win32.c\n\n        # Http server file system\n        ${CMAKE_CURRENT_LIST_DIR}/lwesp/src/apps/http_server/lwesp_http_server_fs_win32.c\n\n        # Port specific\n        ${CMAKE_CURRENT_LIST_DIR}/lwesp/src/system/lwesp_ll_win32.c\n    )\n    target_include_directories(${PROJECT_NAME} PUBLIC\n        ${CMAKE_CURRENT_LIST_DIR}\n        ${CMAKE_CURRENT_LIST_DIR}/dev\n        ${CMAKE_CURRENT_LIST_DIR}/../lwmem/lwmem/src/include\n    )\n\n    # Add subdir with lwesp and link to the project\n    set(LWESP_OPTS_FILE ${CMAKE_CURRENT_LIST_DIR}/dev/lwesp_opts.h)\n    set(LWESP_SYS_PORT \"win32\")\n    add_subdirectory(lwesp)\n    target_link_libraries(${PROJECT_NAME} PUBLIC lwesp_api)\n    target_link_libraries(${PROJECT_NAME} PUBLIC lwesp_apps)\n    target_link_libraries(${PROJECT_NAME} PUBLIC lwesp)\n    add_subdirectory(snippets)\n    target_link_libraries(${PROJECT_NAME} PUBLIC lwesp_snippets)\n\n    # Add compile options to the library, which will propagate options to executable through public link\n    target_compile_definitions(lwesp PUBLIC WIN32 _DEBUG CONSOLE LWESP_DEV)\n    target_compile_options(lwesp PUBLIC -Wall -Wextra -Wpedantic)\nendif()\n"
  },
  {
    "path": "CMakePresets.json",
    "content": "{\n    \"version\": 3,\n    \"configurePresets\": [\n        {\n            \"name\": \"default\",\n            \"hidden\": true,\n            \"generator\": \"Ninja\",\n            \"binaryDir\": \"${sourceDir}/build/${presetName}\",\n            \"cacheVariables\": {\n                \"CMAKE_EXPORT_COMPILE_COMMANDS\": \"ON\"\n            }\n        },\n        {\n            \"name\": \"Win32-Debug\",\n            \"inherits\": \"default\",\n            \"toolchainFile\": \"${sourceDir}/cmake/i686-w64-mingw32-gcc.cmake\",\n            \"cacheVariables\": {\n                \"CMAKE_BUILD_TYPE\": \"Debug\"\n            }\n        },\n        {\n            \"name\": \"Win64-Debug\",\n            \"inherits\": \"default\",\n            \"toolchainFile\": \"${sourceDir}/cmake/x86_64-w64-mingw32-gcc.cmake\",\n            \"cacheVariables\": {\n                \"CMAKE_BUILD_TYPE\": \"Debug\"\n            }\n        }\n    ],\n    \"buildPresets\": [\n        {\n            \"name\": \"Win32-Debug\",\n            \"configurePreset\": \"Win32-Debug\"\n        },\n        {\n            \"name\": \"Win64-Debug\",\n            \"configurePreset\": \"Win64-Debug\"\n        }\n    ]\n}"
  },
  {
    "path": "LICENSE",
    "content": "MIT License\n\nCopyright (c) 2025 Tilen MAJERLE\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n"
  },
  {
    "path": "README.md",
    "content": "# Lightweight ESP-AT parser\n\nLwESP is lightweight ESP AT commands parser library to communicate with ESP8266 or ESP32 Wi-Fi modules using AT commands.\nModule is written in C99 and is system platform agnostic. Its main targets are embedded system devices like ARM Cortex-M, AVR, PIC and others, but can easily work under `Windows`, `Linux` or `MAC` environments too.\n\nEspressif module runs official [AT Commands (esp-at)](https://github.com/espressif/esp-at) software and communicates with host device via UART or SPI communication protocol.\n\nFollow documentation for more information on implementation and details.\n\n<h3>Read first: <a href=\"https://docs.majerle.eu/projects/lwesp/\">Documentation</a></h3>\n\n## Features\n\n- Supports latest ESP32, ESP32-C2, ESP32-C3, ESP32-C6 & ESP8266 AT software from Espressif system\n- Platform independent and very easy to port\n- Development of library under Win32 platform\n- Available examples for ARM Cortex-M, Win32 or POSIX (mostly Linux) platforms\n- Written in C language (C99)\n- Allows different configurations to optimize user requirements\n- Supports implementation with operating systems with advanced inter-thread communications\n- Uses `2` tasks for data handling from user and device\n- Includes several applications built on top of library\n  - Netconn sequential API for client and server\n  - HTTP server with dynamic files (file system) supported\n  - MQTT client\n- Embeds other AT features, such as WPS management, custom DNS setup, Hostname for DHCP, Ping feature\n- User friendly MIT license\n\n## Contribute\n\nFresh contributions are always welcome. Simple instructions to proceed:\n\n1. Fork Github repository\n2. Follow [C style & coding rules](https://github.com/MaJerle/c-code-style) already used in the project\n3. Create a pull request to develop branch with new features or bug fixes\n\nAlternatively you may:\n\n1. Report a bug\n2. Ask for a feature request\n"
  },
  {
    "path": "TODO.md",
    "content": "# TODO list\n\n- Implement `AT+CWSTATE` to query Wi-Fi state\n- Implement `AT+CIPSENDL` and `AT+CIPSENDLCFG` for long data send\n- Implement `AT+CIPTCPOPT` to configure TCP connection\n- Implement BLE feature\n- Implement BT feature\n- Transfer Cayenne MQTT app to be based on non-blocking API instead\n- Add DNS for IPv6 support (Optional)\n- Add `AT+CWJEAP` for WPA2 connections\n- Implement single callback when station is connected and IP is received (so far STA_GOT_IP may be called several times in a row, when IP v4 and v6 are received)\n   - Implement new type of event instead, that is called only once per connection\n- Add support for wifi mode `0` that has disabled WIFI IP"
  },
  {
    "path": "certificates/client_ca_00.crt",
    "content": "-----BEGIN CERTIFICATE-----\nMIIDLTCCAhWgAwIBAgIJAMQZBKBLTB95MA0GCSqGSIb3DQEBBQUAMDcxCzAJBgNV\nBAYTAlMxMQ8wDQYDVQQKDAZFU1AgUzExFzAVBgNVBAMMDkVTUCBSb290IENBIFMx\nMB4XDTE5MDYyMTA4MDAyMloXDTI5MDYxODA4MDAyMlowNzELMAkGA1UEBhMCUzEx\nDzANBgNVBAoMBkVTUCBTMTEXMBUGA1UEAwwORVNQIFJvb3QgQ0EgUzEwggEiMA0G\nCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQCt/chHLK76uZwnGywrmWDFt8ixoH2G\nKJi3QzEW0MT0GUX1/6bCRKEkvDY6Neze26+a6sJCwbhOLcCGIxiPi2L2QHeCrO2n\nPxTfl2pGm+Vhe0TzTJhHpBSrdbnk2DQBjg6CzK+3f6ZBSuKACpMfHg5Xovgq/2Uz\nN3Dz1nZ5N90OlNSNBjFW4i9vIk5LtSh62cEFtdGjwGlXtfm4k30ZxfZF8P9z9FXI\nm9t6L8+B0UqE2Bysg/pHadmw/D0IOqnyji/gzJ56dLQES/Of1R0LQ9EG7ZZLG3eM\n1IsSww+0/Iarm1LqAFfTE3NbYkSajAEXIFEsbHpIw4A36y6A80orIq8bAgMBAAGj\nPDA6MAwGA1UdEwQFMAMBAf8wCwYDVR0PBAQDAgGmMB0GA1UdDgQWBBQE1Ucuke3Z\nPAiqLlJFyBWR3nV0ujANBgkqhkiG9w0BAQUFAAOCAQEAMgH0OyIh2kgw4s7Gv1Uo\nvDKhCCO0GqRYBAzEkXbHSJdl1pYFyp2yNCnPWztF6aDAmM9EzWNOJQlig4xwB1SZ\nTgk3ov6tkRicfbwhvIfAvvb/XWfVo1XsL20Bp4euE/tI9JmPGOUzuiQWaxVrlkuc\nqAg4U3gcHY6nBkanpbY9idPF4lDLYZNkxe3+0mp50NxHmiuM/ShoR8xs0ee4fydV\nwI52uuiEGtjcivHPr0t8J8N+dXJPKqddszsrelwuCDsYMhpJLR2obTMxJx1aP5Zx\njw5BTh1TrdGUDe2JumZ7YDUpkQHnfdR7XTF6XubbeJBjHwWr1A7AzFwmbZDO266s\nRw==\n-----END CERTIFICATE-----\n"
  },
  {
    "path": "certificates/client_ca_generated_atpki.hex",
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  },
  {
    "path": "certificates/client_cert_00.crt",
    "content": "-----BEGIN CERTIFICATE-----\nMIIDLTCCAhWgAwIBAgIJAN6LrsW0Qt2FMA0GCSqGSIb3DQEBCwUAMDcxCzAJBgNV\nBAYTAkMxMQ8wDQYDVQQKDAZFU1AgQzExFzAVBgNVBAMMDkVTUCBSb290IENBIEMx\nMB4XDTE5MDYyMTA4MDAyM1oXDTI5MDYxODA4MDAyM1owNzELMAkGA1UEBhMCQzIx\nDzANBgNVBAoMBkVTUCBDMjEXMBUGA1UEAwwORVNQIFJvb3QgQ0EgQzIwggEiMA0G\nCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQC02DXgCw0gSDShaHLDlanRppKjIoJ0\nJW/+gDkg8j1PCNm5WxkAx3BItBN6hnJwwlQ4DMWCZXe+EDDYz8cKLC5g2TetrpxJ\naSQ4JyPqxU5uiym26C+nTL9/d40Nom//3+fDjA0+7bdUkffcKdhZV7MsxKF2dBb9\neKFJeIjc8q0Q0LqKr3xnKOeGN2Xt80oJTv8XIEfko/mfkINr83AhH/WPkSg2kJS/\nC2Xyl6Q22ew01vZv0Am5ocl3+ju2Dyv/nbQl2Vru1K9TD+b8fDacmqZco4oeQBvf\nEhyW7FOhUf2yLgpUdEEGyAMZ9JgoTJih1dnr9CLHkt/XMCn03HOcfpPlAgMBAAGj\nPDA6MAwGA1UdEwQFMAMBAf8wCwYDVR0PBAQDAgGmMB0GA1UdDgQWBBR+kprR64Cl\nlQZk6w6hJGlsrerCTTANBgkqhkiG9w0BAQsFAAOCAQEAYfcgIyQsA+lvlIMIz+1z\ncyhnGuwywEEa0h5pGvWizxfx/EARam5sCXC49i3S788wAqbdg3d8iQp662ybT3O0\nWimqJDgr7LFIMq8UIxJHIMdcf7mUmleUJUmbAiFAo1XWb6MoVIUW7aR1+0aKKCIK\nOcvYlvkenM3P+lLQe/nEvnvyhsc78V4V56FKz/S+ePsgSIurEaDnFe8LSZ5aHESB\np9muQdGJYMuR1GnZbINix/4j8Q0S5z2MI+6bWqU9cfk1rFuHqd4tZ6BmLCAFC7fH\nw6s/PGhr0UHx+NmTmdOvp9Ny2qLO9vvfl5h7wDG/pzcGvbYWHPZSvPeNVQRE13DH\nDg==\n-----END CERTIFICATE-----\n"
  },
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  },
  {
    "path": "certificates/client_key_00.key",
    "content": "-----BEGIN RSA PRIVATE KEY-----\nMIIEowIBAAKCAQEAtNg14AsNIEg0oWhyw5Wp0aaSoyKCdCVv/oA5IPI9TwjZuVsZ\nAMdwSLQTeoZycMJUOAzFgmV3vhAw2M/HCiwuYNk3ra6cSWkkOCcj6sVObosptugv\np0y/f3eNDaJv/9/nw4wNPu23VJH33CnYWVezLMShdnQW/XihSXiI3PKtENC6iq98\nZyjnhjdl7fNKCU7/FyBH5KP5n5CDa/NwIR/1j5EoNpCUvwtl8pekNtnsNNb2b9AJ\nuaHJd/o7tg8r/520Jdla7tSvUw/m/Hw2nJqmXKOKHkAb3xIcluxToVH9si4KVHRB\nBsgDGfSYKEyYodXZ6/Qix5Lf1zAp9NxznH6T5QIDAQABAoIBAHPyyCAclc7j3LK8\nSBC0jYv40726q4+STUsMpRRFnB9nWkkoalCAjrJemrqNJyS6w8qoDZ58NhjrQpZQ\nKZqRFy9LNhKqiFPdELbcCYBF/vKLUTSPi7YlVAaC/TIHuu2AfpV23ytAuLGFYTiM\nr8UgoKWMcMWEyxS62hZELOQUx/el9xjTv3+HWS9804qcrdyqztJRw2M1fton8C3w\nGPVZ7uwr2aqyuFDLAS17tanTl1E66iczHef+cTK4TjGLIMcNkNHPerAqJ7Le6o1R\nVQaRJX7pVq5uc3jty84PndWhX/Uyo0t3bsI1x+62L6JA37ML4WSDZtBzWyQPJw0l\nYJ8U1SUCgYEA7dO84bV51seNO+vqejCGpk69LQj5wCh06iROcjb3knbODQbRQKOM\n6g21e++Z4WEfoQWaLZVdPn71cXR+EbOvfacG5tGpDus0ZhxH4IM3HmYb5vfcJ0mU\nbyiPfZQSVxjCsdV2vWsbZbHKl5p0UaAyiyT2pMkl4ngySL1OE2dlm2sCgYEAwqnO\noE22l2O/HCBpAmG/7IyOLjhbTuUHlshe8O3KH18/WFbp4Nvf2qv+FZoCRp0W7B+4\n2P9Ncusq3M10TsUh3A/5QOineCPsKe22UTzs2WOAP+YT0MORFWmQttnEETn2+3zS\nsdu6M0K7K/XYtEHcgFM3TT4iP+keYemsYGlpMe8CgYAU0pcVA/iY73vUJUGwVRNU\n+Evj54dGZcRmw6sCoQFoF3LO/SvRBwDNdUnQghfs/b3xMTZgi1VQpXkD5/kpv5u7\n2qXmC7FLlxhNYGiCpbprtPD4dfcWkYCngtudWRuJ+KcDPvdYeko5yyk7wNAyXV5P\nhHr7zoi8nV15tOljFYh15QKBgQC/sKegg+aCPd87u06s4cU1E1QPf7+qeS539OhJ\nKGAZdJnUTAITQ3G0zBlw/C+xiY/BBZvpU77Yo2uZ81fNGaK2KaSxnmkLjZRJ1aPr\na6twhuMMCW0J7ws3orS22sqQjBwCmnCAZHd/cv8N0xKKrzCLzWZv0fe4J7+be5gb\neLH2UQKBgA6DmumbC+aqdSFaYphFFiCEXzrr6o6Iy1d694Ll+Umsx8JnI3TaRuAy\ncDLbLZ41vKeRqkm0ylLEBwsVa7/ycL29eG5vzI4mSg8XABDZaCbOfpyrJzruGTKg\nG4NFJpOVnlhhl5qcKsWhkBwvTGao4+j7FFI1SmbvwxtzmhpvDp/e\n-----END RSA PRIVATE KEY-----\n"
  },
  {
    "path": "certificates/client_key_generated_atpki.HEX",
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    "path": "dev/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#if !__DOXYGEN__\n\n#define LWESP_CFG_IPV6                            1\n\n#define LWESP_CFG_NETCONN                         1\n#define LWESP_CFG_NETCONN_RECEIVE_QUEUE_LEN       16\n\n#define LWESP_CFG_DBG                             LWESP_DBG_ON\n#define LWESP_CFG_DBG_TYPES_ON                    LWESP_DBG_TYPE_TRACE | LWESP_DBG_TYPE_STATE\n#define LWESP_CFG_DBG_IPD                         LWESP_DBG_OFF\n#define LWESP_CFG_DBG_SERVER                      LWESP_DBG_OFF\n#define LWESP_CFG_DBG_MQTT                        LWESP_DBG_OFF\n#define LWESP_CFG_DBG_MEM                         LWESP_DBG_OFF\n#define LWESP_CFG_DBG_PBUF                        LWESP_DBG_OFF\n#define LWESP_CFG_DBG_CONN                        LWESP_DBG_OFF\n#define LWESP_CFG_DBG_VAR                         LWESP_DBG_OFF\n#define LWESP_CFG_RCV_BUFF_SIZE                   0x1000\n\n#define LWESP_CFG_MEM_CUSTOM                      1\n\n#define LWESP_CFG_REST_CLIENT                     1\n\n#define LWESP_CFG_ESP32                           1\n#define LWESP_CFG_ESP8266                         1\n#define LWESP_CFG_ESP32_C2                        1\n#define LWESP_CFG_ESP32_C3                        1\n#define LWESP_CFG_ESP32_C6                        1\n\n#define LWESP_CFG_CONN_MAX_DATA_LEN               1500\n#define LWESP_CFG_INPUT_USE_PROCESS               1\n#define LWESP_CFG_AT_ECHO                         0\n\n#define LWESP_CFG_USE_API_FUNC_EVT                1\n\n#define LWESP_CFG_MAX_CONNS                       5\n\n#define LWESP_CFG_DNS                             1\n#define LWESP_CFG_SNTP                            1\n#define LWESP_CFG_SNTP_AUTO_READ_TIME_ON_UPDATE   1\n#define LWESP_CFG_HOSTNAME                        1\n#define LWESP_CFG_WPS                             1\n#define LWESP_CFG_MDNS                            1\n#define LWESP_CFG_PING                            1\n#define LWESP_CFG_FLASH                           1\n#define LWESP_CFG_MODE_STATION                    1\n\n#define LWESP_CFG_RESET_ON_INIT                   1\n#define LWESP_CFG_RESTORE_ON_INIT                 0\n#define LWESP_CFG_CONN_MANUAL_TCP_RECEIVE         1\n\n#define LWESP_CFG_ACCESS_POINT_STRUCT_FULL_FIELDS 1\n#define LWESP_CFG_LIST_CMD                        1\n\n#define LWESP_CFG_MQTT_MAX_REQUESTS               32\n\n#endif /* !__DOXYGEN__ */\n\n#endif /* LWESP_HDR_OPTS_H */\n"
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    "path": "dev/lwmem_opts.h",
    "content": "/**\n * \\file            lwmem_opts.h\n * \\brief           LwMEM application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwMEM - Lightweight dynamic memory manager library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWMEM_HDR_OPTS_H\n#define LWMEM_HDR_OPTS_H\n\n/* Rename this file to \"lwmem_opts.h\" for your application */\n\n#include \"windows.h\"\n\n/*\n * Open \"include/lwmem/lwmem_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWMEM_CFG_OS                            1\n#define LWMEM_CFG_OS_MUTEX_HANDLE               HANDLE\n\n#endif /* LWMEM_HDR_OPTS_H */\n"
  },
  {
    "path": "dev/main.c",
    "content": "// lwesp_dev_os.cpp : Defines the entry point for the console application.\n//\n\n#include <string.h>\n#include \"examples_common_lwesp_callback_func.h\"\n#include \"lwesp/apps/lwesp_mqtt_client_api.h\"\n#include \"lwesp/lwesp.h\"\n#include \"windows.h\"\n\n#include \"http_server.h\"\n#include \"lwesp/lwesp_opt.h\"\n#include \"lwesp/lwesp_timeout.h\"\n#include \"lwmem/lwmem.h\"\n#include \"mqtt_client.h\"\n#include \"mqtt_client_api.h\"\n#include \"netconn_client.h\"\n#include \"netconn_server.h\"\n#include \"netconn_server_1thread.h\"\n#include \"sntp.h\"\n#include \"station_manager.h\"\n#include \"utils.h\"\n\n#define safeprintf printf\n\nstatic void main_thread(void* arg);\nstatic void input_thread(void* arg);\n\nstatic lwesp_ap_t aps[10];\nstatic size_t aps_count;\n\nstatic lwespr_t lwesp_evt(lwesp_evt_t* evt);\n\nstatic lwesp_sta_info_ap_t connected_ap_info;\nextern volatile uint8_t lwesp_ll_win32_driver_ignore_data;\n\nstatic uint8_t parse_str(char** str, char** out);\nstatic uint8_t parse_num_u64(char** str, uint64_t* out);\nstatic uint8_t parse_num(char** str, uint32_t* out);\n\n/**\n * \\brief           LwMEM memory config\n */\nuint8_t lwmem_region_1[0x4000];\nlwmem_region_t lwmem_regions[] = {\n    {lwmem_region_1, sizeof(lwmem_region_1)},\n    {NULL, 0},\n};\n\n/**\n * \\brief           Command structure\n */\ntypedef struct {\n    uint8_t del;             /*!< Delimiter */\n    const char* cmd;         /*!< Command text */\n    const char* help_params; /*!< Help parameters */\n    const char* help_text;   /*!< Help long text */\n} cmd_t;\n\n/**\n * \\brief           List of test commands\n */\nstatic const cmd_t cmd_commands[] = {\n    {0, \"help\", \"\", \"Print help for commands\"},\n    {0, \"join\", \"<ssid> [<pwd> [<mac>]]\", \"Join to access point\"},\n    {0, \"reconn_set\", \"<interval> <repeat>\", \"Set reconnect config\"},\n    {0, \"quit\", \"\", \"Quit from access point\"},\n    {1, \"IP management\", NULL, NULL},\n    {0, \"stagetip\", \"\", \"Get station IP address\"},\n    {0, \"stasetip\", \"<ip>\", \"Set station IP address\"},\n    {0, \"apgetip\", \"\", \"Get Soft Access point IP address\"},\n    {0, \"apsetip\", \"<ip>\", \"Set Soft Access point IP address\"},\n    {0, \"setdhcp\", \"<enable>\", \"Enable or disable DHCP\"},\n    {1, \"MAC management\", NULL, NULL},\n    {0, \"stagetmac\", \"\", \"Get station MAC address\"},\n    {0, \"stasetmac\", \"<mac>\", \"Set station MAC address\"},\n    {0, \"apgetmac\", \"\", \"Get Soft Access point MAC address\"},\n    {0, \"apsetmac\", \"<mac>\", \"Set Soft Access point MAC address\"},\n    {1, \"Access point\", NULL, NULL},\n    {0, \"apconfig\", \"<enable> [<ssid> <pass> <enc> <ch>]\", \"Configure Soft Access point\"},\n    {0, \"apliststa\", \"\", \"List stations connected to access point\"},\n    {0, \"apquitsta\", \"<mac>\", \"Disconnect station for Soft access point\"},\n    {1, \"Hostname\", NULL, NULL},\n    {0, \"hnset\", \"<hostname>\", \"Set station hostname\"},\n    {0, \"hnget\", \"\", \"Get station hostname\"},\n    {1, \"Misc\", NULL, NULL},\n    {0, \"ping\", \"<host>\", \"Ping domain or IP address\"},\n    {1, \"Separate threads\", NULL, NULL},\n    {0, \"netconn_client\", \"\", \"Start netconn client thread\"},\n    {0, \"netconn_server\", \"\", \"Start netconn server thread\"},\n    {0, \"mqtt_client_api\", \"\", \"Start mqtt client API thread\"},\n    {0, \"ciupdate\", \"\", \"Run ciupdate command\"},\n    {0, \"dhcpenable\", \"\", \"Enable DHCP\"},\n    {0, \"dhcpdisable\", \"\", \"Disable DHCP\"},\n    {0, \"wifidisable\", \"\", \"Disable WIFI mode completely\"}};\n\n/**\n * \\brief           Program entry point\n */\nint\nmain() {\n    safeprintf(\"App start!\\r\\n\");\n\n    /* Setup regions for memory as a start */\n    if (!lwmem_assignmem(lwmem_regions)) {\n        safeprintf(\"Could not assign memory for LwMEM!\\r\\n\");\n        return -1;\n    }\n\n    /* Create main threads */\n    CreateThread(0, 0, (LPTHREAD_START_ROUTINE)main_thread, NULL, 0, NULL);\n    CreateThread(0, 0, (LPTHREAD_START_ROUTINE)input_thread, NULL, 0, NULL);\n\n    /* Do nothing at this point but do not close the program */\n    while (1) {\n        lwesp_delay(1000);\n    }\n}\n\n/**\n * \\brief           Main thread for init purposes\n */\nstatic void\nmain_thread(void* arg) {\n    char hn[10];\n    uint32_t ping_time;\n\n    LWESP_UNUSED(hn);\n    LWESP_UNUSED(arg);\n    LWESP_UNUSED(ping_time);\n\n    /* Init ESP library */\n    lwesp_init(lwesp_evt, 1);\n    if (0) {\n#if LWESP_CFG_ESP32\n    } else if (lwesp_device_is_device(LWESP_DEVICE_ESP32)) {\n        safeprintf(\"Device is ESP32\\r\\n\");\n#endif /* LWESP_CFG_ESP32 */\n#if LWESP_CFG_ESP8266\n    } else if (lwesp_device_is_device(LWESP_DEVICE_ESP8266)) {\n        safeprintf(\"Device is ESP8266\\r\\n\");\n#endif /* LWESP_CFG_ESP8266 */\n#if LWESP_CFG_ESP32_C2\n    } else if (lwesp_device_is_device(LWESP_DEVICE_ESP32_C2)) {\n        safeprintf(\"Device is ESP32-C2\\r\\n\");\n#endif /* LWESP_CFG_ESP32_C2 */\n#if LWESP_CFG_ESP32_C3\n    } else if (lwesp_device_is_device(LWESP_DEVICE_ESP32_C3)) {\n        safeprintf(\"Device is ESP32-C3\\r\\n\");\n#endif /* LWESP_CFG_ESP32_C3 */\n#if LWESP_CFG_ESP32_C6\n    } else if (lwesp_device_is_device(LWESP_DEVICE_ESP32_C6)) {\n        safeprintf(\"Device is ESP32-C6\\r\\n\");\n#endif /* LWESP_CFG_ESP32_C6 */\n    } else {\n        safeprintf(\"Unknown device...\\r\\n\");\n    }\n\n#if 0\n    uint8_t read_data_buffer[1024];\n    uint32_t read_data_length;\n    lwesp_mfg_read(LWESP_MFG_NAMESPACE_SERVER_CERT, \"server_cert\", read_data_buffer, sizeof(read_data_buffer), 0,\n                   &read_data_length, NULL, NULL, 1);\n    printf(\"Len: %u\\r\\n\", (unsigned)read_data_length);\n    lwesp_mfg_read(LWESP_MFG_NAMESPACE_SERVER_CERT, \"server_cert\", read_data_buffer, 15, 20, &read_data_length, NULL,\n                   NULL, 1);\n    printf(\"Len: %u\\r\\n\", (unsigned)read_data_length);\n#endif\n\n    /* Start thread to toggle device present */\n    //lwesp_sys_thread_create(NULL, \"device_present\", (lwesp_sys_thread_fn)lwesp_device_present_toggle, NULL, 0, LWESP_SYS_THREAD_PRIO);\n\n    /*\n     * Try to connect to preferred access point\n     *\n     * Follow function implementation for more info\n     * on how to setup preferred access points for fast connection\n     */\n    lwesp_sta_autojoin(0, NULL, NULL, 1);\n\n    /*\n     * Initialize and start asynchronous connection to preferred acces point\n     *\n     * Will immediately return and will not block the application.\n     * All events are done asynchronously\n     */\n    station_manager_connect_to_access_point_async_init();\n\n    /* Different types of snippets to execute */\n\n    /* HTTP server application example */\n\n    /* SNTP example */\n    sntp_gettime();\n\n    /* Netconn client in separate thread */\n    //lwesp_sys_thread_create(NULL, \"netconn_client\", (lwesp_sys_thread_fn)netconn_client_thread, NULL, 0, LWESP_SYS_THREAD_PRIO);\n\n    /* Netconn client in separate thread */\n    //lwesp_sys_thread_create(NULL, \"netconn_client_ssl\", (lwesp_sys_thread_fn)netconn_client_ssl_thread, NULL, 0, LWESP_SYS_THREAD_PRIO);\n\n    /* Netconn server with multiple threads */\n    //lwesp_sys_thread_create(NULL, \"netconn_server\", (lwesp_sys_thread_fn)netconn_server_thread, NULL, 0, LWESP_SYS_THREAD_PRIO);\n\n    /* Netconn server with single thread */\n    //lwesp_sys_thread_create(NULL, \"netconn_server_single\", (lwesp_sys_thread_fn)netconn_server_1thread_thread, NULL, 0, LWESP_SYS_THREAD_PRIO);\n\n    /* MQTT client with asynchronous events */\n    //lwesp_sys_thread_create(NULL, \"mqtt_client\", (lwesp_sys_thread_fn)mqtt_client_thread, NULL, 0, LWESP_SYS_THREAD_PRIO);\n\n    /* MQTT client with API sequential mode, test application */\n    //lwesp_sys_thread_create(NULL, \"mqtt_client_api\", (lwesp_sys_thread_fn)lwesp_mqtt_client_api_thread, NULL, 0, LWESP_SYS_THREAD_PRIO);\n\n    /* MQTT API client with connectivity to home assistant */\n    lwesp_sys_thread_create(NULL, \"mqtt_client_api_ha\", (lwesp_sys_thread_fn)lwesp_mqtt_client_api_ha_thread, NULL, 0,\n                            LWESP_SYS_THREAD_PRIO);\n\n    /* While loop with delay to prevent main thread termination in development environment */\n    while (1) {\n        lwesp_delay(1000);\n    }\n}\n\n/**\n * \\brief           Console input thread\n */\nstatic void\ninput_thread(void* arg) {\n    char buff[128];\n    char* str;\n    const cmd_t* cmd;\n\n#define IS_LINE(s) (strncmp(buff, (s), sizeof(s) - 1) == 0)\n\n    LWESP_UNUSED(arg);\n\n    /* Notify user */\n    safeprintf(\"Start by writing commands..\\r\\n\");\n\n    /* Very simple input */\n    while (1) {\n        safeprintf(\" > \");\n        memset(buff, 0x00, sizeof(buff));\n        fgets(buff, sizeof(buff), stdin);\n\n        /* Analyze input data */\n        size_t i = 0;\n        for (i = 0; i < LWESP_ARRAYSIZE(cmd_commands); ++i) {\n            if (cmd_commands[i].del) {\n                continue;\n            }\n            if (!strncmp(buff, cmd_commands[i].cmd, strlen(cmd_commands[i].cmd))) {\n                cmd = &cmd_commands[i];\n                break;\n            }\n        }\n        if (i == LWESP_ARRAYSIZE(cmd_commands)) {\n            safeprintf(\"[CMD] Unknown input command\\r\\n\");\n            continue;\n        }\n        safeprintf(\"cmd name: %s\\r\\n\", cmd->cmd);\n        str = buff + strlen(cmd->cmd);\n\n        /* Process each command */\n        if (IS_LINE(\"join\")) {\n            char *ssid, *pass;\n\n            parse_str(&str, &ssid);\n            parse_str(&str, &pass);\n\n            lwesp_sta_join(ssid, pass, NULL, NULL, NULL, 1);\n        } else if (IS_LINE(\"quit\")) {\n            lwesp_sta_quit(NULL, NULL, 1);\n        } else if (IS_LINE(\"reconn_set\")) {\n            uint32_t interval, rep_cnt = 0;\n            parse_num(&str, &interval);\n            if (interval > 0) {\n                parse_num(&str, &rep_cnt);\n            }\n            lwesp_sta_reconnect_set_config(interval, rep_cnt, NULL, NULL, 1);\n        } else if (IS_LINE(\"setip\")) {\n            lwesp_ip_t dev_ip;\n            lwesp_ip_set_ip4(&dev_ip, 192, 168, 1, 150);\n            lwesp_sta_setip(&dev_ip, NULL, NULL, NULL, NULL, 1);\n        } else if (IS_LINE(\"getip\")) {\n            lwesp_sta_getip(NULL, NULL, NULL, NULL, NULL, 1);\n        } else if (IS_LINE(\"dhcpenable\")) {\n            lwesp_dhcp_set_config(1, 0, 1, NULL, NULL, 1);\n        } else if (IS_LINE(\"dhcpdisable\")) {\n            lwesp_dhcp_set_config(1, 0, 1, NULL, NULL, 1);\n        } else if (IS_LINE(\"listap\")) {\n            lwesp_sta_list_ap(NULL, aps, LWESP_ARRAYSIZE(aps), &aps_count, NULL, NULL, 1);\n            safeprintf(\"Detected %d number of access points\\r\\n\", (int)aps_count);\n        } else if (IS_LINE(\"getapinfo\")) {\n            lwesp_sta_info_ap_t ap;\n            lwesp_sta_get_ap_info(&ap, NULL, NULL, 1);\n        } else if (IS_LINE(\"apenable\")) {\n            lwesp_set_wifi_mode(LWESP_MODE_STA_AP, NULL, NULL, 1);\n            lwesp_ap_set_config(\"ESP8266_SSID\", \"its private\", 13, LWESP_ECN_WPA2_PSK, 5, 0, NULL, NULL, 1);\n        } else if (IS_LINE(\"apdisable\")) {\n            lwesp_set_wifi_mode(LWESP_MODE_STA, NULL, NULL, 1);\n        } else if (IS_LINE(\"wifidisable\")) {\n            lwesp_set_wifi_mode(LWESP_MODE_NONE, NULL, NULL, 1);\n        } else if (IS_LINE(\"apliststa\")) {\n            lwesp_sta_t stas[10];\n            size_t stat;\n\n            lwesp_ap_list_sta(stas, LWESP_ARRAYSIZE(stas), &stat, NULL, NULL, 1);\n            safeprintf(\"Number of stations: %d\\r\\n\", (int)stat);\n        } else if (IS_LINE(\"ping\")) {\n            uint32_t pingtime;\n            char* host;\n\n            if (parse_str(&str, &host)) {\n                if (lwesp_ping(host, &pingtime, NULL, NULL, 1) == lwespOK) {\n                    safeprintf(\"Ping time: %d\\r\\n\", (int)pingtime);\n                } else {\n                    safeprintf(\"Error with ping to host \\\"%s\\\"\\r\\n\", host);\n                }\n            } else {\n                safeprintf(\"Cannot parse host\\r\\n\");\n            }\n        } else if (IS_LINE(\"hnset\")) {\n            char* host;\n\n            if (parse_str(&str, &host)) {\n                lwesp_hostname_set(host, NULL, NULL, 1);\n            } else {\n                safeprintf(\"Cannot parse host\\r\\n\");\n            }\n        } else if (IS_LINE(\"hnget\")) {\n            char hn[20];\n            lwesp_hostname_get(hn, sizeof(hn), NULL, NULL, 1);\n            safeprintf(\"Hostname: %s\\r\\n\", hn);\n        } else if (IS_LINE(\"netconn_client\")) {\n            lwesp_sys_sem_t sem;\n            lwesp_sys_sem_create(&sem, 0);\n            lwesp_sys_thread_create(NULL, \"netconn_client\", (lwesp_sys_thread_fn)netconn_client_thread, &sem, 0,\n                                    LWESP_SYS_THREAD_PRIO);\n            lwesp_sys_sem_wait(&sem, 0);\n            lwesp_sys_sem_delete(&sem);\n        } else if (IS_LINE(\"netconn_server\")) {\n            lwesp_sys_thread_create(NULL, \"netconn_server\", (lwesp_sys_thread_fn)netconn_server_thread, NULL, 0,\n                                    LWESP_SYS_THREAD_PRIO);\n        } else if (IS_LINE(\"mqttthread\")) {\n            lwesp_sys_thread_create(NULL, \"mqtt_client_api\", (lwesp_sys_thread_fn)lwesp_mqtt_client_api_thread, NULL, 0,\n                                    LWESP_SYS_THREAD_PRIO);\n        } else if (IS_LINE(\"ignoreon\")) {\n            safeprintf(\"Ignoring data...\\r\\n\");\n            lwesp_ll_win32_driver_ignore_data = 1;\n        } else if (IS_LINE(\"ignoreoff\")) {\n            safeprintf(\"Not ignoring data...\\r\\n\");\n            lwesp_ll_win32_driver_ignore_data = 0;\n        } else if (IS_LINE(\"ciupdate\")) {\n            lwesp_update_sw(NULL, NULL, 1);\n        } else {\n            safeprintf(\"Unknown input!\\r\\n\");\n        }\n    }\n}\n\n/**\n * \\brief           Global ESP event function callback\n * \\param[in]       evt: Event information\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nlwesp_evt(lwesp_evt_t* evt) {\n    switch (evt->type) {\n        case LWESP_EVT_INIT_FINISH: {\n            /* Device is not present on init */\n            //lwesp_device_set_present(0, NULL, NULL, 0);\n            break;\n        }\n        case LWESP_EVT_RESET: {\n            if (lwesp_evt_reset_get_result(evt) == lwespOK) {\n                safeprintf(\"Reset sequence successful!\\r\\n\");\n            } else {\n                safeprintf(\"Reset sequence error!\\r\\n\");\n            }\n            break;\n        }\n        case LWESP_EVT_RESTORE: {\n            if (lwesp_evt_restore_get_result(evt) == lwespOK) {\n                safeprintf(\"Restore sequence successful!\\r\\n\");\n            } else {\n                safeprintf(\"Restore sequence error!\\r\\n\");\n            }\n            break;\n        }\n        case LWESP_EVT_AT_VERSION_NOT_SUPPORTED: {\n            lwesp_sw_version_t v_min, v_curr;\n\n            lwesp_get_min_at_fw_version(&v_min);\n            lwesp_get_current_at_fw_version(&v_curr);\n\n            safeprintf(\"Current ESP[8266/32[-C3]] AT version is not supported by the library\\r\\n\");\n            safeprintf(\"Minimum required AT version is: %08X\\r\\n\", (unsigned)v_min.version);\n            safeprintf(\"Current AT version is: %08X\\r\\n\", (unsigned)v_curr.version);\n            break;\n        }\n        case LWESP_EVT_WIFI_GOT_IP: {\n            safeprintf(\"Wifi got an IP address.\\r\\n\");\n            if (lwesp_sta_has_ipv6_local()) {\n                safeprintf(\"Wifi got IPv6 local IP address.\\r\\n\");\n            }\n            if (lwesp_sta_has_ipv6_global()) {\n                safeprintf(\"Wifi got IPv6 global IP address.\\r\\n\");\n            }\n            break;\n        }\n        case LWESP_EVT_WIFI_CONNECTED: {\n            safeprintf(\"Wifi just connected. Read access point information\\r\\n\");\n            lwesp_sta_get_ap_info(&connected_ap_info, NULL, NULL, 0);\n            break;\n        }\n        case LWESP_EVT_WIFI_DISCONNECTED: {\n            safeprintf(\"Wifi just disconnected\\r\\n\");\n            break;\n        }\n        case LWESP_EVT_STA_INFO_AP: {\n            safeprintf(\"SSID: %s, ch: %d, rssi: %d\\r\\n\", lwesp_evt_sta_info_ap_get_ssid(evt),\n                       (int)lwesp_evt_sta_info_ap_get_channel(evt), (int)lwesp_evt_sta_info_ap_get_rssi(evt));\n            break;\n        }\n        case LWESP_EVT_WIFI_IP_ACQUIRED: {\n            lwesp_ip_t ip;\n            uint8_t is_dhcp;\n\n            safeprintf(\"WIFI IP ACQUIRED!\\r\\n\");\n            if (lwesp_sta_copy_ip(&ip, NULL, NULL, &is_dhcp) == lwespOK) {\n                utils_print_ip(\"IP: \", &ip, \"\\r\\n\");\n            } else {\n                safeprintf(\"Acquired IP is not valid\\r\\n\");\n            }\n            break;\n        }\n#if LWESP_CFG_MODE_ACCESS_POINT\n        case LWESP_EVT_AP_CONNECTED_STA: {\n            lwesp_mac_t* mac = lwesp_evt_ap_connected_sta_get_mac(evt);\n            utils_print_mac(\"New station connected to AP with MAC: \", mac, \"\\r\\n\");\n            break;\n        }\n        case LWESP_EVT_AP_DISCONNECTED_STA: {\n            lwesp_mac_t* mac = lwesp_evt_ap_disconnected_sta_get_mac(evt);\n            utils_print_mac(\"New station disconnected from AP with MAC: \", mac, \"\\r\\n\");\n            break;\n        }\n        case LWESP_EVT_AP_IP_STA: {\n            lwesp_mac_t* mac = lwesp_evt_ap_ip_sta_get_mac(evt);\n            lwesp_ip_t* ip = lwesp_evt_ap_ip_sta_get_ip(evt);\n            utils_print_ip(\"Station got IP address (from AP): \", ip, \"\");\n            utils_print_mac(\" and MAC: \", mac, \"\\r\\n\");\n            break;\n        }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n        default: break;\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Parse string and move pointer after parse\n * \\param[in,out]   str: Pointer to pointer to input string\n * \\param[out]      out: Output variable to set beg of pointer\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nparse_str(char** str, char** out) {\n    char* s = *str;\n    uint8_t is_quote = 0;\n\n    *out = NULL;\n    for (; s != NULL && *s != '\\0' && *s == ' '; ++s) {}\n    if (s != NULL && *s >= ' ') {\n        if (*s == '\"') {\n            is_quote = 1;\n            ++s;\n        } else if (*s == '\\0') {\n            return 0;\n        }\n        *out = s; /* Set where we point */\n        for (; s != NULL && *s >= ' ' && *s != (is_quote ? '\"' : ' '); ++s) {}\n        *s = '\\0';\n        *str = s + 1; /* Set new value for str */\n        return 1;\n    } else {\n        *out = NULL;\n        return 0;\n    }\n}\n\n/**\n * \\brief           Parse number in dec, oct, hex or bin format\n * \\param[in,out]   str: Pointer to pointer to input string\n * \\param[out]      out: Output variable to write value\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nparse_num_u64(char** str, uint64_t* out) {\n    uint64_t r, num = 0;\n    char* s = *str;\n    unsigned char c;\n\n    *out = 0;\n    for (; s != NULL && *s != '\\0' && *s == ' '; ++s) {}\n    if (s != NULL && *s >= '0' && *s <= '9') {\n        /* Check for hex/bin/octal */\n        if (*s == '0') {\n            ++s;\n            if (*s == 'x' || *s == 'X') {\n                r = 16;\n                ++s;\n            } else if (*s == 'b' || *s == 'B') {\n                r = 2;\n                ++s;\n            } else if (*s <= '7') {\n                r = 8;\n            } else if (*s <= ' ') {\n                return 1; /* Single zero */\n            } else {\n                return 0; /* Wrong format */\n            }\n        } else {\n            r = 10;\n        }\n\n        num = 0;\n        for (c = *s; c > ' '; ++s, c = *s) {\n            if (c > 'a') {\n                c -= 0x20;\n            }\n            c -= '0';\n            if (c > 17) {\n                c -= 7;\n                if (c <= 9) {\n                    return 0;\n                }\n            }\n            if (c >= r) {\n                return 0;\n            }\n            num = num * r + c;\n        }\n        *out = num;\n        *str = s;\n        return 1;\n    }\n    return 0;\n}\n\n/**\n * \\brief           Parse number in dec, oct, hex or bin format\n * \\param[in,out]   str: Pointer to pointer to input string\n * \\param[out]      out: Output variable to write value\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nparse_num(char** str, uint32_t* out) {\n    uint64_t num;\n    uint8_t s;\n\n    s = parse_num_u64(str, &num);\n    *out = (uint32_t)num;\n\n    return s;\n}\n"
  },
  {
    "path": "docs/Makefile",
    "content": "# Minimal makefile for Sphinx documentation\n#\n\n# You can set these variables from the command line, and also\n# from the environment for the first two.\nSPHINXOPTS    ?=\nSPHINXBUILD   ?= sphinx-build\nSOURCEDIR     = .\nBUILDDIR      = _build\n\n# Put it first so that \"make\" without argument is like \"make help\".\nhelp:\n\t@$(SPHINXBUILD) -M help \"$(SOURCEDIR)\" \"$(BUILDDIR)\" $(SPHINXOPTS) $(O)\n\n.PHONY: help Makefile\n\n# Catch-all target: route all unknown targets to Sphinx using the new\n# \"make mode\" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).\n%: Makefile\n\t@$(SPHINXBUILD) -M $@ \"$(SOURCEDIR)\" \"$(BUILDDIR)\" $(SPHINXOPTS) $(O)\n"
  },
  {
    "path": "docs/api-reference/apps/cayenne_api.rst",
    "content": ".. _api_app_cayenne_api:\n\nCayenne MQTT API\n================\n\n.. doxygengroup:: LWESP_APP_CAYENNE_API"
  },
  {
    "path": "docs/api-reference/apps/http_server.rst",
    "content": ".. _api_app_http_server:\n\nHTTP Server\n===========\n\n.. doxygengroup:: LWESP_APP_HTTP_SERVER\n.. doxygengroup:: LWESP_APP_HTTP_SERVER_FS_FAT"
  },
  {
    "path": "docs/api-reference/apps/index.rst",
    "content": ".. _api_apps:\n\nApplications\n============\n\n.. toctree::\n    :maxdepth: 2\n    :glob:\n\n    *"
  },
  {
    "path": "docs/api-reference/apps/mqtt_client.rst",
    "content": ".. _api_app_mqtt_client:\n\nMQTT Client\n===========\n\nMQTT client v3.1.1 implementation, based on callback (non-netconn) connection API.\n\n.. literalinclude:: ../../../snippets/mqtt_client.c\n    :language: c\n    :linenos:\n    :caption: MQTT application example code\n\n.. doxygengroup:: LWESP_APP_MQTT_CLIENT\n.. doxygengroup:: LWESP_APP_MQTT_CLIENT_EVT"
  },
  {
    "path": "docs/api-reference/apps/mqtt_client_api.rst",
    "content": ".. _api_app_mqtt_client_api:\n\nMQTT Client API\n===============\n\n*MQTT Client API* provides sequential API built on top of :ref:`api_app_mqtt_client`.\n\n.. literalinclude:: ../../../snippets/mqtt_client_api.c\n    :language: c\n    :linenos:\n    :caption: MQTT API application example code\n\n.. doxygengroup:: LWESP_APP_MQTT_CLIENT_API"
  },
  {
    "path": "docs/api-reference/apps/netconn.rst",
    "content": ".. _api_app_netconn:\n\nNetconn API\n===========\n\n*Netconn API* is addon on top of existing connection module and allows sending and receiving data with sequential API calls, similar to *POSIX socket* API.\n\nIt can operate in client or server mode and uses operating system features, such as message queues and semaphore to link non-blocking callback API for connections with sequential API for application thread.\n\n.. note::\n    Connection API does not directly allow receiving data with sequential and linear code execution.\n    All is based on connection event system.\n    Netconn adds this functionality as it is implemented on top of regular connection API.\n\n.. warning::\n    Netconn API are designed to be called from application threads ONLY.\n    It is not allowed to call any of *netconn API* functions from within interrupt or callback event functions.\n\nNetconn client\n^^^^^^^^^^^^^^\n\n.. figure:: ../../static/images/netconn_client.svg\n    :align: center\n    :alt: Netconn API client block diagram\n\n    Netconn API client block diagram\n\nAbove block diagram shows basic architecture of netconn client application.\nThere is always one application thread (in green) which calls *netconn API* functions to interact with connection API in synchronous mode.\n\nEvery netconn connection uses dedicated structure to handle message queue for data received packet buffers.\nEach time new packet is received (red block, *data received event*), reference to it is written to message queue of netconn structure, while application thread reads new entries from the same queue to get packets.\n\n.. literalinclude:: ../../../snippets/netconn_client.c\n    :language: c\n    :linenos:\n    :caption: Netconn client example\n\nNetconn server\n^^^^^^^^^^^^^^\n\n.. figure:: ../../static/images/netconn_server_1thread.svg\n    :align: center\n    :alt: Netconn API server block diagram\n\n    Netconn API server block diagram\n\nWhen netconn is configured in server mode, it is possible to accept new clients from remote side.\nApplication creates *netconn server connection*, which can only accept *clients* and cannot send/receive any data.\nIt configures server on dedicated port (selected by application) and listens on it.\n\nWhen new client connects, *server callback function* is called with *new active connection event*.\nNewly accepted connection is then written to server structure netconn which is later read by application thread.\nAt the same time, *netconn connection* structure (blue) is created to allow standard send/receive operation on active connection.\n\n.. note::\n    Each connected client has its own *netconn connection* structure.\n    When multiple clients connect to server at the same time, multiple entries are written to *connection accept* message queue and are ready to be processed by application thread.\n\nFrom this point, program flow is the same as in case of *netconn client*.\n\nThis is basic example for netconn thread.\nIt waits for client and processes it in blocking mode.\n\n.. warning::\n    When multiple clients connect at the same time to netconn server,\n    they are processed one-by-one, sequentially. This may introduce delay in response for other clients.\n    Check netconn concurrency option to process multiple clients at the same time\n\n.. literalinclude:: ../../../snippets/netconn_server_1thread.c\n    :language: c\n    :linenos:\n    :caption: Netconn server with single processing thread\n\nNetconn server concurrency\n^^^^^^^^^^^^^^^^^^^^^^^^^^\n\n.. figure:: ../../static/images/netconn_server_concurrency.svg\n\t:align: center\n\t:alt: Netconn API server concurrency block diagram\n\n\tNetconn API server concurrency block diagram\n\nWhen compared to classic netconn server, concurrent netconn server mode allows multiple clients to be processed at the same time.\nThis can drastically improve performance and response time on clients side, especially when many clients are connected to server at the same time.\n\nEvery time *server application thread* (green block) gets new client to process, it starts a new *processing* thread instead of doing it in accept thread.\n\n* Server thread is only dedicated to accept clients and start threads\n* Multiple processing thread can run in parallel to send/receive data from multiple clients\n* No delay when multi clients are active at the same time\n* Higher memory footprint is necessary as there are multiple threads active\n\n.. literalinclude:: ../../../snippets/netconn_server.c\n    :language: c\n    :linenos:\n    :caption: Netconn server with multiple processing threads\n\nNon-blocking receive\n^^^^^^^^^^^^^^^^^^^^\n\nBy default, netconn API is written to only work in separate application thread,\ndedicated for network connection processing. Because of that, by default every function is fully blocking.\nIt will wait until result is ready to be used by application.\n\nIt is, however, possible to enable timeout feature for receiving data only.\nWhen this feature is enabled, :cpp:func:`lwesp_netconn_receive` will block for maximal timeout set with\n:cpp:func:`lwesp_netconn_set_receive_timeout` function.\n\nWhen enabled, if there is no received data for timeout amount of time, function will return with timeout status and application needs to process it accordingly.\n\n.. tip::\n    :c:macro:`LWESP_CFG_NETCONN_RECEIVE_TIMEOUT` must be set to ``1`` to use this feature.\n\n.. doxygengroup:: LWESP_NETCONN"
  },
  {
    "path": "docs/api-reference/cli/cli_input.rst",
    "content": ".. _api_cli_input:\n\nCLI Input module\n================\n\n.. doxygengroup:: CLI_INPUT\n\t"
  },
  {
    "path": "docs/api-reference/cli/cli_opt.rst",
    "content": ".. _api_cli_opt:\n\nCLI Configuration\n=================\n\n.. doxygengroup:: CLI_CONFIG\n\t:inner:"
  },
  {
    "path": "docs/api-reference/cli/index.rst",
    "content": ".. _api_cli:\n\nCommand line interface\n======================\n\n.. toctree::\n\t:maxdepth: 2\n\t:glob:\n\n\t*\n\n.. doxygengroup:: CLI"
  },
  {
    "path": "docs/api-reference/index.rst",
    "content": ".. _api_reference:\n\nAPI reference\n=============\n\nList of all the modules:\n\n.. toctree::\n\t:maxdepth: 2\n\n\tlwesp/index\n\topt\n\tport/index\n\tapps/index\n\tcli/index"
  },
  {
    "path": "docs/api-reference/lwesp/ap.rst",
    "content": ".. _api_lwesp_ap:\n\nAccess point\n============\n\n.. doxygengroup:: LWESP_AP"
  },
  {
    "path": "docs/api-reference/lwesp/ble.rst",
    "content": ".. _api_lwesp_ble:\n\nBluetooth Low Energy\n====================\n\n.. doxygengroup:: LWESP_BLE"
  },
  {
    "path": "docs/api-reference/lwesp/bt.rst",
    "content": ".. _api_lwesp_bt:\n\nBluetooth Classic\n=================\n\n.. doxygengroup:: LWESP_BT"
  },
  {
    "path": "docs/api-reference/lwesp/buff.rst",
    "content": ".. _api_lwesp_buff:\n\nRing buffer\n===========\n\n.. doxygengroup:: LWESP_BUFF"
  },
  {
    "path": "docs/api-reference/lwesp/conn.rst",
    "content": ".. _api_lwesp_conn:\n\nConnections\n===========\n\nConnections are essential feature of WiFi device and middleware.\nIt is developed with strong focus on its performance and since it may interact with huge amount of data,\nit tries to use zero-copy (when available) feature, to decrease processing time.\n\n*ESP AT Firmware* by default supports up to ``5`` connections being active at the same time and supports:\n\n* Up to ``5`` TCP connections active at the same time\n* Up to ``5`` UDP connections active at the same time\n* Up to ``1`` SSL connection active at a time\n\n.. note::\n    Client or server connections are available.\n    Same API function call are used to send/receive data or close connection.\n\nArchitecture of the connection API is using callback event functions.\nThis allows maximal optimization in terms of responsiveness on different kind of events.\n\nExample below shows *bare minimum* implementation to:\n\n* Start a new connection to remote host\n* Send *HTTP GET* request to remote host\n* Process received data in event and print number of received bytes\n\n.. literalinclude:: ../../../snippets/client.c\n    :language: c\n    :linenos:\n    :caption: Client connection minimum example\n\nSending data\n^^^^^^^^^^^^\n\nReceiving data flow is always the same. Whenever new data packet arrives, corresponding event is called to notify application layer.\nWhen it comes to sending data, application may decide between ``2`` options (*this is valid only for non-UDP connections*):\n\n* Write data to temporary transmit buffer\n* Execute *send command* for every API function call\n\nTemporary transmit buffer\n*************************\n\nBy calling :cpp:func:`lwesp_conn_write` on active connection, temporary buffer is allocated and input data are copied to it.\nThere is always up to ``1`` internal buffer active. When it is full (or if input data length is longer than maximal size),\ndata are immediately send out and are not written to buffer.\n\n*ESP AT Firmware* allows (current revision) to transmit up to ``2048`` bytes at a time with single command.\nWhen trying to send more than this, application would need to issue multiple *send commands* on *AT commands level*.\n\nWrite option is used mostly when application needs to write many different small chunks of data.\nTemporary buffer hence prevents many *send command* instructions as it is faster to send single command with big buffer,\nthan many of them with smaller chunks of bytes.\n\n.. literalinclude:: ../../examples_src/conn_write.c\n    :language: c\n    :linenos:\n    :caption: Write data to connection output buffer\n\nTransmit packet manually\n************************\n\nIn some cases it is not possible to use temporary buffers,\nmostly because of memory constraints.\nApplication can directly start *send data* instructions on *AT* level by using :cpp:func:`lwesp_conn_send` or :cpp:func:`lwesp_conn_sendto` functions.\n\n.. doxygengroup:: LWESP_CONN"
  },
  {
    "path": "docs/api-reference/lwesp/debug.rst",
    "content": ".. _api_lwesp_debug:\n\nDebug support\n=============\n\nMiddleware has extended debugging capabilities.\nThese consist of different debugging levels and types of debug messages,\nallowing to track and catch different types of warnings, severe problems or simply output messages\nprogram flow messages (trace messages).\n\nModule is highly configurable using library configuration methods.\nApplication must enable some options to decide what type of messages and for which modules it would like to output messages.\n\nWith default configuration, ``printf`` is used as output function.\nThis behavior can be changed with :c:macro:`LWESP_CFG_DBG_OUT` configuration.\n\nFor successful debugging, application must:\n\n* Enable global debugging by setting :c:macro:`LWESP_CFG_DBG` to :c:macro:`LWESP_DBG_ON`\n* Configure which types of messages to output\n* Configure debugging level, from all messages to severe only\n* Enable specific modules to debug, by setting its configuration value to :c:macro:`LWESP_DBG_ON`\n\n.. tip::\n    Check :ref:`api_lwesp_opt` for all modules with debug implementation.\n\nAn example code with config and latter usage:\n\n.. literalinclude:: ../../examples_src/debug_opts.h\n    :language: c\n    :linenos:\n    :caption: Debug configuration setup\n\n.. literalinclude:: ../../examples_src/debug.c\n    :language: c\n    :linenos:\n    :caption: Debug usage within middleware\n\n.. doxygengroup:: LWESP_DEBUG"
  },
  {
    "path": "docs/api-reference/lwesp/dhcp.rst",
    "content": ".. _api_lwesp_dhcp:\n\nDynamic Host Configuration Protocol\n===================================\n\n.. doxygengroup:: LWESP_DHCP"
  },
  {
    "path": "docs/api-reference/lwesp/dns.rst",
    "content": ".. _api_lwesp_dns:\n\nDomain Name System\n==================\n\n.. doxygengroup:: LWESP_DNS"
  },
  {
    "path": "docs/api-reference/lwesp/evt.rst",
    "content": ".. _api_lwesp_evt:\n\nEvent management\n================\n\n.. doxygengroup:: LWESP_EVT"
  },
  {
    "path": "docs/api-reference/lwesp/flash.rst",
    "content": ".. _api_flash:\n\nSystem Flash\n============\n\n.. doxygengroup:: LWESP_FLASH"
  },
  {
    "path": "docs/api-reference/lwesp/hostname.rst",
    "content": ".. _api_lwesp_hostname:\n\nHostname\n========\n\n.. doxygengroup:: LWESP_HOSTNAME"
  },
  {
    "path": "docs/api-reference/lwesp/index.rst",
    "content": ".. _api_lwesp:\n\nLwESP\n=====\n\n.. toctree::\n\t:maxdepth: 2\n\t:glob:\n\n\t*\n\n.. doxygengroup:: LWESP"
  },
  {
    "path": "docs/api-reference/lwesp/input.rst",
    "content": ".. _api_lwesp_input:\n\nInput module\n============\n\nInput module is used to input received data from *ESP* device to *LwESP* middleware part.\n``2`` processing options are possible:\n\n* Indirect processing with :cpp:func:`lwesp_input` (default mode)\n* Direct processing with :cpp:func:`lwesp_input_process`\n\n.. tip::\n    Direct or indirect processing mode is select by setting :c:macro:`LWESP_CFG_INPUT_USE_PROCESS` configuration value.\n\nIndirect processing\n^^^^^^^^^^^^^^^^^^^\n\nWith indirect processing mode, every received character from *ESP* physical device is written to\nintermediate buffer between low-level driver and *processing* thread.\n\nFunction :cpp:func:`lwesp_input` is used to write data to buffer, which is later processed\nby *processing* thread.\n\nIndirect processing mode allows embedded systems to write received data to buffer from interrupt context (outside threads).\nAs a drawback, its performance is decreased as it involves copying every receive character to intermediate buffer,\nand may also introduce RAM memory footprint increase.\n\nDirect processing\n^^^^^^^^^^^^^^^^^\n\nDirect processing is targeting more advanced host controllers, like STM32 or WIN32 implementation use.\nIt is developed with DMA support in mind, allowing low-level drivers to skip intermediate data buffer\nand process input bytes directly.\n\n.. note::\n\tWhen using this mode, function :cpp:func:`lwesp_input_process` must be used and it may\n\tonly be called from thread context. Processing of input bytes is done in low-level\n\tinput thread, started by application.\n\n.. tip::\n\tCheck :ref:`um_porting_guide` for implementation examples.\n\n.. doxygengroup:: LWESP_INPUT"
  },
  {
    "path": "docs/api-reference/lwesp/mdns.rst",
    "content": ".. _api_lwesp_:\n\nMulticast DNS\n=============\n\n.. doxygengroup:: LWESP_MDNS"
  },
  {
    "path": "docs/api-reference/lwesp/mem.rst",
    "content": ".. _api_lwesp_mem:\n\nMemory manager\n==============\n\n.. doxygengroup:: LWESP_MEM"
  },
  {
    "path": "docs/api-reference/lwesp/pbuf.rst",
    "content": ".. _api_lwesp_pbuf:\n\nPacket buffer\n=============\n\nPacket buffer (or *pbuf*) is buffer manager to handle received data from any connection.\nIt is optimized to construct big buffer of smaller chunks of fragmented data as received bytes are not always coming as single packet.\n\nPbuf block diagram\n^^^^^^^^^^^^^^^^^^\n\n.. figure:: ../../static/images/pbuf_block_diagram.svg\n    :align: center\n    :alt: Block diagram of pbuf chain\n\n    Block diagram of pbuf chain\n\nImage above shows structure of *pbuf* chain. Each *pbuf* consists of:\n\n* Pointer to next *pbuf*, or ``NULL`` when it is last in chain\n* Length of current packet length\n* Length of current packet and all next in chain\n\n  * If *pbuf* is last in chain, total length is the same as current packet length\n\n* Reference counter, indicating how many pointers point to current *pbuf*\n* Actual buffer data\n\nTop image shows ``3`` pbufs connected to single chain.\nThere are ``2`` custom pointer variables to point at different *pbuf* structures. Second *pbuf* has reference counter set to ``2``, as ``2`` variables point to it:\n\n* *next* of *pbuf 1* is the first one\n* *User variable 2* is the second one\n\n.. table:: Block structure\n\n\t+--------------+-----------+------------+---------------------+-------------------+\n\t| Block number | Next pbuf | Block size | Total size in chain | Reference counter |\n\t+==============+===========+============+=====================+===================+\n\t| Block 1      | *Block 2* | ``150``    | ``550``             | ``1``             |\n\t+--------------+-----------+------------+---------------------+-------------------+\n\t| Block 2      | *Block 3* | ``130``    | ``400``             | ``2``             |\n\t+--------------+-----------+------------+---------------------+-------------------+\n\t| Block 3      | ``NULL``  | ``270``    | ``270``             | ``1``             |\n\t+--------------+-----------+------------+---------------------+-------------------+\n\nReference counter\n^^^^^^^^^^^^^^^^^\n\nReference counter holds number of references (or variables) pointing to this block.\nIt is used to properly handle memory free operation, especially when *pbuf* is used by lib core and application layer.\n\n.. note::\n\tIf there would be no reference counter information and application would free memory while another part of library still uses its reference, application would invoke *undefined behavior* and system could crash instantly.\n\nWhen application tries to free pbuf chain as on first image, it would normally call :cpp:func:`lwesp_pbuf_free` function. That would:\n\n* Decrease reference counter by ``1``\n* If reference counter ``== 0``, it removes it from chain list and frees packet buffer memory\n* If reference counter ``!= 0`` after decrease, it stops free procedure\n* Go to next pbuf in chain and repeat steps\n\nAs per first example, result of freeing from *user variable 1* would look similar to image and table below.\nFirst block (blue) had reference counter set to ``1`` prior freeing operation.\nIt was successfully removed as *user variable 1* was the only one pointing to it,\nwhile second (green) block had reference counter set to ``2``, preventing free operation.\n\n.. figure:: ../../static/images/pbuf_block_diagram_after_free.svg\n    :align: center\n    :alt: Block diagram of pbuf chain after free from *user variable 1*\n\n    Block diagram of pbuf chain after free from *user variable 1*\n\n.. table:: Block diagram of pbuf chain after free from *user variable 1*\n\n    +--------------+-----------+------------+---------------------+-------------------+\n    | Block number | Next pbuf | Block size | Total size in chain | Reference counter |\n    +==============+===========+============+=====================+===================+\n    | Block 2      | *Block 3* | ``130``    | ``400``             | ``1``             |\n    +--------------+-----------+------------+---------------------+-------------------+\n    | Block 3      | ``NULL``  | ``270``    | ``270``             | ``1``             |\n    +--------------+-----------+------------+---------------------+-------------------+\n\n.. note::\n    *Block 1* has been successfully freed, but since *block 2* had reference counter set to ``2`` before, it was only decreased by ``1`` to a new value ``1`` and free operation stopped instead.\n    *User variable 2* is still using *pbuf* starting at *block 2* and must manually call :cpp:func:`lwesp_pbuf_free` to free it.\n\nConcatenating vs chaining\n^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThis section will explain difference between *concat* and *chain* operations.\nBoth operations link ``2`` pbufs together in a chain of pbufs,\ndifference is that *chain* operation increases *reference counter* to linked pbuf,\nwhile *concat* keeps *reference counter* at its current status.\n\n.. figure:: ../../static/images/pbuf_cat_vs_chain_1.svg\n    :align: center\n    :alt: Different pbufs, each pointed to by its own variable\n\n    Different pbufs, each pointed to by its own variable\n\nConcat operation\n****************\n\nConcat operation shall be used when ``2`` pbufs are linked together and reference to *second* is no longer used.\n\n.. figure:: ../../static/images/pbuf_cat_vs_chain_2.svg\n    :align: center\n    :alt: Structure after pbuf concat\n\n    Structure after pbuf concat\n\nAfter concating *2 pbufs* together, reference counter of second is still set to ``1``, however we can see that ``2`` pointers point to *second pbuf*.\n\n.. note::\n    After application calls :cpp:func:`lwesp_pbuf_cat`, it must not use pointer which points to *second pbuf*.\n    This would invoke *undefined behavior* if one pointer tries to free memory while second still points to it.\n\nAn example code showing proper usage of concat operation:\n\n.. literalinclude:: ../../examples_src/pbuf_cat.c\n    :language: c\n    :linenos:\n    :caption: Packet buffer concat example\n\nChain operation\n***************\n\nChain operation shall be used when ``2`` pbufs are linked together and reference to *second* is still required.\n\n.. figure:: ../../static/images/pbuf_cat_vs_chain_3.svg\n    :align: center\n    :alt: Structure after pbuf chain\n\n    Structure after pbuf chain\n\nAfter chainin *2 pbufs* together, reference counter of second is increased by ``1``, which allows application to reference second *pbuf* separatelly.\n\n.. note::\n\tAfter application calls :cpp:func:`lwesp_pbuf_chain`,\n\tit also has to manually free its reference using :cpp:func:`lwesp_pbuf_free` function.\n\tForgetting to free pbuf invokes memory leak\n\nAn example code showing proper usage of chain operation:\n\n.. literalinclude:: ../../examples_src/pbuf_chain.c\n    :language: c\n    :linenos:\n    :caption: Packet buffer chain example\n\nExtract pbuf data\n*****************\n\nEach *pbuf* holds some amount of data bytes. When multiple *pbufs* are linked together (either chained or concated), blocks of raw data are not linked to contiguous memory block.\nIt is necessary to process block by block manually.\n\nAn example code showing proper reading of any *pbuf*:\n\n.. literalinclude:: ../../examples_src/pbuf_extract.c\n    :language: c\n    :linenos:\n    :caption: Packet buffer data extraction\n\n.. doxygengroup:: LWESP_PBUF"
  },
  {
    "path": "docs/api-reference/lwesp/ping.rst",
    "content": ".. _api_lwesp_ping:\n\nPing support\n============\n\n.. doxygengroup:: LWESP_PING"
  },
  {
    "path": "docs/api-reference/lwesp/server.rst",
    "content": ".. _api_lwesp_server:\n\nServer\n======\n\n.. doxygengroup:: LWESP_SERVER"
  },
  {
    "path": "docs/api-reference/lwesp/smart.rst",
    "content": ".. _api_lwesp_smart:\n\nSmart config\n============\n\n.. doxygengroup:: LWESP_SMART"
  },
  {
    "path": "docs/api-reference/lwesp/sntp.rst",
    "content": ".. _api_lwesp_sntp:\n\nSimple Network Time Protocol\n============================\n\nESP has built-in support for *Simple Network Time Protocol (SNTP)*.\nIt is support through middleware API calls for configuring servers and reading actual date and time.\n\n.. literalinclude:: ../../../snippets/sntp.c\n    :language: c\n    :linenos:\n    :caption: Minimum SNTP example\n\n.. doxygengroup:: LWESP_SNTP\n"
  },
  {
    "path": "docs/api-reference/lwesp/sta.rst",
    "content": ".. _api_lwesp_sta:\n\nStation API\n===========\n\nStation API is used to work with *ESP* acting in station mode.\nIt allows to join other access point, scan for available access points or simply disconnect from it.\n\nAn example below is showing how all examples (coming with this library) scan for access point and then\ntry to connect to AP from list of preferred one.\n\n.. literalinclude:: ../../../snippets/station_manager.c\n    :language: c\n    :linenos:\n    :caption: Station manager used with all examples\n\n.. doxygengroup:: LWESP_STA"
  },
  {
    "path": "docs/api-reference/lwesp/timeout.rst",
    "content": ".. _api_lwesp_timeout:\n\nTimeout manager\n===============\n\nTimeout manager allows application to call specific function at desired time.\nIt is used in middleware (and can be used by application too) to poll active connections.\n\n.. note::\n    Callback function is called from *processing* thread.\n    It is not allowed to call any blocking API function from it.\n\nWhen application registers timeout, it needs to set timeout, callback function and optional user argument.\nWhen timeout elapses, ESP middleware will call timeout callback.\n\nThis feature can be considered as single-shot software timer.\n\n.. doxygengroup:: LWESP_TIMEOUT"
  },
  {
    "path": "docs/api-reference/lwesp/types.rst",
    "content": ".. _api_lwesp_types:\n\nStructures and enumerations\n===========================\n\n.. doxygengroup:: LWESP_TYPES"
  },
  {
    "path": "docs/api-reference/lwesp/unicode.rst",
    "content": ".. _api_lwesp_unicode:\n\nUnicode\n=======\n\nUnicode decoder block. It can decode sequence of *UTF-8* characters,\nbetween ``1`` and ``4`` bytes long.\n\n.. note::\n    This is simple implementation and does not support string encoding.\n\n.. doxygengroup:: LWESP_UNICODE"
  },
  {
    "path": "docs/api-reference/lwesp/utils.rst",
    "content": ".. _api_lwesp_utils:\n\nUtilities\n=========\n\nUtility functions for various cases.\nThese function are used across entire middleware and can also be used by application.\n\n.. doxygengroup:: LWESP_UTILS"
  },
  {
    "path": "docs/api-reference/lwesp/webserver.rst",
    "content": ".. _api_lwesp_webserver:\n\nWeb Server\n==========\n\nUse ESP-AT's built-in web server feature to help WiFi provisioning and/or Firmware Over-the-Air update. \n\n.. note::\n    Web Server is not enabled in ESP-AT by default. Refer to `ESP-AT User Guide <https://docs.espressif.com/projects/esp-at/en/latest/AT_Command_Set/Web_server_AT_Commands.html>`_ to build a custom image from source.\n\n.. doxygengroup:: LWESP_WEBSERVER"
  },
  {
    "path": "docs/api-reference/lwesp/wps.rst",
    "content": ".. _api_lwesp_wps:\n\nWi-Fi Protected Setup\n=====================\n\n.. doxygengroup:: LWESP_WPS"
  },
  {
    "path": "docs/api-reference/opt.rst",
    "content": ".. _api_lwesp_opt:\n\nConfiguration\n=============\n\nThis is the default configuration of the middleware.\nWhen any of the settings shall be modified, it shall be done in dedicated application config ``lwesp_opts.h`` file.\n\n.. note::\n\tCheck :ref:`getting_started` for guidelines on how to create and use configuration file.\n\n.. doxygengroup:: LWESP_OPT\n\t:inner:"
  },
  {
    "path": "docs/api-reference/port/index.rst",
    "content": ".. _api_lwesp_port:\n\nPlatform specific\n=================\n\nList of all the modules:\n\n.. toctree::\n\t:maxdepth: 2\n\t:glob:\n\n\t*"
  },
  {
    "path": "docs/api-reference/port/ll.rst",
    "content": ".. _api_lwesp_ll:\n\nLow-Level functions\n===================\n\nLow-level module consists of callback-only functions, which are called by middleware\nand must be implemented by final application.\n\n.. tip::\n\tCheck :ref:`um_porting_guide` for actual implementation\n\n.. doxygengroup:: LWESP_LL"
  },
  {
    "path": "docs/api-reference/port/sys.rst",
    "content": ".. _api_lwesp_sys:\n\nSystem functions\n================\n\nSystem functions are bridge between operating system system calls and middleware system calls.\nMiddleware is tightly coupled with operating system features hence it is important to include OS features directly.\n\nIt includes support for:\n\n* Thread management, to start/stop threads\n* Mutex management for recursive mutexes\n* Semaphore management for binary-only semaphores\n* Message queues for thread-safe data exchange between threads\n* Core system protection for mutual exclusion to access shared resources\n\n.. tip::\n\tCheck :ref:`um_porting_guide` for actual implementation guidelines.\n\n.. doxygengroup:: LWESP_SYS"
  },
  {
    "path": "docs/authors/index.rst",
    "content": ".. _authors:\n\nAuthors\n=======\n\nList of authors and contributors to the library\n\n.. literalinclude:: ../../AUTHORS"
  },
  {
    "path": "docs/changelog/index.rst",
    "content": ".. _changelof:\n\nChangelog\n=========\n\n.. literalinclude:: ../../CHANGELOG.md\n"
  },
  {
    "path": "docs/conf.py",
    "content": "# Configuration file for the Sphinx documentation builder.\n#\n# This file only contains a selection of the most common options. For a full\n# list see the documentation:\n# https://www.sphinx-doc.org/en/master/usage/configuration.html\n\n# -- Path setup --------------------------------------------------------------\n\n# If extensions (or modules to document with autodoc) are in another directory,\n# add these directories to sys.path here. If the directory is relative to the\n# documentation root, use os.path.abspath to make it absolute, like shown here.\n#\n# import os\n# import sys\n# sys.path.insert(0, os.path.abspath('.'))\nfrom sphinx.builders.html import StandaloneHTMLBuilder\nimport subprocess, os\n\n# Run doxygen first\n# read_the_docs_build = os.environ.get('READTHEDOCS', None) == 'True'\n# if read_the_docs_build:\nsubprocess.call('doxygen doxyfile.doxy', shell=True)\n# -- Project information -----------------------------------------------------\n\nproject = 'LwESP'\ncopyright = '2025, Tilen MAJERLE'\nauthor = 'Tilen MAJERLE'\n\n# Try to get branch at which this is running\n# and try to determine which version to display in sphinx\n# Version is using git tag if on master/main or \"latest-develop\" if on develop branch\nversion = ''\ngit_branch = ''\n\ndef cmd_exec_print(t):\n    print(\"cmd > \", t, \"\\n\", os.popen(t).read().strip(), \"\\n\")\n\n# Print demo data here\ncmd_exec_print('git branch')\ncmd_exec_print('git describe')\ncmd_exec_print('git describe --tags')\ncmd_exec_print('git describe --tags --abbrev=0')\ncmd_exec_print('git describe --tags --abbrev=1')\n\n# Get current branch\nres = os.popen('git branch').read().strip()\nfor line in res.split(\"\\n\"):\n    if line[0] == '*':\n        git_branch = line[1:].strip()\n\n# Decision for display version\ngit_branch = git_branch.replace('(HEAD detached at ', '').replace(')', '')\nif git_branch.find('master') >= 0 or git_branch.find('main') >= 0:\n    #version = os.popen('git describe --tags --abbrev=0').read().strip()\n    version = 'latest-stable'\nelif git_branch.find('develop-') >= 0 or git_branch.find('develop/') >= 0:\n    version = 'branch-' + git_branch\nelif git_branch == 'develop' or git_branch == 'origin/develop':\n    version = 'latest-develop'\nelse:\n    version = os.popen('git describe --tags --abbrev=0').read().strip()\n\n# For debugging purpose only\nprint(\"GIT BRANCH: \" + git_branch)\nprint(\"PROJ VERSION: \" + version)\n\n# -- General configuration ---------------------------------------------------\n\n# Add any Sphinx extension module names here, as strings. They can be\n# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom\n# ones.\nextensions = [\n    'sphinx.ext.autodoc',\n    'sphinx.ext.intersphinx',\n    'sphinx.ext.autosectionlabel',\n    'sphinx.ext.todo',\n    'sphinx.ext.coverage',\n    'sphinx.ext.mathjax',\n    'sphinx.ext.ifconfig',\n    'sphinx.ext.viewcode',\n    'sphinx_sitemap',\n\n    'breathe',\n]\n\n# Add any paths that contain templates here, relative to this directory.\ntemplates_path = ['templates']\n\n# List of patterns, relative to source directory, that match files and\n# directories to ignore when looking for source files.\n# This pattern also affects html_static_path and html_extra_path.\nexclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']\n\nhighlight_language = 'c'\n\n# -- Options for HTML output -------------------------------------------------\n\n# The theme to use for HTML and HTML Help pages.  See the documentation for\n# a list of builtin themes.\n#\nhtml_theme = 'sphinx_rtd_theme'\nhtml_theme_options = {\n    'canonical_url': '',\n    'analytics_id': '',  #  Provided by Google in your dashboard\n    'display_version': True,\n    'prev_next_buttons_location': 'bottom',\n    'style_external_links': False,\n\n    'logo_only': False,\n\n    # Toc options\n    'collapse_navigation': True,\n    'sticky_navigation': True,\n    'navigation_depth': 4,\n    'includehidden': True,\n    'titles_only': False\n}\nhtml_logo = 'static/images/logo.svg'\ngithub_url = 'https://github.com/MaJerle/esp-at-lib'\nhtml_baseurl = 'https://docs.majerle.eu/projects/esp-at-lib/'\n\n# Add any paths that contain custom static files (such as style sheets) here,\n# relative to this directory. They are copied after the builtin static files,\n# so a file named \"default.css\" will overwrite the builtin \"default.css\".\nhtml_static_path = ['static']\nhtml_css_files = [\n    'css/common.css',\n    'css/custom.css',\n    'https://cdnjs.cloudflare.com/ajax/libs/font-awesome/5.15.1/css/all.min.css',\n]\nhtml_js_files = [\n    ''\n]\n\n# Master index file\nmaster_doc = 'index'\n\n# --- Breathe configuration -----------------------------------------------------\nbreathe_projects = {\n\t\"lwesp\": \"_build/xml/\"\n}\nbreathe_default_project = \"lwesp\"\nbreathe_default_members = ('members', 'undoc-members')\nbreathe_show_enumvalue_initializer = True"
  },
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    "path": "docs/doxyfile.doxy",
    "content": "# Doxyfile 1.9.4\n\n# This file describes the settings to be used by the documentation system\n# doxygen (www.doxygen.org) for a project.\n#\n# All text after a double hash (##) is considered a comment and is placed in\n# front of the TAG it is preceding.\n#\n# All text after a single hash (#) is considered a comment and will be ignored.\n# The format is:\n# TAG = value [value, ...]\n# For lists, items can also be appended using:\n# TAG += value [value, ...]\n# Values that contain spaces should be placed between quotes (\\\" \\\").\n#\n# Note:\n#\n# Use doxygen to compare the used configuration file with the template\n# configuration file:\n# doxygen -x [configFile]\n# Use doxygen to compare the used configuration file with the template\n# configuration file without replacing the environment variables:\n# doxygen -x_noenv [configFile]\n\n#---------------------------------------------------------------------------\n# Project related configuration options\n#---------------------------------------------------------------------------\n\n# This tag specifies the encoding used for all characters in the configuration\n# file that follow. The default is UTF-8 which is also the encoding used for all\n# text before the first occurrence of this tag. Doxygen uses libiconv (or the\n# iconv built into libc) for the transcoding. See\n# https://www.gnu.org/software/libiconv/ for the list of possible encodings.\n# The default value is: UTF-8.\n\nDOXYFILE_ENCODING      = UTF-8\n\n# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by\n# double-quotes, unless you are using Doxywizard) that should identify the\n# project for which the documentation is generated. This name is used in the\n# title of most generated pages and in a few other places.\n# The default value is: My Project.\n\nPROJECT_NAME           = LwESP\n\n# The PROJECT_NUMBER tag can be used to enter a project or revision number. This\n# could be handy for archiving the generated documentation or if some version\n# control system is used.\n\nPROJECT_NUMBER         =\n\n# Using the PROJECT_BRIEF tag one can provide an optional one line description\n# for a project that appears at the top of each page and should give viewer a\n# quick idea about the purpose of the project. Keep the description short.\n\nPROJECT_BRIEF          = \"Lightweight ESP-AT parser library\"\n\n# With the PROJECT_LOGO tag one can specify a logo or an icon that is included\n# in the documentation. The maximum height of the logo should not exceed 55\n# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy\n# the logo to the output directory.\n\nPROJECT_LOGO           =\n\n# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path\n# into which the generated documentation will be written. If a relative path is\n# entered, it will be relative to the location where doxygen was started. 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If set\n# to NO, structs, classes, and unions are shown on a separate page (for HTML and\n# Man pages) or section (for LaTeX and RTF).\n# The default value is: NO.\n\nINLINE_SIMPLE_STRUCTS  = NO\n\n# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or\n# enum is documented as struct, union, or enum with the name of the typedef. So\n# typedef struct TypeS {} TypeT, will appear in the documentation as a struct\n# with name TypeT. When disabled the typedef will appear as a member of a file,\n# namespace, or class. And the struct will be named TypeS. This can typically be\n# useful for C code in case the coding convention dictates that all compound\n# types are typedef'ed and only the typedef is referenced, never the tag name.\n# The default value is: NO.\n\nTYPEDEF_HIDES_STRUCT   = YES\n\n# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This\n# cache is used to resolve symbols given their name and scope. Since this can be\n# an expensive process and often the same symbol appears multiple times in the\n# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small\n# doxygen will become slower. If the cache is too large, memory is wasted. The\n# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range\n# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536\n# symbols. At the end of a run doxygen will report the cache usage and suggest\n# the optimal cache size from a speed point of view.\n# Minimum value: 0, maximum value: 9, default value: 0.\n\nLOOKUP_CACHE_SIZE      = 0\n\n# The NUM_PROC_THREADS specifies the number of threads doxygen is allowed to use\n# during processing. When set to 0 doxygen will based this on the number of\n# cores available in the system. You can set it explicitly to a value larger\n# than 0 to get more control over the balance between CPU load and processing\n# speed. At this moment only the input processing can be done using multiple\n# threads. Since this is still an experimental feature the default is set to 1,\n# which effectively disables parallel processing. Please report any issues you\n# encounter. Generating dot graphs in parallel is controlled by the\n# DOT_NUM_THREADS setting.\n# Minimum value: 0, maximum value: 32, default value: 1.\n\nNUM_PROC_THREADS       = 1\n\n#---------------------------------------------------------------------------\n# Build related configuration options\n#---------------------------------------------------------------------------\n\n# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in\n# documentation are documented, even if no documentation was available. Private\n# class members and static file members will be hidden unless the\n# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.\n# Note: This will also disable the warnings about undocumented members that are\n# normally produced when WARNINGS is set to YES.\n# The default value is: NO.\n\nEXTRACT_ALL            = NO\n\n# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will\n# be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIVATE        = NO\n\n# If the EXTRACT_PRIV_VIRTUAL tag is set to YES, documented private virtual\n# methods of a class will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PRIV_VIRTUAL   = NO\n\n# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal\n# scope will be included in the documentation.\n# The default value is: NO.\n\nEXTRACT_PACKAGE        = NO\n\n# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be\n# included in the documentation.\n# The default value is: NO.\n\nEXTRACT_STATIC         = YES\n\n# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined\n# locally in source files will be included in the documentation. If set to NO,\n# only classes defined in header files are included. Does not have any effect\n# for Java sources.\n# The default value is: YES.\n\nEXTRACT_LOCAL_CLASSES  = YES\n\n# This flag is only useful for Objective-C code. If set to YES, local methods,\n# which are defined in the implementation section but not in the interface are\n# included in the documentation. If set to NO, only methods in the interface are\n# included.\n# The default value is: NO.\n\nEXTRACT_LOCAL_METHODS  = NO\n\n# If this flag is set to YES, the members of anonymous namespaces will be\n# extracted and appear in the documentation as a namespace called\n# 'anonymous_namespace{file}', where file will be replaced with the base name of\n# the file that contains the anonymous namespace. By default anonymous namespace\n# are hidden.\n# The default value is: NO.\n\nEXTRACT_ANON_NSPACES   = NO\n\n# If this flag is set to YES, the name of an unnamed parameter in a declaration\n# will be determined by the corresponding definition. By default unnamed\n# parameters remain unnamed in the output.\n# The default value is: YES.\n\nRESOLVE_UNNAMED_PARAMS = YES\n\n# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all\n# undocumented members inside documented classes or files. If set to NO these\n# members will be included in the various overviews, but no documentation\n# section is generated. This option has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_MEMBERS     = NO\n\n# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all\n# undocumented classes that are normally visible in the class hierarchy. If set\n# to NO, these classes will be included in the various overviews. This option\n# has no effect if EXTRACT_ALL is enabled.\n# The default value is: NO.\n\nHIDE_UNDOC_CLASSES     = NO\n\n# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend\n# declarations. If set to NO, these declarations will be included in the\n# documentation.\n# The default value is: NO.\n\nHIDE_FRIEND_COMPOUNDS  = NO\n\n# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any\n# documentation blocks found inside the body of a function. If set to NO, these\n# blocks will be appended to the function's detailed documentation block.\n# The default value is: NO.\n\nHIDE_IN_BODY_DOCS      = NO\n\n# The INTERNAL_DOCS tag determines if documentation that is typed after a\n# \\internal command is included. If the tag is set to NO then the documentation\n# will be excluded. Set it to YES to include the internal documentation.\n# The default value is: NO.\n\nINTERNAL_DOCS          = NO\n\n# With the correct setting of option CASE_SENSE_NAMES doxygen will better be\n# able to match the capabilities of the underlying filesystem. In case the\n# filesystem is case sensitive (i.e. it supports files in the same directory\n# whose names only differ in casing), the option must be set to YES to properly\n# deal with such files in case they appear in the input. For filesystems that\n# are not case sensitive the option should be set to NO to properly deal with\n# output files written for symbols that only differ in casing, such as for two\n# classes, one named CLASS and the other named Class, and to also support\n# references to files without having to specify the exact matching casing. On\n# Windows (including Cygwin) and MacOS, users should typically set this option\n# to NO, whereas on Linux or other Unix flavors it should typically be set to\n# YES.\n# The default value is: system dependent.\n\nCASE_SENSE_NAMES       = NO\n\n# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with\n# their full class and namespace scopes in the documentation. If set to YES, the\n# scope will be hidden.\n# The default value is: NO.\n\nHIDE_SCOPE_NAMES       = YES\n\n# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will\n# append additional text to a page's title, such as Class Reference. If set to\n# YES the compound reference will be hidden.\n# The default value is: NO.\n\nHIDE_COMPOUND_REFERENCE= NO\n\n# If the SHOW_HEADERFILE tag is set to YES then the documentation for a class\n# will show which file needs to be included to use the class.\n# The default value is: YES.\n\nSHOW_HEADERFILE        = YES\n\n# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of\n# the files that are included by a file in the documentation of that file.\n# The default value is: YES.\n\nSHOW_INCLUDE_FILES     = YES\n\n# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each\n# grouped member an include statement to the documentation, telling the reader\n# which file to include in order to use the member.\n# The default value is: NO.\n\nSHOW_GROUPED_MEMB_INC  = NO\n\n# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include\n# files with double quotes in the documentation rather than with sharp brackets.\n# The default value is: NO.\n\nFORCE_LOCAL_INCLUDES   = NO\n\n# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the\n# documentation for inline members.\n# The default value is: YES.\n\nINLINE_INFO            = YES\n\n# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the\n# (detailed) documentation of file and class members alphabetically by member\n# name. If set to NO, the members will appear in declaration order.\n# The default value is: YES.\n\nSORT_MEMBER_DOCS       = YES\n\n# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief\n# descriptions of file, namespace and class members alphabetically by member\n# name. If set to NO, the members will appear in declaration order. Note that\n# this will also influence the order of the classes in the class list.\n# The default value is: NO.\n\nSORT_BRIEF_DOCS        = NO\n\n# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the\n# (brief and detailed) documentation of class members so that constructors and\n# destructors are listed first. If set to NO the constructors will appear in the\n# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.\n# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief\n# member documentation.\n# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting\n# detailed member documentation.\n# The default value is: NO.\n\nSORT_MEMBERS_CTORS_1ST = NO\n\n# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy\n# of group names into alphabetical order. If set to NO the group names will\n# appear in their defined order.\n# The default value is: NO.\n\nSORT_GROUP_NAMES       = NO\n\n# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by\n# fully-qualified names, including namespaces. If set to NO, the class list will\n# be sorted only by class name, not including the namespace part.\n# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.\n# Note: This option applies only to the class list, not to the alphabetical\n# list.\n# The default value is: NO.\n\nSORT_BY_SCOPE_NAME     = NO\n\n# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper\n# type resolution of all parameters of a function it will reject a match between\n# the prototype and the implementation of a member function even if there is\n# only one candidate or it is obvious which candidate to choose by doing a\n# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still\n# accept a match between prototype and implementation in such cases.\n# The default value is: NO.\n\nSTRICT_PROTO_MATCHING  = NO\n\n# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo\n# list. This list is created by putting \\todo commands in the documentation.\n# The default value is: YES.\n\nGENERATE_TODOLIST      = YES\n\n# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test\n# list. This list is created by putting \\test commands in the documentation.\n# The default value is: YES.\n\nGENERATE_TESTLIST      = YES\n\n# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug\n# list. This list is created by putting \\bug commands in the documentation.\n# The default value is: YES.\n\nGENERATE_BUGLIST       = YES\n\n# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO)\n# the deprecated list. This list is created by putting \\deprecated commands in\n# the documentation.\n# The default value is: YES.\n\nGENERATE_DEPRECATEDLIST= YES\n\n# The ENABLED_SECTIONS tag can be used to enable conditional documentation\n# sections, marked by \\if <section_label> ... \\endif and \\cond <section_label>\n# ... \\endcond blocks.\n\nENABLED_SECTIONS       =\n\n# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the\n# initial value of a variable or macro / define can have for it to appear in the\n# documentation. If the initializer consists of more lines than specified here\n# it will be hidden. Use a value of 0 to hide initializers completely. The\n# appearance of the value of individual variables and macros / defines can be\n# controlled using \\showinitializer or \\hideinitializer command in the\n# documentation regardless of this setting.\n# Minimum value: 0, maximum value: 10000, default value: 30.\n\nMAX_INITIALIZER_LINES  = 30\n\n# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at\n# the bottom of the documentation of classes and structs. If set to YES, the\n# list will mention the files that were used to generate the documentation.\n# The default value is: YES.\n\nSHOW_USED_FILES        = NO\n\n# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This\n# will remove the Files entry from the Quick Index and from the Folder Tree View\n# (if specified).\n# The default value is: YES.\n\nSHOW_FILES             = NO\n\n# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces\n# page. This will remove the Namespaces entry from the Quick Index and from the\n# Folder Tree View (if specified).\n# The default value is: YES.\n\nSHOW_NAMESPACES        = YES\n\n# The FILE_VERSION_FILTER tag can be used to specify a program or script that\n# doxygen should invoke to get the current version for each file (typically from\n# the version control system). Doxygen will invoke the program by executing (via\n# popen()) the command command input-file, where command is the value of the\n# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided\n# by doxygen. Whatever the program writes to standard output is used as the file\n# version. For an example see the documentation.\n\nFILE_VERSION_FILTER    =\n\n# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed\n# by doxygen. The layout file controls the global structure of the generated\n# output files in an output format independent way. To create the layout file\n# that represents doxygen's defaults, run doxygen with the -l option. You can\n# optionally specify a file name after the option, if omitted DoxygenLayout.xml\n# will be used as the name of the layout file. See also section \"Changing the\n# layout of pages\" for information.\n#\n# Note that if you run doxygen from a directory containing a file called\n# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE\n# tag is left empty.\n\nLAYOUT_FILE            =\n\n# The CITE_BIB_FILES tag can be used to specify one or more bib files containing\n# the reference definitions. This must be a list of .bib files. The .bib\n# extension is automatically appended if omitted. This requires the bibtex tool\n# to be installed. See also https://en.wikipedia.org/wiki/BibTeX for more info.\n# For LaTeX the style of the bibliography can be controlled using\n# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the\n# search path. See also \\cite for info how to create references.\n\nCITE_BIB_FILES         =\n\n#---------------------------------------------------------------------------\n# Configuration options related to warning and progress messages\n#---------------------------------------------------------------------------\n\n# The QUIET tag can be used to turn on/off the messages that are generated to\n# standard output by doxygen. If QUIET is set to YES this implies that the\n# messages are off.\n# The default value is: NO.\n\nQUIET                  = NO\n\n# The WARNINGS tag can be used to turn on/off the warning messages that are\n# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES\n# this implies that the warnings are on.\n#\n# Tip: Turn warnings on while writing the documentation.\n# The default value is: YES.\n\nWARNINGS               = YES\n\n# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate\n# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag\n# will automatically be disabled.\n# The default value is: YES.\n\nWARN_IF_UNDOCUMENTED   = YES\n\n# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for\n# potential errors in the documentation, such as documenting some parameters in\n# a documented function twice, or documenting parameters that don't exist or\n# using markup commands wrongly.\n# The default value is: YES.\n\nWARN_IF_DOC_ERROR      = YES\n\n# If WARN_IF_INCOMPLETE_DOC is set to YES, doxygen will warn about incomplete\n# function parameter documentation. If set to NO, doxygen will accept that some\n# parameters have no documentation without warning.\n# The default value is: YES.\n\nWARN_IF_INCOMPLETE_DOC = YES\n\n# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that\n# are documented, but have no documentation for their parameters or return\n# value. If set to NO, doxygen will only warn about wrong parameter\n# documentation, but not about the absence of documentation. If EXTRACT_ALL is\n# set to YES then this flag will automatically be disabled. See also\n# WARN_IF_INCOMPLETE_DOC\n# The default value is: NO.\n\nWARN_NO_PARAMDOC       = YES\n\n# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when\n# a warning is encountered. If the WARN_AS_ERROR tag is set to FAIL_ON_WARNINGS\n# then doxygen will continue running as if WARN_AS_ERROR tag is set to NO, but\n# at the end of the doxygen process doxygen will return with a non-zero status.\n# Possible values are: NO, YES and FAIL_ON_WARNINGS.\n# The default value is: NO.\n\nWARN_AS_ERROR          = NO\n\n# The WARN_FORMAT tag determines the format of the warning messages that doxygen\n# can produce. The string should contain the $file, $line, and $text tags, which\n# will be replaced by the file and line number from which the warning originated\n# and the warning text. Optionally the format may contain $version, which will\n# be replaced by the version of the file (if it could be obtained via\n# FILE_VERSION_FILTER)\n# See also: WARN_LINE_FORMAT\n# The default value is: $file:$line: $text.\n\nWARN_FORMAT            = \"$file:$line: $text\"\n\n# In the $text part of the WARN_FORMAT command it is possible that a reference\n# to a more specific place is given. To make it easier to jump to this place\n# (outside of doxygen) the user can define a custom \"cut\" / \"paste\" string.\n# Example:\n# WARN_LINE_FORMAT = \"'vi $file +$line'\"\n# See also: WARN_FORMAT\n# The default value is: at line $line of file $file.\n\nWARN_LINE_FORMAT       = \"at line $line of file $file\"\n\n# The WARN_LOGFILE tag can be used to specify a file to which warning and error\n# messages should be written. If left blank the output is written to standard\n# error (stderr). In case the file specified cannot be opened for writing the\n# warning and error messages are written to standard error. When as file - is\n# specified the warning and error messages are written to standard output\n# (stdout).\n\nWARN_LOGFILE           =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the input files\n#---------------------------------------------------------------------------\n\n# The INPUT tag is used to specify the files and/or directories that contain\n# documented source files. You may enter file names like myfile.cpp or\n# directories like /usr/src/myproject. Separate the files or directories with\n# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING\n# Note: If this tag is empty the current directory is searched.\n\nINPUT                  = ../lwesp/\n\n# This tag can be used to specify the character encoding of the source files\n# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses\n# libiconv (or the iconv built into libc) for the transcoding. See the libiconv\n# documentation (see:\n# https://www.gnu.org/software/libiconv/) for the list of possible encodings.\n# The default value is: UTF-8.\n\nINPUT_ENCODING         = UTF-8\n\n# If the value of the INPUT tag contains directories, you can use the\n# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and\n# *.h) to filter out the source-files in the directories.\n#\n# Note that for custom extensions or not directly supported extensions you also\n# need to set EXTENSION_MAPPING for the extension otherwise the files are not\n# read by doxygen.\n#\n# Note the list of default checked file patterns might differ from the list of\n# default file extension mappings.\n#\n# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp,\n# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h,\n# *.hh, *.hxx, *.hpp, *.h++, *.l, *.cs, *.d, *.php, *.php4, *.php5, *.phtml,\n# *.inc, *.m, *.markdown, *.md, *.mm, *.dox (to be provided as doxygen C\n# comment), *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, *.f18, *.f, *.for, *.vhd,\n# *.vhdl, *.ucf, *.qsf and *.ice.\n\nFILE_PATTERNS          = *.c \\\n                         *.cc \\\n                         *.cxx \\\n                         *.cpp \\\n                         *.c++ \\\n                         *.java \\\n                         *.ii \\\n                         *.ixx \\\n                         *.ipp \\\n                         *.i++ \\\n                         *.inl \\\n                         *.idl \\\n                         *.ddl \\\n                         *.odl \\\n                         *.h \\\n                         *.hh \\\n                         *.hxx \\\n                         *.hpp \\\n                         *.h++ \\\n                         *.cs \\\n                         *.d \\\n                         *.php \\\n                         *.php4 \\\n                         *.php5 \\\n                         *.phtml \\\n                         *.inc \\\n                         *.m \\\n                         *.markdown \\\n                         *.md \\\n                         *.mm \\\n                         *.dox \\\n                         *.py \\\n                         *.f90 \\\n                         *.f \\\n                         *.for \\\n                         *.tcl \\\n                         *.vhd \\\n                         *.vhdl \\\n                         *.ucf \\\n                         *.qsf \\\n                         *.as \\\n                         *.js\n\n# The RECURSIVE tag can be used to specify whether or not subdirectories should\n# be searched for input files as well.\n# The default value is: NO.\n\nRECURSIVE              = YES\n\n# The EXCLUDE tag can be used to specify files and/or directories that should be\n# excluded from the INPUT source files. This way you can easily exclude a\n# subdirectory from a directory tree whose root is specified with the INPUT tag.\n#\n# Note that relative paths are relative to the directory from which doxygen is\n# run.\n\nEXCLUDE                =\n\n# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or\n# directories that are symbolic links (a Unix file system feature) are excluded\n# from the input.\n# The default value is: NO.\n\nEXCLUDE_SYMLINKS       = NO\n\n# If the value of the INPUT tag contains directories, you can use the\n# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude\n# certain files from those directories.\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories for example use the pattern */test/*\n\nEXCLUDE_PATTERNS       =\n\n# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names\n# (namespaces, classes, functions, etc.) that should be excluded from the\n# output. The symbol name can be a fully qualified name, a word, or if the\n# wildcard * is used, a substring. Examples: ANamespace, AClass,\n# ANamespace::AClass, ANamespace::*Test\n#\n# Note that the wildcards are matched against the file with absolute path, so to\n# exclude all test directories use the pattern */test/*\n\nEXCLUDE_SYMBOLS        =\n\n# The EXAMPLE_PATH tag can be used to specify one or more files or directories\n# that contain example code fragments that are included (see the \\include\n# command).\n\nEXAMPLE_PATH           =\n\n# If the value of the EXAMPLE_PATH tag contains directories, you can use the\n# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and\n# *.h) to filter out the source-files in the directories. If left blank all\n# files are included.\n\nEXAMPLE_PATTERNS       = *\n\n# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be\n# searched for input files to be used with the \\include or \\dontinclude commands\n# irrespective of the value of the RECURSIVE tag.\n# The default value is: NO.\n\nEXAMPLE_RECURSIVE      = NO\n\n# The IMAGE_PATH tag can be used to specify one or more files or directories\n# that contain images that are to be included in the documentation (see the\n# \\image command).\n\nIMAGE_PATH             =\n\n# The INPUT_FILTER tag can be used to specify a program that doxygen should\n# invoke to filter for each input file. Doxygen will invoke the filter program\n# by executing (via popen()) the command:\n#\n# <filter> <input-file>\n#\n# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the\n# name of an input file. Doxygen will then use the output that the filter\n# program writes to standard output. If FILTER_PATTERNS is specified, this tag\n# will be ignored.\n#\n# Note that the filter must not add or remove lines; it is applied before the\n# code is scanned, but not when the output code is generated. If lines are added\n# or removed, the anchors will not be placed correctly.\n#\n# Note that for custom extensions or not directly supported extensions you also\n# need to set EXTENSION_MAPPING for the extension otherwise the files are not\n# properly processed by doxygen.\n\nINPUT_FILTER           =\n\n# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern\n# basis. Doxygen will compare the file name with each pattern and apply the\n# filter if there is a match. The filters are a list of the form: pattern=filter\n# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how\n# filters are used. If the FILTER_PATTERNS tag is empty or if none of the\n# patterns match the file name, INPUT_FILTER is applied.\n#\n# Note that for custom extensions or not directly supported extensions you also\n# need to set EXTENSION_MAPPING for the extension otherwise the files are not\n# properly processed by doxygen.\n\nFILTER_PATTERNS        =\n\n# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using\n# INPUT_FILTER) will also be used to filter the input files that are used for\n# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).\n# The default value is: NO.\n\nFILTER_SOURCE_FILES    = NO\n\n# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file\n# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and\n# it is also possible to disable source filtering for a specific pattern using\n# *.ext= (so without naming a filter).\n# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.\n\nFILTER_SOURCE_PATTERNS =\n\n# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that\n# is part of the input, its contents will be placed on the main page\n# (index.html). This can be useful if you have a project on for instance GitHub\n# and want to reuse the introduction page also for the doxygen output.\n\nUSE_MDFILE_AS_MAINPAGE =\n\n#---------------------------------------------------------------------------\n# Configuration options related to source browsing\n#---------------------------------------------------------------------------\n\n# If the SOURCE_BROWSER tag is set to YES then a list of source files will be\n# generated. Documented entities will be cross-referenced with these sources.\n#\n# Note: To get rid of all source code in the generated output, make sure that\n# also VERBATIM_HEADERS is set to NO.\n# The default value is: NO.\n\nSOURCE_BROWSER         = NO\n\n# Setting the INLINE_SOURCES tag to YES will include the body of functions,\n# classes and enums directly into the documentation.\n# The default value is: NO.\n\nINLINE_SOURCES         = NO\n\n# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any\n# special comment blocks from generated source code fragments. Normal C, C++ and\n# Fortran comments will always remain visible.\n# The default value is: YES.\n\nSTRIP_CODE_COMMENTS    = YES\n\n# If the REFERENCED_BY_RELATION tag is set to YES then for each documented\n# entity all documented functions referencing it will be listed.\n# The default value is: NO.\n\nREFERENCED_BY_RELATION = NO\n\n# If the REFERENCES_RELATION tag is set to YES then for each documented function\n# all documented entities called/used by that function will be listed.\n# The default value is: NO.\n\nREFERENCES_RELATION    = NO\n\n# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set\n# to YES then the hyperlinks from functions in REFERENCES_RELATION and\n# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will\n# link to the documentation.\n# The default value is: YES.\n\nREFERENCES_LINK_SOURCE = YES\n\n# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the\n# source code will show a tooltip with additional information such as prototype,\n# brief description and links to the definition and documentation. Since this\n# will make the HTML file larger and loading of large files a bit slower, you\n# can opt to disable this feature.\n# The default value is: YES.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nSOURCE_TOOLTIPS        = YES\n\n# If the USE_HTAGS tag is set to YES then the references to source code will\n# point to the HTML generated by the htags(1) tool instead of doxygen built-in\n# source browser. The htags tool is part of GNU's global source tagging system\n# (see https://www.gnu.org/software/global/global.html). You will need version\n# 4.8.6 or higher.\n#\n# To use it do the following:\n# - Install the latest version of global\n# - Enable SOURCE_BROWSER and USE_HTAGS in the configuration file\n# - Make sure the INPUT points to the root of the source tree\n# - Run doxygen as normal\n#\n# Doxygen will invoke htags (and that will in turn invoke gtags), so these\n# tools must be available from the command line (i.e. in the search path).\n#\n# The result: instead of the source browser generated by doxygen, the links to\n# source code will now point to the output of htags.\n# The default value is: NO.\n# This tag requires that the tag SOURCE_BROWSER is set to YES.\n\nUSE_HTAGS              = NO\n\n# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a\n# verbatim copy of the header file for each class for which an include is\n# specified. Set to NO to disable this.\n# See also: Section \\class.\n# The default value is: YES.\n\nVERBATIM_HEADERS       = YES\n\n# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the\n# clang parser (see:\n# http://clang.llvm.org/) for more accurate parsing at the cost of reduced\n# performance. This can be particularly helpful with template rich C++ code for\n# which doxygen's built-in parser lacks the necessary type information.\n# Note: The availability of this option depends on whether or not doxygen was\n# generated with the -Duse_libclang=ON option for CMake.\n# The default value is: NO.\n\nCLANG_ASSISTED_PARSING = NO\n\n# If the CLANG_ASSISTED_PARSING tag is set to YES and the CLANG_ADD_INC_PATHS\n# tag is set to YES then doxygen will add the directory of each input to the\n# include path.\n# The default value is: YES.\n# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.\n\nCLANG_ADD_INC_PATHS    = YES\n\n# If clang assisted parsing is enabled you can provide the compiler with command\n# line options that you would normally use when invoking the compiler. Note that\n# the include paths will already be set by doxygen for the files and directories\n# specified with INPUT and INCLUDE_PATH.\n# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.\n\nCLANG_OPTIONS          =\n\n# If clang assisted parsing is enabled you can provide the clang parser with the\n# path to the directory containing a file called compile_commands.json. This\n# file is the compilation database (see:\n# http://clang.llvm.org/docs/HowToSetupToolingForLLVM.html) containing the\n# options used when the source files were built. This is equivalent to\n# specifying the -p option to a clang tool, such as clang-check. These options\n# will then be passed to the parser. Any options specified with CLANG_OPTIONS\n# will be added as well.\n# Note: The availability of this option depends on whether or not doxygen was\n# generated with the -Duse_libclang=ON option for CMake.\n\nCLANG_DATABASE_PATH    =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the alphabetical class index\n#---------------------------------------------------------------------------\n\n# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all\n# compounds will be generated. Enable this if the project contains a lot of\n# classes, structs, unions or interfaces.\n# The default value is: YES.\n\nALPHABETICAL_INDEX     = YES\n\n# In case all classes in a project start with a common prefix, all classes will\n# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag\n# can be used to specify a prefix (or a list of prefixes) that should be ignored\n# while generating the index headers.\n# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.\n\nIGNORE_PREFIX          =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the HTML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output\n# The default value is: YES.\n\nGENERATE_HTML          = YES\n\n# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_OUTPUT            = html\n\n# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each\n# generated HTML page (for example: .htm, .php, .asp).\n# The default value is: .html.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FILE_EXTENSION    = .html\n\n# The HTML_HEADER tag can be used to specify a user-defined HTML header file for\n# each generated HTML page. If the tag is left blank doxygen will generate a\n# standard header.\n#\n# To get valid HTML the header file that includes any scripts and style sheets\n# that doxygen needs, which is dependent on the configuration options used (e.g.\n# the setting GENERATE_TREEVIEW). It is highly recommended to start with a\n# default header using\n# doxygen -w html new_header.html new_footer.html new_stylesheet.css\n# YourConfigFile\n# and then modify the file new_header.html. See also section \"Doxygen usage\"\n# for information on how to generate the default header that doxygen normally\n# uses.\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. For a description\n# of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_HEADER            =\n\n# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each\n# generated HTML page. If the tag is left blank doxygen will generate a standard\n# footer. See HTML_HEADER for more information on how to generate a default\n# footer and what special commands can be used inside the footer. See also\n# section \"Doxygen usage\" for information on how to generate the default footer\n# that doxygen normally uses.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FOOTER            =\n\n# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style\n# sheet that is used by each HTML page. It can be used to fine-tune the look of\n# the HTML output. If left blank doxygen will generate a default style sheet.\n# See also section \"Doxygen usage\" for information on how to generate the style\n# sheet that doxygen normally uses.\n# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as\n# it is more robust and this tag (HTML_STYLESHEET) will in the future become\n# obsolete.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_STYLESHEET        =\n\n# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined\n# cascading style sheets that are included after the standard style sheets\n# created by doxygen. Using this option one can overrule certain style aspects.\n# This is preferred over using HTML_STYLESHEET since it does not replace the\n# standard style sheet and is therefore more robust against future updates.\n# Doxygen will copy the style sheet files to the output directory.\n# Note: The order of the extra style sheet files is of importance (e.g. the last\n# style sheet in the list overrules the setting of the previous ones in the\n# list). For an example see the documentation.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_STYLESHEET  =\n\n# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the HTML output directory. Note\n# that these files will be copied to the base HTML output directory. Use the\n# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these\n# files. In the HTML_STYLESHEET file, use the file name only. Also note that the\n# files will be copied as-is; there are no commands or markers available.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_EXTRA_FILES       =\n\n# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen\n# will adjust the colors in the style sheet and background images according to\n# this color. Hue is specified as an angle on a color-wheel, see\n# https://en.wikipedia.org/wiki/Hue for more information. For instance the value\n# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300\n# purple, and 360 is red again.\n# Minimum value: 0, maximum value: 359, default value: 220.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_HUE    = 220\n\n# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors\n# in the HTML output. For a value of 0 the output will use gray-scales only. A\n# value of 255 will produce the most vivid colors.\n# Minimum value: 0, maximum value: 255, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_SAT    = 100\n\n# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the\n# luminance component of the colors in the HTML output. Values below 100\n# gradually make the output lighter, whereas values above 100 make the output\n# darker. The value divided by 100 is the actual gamma applied, so 80 represents\n# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not\n# change the gamma.\n# Minimum value: 40, maximum value: 240, default value: 80.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_COLORSTYLE_GAMMA  = 80\n\n# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML\n# page will contain the date and time when the page was generated. Setting this\n# to YES can help to show when doxygen was last run and thus if the\n# documentation is up to date.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_TIMESTAMP         = YES\n\n# If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML\n# documentation will contain a main index with vertical navigation menus that\n# are dynamically created via JavaScript. If disabled, the navigation index will\n# consists of multiple levels of tabs that are statically embedded in every HTML\n# page. Disable this option to support browsers that do not have JavaScript,\n# like the Qt help browser.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_MENUS     = YES\n\n# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML\n# documentation will contain sections that can be hidden and shown after the\n# page has loaded.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_DYNAMIC_SECTIONS  = NO\n\n# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries\n# shown in the various tree structured indices initially; the user can expand\n# and collapse entries dynamically later on. Doxygen will expand the tree to\n# such a level that at most the specified number of entries are visible (unless\n# a fully collapsed tree already exceeds this amount). So setting the number of\n# entries 1 will produce a full collapsed tree by default. 0 is a special value\n# representing an infinite number of entries and will result in a full expanded\n# tree by default.\n# Minimum value: 0, maximum value: 9999, default value: 100.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_INDEX_NUM_ENTRIES = 100\n\n# If the GENERATE_DOCSET tag is set to YES, additional index files will be\n# generated that can be used as input for Apple's Xcode 3 integrated development\n# environment (see:\n# https://developer.apple.com/xcode/), introduced with OSX 10.5 (Leopard). To\n# create a documentation set, doxygen will generate a Makefile in the HTML\n# output directory. Running make will produce the docset in that directory and\n# running make install will install the docset in\n# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at\n# startup. See https://developer.apple.com/library/archive/featuredarticles/Doxy\n# genXcode/_index.html for more information.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_DOCSET        = NO\n\n# This tag determines the name of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# The default value is: Doxygen generated docs.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDNAME        = \"Doxygen generated docs\"\n\n# This tag determines the URL of the docset feed. A documentation feed provides\n# an umbrella under which multiple documentation sets from a single provider\n# (such as a company or product suite) can be grouped.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_FEEDURL         =\n\n# This tag specifies a string that should uniquely identify the documentation\n# set bundle. This should be a reverse domain-name style string, e.g.\n# com.mycompany.MyDocSet. Doxygen will append .docset to the name.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_BUNDLE_ID       = org.doxygen.Project\n\n# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify\n# the documentation publisher. This should be a reverse domain-name style\n# string, e.g. com.mycompany.MyDocSet.documentation.\n# The default value is: org.doxygen.Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_ID    = org.doxygen.Publisher\n\n# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.\n# The default value is: Publisher.\n# This tag requires that the tag GENERATE_DOCSET is set to YES.\n\nDOCSET_PUBLISHER_NAME  = Publisher\n\n# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three\n# additional HTML index files: index.hhp, index.hhc, and index.hhk. The\n# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop\n# on Windows. In the beginning of 2021 Microsoft took the original page, with\n# a.o. the download links, offline the HTML help workshop was already many years\n# in maintenance mode). You can download the HTML help workshop from the web\n# archives at Installation executable (see:\n# http://web.archive.org/web/20160201063255/http://download.microsoft.com/downlo\n# ad/0/A/9/0A939EF6-E31C-430F-A3DF-DFAE7960D564/htmlhelp.exe).\n#\n# The HTML Help Workshop contains a compiler that can convert all HTML output\n# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML\n# files are now used as the Windows 98 help format, and will replace the old\n# Windows help format (.hlp) on all Windows platforms in the future. Compressed\n# HTML files also contain an index, a table of contents, and you can search for\n# words in the documentation. The HTML workshop also contains a viewer for\n# compressed HTML files.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_HTMLHELP      = NO\n\n# The CHM_FILE tag can be used to specify the file name of the resulting .chm\n# file. You can add a path in front of the file if the result should not be\n# written to the html output directory.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_FILE               =\n\n# The HHC_LOCATION tag can be used to specify the location (absolute path\n# including file name) of the HTML help compiler (hhc.exe). If non-empty,\n# doxygen will try to run the HTML help compiler on the generated index.hhp.\n# The file has to be specified with full path.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nHHC_LOCATION           =\n\n# The GENERATE_CHI flag controls if a separate .chi index file is generated\n# (YES) or that it should be included in the main .chm file (NO).\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nGENERATE_CHI           = NO\n\n# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc)\n# and project file content.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nCHM_INDEX_ENCODING     =\n\n# The BINARY_TOC flag controls whether a binary table of contents is generated\n# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it\n# enables the Previous and Next buttons.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nBINARY_TOC             = NO\n\n# The TOC_EXPAND flag can be set to YES to add extra items for group members to\n# the table of contents of the HTML help documentation and to the tree view.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTMLHELP is set to YES.\n\nTOC_EXPAND             = NO\n\n# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and\n# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that\n# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help\n# (.qch) of the generated HTML documentation.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_QHP           = NO\n\n# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify\n# the file name of the resulting .qch file. The path specified is relative to\n# the HTML output folder.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQCH_FILE               =\n\n# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help\n# Project output. For more information please see Qt Help Project / Namespace\n# (see:\n# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#namespace).\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_NAMESPACE          = org.doxygen.Project\n\n# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt\n# Help Project output. For more information please see Qt Help Project / Virtual\n# Folders (see:\n# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#virtual-folders).\n# The default value is: doc.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_VIRTUAL_FOLDER     = doc\n\n# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom\n# filter to add. For more information please see Qt Help Project / Custom\n# Filters (see:\n# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_NAME   =\n\n# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the\n# custom filter to add. For more information please see Qt Help Project / Custom\n# Filters (see:\n# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_CUST_FILTER_ATTRS  =\n\n# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this\n# project's filter section matches. Qt Help Project / Filter Attributes (see:\n# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#filter-attributes).\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHP_SECT_FILTER_ATTRS  =\n\n# The QHG_LOCATION tag can be used to specify the location (absolute path\n# including file name) of Qt's qhelpgenerator. If non-empty doxygen will try to\n# run qhelpgenerator on the generated .qhp file.\n# This tag requires that the tag GENERATE_QHP is set to YES.\n\nQHG_LOCATION           =\n\n# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be\n# generated, together with the HTML files, they form an Eclipse help plugin. To\n# install this plugin and make it available under the help contents menu in\n# Eclipse, the contents of the directory containing the HTML and XML files needs\n# to be copied into the plugins directory of eclipse. The name of the directory\n# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.\n# After copying Eclipse needs to be restarted before the help appears.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_ECLIPSEHELP   = NO\n\n# A unique identifier for the Eclipse help plugin. When installing the plugin\n# the directory name containing the HTML and XML files should also have this\n# name. Each documentation set should have its own identifier.\n# The default value is: org.doxygen.Project.\n# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.\n\nECLIPSE_DOC_ID         = org.doxygen.Project\n\n# If you want full control over the layout of the generated HTML pages it might\n# be necessary to disable the index and replace it with your own. The\n# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top\n# of each HTML page. A value of NO enables the index and the value YES disables\n# it. Since the tabs in the index contain the same information as the navigation\n# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nDISABLE_INDEX          = NO\n\n# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index\n# structure should be generated to display hierarchical information. If the tag\n# value is set to YES, a side panel will be generated containing a tree-like\n# index structure (just like the one that is generated for HTML Help). For this\n# to work a browser that supports JavaScript, DHTML, CSS and frames is required\n# (i.e. any modern browser). Windows users are probably better off using the\n# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can\n# further fine tune the look of the index (see \"Fine-tuning the output\"). As an\n# example, the default style sheet generated by doxygen has an example that\n# shows how to put an image at the root of the tree instead of the PROJECT_NAME.\n# Since the tree basically has the same information as the tab index, you could\n# consider setting DISABLE_INDEX to YES when enabling this option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nGENERATE_TREEVIEW      = YES\n\n# When both GENERATE_TREEVIEW and DISABLE_INDEX are set to YES, then the\n# FULL_SIDEBAR option determines if the side bar is limited to only the treeview\n# area (value NO) or if it should extend to the full height of the window (value\n# YES). Setting this to YES gives a layout similar to\n# https://docs.readthedocs.io with more room for contents, but less room for the\n# project logo, title, and description. If either GENERATE_TREEVIEW or\n# DISABLE_INDEX is set to NO, this option has no effect.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFULL_SIDEBAR           = NO\n\n# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that\n# doxygen will group on one line in the generated HTML documentation.\n#\n# Note that a value of 0 will completely suppress the enum values from appearing\n# in the overview section.\n# Minimum value: 0, maximum value: 20, default value: 4.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nENUM_VALUES_PER_LINE   = 4\n\n# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used\n# to set the initial width (in pixels) of the frame in which the tree is shown.\n# Minimum value: 0, maximum value: 1500, default value: 250.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nTREEVIEW_WIDTH         = 250\n\n# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to\n# external symbols imported via tag files in a separate window.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nEXT_LINKS_IN_WINDOW    = NO\n\n# If the OBFUSCATE_EMAILS tag is set to YES, doxygen will obfuscate email\n# addresses.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nOBFUSCATE_EMAILS       = YES\n\n# If the HTML_FORMULA_FORMAT option is set to svg, doxygen will use the pdf2svg\n# tool (see https://github.com/dawbarton/pdf2svg) or inkscape (see\n# https://inkscape.org) to generate formulas as SVG images instead of PNGs for\n# the HTML output. These images will generally look nicer at scaled resolutions.\n# Possible values are: png (the default) and svg (looks nicer but requires the\n# pdf2svg or inkscape tool).\n# The default value is: png.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nHTML_FORMULA_FORMAT    = png\n\n# Use this tag to change the font size of LaTeX formulas included as images in\n# the HTML documentation. When you change the font size after a successful\n# doxygen run you need to manually remove any form_*.png images from the HTML\n# output directory to force them to be regenerated.\n# Minimum value: 8, maximum value: 50, default value: 10.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_FONTSIZE       = 10\n\n# Use the FORMULA_TRANSPARENT tag to determine whether or not the images\n# generated for formulas are transparent PNGs. Transparent PNGs are not\n# supported properly for IE 6.0, but are supported on all modern browsers.\n#\n# Note that when changing this option you need to delete any form_*.png files in\n# the HTML output directory before the changes have effect.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nFORMULA_TRANSPARENT    = YES\n\n# The FORMULA_MACROFILE can contain LaTeX \\newcommand and \\renewcommand commands\n# to create new LaTeX commands to be used in formulas as building blocks. See\n# the section \"Including formulas\" for details.\n\nFORMULA_MACROFILE      =\n\n# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see\n# https://www.mathjax.org) which uses client side JavaScript for the rendering\n# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX\n# installed or if you want to formulas look prettier in the HTML output. When\n# enabled you may also need to install MathJax separately and configure the path\n# to it using the MATHJAX_RELPATH option.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nUSE_MATHJAX            = YES\n\n# With MATHJAX_VERSION it is possible to specify the MathJax version to be used.\n# Note that the different versions of MathJax have different requirements with\n# regards to the different settings, so it is possible that also other MathJax\n# settings have to be changed when switching between the different MathJax\n# versions.\n# Possible values are: MathJax_2 and MathJax_3.\n# The default value is: MathJax_2.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_VERSION        = MathJax_2\n\n# When MathJax is enabled you can set the default output format to be used for\n# the MathJax output. For more details about the output format see MathJax\n# version 2 (see:\n# http://docs.mathjax.org/en/v2.7-latest/output.html) and MathJax version 3\n# (see:\n# http://docs.mathjax.org/en/latest/web/components/output.html).\n# Possible values are: HTML-CSS (which is slower, but has the best\n# compatibility. This is the name for Mathjax version 2, for MathJax version 3\n# this will be translated into chtml), NativeMML (i.e. MathML. Only supported\n# for NathJax 2. For MathJax version 3 chtml will be used instead.), chtml (This\n# is the name for Mathjax version 3, for MathJax version 2 this will be\n# translated into HTML-CSS) and SVG.\n# The default value is: HTML-CSS.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_FORMAT         = HTML-CSS\n\n# When MathJax is enabled you need to specify the location relative to the HTML\n# output directory using the MATHJAX_RELPATH option. The destination directory\n# should contain the MathJax.js script. For instance, if the mathjax directory\n# is located at the same level as the HTML output directory, then\n# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax\n# Content Delivery Network so you can quickly see the result without installing\n# MathJax. However, it is strongly recommended to install a local copy of\n# MathJax from https://www.mathjax.org before deployment. The default value is:\n# - in case of MathJax version 2: https://cdn.jsdelivr.net/npm/mathjax@2\n# - in case of MathJax version 3: https://cdn.jsdelivr.net/npm/mathjax@3\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_RELPATH        = http://cdn.mathjax.org/mathjax/latest\n\n# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax\n# extension names that should be enabled during MathJax rendering. For example\n# for MathJax version 2 (see\n# https://docs.mathjax.org/en/v2.7-latest/tex.html#tex-and-latex-extensions):\n# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols\n# For example for MathJax version 3 (see\n# http://docs.mathjax.org/en/latest/input/tex/extensions/index.html):\n# MATHJAX_EXTENSIONS = ams\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_EXTENSIONS     =\n\n# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces\n# of code that will be used on startup of the MathJax code. See the MathJax site\n# (see:\n# http://docs.mathjax.org/en/v2.7-latest/output.html) for more details. For an\n# example see the documentation.\n# This tag requires that the tag USE_MATHJAX is set to YES.\n\nMATHJAX_CODEFILE       =\n\n# When the SEARCHENGINE tag is enabled doxygen will generate a search box for\n# the HTML output. The underlying search engine uses javascript and DHTML and\n# should work on any modern browser. Note that when using HTML help\n# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)\n# there is already a search function so this one should typically be disabled.\n# For large projects the javascript based search engine can be slow, then\n# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to\n# search using the keyboard; to jump to the search box use <access key> + S\n# (what the <access key> is depends on the OS and browser, but it is typically\n# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down\n# key> to jump into the search results window, the results can be navigated\n# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel\n# the search. The filter options can be selected when the cursor is inside the\n# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>\n# to select a filter and <Enter> or <escape> to activate or cancel the filter\n# option.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_HTML is set to YES.\n\nSEARCHENGINE           = YES\n\n# When the SERVER_BASED_SEARCH tag is enabled the search engine will be\n# implemented using a web server instead of a web client using JavaScript. There\n# are two flavors of web server based searching depending on the EXTERNAL_SEARCH\n# setting. When disabled, doxygen will generate a PHP script for searching and\n# an index file used by the script. When EXTERNAL_SEARCH is enabled the indexing\n# and searching needs to be provided by external tools. See the section\n# \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSERVER_BASED_SEARCH    = NO\n\n# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP\n# script for searching. Instead the search results are written to an XML file\n# which needs to be processed by an external indexer. Doxygen will invoke an\n# external search engine pointed to by the SEARCHENGINE_URL option to obtain the\n# search results.\n#\n# Doxygen ships with an example indexer (doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see:\n# https://xapian.org/).\n#\n# See the section \"External Indexing and Searching\" for details.\n# The default value is: NO.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH        = NO\n\n# The SEARCHENGINE_URL should point to a search engine hosted by a web server\n# which will return the search results when EXTERNAL_SEARCH is enabled.\n#\n# Doxygen ships with an example indexer (doxyindexer) and search engine\n# (doxysearch.cgi) which are based on the open source search engine library\n# Xapian (see:\n# https://xapian.org/). See the section \"External Indexing and Searching\" for\n# details.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHENGINE_URL       =\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed\n# search data is written to a file for indexing by an external tool. With the\n# SEARCHDATA_FILE tag the name of this file can be specified.\n# The default file is: searchdata.xml.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nSEARCHDATA_FILE        = searchdata.xml\n\n# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the\n# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is\n# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple\n# projects and redirect the results back to the right project.\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTERNAL_SEARCH_ID     =\n\n# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen\n# projects other than the one defined by this configuration file, but that are\n# all added to the same external search index. Each project needs to have a\n# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of\n# to a relative location where the documentation can be found. The format is:\n# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...\n# This tag requires that the tag SEARCHENGINE is set to YES.\n\nEXTRA_SEARCH_MAPPINGS  =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the LaTeX output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_LATEX tag is set to YES, doxygen will generate LaTeX output.\n# The default value is: YES.\n\nGENERATE_LATEX         = NO\n\n# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: latex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_OUTPUT           = latex\n\n# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be\n# invoked.\n#\n# Note that when not enabling USE_PDFLATEX the default is latex when enabling\n# USE_PDFLATEX the default is pdflatex and when in the later case latex is\n# chosen this is overwritten by pdflatex. For specific output languages the\n# default can have been set differently, this depends on the implementation of\n# the output language.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_CMD_NAME         = latex\n\n# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate\n# index for LaTeX.\n# Note: This tag is used in the Makefile / make.bat.\n# See also: LATEX_MAKEINDEX_CMD for the part in the generated output file\n# (.tex).\n# The default file is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nMAKEINDEX_CMD_NAME     = makeindex\n\n# The LATEX_MAKEINDEX_CMD tag can be used to specify the command name to\n# generate index for LaTeX. In case there is no backslash (\\) as first character\n# it will be automatically added in the LaTeX code.\n# Note: This tag is used in the generated output file (.tex).\n# See also: MAKEINDEX_CMD_NAME for the part in the Makefile / make.bat.\n# The default value is: makeindex.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_MAKEINDEX_CMD    = makeindex\n\n# If the COMPACT_LATEX tag is set to YES, doxygen generates more compact LaTeX\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nCOMPACT_LATEX          = YES\n\n# The PAPER_TYPE tag can be used to set the paper type that is used by the\n# printer.\n# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x\n# 14 inches) and executive (7.25 x 10.5 inches).\n# The default value is: a4.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPAPER_TYPE             = a4\n\n# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names\n# that should be included in the LaTeX output. The package can be specified just\n# by its name or with the correct syntax as to be used with the LaTeX\n# \\usepackage command. To get the times font for instance you can specify :\n# EXTRA_PACKAGES=times or EXTRA_PACKAGES={times}\n# To use the option intlimits with the amsmath package you can specify:\n# EXTRA_PACKAGES=[intlimits]{amsmath}\n# If left blank no extra packages will be included.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nEXTRA_PACKAGES         =\n\n# The LATEX_HEADER tag can be used to specify a user-defined LaTeX header for\n# the generated LaTeX document. The header should contain everything until the\n# first chapter. If it is left blank doxygen will generate a standard header. It\n# is highly recommended to start with a default header using\n# doxygen -w latex new_header.tex new_footer.tex new_stylesheet.sty\n# and then modify the file new_header.tex. See also section \"Doxygen usage\" for\n# information on how to generate the default header that doxygen normally uses.\n#\n# Note: Only use a user-defined header if you know what you are doing!\n# Note: The header is subject to change so you typically have to regenerate the\n# default header when upgrading to a newer version of doxygen. The following\n# commands have a special meaning inside the header (and footer): For a\n# description of the possible markers and block names see the documentation.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HEADER           =\n\n# The LATEX_FOOTER tag can be used to specify a user-defined LaTeX footer for\n# the generated LaTeX document. The footer should contain everything after the\n# last chapter. If it is left blank doxygen will generate a standard footer. See\n# LATEX_HEADER for more information on how to generate a default footer and what\n# special commands can be used inside the footer. See also section \"Doxygen\n# usage\" for information on how to generate the default footer that doxygen\n# normally uses. Note: Only use a user-defined footer if you know what you are\n# doing!\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_FOOTER           =\n\n# The LATEX_EXTRA_STYLESHEET tag can be used to specify additional user-defined\n# LaTeX style sheets that are included after the standard style sheets created\n# by doxygen. Using this option one can overrule certain style aspects. Doxygen\n# will copy the style sheet files to the output directory.\n# Note: The order of the extra style sheet files is of importance (e.g. the last\n# style sheet in the list overrules the setting of the previous ones in the\n# list).\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_STYLESHEET =\n\n# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or\n# other source files which should be copied to the LATEX_OUTPUT output\n# directory. Note that the files will be copied as-is; there are no commands or\n# markers available.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EXTRA_FILES      =\n\n# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is\n# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will\n# contain links (just like the HTML output) instead of page references. This\n# makes the output suitable for online browsing using a PDF viewer.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nPDF_HYPERLINKS         = YES\n\n# If the USE_PDFLATEX tag is set to YES, doxygen will use the engine as\n# specified with LATEX_CMD_NAME to generate the PDF file directly from the LaTeX\n# files. Set this option to YES, to get a higher quality PDF documentation.\n#\n# See also section LATEX_CMD_NAME for selecting the engine.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nUSE_PDFLATEX           = YES\n\n# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode\n# command to the generated LaTeX files. This will instruct LaTeX to keep running\n# if errors occur, instead of asking the user for help.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BATCHMODE        = NO\n\n# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the\n# index chapters (such as File Index, Compound Index, etc.) in the output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_HIDE_INDICES     = NO\n\n# The LATEX_BIB_STYLE tag can be used to specify the style to use for the\n# bibliography, e.g. plainnat, or ieeetr. See\n# https://en.wikipedia.org/wiki/BibTeX and \\cite for more info.\n# The default value is: plain.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_BIB_STYLE        = plain\n\n# If the LATEX_TIMESTAMP tag is set to YES then the footer of each generated\n# page will contain the date and time when the page was generated. Setting this\n# to NO can help when comparing the output of multiple runs.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_TIMESTAMP        = NO\n\n# The LATEX_EMOJI_DIRECTORY tag is used to specify the (relative or absolute)\n# path from which the emoji images will be read. If a relative path is entered,\n# it will be relative to the LATEX_OUTPUT directory. If left blank the\n# LATEX_OUTPUT directory will be used.\n# This tag requires that the tag GENERATE_LATEX is set to YES.\n\nLATEX_EMOJI_DIRECTORY  =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the RTF output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_RTF tag is set to YES, doxygen will generate RTF output. The\n# RTF output is optimized for Word 97 and may not look too pretty with other RTF\n# readers/editors.\n# The default value is: NO.\n\nGENERATE_RTF           = NO\n\n# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: rtf.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_OUTPUT             = rtf\n\n# If the COMPACT_RTF tag is set to YES, doxygen generates more compact RTF\n# documents. This may be useful for small projects and may help to save some\n# trees in general.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nCOMPACT_RTF            = YES\n\n# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will\n# contain hyperlink fields. The RTF file will contain links (just like the HTML\n# output) instead of page references. This makes the output suitable for online\n# browsing using Word or some other Word compatible readers that support those\n# fields.\n#\n# Note: WordPad (write) and others do not support links.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_HYPERLINKS         = YES\n\n# Load stylesheet definitions from file. Syntax is similar to doxygen's\n# configuration file, i.e. a series of assignments. You only have to provide\n# replacements, missing definitions are set to their default value.\n#\n# See also section \"Doxygen usage\" for information on how to generate the\n# default style sheet that doxygen normally uses.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_STYLESHEET_FILE    =\n\n# Set optional variables used in the generation of an RTF document. Syntax is\n# similar to doxygen's configuration file. A template extensions file can be\n# generated using doxygen -e rtf extensionFile.\n# This tag requires that the tag GENERATE_RTF is set to YES.\n\nRTF_EXTENSIONS_FILE    =\n\n#---------------------------------------------------------------------------\n# Configuration options related to the man page output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_MAN tag is set to YES, doxygen will generate man pages for\n# classes and files.\n# The default value is: NO.\n\nGENERATE_MAN           = NO\n\n# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it. A directory man3 will be created inside the directory specified by\n# MAN_OUTPUT.\n# The default directory is: man.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_OUTPUT             = man\n\n# The MAN_EXTENSION tag determines the extension that is added to the generated\n# man pages. In case the manual section does not start with a number, the number\n# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is\n# optional.\n# The default value is: .3.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_EXTENSION          = .3\n\n# The MAN_SUBDIR tag determines the name of the directory created within\n# MAN_OUTPUT in which the man pages are placed. If defaults to man followed by\n# MAN_EXTENSION with the initial . removed.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_SUBDIR             =\n\n# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it\n# will generate one additional man file for each entity documented in the real\n# man page(s). These additional files only source the real man page, but without\n# them the man command would be unable to find the correct page.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_MAN is set to YES.\n\nMAN_LINKS              = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the XML output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_XML tag is set to YES, doxygen will generate an XML file that\n# captures the structure of the code including all documentation.\n# The default value is: NO.\n\nGENERATE_XML           = YES\n\n# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a\n# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of\n# it.\n# The default directory is: xml.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_OUTPUT             = xml\n\n# If the XML_PROGRAMLISTING tag is set to YES, doxygen will dump the program\n# listings (including syntax highlighting and cross-referencing information) to\n# the XML output. Note that enabling this will significantly increase the size\n# of the XML output.\n# The default value is: YES.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_PROGRAMLISTING     = YES\n\n# If the XML_NS_MEMB_FILE_SCOPE tag is set to YES, doxygen will include\n# namespace members in file scope as well, matching the HTML output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_XML is set to YES.\n\nXML_NS_MEMB_FILE_SCOPE = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the DOCBOOK output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_DOCBOOK tag is set to YES, doxygen will generate Docbook files\n# that can be used to generate PDF.\n# The default value is: NO.\n\nGENERATE_DOCBOOK       = NO\n\n# The DOCBOOK_OUTPUT tag is used to specify where the Docbook pages will be put.\n# If a relative path is entered the value of OUTPUT_DIRECTORY will be put in\n# front of it.\n# The default directory is: docbook.\n# This tag requires that the tag GENERATE_DOCBOOK is set to YES.\n\nDOCBOOK_OUTPUT         = docbook\n\n#---------------------------------------------------------------------------\n# Configuration options for the AutoGen Definitions output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_AUTOGEN_DEF tag is set to YES, doxygen will generate an\n# AutoGen Definitions (see http://autogen.sourceforge.net/) file that captures\n# the structure of the code including all documentation. Note that this feature\n# is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_AUTOGEN_DEF   = NO\n\n#---------------------------------------------------------------------------\n# Configuration options related to the Perl module output\n#---------------------------------------------------------------------------\n\n# If the GENERATE_PERLMOD tag is set to YES, doxygen will generate a Perl module\n# file that captures the structure of the code including all documentation.\n#\n# Note that this feature is still experimental and incomplete at the moment.\n# The default value is: NO.\n\nGENERATE_PERLMOD       = NO\n\n# If the PERLMOD_LATEX tag is set to YES, doxygen will generate the necessary\n# Makefile rules, Perl scripts and LaTeX code to be able to generate PDF and DVI\n# output from the Perl module output.\n# The default value is: NO.\n# This tag requires that the tag GENERATE_PERLMOD is set to YES.\n\nPERLMOD_LATEX          = NO\n\n# If the PERLMOD_PRETTY tag is set to YES, the Perl module output will be nicely\n# formatted so it can be parsed by a human reader. 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    "path": "docs/examples/index.rst",
    "content": ".. _examples:\n\nExamples and demos\n==================\n\nVarious examples are provided for fast library evaluation on embedded systems. These are prepared and maintained for ``2`` platforms, but could be easily extended to more platforms:\n\n* WIN32 examples, prepared as `CMake` projects, ready for `MSYS2 GCC compiler`\n* ARM Cortex-M examples for STM32, prepared as `STM32CubeIDE <https://www.st.com/en/development-tools/stm32cubeide.html>`_ GCC projects. These are also supported in *Visual Studio Code* through *CMake* and *ninja* build system. `Dedicated tutorial <https://github.com/MaJerle/stm32-cube-cmake-vscode>`_ is available to get started in *VSCode*.\n\n.. note::\n\tLibrary is platform agnostic and can be used on many different products\n\nExample architectures\n^^^^^^^^^^^^^^^^^^^^^\n\nThere are many platforms available today on a market, however supporting them all would be tough task for single person.\nTherefore it has been decided to support (for purpose of examples) ``2`` platforms only, `WIN32` and `STM32`.\n\nWIN32\n*****\n\nExamples for *WIN32* are CMake-ready and *VSCode*-ready.\nIt utilizes CMake-presets feature to let you select the example and compile it directly.\n\n* Make sure you have installed GCC compiler and is in env path (you can get it through MSYS2 packet manager)\n* Install ninja and cmake and make them available in the path (you can get all through MSYS2 packet manager)\n* Go to *examples win32* folder, open vscode there or run cmd: ``cmake --preset <project name>`` to configure cmake and later ``cmake --build --preset <project name>`` to compile the project\n\nApplication opens *COM* port, set in the low-level driver.\nExternal USB to UART converter (FTDI-like device) is necessary in order to connect to *ESP* device.\n\n.. note::\n\t*ESP* device is connected with *USB to UART converter* only by *RX* and *TX* pins.\n\nDevice driver is located in ``/lwesp/src/system/lwesp_ll_win32.c``\n\nSTM32\n*****\n\nEmbedded market is supported by many vendors and STMicroelectronics is, with their `STM32 <https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html>`_ series of microcontrollers, one of the most important players.\nThere are numerous amount of examples and topics related to this architecture.\n\nExamples for *STM32* are natively supported with `STM32CubeIDE <https://www.st.com/en/development-tools/stm32cubeide.html>`_, an official development IDE from STMicroelectronics.\n\nYou can run examples on one of official development boards, available in repository examples.\n\n.. table:: Supported development boards\n\n\t+----------------------+--------------------------------------------------+----------------------+\n\t| Board name           | ESP settings                                     | Debug settings       |\n\t|                      +--------+------+------+------+------+------+------+--------+------+------+\n\t|                      | UART   | MTX  | MRX  | RST  | GP0  | GP2  | CHPD | UART   | MDTX | MDRX |\n\t+======================+========+======+======+======+======+======+======+========+======+======+\n\t| STM32F769I-Discovery | UART5  | PC12 | PD2  | PJ14 | -    | -    | -    | USART1 | PA9  | PA10 |\n\t+----------------------+--------+------+------+------+------+------+------+--------+------+------+\n\t| STM32F723E-Discovery | UART5  | PC12 | PD2  | PG14 | -    | PD6  | PD3  | USART6 | PC6  | PC7  |\n\t+----------------------+--------+------+------+------+------+------+------+--------+------+------+\n\t| STM32L496G-Discovery | USART1 | PB6  | PG10 | PB2  | PH2  | PA0  | PA4  | USART2 | PA2  | PD6  |\n\t+----------------------+--------+------+------+------+------+------+------+--------+------+------+\n\t| STM32L432KC-Nucleo   | USART1 | PA9  | PA10 | PA12 | PA7  | PA6  | PB0  | USART2 | PA2  | PA3  |\n\t+----------------------+--------+------+------+------+------+------+------+--------+------+------+\n\t| STM32F429ZI-Nucleo   | USART2 | PD5  | PD6  | PD1  | PD4  | PD7  | PD3  | USART3 | PD8  | PD9  |\n\t+----------------------+--------+------+------+------+------+------+------+--------+------+------+\n\nPins to connect with ESP device:\n\n* *MTX*: MCU TX pin, connected to ESP RX pin\n* *MRX*: MCU RX pin, connected to ESP TX pin\n* *RST*: MCU output pin to control reset state of ESP device\n* *GP0*: `GPIO0` pin of ESP8266, connected to MCU, configured as output at MCU side\n* *GP2*: `GPIO2` pin of ESP8266, connected to MCU, configured as output at MCU side\n* *CHPD*: `CH_PD` pin of ESP8266, connected to MCU, configured as output at MCU side\n\n.. note::\n\t*GP0*, *GP2*, *CH_PD* pins are not always necessary for *ESP* device to work properly.\n\tWhen not used, these pins must be tied to fixed values as explained in *ESP* datasheet.\n\nOther pins are for your information and are used for debugging purposes on board.\n\n* MDTX: MCU Debug TX pin, connected via on-board ST-Link to PC\n* MDRX: MCU Debug RX pin, connected via on-board ST-Link to PC\n* Baudrate is always set to ``921600`` bauds\n\nExamples list\n^^^^^^^^^^^^^\n\nHere is a list of all examples coming with this library.\n\n.. tip::\n\tExamples are located in ``/examples/`` folder in downloaded package.\n\tCheck :ref:`download_library` section to get your package.\n\n.. warning::\n\tSeveral examples need to connect to access point first, then they may start client connection or pinging server.\n\tApplication needs to modify file ``/snippets/station_manager.c`` and update ``ap_list`` variable with preferred access points,\n\tin order to allow *ESP* to connect to home/local network\n\nAccess point\n************\n\n*ESP* device is configured as software access point, allowing stations to connect to it.\nWhen station connects to access point, it will output its *MAC* and *IP* addresses.\n\nClient\n******\n\nApplication tries to connect to custom server with classic, event-based API.\nIt starts concurrent connections and processes data in its event callback function.\n\nServer\n******\n\nIt starts server on port ``80`` in event based connection mode.\nEvery client is processed in callback function.\n\nWhen *ESP* is successfully connected to access point, it is possible to connect to it using its assigned IP address.\n\nDomain name server\n******************\n\n*ESP* tries to get domain name from specific domain name, ``example.com`` as an example.\nIt needs to be connected to access point to have access to global internet.\n\nMQTT Client\n***********\n\nThis example demonstrates raw MQTT connection to mosquitto test server.\nA new application thread is started after *ESP* successfully connects to access point.\nMQTT application starts by initiating a new TCP connection.\n\nThis is event-based example as there is no linear code.\n\nMQTT Client API\n***************\n\nSimilar to *MQTT Client* examples, but it uses separate thread to process\nevents in blocking mode. Application does not use events to process data,\nrather it uses blocking API to receive packets\n\nNetconn client\n**************\n\nNetconn client is based on sequential API.\nIt starts connection to server, sends initial request and then waits to receive data.\n\nProcessing is in separate thread and fully sequential, no callbacks or events.\n\nNetconn server\n**************\n\nNetconn server is based on sequential API.\nIt starts server on specific port (see example details) and it waits for new client in separate threads.\nOnce new client has been accepted, it waits for client request and processes data accordingly by sending reply message back.\n\n.. tip::\n\tServer may accept multiple clients at the same time\n\n.. toctree::\n\t:maxdepth: 2\n"
  },
  {
    "path": "docs/examples_src/command_blocking.c",
    "content": "char hostname[20];\n\n/* Somewhere in thread function */\n\n/* Get device hostname in blocking mode */\n/* Function returns actual result */\nif (lwesp_hostname_get(hostname, sizeof(hostname), NULL, NULL, 1 /* 1 means blocking call */) == lwespOK) {\n    /* At this point we have valid result and parameters from API function */\n    printf(\"ESP hostname is %s\\r\\n\", hostname);\n} else {\n    printf(\"Error reading ESP hostname..\\r\\n\");\n}"
  },
  {
    "path": "docs/examples_src/command_nonblocking.c",
    "content": "char hostname[20];\n\n/* Hostname event function, called when lwesp_hostname_get() function finishes */\nvoid\nhostname_fn(lwespr_t res, void* arg) {\n    /* Check actual result from device */\n    if (res == lwespOK) {\n        printf(\"ESP hostname is %s\\r\\n\", hostname);\n    } else {\n        printf(\"Error reading ESP hostname...\\r\\n\");\n    }\n}\n\n/* Somewhere in thread and/or other ESP event function */\n\n/* Get device hostname in non-blocking mode */\n/* Function now returns if command has been sent to internal message queue */\nif (lwesp_hostname_get(hostname, sizeof(hostname), hostname_fn, NULL, 0 /* 0 means non-blocking call */) == lwespOK) {\n    /* At this point application knows that command has been sent to queue */\n    /* But it does not have yet valid data in \"hostname\" variable */\n    printf(\"ESP hostname get command sent to queue.\\r\\n\");\n} else {\n    /* Error writing message to queue */\n    printf(\"Cannot send hostname get command to queue.\\r\\n\");\n}"
  },
  {
    "path": "docs/examples_src/command_nonblocking_bad.c",
    "content": "char hostname[20];\n\n/* Hostname event function, called when lwesp_hostname_get() function finishes */\nvoid\nhostname_fn(lwespr_t res, void* arg) {\n    /* Check actual result from device */\n    if (res == lwespOK) {\n        printf(\"ESP hostname is %s\\r\\n\", hostname);\n    } else {\n        printf(\"Error reading ESP hostname...\\r\\n\");\n    }\n}\n\n/* Check hostname */\nvoid\ncheck_hostname(void) {\n    char hostname[20];\n\n    /* Somewhere in thread and/or other ESP event function */\n\n    /* Get device hostname in non-blocking mode */\n    /* Function now returns if command has been sent to internal message queue */\n    /* Function will use local \"hostname\" variable and will write to undefined memory */\n    if (lwesp_hostname_get(hostname, sizeof(hostname), hostname_fn, NULL, 0 /* 0 means non-blocking call */) == lwespOK) {\n        /* At this point application knows that command has been sent to queue */\n        /* But it does not have yet valid data in \"hostname\" variable */\n        printf(\"ESP hostname get command sent to queue.\\r\\n\");\n    } else {\n        /* Error writing message to queue */\n        printf(\"Cannot send hostname get command to queue.\\r\\n\");\n    }\n}"
  },
  {
    "path": "docs/examples_src/config.h",
    "content": "#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/* Increase default receive buffer length */\n#define LWESP_RCV_BUFF_SIZE                   0x800\n\n#endif /* LWESP_HDR_OPTS_H */"
  },
  {
    "path": "docs/examples_src/conn_write.c",
    "content": "size_t rem_len;\nlwesp_conn_p conn;\nlwespr_t res;\n\n/* ... other tasks to make sure connection is established */\n\n/* We are connected to server at this point! */\n/*\n * Call write function to write data to memory\n * and do not send immediately unless buffer is full after this write\n *\n * rem_len will give us response how much bytes\n * is available in memory after write\n */\nres = lwesp_conn_write(conn, \"My string\", 9, 0, &rem_len);\nif (rem_len == 0) {\n    printf(\"No more memory available for next write!\\r\\n\");\n}\nres = lwesp_conn_write(conn, \"example.com\", 11, 0, &rem_len);\n\n/*\n * Data will stay in buffer until buffer is full,\n * except if user wants to force send,\n * call write function with flush mode enabled\n *\n * It will send out together 20 bytes\n */\nlwesp_conn_write(conn, NULL, 0, 1, NULL);\n"
  },
  {
    "path": "docs/examples_src/debug.c",
    "content": "#include \"lwesp/lwesp_debug.h\"\n\n/*\n * Print debug message to the screen\n * Trace message will be printed as it is enabled in types\n * while state message will not be printed.\n */\nLWESP_DEBUGF(MY_DBG_MODULE | LWESP_DBG_TYPE_TRACE, \"This is trace message on my program\\r\\n\");\nLWESP_DEBUGF(MY_DBG_MODULE | LWESP_DBG_TYPE_STATE, \"This is state message on my program\\r\\n\");\n"
  },
  {
    "path": "docs/examples_src/debug_opts.h",
    "content": "/* Modifications of lwesp_opts.h file for configuration */\n\n/* Enable global debug */\n#define LWESP_CFG_DBG               LWESP_DBG_ON\n\n/*\n * Enable debug types.\n * Application may use bitwise OR | to use multiple types:\n *    LWESP_DBG_TYPE_TRACE | LWESP_DBG_TYPE_STATE\n */\n#define LWESP_CFG_DBG_TYPES_ON      LWESP_DBG_TYPE_TRACE\n\n/* Enable debug on custom module */\n#define MY_DBG_MODULE               LWESP_DBG_ON\n"
  },
  {
    "path": "docs/examples_src/evt.c",
    "content": "/*\n * \\brief           User defined callback function for ESP events\n * \\param[in]       evt: Callback event data\n */\nlwespr_t\nlwesp_callback_function(lwesp_evt_t* evt) {\n    switch (lwesp_evt_get_type(evt)) {\n        case LWESP_EVT_RESET: {                    /* Reset detected on ESP device */\n            if (lwesp_evt_reset_is_forced(evt)) {  /* Check if forced by user */\n                printf(\"Reset forced by user!\\r\\n\");\n            }\n            break;\n        }\n        default: break;\n    }\n    return lwespOK;\n}"
  },
  {
    "path": "docs/examples_src/mem.c",
    "content": "/*\n * This part should be done in ll initialization function only once on startup\n * Check LWESP_LL part of library for more info\n */\n\n#if !LWESP_CFG_MEM_CUSTOM\n\n/* We can simply create a big array variable which will be linked to internal memory by linker */\nuint8_t mem_int[0x1000];\n\n/*\n * Define memory regions for allocating algorithm,\n * make sure regions are in correct order for memory location\n */\nlwesp_mem_region_t mem_regions[] = {\n    { mem_int, sizeof(mem_int) },               /* Set first memory region to internal memory of length 0x1000 bytes */\n    { (void *)0xC0000000, 0x8000 },             /* External heap memory is located on 0xC0000000 and has 0x8000 bytes of memory */\n};\n\n/* On startup, user must call function to assign memory regions */\nlwesp_mem_assignmemory(mem_regions, LWESP_ARRAYSIZE(mem_regions));\n\n#endif /* !LWESP_CFG_MEM_CUSTOM */"
  },
  {
    "path": "docs/examples_src/pbuf_cat.c",
    "content": "lwesp_pbuf_p a, b;\n\n/* Create 2 pbufs of different sizes */\na = lwesp_pbuf_new(10);\nb = lwesp_pbuf_new(20);\n\n/* Link them together with concat operation */\n/* Reference on b will stay as is, won't be increased */\nlwesp_pbuf_cat(a, b);\n\n/*\n * Operating with b variable has from now on undefined behavior,\n * application shall stop using variable b to access pbuf.\n *\n * The best way would be to set b reference to NULL\n */\nb = NULL;\n\n/*\n * When application doesn't need pbufs anymore,\n * free a and it will also free b\n */\nlwesp_pbuf_free(a);"
  },
  {
    "path": "docs/examples_src/pbuf_chain.c",
    "content": "lwesp_pbuf_p a, b;\n\n/* Create 2 pbufs of different sizes */\na = lwesp_pbuf_new(10);\nb = lwesp_pbuf_new(20);\n\n/* Chain both pbufs together */\n/* This will increase reference on b as 2 variables now point to it */\nlwesp_pbuf_chain(a, b);\n\n/*\n * When application does not need a anymore, it may free it\n\n * This will free only pbuf a, as pbuf b has now 2 references:\n *  - one from pbuf a\n *  - one from variable b\n */\n\n/* If application calls this, it will free only first pbuf */\n/* As there is link to b pbuf somewhere */\nlwesp_pbuf_free(a);\n\n/* Reset a variable, not used anymore */\na = NULL;\n\n/*\n * At this point, b is still valid memory block,\n * but when application doesn't need it anymore,\n * it should free it, otherwise memory leak appears\n */\nlwesp_pbuf_free(b);\n\n/* Reset b variable */\nb = NULL;"
  },
  {
    "path": "docs/examples_src/pbuf_extract.c",
    "content": "const void* data;\nsize_t pos, len;\nlwesp_pbuf_p a, b, c;\n\nconst char str_a[] = \"This is one long\";\nconst char str_a[] = \"string. We want to save\";\nconst char str_a[] = \"chain of pbufs to file\";\n\n/* Create pbufs to hold these strings */\na = lwesp_pbuf_new(strlen(str_a));\nb = lwesp_pbuf_new(strlen(str_b));\nc = lwesp_pbuf_new(strlen(str_c));\n\n/* Write data to pbufs */\nlwesp_pbuf_take(a, str_a, strlen(str_a), 0);\nlwesp_pbuf_take(b, str_b, strlen(str_b), 0);\nlwesp_pbuf_take(c, str_c, strlen(str_c), 0);\n\n/* Connect pbufs together */\nlwesp_pbuf_chain(a, b);\nlwesp_pbuf_chain(a, c);\n\n/*\n * pbuf a now contains chain of b and c together\n * and at this point application wants to print (or save) data from chained pbuf\n *\n * Process pbuf by pbuf with code below\n */\n\n/*\n * Get linear address of current pbuf at specific offset\n * Function will return pointer to memory address at specific position\n * and `len` will hold length of data block\n */\npos = 0;\nwhile ((data = lwesp_pbuf_get_linear_addr(a, pos, &len)) != NULL) {\n    /* Custom process function... */\n    /* Process data with data pointer and block length */\n    process_data(data, len);\n    printf(\"Str: %.*s\", len, data);\n\n    /* Increase offset position for next block */\n    pos += len;\n}\n\n/* Call free only on a pbuf. Since it is chained, b and c will be freed too */\nlwesp_pbuf_free(a);\n"
  },
  {
    "path": "docs/examples_src/sntp_custom_server.c",
    "content": "/* Set custom NTP servers. You may apply up to 3 servers, all are optional */\nlwesp_sntp_set_config(1, 1, \"server1.myntp.com\", \"server2.myntp.com\", \"server3.myntp.com\", NULL, NULL, 1);"
  },
  {
    "path": "docs/examples_src/sta.c",
    "content": "size_t i, apf;\nlwesp_ap_t aps[100];\n\n/* Search for access points around ESP station */\nif (lwesp_sta_list_ap(NULL, aps, LWESP_ARRAYSIZE(aps), &apf, NULL, NULL, 1) == lwespOK) {\n    for (i = 0; i < apf; i++) {\n        printf(\"AP found: %s\\r\\n\", aps[i].ssid);\n    }\n}"
  },
  {
    "path": "docs/firmware-update/index.rst",
    "content": ".. _firmware_update:\n\nUpdate ESP AT firmware\n======================\n\nLwESP is developed to match latest releases of official Espressif AT releases for various ESP devices.\n\nHave a look in `their AT firmware documentation pages to find out more <https://docs.espressif.com/projects/esp-at/en/latest/index.html>`_."
  },
  {
    "path": "docs/get-started/index.rst",
    "content": ".. _getting_started:\n\nGetting started\n===============\n\nGetting started may be the most challenging part of every new library.\nThis guide is describing how to start with the library quickly and effectively\n\n.. _download_library:\n\nDownload library\n^^^^^^^^^^^^^^^^\n\nLibrary is primarly hosted on `Github <https://github.com/MaJerle/lwesp>`_.\n\nYou can get it by:\n\n* Downloading latest release from `releases area <https://github.com/MaJerle/lwesp/releases>`_ on Github\n* Clone ``main`` branch for latest stable version\n* Clone ``develop`` branch for latest development\n\nDownload from releases\n**********************\n\nAll releases are available on Github `releases area <https://github.com/MaJerle/lwesp/releases>`_.\n\nClone from Github\n*****************\n\nFirst-time clone\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThis is used when you do not have yet local copy on your machine.\n\n* Make sure ``git`` is installed.\n* Open console and navigate to path in the system to clone repository to. Use command ``cd your_path``\n* Clone repository with one of available options below\n\n  * Run ``git clone --recurse-submodules https://github.com/MaJerle/lwesp`` command to clone entire repository, including submodules\n  * Run ``git clone --recurse-submodules --branch develop https://github.com/MaJerle/lwesp`` to clone `development` branch, including submodules\n  * Run ``git clone --recurse-submodules --branch main https://github.com/MaJerle/lwesp`` to clone `latest stable` branch, including submodules\n\n* Navigate to ``examples`` directory and run favourite example\n\nUpdate cloned to latest version\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\n* Open console and navigate to path in the system where your repository is located. Use command ``cd your_path``\n* Run ``git pull origin main`` command to get latest changes on ``main`` branch\n* Run ``git pull origin develop`` command to get latest changes on ``develop`` branch\n* Run ``git submodule update --init --remote`` to update submodules to latest version\n\n.. note::\n  This is preferred option to use when you want to evaluate library and run prepared examples.\n  Repository consists of multiple submodules which can be automatically downloaded when cloning and pulling changes from root repository.\n\nAdd library to project\n^^^^^^^^^^^^^^^^^^^^^^\n\nAt this point it is assumed that you have successfully download library, either with ``git clone`` command or with manual download from the library releases page.\nNext step is to add the library to the project, by means of source files to compiler inputs and header files in search path.\n\n*CMake* is the main supported build system. Package comes with the ``CMakeLists.txt`` and ``library.cmake`` files, both located in the ``lwesp`` directory:\n\n* ``library.cmake``: It is a fully configured set of variables and with library definition. User can include this file to the project file with ``include(path/to/library.cmake)`` and then manually use the variables provided by the file, such as list of source files, include paths or necessary compiler definitions. It is up to the user to properly use the this file on its own.\n* ``CMakeLists.txt``: It is a wrapper-only file and includes ``library.cmake`` file. It is used for when user wants to include the library to the main project by simply calling *CMake* ``add_subdirectory`` command, followed by ``target_link_libraries`` to link external library to the final project.\n\n.. tip::\n    Open ``library.cmake`` and analyze the provided information. Among variables, you can also find list of all possible exposed libraries for the user.\n\nIf you do not use the *CMake*, you can do the following:\n\n* Copy ``lwesp`` folder to your project, it contains library files\n* Add ``lwesp/src/include`` folder to `include path` of your toolchain. This is where `C/C++` compiler can find the files during compilation process. Usually using ``-I`` flag\n* Add source files from ``lwesp/src/`` folder to toolchain build. These files are built by `C/C++` compiler\n* Copy ``lwesp/src/include/lwesp/lwesp_opts_template.h`` to project folder and rename it to ``lwesp_opts.h``\n* Build the project\n\nConfiguration file\n^^^^^^^^^^^^^^^^^^\n\nConfiguration file is used to overwrite default settings defined for the essential use case.\nLibrary comes with template config file, which can be modified according to the application needs.\nand it should be copied (or simply renamed in-place) and named ``lwesp_opts.h``\n\n.. note::\n    Default configuration template file location: ``lwesp/src/include/lwesp/lwesp_opts_template.h``.\n    File must be renamed to ``lwesp_opts.h`` first and then copied to the project directory where compiler\n    include paths have access to it by using ``#include \"lwesp_opts.h\"``.\n\n.. tip::\n    If you are using *CMake* build system, define the variable ``LWESP_OPTS_FILE`` before adding library's directory to the *CMake* project.\n    Variable must contain the path to the user options file. If not provided and to avoid build error, one will be generated in the build directory.\n\nConfiguration options list is available available in the :ref:`api_lwesp_opt` section.\nIf any option is about to be modified, it should be done in configuration file\n\n.. literalinclude:: ../../lwesp/src/include/lwesp/lwesp_opts_template.h\n    :language: c\n    :linenos:\n    :caption: Template configuration file\n\n.. note::\n    If you prefer to avoid using configuration file, application must define\n    a global symbol ``LWESP_IGNORE_USER_OPTS``, visible across entire application.\n    This can be achieved with ``-D`` compiler option.\n"
  },
  {
    "path": "docs/index.rst",
    "content": "LwESP |version| documentation\n=============================\n\nWelcome to the documentation for version |version|.\n\nLwESP is generic, platform independent, ESP-AT parser library to communicate with *ESP8266* or *ESP32* WiFi-based microcontrollers from *Espressif systems* using official AT Commands set running on ESP device.\nIts objective is to run on master system, while Espressif device runs official AT commands firmware developed and maintained by *Espressif systems*.\n\n.. image:: static/images/logo.svg\n    :align: center\n\n.. rst-class:: center\n.. rst-class:: index_links\n\n\t:ref:`download_library` :ref:`getting_started` `Open Github <https://github.com/MaJerle/lwesp>`_ `Donate <https://paypal.me/tilz0R>`_\n\nFeatures\n^^^^^^^^\n\n* Supports latest ESP32, ESP32-C2, ESP32-C3, ESP32-C6 & ESP8266 AT software from Espressif system\n* Platform independent and easy to port, written in C99\n\n  * Library is developed under Win32 platform\n  * Provided examples for ARM Cortex-M or Win32 platforms\n\n* Allows different configurations to optimize user requirements\n* Optimized for systems with operating systems (or RTOS)\n\n  * Currently only OS mode is supported\n  * ``2`` different threads to process user inputs and received data\n\n    * Producer thread to collect user commands from application threads and to start command execution\n    * Process thread to process received data from *ESP* device\n\n* Allows sequential API for connections in client and server mode\n* Includes several applications built on top of library\n\n  * HTTP server with dynamic files (file system) support\n  * MQTT client for MQTT connection\n  * MQTT client Cayenne API for Cayenne MQTT server\n\n* Embeds other AT features, such as WPS\n* User friendly MIT license\n\nRequirements\n^^^^^^^^^^^^\n\n* C compiler\n* *ESP8266* or *ESP32* device with running AT-Commands firmware\n\nContribute\n^^^^^^^^^^\n\nFresh contributions are always welcome. Simple instructions to proceed:\n\n#. Fork Github repository\n#. Respect `C style & coding rules <https://github.com/MaJerle/c-code-style>`_ used by the library\n#. Create a pull request to ``develop`` branch with new features or bug fixes\n\nAlternatively you may:\n\n#. Report a bug\n#. Ask for a feature request\n\nLicense\n^^^^^^^\n\n.. literalinclude:: ../LICENSE\n\nTable of contents\n^^^^^^^^^^^^^^^^^\n\n.. toctree::\n    :maxdepth: 2\n    :caption: Contents\n\n    self\n    get-started/index\n    user-manual/index\n    api-reference/index\n    examples/index\n    firmware-update/index\n    changelog/index\n    authors/index\n\n.. toctree::\n    :maxdepth: 2\n    :caption: Other projects\n    :hidden:\n\n    LwBTN - Button manager <https://github.com/MaJerle/lwbtn>\n    LwDTC - DateTimeCron <https://github.com/MaJerle/lwdtc>\n    LwESP - ESP-AT library <https://github.com/MaJerle/lwesp>\n    LwEVT - Event manager <https://github.com/MaJerle/lwevt>\n    LwGPS - GPS NMEA parser <https://github.com/MaJerle/lwgps>\n    LwCELL - Cellular modem host AT library <https://github.com/MaJerle/lwcell>\n    LwJSON - JSON parser <https://github.com/MaJerle/lwjson>\n    LwMEM - Memory manager <https://github.com/MaJerle/lwmem>\n    LwOW - OneWire with UART <https://github.com/MaJerle/lwow>\n    LwPKT - Packet protocol <https://github.com/MaJerle/lwpkt>\n    LwPRINTF - Printf <https://github.com/MaJerle/lwprintf>\n    LwRB - Ring buffer <https://github.com/MaJerle/lwrb>\n    LwSHELL - Shell <https://github.com/MaJerle/lwshell>\n    LwUTIL - Utility functions <https://github.com/MaJerle/lwutil>\n    LwWDG - RTOS task watchdog <https://github.com/MaJerle/lwwdg>"
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    "content": "/**\n * @license\n * Copyright 2019 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n:root {\n  --heading-color: red;\n  --duration: 0.5s;\n  --timing: ease;\n}\n\n*,\n::before,\n::after {\n  box-sizing: border-box;\n}\n\nbody {\n  margin: 0;\n  transition:\n    color var(--duration) var(--timing),\n    background-color var(--duration) var(--timing);\n  font-family: sans-serif;\n  font-size: 12pt;\n  background-color: var(--background-color);\n  color: var(--text-color);\n  display: flex;\n  justify-content: center;\n}\n\nmain {\n  margin: 1rem;\n  max-width: 30rem;\n  position: relative;\n}\n\nh1 {\n  color: var(--heading-color);\n  text-shadow: 0.1rem 0.1rem 0.1rem var(--shadow-color);\n  transition: text-shadow var(--duration) var(--timing);\n}\n\nimg {\n  max-width: 100%;\n  height: auto;\n  transition: filter var(--duration) var(--timing);\n}\n\np {\n  line-height: 1.5;\n  word-wrap: break-word;\n  overflow-wrap: break-word;\n  hyphens: auto;\n}\n\nfieldset {\n  border: solid 0.1rem;\n  box-shadow: 0.1rem 0.1rem 0.1rem var(--shadow-color);\n  transition: box-shadow var(--duration) var(--timing);\n}\n\ndiv {\n  padding: 0.5rem;\n}\n\naside {\n  position: absolute;\n  right: 0;\n  padding: 0.5rem;\n}\n\naside:nth-of-type(1) {\n  top: 0;\n}\n\naside:nth-of-type(2) {\n  top: 3rem;\n}\n\naside:nth-of-type(3) {\n  top: 7rem;\n}\n\naside:nth-of-type(4) {\n  top: 12rem;\n}\n\n#content select,\n#content button,\n#content input[type=\"text\"],\n#content input[type=\"search\"] {\n  width: 15rem;\n}\n\ndark-mode-toggle {\n  --dark-mode-toggle-remember-icon-checked: url(\"checked.svg\");\n  --dark-mode-toggle-remember-icon-unchecked: url(\"unchecked.svg\");\n  --dark-mode-toggle-remember-font: 0.75rem \"Helvetica\";\n  --dark-mode-toggle-legend-font: bold 0.85rem \"Helvetica\";\n  --dark-mode-toggle-label-font: 0.85rem \"Helvetica\";\n  --dark-mode-toggle-color: var(--text-color);\n  --dark-mode-toggle-background-color: none;\n\n  margin-bottom: 1.5rem;\n}\n\n#dark-mode-toggle-1 {\n  --dark-mode-toggle-dark-icon: url(\"sun.png\");\n  --dark-mode-toggle-light-icon: url(\"moon.png\");\n}\n\n#dark-mode-toggle-2 {\n  --dark-mode-toggle-dark-icon: url(\"sun.svg\");\n  --dark-mode-toggle-light-icon: url(\"moon.svg\");\n  --dark-mode-toggle-icon-size: 2rem;\n  --dark-mode-toggle-icon-filter: invert(100%);\n}\n\n#dark-mode-toggle-3,\n#dark-mode-toggle-4 {\n  --dark-mode-toggle-dark-icon: url(\"moon.png\");\n  --dark-mode-toggle-light-icon: url(\"sun.png\");\n}\n\n#dark-mode-toggle-3 {\n  --dark-mode-toggle-remember-filter: invert(100%);\n}\n\n#dark-mode-toggle-4 {\n  --dark-mode-toggle-active-mode-background-color: var(--accent-color);\n  --dark-mode-toggle-remember-filter: invert(100%);\n}\n"
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    "content": "/**\n * Copyright 2019 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n// @license © 2019 Google LLC. Licensed under the Apache License, Version 2.0.\nconst doc = document;\nconst store = localStorage;\nconst PREFERS_COLOR_SCHEME = 'prefers-color-scheme';\nconst MEDIA = 'media';\nconst LIGHT = 'light';\nconst DARK = 'dark';\nconst MQ_DARK = `(${PREFERS_COLOR_SCHEME}:${DARK})`;\nconst MQ_LIGHT = `(${PREFERS_COLOR_SCHEME}:${LIGHT})`;\nconst LINK_REL_STYLESHEET = 'link[rel=stylesheet]';\nconst REMEMBER = 'remember';\nconst LEGEND = 'legend';\nconst TOGGLE = 'toggle';\nconst SWITCH = 'switch';\nconst APPEARANCE = 'appearance';\nconst PERMANENT = 'permanent';\nconst MODE = 'mode';\nconst COLOR_SCHEME_CHANGE = 'colorschemechange';\nconst PERMANENT_COLOR_SCHEME = 'permanentcolorscheme';\nconst ALL = 'all';\nconst NOT_ALL = 'not all';\nconst NAME = 'dark-mode-toggle';\nconst DEFAULT_URL = 'https://googlechromelabs.github.io/dark-mode-toggle/demo/';\n\n// See https://html.spec.whatwg.org/multipage/common-dom-interfaces.html ↵\n// #reflecting-content-attributes-in-idl-attributes.\nconst installStringReflection = (obj, attrName, propName = attrName) => {\n  Object.defineProperty(obj, propName, {\n    enumerable: true,\n    get() {\n      const value = this.getAttribute(attrName);\n      return value === null ? '' : value;\n    },\n    set(v) {\n      this.setAttribute(attrName, v);\n    },\n  });\n};\n\nconst installBoolReflection = (obj, attrName, propName = attrName) => {\n  Object.defineProperty(obj, propName, {\n    enumerable: true,\n    get() {\n      return this.hasAttribute(attrName);\n    },\n    set(v) {\n      if (v) {\n        this.setAttribute(attrName, '');\n      } else {\n        this.removeAttribute(attrName);\n      }\n    },\n  });\n};\n\nconst template = doc.createElement('template');\n// ⚠️ Note: this is a minified version of `src/template-contents.tpl`.\n// Compress the CSS with https://cssminifier.com/, then paste it here.\n// eslint-disable-next-line max-len\ntemplate.innerHTML = `<style>*,::after,::before{box-sizing:border-box}:host{contain:content;display:block}:host([hidden]){display:none}form{background-color:var(--${NAME}-background-color,transparent);color:var(--${NAME}-color,inherit);padding:0}fieldset{border:none;margin:0;padding-block:.25rem;padding-inline:.25rem}legend{font:var(--${NAME}-legend-font,inherit);padding:0}input,label{cursor:pointer}label{white-space:nowrap}input{opacity:0;position:absolute;pointer-events:none}input:focus-visible+label{outline:#e59700 auto 2px;outline:-webkit-focus-ring-color auto 5px}label:not(:empty)::before{margin-inline-end:.5rem;}label::before{content:\"\";display:inline-block;background-size:var(--${NAME}-icon-size,1rem);background-repeat:no-repeat;height:var(--${NAME}-icon-size,1rem);width:var(--${NAME}-icon-size,1rem);vertical-align:middle;}[part=lightLabel]::before{background-image:var(--${NAME}-light-icon, url(\"${DEFAULT_URL}sun.png\"))}[part=darkLabel]::before{filter:var(--${NAME}-icon-filter, none);background-image:var(--${NAME}-dark-icon, url(\"${DEFAULT_URL}moon.png\"))}[part=toggleLabel]::before{background-image:var(--${NAME}-checkbox-icon,none)}[part=permanentLabel]::before{background-image:var(--${NAME}-remember-icon-unchecked, url(\"${DEFAULT_URL}unchecked.svg\"))}[part=darkLabel],[part=lightLabel],[part=toggleLabel]{font:var(--${NAME}-label-font,inherit)}[part=darkLabel]:empty,[part=lightLabel]:empty,[part=toggleLabel]:empty{font-size:0;padding:0}[part=permanentLabel]{font:var(--${NAME}-remember-font,inherit)}input:checked+[part=permanentLabel]::before{background-image:var(--${NAME}-remember-icon-checked, url(\"${DEFAULT_URL}checked.svg\"))}input:checked+[part=darkLabel],input:checked+[part=lightLabel]{background-color:var(--${NAME}-active-mode-background-color,transparent)}input:checked+[part=darkLabel]::before,input:checked+[part=lightLabel]::before{background-color:var(--${NAME}-active-mode-background-color,transparent)}input:checked+[part=toggleLabel]::before{filter:var(--${NAME}-icon-filter, none)}input:checked+[part=toggleLabel]+aside [part=permanentLabel]::before{filter:var(--${NAME}-remember-filter, invert(100%))}aside{visibility:hidden;margin-block-start:.15rem}[part=darkLabel]:focus-visible~aside,[part=lightLabel]:focus-visible~aside,[part=toggleLabel]:focus-visible~aside{visibility:visible;transition:visibility 0s}aside [part=permanentLabel]:empty{display:none}@media (hover:hover){aside{transition:visibility 3s}aside:hover{visibility:visible}[part=darkLabel]:hover~aside,[part=lightLabel]:hover~aside,[part=toggleLabel]:hover~aside{visibility:visible;transition:visibility 0s}}</style><form part=form><fieldset part=fieldset><legend part=legend></legend><input part=lightRadio id=l name=mode type=radio><label part=lightLabel for=l></label><input part=darkRadio id=d name=mode type=radio><label part=darkLabel for=d></label><input part=toggleCheckbox id=t type=checkbox><label part=toggleLabel for=t></label><aside part=aside><input part=permanentCheckbox id=p type=checkbox><label part=permanentLabel for=p></label></aside></fieldset></form>`;\n\nexport class DarkModeToggle extends HTMLElement {\n  static get observedAttributes() {\n    return [MODE, APPEARANCE, PERMANENT, LEGEND, LIGHT, DARK, REMEMBER];\n  }\n\n  constructor() {\n    super();\n\n    installStringReflection(this, MODE);\n    installStringReflection(this, APPEARANCE);\n    installStringReflection(this, LEGEND);\n    installStringReflection(this, LIGHT);\n    installStringReflection(this, DARK);\n    installStringReflection(this, REMEMBER);\n\n    installBoolReflection(this, PERMANENT);\n\n    this._darkCSS = null;\n    this._lightCSS = null;\n\n    doc.addEventListener(COLOR_SCHEME_CHANGE, (event) => {\n      this.mode = event.detail.colorScheme;\n      this._updateRadios();\n      this._updateCheckbox();\n    });\n\n    doc.addEventListener(PERMANENT_COLOR_SCHEME, (event) => {\n      this.permanent = event.detail.permanent;\n      this._permanentCheckbox.checked = this.permanent;\n    });\n\n    this._initializeDOM();\n  }\n\n  _initializeDOM() {\n    const shadowRoot = this.attachShadow({mode: 'open'});\n    shadowRoot.appendChild(template.content.cloneNode(true));\n\n    // We need to support `media=\"(prefers-color-scheme: dark)\"` (with space)\n    // and `media=\"(prefers-color-scheme:dark)\"` (without space)\n    this._darkCSS = doc.querySelectorAll(`${LINK_REL_STYLESHEET}[${MEDIA}*=${PREFERS_COLOR_SCHEME}][${MEDIA}*=\"${DARK}\"]`);\n    this._lightCSS = doc.querySelectorAll(`${LINK_REL_STYLESHEET}[${MEDIA}*=${PREFERS_COLOR_SCHEME}][${MEDIA}*=\"${LIGHT}\"]`);\n\n    // Get DOM references.\n    this._lightRadio = shadowRoot.querySelector('[part=lightRadio]');\n    this._lightLabel = shadowRoot.querySelector('[part=lightLabel]');\n    this._darkRadio = shadowRoot.querySelector('[part=darkRadio]');\n    this._darkLabel = shadowRoot.querySelector('[part=darkLabel]');\n    this._darkCheckbox = shadowRoot.querySelector('[part=toggleCheckbox]');\n    this._checkboxLabel = shadowRoot.querySelector('[part=toggleLabel]');\n    this._legendLabel = shadowRoot.querySelector('legend');\n    this._permanentAside = shadowRoot.querySelector('aside');\n    this._permanentCheckbox =\n        shadowRoot.querySelector('[part=permanentCheckbox]');\n    this._permanentLabel = shadowRoot.querySelector('[part=permanentLabel]');\n\n    // Does the browser support native `prefers-color-scheme`?\n    const hasNativePrefersColorScheme =\n        matchMedia(MQ_DARK).media !== NOT_ALL;\n    // Listen to `prefers-color-scheme` changes.\n    if (hasNativePrefersColorScheme) {\n      matchMedia(MQ_DARK).addListener(({matches}) => {\n        this.mode = matches ? DARK : LIGHT;\n        this._dispatchEvent(COLOR_SCHEME_CHANGE, {colorScheme: this.mode});\n      });\n    }\n    // Set initial state, giving preference to a remembered value, then the\n    // native value (if supported), and eventually defaulting to a light\n    // experience.\n    const rememberedValue = store.getItem(NAME);\n    if (rememberedValue && [DARK, LIGHT].includes(rememberedValue)) {\n      this.mode = rememberedValue;\n      this._permanentCheckbox.checked = true;\n      this.permanent = true;\n    } else if (hasNativePrefersColorScheme) {\n      this.mode = matchMedia(MQ_LIGHT).matches ? LIGHT : DARK;\n    }\n    if (!this.mode) {\n      this.mode = LIGHT;\n    }\n    if (this.permanent && !rememberedValue) {\n      store.setItem(NAME, this.mode);\n    }\n\n    // Default to toggle appearance.\n    if (!this.appearance) {\n      this.appearance = TOGGLE;\n    }\n\n    // Update the appearance to either of toggle or switch.\n    this._updateAppearance();\n\n    // Update the radios\n    this._updateRadios();\n\n    // Make the checkbox reflect the state of the radios\n    this._updateCheckbox();\n\n    // Synchronize the behavior of the radio and the checkbox.\n    [this._lightRadio, this._darkRadio].forEach((input) => {\n      input.addEventListener('change', () => {\n        this.mode = this._lightRadio.checked ? LIGHT : DARK;\n        this._updateCheckbox();\n        this._dispatchEvent(COLOR_SCHEME_CHANGE, {colorScheme: this.mode});\n      });\n    });\n    this._darkCheckbox.addEventListener('change', () => {\n      this.mode = this._darkCheckbox.checked ? DARK : LIGHT;\n      this._updateRadios();\n      this._dispatchEvent(COLOR_SCHEME_CHANGE, {colorScheme: this.mode});\n    });\n\n    // Make remembering the last mode optional\n    this._permanentCheckbox.addEventListener('change', () => {\n      this.permanent = this._permanentCheckbox.checked;\n      this._dispatchEvent(PERMANENT_COLOR_SCHEME, {\n        permanent: this.permanent,\n      });\n    });\n\n    // Finally update the mode and let the world know what's going on\n    this._updateMode();\n    this._dispatchEvent(COLOR_SCHEME_CHANGE, {colorScheme: this.mode});\n    this._dispatchEvent(PERMANENT_COLOR_SCHEME, {\n      permanent: this.permanent,\n    });\n  }\n\n  attributeChangedCallback(name, oldValue, newValue) {\n    if (name === MODE) {\n      if (![LIGHT, DARK].includes(newValue)) {\n        throw new RangeError(`Allowed values: \"${LIGHT}\" and \"${DARK}\".`);\n      }\n      // Only show the dialog programmatically on devices not capable of hover\n      // and only if there is a label\n      if (matchMedia('(hover:none)').matches && this.remember) {\n        this._showPermanentAside();\n      }\n      if (this.permanent) {\n        store.setItem(NAME, this.mode);\n      }\n      this._updateRadios();\n      this._updateCheckbox();\n      this._updateMode();\n    } else if (name === APPEARANCE) {\n      if (![TOGGLE, SWITCH].includes(newValue)) {\n        throw new RangeError(`Allowed values: \"${TOGGLE}\" and \"${SWITCH}\".`);\n      }\n      this._updateAppearance();\n    } else if (name === PERMANENT) {\n      if (this.permanent) {\n        store.setItem(NAME, this.mode);\n      } else {\n        store.removeItem(NAME);\n      }\n      this._permanentCheckbox.checked = this.permanent;\n    } else if (name === LEGEND) {\n      this._legendLabel.textContent = newValue;\n    } else if (name === REMEMBER) {\n      this._permanentLabel.textContent = newValue;\n    } else if (name === LIGHT) {\n      this._lightLabel.textContent = newValue;\n      if (this.mode === LIGHT) {\n        this._checkboxLabel.textContent = newValue;\n      }\n    } else if (name === DARK) {\n      this._darkLabel.textContent = newValue;\n      if (this.mode === DARK) {\n        this._checkboxLabel.textContent = newValue;\n      }\n    }\n  }\n\n  _dispatchEvent(type, value) {\n    this.dispatchEvent(new CustomEvent(type, {\n      bubbles: true,\n      composed: true,\n      detail: value,\n    }));\n  }\n\n  _updateAppearance() {\n    // Hide or show the light-related affordances dependent on the appearance,\n    // which can be \"switch\" or \"toggle\".\n    const appearAsToggle = this.appearance === TOGGLE;\n    this._lightRadio.hidden = appearAsToggle;\n    this._lightLabel.hidden = appearAsToggle;\n    this._darkRadio.hidden = appearAsToggle;\n    this._darkLabel.hidden = appearAsToggle;\n    this._darkCheckbox.hidden = !appearAsToggle;\n    this._checkboxLabel.hidden = !appearAsToggle;\n  }\n\n  _updateRadios() {\n    if (this.mode === LIGHT) {\n      this._lightRadio.checked = true;\n    } else {\n      this._darkRadio.checked = true;\n    }\n  }\n\n  _updateCheckbox() {\n    if (this.mode === LIGHT) {\n      this._checkboxLabel.style.setProperty(`--${NAME}-checkbox-icon`,\n          `var(--${NAME}-light-icon,url(\"${DEFAULT_URL}moon.png\"))`);\n      this._checkboxLabel.textContent = this.light;\n      if (!this.light) {\n        this._checkboxLabel.ariaLabel = DARK;\n      }\n      this._darkCheckbox.checked = false;\n    } else {\n      this._checkboxLabel.style.setProperty(`--${NAME}-checkbox-icon`,\n          `var(--${NAME}-dark-icon,url(\"${DEFAULT_URL}sun.png\"))`);\n      this._checkboxLabel.textContent = this.dark;\n      if (!this.dark) {\n        this._checkboxLabel.ariaLabel = LIGHT;\n      }\n      this._darkCheckbox.checked = true;\n    }\n  }\n\n  _updateMode() {\n    if (this.mode === LIGHT) {\n      this._lightCSS.forEach((link) => {\n        link.media = ALL;\n        link.disabled = false;\n      });\n      this._darkCSS.forEach((link) => {\n        link.media = NOT_ALL;\n        link.disabled = true;\n      });\n    } else {\n      this._darkCSS.forEach((link) => {\n        link.media = ALL;\n        link.disabled = false;\n      });\n      this._lightCSS.forEach((link) => {\n        link.media = NOT_ALL;\n        link.disabled = true;\n      });\n    }\n  }\n\n  _showPermanentAside() {\n    this._permanentAside.style.visibility = 'visible';\n    setTimeout(() => {\n      this._permanentAside.style.visibility = 'hidden';\n    }, 3000);\n  }\n}\n\ncustomElements.define(NAME, DarkModeToggle);"
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    "content": "/**\n * @license\n * Copyright 2019 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n:root {\n  color-scheme: dark; /* stylelint-disable-line property-no-unknown */\n\n  --background-color: rgb(15 15 15);\n  --text-color: rgb(240 240 240);\n  --shadow-color: rgb(240 240 240 / 50%);\n  --accent-color: rgb(0 0 240 / 50%);\n}\n\nimg {\n  filter: grayscale(50%);\n}\n\n.icon {\n  filter: invert(100%);\n}\n\na {\n  color: yellow;\n}\n"
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    "content": "/**\n * @license\n * Copyright 2019 Google LLC\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n *     https://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n:root {\n  color-scheme: light; /* stylelint-disable-line property-no-unknown */\n\n  --background-color: rgb(240 240 240);\n  --text-color: rgb(15 15 15);\n  --shadow-color: rgb(15 15 15 / 50%);\n  --accent-color: rgb(240 0 0 / 50%);\n}\n"
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    "content": "<mxfile modified=\"2019-12-14T11:20:01.702Z\" host=\"Electron\" agent=\"Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/12.3.2 Chrome/78.0.3904.113 Electron/7.1.2 Safari/537.36\" etag=\"E2o49qgMZAAlEAuQ1TzI\" version=\"12.3.2\" type=\"device\" pages=\"1\"><diagram id=\"c7558073-3199-34d8-9f00-42111426c3f3\" name=\"Page-1\">7VxbU+O4Ev41eYSyLd/yCIHZZc9cOEAVZ55OKbaSeHEsr61MyPz61c1XKZchdmJqgCqwWvKtu7/uVrfkEZgsX//IYLr4gkMUjywjfB2Bm5FlWSYA9B+jbATFtExbUOZZFEpaRXiMfiJJNCR1FYUobwwkGMckSpvEACcJCkiDBrMMr5vDZjhu3jWFc6QQHgMYq9TnKCQLSTXdcdXxJ4rmC3lr3/JExxQGL/MMrxJ5v5EFZvxHdC9hcS35ovkChnhdI4HbEZhkGBNxtHydoJgxt2CbOO/Tlt7yuTOUkENOuPnrE0lnX27Rz8ieX0Tmf73p1QXwxWV+wHiFivfgT0s2BYfWi4igxxQGrL2majAC1wuyjGnLpIezKI4nOMYZHw2QGTrIo/ScZPgF1XrGrgegS3vkLVFG0OvWlzFLFlHdQ3iJSLahQ+QJji+5KtXOG5uXjqCsKykCW45a1ARYngql5szLq1fcoweSgXpmOnZomTMbWoZnB844vBh7XTMyhMifBTpGuoGPprOSkQrXNLzdykjbaDLSLNS1zkZLw0bX7oWN467ZSAFpBVo2hu7Uddxu2Oi5b2Rjyf9O2Wga4Gy4PoqPjt3ko2+558W1adgKJ6/u7z/fTa6e7r59pR1Pfz7cXlGyYSocpi9NmkzNUB79hFM+wKDtFEcJ4c/rXI+cG0qBK4Jz4SXZCTCO5gk9DihPEWX4NeNlRN3XlewgmMktp2KMkvkTa9xc2Ex8OCHS21pG0ZaP5nQhKf8QSVmuRlKgA0FZDvCoCTKAbQPbM8cXqn6jkDp62cQZWeA5TmB8W1GvufdGoZRFTUzoNSL/Y2T6SqL1vehJ6IPWuljzu7zA34iQjeQ5EyMlVff9jLlszKZoTEtjsfwA6S3W1Hdsxyh7injF2oW9HK+yAG3VbmlvCczmiGxhrbwS4+dOzchQDEn0oxlYdYxG1T88w4hQSoLWLOpCec4CPhZEshiNHcGQyZiGhhlesmaaxhRAJMIJG7bIEAxzerTKKYDo/6v7OzZ4lQRsSK6oVVNp9hnRlqi78NhWy9V4qquxfK2r6UMiRRxfk8gjIg1RBHi5hAkTAdmkXCK8EZGcd2bUKKY4CQX7oyRdsdNDSCBrzrhsA3Yx+ahDEobjNYUxtrVWUCcOtx9xaNxVHGOq74jLZIn5408p6YVPl7JCVKhk+sB57PsH87gnlXc+fM0bfE2hmnVfs92eDMHbWK4CpvsMh6tAmCrhO/qM+mI0IwOK+WzPaboeoLoeU4fDLiI+jXjUOTcVD3MVv6l8fGDsl8/4dPJRk0sTKhHuiUS4lqMlTBc4Y5SR5caMmVN6MGcHtLOg0XuX5NJr5ZskWGQ4oaKTwdwUkTVC7CitwVREG7qwr+yU3pAHktFyicKIPmUcDz/eoOZS5wxLwdeFPO5AyPokojrz/VV/qPVdGh+n85s1r1n50JvXWtfNpmjs8Ki8UZ3GW8V53XnNllt7gxstuL3bjQrsHeE1+alXWQY3tQHSMFZXvmeESj3dohxQqKfhFOpZKZi4aKVu5dMdoYHHz/6P0EDzQwP1YjlaCd/ue4pnrPmeu7yY+DC/AD6pxn2Bl9NVfhbD7hb1phI52nyab6p2vZ+JJLCPhtRvOckxDrHOYEApNaBG0d+RmvZSo+YmNxOcoBbrJWlvCnsZhSFXHx3smirVB/KsNvKArpZoa5Bn9RZRHQ++YyIqFaSd+zMVcL8O2q78mW0d6s/ss6G0eEY18f3GOVSVH2czIR7kzWFE50b04Yw5z+DSafEqZgcyc17lccXfNEOM18XESczKGvOsoc+eLPPg2ZPZT6HWBh9u9g2QLVILu91sAZrTu1mlhvYRTe0X87bC487iJBiMiNUZx2eRVlITVaqdpkP+v9VYu3DJjGMyzVNh00uDvyvjlaq50OFXMy1NyrK30o4iQvcDpb+OUnAASp3BoFRdGPWIOFxkwZnHRVdPjA+U72VYU8Y+LDzKV8FCPJcGygUhKgjsYtd/fHmoYTtqD67j/XL4IB0fCFKnA5C+pwDpbBh0NBgcDOScbVMXAa3OnGFrSnNZXjjbis2nRcRAzP+sF4hfRuM3hQFAfGjCbwP56qBLPaYHDl/gntDH9rNWogbeGl7fDXxVtNpdo/VN9Rvbbxb4HdNoyfq44o15fJ3msPrLO9cGdxDa4IJ+tUFNaT2gf1YoL11D23yXxZua0yg7iwhtYIUdp7XBwtYs1yx3C9SNbxfL2c0zTGjscQNxlwbwC8I9yiL6DqwIMEwoalaomZ0nGDqxzK7f2u3VGu+45q7xR2NXXWYqVv1WOeIyewyDAGdyda8yu8oJJBSZfFpFOYhgLtapFmuHD89o74kLV0mx5lW/EmjgMZujidn6y1ObZ0hX2n7Lbtjvxmy4gzUbbRd+brOhLqh9KEFfmY4K/uWCddGRYBLNWHOVo4yDgbBETADjmG3HHVX7NqrOwg4NDODtWtRpAf6ea/71VbNWF6a2JQnbVyWh23DYRfVf3c70Ff+mYnDN84nB1GSFqTVnhhH/YJZmYMbDHjd55RkHVrE7qZoYCj8+MrKmp4kB/K5jgIP1WbXvMuUqqxxyRUctEh+Yhnut7cUn3eVYZCY+NLyu4ZolF8W4M2i4urdE7v3hdwsQvVko9f2S/r+bNeLKSGw9pQzH7KrzGE8hO9hZ2Xu++8S2Bk++ff16O3m6vTlkHqqvcFDKRF5Gf5GJJtidbmSoK6bS+qC3vnuFvffTgr1uDpeoNo6GBYQH1WwmzKsaWyoxI+v67v6g92TzeLREfC5RBt6lFBJE1jh7UeyP/KiPqKQM3AKVlmWfBeoicWe9p/VCJ0uU69YDnW/9j7re53mBtKt7lLLjt/8cuhiARaB1aCqDy5G3Dw/fHrZAVXOrtjGsoVXMtXXTcT6SlT4pH1spu26ruNS2YbZBMNVstxUjmPGOEsr5odsN4JzSbryziUybWfYpS9M71ni3UlRklSWjWkpb6Gi/K52P+z5ae6UzcPQfTbBU1naxGVjPWt030lpm7aFgMZ41bBC3PC8JXidq5Q9ykYiVHKnIZ/a9KqPt8xz2q/N5Lv+RV6jRxU83wrbbIDJVEJm6DzH1BiJw/KqPj/0rW6KgHTstT7GF5U1lCM93m+bIau8L3n8KAHtPMc09p/Sz+1jznYPnLCLNQiZ3Gdpw5p8V6ieMOcqoeO3PTG370oBmX1x/XxpQ60fvJl/ehUxs+7L1BZYhbFZUixhbvpCoptUG/oXEo6TlthCk/0ZtV19IpM3qW8LCslVfbAa3/wI=</diagram></mxfile>"
  },
  {
    "path": "docs/user-manual/architecture.rst",
    "content": ".. _um_arch:\n\nArchitecture\n============\n\nArchitecture of the library consists of ``4`` layers.\n\n.. figure:: ../static/images/system_structure.svg\n\t:align: center\n\t:alt: ESP-AT layer architecture overview\n\n\tESP-AT layer architecture overview\n\nApplication layer\n^^^^^^^^^^^^^^^^^\n\n*User layer* is the highest layer of the final application.\nThis is the part where API functions are called to execute some command.\n\nMiddleware layer\n^^^^^^^^^^^^^^^^\n\nMiddleware part is actively developed and shall not be modified by customer by any means.\nIf there is a necessity to do it, often it means that developer of the application uses it wrongly.\nThis part is platform independent and does not use any specific compiler features for proper operation.\n\n.. note::\n\tThere is no compiler specific features implemented in this layer.\n\nSystem & low-level layer\n^^^^^^^^^^^^^^^^^^^^^^^^\n\nApplication needs to fully implement this part and resolve it with care.\nFunctions are related to actual implementation with *ESP* device and are highly\narchitecture oriented. Some examples for `WIN32` and `ARM Cortex-M` are included with library.\n\n.. tip::\n\tCheck :ref:`um_porting_guide` for detailed instructions and examples.\n\nSystem functions\n****************\n\nSystem functions are bridge between operating system running on embedded system and ESP-AT middleware.\nFunctions need to provide:\n\n* Thread management\n* Binary semaphore management\n* Recursive mutex management\n* Message queue management\n* Current time status information\n\n.. tip::\n\tSystem function prototypes are available in :ref:`api_lwesp_sys` section.\n\nLow-level implementation\n************************\n\nLow-Level, or *LWESP_LL*, is part, dedicated for communication between *ESP-AT* middleware and *ESP* physical device.\nApplication needs to implement output function to send necessary *AT command* instruction aswell as implement\n*input module* to send received data from *ESP* device to *ESP-AT* middleware.\n\nApplication must also assure memory assignment for :ref:`api_lwesp_mem` when default allocation is used.\n\n.. tip::\n\tLow level, input module & memory function prototypes are available in\n\t:ref:`api_lwesp_ll`, :ref:`api_lwesp_input` and :ref:`api_lwesp_mem` respectfully.\n\nESP physical device\n^^^^^^^^^^^^^^^^^^^\n\n .. toctree::\n    :maxdepth: 2"
  },
  {
    "path": "docs/user-manual/blocking-nonblocking.rst",
    "content": ".. _um_blocking_nonblocking:\n\nBlocking or non-blocking API calls\n==================================\n\nAPI functions often allow application to set ``blocking`` parameter indicating if function shall be blocking or non-blocking.\n\nBlocking mode\n^^^^^^^^^^^^^\n\nWhen the function is called in blocking mode ``blocking = 1``, application thread gets suspended until response from *ESP* device is received.\nIf there is a queue of multiple commands, thread may wait a while before receiving data.\n\nWhen API function returns, application has valid response data and can react immediately.\n\n* Linear programming model may be used\n* Application may use multiple threads for real-time execution to prevent system stalling when running function call\n\n.. warning::\n\tDue to internal architecture, it is not allowed to call API functions in *blocking mode* from events or callbacks.\n\tAny attempt to do so will result in function returning error.\n\nExample code:\n\n.. literalinclude:: ../examples_src/command_blocking.c\n    :language: c\n    :linenos:\n    :caption: Blocking command example\n\nNon-blocking mode\n^^^^^^^^^^^^^^^^^\n\nIf the API function is called in non-blocking mode, function will return immediately with status indicating if command request has been successfully sent to internal command queue.\nResponse has to be processed in event callback function.\n\n.. warning::\n\tDue to internal architecture, it is only allowed to call API functions in *non-blocking mode* from events or callbacks.\n\tAny attempt not to do so will result in function returning error.\n\nExample code:\n\n.. literalinclude:: ../examples_src/command_nonblocking.c\n    :language: c\n    :linenos:\n    :caption: Non-blocking command example\n\n.. warning::\n\tWhen using non-blocking API calls, do not use local variables as parameter. \n\tThis may introduce *undefined behavior* and *memory corruption* if application function returns before command is executed.\n\nExample of a bad code:\n\n.. literalinclude:: ../examples_src/command_nonblocking_bad.c\n    :language: c\n    :linenos:\n    :caption: Example of bad usage of non-blocking command\n\n.. toctree::\n    :maxdepth: 2\n    :glob:"
  },
  {
    "path": "docs/user-manual/events-cb-fn.rst",
    "content": ".. _um_events_cb_fn:\n\nEvents and callback functions\n=============================\n\nLibrary uses events to notify application layer for (possible, but not limited to) unexpected events.\nThis concept is used aswell for commands with longer executing time, such as *scanning access points* or when application starts new connection as client mode.\n\nThere are ``3`` types of events/callbacks available:\n\n* *Global event* callback function, assigned when initializing library\n* *Connection specific event* callback function, to process only events related to connection, such as *connection error*, *data send*, *data receive*, *connection closed*\n* *API function* call based event callback function\n\nEvery callback is always called from protected area of middleware (when exclusing access is granted to single thread only),\nand it can be called from one of these ``3`` threads:\n\n- *Producing thread*\n- *Processing thread*\n- *Input thread*, when :c:macro:`LWESP_CFG_INPUT_USE_PROCESS` is enabled and :cpp:func:`lwesp_input_process` function is called\n\n.. tip::\n    Check :ref:`um_inter_thread_comm` for more details about *Producing* and *Processing* thread.\n\nGlobal event callback\n^^^^^^^^^^^^^^^^^^^^^\n\nGlobal event callback function is assigned at library initialization.\nIt is used by the application to receive any kind of event, except the one related to connection:\n\n* ESP station successfully connected to access point\n* ESP physical device reset has been detected\n* Restore operation finished\n* New station has connected to access point\n* and many more..\n\n.. tip::\n    Check :ref:`api_lwesp_evt` section for different kind of events\n\nBy default, global event function is single function.\nIf the application tries to split different events with different callback functions,\nit is possible to do so by using :cpp:func:`lwesp_evt_register` function to register a new,\ncustom, event function.\n\n.. tip::\n    Implementation of :ref:`api_app_netconn` leverages :cpp:func:`lwesp_evt_register` to\n    receive event when station disconnected from wifi access point.\n    Check its source file for actual implementation.\n\n.. literalinclude:: ../../lwesp/src/api/lwesp_netconn.c\n    :language: c\n    :linenos:\n    :caption: Netconn API module actual implementation\n\nConnection specific event\n^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThis events are subset of global event callback.\nThey work exactly the same way as global, but only receive events related to connections.\n\n.. tip::\n    Connection related events start with ``LWESP_EVT_CONN_*``, such as :c:member:`LWESP_EVT_CONN_RECV`.\n    Check :ref:`api_lwesp_evt` for list of all connection events.\n\nConnection events callback function is set for ``2`` cases:\n\n* Each client (when application starts connection) sets event callback function when trying to connect with :cpp:func:`lwesp_conn_start` function\n* Application sets global event callback function when enabling server mode with :cpp:func:`lwesp_set_server` function\n\n.. literalinclude:: ../../snippets/client.c\n    :language: c\n    :linenos:\n    :caption: An example of client with its dedicated event callback function\n\nAPI call event\n^^^^^^^^^^^^^^\n\nAPI function call event function is special type of event and is linked to command execution.\nIt is especially useful when dealing with non-blocking commands to understand when specific\ncommand execution finished and when next operation could start.\n\nEvery API function, which directly operates with AT command on physical device layer,\nhas optional ``2`` parameters for API call event:\n\n* Callback function, called when command finished\n* Custom user parameter for callback function\n\nBelow is an example code for DNS resolver.\nIt uses custom API callback function with custom argument,\nused to distinguis domain name (when multiple domains are to be resolved).\n\n.. literalinclude:: ../../snippets/dns.c\n    :language: c\n    :linenos:\n    :caption: Simple example for API call event, using DNS module\n\n.. toctree::\n    :maxdepth: 2\n    :glob:"
  },
  {
    "path": "docs/user-manual/index.rst",
    "content": ".. _um:\n\nUser manual\n===========\n\n.. toctree::\n    :maxdepth: 2\n\n    overview\n    architecture\n    inter-thread-comm\n    events-cb-fn\n    blocking-nonblocking\n    porting-guide\n    ssl-support"
  },
  {
    "path": "docs/user-manual/inter-thread-comm.rst",
    "content": ".. _um_inter_thread_comm:\n\nInter thread communication\n==========================\n\nESP-AT middleware is only available with operating system.\nFor successful resources management, it uses ``2`` threads within library and allows multiple application threads to post new command to be processed.\n\n.. figure:: ../static/images/thread_communication.svg\n\t:align: center\n\t:alt: Inter-thread architecture block diagram\n\n\tInter-thread architecture block diagram\n\n*Producing* and *Processing* threads are part of library, its implementation is in ``lwesp_threads.c`` file.\n\nProcessing thread\n^^^^^^^^^^^^^^^^^\n\n*Processing thread* is in charge of processing each and every received character from *ESP* device.\nIt can process *URC* messages which are received from *ESP* device without any command request. Some of them are:\n\n* *+IPD* indicating new data packet received from remote side on active connection\n* *WIFI CONNECTED* indicating *ESP* has been just connected to access point\n* and more others\n\n.. note::\n\tReceived messages without any command (URC messages) are sent to application layer using events,\n\twhere they can be processed and used in further steps\n\nThis thread also checks and processes specific received messages based on active command.\nAs an example, when application tries to make a new connection to remote server, it starts command with ``AT+CIPSTART`` message.\nThread understands that active command is to connect to remote side and will wait for potential ``+LINK_CONN:<...>`` message,\nindicating connection status. it will also wait for ``OK`` or ``ERROR``,\nindicating *command finished* status before it unlocks **sync_sem** to unblock *producing thread*.\n\n.. tip::\n\tWhen thread tries to unlock **sync_sem**, it first checks if it has been locked by *producing thread*.\n\nProducing thread\n^^^^^^^^^^^^^^^^\n\n*Producing thread* waits for command messages posted from application thread.\nWhen new message has been received, it sends initial *AT message* over AT port.\n\n* It checks if command is valid and if it has corresponding initial AT sequence, such as ``AT+CIPSTART``\n* It locks **sync_sem** semaphore and waits for processing thread to unlock it\n\n  * *Processing thread* is in charge to read respone from *ESP* and react accordingly. See previous section for details.\n\n* If application uses *blocking mode*, it unlocks command **sem** semaphore and returns response\n* If application uses *non-blocking mode*, it frees memory for message and sends event with response message\n\nApplication thread\n^^^^^^^^^^^^^^^^^^\n\nApplication thread is considered any thread which calls API functions and therefore writes new messages to *producing message queue*,\nlater processed by *producing thread*.\n\nA new message memory is allocated in this thread and type of command is assigned to it, together with required input data for command.\nIt also sets *blocking* or *non-blocking* mode, how command shall be executed.\n\nWhen application tries to execute command in *blocking mode*, it creates new sync semaphore **sem**, locks it,\nwrites message to *producing queue* and waits for **sem** to get unlocked.\nThis effectively puts thread to blocked state by operating system and removes it from scheduler until semaphore is unlocked again.\nSemaphore **sem** gets unlocked in *producing thread* when response has been received for specific command.\n\n.. tip::\n\t**sem** semaphore is unlocked in *producing* thread after **sync_sem** is unlocked in *processing* thread\n\n.. note::\n    Every command message uses its own **sem** semaphore to sync multiple *application* threads at the same time.\n\nIf message is to be executed in *non-blocking* mode, **sem** is not created as there is no need to block application thread.\nWhen this is the case, application thread will only write message command to *producing queue* and return status of writing to application.\n\n.. toctree::\n    :maxdepth: 2\n    :glob:"
  },
  {
    "path": "docs/user-manual/overview.rst",
    "content": ".. _um_overview:\n\nOverview\n========\n\nWiFi devices (focus on *ESP8266* and *ESP32*) from *Espressif Systems* are low-cost and very useful for embedded projects.\nThese are classic microcontrollers without embedded flash memory. Application needs to assure external Quad-SPI flash to execute code from it directly.\n\n*Espressif* offers SDK to program these microcontrollers directly and run code from there.\nIt is called *RTOS-based SDK*, written in C language, and allows customers to program MCU starting with ``main`` function.\nThese devices have some basic peripherals, such as GPIO, ADC, SPI, I2C, UART, etc. Pretty basic though.\n\nWifi connectivity is often part of bigger system with more powerful MCU.\nThere is usually bigger MCU + Wifi transceiver (usually module) aside with UART/SPI communication.\nMCU handles application, such as display & graphics, runs operating systems, drives motor and has additional external memories.\n\n.. figure:: ../static/images/example_app_arch.svg\n\t:align: center\n\t:alt: Typical application example with access to WiFi\n\n\tTypical application example with access to WiFi\n\n*Espressif* is not only developing *RTOS SDK* firmware, it also develops *AT Slave firmware* based on *RTOS-SDK*.\nThis is a special application, which is running on *ESP* device and allows host MCU to send *AT commands* and get response for it.\nNow it is time to use *LwESP* you are reading this manual for.\n\n*LwESP* has been developed to allow customers to:\n\n* Develop on single (host MCU) architecture at the same time and do not care about *Espressif* arch\n* Shorten time to market\n\nCustomers using *LwESP* do not need to take care about proper command for specific task,\nthey can call API functions, such as :cpp:func:`lwesp_sta_join` to join WiFi network instead.\nLibrary will take the necessary steps in order to send right command to device via low-level driver (usually UART) and\nprocess incoming response from device before it will notify application layer if it was successfuly or not.\n\n.. note::\n\t*LwESP* offers efficient communication between host MCU at one side and *Espressif* wifi transceiver on another side.\n\nTo summarize:\n\n* *ESP* device runs official *AT* firmware, provided by *Espressif systems*\n* Host MCU runs custom application, together with *LwESP* library\n* Host MCU communicates with *ESP* device with UART or similar interface.\n\n.. toctree::\n    :maxdepth: 2\n    :glob:"
  },
  {
    "path": "docs/user-manual/porting-guide.rst",
    "content": ".. _um_porting_guide:\n\nPorting guide\n=============\n\nHigh level of *ESP-AT* library is platform independent, written in C (C11),\nhowever there is an important part where middleware needs to communicate with target *ESP* device\nand it must work under different optional operating systems selected by final customer.\n\nPorting consists of:\n\n* Implementation of *low-level* part, for actual communication between host device and *ESP* device\n* Implementation of system functions, link between target operating system and middleware functions\n* Assignment of memory for allocation manager\n\nImplement low-level driver\n^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nTo successfully prepare all parts of *low-level* driver, application must take care of:\n\n* Implementing :cpp:func:`lwesp_ll_init` and :cpp:func:`lwesp_ll_deinit` callback functions\n* Implement and assign *send data* and optional *hardware reset* function callbacks\n* Assign memory for allocation manager when using default allocator or use custom allocator\n* Process received data from *ESP* device and send it to input module for further processing\n\n.. tip::\n    Port examples are available for STM32 and WIN32 architectures.\n    Both actual working and up-to-date implementations are available within the library.\n\n.. note::\n    Check :ref:`api_lwesp_input` for more information about direct & indirect input processing.\n\nImplement system functions\n^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nSystem functions are bridge between operating system calls and *ESP* middleware.\n*ESP* library relies on stable operating system features and its implementation and\ndoes not require any special features which do not normally come with operating systems.\n\nOperating system must support:\n\n* Thread management functions\n* Mutex management functions\n* Binary semaphores only, no need for counting semaphores\n* Message queue management functions\n\n.. warning::\n    If any of the features are not available within targeted operating system,\n    customer needs to resolve it with care. As an example, message queue is not available\n    in WIN32 OS API therefore custom message queue has been implemented using binary semaphores\n\nApplication needs to implement all system call functions, starting with ``lwesp_sys_``.\nIt must also prepare header file for standard types in order to support OS types within *ESP* middleware.\n\nAn example code is provided latter section of this page for WIN32 and STM32.\n\nSteps to follow\n***************\n\n* Copy ``lwesp/src/system/lwesp_sys_template.c`` to the same folder and rename it to application port, eg. ``lwesp_sys_win32.c``\n* Open newly created file and implement all system functions\n* Copy folder ``lwesp/src/include/system/port/template/*`` to the same folder and rename *folder name* to application port, eg. ``cmsis_os``\n* Open ``lwesp_sys_port.h`` file from newly created folder and implement all *typedefs* and *macros* for specific target\n* Add source file to compiler sources and add path to header file to include paths in compiler options\n\n.. note::\n    Check :ref:`api_lwesp_sys` for function prototypes.\n\nExample: Low-level driver for WIN32\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nExample code for low-level porting on `WIN32` platform.\nIt uses native *Windows* features to open *COM* port and read/write from/to it.\n\nNotes:\n\n* It uses separate thread for received data processing.\n  It uses :cpp:func:`lwesp_input_process` or :cpp:func:`lwesp_input` functions, based on application configuration of :c:macro:`LWESP_CFG_INPUT_USE_PROCESS` parameter.\n\n  * When :c:macro:`LWESP_CFG_INPUT_USE_PROCESS` is disabled, dedicated receive buffer is created by *ESP-AT* library\n    and :cpp:func:`lwesp_input` function just writes data to it and does not process received characters immediately.\n    This is handled by *Processing* thread at later stage instead.\n  * When :c:macro:`LWESP_CFG_INPUT_USE_PROCESS` is enabled, :cpp:func:`lwesp_input_process` is used,\n    which directly processes input data and sends potential callback/event functions to application layer.\n\n* Memory manager has been assigned to ``1`` region of ``LWESP_MEM_SIZE`` size\n* It sets *send* and *reset* callback functions for *ESP-AT* library\n\n.. literalinclude:: ../../lwesp/src/system/lwesp_ll_win32.c\n    :language: c\n    :linenos:\n    :caption: Actual implementation of low-level driver for WIN32\n\nExample: Low-level driver for STM32\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nExample code for low-level porting on `STM32` platform.\nIt uses `CMSIS-OS` based application layer functions for implementing threads & other OS dependent features.\n\nNotes:\n\n* It uses separate thread for received data processing.\n  It uses :cpp:func:`lwesp_input_process` function to directly process received data without using intermediate receive buffer\n* Memory manager has been assigned to ``1`` region of ``LWESP_MEM_SIZE`` size\n* It sets *send* and *reset* callback functions for *ESP-AT* library\n\n.. literalinclude:: ../../lwesp/src/system/lwesp_ll_stm32.c\n    :language: c\n    :linenos:\n    :caption: Actual implementation of low-level driver for STM32\n\nExample: System functions for WIN32\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\n.. literalinclude:: ../../lwesp/src/include/system/port/win32/lwesp_sys_port.h\n    :language: c\n    :linenos:\n    :caption: Actual header implementation of system functions for WIN32\n\n.. literalinclude:: ../../lwesp/src/system/lwesp_sys_win32.c\n    :language: c\n    :linenos:\n    :caption: Actual implementation of system functions for WIN32\n\nExample: System functions for CMSIS-OS\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\n.. literalinclude:: ../../lwesp/src/include/system/port/cmsis_os/lwesp_sys_port.h\n    :language: c\n    :linenos:\n    :caption: Actual header implementation of system functions for CMSIS-OS based operating systems\n\n.. literalinclude:: ../../lwesp/src/system/lwesp_sys_cmsis_os.c\n    :language: c\n    :linenos:\n    :caption: Actual implementation of system functions for CMSIS-OS based operating systems\n\n.. toctree::\n    :maxdepth: 2\n    :glob:"
  },
  {
    "path": "docs/user-manual/ssl-support.rst",
    "content": ".. _um_ssl_support:\n\nTCP connection SSL support\n==========================\n\n.. warning:: \n    SSL support is currently in experimental mode. API changes may occur in the future.\n\nESP-AT binary, running on Espressif chips, supports SLL connection types.\nSuch connections, to work properly, require client or server certificates to be loaded to Espressif device.\n\nWith the recent update, *July 29th, 2023*, library has been updated to support AT commands for flash and MFG operations,\nallowing host microcontroller to load required certificates to the Espressif device.\n\n.. note::\n    Minimum required ESP-AT library running on ESP device is now ``v3.2.0``, which supports new *AT+SYSMFG* command,\n    that is required to load custom data to the device.\n\n.. note::\n    SSL connections mentioned on this page are secure from Espressif device towards network.\n    Data between host MCU and Espressif MCU is not protected and may be exposed to an attacker\n\nPrepare the certificate\n***********************\n\nAssuming we would like to establish connection to another server with secure SSL connection,\nESP device shall have up to ``3`` certificates loaded in its own system flash. These are:\n\n* *client_ca* - Client root CA certificate - client uses this certificate to verify server. `Example <https://github.com/espressif/esp-at/blob/c0391fd1/components/customized_partitions/raw_data/client_ca/client_ca_00.crt>`_\n* *client_cert* - Client certificate. `Example <https://github.com/espressif/esp-at/blob/c0391fd1/components/customized_partitions/raw_data/client_cert/client_cert_00.crt>`_\n* *client_key* - Client private key. `Example <https://github.com/espressif/esp-at/blob/c0391fd1/components/customized_partitions/raw_data/client_key/client_key_00.key>`_\n\nESP-AT website includes some test certificates, that could be used for test purposes: `Description of all slots <https://docs.espressif.com/projects/esp-at/en/latest/esp32/Compile_and_Develop/How_to_update_pki_config.html>`_\n\nLwESP repository contains aforementioned certificates in the *certificates* folder. There are *2* files for each certificate:\n\n* Original *.crt* or *.key* file\n* Original *.crt* or *.key* file converted to *.hex* array for easier include in the C project.\n\nLoad to ESP device\n******************\n\nLoading can be done as part of custom AT firmware build, or by using AT commands.\nLwESP library has the support for system flash and manufacturing NVS data operation, that is required for certificate load.\n\nAll combined, steps to establish SSL connection is to:\n\n* Have certificates loaded to ESP-AT device with Espressif format\n* Have configured connections to use your certificates, if *SSL* type is used on them\n* Have valid time in ESP device. *SNTP* module can help with that\n\nExample\n*******\n\nBelow is the up-to-date netconn API example using SSL connection. Example file is located in ``snippets/netconn_client_ssl.c``\n\n.. literalinclude:: ../../snippets/netconn_client_ssl.c\n    :language: c\n    :linenos:\n    :caption: Netconn example with SSL\n\n.. toctree::\n    :maxdepth: 2\n    :glob:"
  },
  {
    "path": "examples/README.md",
    "content": "# ESP examples\n\nExamples are split into different CPU architectures. Currently you can find examples for:\n\n- `Visual Studio`: All examples will be always released for Visual studio, due to the fact that library is developed in it. You can run examples with NodeMCU hardware or any other hardware, if you connect it to USB and run with AT commands\n- `POSIX`: Some examples will be added for Linux (or other POSIX compliant platforms). You can run examples with ESP devices\nconnected to USB-TTL adapters or single board computers (e.g. Raspberry Pi).\n- `STM32-Discovery`: Small amount of examples are available for STM32 based Discovery boards which come with socket for ESP-01 device. Examples are written in *Atollic TrueSTUDIO (GCC compiler)*, *Keil uVision (MDK-ARM compiler)* and *IAR*.\n\n### ESP requirements\n\nIn order to run the examples, ESP device must run the AT software provided from Espressif systems.\nPlease check official documentation for detailed requirements to run this library with you ESP8266 device.\n\n## WIN32 Examples\n\nAll windows based examples are written in Visual Studio 2017 as \"Win32 project\" and \"Console Application\".\n\n### Visual Studio configuration\n\nIt may happen that Visual Studio sets different configuration on first project load and this may lead to wrong build and possible errors. Active configuration must be `Debug` and `Win32` or `x86`. Default active build can be set in project settings.\n\n### NodeMCU development board\n\nFor development purposes, NodeMCU v3 board was used with virtual COM port support\nto translate USB communication to UART required for ESP8266.\n\n> Some NodeMCU boards have [CH340 USB->UART](https://www.tindie.com/products/multicognitive/nodemcu-esp8266-v3-lua-ch340-wifi-dev-board/) transceiver where I found problems with communication due to data loss between ESP and PC even at 115200 bauds. Try to find [NodeMCU with something else than CH340](https://www.ebay.com/itm/NodeMcu-Amica-V3-ESP-12E-ESP12E-4MB-FLASH-Lua-WIFI-Networking-dev-board-ESP8266-/141778019163).\n\n### System functions for WIN32\n\nRequired system functions are based on \"windows.h\" file, available on windows operating system. Natively, there is support for:\n1. Timing functions\n2. Semaphores\n3. Mutexes\n4. Threads\n\nThe last part are message queues which are not implemented in Windows OS. Message queues were developed with help of semaphores and dynamic memory allocatations. System port for WIN32 is available in [esp_sys_win32.c](/src/system/esp_sys_win32.c) file.\n\n### Communication with WIN32\n\nCommunication with NodeMCU hardware is using virtual files for COM ports. \nImplementation of low-level part (together with memory allocation for library) is available in [esp_ll_win32.c](/src/system/esp_ll_win32.c) file.\n\n> In order to start using this port, user must set the appropriate COM port name when opening a virtual file. Please check implementation file for details.\n\n## POSIX Examples\nAll POSIX examples are using CMake build system and can be built either native or cross-compile with the following instructions:\n```bash\ncd ${EXAMPLE_PROJECT_DIRECTORY}\nmkdir build && cd build # Create a build directory\ncmake .. && make -j$(nproc)\n```\n\n### System functions for POSIX\nThis port utilized pthread library:\n1. Mutexes\n2. Semaphores\n3. Threads\n\nas well as `<time.h>` for:\n1. SysTick\n2. Timed Semaphores\n\nPOSIX message queue are too powerful for this, so the same implementation as Windows is used.\n\n### Communication with POSIX system\nCommunication with NodeMCU hardware is done by using POSIX APIs through `/dev/ttyXYZ` character device. \nImplementation of low-level part (together with memory allocation for library) is available in [esp_ll_posix.c](/src/system/esp_ll_posix.c) file.\n\n> The communication serial port may also needs to be altered if necessary, just like Windows port does.\n\n## STM32F769I-Discovery\n\nUse connector **CN2** to connect ESP-01 module with the board\n```\nDetailed pinout for STM32F769I-Discovery board\n\nESP-01 connection\n- ESP_RX:           PC12\n- ESP_TX:           PD2\n- ESP_RESET:        PJ14\n\n- UART:             UART5\n- UART DMA:         DMA1\n- UART DMA STREAM:  DMA_STREAM_0\n- UART DMA CHANNEL: DMA_CHANNEL_4\n\nDEBUG UART, connected through ST-LinkV2/1\n- UART:             USART1\n- UART_TX:          PA9\n- UART_RX:          PA10\n- UART baudrate:    921600\n```\n\nDriver implementation is available in [esp_ll_stm32f769i_discovery.c](/src/system/esp_ll_stm32f769i_discovery.c)\n\n## STM32F723E-Discovery\n\nUse connector **CN14** to connect ESP-01 module with the board\n```\nDetailed pinout for STM32F723E-Discovery board\n\nESP-01 connection\n- ESP_RX:           PC12\n- ESP_TX:           PD2\n- ESP_RESET:        PG14\n- ESP_CH_PD:        PD3\n- ESP_GPIO_2:       PD6\n\n- UART:             UART5\n- UART DMA:         DMA1\n- UART DMA STREAM:  DMA_STREAM_0\n- UART DMA CHANNEL: DMA_CHANNEL_4\n\nDEBUG UART, connected through ST-LinkV2/1\n- UART:             USART6\n- UART_TX:          PC6\n- UART_RX:          PC7\n- UART baudrate:    921600\n```\n\nDriver implementation is available in [esp_ll_stm32f723e_discovery.c](/src/system/esp_ll_stm32f723e_discovery.c) file.\n\n## STM32L496G-Discovery\n\nDiscovery comes with STMOD+ extensions board which includes connector marked as **ESP-01**.\n\n```\nDetailed pinout for STM32L496G-Discovery board\n\nESP-01 connection\n- ESP_RX:           PB6\n- ESP_TX:           PG10, pin connected on VDDIO2 domain, make sure it is enabled in PWR registers\n- ESP_RESET:        PB2\n- ESP_CH_PD:        PA4\n- ESP_GPIO_0:       PH0\n- ESP_GPIO_2:       PA0\n\n- UART:             USART1\n- UART DMA:         DMA1\n- UART DMA CHANNEL: DMA_CHANNEL_5\n- UART DMA REQUEST: DMA_REQUEST_2\n\nDEBUG UART, connected through ST-LinkV2/1\n- UART:             USART2\n- UART_TX:          PA2\n- UART_RX:          PD6\n- UART baudrate:    921600\n```\n\nDriver implementation is available in [esp_ll_stm32l496g_discovery.c](/src/system/esp_ll_stm32l496g_discovery.c)\n\n## STM32L432KC-Nucleo\n\n```\nDetailed pinout for STM32L432KC-Nucleo board\n\nESP-01 connection\n- ESP_RX:           PA9\n- ESP_TX:           PA10\n- ESP_RESET:        PA12\n- ESP_CH_PD:        PB0\n- ESP_GPIO_0:       PA7\n- ESP_GPIO_2:       PA6\n\n- UART:             USART1\n- UART DMA:         DMA1\n- UART DMA CHANNEL: DMA_CHANNEL_5\n- UART DMA REQUEST: DMA_REQUEST_2\n\nDEBUG UART, connected through ST-LinkV2/1\n- UART:             USART2\n- UART_TX:          PA2\n- UART_RX:          PA3\n- UART baudrate:    921600\n```\n\nDriver implementation is available in [esp_ll_stm32l432kc_nucleo.c](/src/system/esp_ll_stm32l432kc_nucleo.c)\n"
  },
  {
    "path": "examples/lib/FreeRTOS/CMSIS_RTOS/cmsis_os.c",
    "content": "/* ----------------------------------------------------------------------\n * $Date:        5. February 2013\n * $Revision:    V1.02\n *\n * Project:      CMSIS-RTOS API\n * Title:        cmsis_os.c\n *\n * Version 0.02\n *    Initial Proposal Phase\n * Version 0.03\n *    osKernelStart added, optional feature: main started as thread\n *    osSemaphores have standard behavior\n *    osTimerCreate does not start the timer, added osTimerStart\n *    osThreadPass is renamed to osThreadYield\n * Version 1.01\n *    Support for C++ interface\n *     - const attribute removed from the osXxxxDef_t typedef's\n *     - const attribute added to the osXxxxDef macros\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\n *    Added: osKernelInitialize\n * Version 1.02\n *    Control functions for short timeouts in microsecond resolution:\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\n *    Removed: osSignalGet \n *    \n *  \n *----------------------------------------------------------------------------\n *\n * Portions Copyright  2016 STMicroelectronics International N.V. All rights reserved.\n * Portions Copyright (c) 2013 ARM LIMITED\n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *  - Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  - Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n *  - Neither the name of ARM  nor the names of its contributors may be used\n *    to endorse or promote products derived from this software without\n *    specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *---------------------------------------------------------------------------*/\n\n /**\n  ******************************************************************************\n  * @file    cmsis_os.c\n  * @author  MCD Application Team\n  * @date    13-July-2017\n  * @brief   CMSIS-RTOS API implementation for FreeRTOS V9.0.0\n  ******************************************************************************\n  * @attention\n  *\n  * Redistribution and use in source and binary forms, with or without \n  * modification, are permitted, provided that the following conditions are met:\n  *\n  * 1. Redistribution of source code must retain the above copyright notice, \n  *    this list of conditions and the following disclaimer.\n  * 2. Redistributions in binary form must reproduce the above copyright notice,\n  *    this list of conditions and the following disclaimer in the documentation\n  *    and/or other materials provided with the distribution.\n  * 3. Neither the name of STMicroelectronics nor the names of other \n  *    contributors to this software may be used to endorse or promote products \n  *    derived from this software without specific written permission.\n  * 4. This software, including modifications and/or derivative works of this \n  *    software, must execute solely and exclusively on microcontroller or\n  *    microprocessor devices manufactured by or for STMicroelectronics.\n  * 5. Redistribution and use of this software other than as permitted under \n  *    this license is void and will automatically terminate your rights under \n  *    this license. \n  *\n  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS \"AS IS\" \n  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT \n  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \n  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY\n  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT \n  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, \n  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF \n  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING \n  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */ \n\n#include <string.h>\n#include \"cmsis_os.h\"\n\n/*\n * ARM Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n\n  #define __ASM            __asm                                      \n  #define __INLINE         __inline                                     \n  #define __STATIC_INLINE  static __inline\n\n  #include \"cmsis_armcc.h\"\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n\n  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */\n  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */\n  #define __STATIC_INLINE  static inline\n\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n\n  #ifndef   __ASM\n    #define __ASM                     __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                  inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE           static inline\n  #endif\n\n  #include <cmsis_iar.h>\n#endif\n\nextern void xPortSysTickHandler(void);\n\n/* Convert from CMSIS type osPriority to FreeRTOS priority number */\nstatic unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)\n{\n  unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;\n  \n  if (priority != osPriorityError) {\n    fpriority += (priority - osPriorityIdle);\n  }\n  \n  return fpriority;\n}\n\n#if (INCLUDE_uxTaskPriorityGet == 1)\n/* Convert from FreeRTOS priority number to CMSIS type osPriority */\nstatic osPriority makeCmsisPriority (unsigned portBASE_TYPE fpriority)\n{\n  osPriority priority = osPriorityError;\n  \n  if ((fpriority - tskIDLE_PRIORITY) <= (osPriorityRealtime - osPriorityIdle)) {\n    priority = (osPriority)((int)osPriorityIdle + (int)(fpriority - tskIDLE_PRIORITY));\n  }\n  \n  return priority;\n}\n#endif\n\n\n/* Determine whether we are in thread mode or handler mode. */\nstatic int inHandlerMode (void)\n{\n  return __get_IPSR() != 0;\n}\n\n/*********************** Kernel Control Functions *****************************/\n/**\n* @brief  Initialize the RTOS Kernel for creating objects.\n* @retval status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osKernelInitialize shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osKernelInitialize (void);\n\n/**\n* @brief  Start the RTOS Kernel with executing the specified thread.\n* @param  thread_def    thread definition referenced with \\ref osThread.\n* @param  argument      pointer that is passed to the thread function as start argument.\n* @retval status code that indicates the execution status of the function\n* @note   MUST REMAIN UNCHANGED: \\b osKernelStart shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osKernelStart (void)\n{\n  vTaskStartScheduler();\n  \n  return osOK;\n}\n\n/**\n* @brief  Check if the RTOS kernel is already started\n* @param  None\n* @retval (0) RTOS is not started\n*         (1) RTOS is started\n*         (-1) if this feature is disabled in FreeRTOSConfig.h \n* @note  MUST REMAIN UNCHANGED: \\b osKernelRunning shall be consistent in every CMSIS-RTOS.\n*/\nint32_t osKernelRunning(void)\n{\n#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n  if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED)\n    return 0;\n  else\n    return 1;\n#else\n\treturn (-1);\n#endif\t\n}\n\n#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available\n/**\n* @brief  Get the value of the Kernel SysTick timer\n* @param  None\n* @retval None\n* @note   MUST REMAIN UNCHANGED: \\b osKernelSysTick shall be consistent in every CMSIS-RTOS.\n*/\nuint32_t osKernelSysTick(void)\n{\n  if (inHandlerMode()) {\n    return xTaskGetTickCountFromISR();\n  }\n  else {\n    return xTaskGetTickCount();\n  }\n}\n#endif    // System Timer available\n/*********************** Thread Management *****************************/\n/**\n* @brief  Create a thread and add it to Active Threads and set it to state READY.\n* @param  thread_def    thread definition referenced with \\ref osThread.\n* @param  argument      pointer that is passed to the thread function as start argument.\n* @retval thread ID for reference by other functions or NULL in case of error.\n* @note   MUST REMAIN UNCHANGED: \\b osThreadCreate shall be consistent in every CMSIS-RTOS.\n*/\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)\n{\n  TaskHandle_t handle;\n  \n#if( configSUPPORT_STATIC_ALLOCATION == 1 ) &&  ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n  if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {\n    handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,\n              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),\n              thread_def->buffer, thread_def->controlblock);\n  }\n  else {\n    if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,\n              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),\n              &handle) != pdPASS)  {\n      return NULL;\n    } \n  }\n#elif( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n    handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,\n              thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),\n              thread_def->buffer, thread_def->controlblock);\n#else\n  if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,\n                   thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),\n                   &handle) != pdPASS)  {\n    return NULL;\n  }     \n#endif\n  \n  return handle;\n}\n\n/**\n* @brief  Return the thread ID of the current running thread.\n* @retval thread ID for reference by other functions or NULL in case of error.\n* @note   MUST REMAIN UNCHANGED: \\b osThreadGetId shall be consistent in every CMSIS-RTOS.\n*/\nosThreadId osThreadGetId (void)\n{\n#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\n  return xTaskGetCurrentTaskHandle();\n#else\n\treturn NULL;\n#endif\n}\n\n/**\n* @brief  Terminate execution of a thread and remove it from Active Threads.\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osThreadTerminate shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osThreadTerminate (osThreadId thread_id)\n{\n#if (INCLUDE_vTaskDelete == 1)\n  vTaskDelete(thread_id);\n  return osOK;\n#else\n  return osErrorOS;\n#endif\n}\n\n/**\n* @brief  Pass control to next thread that is in state \\b READY.\n* @retval status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osThreadYield shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osThreadYield (void)\n{\n  taskYIELD();\n  \n  return osOK;\n}\n\n/**\n* @brief   Change priority of an active thread.\n* @param   thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @param   priority      new priority value for the thread function.\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osThreadSetPriority shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority)\n{\n#if (INCLUDE_vTaskPrioritySet == 1)\n  vTaskPrioritySet(thread_id, makeFreeRtosPriority(priority));\n  return osOK;\n#else\n  return osErrorOS;\n#endif\n}\n\n/**\n* @brief   Get current priority of an active thread.\n* @param   thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval  current priority value of the thread function.\n* @note   MUST REMAIN UNCHANGED: \\b osThreadGetPriority shall be consistent in every CMSIS-RTOS.\n*/\nosPriority osThreadGetPriority (osThreadId thread_id)\n{\n#if (INCLUDE_uxTaskPriorityGet == 1)\n  if (inHandlerMode())\n  {\n    return makeCmsisPriority(uxTaskPriorityGetFromISR(thread_id));  \n  }\n  else\n  {  \n    return makeCmsisPriority(uxTaskPriorityGet(thread_id));\n  }\n#else\n  return osPriorityError;\n#endif\n}\n\n/*********************** Generic Wait Functions *******************************/\n/**\n* @brief   Wait for Timeout (Time Delay)\n* @param   millisec      time delay value\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osDelay (uint32_t millisec)\n{\n#if INCLUDE_vTaskDelay\n  TickType_t ticks = millisec / portTICK_PERIOD_MS;\n  \n  vTaskDelay(ticks ? ticks : 1);          /* Minimum delay = 1 tick */\n  \n  return osOK;\n#else\n  (void) millisec;\n  \n  return osErrorResource;\n#endif\n}\n\n#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0)) /* Generic Wait available */\n/**\n* @brief  Wait for Signal, Message, Mail, or Timeout\n* @param   millisec  timeout value or 0 in case of no time-out\n* @retval  event that contains signal, message, or mail information or error code.\n* @note   MUST REMAIN UNCHANGED: \\b osWait shall be consistent in every CMSIS-RTOS.\n*/\nosEvent osWait (uint32_t millisec);\n\n#endif  /* Generic Wait available */\n\n/***********************  Timer Management Functions ***************************/\n/**\n* @brief  Create a timer.\n* @param  timer_def     timer object referenced with \\ref osTimer.\n* @param  type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n* @param  argument      argument to the timer call back function.\n* @retval  timer ID for reference by other functions or NULL in case of error.\n* @note   MUST REMAIN UNCHANGED: \\b osTimerCreate shall be consistent in every CMSIS-RTOS.\n*/\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument)\n{\n#if (configUSE_TIMERS == 1)\n\n#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) \n  if(timer_def->controlblock != NULL) {\n    return xTimerCreateStatic((const char *)\"\",\n                      1, // period should be filled when starting the Timer using osTimerStart\n                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,\n                      (void *) argument,\n                      (TaskFunction_t)timer_def->ptimer,\n                      (StaticTimer_t *)timer_def->controlblock);\n  }\n  else {\n    return xTimerCreate((const char *)\"\",\n                      1, // period should be filled when starting the Timer using osTimerStart\n                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,\n                      (void *) argument,\n                      (TaskFunction_t)timer_def->ptimer);\n }\n#elif( configSUPPORT_STATIC_ALLOCATION == 1 )\n  return xTimerCreateStatic((const char *)\"\",\n                      1, // period should be filled when starting the Timer using osTimerStart\n                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,\n                      (void *) argument,\n                      (TaskFunction_t)timer_def->ptimer,\n                      (StaticTimer_t *)timer_def->controlblock);  \n#else\n  return xTimerCreate((const char *)\"\",\n                      1, // period should be filled when starting the Timer using osTimerStart\n                      (type == osTimerPeriodic) ? pdTRUE : pdFALSE,\n                      (void *) argument,\n                      (TaskFunction_t)timer_def->ptimer);\n#endif\n\n#else \n\treturn NULL;\n#endif\n}\n\n/**\n* @brief  Start or restart a timer.\n* @param  timer_id      timer ID obtained by \\ref osTimerCreate.\n* @param  millisec      time delay value of the timer.\n* @retval  status code that indicates the execution status of the function\n* @note   MUST REMAIN UNCHANGED: \\b osTimerStart shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec)\n{\n  osStatus result = osOK;\n#if (configUSE_TIMERS == 1)  \n  portBASE_TYPE taskWoken = pdFALSE;\n  TickType_t ticks = millisec / portTICK_PERIOD_MS;\n\n  if (ticks == 0)\n    ticks = 1;\n    \n  if (inHandlerMode()) \n  {\n    if (xTimerChangePeriodFromISR(timer_id, ticks, &taskWoken) != pdPASS)\n    {\n      result = osErrorOS;\n    }\n    else\n    {\n      portEND_SWITCHING_ISR(taskWoken);     \n    }\n  }\n  else \n  {\n    if (xTimerChangePeriod(timer_id, ticks, 0) != pdPASS)\n      result = osErrorOS;\n  }\n\n#else \n  result = osErrorOS;\n#endif\n  return result;\n}\n\n/**\n* @brief  Stop a timer.\n* @param  timer_id      timer ID obtained by \\ref osTimerCreate\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osTimerStop shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osTimerStop (osTimerId timer_id)\n{\n  osStatus result = osOK;\n#if (configUSE_TIMERS == 1)  \n  portBASE_TYPE taskWoken = pdFALSE;\n\n  if (inHandlerMode()) {\n    if (xTimerStopFromISR(timer_id, &taskWoken) != pdPASS) {\n      return osErrorOS;\n    }\n    portEND_SWITCHING_ISR(taskWoken);\n  }\n  else {\n    if (xTimerStop(timer_id, 0) != pdPASS) {\n      result = osErrorOS;\n    }\n  }\n#else \n  result = osErrorOS;\n#endif \n  return result;\n}\n\n/**\n* @brief  Delete a timer.\n* @param  timer_id      timer ID obtained by \\ref osTimerCreate\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osTimerDelete shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osTimerDelete (osTimerId timer_id)\n{\nosStatus result = osOK;\n\n#if (configUSE_TIMERS == 1)\n\n   if (inHandlerMode()) {\n     return osErrorISR;\n  }\n  else { \n    if ((xTimerDelete(timer_id, osWaitForever )) != pdPASS) {\n      result = osErrorOS;\n    }\n  } \n    \n#else \n  result = osErrorOS;\n#endif \n \n  return result;\n}\n\n/***************************  Signal Management ********************************/\n/**\n* @brief  Set the specified Signal Flags of an active thread.\n* @param  thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @param  signals       specifies the signal flags of the thread that should be set.\n* @retval previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\n* @note   MUST REMAIN UNCHANGED: \\b osSignalSet shall be consistent in every CMSIS-RTOS.\n*/\nint32_t osSignalSet (osThreadId thread_id, int32_t signal)\n{\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\t\n  BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n  uint32_t ulPreviousNotificationValue = 0;\n  \n  if (inHandlerMode())\n  {\n    if(xTaskGenericNotifyFromISR( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue, &xHigherPriorityTaskWoken ) != pdPASS )\n      return 0x80000000;\n    \n    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n  }  \n  else if(xTaskGenericNotify( thread_id , (uint32_t)signal, eSetBits, &ulPreviousNotificationValue) != pdPASS )\n    return 0x80000000;\n  \n  return ulPreviousNotificationValue;\n#else\n  (void) thread_id;\n  (void) signal;\n\n  return 0x80000000; /* Task Notification not supported */ \t\n#endif\n}\n\n/**\n* @brief  Clear the specified Signal Flags of an active thread.\n* @param  thread_id  thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @param  signals    specifies the signal flags of the thread that shall be cleared.\n* @retval  previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\n* @note   MUST REMAIN UNCHANGED: \\b osSignalClear shall be consistent in every CMSIS-RTOS.\n*/\nint32_t osSignalClear (osThreadId thread_id, int32_t signal);\n\n/**\n* @brief  Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\n* @param  signals   wait until all specified signal flags set or 0 for any single signal flag.\n* @param  millisec  timeout value or 0 in case of no time-out.\n* @retval  event flag information or error code.\n* @note   MUST REMAIN UNCHANGED: \\b osSignalWait shall be consistent in every CMSIS-RTOS.\n*/\nosEvent osSignalWait (int32_t signals, uint32_t millisec)\n{\n  osEvent ret;\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\n  TickType_t ticks;\n\n  ret.value.signals = 0;  \n  ticks = 0;\n  if (millisec == osWaitForever) {\n    ticks = portMAX_DELAY;\n  }\n  else if (millisec != 0) {\n    ticks = millisec / portTICK_PERIOD_MS;\n    if (ticks == 0) {\n      ticks = 1;\n    }\n  }  \n  \n  if (inHandlerMode())\n  {\n    ret.status = osErrorISR;  /*Not allowed in ISR*/\n  }\n  else\n  {\n    if(xTaskNotifyWait( 0,(uint32_t) signals, (uint32_t *)&ret.value.signals, ticks) != pdTRUE)\n    {\n      if(ticks == 0)  ret.status = osOK;\n      else  ret.status = osEventTimeout;\n    }\n    else if(ret.value.signals < 0)\n    {\n      ret.status =  osErrorValue;     \n    }\n    else  ret.status =  osEventSignal;\n  }\n#else\n  (void) signals;\n  (void) millisec;\n\t\n  ret.status =  osErrorOS;\t/* Task Notification not supported */\n#endif\n  \n  return ret;\n}\n\n/****************************  Mutex Management ********************************/\n/**\n* @brief  Create and Initialize a Mutex object\n* @param  mutex_def     mutex definition referenced with \\ref osMutex.\n* @retval  mutex ID for reference by other functions or NULL in case of error.\n* @note   MUST REMAIN UNCHANGED: \\b osMutexCreate shall be consistent in every CMSIS-RTOS.\n*/\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def)\n{\n#if ( configUSE_MUTEXES == 1)\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n  if (mutex_def->controlblock != NULL) {\n    return xSemaphoreCreateMutexStatic( mutex_def->controlblock );\n     }\n  else {\n    return xSemaphoreCreateMutex(); \n  }\n#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )\n  return xSemaphoreCreateMutexStatic( mutex_def->controlblock );\n#else  \n    return xSemaphoreCreateMutex(); \n#endif\n#else\n  return NULL;\n#endif\n}\n\n/**\n* @brief Wait until a Mutex becomes available\n* @param mutex_id      mutex ID obtained by \\ref osMutexCreate.\n* @param millisec      timeout value or 0 in case of no time-out.\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osMutexWait shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec)\n{\n  TickType_t ticks;\n  portBASE_TYPE taskWoken = pdFALSE;  \n  \n  \n  if (mutex_id == NULL) {\n    return osErrorParameter;\n  }\n  \n  ticks = 0;\n  if (millisec == osWaitForever) {\n    ticks = portMAX_DELAY;\n  }\n  else if (millisec != 0) {\n    ticks = millisec / portTICK_PERIOD_MS;\n    if (ticks == 0) {\n      ticks = 1;\n    }\n  }\n  \n  if (inHandlerMode()) {\n    if (xSemaphoreTakeFromISR(mutex_id, &taskWoken) != pdTRUE) {\n      return osErrorOS;\n    }\n\tportEND_SWITCHING_ISR(taskWoken);\n  } \n  else if (xSemaphoreTake(mutex_id, ticks) != pdTRUE) {\n    return osErrorOS;\n  }\n  \n  return osOK;\n}\n\n/**\n* @brief Release a Mutex that was obtained by \\ref osMutexWait\n* @param mutex_id      mutex ID obtained by \\ref osMutexCreate.\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osMutexRelease shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osMutexRelease (osMutexId mutex_id)\n{\n  osStatus result = osOK;\n  portBASE_TYPE taskWoken = pdFALSE;\n  \n  if (inHandlerMode()) {\n    if (xSemaphoreGiveFromISR(mutex_id, &taskWoken) != pdTRUE) {\n      return osErrorOS;\n    }\n    portEND_SWITCHING_ISR(taskWoken);\n  }\n  else if (xSemaphoreGive(mutex_id) != pdTRUE) \n  {\n    result = osErrorOS;\n  }\n  return result;\n}\n\n/**\n* @brief Delete a Mutex\n* @param mutex_id  mutex ID obtained by \\ref osMutexCreate.\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osMutexDelete shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osMutexDelete (osMutexId mutex_id)\n{\n  if (inHandlerMode()) {\n    return osErrorISR;\n  }\n\n  vQueueDelete(mutex_id);\n\n  return osOK;\n}\n\n/********************  Semaphore Management Functions **************************/\n\n#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))\n\n/**\n* @brief Create and Initialize a Semaphore object used for managing resources\n* @param semaphore_def semaphore definition referenced with \\ref osSemaphore.\n* @param count         number of available resources.\n* @retval  semaphore ID for reference by other functions or NULL in case of error.\n* @note   MUST REMAIN UNCHANGED: \\b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.\n*/\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count)\n{ \n#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n  osSemaphoreId sema;\n  \n  if (semaphore_def->controlblock != NULL){\n    if (count == 1) {\n      return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );\n    }\n    else {\n#if (configUSE_COUNTING_SEMAPHORES == 1 )\n      return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );\n#else\n      return NULL;\n#endif\n    }\n  }\n  else {\n    if (count == 1) {\n      vSemaphoreCreateBinary(sema);\n      return sema;\n    }\n    else {\n#if (configUSE_COUNTING_SEMAPHORES == 1 )\t\n      return xSemaphoreCreateCounting(count, count);\n#else\n      return NULL;\n#endif    \n    }\n  }\n#elif ( configSUPPORT_STATIC_ALLOCATION == 1 ) // configSUPPORT_DYNAMIC_ALLOCATION == 0\n  if(count == 1) {\n    return xSemaphoreCreateBinaryStatic( semaphore_def->controlblock );\n  }\n  else\n  {\n#if (configUSE_COUNTING_SEMAPHORES == 1 )\n      return xSemaphoreCreateCountingStatic( count, count, semaphore_def->controlblock );\n#else\n      return NULL;\n#endif    \n  }\n#else  // configSUPPORT_STATIC_ALLOCATION == 0  && configSUPPORT_DYNAMIC_ALLOCATION == 1\n  osSemaphoreId sema;\n \n  if (count == 1) {\n    vSemaphoreCreateBinary(sema);\n    return sema;\n  }\n  else {\n#if (configUSE_COUNTING_SEMAPHORES == 1 )\t\n    return xSemaphoreCreateCounting(count, count);\n#else\n    return NULL;\n#endif\n  }\n#endif\n}\n\n/**\n* @brief Wait until a Semaphore token becomes available\n* @param  semaphore_id  semaphore object referenced with \\ref osSemaphore.\n* @param  millisec      timeout value or 0 in case of no time-out.\n* @retval  number of available tokens, or -1 in case of incorrect parameters.\n* @note   MUST REMAIN UNCHANGED: \\b osSemaphoreWait shall be consistent in every CMSIS-RTOS.\n*/\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec)\n{\n  TickType_t ticks;\n  portBASE_TYPE taskWoken = pdFALSE;  \n  \n  \n  if (semaphore_id == NULL) {\n    return osErrorParameter;\n  }\n  \n  ticks = 0;\n  if (millisec == osWaitForever) {\n    ticks = portMAX_DELAY;\n  }\n  else if (millisec != 0) {\n    ticks = millisec / portTICK_PERIOD_MS;\n    if (ticks == 0) {\n      ticks = 1;\n    }\n  }\n  \n  if (inHandlerMode()) {\n    if (xSemaphoreTakeFromISR(semaphore_id, &taskWoken) != pdTRUE) {\n      return osErrorOS;\n    }\n\tportEND_SWITCHING_ISR(taskWoken);\n  }  \n  else if (xSemaphoreTake(semaphore_id, ticks) != pdTRUE) {\n    return osErrorOS;\n  }\n  \n  return osOK;\n}\n\n/**\n* @brief Release a Semaphore token\n* @param  semaphore_id  semaphore object referenced with \\ref osSemaphore.\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id)\n{\n  osStatus result = osOK;\n  portBASE_TYPE taskWoken = pdFALSE;\n  \n  \n  if (inHandlerMode()) {\n    if (xSemaphoreGiveFromISR(semaphore_id, &taskWoken) != pdTRUE) {\n      return osErrorOS;\n    }\n    portEND_SWITCHING_ISR(taskWoken);\n  }\n  else {\n    if (xSemaphoreGive(semaphore_id) != pdTRUE) {\n      result = osErrorOS;\n    }\n  }\n  \n  return result;\n}\n\n/**\n* @brief Delete a Semaphore\n* @param  semaphore_id  semaphore object referenced with \\ref osSemaphore.\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id)\n{\n  if (inHandlerMode()) {\n    return osErrorISR;\n  }\n\n  vSemaphoreDelete(semaphore_id);\n\n  return osOK; \n}\n\n#endif    /* Use Semaphores */\n\n/*******************   Memory Pool Management Functions  ***********************/\n\n#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0)) \n\n//TODO\n//This is a primitive and inefficient wrapper around the existing FreeRTOS memory management.\n//A better implementation will have to modify heap_x.c!\n\n\ntypedef struct os_pool_cb {\n  void *pool;\n  uint8_t *markers;\n  uint32_t pool_sz;\n  uint32_t item_sz;\n  uint32_t currentIndex;\n} os_pool_cb_t;\n\n\n/**\n* @brief Create and Initialize a memory pool\n* @param  pool_def      memory pool definition referenced with \\ref osPool.\n* @retval  memory pool ID for reference by other functions or NULL in case of error.\n* @note   MUST REMAIN UNCHANGED: \\b osPoolCreate shall be consistent in every CMSIS-RTOS.\n*/\nosPoolId osPoolCreate (const osPoolDef_t *pool_def)\n{\n#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n  osPoolId thePool;\n  int itemSize = 4 * ((pool_def->item_sz + 3) / 4);\n  uint32_t i;\n  \n  /* First have to allocate memory for the pool control block. */\n thePool = pvPortMalloc(sizeof(os_pool_cb_t));\n\n  \n  if (thePool) {\n    thePool->pool_sz = pool_def->pool_sz;\n    thePool->item_sz = itemSize;\n    thePool->currentIndex = 0;\n    \n    /* Memory for markers */\n    thePool->markers = pvPortMalloc(pool_def->pool_sz);\n   \n    if (thePool->markers) {\n      /* Now allocate the pool itself. */\n     thePool->pool = pvPortMalloc(pool_def->pool_sz * itemSize);\n      \n      if (thePool->pool) {\n        for (i = 0; i < pool_def->pool_sz; i++) {\n          thePool->markers[i] = 0;\n        }\n      }\n      else {\n        vPortFree(thePool->markers);\n        vPortFree(thePool);\n        thePool = NULL;\n      }\n    }\n    else {\n      vPortFree(thePool);\n      thePool = NULL;\n    }\n  }\n\n  return thePool;\n \n#else\n  return NULL;\n#endif\n}\n\n/**\n* @brief Allocate a memory block from a memory pool\n* @param pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n* @retval  address of the allocated memory block or NULL in case of no memory available.\n* @note   MUST REMAIN UNCHANGED: \\b osPoolAlloc shall be consistent in every CMSIS-RTOS.\n*/\nvoid *osPoolAlloc (osPoolId pool_id)\n{\n  int dummy = 0;\n  void *p = NULL;\n  uint32_t i;\n  uint32_t index;\n  \n  if (inHandlerMode()) {\n    dummy = portSET_INTERRUPT_MASK_FROM_ISR();\n  }\n  else {\n    vPortEnterCritical();\n  }\n  \n  for (i = 0; i < pool_id->pool_sz; i++) {\n    index = pool_id->currentIndex + i;\n    if (index >= pool_id->pool_sz) {\n      index = 0;\n    }\n    \n    if (pool_id->markers[index] == 0) {\n      pool_id->markers[index] = 1;\n      p = (void *)((uint32_t)(pool_id->pool) + (index * pool_id->item_sz));\n      pool_id->currentIndex = index;\n      break;\n    }\n  }\n  \n  if (inHandlerMode()) {\n    portCLEAR_INTERRUPT_MASK_FROM_ISR(dummy);\n  }\n  else {\n    vPortExitCritical();\n  }\n  \n  return p;\n}\n\n/**\n* @brief Allocate a memory block from a memory pool and set memory block to zero\n* @param  pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n* @retval  address of the allocated memory block or NULL in case of no memory available.\n* @note   MUST REMAIN UNCHANGED: \\b osPoolCAlloc shall be consistent in every CMSIS-RTOS.\n*/\nvoid *osPoolCAlloc (osPoolId pool_id)\n{\n  void *p = osPoolAlloc(pool_id);\n  \n  if (p != NULL)\n  {\n    memset(p, 0, sizeof(pool_id->pool_sz));\n  }\n  \n  return p;\n}\n\n/**\n* @brief Return an allocated memory block back to a specific memory pool\n* @param  pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n* @param  block         address of the allocated memory block that is returned to the memory pool.\n* @retval  status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osPoolFree shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osPoolFree (osPoolId pool_id, void *block)\n{\n  uint32_t index;\n  \n  if (pool_id == NULL) {\n    return osErrorParameter;\n  }\n  \n  if (block == NULL) {\n    return osErrorParameter;\n  }\n  \n  if (block < pool_id->pool) {\n    return osErrorParameter;\n  }\n  \n  index = (uint32_t)block - (uint32_t)(pool_id->pool);\n  if (index % pool_id->item_sz) {\n    return osErrorParameter;\n  }\n  index = index / pool_id->item_sz;\n  if (index >= pool_id->pool_sz) {\n    return osErrorParameter;\n  }\n  \n  pool_id->markers[index] = 0;\n  \n  return osOK;\n}\n\n\n#endif   /* Use Memory Pool Management */\n\n/*******************   Message Queue Management Functions  *********************/\n\n#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0)) /* Use Message Queues */\n\n/**\n* @brief Create and Initialize a Message Queue\n* @param queue_def     queue definition referenced with \\ref osMessageQ.\n* @param  thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n* @retval  message queue ID for reference by other functions or NULL in case of error.\n* @note   MUST REMAIN UNCHANGED: \\b osMessageCreate shall be consistent in every CMSIS-RTOS.\n*/\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)\n{\n  (void) thread_id;\n  \n#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n  if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {\n    return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);\n  }\n  else {\n    return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);\n  }\n#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )\n  return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);\n#else  \n  return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);\n#endif\n}\n\n/**\n* @brief Put a Message to a Queue.\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @param  info      message information.\n* @param  millisec  timeout value or 0 in case of no time-out.\n* @retval status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osMessagePut shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)\n{\n  portBASE_TYPE taskWoken = pdFALSE;\n  TickType_t ticks;\n  \n  ticks = millisec / portTICK_PERIOD_MS;\n  if (ticks == 0) {\n    ticks = 1;\n  }\n  \n  if (inHandlerMode()) {\n    if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {\n      return osErrorOS;\n    }\n    portEND_SWITCHING_ISR(taskWoken);\n  }\n  else {\n    if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {\n      return osErrorOS;\n    }\n  }\n  \n  return osOK;\n}\n\n/**\n* @brief Get a Message or Wait for a Message from a Queue.\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @param  millisec  timeout value or 0 in case of no time-out.\n* @retval event information that includes status code.\n* @note   MUST REMAIN UNCHANGED: \\b osMessageGet shall be consistent in every CMSIS-RTOS.\n*/\nosEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)\n{\n  portBASE_TYPE taskWoken;\n  TickType_t ticks;\n  osEvent event;\n  \n  event.def.message_id = queue_id;\n  event.value.v = 0;\n  \n  if (queue_id == NULL) {\n    event.status = osErrorParameter;\n    return event;\n  }\n  \n  taskWoken = pdFALSE;\n  \n  ticks = 0;\n  if (millisec == osWaitForever) {\n    ticks = portMAX_DELAY;\n  }\n  else if (millisec != 0) {\n    ticks = millisec / portTICK_PERIOD_MS;\n    if (ticks == 0) {\n      ticks = 1;\n    }\n  }\n  \n  if (inHandlerMode()) {\n    if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {\n      /* We have mail */\n      event.status = osEventMessage;\n    }\n    else {\n      event.status = osOK;\n    }\n    portEND_SWITCHING_ISR(taskWoken);\n  }\n  else {\n    if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {\n      /* We have mail */\n      event.status = osEventMessage;\n    }\n    else {\n      event.status = (ticks == 0) ? osOK : osEventTimeout;\n    }\n  }\n  \n  return event;\n}\n\n#endif     /* Use Message Queues */\n\n/********************   Mail Queue Management Functions  ***********************/\n#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))  /* Use Mail Queues */\n\n\ntypedef struct os_mailQ_cb {\n  const osMailQDef_t *queue_def;\n  QueueHandle_t handle;\n  osPoolId pool;\n} os_mailQ_cb_t;\n\n/**\n* @brief Create and Initialize mail queue\n* @param  queue_def     reference to the mail queue definition obtain with \\ref osMailQ\n* @param   thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n* @retval mail queue ID for reference by other functions or NULL in case of error.\n* @note   MUST REMAIN UNCHANGED: \\b osMailCreate shall be consistent in every CMSIS-RTOS.\n*/\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id)\n{\n#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n  (void) thread_id;\n  \n  osPoolDef_t pool_def = {queue_def->queue_sz, queue_def->item_sz, NULL};\n  \n  /* Create a mail queue control block */\n\n  *(queue_def->cb) = pvPortMalloc(sizeof(struct os_mailQ_cb));\n\n  if (*(queue_def->cb) == NULL) {\n    return NULL;\n  }\n  (*(queue_def->cb))->queue_def = queue_def;\n  \n  /* Create a queue in FreeRTOS */\n  (*(queue_def->cb))->handle = xQueueCreate(queue_def->queue_sz, sizeof(void *));\n\n\n  if ((*(queue_def->cb))->handle == NULL) {\n    vPortFree(*(queue_def->cb));\n    return NULL;\n  }\n  \n  /* Create a mail pool */\n  (*(queue_def->cb))->pool = osPoolCreate(&pool_def);\n  if ((*(queue_def->cb))->pool == NULL) {\n    //TODO: Delete queue. How to do it in FreeRTOS?\n    vPortFree(*(queue_def->cb));\n    return NULL;\n  }\n  \n  return *(queue_def->cb);\n#else\n  return NULL;\n#endif\n}\n\n/**\n* @brief Allocate a memory block from a mail\n* @param  queue_id      mail queue ID obtained with \\ref osMailCreate.\n* @param  millisec      timeout value or 0 in case of no time-out.\n* @retval pointer to memory block that can be filled with mail or NULL in case error.\n* @note   MUST REMAIN UNCHANGED: \\b osMailAlloc shall be consistent in every CMSIS-RTOS.\n*/\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec)\n{\n  (void) millisec;\n  void *p;\n  \n  \n  if (queue_id == NULL) {\n    return NULL;\n  }\n  \n  p = osPoolAlloc(queue_id->pool);\n  \n  return p;\n}\n\n/**\n* @brief Allocate a memory block from a mail and set memory block to zero\n* @param  queue_id      mail queue ID obtained with \\ref osMailCreate.\n* @param  millisec      timeout value or 0 in case of no time-out.\n* @retval pointer to memory block that can be filled with mail or NULL in case error.\n* @note   MUST REMAIN UNCHANGED: \\b osMailCAlloc shall be consistent in every CMSIS-RTOS.\n*/\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec)\n{\n  uint32_t i;\n  void *p = osMailAlloc(queue_id, millisec);\n  \n  if (p) {\n    for (i = 0; i < queue_id->queue_def->item_sz; i++) {\n      ((uint8_t *)p)[i] = 0;\n    }\n  }\n  \n  return p;\n}\n\n/**\n* @brief Put a mail to a queue\n* @param  queue_id      mail queue ID obtained with \\ref osMailCreate.\n* @param  mail          memory block previously allocated with \\ref osMailAlloc or \\ref osMailCAlloc.\n* @retval status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osMailPut shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osMailPut (osMailQId queue_id, void *mail)\n{\n  portBASE_TYPE taskWoken;\n  \n  \n  if (queue_id == NULL) {\n    return osErrorParameter;\n  }\n  \n  taskWoken = pdFALSE;\n  \n  if (inHandlerMode()) {\n    if (xQueueSendFromISR(queue_id->handle, &mail, &taskWoken) != pdTRUE) {\n      return osErrorOS;\n    }\n    portEND_SWITCHING_ISR(taskWoken);\n  }\n  else {\n    if (xQueueSend(queue_id->handle, &mail, 0) != pdTRUE) { \n      return osErrorOS;\n    }\n  }\n  \n  return osOK;\n}\n\n/**\n* @brief Get a mail from a queue\n* @param  queue_id   mail queue ID obtained with \\ref osMailCreate.\n* @param millisec    timeout value or 0 in case of no time-out\n* @retval event that contains mail information or error code.\n* @note   MUST REMAIN UNCHANGED: \\b osMailGet shall be consistent in every CMSIS-RTOS.\n*/\nosEvent osMailGet (osMailQId queue_id, uint32_t millisec)\n{\n  portBASE_TYPE taskWoken;\n  TickType_t ticks;\n  osEvent event;\n  \n  event.def.mail_id = queue_id;\n  \n  if (queue_id == NULL) {\n    event.status = osErrorParameter;\n    return event;\n  }\n  \n  taskWoken = pdFALSE;\n  \n  ticks = 0;\n  if (millisec == osWaitForever) {\n    ticks = portMAX_DELAY;\n  }\n  else if (millisec != 0) {\n    ticks = millisec / portTICK_PERIOD_MS;\n    if (ticks == 0) {\n      ticks = 1;\n    }\n  }\n  \n  if (inHandlerMode()) {\n    if (xQueueReceiveFromISR(queue_id->handle, &event.value.p, &taskWoken) == pdTRUE) {\n      /* We have mail */\n      event.status = osEventMail;\n    }\n    else {\n      event.status = osOK;\n    }\n    portEND_SWITCHING_ISR(taskWoken);\n  }\n  else {\n    if (xQueueReceive(queue_id->handle, &event.value.p, ticks) == pdTRUE) {\n      /* We have mail */\n      event.status = osEventMail;\n    }\n    else {\n      event.status = (ticks == 0) ? osOK : osEventTimeout;\n    }\n  }\n  \n  return event;\n}\n\n/**\n* @brief Free a memory block from a mail\n* @param  queue_id mail queue ID obtained with \\ref osMailCreate.\n* @param  mail     pointer to the memory block that was obtained with \\ref osMailGet.\n* @retval status code that indicates the execution status of the function.\n* @note   MUST REMAIN UNCHANGED: \\b osMailFree shall be consistent in every CMSIS-RTOS.\n*/\nosStatus osMailFree (osMailQId queue_id, void *mail)\n{\n  if (queue_id == NULL) {\n    return osErrorParameter;\n  }\n  \n  return osPoolFree(queue_id->pool, mail);\n}\n#endif  /* Use Mail Queues */\n\n/*************************** Additional specific APIs to Free RTOS ************/\n/**\n* @brief  Handles the tick increment\n* @param  none.\n* @retval none.\n*/\nvoid osSystickHandler(void)\n{\n\n#if (INCLUDE_xTaskGetSchedulerState  == 1 )\n  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)\n  {\n#endif  /* INCLUDE_xTaskGetSchedulerState */  \n    xPortSysTickHandler();\n#if (INCLUDE_xTaskGetSchedulerState  == 1 )\n  }\n#endif  /* INCLUDE_xTaskGetSchedulerState */  \n}\n\n#if ( INCLUDE_eTaskGetState == 1 )\n/**\n* @brief  Obtain the state of any thread.\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval  the stae of the thread, states are encoded by the osThreadState enumerated type.\n*/\nosThreadState osThreadGetState(osThreadId thread_id)\n{\n  eTaskState ThreadState;\n  osThreadState result;\n  \n  ThreadState = eTaskGetState(thread_id);\n  \n  switch (ThreadState)\n  {\n  case eRunning :\n    result = osThreadRunning;\n    break;\n  case eReady :\n    result = osThreadReady;\n    break;\n  case eBlocked :\n    result = osThreadBlocked;\n    break;\n  case eSuspended :\n    result = osThreadSuspended;\n    break;\n  case eDeleted :\n    result = osThreadDeleted;\n    break;\n  default:\n    result = osThreadError;\n  } \n  \n  return result;\n}\n#endif /* INCLUDE_eTaskGetState */\n\n#if (INCLUDE_eTaskGetState == 1)\n/**\n* @brief Check if a thread is already suspended or not.\n* @param thread_id thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval status code that indicates the execution status of the function.\n*/\nosStatus osThreadIsSuspended(osThreadId thread_id)\n{\n  if (eTaskGetState(thread_id) == eSuspended)\n    return osOK;\n  else\n    return osErrorOS;\n}\n#endif /* INCLUDE_eTaskGetState */\n/**\n* @brief  Suspend execution of a thread.\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadSuspend (osThreadId thread_id)\n{\n#if (INCLUDE_vTaskSuspend == 1)\n    vTaskSuspend(thread_id);\n  \n  return osOK;\n#else\n  return osErrorResource;\n#endif\n}\n\n/**\n* @brief  Resume execution of a suspended thread.\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadResume (osThreadId thread_id)\n{\n#if (INCLUDE_vTaskSuspend == 1)  \n  if(inHandlerMode())\n  {\n    if (xTaskResumeFromISR(thread_id) == pdTRUE)\n    {\n      portYIELD_FROM_ISR(pdTRUE);\n    }\n  }\n  else\n  {\n    vTaskResume(thread_id);\n  }\n  return osOK;\n#else\n  return osErrorResource;\n#endif\n}\n\n/**\n* @brief  Suspend execution of a all active threads.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadSuspendAll (void)\n{\n  vTaskSuspendAll();\n  \n  return osOK;\n}\n\n/**\n* @brief  Resume execution of a all suspended threads.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadResumeAll (void)\n{\n  if (xTaskResumeAll() == pdTRUE)\n    return osOK;\n  else\n    return osErrorOS;\n  \n}\n\n/**\n* @brief  Delay a task until a specified time\n* @param   PreviousWakeTime   Pointer to a variable that holds the time at which the \n*          task was last unblocked. PreviousWakeTime must be initialised with the current time\n*          prior to its first use (PreviousWakeTime = osKernelSysTick() )\n* @param   millisec    time delay value\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec)\n{\n#if INCLUDE_vTaskDelayUntil\n  TickType_t ticks = (millisec / portTICK_PERIOD_MS);\n  vTaskDelayUntil((TickType_t *) PreviousWakeTime, ticks ? ticks : 1);\n  \n  return osOK;\n#else\n  (void) millisec;\n  (void) PreviousWakeTime;\n  \n  return osErrorResource;\n#endif\n}\n\n/**\n* @brief   Abort the delay for a specific thread\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId   \n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osAbortDelay(osThreadId thread_id)\n{\n#if INCLUDE_xTaskAbortDelay\n  \n  xTaskAbortDelay(thread_id);\n  \n  return osOK;\n#else\n  (void) thread_id;\n  \n  return osErrorResource;\n#endif\n}\n\n/**\n* @brief   Lists all the current threads, along with their current state \n*          and stack usage high water mark.\n* @param   buffer   A buffer into which the above mentioned details\n*          will be written\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadList (uint8_t *buffer)\n{\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) )\n  vTaskList((char *)buffer);\n#endif\n  return osOK;\n}\n\n/**\n* @brief  Receive an item from a queue without removing the item from the queue.\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @param  millisec  timeout value or 0 in case of no time-out.\n* @retval event information that includes status code.\n*/\nosEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec)\n{\n  TickType_t ticks;\n  osEvent event;\n  \n  event.def.message_id = queue_id;\n  \n  if (queue_id == NULL) {\n    event.status = osErrorParameter;\n    return event;\n  }\n  \n  ticks = 0;\n  if (millisec == osWaitForever) {\n    ticks = portMAX_DELAY;\n  }\n  else if (millisec != 0) {\n    ticks = millisec / portTICK_PERIOD_MS;\n    if (ticks == 0) {\n      ticks = 1;\n    }\n  }\n  \n  if (xQueuePeek(queue_id, &event.value.v, ticks) == pdTRUE) \n  {\n    /* We have mail */\n    event.status = osEventMessage;\n  }\n  else \n  {\n    event.status = (ticks == 0) ? osOK : osEventTimeout;\n  }\n  \n  return event;\n}\n\n/**\n* @brief  Get the number of messaged stored in a queue.\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @retval number of messages stored in a queue.\n*/\nuint32_t osMessageWaiting(osMessageQId queue_id)\n{\n  if (inHandlerMode()) {\n    return uxQueueMessagesWaitingFromISR(queue_id);\n  }\n  else\n  {\n    return uxQueueMessagesWaiting(queue_id);\n  }\n}\n\n/**\n* @brief  Get the available space in a message queue.\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @retval available space in a message queue.\n*/\nuint32_t osMessageAvailableSpace(osMessageQId queue_id)  \n{\n  return uxQueueSpacesAvailable(queue_id);\n}\n\n/**\n* @brief Delete a Message Queue\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osMessageDelete (osMessageQId queue_id)\n{\n  if (inHandlerMode()) {\n    return osErrorISR;\n  }\n\n  vQueueDelete(queue_id);\n\n  return osOK; \n}\n\n/**\n* @brief  Create and Initialize a Recursive Mutex\n* @param  mutex_def     mutex definition referenced with \\ref osMutex.\n* @retval  mutex ID for reference by other functions or NULL in case of error..\n*/\nosMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def)\n{\n#if (configUSE_RECURSIVE_MUTEXES == 1)\n#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n  if (mutex_def->controlblock != NULL){\n    return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock );\n  }\n  else {\n    return xSemaphoreCreateRecursiveMutex();\n  }\n#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )\n  return xSemaphoreCreateRecursiveMutexStatic( mutex_def->controlblock );\n#else \n  return xSemaphoreCreateRecursiveMutex();\n#endif\n#else\n  return NULL;\n#endif\t\n}\n\n/**\n* @brief  Release a Recursive Mutex\n* @param   mutex_id      mutex ID obtained by \\ref osRecursiveMutexCreate.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osRecursiveMutexRelease (osMutexId mutex_id)\n{\n#if (configUSE_RECURSIVE_MUTEXES == 1)\n  osStatus result = osOK;\n \n  if (xSemaphoreGiveRecursive(mutex_id) != pdTRUE) \n  {\n    result = osErrorOS;\n  }\n  return result;\n#else\n\treturn osErrorResource;\n#endif\n}\n\n/**\n* @brief  Release a Recursive Mutex\n* @param   mutex_id    mutex ID obtained by \\ref osRecursiveMutexCreate.\n* @param millisec      timeout value or 0 in case of no time-out.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec)\n{\n#if (configUSE_RECURSIVE_MUTEXES == 1)\n  TickType_t ticks;\n  \n  if (mutex_id == NULL)\n  {\n    return osErrorParameter;\n  }\n  \n  ticks = 0;\n  if (millisec == osWaitForever) \n  {\n    ticks = portMAX_DELAY;\n  }\n  else if (millisec != 0) \n  {\n    ticks = millisec / portTICK_PERIOD_MS;\n    if (ticks == 0) \n    {\n      ticks = 1;\n    }\n  }\n  \n  if (xSemaphoreTakeRecursive(mutex_id, ticks) != pdTRUE) \n  {\n    return osErrorOS;\n  }\n  return osOK;\n#else\n\treturn osErrorResource;\n#endif\n}\n\n/**\n* @brief  Returns the current count value of a counting semaphore\n* @param  semaphore_id  semaphore_id ID obtained by \\ref osSemaphoreCreate.\n* @retval  count value\n*/\nuint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id)\n{\n  return uxSemaphoreGetCount(semaphore_id);\n}\n"
  },
  {
    "path": "examples/lib/FreeRTOS/CMSIS_RTOS/cmsis_os.h",
    "content": "/* ----------------------------------------------------------------------\n * $Date:        5. February 2013\n * $Revision:    V1.02\n *\n * Project:      CMSIS-RTOS API\n * Title:        cmsis_os.h header file\n *\n * Version 0.02\n *    Initial Proposal Phase\n * Version 0.03\n *    osKernelStart added, optional feature: main started as thread\n *    osSemaphores have standard behavior\n *    osTimerCreate does not start the timer, added osTimerStart\n *    osThreadPass is renamed to osThreadYield\n * Version 1.01\n *    Support for C++ interface\n *     - const attribute removed from the osXxxxDef_t typedef's\n *     - const attribute added to the osXxxxDef macros\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\n *    Added: osKernelInitialize\n * Version 1.02\n *    Control functions for short timeouts in microsecond resolution:\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\n *    Removed: osSignalGet \n *    \n *  \n *----------------------------------------------------------------------------\n *\n * Portions Copyright  2016 STMicroelectronics International N.V. All rights reserved.\n * Portions Copyright (c) 2013 ARM LIMITED\n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *  - Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *  - Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n *  - Neither the name of ARM  nor the names of its contributors may be used\n *    to endorse or promote products derived from this software without\n *    specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *---------------------------------------------------------------------------*/\n\n /**\n  ******************************************************************************\n  * @file    cmsis_os.h\n  * @author  MCD Application Team\n  * @date    13-July-2017\n  * @brief   Header of cmsis_os.c\n  *          A new set of APIs are added in addition to existing ones, these APIs \n  *          are specific to FreeRTOS.\n  ******************************************************************************\n  * @attention\n  *\n  * Redistribution and use in source and binary forms, with or without \n  * modification, are permitted, provided that the following conditions are met:\n  *\n  * 1. Redistribution of source code must retain the above copyright notice, \n  *    this list of conditions and the following disclaimer.\n  * 2. Redistributions in binary form must reproduce the above copyright notice,\n  *    this list of conditions and the following disclaimer in the documentation\n  *    and/or other materials provided with the distribution.\n  * 3. Neither the name of STMicroelectronics nor the names of other \n  *    contributors to this software may be used to endorse or promote products \n  *    derived from this software without specific written permission.\n  * 4. This software, including modifications and/or derivative works of this \n  *    software, must execute solely and exclusively on microcontroller or\n  *    microprocessor devices manufactured by or for STMicroelectronics.\n  * 5. Redistribution and use of this software other than as permitted under \n  *    this license is void and will automatically terminate your rights under \n  *    this license. \n  *\n  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS \"AS IS\" \n  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT \n  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A \n  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY\n  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT \n  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, \n  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF \n  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING \n  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\t\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"timers.h\"\n#include \"queue.h\"\n#include \"semphr.h\"\n#include \"event_groups.h\"\n\n/**\n\\page cmsis_os_h Header File Template: cmsis_os.h\n\nThe file \\b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).\nEach RTOS that is compliant with CMSIS-RTOS shall provide a specific \\b cmsis_os.h header file that represents\nits implementation.\n\nThe file cmsis_os.h contains:\n - CMSIS-RTOS API function definitions\n - struct definitions for parameters and return types\n - status and priority values used by CMSIS-RTOS API functions\n - macros for defining threads and other kernel objects\n\n\n<b>Name conventions and header file modifications</b>\n\nAll definitions are prefixed with \\b os to give an unique name space for CMSIS-RTOS functions.\nDefinitions that are prefixed \\b os_ are not used in the application code but local to this header file.\nAll definitions and functions that belong to a module are grouped and have a common prefix, i.e. \\b osThread.\n\nDefinitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.\nThese definitions can be specific to the underlying RTOS kernel.\n\nDefinitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer\ncompliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.\n\n\n<b>Function calls from interrupt service routines</b>\n\nThe following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):\n  - \\ref osSignalSet\n  - \\ref osSemaphoreRelease\n  - \\ref osPoolAlloc, \\ref osPoolCAlloc, \\ref osPoolFree\n  - \\ref osMessagePut, \\ref osMessageGet\n  - \\ref osMailAlloc, \\ref osMailCAlloc, \\ref osMailGet, \\ref osMailPut, \\ref osMailFree\n\nFunctions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called\nfrom an ISR context the status code \\b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.\n\nSome CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.\nIf this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \\b osErrorISRRecursive.\n\n\n<b>Define and reference object definitions</b>\n\nWith <b>\\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file\nthat is used throughout a project as shown below:\n\n<i>Header File</i>\n\\code\n#include <cmsis_os.h>                                         // CMSIS RTOS header file\n\n// Thread definition\nextern void thread_sample (void const *argument);             // function prototype\nosThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);\n\n// Pool definition\nosPoolDef(MyPool, 10, long);\n\\endcode\n\n\nThis header file defines all objects when included in a C/C++ source file. When <b>\\#define osObjectsExternal</b> is\npresent before the header file, the objects are defined as external symbols. A single consistent header file can therefore be\nused throughout the whole project.\n\n<i>Example</i>\n\\code\n#include \"osObjects.h\"     // Definition of the CMSIS-RTOS objects\n\\endcode\n\n\\code\n#define osObjectExternal   // Objects will be defined as external symbols\n#include \"osObjects.h\"     // Reference to the CMSIS-RTOS objects\n\\endcode\n\n*/\n\n#ifndef _CMSIS_OS_H\n#define _CMSIS_OS_H\n\n/// \\note MUST REMAIN UNCHANGED: \\b osCMSIS identifies the CMSIS-RTOS API version.\n#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])\n\n/// \\note CAN BE CHANGED: \\b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.\n#define osCMSIS_KERNEL    0x10000\t   ///< RTOS identification and version (main [31:16] .sub [15:0])\n\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelSystemId shall be consistent in every CMSIS-RTOS.\n#define osKernelSystemId \"KERNEL V1.00\"   ///< RTOS identification string\n\n/// \\note MUST REMAIN UNCHANGED: \\b osFeature_xxx shall be consistent in every CMSIS-RTOS.\n#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available\n#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available\n#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available\n#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available\n#define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread\n#define osFeature_Semaphore    1      ///< osFeature_Semaphore function: 1=available, 0=not available\n#define osFeature_Wait         0       ///< osWait function: 1=available, 0=not available\n#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n\n// ==== Enumeration, structures, defines ====\n\n/// Priority used for thread control.\n/// \\note MUST REMAIN UNCHANGED: \\b osPriority shall be consistent in every CMSIS-RTOS.\ntypedef enum  {\n  osPriorityIdle          = -3,          ///< priority: idle (lowest)\n  osPriorityLow           = -2,          ///< priority: low\n  osPriorityBelowNormal   = -1,          ///< priority: below normal\n  osPriorityNormal        =  0,          ///< priority: normal (default)\n  osPriorityAboveNormal   = +1,          ///< priority: above normal\n  osPriorityHigh          = +2,          ///< priority: high\n  osPriorityRealtime      = +3,          ///< priority: realtime (highest)\n  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority\n} osPriority;\n\n/// Timeout value.\n/// \\note MUST REMAIN UNCHANGED: \\b osWaitForever shall be consistent in every CMSIS-RTOS.\n#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value\n\n/// Status code values returned by CMSIS-RTOS functions.\n/// \\note MUST REMAIN UNCHANGED: \\b osStatus shall be consistent in every CMSIS-RTOS.\ntypedef enum  {\n  osOK                    =     0,       ///< function completed; no error or event occurred.\n  osEventSignal           =  0x08,       ///< function completed; signal event occurred.\n  osEventMessage          =  0x10,       ///< function completed; message event occurred.\n  osEventMail             =  0x20,       ///< function completed; mail event occurred.\n  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.\n  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.\n  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.\n  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.\n  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.\n  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.\n  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorValue            =  0x86,       ///< value of a parameter is out of range.\n  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.\n  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.\n} osStatus;\n\n#if ( INCLUDE_eTaskGetState == 1 )\n/* Thread state returned by osThreadGetState */\ntypedef enum {\n\tosThreadRunning   = 0x0,\t      /* A thread is querying the state of itself, so must be running. */\n\tosThreadReady     = 0x1 ,\t\t\t        /* The thread being queried is in a read or pending ready list. */\n\tosThreadBlocked   = 0x2,\t\t        /* The thread being queried is in the Blocked state. */\n\tosThreadSuspended = 0x3,\t      /* The thread being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */\n\tosThreadDeleted   = 0x4,\t\t          /* The thread being queried has been deleted, but its TCB has not yet been freed. */   \n  osThreadError     = 0x7FFFFFFF\n} osThreadState;\n#endif /* INCLUDE_eTaskGetState */\n\n/// Timer type value for the timer definition.\n/// \\note MUST REMAIN UNCHANGED: \\b os_timer_type shall be consistent in every CMSIS-RTOS.\ntypedef enum  {\n  osTimerOnce             =     0,       ///< one-shot timer\n  osTimerPeriodic         =     1        ///< repeating timer\n} os_timer_type;\n\n/// Entry point of a thread.\n/// \\note MUST REMAIN UNCHANGED: \\b os_pthread shall be consistent in every CMSIS-RTOS.\ntypedef void (*os_pthread) (void const *argument);\n\n/// Entry point of a timer call back function.\n/// \\note MUST REMAIN UNCHANGED: \\b os_ptimer shall be consistent in every CMSIS-RTOS.\ntypedef void (*os_ptimer) (void const *argument);\n\n// >>> the following data type definitions may shall adapted towards a specific RTOS\n\n/// Thread ID identifies the thread (pointer to a thread control block).\n/// \\note CAN BE CHANGED: \\b os_thread_cb is implementation specific in every CMSIS-RTOS.\ntypedef TaskHandle_t osThreadId;\n\n/// Timer ID identifies the timer (pointer to a timer control block).\n/// \\note CAN BE CHANGED: \\b os_timer_cb is implementation specific in every CMSIS-RTOS.\ntypedef TimerHandle_t osTimerId;\n\n/// Mutex ID identifies the mutex (pointer to a mutex control block).\n/// \\note CAN BE CHANGED: \\b os_mutex_cb is implementation specific in every CMSIS-RTOS.\ntypedef SemaphoreHandle_t osMutexId;\n\n/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).\n/// \\note CAN BE CHANGED: \\b os_semaphore_cb is implementation specific in every CMSIS-RTOS.\ntypedef SemaphoreHandle_t osSemaphoreId;\n\n/// Pool ID identifies the memory pool (pointer to a memory pool control block).\n/// \\note CAN BE CHANGED: \\b os_pool_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_pool_cb *osPoolId;\n\n/// Message ID identifies the message queue (pointer to a message queue control block).\n/// \\note CAN BE CHANGED: \\b os_messageQ_cb is implementation specific in every CMSIS-RTOS.\ntypedef QueueHandle_t osMessageQId;\n\n/// Mail ID identifies the mail queue (pointer to a mail queue control block).\n/// \\note CAN BE CHANGED: \\b os_mailQ_cb is implementation specific in every CMSIS-RTOS.\ntypedef struct os_mailQ_cb *osMailQId;\n\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\ntypedef StaticTask_t               osStaticThreadDef_t;\ntypedef StaticTimer_t              osStaticTimerDef_t;\ntypedef StaticSemaphore_t          osStaticMutexDef_t;         \ntypedef StaticSemaphore_t          osStaticSemaphoreDef_t;\ntypedef StaticQueue_t              osStaticMessageQDef_t;\n\n#endif\n\n\n\n\n/// Thread Definition structure contains startup information of a thread.\n/// \\note CAN BE CHANGED: \\b os_thread_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_thread_def  {\n  char                   *name;        ///< Thread name \n  os_pthread             pthread;      ///< start address of thread function\n  osPriority             tpriority;    ///< initial thread priority\n  uint32_t               instances;    ///< maximum number of instances of that thread function\n  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n  uint32_t               *buffer;      ///< stack buffer for static allocation; NULL for dynamic allocation\n  osStaticThreadDef_t    *controlblock;     ///< control block to hold thread's data for static allocation; NULL for dynamic allocation\n#endif\n} osThreadDef_t;\n\n/// Timer Definition structure contains timer parameters.\n/// \\note CAN BE CHANGED: \\b os_timer_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_timer_def  {\n  os_ptimer                 ptimer;    ///< start address of a timer function\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n  osStaticTimerDef_t        *controlblock;      ///< control block to hold timer's data for static allocation; NULL for dynamic allocation\n#endif\n} osTimerDef_t;\n\n/// Mutex Definition structure contains setup information for a mutex.\n/// \\note CAN BE CHANGED: \\b os_mutex_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_mutex_def  {\n  uint32_t                   dummy;    ///< dummy value.\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n  osStaticMutexDef_t         *controlblock;      ///< control block for static allocation; NULL for dynamic allocation\n#endif\n} osMutexDef_t;\n\n/// Semaphore Definition structure contains setup information for a semaphore.\n/// \\note CAN BE CHANGED: \\b os_semaphore_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_semaphore_def  {\n  uint32_t                   dummy;    ///< dummy value.\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n  osStaticSemaphoreDef_t     *controlblock;      ///< control block for static allocation; NULL for dynamic allocation\n#endif\n} osSemaphoreDef_t;\n\n/// Definition structure for memory block allocation.\n/// \\note CAN BE CHANGED: \\b os_pool_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_pool_def  {\n  uint32_t                 pool_sz;    ///< number of items (elements) in the pool\n  uint32_t                 item_sz;    ///< size of an item\n  void                       *pool;    ///< pointer to memory for pool\n} osPoolDef_t;\n\n/// Definition structure for message queue.\n/// \\note CAN BE CHANGED: \\b os_messageQ_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_messageQ_def  {\n  uint32_t                queue_sz;    ///< number of elements in the queue\n  uint32_t                item_sz;    ///< size of an item\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n  uint8_t                 *buffer;      ///< buffer for static allocation; NULL for dynamic allocation\n  osStaticMessageQDef_t   *controlblock;     ///< control block to hold queue's data for static allocation; NULL for dynamic allocation\n#endif\n  //void                       *pool;    ///< memory array for messages\n} osMessageQDef_t;\n\n/// Definition structure for mail queue.\n/// \\note CAN BE CHANGED: \\b os_mailQ_def is implementation specific in every CMSIS-RTOS.\ntypedef struct os_mailQ_def  {\n  uint32_t                queue_sz;    ///< number of elements in the queue\n  uint32_t                 item_sz;    ///< size of an item\n  struct os_mailQ_cb **cb;\n} osMailQDef_t;\n\n/// Event structure contains detailed information about an event.\n/// \\note MUST REMAIN UNCHANGED: \\b os_event shall be consistent in every CMSIS-RTOS.\n///       However the struct may be extended at the end.\ntypedef struct  {\n  osStatus                 status;     ///< status code: event or error information\n  union  {\n    uint32_t                    v;     ///< message as 32-bit value\n    void                       *p;     ///< message or mail as void pointer\n    int32_t               signals;     ///< signal flags\n  } value;                             ///< event value\n  union  {\n    osMailQId             mail_id;     ///< mail id obtained by \\ref osMailCreate\n    osMessageQId       message_id;     ///< message id obtained by \\ref osMessageCreate\n  } def;                               ///< event definition\n} osEvent;\n\n\n//  ==== Kernel Control Functions ====\n\n/// Initialize the RTOS Kernel for creating objects.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelInitialize shall be consistent in every CMSIS-RTOS.\nosStatus osKernelInitialize (void);\n\n/// Start the RTOS Kernel.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelStart shall be consistent in every CMSIS-RTOS.\nosStatus osKernelStart (void);\n\n/// Check if the RTOS kernel is already started.\n/// \\note MUST REMAIN UNCHANGED: \\b osKernelRunning shall be consistent in every CMSIS-RTOS.\n/// \\return 0 RTOS is not started, 1 RTOS is started.\nint32_t osKernelRunning(void);\n\n#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available\n\n/// Get the RTOS kernel system timer counter \n/// \\note MUST REMAIN UNCHANGED: \\b osKernelSysTick shall be consistent in every CMSIS-RTOS.\n/// \\return RTOS kernel system timer as 32-bit value \nuint32_t osKernelSysTick (void);\n\n/// The RTOS kernel system timer frequency in Hz\n/// \\note Reflects the system timer setting and is typically defined in a configuration file.\n#define osKernelSysTickFrequency      (configTICK_RATE_HZ)\n\n/// Convert a microseconds value to a RTOS kernel system timer value.\n/// \\param         microsec     time value in microseconds.\n/// \\return time value normalized to the \\ref osKernelSysTickFrequency\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)\n\n#endif    // System Timer available\n\n//  ==== Thread Management ====\n\n/// Create a Thread Definition with function, priority, and stack requirements.\n/// \\param         name         name of the thread function.\n/// \\param         priority     initial priority of the thread function.\n/// \\param         instances    number of possible thread instances.\n/// \\param         stacksz      stack size (in bytes) requirements for the thread function.\n/// \\note CAN BE CHANGED: The parameters to \\b osThreadDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osThreadDef(name, thread, priority, instances, stacksz)  \\\nextern const osThreadDef_t os_thread_def_##name\n#else                            // define the object\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n#define osThreadDef(name, thread, priority, instances, stacksz)  \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ #name, (thread), (priority), (instances), (stacksz), NULL, NULL }\n\n#define osThreadStaticDef(name, thread, priority, instances, stacksz, buffer, control)  \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ #name, (thread), (priority), (instances), (stacksz), (buffer), (control) }\n#else //configSUPPORT_STATIC_ALLOCATION == 0\n\n#define osThreadDef(name, thread, priority, instances, stacksz)  \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ #name, (thread), (priority), (instances), (stacksz)}\n#endif\n#endif\n\n/// Access a Thread definition.\n/// \\param         name          name of the thread definition object.\n/// \\note CAN BE CHANGED: The parameter to \\b osThread shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osThread(name)  \\\n&os_thread_def_##name\n\n/// Create a thread and add it to Active Threads and set it to state READY.\n/// \\param[in]     thread_def    thread definition referenced with \\ref osThread.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\return thread ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadCreate shall be consistent in every CMSIS-RTOS.\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);\n\n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadGetId shall be consistent in every CMSIS-RTOS.\nosThreadId osThreadGetId (void);\n\n/// Terminate execution of a thread and remove it from Active Threads.\n/// \\param[in]     thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadTerminate shall be consistent in every CMSIS-RTOS.\nosStatus osThreadTerminate (osThreadId thread_id);\n\n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadYield shall be consistent in every CMSIS-RTOS.\nosStatus osThreadYield (void);\n\n/// Change priority of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadSetPriority shall be consistent in every CMSIS-RTOS.\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);\n\n/// Get current priority of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return current priority value of the thread function.\n/// \\note MUST REMAIN UNCHANGED: \\b osThreadGetPriority shall be consistent in every CMSIS-RTOS.\nosPriority osThreadGetPriority (osThreadId thread_id);\n\n\n//  ==== Generic Wait Functions ====\n\n/// Wait for Timeout (Time Delay).\n/// \\param[in]     millisec      time delay value\n/// \\return status code that indicates the execution status of the function.\nosStatus osDelay (uint32_t millisec);\n\n#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available\n\n/// Wait for Signal, Message, Mail, or Timeout.\n/// \\param[in] millisec          timeout value or 0 in case of no time-out\n/// \\return event that contains signal, message, or mail information or error code.\n/// \\note MUST REMAIN UNCHANGED: \\b osWait shall be consistent in every CMSIS-RTOS.\nosEvent osWait (uint32_t millisec);\n\n#endif  // Generic Wait available\n\n\n//  ==== Timer Management Functions ====\n/// Define a Timer object.\n/// \\param         name          name of the timer object.\n/// \\param         function      name of the timer call back function.\n/// \\note CAN BE CHANGED: The parameter to \\b osTimerDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osTimerDef(name, function)  \\\nextern const osTimerDef_t os_timer_def_##name\n#else                            // define the object\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 ) \n#define osTimerDef(name, function)  \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function), NULL }\n\n#define osTimerStaticDef(name, function, control)  \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function), (control) }\n#else //configSUPPORT_STATIC_ALLOCATION == 0\n#define osTimerDef(name, function)  \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function) }\n#endif\n#endif\n\n/// Access a Timer definition.\n/// \\param         name          name of the timer object.\n/// \\note CAN BE CHANGED: The parameter to \\b osTimer shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osTimer(name) \\\n&os_timer_def_##name\n\n/// Create a timer.\n/// \\param[in]     timer_def     timer object referenced with \\ref osTimer.\n/// \\param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer call back function.\n/// \\return timer ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerCreate shall be consistent in every CMSIS-RTOS.\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);\n\n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\param[in]     millisec      time delay value of the timer.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerStart shall be consistent in every CMSIS-RTOS.\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec);\n\n/// Stop the timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerStop shall be consistent in every CMSIS-RTOS.\nosStatus osTimerStop (osTimerId timer_id);\n\n/// Delete a timer that was created by \\ref osTimerCreate.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osTimerDelete shall be consistent in every CMSIS-RTOS.\nosStatus osTimerDelete (osTimerId timer_id);\n\n\n//  ==== Signal Management ====\n\n/// Set the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that should be set.\n/// \\return osOK if successful, osErrorOS if failed.\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalSet shall be consistent in every CMSIS-RTOS.\nint32_t osSignalSet (osThreadId thread_id, int32_t signals);\n\n/// Clear the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that shall be cleared.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalClear shall be consistent in every CMSIS-RTOS.\nint32_t osSignalClear (osThreadId thread_id, int32_t signals);\n\n/// Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\n/// \\param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\n/// \\return event flag information or error code.\n/// \\note MUST REMAIN UNCHANGED: \\b osSignalWait shall be consistent in every CMSIS-RTOS.\nosEvent osSignalWait (int32_t signals, uint32_t millisec);\n\n\n//  ==== Mutex Management ====\n\n/// Define a Mutex.\n/// \\param         name          name of the mutex object.\n/// \\note CAN BE CHANGED: The parameter to \\b osMutexDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMutexDef(name)  \\\nextern const osMutexDef_t os_mutex_def_##name\n#else                            // define the object\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n#define osMutexDef(name)  \\\nconst osMutexDef_t os_mutex_def_##name = { 0, NULL }\n\n#define osMutexStaticDef(name, control)  \\\nconst osMutexDef_t os_mutex_def_##name = { 0, (control) }\n#else //configSUPPORT_STATIC_ALLOCATION == 0\n#define osMutexDef(name)  \\\nconst osMutexDef_t os_mutex_def_##name = { 0 }\n\n#endif\n\n#endif\n\n/// Access a Mutex definition.\n/// \\param         name          name of the mutex object.\n/// \\note CAN BE CHANGED: The parameter to \\b osMutex shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMutex(name)  \\\n&os_mutex_def_##name\n\n/// Create and Initialize a Mutex object.\n/// \\param[in]     mutex_def     mutex definition referenced with \\ref osMutex.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexCreate shall be consistent in every CMSIS-RTOS.\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def);\n\n/// Wait until a Mutex becomes available.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexWait shall be consistent in every CMSIS-RTOS.\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);\n\n/// Release a Mutex that was obtained by \\ref osMutexWait.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexRelease shall be consistent in every CMSIS-RTOS.\nosStatus osMutexRelease (osMutexId mutex_id);\n\n/// Delete a Mutex that was created by \\ref osMutexCreate.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMutexDelete shall be consistent in every CMSIS-RTOS.\nosStatus osMutexDelete (osMutexId mutex_id);\n\n\n//  ==== Semaphore Management Functions ====\n\n#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available\n\n/// Define a Semaphore object.\n/// \\param         name          name of the semaphore object.\n/// \\note CAN BE CHANGED: The parameter to \\b osSemaphoreDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osSemaphoreDef(name)  \\\nextern const osSemaphoreDef_t os_semaphore_def_##name\n#else                            // define the object\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n#define osSemaphoreDef(name)  \\\nconst osSemaphoreDef_t os_semaphore_def_##name = { 0, NULL }\n\n#define osSemaphoreStaticDef(name, control)  \\\nconst osSemaphoreDef_t os_semaphore_def_##name = { 0, (control) }\n\n#else //configSUPPORT_STATIC_ALLOCATION == 0\n#define osSemaphoreDef(name)  \\\nconst osSemaphoreDef_t os_semaphore_def_##name = { 0 }\n#endif\n#endif\n\n/// Access a Semaphore definition.\n/// \\param         name          name of the semaphore object.\n/// \\note CAN BE CHANGED: The parameter to \\b osSemaphore shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osSemaphore(name)  \\\n&os_semaphore_def_##name\n\n/// Create and Initialize a Semaphore object used for managing resources.\n/// \\param[in]     semaphore_def semaphore definition referenced with \\ref osSemaphore.\n/// \\param[in]     count         number of available resources.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);\n\n/// Wait until a Semaphore token becomes available.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\n/// \\return number of available tokens, or -1 in case of incorrect parameters.\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreWait shall be consistent in every CMSIS-RTOS.\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);\n\n/// Release a Semaphore token.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id);\n\n/// Delete a Semaphore that was created by \\ref osSemaphoreCreate.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id);\n\n#endif     // Semaphore available\n\n\n//  ==== Memory Pool Management Functions ====\n\n#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available\n\n/// \\brief Define a Memory Pool.\n/// \\param         name          name of the memory pool.\n/// \\param         no            maximum number of blocks (objects) in the memory pool.\n/// \\param         type          data type of a single block (object).\n/// \\note CAN BE CHANGED: The parameter to \\b osPoolDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osPoolDef(name, no, type)   \\\nextern const osPoolDef_t os_pool_def_##name\n#else                            // define the object\n#define osPoolDef(name, no, type)   \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), NULL }\n#endif\n\n/// \\brief Access a Memory Pool definition.\n/// \\param         name          name of the memory pool\n/// \\note CAN BE CHANGED: The parameter to \\b osPool shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osPool(name) \\\n&os_pool_def_##name\n\n/// Create and Initialize a memory pool.\n/// \\param[in]     pool_def      memory pool definition referenced with \\ref osPool.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolCreate shall be consistent in every CMSIS-RTOS.\nosPoolId osPoolCreate (const osPoolDef_t *pool_def);\n\n/// Allocate a memory block from a memory pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolAlloc shall be consistent in every CMSIS-RTOS.\nvoid *osPoolAlloc (osPoolId pool_id);\n\n/// Allocate a memory block from a memory pool and set memory block to zero.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolCAlloc shall be consistent in every CMSIS-RTOS.\nvoid *osPoolCAlloc (osPoolId pool_id);\n\n/// Return an allocated memory block back to a specific memory pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\param[in]     block         address of the allocated memory block that is returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osPoolFree shall be consistent in every CMSIS-RTOS.\nosStatus osPoolFree (osPoolId pool_id, void *block);\n\n#endif   // Memory Pool Management available\n\n\n//  ==== Message Queue Management Functions ====\n\n#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available\n\n/// \\brief Create a Message Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of messages in the queue.\n/// \\param         type          data type of a single message element (for debugger).\n/// \\note CAN BE CHANGED: The parameter to \\b osMessageQDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMessageQDef(name, queue_sz, type)   \\\nextern const osMessageQDef_t os_messageQ_def_##name\n#else                            // define the object\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n#define osMessageQDef(name, queue_sz, type)   \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), sizeof (type), NULL, NULL  }\n\n#define osMessageQStaticDef(name, queue_sz, type, buffer, control)   \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), sizeof (type) , (buffer), (control)}\n#else //configSUPPORT_STATIC_ALLOCATION == 1\n#define osMessageQDef(name, queue_sz, type)   \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), sizeof (type) }\n\n#endif\n#endif\n\n/// \\brief Access a Message Queue Definition.\n/// \\param         name          name of the queue\n/// \\note CAN BE CHANGED: The parameter to \\b osMessageQ shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMessageQ(name) \\\n&os_messageQ_def_##name\n\n/// Create and Initialize a Message Queue.\n/// \\param[in]     queue_def     queue definition referenced with \\ref osMessageQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMessageCreate shall be consistent in every CMSIS-RTOS.\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\n\n/// Put a Message to a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     info          message information.\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMessagePut shall be consistent in every CMSIS-RTOS.\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);\n\n/// Get a Message or Wait for a Message from a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out.\n/// \\return event information that includes status code.\n/// \\note MUST REMAIN UNCHANGED: \\b osMessageGet shall be consistent in every CMSIS-RTOS.\nosEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);\n\n#endif     // Message Queues available\n\n\n//  ==== Mail Queue Management Functions ====\n\n#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available\n\n/// \\brief Create a Mail Queue Definition.\n/// \\param         name          name of the queue\n/// \\param         queue_sz      maximum number of messages in queue\n/// \\param         type          data type of a single message element\n/// \\note CAN BE CHANGED: The parameter to \\b osMailQDef shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#if defined (osObjectsExternal)  // object is external\n#define osMailQDef(name, queue_sz, type) \\\nextern struct os_mailQ_cb *os_mailQ_cb_##name \\\nextern osMailQDef_t os_mailQ_def_##name\n#else                            // define the object\n#define osMailQDef(name, queue_sz, type) \\\nstruct os_mailQ_cb *os_mailQ_cb_##name; \\\nconst osMailQDef_t os_mailQ_def_##name =  \\\n{ (queue_sz), sizeof (type), (&os_mailQ_cb_##name) }\n#endif\n\n/// \\brief Access a Mail Queue Definition.\n/// \\param         name          name of the queue\n/// \\note CAN BE CHANGED: The parameter to \\b osMailQ shall be consistent but the\n///       macro body is implementation specific in every CMSIS-RTOS.\n#define osMailQ(name)  \\\n&os_mailQ_def_##name\n\n/// Create and Initialize mail queue.\n/// \\param[in]     queue_def     reference to the mail queue definition obtain with \\ref osMailQ\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return mail queue ID for reference by other functions or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailCreate shall be consistent in every CMSIS-RTOS.\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);\n\n/// Allocate a memory block from a mail.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailAlloc shall be consistent in every CMSIS-RTOS.\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec);\n\n/// Allocate a memory block from a mail and set memory block to zero.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailCAlloc shall be consistent in every CMSIS-RTOS.\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec);\n\n/// Put a mail to a queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          memory block previously allocated with \\ref osMailAlloc or \\ref osMailCAlloc.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailPut shall be consistent in every CMSIS-RTOS.\nosStatus osMailPut (osMailQId queue_id, void *mail);\n\n/// Get a mail from a queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      timeout value or 0 in case of no time-out\n/// \\return event that contains mail information or error code.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailGet shall be consistent in every CMSIS-RTOS.\nosEvent osMailGet (osMailQId queue_id, uint32_t millisec);\n\n/// Free a memory block from a mail.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to the memory block that was obtained with \\ref osMailGet.\n/// \\return status code that indicates the execution status of the function.\n/// \\note MUST REMAIN UNCHANGED: \\b osMailFree shall be consistent in every CMSIS-RTOS.\nosStatus osMailFree (osMailQId queue_id, void *mail);\n\n#endif  // Mail Queues available\n\n/*************************** Additional specific APIs to Free RTOS ************/\n/**\n* @brief  Handles the tick increment\n* @param  none.\n* @retval none.\n*/\nvoid osSystickHandler(void);\n\n#if ( INCLUDE_eTaskGetState == 1 )\n/**\n* @brief  Obtain the state of any thread.\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval  the stae of the thread, states are encoded by the osThreadState enumerated type.\n*/\nosThreadState osThreadGetState(osThreadId thread_id);\n#endif /* INCLUDE_eTaskGetState */\n\n#if ( INCLUDE_eTaskGetState == 1 )\n/**\n* @brief Check if a thread is already suspended or not.\n* @param thread_id thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval status code that indicates the execution status of the function.\n*/\n\nosStatus osThreadIsSuspended(osThreadId thread_id);\n\n#endif /* INCLUDE_eTaskGetState */\n\n/**\n* @brief  Suspend execution of a thread.\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadSuspend (osThreadId thread_id);\n\n/**\n* @brief  Resume execution of a suspended thread.\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadResume (osThreadId thread_id);\n\n/**\n* @brief  Suspend execution of a all active threads.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadSuspendAll (void);\n\n/**\n* @brief  Resume execution of a all suspended threads.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadResumeAll (void);\n\n/**\n* @brief  Delay a task until a specified time\n* @param   PreviousWakeTime   Pointer to a variable that holds the time at which the \n*          task was last unblocked. PreviousWakeTime must be initialised with the current time\n*          prior to its first use (PreviousWakeTime = osKernelSysTick() )\n* @param   millisec    time delay value\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osDelayUntil (uint32_t *PreviousWakeTime, uint32_t millisec);\n\n/**\n* @brief   Abort the delay for a specific thread\n* @param   thread_id   thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId   \n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osAbortDelay(osThreadId thread_id);\n\n/**\n* @brief   Lists all the current threads, along with their current state \n*          and stack usage high water mark.\n* @param   buffer   A buffer into which the above mentioned details\n*          will be written\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osThreadList (uint8_t *buffer);\n\n/**\n* @brief  Receive an item from a queue without removing the item from the queue.\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @param  millisec  timeout value or 0 in case of no time-out.\n* @retval event information that includes status code.\n*/\nosEvent osMessagePeek (osMessageQId queue_id, uint32_t millisec);\n\n/**\n* @brief  Get the number of messaged stored in a queue.\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @retval number of messages stored in a queue.\n*/\nuint32_t osMessageWaiting(osMessageQId queue_id);\n\n/**\n* @brief  Get the available space in a message queue.\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @retval available space in a message queue.\n*/\nuint32_t osMessageAvailableSpace(osMessageQId queue_id);\n\n/**\n* @brief Delete a Message Queue\n* @param  queue_id  message queue ID obtained with \\ref osMessageCreate.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osMessageDelete (osMessageQId queue_id);\n\n/**\n* @brief  Create and Initialize a Recursive Mutex\n* @param  mutex_def     mutex definition referenced with \\ref osMutex.\n* @retval  mutex ID for reference by other functions or NULL in case of error..\n*/\nosMutexId osRecursiveMutexCreate (const osMutexDef_t *mutex_def);\n\n/**\n* @brief  Release a Recursive Mutex\n* @param   mutex_id      mutex ID obtained by \\ref osRecursiveMutexCreate.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osRecursiveMutexRelease (osMutexId mutex_id);\n\n/**\n* @brief  Release a Recursive Mutex\n* @param   mutex_id    mutex ID obtained by \\ref osRecursiveMutexCreate.\n* @param millisec      timeout value or 0 in case of no time-out.\n* @retval  status code that indicates the execution status of the function.\n*/\nosStatus osRecursiveMutexWait (osMutexId mutex_id, uint32_t millisec);\n\n/**\n* @brief  Returns the current count value of a counting semaphore\n* @param   semaphore_id  semaphore_id ID obtained by \\ref osSemaphoreCreate.\n* @retval  count value\n*/\nuint32_t osSemaphoreGetCount(osSemaphoreId semaphore_id);\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif  // _CMSIS_OS_H\n"
  },
  {
    "path": "examples/lib/FreeRTOS/CMSIS_RTOS/cpu_utils.c",
    "content": "/**\n  ******************************************************************************\n  * @file    cpu_utils.c\n  * @author  MCD Application Team\n  * @version V1.1.0\n  * @date    20-November-2014\n  * @brief   Utilities for CPU Load calculation\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */ \n\n/********************** NOTES **********************************************\nTo use this module, the following steps should be followed :\n\n1- in the _OS_Config.h file (ex. FreeRTOSConfig.h) enable the following macros : \n      - #define configUSE_IDLE_HOOK        1\n      - #define configUSE_TICK_HOOK        1\n\n2- in the _OS_Config.h define the following macros : \n      - #define traceTASK_SWITCHED_IN()  extern void StartIdleMonitor(void); \\\n                                         StartIdleMonitor()\n      - #define traceTASK_SWITCHED_OUT() extern void EndIdleMonitor(void); \\\n                                         EndIdleMonitor()\n*******************************************************************************/\n\n\n/* Includes ------------------------------------------------------------------*/\n#include \"cpu_utils.h\"\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\nxTaskHandle    xIdleHandle = NULL;\nvolatile uint32_t  osCPU_Usage = 0; \nuint32_t       osCPU_IdleStartTime = 0; \nuint32_t       osCPU_IdleSpentTime = 0; \nuint32_t       osCPU_TotalIdleTime = 0; \n\n/* Private functions ---------------------------------------------------------*/\n/**\n  * @brief  Application Idle Hook\n  * @param  None \n  * @retval None\n  */\nvoid vApplicationIdleHook(void) \n{\n  if( xIdleHandle == NULL )\n  {\n    /* Store the handle to the idle task. */\n    xIdleHandle = xTaskGetCurrentTaskHandle();\n  }\n}\n\n/**\n  * @brief  Application Idle Hook\n  * @param  None \n  * @retval None\n  */\nvoid vApplicationTickHook (void)\n{\n  static int tick = 0;\n  \n  if(tick ++ > CALCULATION_PERIOD)\n  {\n    tick = 0;\n    \n    if(osCPU_TotalIdleTime > 1000)\n    {\n      osCPU_TotalIdleTime = 1000;\n    }\n    osCPU_Usage = (100 - (osCPU_TotalIdleTime * 100) / CALCULATION_PERIOD);\n    osCPU_TotalIdleTime = 0;\n  }\n}\n\n/**\n  * @brief  Start Idle monitor\n  * @param  None \n  * @retval None\n  */\nvoid StartIdleMonitor (void)\n{\n  if( xTaskGetCurrentTaskHandle() == xIdleHandle ) \n  {\n    osCPU_IdleStartTime = xTaskGetTickCountFromISR();\n  }\n}\n\n/**\n  * @brief  Stop Idle monitor\n  * @param  None \n  * @retval None\n  */\nvoid EndIdleMonitor (void)\n{\n  if( xTaskGetCurrentTaskHandle() == xIdleHandle )\n  {\n    /* Store the handle to the idle task. */\n    osCPU_IdleSpentTime = xTaskGetTickCountFromISR() - osCPU_IdleStartTime;\n    osCPU_TotalIdleTime += osCPU_IdleSpentTime; \n  }\n}\n\n/**\n  * @brief  Stop Idle monitor\n  * @param  None \n  * @retval None\n  */\nuint16_t osGetCPUUsage (void)\n{\n  return (uint16_t)osCPU_Usage;\n}\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/FreeRTOS/CMSIS_RTOS/cpu_utils.h",
    "content": "/**\n  ******************************************************************************\n  * @file    cpu_utils.h\n  * @author  MCD Application Team\n  * @version V1.1.0\n  * @date    20-November-2014\n  * @brief   Header for cpu_utils module\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef _CPU_UTILS_H__\n#define _CPU_UTILS_H__\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"cmsis_os.h\"\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Exported variables --------------------------------------------------------*/\n/* Exported macro ------------------------------------------------------------*/\n#define CALCULATION_PERIOD    1000\n\n/* Exported functions ------------------------------------------------------- */\nuint16_t osGetCPUUsage (void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _CPU_UTILS_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/FreeRTOS/CMSIS_RTOS_V2/cmsis_os.h",
    "content": "/* --------------------------------------------------------------------------\n * Portions Copyright  2017 STMicroelectronics International N.V. All rights reserved.\n * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.\n * --------------------------------------------------------------------------\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * Project:      CMSIS-RTOS API\n * Title:        cmsis_os.h header file\n *\n * Version 0.02\n *    Initial Proposal Phase\n * Version 0.03\n *    osKernelStart added, optional feature: main started as thread\n *    osSemaphores have standard behavior\n *    osTimerCreate does not start the timer, added osTimerStart\n *    osThreadPass is renamed to osThreadYield\n * Version 1.01\n *    Support for C++ interface\n *     - const attribute removed from the osXxxxDef_t typedefs\n *     - const attribute added to the osXxxxDef macros\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\n *    Added: osKernelInitialize\n * Version 1.02\n *    Control functions for short timeouts in microsecond resolution:\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\n *    Removed: osSignalGet\n * Version 2.0.0\n *    OS objects creation without macros (dynamic creation and resource allocation):\n *     - added: osXxxxNew functions which replace osXxxxCreate\n *     - added: osXxxxAttr_t structures\n *     - deprecated: osXxxxCreate functions, osXxxxDef_t structures\n *     - deprecated: osXxxxDef and osXxxx macros\n *    osStatus codes simplified and renamed to osStatus_t\n *    osEvent return structure deprecated\n *    Kernel:\n *     - added: osKernelInfo_t and osKernelGetInfo\n *     - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)\n *     - added: osKernelLock, osKernelUnlock\n *     - added: osKernelSuspend, osKernelResume\n *     - added: osKernelGetTickCount, osKernelGetTickFreq\n *     - renamed osKernelSysTick to osKernelGetSysTimerCount\n *     - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq\n *     - deprecated osKernelSysTickMicroSec\n *    Thread:\n *     - extended number of thread priorities\n *     - renamed osPrioriry to osPrioriry_t\n *     - replaced osThreadCreate with osThreadNew\n *     - added: osThreadGetName\n *     - added: osThreadState_t and osThreadGetState\n *     - added: osThreadGetStackSize, osThreadGetStackSpace\n *     - added: osThreadSuspend, osThreadResume\n *     - added: osThreadJoin, osThreadDetach, osThreadExit\n *     - added: osThreadGetCount, osThreadEnumerate\n *     - added: Thread Flags (moved from Signals)\n *    Signals:\n *     - renamed osSignals to osThreadFlags (moved to Thread Flags)\n *     - changed return value of Set/Clear/Wait functions\n *     - Clear function limited to current running thread\n *     - extended Wait function (options)\n *     - added: osThreadFlagsGet\n *    Event Flags:\n *     - added new independent object for handling Event Flags\n *    Delay and Wait functions:\n *     - added: osDelayUntil\n *     - deprecated: osWait\n *    Timer:\n *     - replaced osTimerCreate with osTimerNew\n *     - added: osTimerGetName, osTimerIsRunning\n *    Mutex:\n *     - extended: attributes (Recursive, Priority Inherit, Robust)\n *     - replaced osMutexCreate with osMutexNew\n *     - renamed osMutexWait to osMutexAcquire\n *     - added: osMutexGetName, osMutexGetOwner\n *    Semaphore:\n *     - extended: maximum and initial token count\n *     - replaced osSemaphoreCreate with osSemaphoreNew\n *     - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)\n *     - added: osSemaphoreGetName, osSemaphoreGetCount\n *    Memory Pool:\n *     - using osMemoryPool prefix instead of osPool\n *     - replaced osPoolCreate with osMemoryPoolNew\n *     - extended osMemoryPoolAlloc (timeout)\n *     - added: osMemoryPoolGetName\n *     - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize\n *     - added: osMemoryPoolGetCount, osMemoryPoolGetSpace\n *     - added: osMemoryPoolDelete\n *     - deprecated: osPoolCAlloc\n *    Message Queue:\n *     - extended: fixed size message instead of a single 32-bit value\n *     - using osMessageQueue prefix instead of osMessage\n *     - replaced osMessageCreate with osMessageQueueNew\n *     - updated: osMessageQueuePut, osMessageQueueGet\n *     - added: osMessageQueueGetName\n *     - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize\n *     - added: osMessageQueueGetCount, osMessageQueueGetSpace\n *     - added: osMessageQueueReset, osMessageQueueDelete\n *    Mail Queue:\n *     - deprecated (superseded by extended Message Queue functionality)\n * Version 2.1.0\n *    Support for critical and uncritical sections (nesting safe):\n *    - updated: osKernelLock, osKernelUnlock\n *    - added: osKernelRestoreLock\n *    Updated Thread and Event Flags:\n *    - changed flags parameter and return type from int32_t to uint32_t\n *---------------------------------------------------------------------------*/\n\n#ifndef CMSIS_OS_H_\n#define CMSIS_OS_H_\n\n#define osCMSIS             0x20001U    ///< API version (main[31:16].sub[15:0])\n\n#define osCMSIS_FreeRTOS    0xA0001U    ///< RTOS identification and version (main[31:16].sub[15:0])\n\n#define osKernelSystemId    \"FreeRTOS V10.0.1\" ///< RTOS identification string\n\n#define osFeature_MainThread  0         ///< main thread      1=main can be thread, 0=not available\n#define osFeature_Signals     24U       ///< maximum number of Signal Flags available per thread\n#define osFeature_Semaphore   65535U    ///< maximum count for \\ref osSemaphoreCreate function\n#define osFeature_Wait        0         ///< osWait function: 1=available, 0=not available\n#define osFeature_SysTick     1         ///< osKernelSysTick functions: 1=available, 0=not available\n#define osFeature_Pool        0         ///< Memory Pools:    1=available, 0=not available\n#define osFeature_MessageQ    1         ///< Message Queues:  1=available, 0=not available\n#define osFeature_MailQ       0         ///< Mail Queues:     1=available, 0=not available\n\n#if   defined(__CC_ARM)\n#define os_InRegs __value_in_regs\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define os_InRegs __attribute__((value_in_regs))\n#else\n#define os_InRegs\n#endif\n\n#include \"cmsis_os2.h\"\n#include \"FreeRTOS.h\"\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n\n// ==== Enumerations, structures, defines ====\n\n/// Priority values.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osPriorityIdle          = -3,         ///< Priority: idle (lowest)\n  osPriorityLow           = -2,         ///< Priority: low\n  osPriorityBelowNormal   = -1,         ///< Priority: below normal\n  osPriorityNormal        =  0,         ///< Priority: normal (default)\n  osPriorityAboveNormal   = +1,         ///< Priority: above normal\n  osPriorityHigh          = +2,         ///< Priority: high\n  osPriorityRealtime      = +3,         ///< Priority: realtime (highest)\n  osPriorityError         = 0x84,       ///< System cannot determine priority or illegal priority.\n  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osPriority;\n#else\n#define osPriority osPriority_t\n#endif\n\n/// Entry point of a thread.\ntypedef void (*os_pthread) (void const *argument);\n\n/// Entry point of a timer call back function.\ntypedef void (*os_ptimer) (void const *argument);\n\n/// Timer type.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osTimerOnce             = 0,          ///< One-shot timer.\n  osTimerPeriodic         = 1           ///< Repeating timer.\n} os_timer_type;\n#else\n#define os_timer_type osTimerType_t\n#endif\n\n/// Timeout value.\n#define osWaitForever       0xFFFFFFFFU ///< Wait forever timeout value.\n\n/// Status code values returned by CMSIS-RTOS functions.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osOK                    =    0,       ///< Function completed; no error or event occurred.\n  osEventSignal           = 0x08,       ///< Function completed; signal event occurred.\n  osEventMessage          = 0x10,       ///< Function completed; message event occurred.\n  osEventMail             = 0x20,       ///< Function completed; mail event occurred.\n  osEventTimeout          = 0x40,       ///< Function completed; timeout occurred.\n  osErrorParameter        = 0x80,       ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.\n  osErrorResource         = 0x81,       ///< Resource not available: a specified resource was not available.\n  osErrorTimeoutResource  = 0xC1,       ///< Resource not available within given time: a specified resource was not available within the timeout period.\n  osErrorISR              = 0x82,       ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osErrorISRRecursive     = 0x83,       ///< Function called multiple times from ISR with same object.\n  osErrorPriority         = 0x84,       ///< System cannot determine priority or thread has illegal priority.\n  osErrorNoMemory         = 0x85,       ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorValue            = 0x86,       ///< Value of a parameter is out of range.\n  osErrorOS               = 0xFF,       ///< Unspecified RTOS error: run-time error but no other error message fits.\n  osStatusReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osStatus;\n#else\ntypedef int32_t                  osStatus;\n#define osEventSignal           (0x08)\n#define osEventMessage          (0x10)\n#define osEventMail             (0x20)\n#define osEventTimeout          (0x40)\n#define osErrorOS               osError\n#define osErrorTimeoutResource  osErrorTimeout\n#define osErrorISRRecursive     (-126)\n#define osErrorValue            (-127)\n#define osErrorPriority         (-128)\n#endif\n\n\n// >>> the following data type definitions may be adapted towards a specific RTOS\n\n/// Thread ID identifies the thread.\n#if (osCMSIS < 0x20000U)\ntypedef void *osThreadId;\n#else\n#define osThreadId osThreadId_t\n#endif\n\n/// Timer ID identifies the timer.\n#if (osCMSIS < 0x20000U)\ntypedef void *osTimerId;\n#else\n#define osTimerId osTimerId_t\n#endif\n\n/// Mutex ID identifies the mutex.\n#if (osCMSIS < 0x20000U)\ntypedef void *osMutexId;\n#else\n#define osMutexId osMutexId_t\n#endif\n\n/// Semaphore ID identifies the semaphore.\n#if (osCMSIS < 0x20000U)\ntypedef void *osSemaphoreId;\n#else\n#define osSemaphoreId osSemaphoreId_t\n#endif\n\n/// Pool ID identifies the memory pool.\ntypedef void *osPoolId;\n\n/// Message ID identifies the message queue.\ntypedef void *osMessageQId;\n\n/// Mail ID identifies the mail queue.\ntypedef void *osMailQId;\n\n\n/// Thread Definition structure contains startup information of a thread.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_thread_def {\n  os_pthread                 pthread;   ///< start address of thread function\n  osPriority               tpriority;   ///< initial thread priority\n  uint32_t                 instances;   ///< maximum number of instances of that thread function\n  uint32_t                 stacksize;   ///< stack size requirements in bytes; 0 is default stack size\n} osThreadDef_t;\n#else\ntypedef struct os_thread_def {\n  os_pthread                 pthread;   ///< start address of thread function\n  osThreadAttr_t                attr;   ///< thread attributes\n} osThreadDef_t;\n#endif\n\n/// Timer Definition structure contains timer parameters.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_timer_def {\n  os_ptimer                   ptimer;   ///< start address of a timer function\n} osTimerDef_t;\n#else\ntypedef struct os_timer_def {\n  os_ptimer                   ptimer;   ///< start address of a timer function\n  osTimerAttr_t                 attr;   ///< timer attributes\n} osTimerDef_t;\n#endif\n\n/// Mutex Definition structure contains setup information for a mutex.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_mutex_def {\n  uint32_t                     dummy;   ///< dummy value\n} osMutexDef_t;\n#else\n#define osMutexDef_t osMutexAttr_t\n#endif\n\n/// Semaphore Definition structure contains setup information for a semaphore.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_semaphore_def {\n  uint32_t                     dummy;   ///< dummy value\n} osSemaphoreDef_t;\n#else\n#define osSemaphoreDef_t osSemaphoreAttr_t\n#endif\n\n/// Definition structure for memory block allocation.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_pool_def {\n  uint32_t                   pool_sz;   ///< number of items (elements) in the pool\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *pool;   ///< pointer to memory for pool\n} osPoolDef_t;\n#else\ntypedef struct os_pool_def {\n  uint32_t                   pool_sz;   ///< number of items (elements) in the pool\n  uint32_t                   item_sz;   ///< size of an item\n  osMemoryPoolAttr_t            attr;   ///< memory pool attributes\n} osPoolDef_t;\n#endif\n\n/// Definition structure for message queue.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_messageQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  void                         *pool;   ///< memory array for messages\n} osMessageQDef_t;\n#else\ntypedef struct os_messageQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  osMessageQueueAttr_t          attr;   ///< message queue attributes\n} osMessageQDef_t;\n#endif\n\n/// Definition structure for mail queue.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_mailQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *pool;   ///< memory array for mail\n} osMailQDef_t;\n#else\ntypedef struct os_mailQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *mail;   ///< pointer to mail\n  osMemoryPoolAttr_t         mp_attr;   ///< memory pool attributes\n  osMessageQueueAttr_t       mq_attr;   ///< message queue attributes\n} osMailQDef_t;\n#endif\n\n\n/// Event structure contains detailed information about an event.\ntypedef struct {\n  osStatus                    status;   ///< status code: event or error information\n  union {\n    uint32_t                       v;   ///< message as 32-bit value\n    void                          *p;   ///< message or mail as void pointer\n    int32_t                  signals;   ///< signal flags\n  } value;                              ///< event value\n  union {\n    osMailQId                mail_id;   ///< mail id obtained by \\ref osMailCreate\n    osMessageQId          message_id;   ///< message id obtained by \\ref osMessageCreate\n  } def;                                ///< event definition\n} osEvent;\n\n\n//  ==== Kernel Management Functions ====\n\n/// Initialize the RTOS Kernel for creating objects.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osKernelInitialize (void);\n#endif\n\n/// Start the RTOS Kernel scheduler.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osKernelStart (void);\n#endif\n\n/// Check if the RTOS kernel is already started.\n/// \\return 0 RTOS is not started, 1 RTOS is started.\n#if (osCMSIS < 0x20000U)\nint32_t osKernelRunning(void);\n#endif\n\n#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0))  // System Timer available\n\n/// Get the RTOS kernel system timer counter.\n/// \\return RTOS kernel system timer as 32-bit value\n#if (osCMSIS < 0x20000U)\nuint32_t osKernelSysTick (void);\n#else\n#define  osKernelSysTick osKernelGetSysTimerCount\n#endif\n\n/// The RTOS kernel system timer frequency in Hz.\n/// \\note Reflects the system timer setting and is typically defined in a configuration file.\n#if (osCMSIS < 0x20000U)\n#define osKernelSysTickFrequency 100000000\n#endif\n\n/// Convert a microseconds value to a RTOS kernel system timer value.\n/// \\param         microsec     time value in microseconds.\n/// \\return time value normalized to the \\ref osKernelSysTickFrequency\n#if (osCMSIS < 0x20000U)\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)\n#else\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec *  osKernelGetSysTimerFreq()) / 1000000)\n#endif\n\n#endif  // System Timer available\n\n\n//  ==== Thread Management Functions ====\n\n/// Create a Thread Definition with function, priority, and stack requirements.\n/// \\param         name          name of the thread function.\n/// \\param         priority      initial priority of the thread function.\n/// \\param         instances     number of possible thread instances (used to statically allocate memory).\n/// \\param         stacksz       stack size (in bytes) requirements for the thread function.\n#if defined (osObjectsExternal)  // object is external\n#define osThreadDef(name, priority, instances, stacksz) \\\nextern const osThreadDef_t os_thread_def_##name\n#else                            // define the object\n#define osThreadDef(name, priority, instances, stacksz) \\\nstatic uint32_t os_thread_stack##name[(stacksz)?(((stacksz+3)/4)):1]; \\\nstatic StaticTask_t os_thread_cb_##name; \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ (name), \\\n  { NULL, osThreadDetached, \\\n    (instances == 1) ? (&os_thread_cb_##name) : NULL,\\\n    (instances == 1) ? sizeof(StaticTask_t) : 0U, \\\n    ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \\\n    4*((stacksz+3)/4), \\\n    (priority), 0U, 0U } }\n#endif\n\n/// Access a Thread definition.\n/// \\param         name          name of the thread definition object.\n#define osThread(name) \\\n&os_thread_def_##name\n\n/// Create a thread and add it to Active Threads and set it to state READY.\n/// \\param[in]     thread_def    thread definition referenced with \\ref osThread.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);\n\n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\n#if (osCMSIS < 0x20000U)\nosThreadId osThreadGetId (void);\n#endif\n\n/// Change priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);\n#endif\n\n/// Get current priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return current priority value of the specified thread.\n#if (osCMSIS < 0x20000U)\nosPriority osThreadGetPriority (osThreadId thread_id);\n#endif\n\n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadYield (void);\n#endif\n\n/// Terminate execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadTerminate (osThreadId thread_id);\n#endif\n\n\n//  ==== Signal Management ====\n\n/// Set the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that should be set.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\nint32_t osSignalSet (osThreadId thread_id, int32_t signals);\n\n/// Clear the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that shall be cleared.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.\nint32_t osSignalClear (osThreadId thread_id, int32_t signals);\n\n/// Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\n/// \\param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flag information or error code.\nos_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);\n\n\n//  ==== Generic Wait Functions ====\n\n/// Wait for Timeout (Time Delay).\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osDelay (uint32_t millisec);\n#endif\n\n#if (defined (osFeature_Wait) && (osFeature_Wait != 0))  // Generic Wait available\n\n/// Wait for Signal, Message, Mail, or Timeout.\n/// \\param[in] millisec          \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return event that contains signal, message, or mail information or error code.\nos_InRegs osEvent osWait (uint32_t millisec);\n\n#endif  // Generic Wait available\n\n\n//  ==== Timer Management Functions ====\n\n/// Define a Timer object.\n/// \\param         name          name of the timer object.\n/// \\param         function      name of the timer call back function.\n#if defined (osObjectsExternal)  // object is external\n#define osTimerDef(name, function) \\\nextern const osTimerDef_t os_timer_def_##name\n#else                            // define the object\n#define osTimerDef(name, function) \\\nstatic StaticTimer_t os_timer_cb_##name; \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } }\n#endif\n\n/// Access a Timer definition.\n/// \\param         name          name of the timer object.\n#define osTimer(name) \\\n&os_timer_def_##name\n\n/// Create and Initialize a timer.\n/// \\param[in]     timer_def     timer object referenced with \\ref osTimer.\n/// \\param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer call back function.\n/// \\return timer ID for reference by other functions or NULL in case of error.\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);\n\n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec);\n#endif\n\n/// Stop a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerStop (osTimerId timer_id);\n#endif\n\n/// Delete a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerDelete (osTimerId timer_id);\n#endif\n\n\n//  ==== Mutex Management Functions ====\n\n/// Define a Mutex.\n/// \\param         name          name of the mutex object.\n#if defined (osObjectsExternal)  // object is external\n#define osMutexDef(name) \\\nextern const osMutexDef_t os_mutex_def_##name\n#else                            // define the object\n#define osMutexDef(name) \\\nstatic StaticSemaphore_t os_mutex_cb_##name; \\\nconst osMutexDef_t os_mutex_def_##name = \\\n{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) }\n#endif\n\n/// Access a Mutex definition.\n/// \\param         name          name of the mutex object.\n#define osMutex(name) \\\n&os_mutex_def_##name\n\n/// Create and Initialize a Mutex object.\n/// \\param[in]     mutex_def     mutex definition referenced with \\ref osMutex.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def);\n\n/// Wait until a Mutex becomes available.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);\n#else\n#define  osMutexWait osMutexAcquire\n#endif\n\n/// Release a Mutex that was obtained by \\ref osMutexWait.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexRelease (osMutexId mutex_id);\n#endif\n\n/// Delete a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexDelete (osMutexId mutex_id);\n#endif\n\n\n//  ==== Semaphore Management Functions ====\n\n#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))  // Semaphore available\n\n/// Define a Semaphore object.\n/// \\param         name          name of the semaphore object.\n#if defined (osObjectsExternal)  // object is external\n#define osSemaphoreDef(name) \\\nextern const osSemaphoreDef_t os_semaphore_def_##name\n#else                            // define the object\n#define osSemaphoreDef(name) \\\nstatic StaticSemaphore_t os_semaphore_cb_##name; \\\nconst osSemaphoreDef_t os_semaphore_def_##name = \\\n{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) }\n#endif\n\n/// Access a Semaphore definition.\n/// \\param         name          name of the semaphore object.\n#define osSemaphore(name) \\\n&os_semaphore_def_##name\n\n/// Create and Initialize a Semaphore object.\n/// \\param[in]     semaphore_def semaphore definition referenced with \\ref osSemaphore.\n/// \\param[in]     count         maximum and initial number of available tokens.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);\n\n/// Wait until a Semaphore token becomes available.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return number of available tokens, or -1 in case of incorrect parameters.\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);\n\n/// Release a Semaphore token.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id);\n#endif\n\n/// Delete a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id);\n#endif\n\n#endif  // Semaphore available\n\n\n//  ==== Memory Pool Management Functions ====\n\n#if (defined(osFeature_Pool) && (osFeature_Pool != 0))  // Memory Pool available\n\n/// \\brief Define a Memory Pool.\n/// \\param         name          name of the memory pool.\n/// \\param         no            maximum number of blocks (objects) in the memory pool.\n/// \\param         type          data type of a single block (object).\n#if defined (osObjectsExternal)  // object is external\n#define osPoolDef(name, no, type) \\\nextern const osPoolDef_t os_pool_def_##name\n#else                            // define the object\n#define osPoolDef(name, no, type) \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), NULL }\n#endif\n\n/// \\brief Access a Memory Pool definition.\n/// \\param         name          name of the memory pool\n#define osPool(name) \\\n&os_pool_def_##name\n\n/// Create and Initialize a Memory Pool object.\n/// \\param[in]     pool_def      memory pool definition referenced with \\ref osPool.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\nosPoolId osPoolCreate (const osPoolDef_t *pool_def);\n\n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolAlloc (osPoolId pool_id);\n\n/// Allocate a memory block from a Memory Pool and set memory block to zero.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolCAlloc (osPoolId pool_id);\n\n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\param[in]     block         address of the allocated memory block to be returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus osPoolFree (osPoolId pool_id, void *block);\n\n#endif  // Memory Pool available\n\n\n//  ==== Message Queue Management Functions ====\n\n#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))  // Message Queue available\n\n/// \\brief Create a Message Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of messages in the queue.\n/// \\param         type          data type of a single message element (for debugger).\n#if defined (osObjectsExternal)  // object is external\n#define osMessageQDef(name, queue_sz, type) \\\nextern const osMessageQDef_t os_messageQ_def_##name\n#else                            // define the object\n#define osMessageQDef(name, queue_sz, type) \\\nstatic StaticQueue_t os_mq_cb_##name; \\\nstatic uint32_t os_mq_data_##name[(queue_sz) * sizeof(type)]; \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), \\\n  { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \\\n              (&os_mq_data_##name), sizeof(os_mq_data_##name) } }\n#endif\n\n/// \\brief Access a Message Queue Definition.\n/// \\param         name          name of the queue\n#define osMessageQ(name) \\\n&os_messageQ_def_##name\n\n/// Create and Initialize a Message Queue object.\n/// \\param[in]     queue_def     message queue definition referenced with \\ref osMessageQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\n\n/// Put a Message to a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     info          message information.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);\n\n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\nos_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);\n\n#endif  // Message Queue available\n\n\n//  ==== Mail Queue Management Functions ====\n\n#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))  // Mail Queue available\n\n/// \\brief Create a Mail Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of mails in the queue.\n/// \\param         type          data type of a single mail element.\n#if defined (osObjectsExternal)  // object is external\n#define osMailQDef(name, queue_sz, type) \\\nextern const osMailQDef_t os_mailQ_def_##name\n#else                            // define the object\n#define osMailQDef(name, queue_sz, type) \\\nconst osMailQDef_t os_mailQ_def_##name = \\\n{ (queue_sz), sizeof(type), NULL }\n#endif\n\n/// \\brief Access a Mail Queue Definition.\n/// \\param         name          name of the queue\n#define osMailQ(name) \\\n&os_mailQ_def_##name\n\n/// Create and Initialize a Mail Queue object.\n/// \\param[in]     queue_def     mail queue definition referenced with \\ref osMailQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return mail queue ID for reference by other functions or NULL in case of error.\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);\n\n/// Allocate a memory block for mail from a mail memory pool.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec);\n\n/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec);\n\n/// Put a Mail into a Queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to memory with mail to put into a queue.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailPut (osMailQId queue_id, const void *mail);\n\n/// Get a Mail from a Queue or timeout if Queue is empty.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\nos_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);\n\n/// Free a memory block by returning it to a mail memory pool.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to memory block that was obtained with \\ref osMailGet.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailFree (osMailQId queue_id, void *mail);\n\n#endif  // Mail Queue available\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif  // CMSIS_OS_H_\n"
  },
  {
    "path": "examples/lib/FreeRTOS/CMSIS_RTOS_V2/cmsis_os2.c",
    "content": "/* --------------------------------------------------------------------------\n * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.\n * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.\n * --------------------------------------------------------------------------\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    cmsis_os2.c\n *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS\n *\n *---------------------------------------------------------------------------*/\n\n#include <string.h>\n\n#include \"cmsis_os2.h\"                  // ::CMSIS:RTOS2\n#include \"cmsis_compiler.h\"\n\n#include \"FreeRTOS.h\"                   // ARM.FreeRTOS::RTOS:Core\n#include \"task.h\"                       // ARM.FreeRTOS::RTOS:Core\n#include \"event_groups.h\"               // ARM.FreeRTOS::RTOS:Event Groups\n#include \"semphr.h\"                     // ARM.FreeRTOS::RTOS:Core\n\n/*---------------------------------------------------------------------------*/\n#ifndef __ARM_ARCH_6M__\n  #define __ARM_ARCH_6M__         0\n#endif\n#ifndef __ARM_ARCH_7M__\n  #define __ARM_ARCH_7M__         0\n#endif\n#ifndef __ARM_ARCH_7EM__\n  #define __ARM_ARCH_7EM__        0\n#endif\n#ifndef __ARM_ARCH_8M_MAIN__\n  #define __ARM_ARCH_8M_MAIN__    0\n#endif\n#ifndef __ARM_ARCH_7A__\n  #define __ARM_ARCH_7A__         0\n#endif\n\n#if   ((__ARM_ARCH_7M__      == 1U) || \\\n       (__ARM_ARCH_7EM__     == 1U) || \\\n       (__ARM_ARCH_8M_MAIN__ == 1U))\n#define IS_IRQ_MASKED()           ((__get_PRIMASK() != 0U) || ((KernelState == osKernelRunning) && (__get_BASEPRI() != 0U)))\n#elif  (__ARM_ARCH_6M__      == 1U)\n#define IS_IRQ_MASKED()           ((__get_PRIMASK() != 0U) &&  (KernelState == osKernelRunning))\n#elif (__ARM_ARCH_7A__       == 1)\n#define IS_IRQ_MASKED()           (0U)\n#else\n#define IS_IRQ_MASKED()           (__get_PRIMASK() != 0U)\n#endif\n\n#if    (__ARM_ARCH_7A__      == 1U)\n/* CPSR mode bitmasks */\n#define CPSR_MODE_USER            0x10U\n#define CPSR_MODE_SYSTEM          0x1FU\n\n#define IS_IRQ_MODE()             ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM))\n#else\n#define IS_IRQ_MODE()             (__get_IPSR() != 0U)\n#endif\n\n#define IS_IRQ()                  (IS_IRQ_MODE() || IS_IRQ_MASKED())\n\n/* Limits */\n#define MAX_BITS_TASK_NOTIFY      31U\n#define MAX_BITS_EVENT_GROUPS     24U\n\n#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY)  - 1U))\n#define EVENT_FLAGS_INVALID_BITS  (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U))\n\n/* Kernel version and identification string definition */\n#define KERNEL_VERSION            (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \\\n                                   ((uint32_t)tskKERNEL_VERSION_MINOR *    10000UL) | \\\n                                   ((uint32_t)tskKERNEL_VERSION_BUILD *        1UL))\n\n#define KERNEL_ID                 \"FreeRTOS V10.0.1\"\n\n/* Timer callback information structure definition */\ntypedef struct {\n  osTimerFunc_t func;\n  void         *arg;\n} TimerCallback_t;\n\n/* Kernel initialization state */\nstatic osKernelState_t KernelState;\n\n/* Heap region definition used by heap_5 variant */\n#if defined(USE_FreeRTOS_HEAP_5)\n#if (configAPPLICATION_ALLOCATED_HEAP == 1)\n/*\n  The application writer has already defined the array used for the RTOS\n  heap - probably so it can be placed in a special segment or address.\n*/\n  extern uint8_t ucHeap[configTOTAL_HEAP_SIZE];\n#else\n  static uint8_t ucHeap[configTOTAL_HEAP_SIZE];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\nstatic HeapRegion_t xHeapRegions[] = {\n  { ucHeap, configTOTAL_HEAP_SIZE },\n  { NULL,   0                     }\n};\n#endif /* USE_FreeRTOS_HEAP_5 */\n\n#if defined(SysTick)\n/* FreeRTOS tick timer interrupt handler prototype */\nextern void xPortSysTickHandler (void);\n\n/*\n  SysTick handler implementation that also clears overflow flag.\n*/\nvoid SysTick_Handler (void) {\n  /* Clear overflow flag */\n  SysTick->CTRL;\n\n  /* Call tick handler */\n  xPortSysTickHandler();\n}\n#endif /* SysTick */\n\n/*---------------------------------------------------------------------------*/\n\nosStatus_t osKernelInitialize (void) {\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    if (KernelState == osKernelInactive) {\n      #if defined(USE_FreeRTOS_HEAP_5)\n        vPortDefineHeapRegions (xHeapRegions);\n      #endif\n      KernelState = osKernelReady;\n      stat = osOK;\n    } else {\n      stat = osError;\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {\n\n  if (version != NULL) {\n    version->api    = KERNEL_VERSION;\n    version->kernel = KERNEL_VERSION;\n  }\n\n  if ((id_buf != NULL) && (id_size != 0U)) {\n    if (id_size > sizeof(KERNEL_ID)) {\n      id_size = sizeof(KERNEL_ID);\n    }\n    memcpy(id_buf, KERNEL_ID, id_size);\n  }\n\n  return (osOK);\n}\n\nosKernelState_t osKernelGetState (void) {\n  osKernelState_t state;\n\n  switch (xTaskGetSchedulerState()) {\n    case taskSCHEDULER_RUNNING:\n      state = osKernelRunning;\n      break;\n\n    case taskSCHEDULER_SUSPENDED:\n      state = osKernelLocked;\n      break;\n\n    case taskSCHEDULER_NOT_STARTED:\n    default:\n      if (KernelState == osKernelReady) {\n        state = osKernelReady;\n      } else {\n        state = osKernelInactive;\n      }\n      break;\n  }\n\n  return (state);\n}\n\nosStatus_t osKernelStart (void) {\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    if (KernelState == osKernelReady) {\n      KernelState = osKernelRunning;\n      vTaskStartScheduler();\n      stat = osOK;\n    } else {\n      stat = osError;\n    }\n  }\n\n  return (stat);\n}\n\nint32_t osKernelLock (void) {\n  int32_t lock;\n\n  if (IS_IRQ()) {\n    lock = (int32_t)osErrorISR;\n  }\n  else {\n    switch (xTaskGetSchedulerState()) {\n      case taskSCHEDULER_SUSPENDED:\n        lock = 1;\n        break;\n\n      case taskSCHEDULER_RUNNING:\n        vTaskSuspendAll();\n        lock = 0;\n        break;\n\n      case taskSCHEDULER_NOT_STARTED:\n      default:\n        lock = (int32_t)osError;\n        break;\n    }\n  }\n\n  return (lock);\n}\n\nint32_t osKernelUnlock (void) {\n  int32_t lock;\n\n  if (IS_IRQ()) {\n    lock = (int32_t)osErrorISR;\n  }\n  else {\n    switch (xTaskGetSchedulerState()) {\n      case taskSCHEDULER_SUSPENDED:\n        lock = 1;\n\n        if (xTaskResumeAll() != pdTRUE) {\n          if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) {\n            lock = (int32_t)osError;\n          }\n        }\n        break;\n\n      case taskSCHEDULER_RUNNING:\n        lock = 0;\n        break;\n\n      case taskSCHEDULER_NOT_STARTED:\n      default:\n        lock = (int32_t)osError;\n        break;\n    }\n  }\n\n  return (lock);\n}\n\nint32_t osKernelRestoreLock (int32_t lock) {\n\n  if (IS_IRQ()) {\n    lock = (int32_t)osErrorISR;\n  }\n  else {\n    switch (xTaskGetSchedulerState()) {\n      case taskSCHEDULER_SUSPENDED:\n      case taskSCHEDULER_RUNNING:\n        if (lock == 1) {\n          vTaskSuspendAll();\n        }\n        else {\n          if (lock != 0) {\n            lock = (int32_t)osError;\n          }\n          else {\n            if (xTaskResumeAll() != pdTRUE) {\n              if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) {\n                lock = (int32_t)osError;\n              }\n            }\n          }\n        }\n        break;\n\n      case taskSCHEDULER_NOT_STARTED:\n      default:\n        lock = (int32_t)osError;\n        break;\n    }\n  }\n\n  return (lock);\n}\n\nuint32_t osKernelGetTickCount (void) {\n  TickType_t ticks;\n\n  if (IS_IRQ()) {\n    ticks = xTaskGetTickCountFromISR();\n  } else {\n    ticks = xTaskGetTickCount();\n  }\n\n  return (ticks);\n}\n\nuint32_t osKernelGetTickFreq (void) {\n  return (configTICK_RATE_HZ);\n}\n\nuint32_t osKernelGetSysTimerCount (void) {\n  TickType_t ticks;\n  uint32_t val;\n\n  portDISABLE_INTERRUPTS();\n\n  ticks = xTaskGetTickCount();\n\n  val = ticks * ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );\n  portENABLE_INTERRUPTS();\n\n  return (val);\n}\n\nuint32_t osKernelGetSysTimerFreq (void) {\n  return (configCPU_CLOCK_HZ);\n}\n\n/*---------------------------------------------------------------------------*/\n\nosThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {\n  char empty;\n  const char *name;\n  uint32_t stack;\n  TaskHandle_t hTask;\n  UBaseType_t prio;\n  int32_t mem;\n\n  hTask = NULL;\n\n  if (!IS_IRQ() && (func != NULL)) {\n    stack = configMINIMAL_STACK_SIZE;\n    prio  = (UBaseType_t)osPriorityNormal;\n\n    empty = '\\0';\n    name  = &empty;\n    mem   = -1;\n\n    if (attr != NULL) {\n      if (attr->name != NULL) {\n        name = attr->name;\n      }\n      if (attr->priority != osPriorityNone) {\n        prio = (UBaseType_t)attr->priority;\n      }\n\n      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {\n        return (NULL);\n      }\n\n      if (attr->stack_size > 0U) {\n        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */\n        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */\n        stack = attr->stack_size / sizeof(StackType_t);\n      }\n\n      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&\n          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {\n        mem = 1;\n      }\n      else {\n        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {\n          mem = 0;\n        }\n      }\n    }\n    else {\n      mem = 0;\n    }\n\n    if (mem == 1) {\n      hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,\n                                                                                    (StaticTask_t *)attr->cb_mem);\n    }\n    else {\n      if (mem == 0) {\n        if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {\n          hTask = NULL;\n        }\n      }\n    }\n  }\n\n  return ((osThreadId_t)hTask);\n}\n\nconst char *osThreadGetName (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  const char *name;\n\n  if (IS_IRQ() || (hTask == NULL)) {\n    name = NULL;\n  } else {\n    name = pcTaskGetName (hTask);\n  }\n\n  return (name);\n}\n\nosThreadId_t osThreadGetId (void) {\n  osThreadId_t id;\n\n  if (IS_IRQ()) {\n    id = NULL;\n  } else {\n    id = (osThreadId_t)xTaskGetCurrentTaskHandle();\n  }\n\n  return (id);\n}\n\nosThreadState_t osThreadGetState (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osThreadState_t state;\n\n  if (IS_IRQ() || (hTask == NULL)) {\n    state = osThreadError;\n  }\n  else {\n    switch (eTaskGetState (hTask)) {\n      case eRunning:   state = osThreadRunning;    break;\n      case eReady:     state = osThreadReady;      break;\n      case eBlocked:\n      case eSuspended: state = osThreadBlocked;    break;\n      case eDeleted:   state = osThreadTerminated; break;\n      case eInvalid:\n      default:         state = osThreadError;      break;\n    }\n  }\n\n  return (state);\n}\n\nuint32_t osThreadGetStackSpace (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  uint32_t sz;\n\n  if (IS_IRQ() || (hTask == NULL)) {\n    sz = 0U;\n  } else {\n    sz = (uint32_t)uxTaskGetStackHighWaterMark (hTask);\n  }\n\n  return (sz);\n}\n\nuint32_t osThreadGetStackSize\t(osThreadId_t thread_id) {\n  /*\n   * this implmentation is not correct.\n   * this function is implmented to avoid link errors (undefined reference)\n   * Bug reported : https://github.com/ARM-software/CMSIS-FreeRTOS/issues/14\n   */\n  (void) thread_id;\n  return 0;\n}\n\nosStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if ((hTask == NULL) || (priority < osPriorityIdle) || (priority > osPriorityISR)) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    vTaskPrioritySet (hTask, (UBaseType_t)priority);\n  }\n\n  return (stat);\n}\n\nosPriority_t osThreadGetPriority (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osPriority_t prio;\n\n  if (IS_IRQ() || (hTask == NULL)) {\n    prio = osPriorityError;\n  } else {\n    prio = (osPriority_t)uxTaskPriorityGet (hTask);\n  }\n\n  return (prio);\n}\n\nosStatus_t osThreadYield (void) {\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  } else {\n    stat = osOK;\n    taskYIELD();\n  }\n\n  return (stat);\n}\n\nosStatus_t osThreadSuspend (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTask == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    vTaskSuspend (hTask);\n  }\n\n  return (stat);\n}\n\nosStatus_t osThreadResume (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTask == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    vTaskResume (hTask);\n  }\n\n  return (stat);\n}\n\n__NO_RETURN void osThreadExit (void) {\n#ifndef USE_FreeRTOS_HEAP_1\n  vTaskDelete (NULL);\n#endif\n  for (;;);\n}\n\nosStatus_t osThreadTerminate (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osStatus_t stat;\n#ifndef USE_FreeRTOS_HEAP_1\n  eTaskState tstate;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTask == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    tstate = eTaskGetState (hTask);\n\n    if (tstate != eDeleted) {\n      stat = osOK;\n      vTaskDelete (hTask);\n    } else {\n      stat = osErrorResource;\n    }\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\nuint32_t osThreadGetCount (void) {\n  uint32_t count;\n\n  if (IS_IRQ()) {\n    count = 0U;\n  } else {\n    count = uxTaskGetNumberOfTasks();\n  }\n\n  return (count);\n}\n\nuint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {\n  uint32_t i, count;\n  TaskStatus_t *task;\n\n  if (IS_IRQ() || (thread_array == NULL) || (array_items == 0U)) {\n    count = 0U;\n  } else {\n    vTaskSuspendAll();\n\n    count = uxTaskGetNumberOfTasks();\n    task  = pvPortMalloc (count * sizeof(TaskStatus_t));\n\n    if (task != NULL) {\n      count = uxTaskGetSystemState (task, count, NULL);\n\n      for (i = 0U; (i < count) && (i < array_items); i++) {\n        thread_array[i] = (osThreadId_t)task[i].xHandle;\n      }\n      count = i;\n    }\n    (void)xTaskResumeAll();\n\n    vPortFree (task);\n  }\n\n  return (count);\n}\n\nuint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  uint32_t rflags;\n  BaseType_t yield;\n\n  if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else {\n    rflags = (uint32_t)osError;\n\n    if (IS_IRQ()) {\n      yield = pdFALSE;\n\n      (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield);\n      (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL);\n\n      portYIELD_FROM_ISR (yield);\n    }\n    else {\n      (void)xTaskNotify (hTask, flags, eSetBits);\n      (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags);\n    }\n  }\n  /* Return flags after setting */\n  return (rflags);\n}\n\nuint32_t osThreadFlagsClear (uint32_t flags) {\n  TaskHandle_t hTask;\n  uint32_t rflags, cflags;\n\n  if (IS_IRQ()) {\n    rflags = (uint32_t)osErrorISR;\n  }\n  else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else {\n    hTask = xTaskGetCurrentTaskHandle();\n\n    if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &cflags) == pdPASS) {\n      rflags = cflags;\n      cflags &= ~flags;\n\n      if (xTaskNotify (hTask, cflags, eSetValueWithOverwrite) != pdPASS) {\n        rflags = (uint32_t)osError;\n      }\n    }\n    else {\n      rflags = (uint32_t)osError;\n    }\n  }\n\n  /* Return flags before clearing */\n  return (rflags);\n}\n\nuint32_t osThreadFlagsGet (void) {\n  TaskHandle_t hTask;\n  uint32_t rflags;\n\n  if (IS_IRQ()) {\n    rflags = (uint32_t)osErrorISR;\n  }\n  else {\n    hTask = xTaskGetCurrentTaskHandle();\n\n    if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags) != pdPASS) {\n      rflags = (uint32_t)osError;\n    }\n  }\n\n  return (rflags);\n}\n\nuint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {\n  uint32_t rflags, nval;\n  uint32_t clear;\n  TickType_t t0, td, tout;\n  BaseType_t rval;\n\n  if (IS_IRQ()) {\n    rflags = (uint32_t)osErrorISR;\n  }\n  else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else {\n    if ((options & osFlagsNoClear) == osFlagsNoClear) {\n      clear = 0U;\n    } else {\n      clear = flags;\n    }\n\n    rflags = 0U;\n    tout   = timeout;\n\n    t0 = xTaskGetTickCount();\n    do {\n      rval = xTaskNotifyWait (0, clear, &nval, tout);\n\n      if (rval == pdPASS) {\n        rflags &= flags;\n        rflags |= nval;\n\n        if ((options & osFlagsWaitAll) == osFlagsWaitAll) {\n          if ((flags & rflags) == flags) {\n            break;\n          } else {\n            if (timeout == 0U) {\n              rflags = (uint32_t)osErrorResource;\n              break;\n            }\n          }\n        }\n        else {\n          if ((flags & rflags) != 0) {\n            break;\n          } else {\n            if (timeout == 0U) {\n              rflags = (uint32_t)osErrorResource;\n              break;\n            }\n          }\n        }\n\n        /* Update timeout */\n        td = xTaskGetTickCount() - t0;\n\n        if (td > tout) {\n          tout  = 0;\n        } else {\n          tout -= td;\n        }\n      }\n      else {\n        if (timeout == 0) {\n          rflags = (uint32_t)osErrorResource;\n        } else {\n          rflags = (uint32_t)osErrorTimeout;\n        }\n      }\n    }\n    while (rval != pdFAIL);\n  }\n\n  /* Return flags before clearing */\n  return (rflags);\n}\n\nosStatus_t osDelay (uint32_t ticks) {\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    stat = osOK;\n\n    if (ticks != 0U) {\n      vTaskDelay(ticks);\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osDelayUntil (uint32_t ticks) {\n  TickType_t tcnt;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    stat = osOK;\n    tcnt = xTaskGetTickCount();\n\n    vTaskDelayUntil (&tcnt, (TickType_t)(ticks - tcnt));\n  }\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n\nstatic void TimerCallback (TimerHandle_t hTimer) {\n  TimerCallback_t *callb;\n\n  callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);\n\n  if (callb != NULL) {\n    callb->func (callb->arg);\n  }\n}\n\nosTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {\n  const char *name;\n  TimerHandle_t hTimer;\n  TimerCallback_t *callb;\n  UBaseType_t reload;\n  int32_t mem;\n\n  hTimer = NULL;\n\n  if (!IS_IRQ() && (func != NULL)) {\n    /* Allocate memory to store callback function and argument */\n    callb = pvPortMalloc (sizeof(TimerCallback_t));\n\n    if (callb != NULL) {\n      callb->func = func;\n      callb->arg  = argument;\n\n      if (type == osTimerOnce) {\n        reload = pdFALSE;\n      } else {\n        reload = pdTRUE;\n      }\n\n      mem  = -1;\n      name = NULL;\n\n      if (attr != NULL) {\n        if (attr->name != NULL) {\n          name = attr->name;\n        }\n\n        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) {\n          mem = 1;\n        }\n        else {\n          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n            mem = 0;\n          }\n        }\n      }\n      else {\n        mem = 0;\n      }\n\n      if (mem == 1) {\n        hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem);\n      }\n      else {\n        if (mem == 0) {\n          hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback);\n        }\n      }\n    }\n  }\n\n  return ((osTimerId_t)hTimer);\n}\n\nconst char *osTimerGetName (osTimerId_t timer_id) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  const char *p;\n\n  if (IS_IRQ() || (hTimer == NULL)) {\n    p = NULL;\n  } else {\n    p = pcTimerGetName (hTimer);\n  }\n\n  return (p);\n}\n\nosStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTimer == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) {\n      stat = osOK;\n    } else {\n      stat = osErrorResource;\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osTimerStop (osTimerId_t timer_id) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTimer == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    if (xTimerIsTimerActive (hTimer) == pdFALSE) {\n      stat = osErrorResource;\n    }\n    else {\n      if (xTimerStop (hTimer, 0) == pdPASS) {\n        stat = osOK;\n      } else {\n        stat = osError;\n      }\n    }\n  }\n\n  return (stat);\n}\n\nuint32_t osTimerIsRunning (osTimerId_t timer_id) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  uint32_t running;\n\n  if (IS_IRQ() || (hTimer == NULL)) {\n    running = 0U;\n  } else {\n    running = (uint32_t)xTimerIsTimerActive (hTimer);\n  }\n\n  return (running);\n}\n\nosStatus_t osTimerDelete (osTimerId_t timer_id) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  osStatus_t stat;\n#ifndef USE_FreeRTOS_HEAP_1\n  TimerCallback_t *callb;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTimer == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);\n\n    if (xTimerDelete (hTimer, 0) == pdPASS) {\n      vPortFree (callb);\n      stat = osOK;\n    } else {\n      stat = osErrorResource;\n    }\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n\nosEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {\n  EventGroupHandle_t hEventGroup;\n  int32_t mem;\n\n  hEventGroup = NULL;\n\n  if (!IS_IRQ()) {\n    mem = -1;\n\n    if (attr != NULL) {\n      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticEventGroup_t))) {\n        mem = 1;\n      }\n      else {\n        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n          mem = 0;\n        }\n      }\n    }\n    else {\n      mem = 0;\n    }\n\n    if (mem == 1) {\n      hEventGroup = xEventGroupCreateStatic (attr->cb_mem);\n    }\n    else {\n      if (mem == 0) {\n        hEventGroup = xEventGroupCreate();\n      }\n    }\n  }\n\n  return ((osEventFlagsId_t)hEventGroup);\n}\n\nuint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  uint32_t rflags;\n  BaseType_t yield;\n\n  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    yield = pdFALSE;\n\n    if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) != pdFAIL) {\n      rflags = (uint32_t)osErrorResource;\n    } else {\n      rflags = flags;\n      portYIELD_FROM_ISR (yield);\n    }\n  }\n  else {\n    rflags = xEventGroupSetBits (hEventGroup, (EventBits_t)flags);\n  }\n\n  return (rflags);\n}\n\nuint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  uint32_t rflags;\n\n  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    rflags = xEventGroupGetBitsFromISR (hEventGroup);\n\n    if (xEventGroupClearBitsFromISR (hEventGroup, (EventBits_t)flags) == pdFAIL) {\n      rflags = (uint32_t)osErrorResource;\n    }\n  }\n  else {\n    rflags = xEventGroupClearBits (hEventGroup, (EventBits_t)flags);\n  }\n\n  return (rflags);\n}\n\nuint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  uint32_t rflags;\n\n  if (ef_id == NULL) {\n    rflags = 0U;\n  }\n  else if (IS_IRQ()) {\n    rflags = xEventGroupGetBitsFromISR (hEventGroup);\n  }\n  else {\n    rflags = xEventGroupGetBits (hEventGroup);\n  }\n\n  return (rflags);\n}\n\nuint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  BaseType_t wait_all;\n  BaseType_t exit_clr;\n  uint32_t rflags;\n\n  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    rflags = (uint32_t)osErrorISR;\n  }\n  else {\n    if (options & osFlagsWaitAll) {\n      wait_all = pdTRUE;\n    } else {\n      wait_all = pdFAIL;\n    }\n\n    if (options & osFlagsNoClear) {\n      exit_clr = pdFAIL;\n    } else {\n      exit_clr = pdTRUE;\n    }\n\n    rflags = xEventGroupWaitBits (hEventGroup, (EventBits_t)flags, exit_clr, wait_all, (TickType_t)timeout);\n\n    if (options & osFlagsWaitAll) {\n      if (flags != rflags) {\n        if (timeout > 0U) {\n          rflags = (uint32_t)osErrorTimeout;\n        } else {\n          rflags = (uint32_t)osErrorResource;\n        }\n      }\n    }\n    else {\n      if ((flags & rflags) == 0U) {\n        if (timeout > 0U) {\n          rflags = (uint32_t)osErrorTimeout;\n        } else {\n          rflags = (uint32_t)osErrorResource;\n        }\n      }\n    }\n  }\n\n  return (rflags);\n}\n\nosStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  osStatus_t stat;\n\n#ifndef USE_FreeRTOS_HEAP_1\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hEventGroup == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    vEventGroupDelete (hEventGroup);\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n\nosMutexId_t osMutexNew (const osMutexAttr_t *attr) {\n  SemaphoreHandle_t hMutex;\n  uint32_t type;\n  uint32_t rmtx;\n  int32_t  mem;\n  #if (configQUEUE_REGISTRY_SIZE > 0)\n  const char *name;\n  #endif\n\n  hMutex = NULL;\n\n  if (!IS_IRQ()) {\n    if (attr != NULL) {\n      type = attr->attr_bits;\n    } else {\n      type = 0U;\n    }\n\n    if ((type & osMutexRecursive) == osMutexRecursive) {\n      rmtx = 1U;\n    } else {\n      rmtx = 0U;\n    }\n\n    if ((type & osMutexRobust) != osMutexRobust) {\n      mem = -1;\n\n      if (attr != NULL) {\n        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {\n          mem = 1;\n        }\n        else {\n          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n            mem = 0;\n          }\n        }\n      }\n      else {\n        mem = 0;\n      }\n\n      if (mem == 1) {\n        if (rmtx != 0U) {\n          hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);\n        }\n        else {\n          hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);\n        }\n      }\n      else {\n        if (mem == 0) {\n          if (rmtx != 0U) {\n            hMutex = xSemaphoreCreateRecursiveMutex ();\n          } else {\n            hMutex = xSemaphoreCreateMutex ();\n          }\n        }\n      }\n\n      #if (configQUEUE_REGISTRY_SIZE > 0)\n      if (hMutex != NULL) {\n        if (attr != NULL) {\n          name = attr->name;\n        } else {\n          name = NULL;\n        }\n        vQueueAddToRegistry (hMutex, name);\n      }\n      #endif\n\n      if ((hMutex != NULL) && (rmtx != 0U)) {\n        hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);\n      }\n    }\n  }\n\n  return ((osMutexId_t)hMutex);\n}\n\nosStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {\n  SemaphoreHandle_t hMutex;\n  osStatus_t stat;\n  uint32_t rmtx;\n\n  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);\n\n  rmtx = (uint32_t)mutex_id & 1U;\n\n  stat = osOK;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hMutex == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    if (rmtx != 0U) {\n      if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {\n        if (timeout != 0U) {\n          stat = osErrorTimeout;\n        } else {\n          stat = osErrorResource;\n        }\n      }\n    }\n    else {\n      if (xSemaphoreTake (hMutex, timeout) != pdPASS) {\n        if (timeout != 0U) {\n          stat = osErrorTimeout;\n        } else {\n          stat = osErrorResource;\n        }\n      }\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osMutexRelease (osMutexId_t mutex_id) {\n  SemaphoreHandle_t hMutex;\n  osStatus_t stat;\n  uint32_t rmtx;\n\n  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);\n\n  rmtx = (uint32_t)mutex_id & 1U;\n\n  stat = osOK;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hMutex == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    if (rmtx != 0U) {\n      if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {\n        stat = osErrorResource;\n      }\n    }\n    else {\n      if (xSemaphoreGive (hMutex) != pdPASS) {\n        stat = osErrorResource;\n      }\n    }\n  }\n\n  return (stat);\n}\n\nosThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {\n  SemaphoreHandle_t hMutex;\n  osThreadId_t owner;\n\n  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);\n\n  if (IS_IRQ() || (hMutex == NULL)) {\n    owner = NULL;\n  } else {\n    owner = (osThreadId_t)xSemaphoreGetMutexHolder (hMutex);\n  }\n\n  return (owner);\n}\n\nosStatus_t osMutexDelete (osMutexId_t mutex_id) {\n  osStatus_t stat;\n#ifndef USE_FreeRTOS_HEAP_1\n  SemaphoreHandle_t hMutex;\n\n  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hMutex == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    #if (configQUEUE_REGISTRY_SIZE > 0)\n    vQueueUnregisterQueue (hMutex);\n    #endif\n    stat = osOK;\n    vSemaphoreDelete (hMutex);\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n\nosSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {\n  SemaphoreHandle_t hSemaphore;\n  int32_t mem;\n  #if (configQUEUE_REGISTRY_SIZE > 0)\n  const char *name;\n  #endif\n\n  hSemaphore = NULL;\n\n  if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) {\n    mem = -1;\n\n    if (attr != NULL) {\n      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {\n        mem = 1;\n      }\n      else {\n        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n          mem = 0;\n        }\n      }\n    }\n    else {\n      mem = 0;\n    }\n\n    if (mem != -1) {\n      if (max_count == 1U) {\n        if (mem == 1) {\n          hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem);\n        }\n        else {\n          hSemaphore = xSemaphoreCreateBinary();\n        }\n\n        if ((hSemaphore != NULL) && (initial_count != 0U)) {\n          if (xSemaphoreGive (hSemaphore) != pdPASS) {\n            vSemaphoreDelete (hSemaphore);\n            hSemaphore = NULL;\n          }\n        }\n      }\n      else {\n        if (mem == 1) {\n          hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem);\n        }\n        else {\n          hSemaphore = xSemaphoreCreateCounting (max_count, initial_count);\n        }\n      }\n\n      #if (configQUEUE_REGISTRY_SIZE > 0)\n      if (hSemaphore != NULL) {\n        if (attr != NULL) {\n          name = attr->name;\n        } else {\n          name = NULL;\n        }\n        vQueueAddToRegistry (hSemaphore, name);\n      }\n      #endif\n    }\n  }\n\n  return ((osSemaphoreId_t)hSemaphore);\n}\n\nosStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {\n  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;\n  osStatus_t stat;\n  BaseType_t yield;\n\n  stat = osOK;\n\n  if (hSemaphore == NULL) {\n    stat = osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    if (timeout != 0U) {\n      stat = osErrorParameter;\n    }\n    else {\n      yield = pdFALSE;\n\n      if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) {\n        stat = osErrorResource;\n      } else {\n        portYIELD_FROM_ISR (yield);\n      }\n    }\n  }\n  else {\n    if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) {\n      if (timeout != 0U) {\n        stat = osErrorTimeout;\n      } else {\n        stat = osErrorResource;\n      }\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {\n  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;\n  osStatus_t stat;\n  BaseType_t yield;\n\n  stat = osOK;\n\n  if (hSemaphore == NULL) {\n    stat = osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    yield = pdFALSE;\n\n    if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) {\n      stat = osErrorResource;\n    } else {\n      portYIELD_FROM_ISR (yield);\n    }\n  }\n  else {\n    if (xSemaphoreGive (hSemaphore) != pdPASS) {\n      stat = osErrorResource;\n    }\n  }\n\n  return (stat);\n}\n\nuint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {\n  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;\n  uint32_t count;\n\n  if (hSemaphore == NULL) {\n    count = 0U;\n  }\n  else if (IS_IRQ()) {\n    count = uxQueueMessagesWaitingFromISR (hSemaphore);\n  } else {\n    count = (uint32_t)uxSemaphoreGetCount (hSemaphore);\n  }\n\n  return (count);\n}\n\nosStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) {\n  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;\n  osStatus_t stat;\n\n#ifndef USE_FreeRTOS_HEAP_1\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hSemaphore == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    #if (configQUEUE_REGISTRY_SIZE > 0)\n    vQueueUnregisterQueue (hSemaphore);\n    #endif\n\n    stat = osOK;\n    vSemaphoreDelete (hSemaphore);\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n\nosMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {\n  QueueHandle_t hQueue;\n  int32_t mem;\n  #if (configQUEUE_REGISTRY_SIZE > 0)\n  const char *name;\n  #endif\n\n  hQueue = NULL;\n\n  if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) {\n    mem = -1;\n\n    if (attr != NULL) {\n      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&\n          (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {\n        mem = 1;\n      }\n      else {\n        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&\n            (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {\n          mem = 0;\n        }\n      }\n    }\n    else {\n      mem = 0;\n    }\n\n    if (mem == 1) {\n      hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);\n    }\n    else {\n      if (mem == 0) {\n        hQueue = xQueueCreate (msg_count, msg_size);\n      }\n    }\n\n    #if (configQUEUE_REGISTRY_SIZE > 0)\n    if (hQueue != NULL) {\n      if (attr != NULL) {\n        name = attr->name;\n      } else {\n        name = NULL;\n      }\n      vQueueAddToRegistry (hQueue, name);\n    }\n    #endif\n\n  }\n\n  return ((osMessageQueueId_t)hQueue);\n}\n\nosStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  osStatus_t stat;\n  BaseType_t yield;\n\n  (void)msg_prio; /* Message priority is ignored */\n\n  stat = osOK;\n\n  if (IS_IRQ()) {\n    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {\n      stat = osErrorParameter;\n    }\n    else {\n      yield = pdFALSE;\n\n      if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {\n        stat = osErrorResource;\n      } else {\n        portYIELD_FROM_ISR (yield);\n      }\n    }\n  }\n  else {\n    if ((hQueue == NULL) || (msg_ptr == NULL)) {\n      stat = osErrorParameter;\n    }\n    else {\n      if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {\n        if (timeout != 0U) {\n          stat = osErrorTimeout;\n        } else {\n          stat = osErrorResource;\n        }\n      }\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  osStatus_t stat;\n  BaseType_t yield;\n\n  (void)msg_prio; /* Message priority is ignored */\n\n  stat = osOK;\n\n  if (IS_IRQ()) {\n    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {\n      stat = osErrorParameter;\n    }\n    else {\n      yield = pdFALSE;\n\n      if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {\n        stat = osErrorResource;\n      } else {\n        portYIELD_FROM_ISR (yield);\n      }\n    }\n  }\n  else {\n    if ((hQueue == NULL) || (msg_ptr == NULL)) {\n      stat = osErrorParameter;\n    }\n    else {\n      if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {\n        if (timeout != 0U) {\n          stat = osErrorTimeout;\n        } else {\n          stat = osErrorResource;\n        }\n      }\n    }\n  }\n\n  return (stat);\n}\n\nuint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {\n  StaticQueue_t *mq = (StaticQueue_t *)mq_id;\n  uint32_t capacity;\n\n  if (mq == NULL) {\n    capacity = 0U;\n  } else {\n    /* capacity = pxQueue->uxLength */\n    capacity = mq->uxDummy4[1];\n  }\n\n  return (capacity);\n}\n\nuint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {\n  StaticQueue_t *mq = (StaticQueue_t *)mq_id;\n  uint32_t size;\n\n  if (mq == NULL) {\n    size = 0U;\n  } else {\n    /* size = pxQueue->uxItemSize */\n    size = mq->uxDummy4[2];\n  }\n\n  return (size);\n}\n\nuint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  UBaseType_t count;\n\n  if (hQueue == NULL) {\n    count = 0U;\n  }\n  else if (IS_IRQ()) {\n    count = uxQueueMessagesWaitingFromISR (hQueue);\n  }\n  else {\n    count = uxQueueMessagesWaiting (hQueue);\n  }\n\n  return ((uint32_t)count);\n}\n\nuint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {\n  StaticQueue_t *mq = (StaticQueue_t *)mq_id;\n  uint32_t space;\n  uint32_t isrm;\n\n  if (mq == NULL) {\n    space = 0U;\n  }\n  else if (IS_IRQ()) {\n    isrm = taskENTER_CRITICAL_FROM_ISR();\n\n    /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */\n    space = mq->uxDummy4[1] - mq->uxDummy4[0];\n\n    taskEXIT_CRITICAL_FROM_ISR(isrm);\n  }\n  else {\n    space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq);\n  }\n\n  return (space);\n}\n\nosStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hQueue == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    (void)xQueueReset (hQueue);\n  }\n\n  return (stat);\n}\n\nosStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  osStatus_t stat;\n\n#ifndef USE_FreeRTOS_HEAP_1\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hQueue == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    #if (configQUEUE_REGISTRY_SIZE > 0)\n    vQueueUnregisterQueue (hQueue);\n    #endif\n\n    stat = osOK;\n    vQueueDelete (hQueue);\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n\n/* Callback function prototypes */\nextern void vApplicationIdleHook (void);\nextern void vApplicationTickHook (void);\nextern void vApplicationMallocFailedHook (void);\nextern void vApplicationDaemonTaskStartupHook (void);\nextern void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName);\n\n/**\n  Dummy implementation of the callback function vApplicationIdleHook().\n*/\n#if (configUSE_IDLE_HOOK == 1)\n__WEAK void vApplicationIdleHook (void){}\n#endif\n\n/**\n  Dummy implementation of the callback function vApplicationTickHook().\n*/\n#if (configUSE_TICK_HOOK == 1)\n __WEAK void vApplicationTickHook (void){}\n#endif\n\n/**\n  Dummy implementation of the callback function vApplicationMallocFailedHook().\n*/\n#if (configUSE_MALLOC_FAILED_HOOK == 1)\n__WEAK void vApplicationMallocFailedHook (void){}\n#endif\n\n/**\n  Dummy implementation of the callback function vApplicationDaemonTaskStartupHook().\n*/\n#if (configUSE_DAEMON_TASK_STARTUP_HOOK == 1)\n__WEAK void vApplicationDaemonTaskStartupHook (void){}\n#endif\n\n/**\n  Dummy implementation of the callback function vApplicationStackOverflowHook().\n*/\n#if (configCHECK_FOR_STACK_OVERFLOW > 0)\n__WEAK void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName) {\n  (void)xTask;\n  (void)pcTaskName;\n}\n#endif\n\n/*---------------------------------------------------------------------------*/\n\n/* External Idle and Timer task static memory allocation functions */\nextern void vApplicationGetIdleTaskMemory  (StaticTask_t **ppxIdleTaskTCBBuffer,  StackType_t **ppxIdleTaskStackBuffer,  uint32_t *pulIdleTaskStackSize);\nextern void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize);\n\n/* Idle task control block and stack */\nstatic StaticTask_t Idle_TCB;\nstatic StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];\n\n/* Timer task control block and stack */\nstatic StaticTask_t Timer_TCB;\nstatic StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];\n\n/*\n  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION\n  equals to 1 and is required for static memory allocation support.\n*/\nvoid vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {\n  *ppxIdleTaskTCBBuffer   = &Idle_TCB;\n  *ppxIdleTaskStackBuffer = &Idle_Stack[0];\n  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;\n}\n\n/*\n  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION\n  equals to 1 and is required for static memory allocation support.\n*/\nvoid vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {\n  *ppxTimerTaskTCBBuffer   = &Timer_TCB;\n  *ppxTimerTaskStackBuffer = &Timer_Stack[0];\n  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;\n}\n"
  },
  {
    "path": "examples/lib/FreeRTOS/CMSIS_RTOS_V2/cmsis_os2.h",
    "content": "/* --------------------------------------------------------------------------\n * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.\n * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.\n * --------------------------------------------------------------------------\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    cmsis_os2.h\n *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS\n *\n *---------------------------------------------------------------------------*/\n\n#ifndef CMSIS_OS2_H_\n#define CMSIS_OS2_H_\n\n#ifndef __NO_RETURN\n#if   defined(__CC_ARM)\n#define __NO_RETURN __declspec(noreturn)\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define __NO_RETURN __attribute__((__noreturn__))\n#elif defined(__GNUC__)\n#define __NO_RETURN __attribute__((__noreturn__))\n#elif defined(__ICCARM__)\n#define __NO_RETURN __noreturn\n#else\n#define __NO_RETURN\n#endif\n#endif\n\n#include <stdint.h>\n#include <stddef.h>\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n\n//  ==== Enumerations, structures, defines ====\n\n/// Version information.\ntypedef struct {\n  uint32_t                       api;   ///< API version (major.minor.rev: mmnnnrrrr dec).\n  uint32_t                    kernel;   ///< Kernel version (major.minor.rev: mmnnnrrrr dec).\n} osVersion_t;\n\n/// Kernel state.\ntypedef enum {\n  osKernelInactive        =  0,         ///< Inactive.\n  osKernelReady           =  1,         ///< Ready.\n  osKernelRunning         =  2,         ///< Running.\n  osKernelLocked          =  3,         ///< Locked.\n  osKernelSuspended       =  4,         ///< Suspended.\n  osKernelError           = -1,         ///< Error.\n  osKernelReserved        = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.\n} osKernelState_t;\n\n/// Thread state.\ntypedef enum {\n  osThreadInactive        =  0,         ///< Inactive.\n  osThreadReady           =  1,         ///< Ready.\n  osThreadRunning         =  2,         ///< Running.\n  osThreadBlocked         =  3,         ///< Blocked.\n  osThreadTerminated      =  4,         ///< Terminated.\n  osThreadError           = -1,         ///< Error.\n  osThreadReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osThreadState_t;\n\n/// Priority values.\ntypedef enum {\n  osPriorityNone          =  0,         ///< No priority (not initialized).\n  osPriorityIdle          =  1,         ///< Reserved for Idle thread.\n  osPriorityLow           =  8,         ///< Priority: low\n  osPriorityLow1          =  8+1,       ///< Priority: low + 1\n  osPriorityLow2          =  8+2,       ///< Priority: low + 2\n  osPriorityLow3          =  8+3,       ///< Priority: low + 3\n  osPriorityLow4          =  8+4,       ///< Priority: low + 4\n  osPriorityLow5          =  8+5,       ///< Priority: low + 5\n  osPriorityLow6          =  8+6,       ///< Priority: low + 6\n  osPriorityLow7          =  8+7,       ///< Priority: low + 7\n  osPriorityBelowNormal   = 16,         ///< Priority: below normal\n  osPriorityBelowNormal1  = 16+1,       ///< Priority: below normal + 1\n  osPriorityBelowNormal2  = 16+2,       ///< Priority: below normal + 2\n  osPriorityBelowNormal3  = 16+3,       ///< Priority: below normal + 3\n  osPriorityBelowNormal4  = 16+4,       ///< Priority: below normal + 4\n  osPriorityBelowNormal5  = 16+5,       ///< Priority: below normal + 5\n  osPriorityBelowNormal6  = 16+6,       ///< Priority: below normal + 6\n  osPriorityBelowNormal7  = 16+7,       ///< Priority: below normal + 7\n  osPriorityNormal        = 24,         ///< Priority: normal\n  osPriorityNormal1       = 24+1,       ///< Priority: normal + 1\n  osPriorityNormal2       = 24+2,       ///< Priority: normal + 2\n  osPriorityNormal3       = 24+3,       ///< Priority: normal + 3\n  osPriorityNormal4       = 24+4,       ///< Priority: normal + 4\n  osPriorityNormal5       = 24+5,       ///< Priority: normal + 5\n  osPriorityNormal6       = 24+6,       ///< Priority: normal + 6\n  osPriorityNormal7       = 24+7,       ///< Priority: normal + 7\n  osPriorityAboveNormal   = 32,         ///< Priority: above normal\n  osPriorityAboveNormal1  = 32+1,       ///< Priority: above normal + 1\n  osPriorityAboveNormal2  = 32+2,       ///< Priority: above normal + 2\n  osPriorityAboveNormal3  = 32+3,       ///< Priority: above normal + 3\n  osPriorityAboveNormal4  = 32+4,       ///< Priority: above normal + 4\n  osPriorityAboveNormal5  = 32+5,       ///< Priority: above normal + 5\n  osPriorityAboveNormal6  = 32+6,       ///< Priority: above normal + 6\n  osPriorityAboveNormal7  = 32+7,       ///< Priority: above normal + 7\n  osPriorityHigh          = 40,         ///< Priority: high\n  osPriorityHigh1         = 40+1,       ///< Priority: high + 1\n  osPriorityHigh2         = 40+2,       ///< Priority: high + 2\n  osPriorityHigh3         = 40+3,       ///< Priority: high + 3\n  osPriorityHigh4         = 40+4,       ///< Priority: high + 4\n  osPriorityHigh5         = 40+5,       ///< Priority: high + 5\n  osPriorityHigh6         = 40+6,       ///< Priority: high + 6\n  osPriorityHigh7         = 40+7,       ///< Priority: high + 7\n  osPriorityRealtime      = 48,         ///< Priority: realtime\n  osPriorityRealtime1     = 48+1,       ///< Priority: realtime + 1\n  osPriorityRealtime2     = 48+2,       ///< Priority: realtime + 2\n  osPriorityRealtime3     = 48+3,       ///< Priority: realtime + 3\n  osPriorityRealtime4     = 48+4,       ///< Priority: realtime + 4\n  osPriorityRealtime5     = 48+5,       ///< Priority: realtime + 5\n  osPriorityRealtime6     = 48+6,       ///< Priority: realtime + 6\n  osPriorityRealtime7     = 48+7,       ///< Priority: realtime + 7\n  osPriorityISR           = 56,         ///< Reserved for ISR deferred thread.\n  osPriorityError         = -1,         ///< System cannot determine priority or illegal priority.\n  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osPriority_t;\n\n/// Entry point of a thread.\ntypedef void (*osThreadFunc_t) (void *argument);\n\n/// Timer callback function.\ntypedef void (*osTimerFunc_t) (void *argument);\n\n/// Timer type.\ntypedef enum {\n  osTimerOnce               = 0,          ///< One-shot timer.\n  osTimerPeriodic           = 1           ///< Repeating timer.\n} osTimerType_t;\n\n// Timeout value.\n#define osWaitForever         0xFFFFFFFFU ///< Wait forever timeout value.\n\n// Flags options (\\ref osThreadFlagsWait and \\ref osEventFlagsWait).\n#define osFlagsWaitAny        0x00000000U ///< Wait for any flag (default).\n#define osFlagsWaitAll        0x00000001U ///< Wait for all flags.\n#define osFlagsNoClear        0x00000002U ///< Do not clear flags which have been specified to wait for.\n\n// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).\n#define osFlagsError          0x80000000U ///< Error indicator.\n#define osFlagsErrorUnknown   0xFFFFFFFFU ///< osError (-1).\n#define osFlagsErrorTimeout   0xFFFFFFFEU ///< osErrorTimeout (-2).\n#define osFlagsErrorResource  0xFFFFFFFDU ///< osErrorResource (-3).\n#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).\n#define osFlagsErrorISR       0xFFFFFFFAU ///< osErrorISR (-6).\n\n// Thread attributes (attr_bits in \\ref osThreadAttr_t).\n#define osThreadDetached      0x00000000U ///< Thread created in detached mode (default)\n#define osThreadJoinable      0x00000001U ///< Thread created in joinable mode\n\n// Mutex attributes (attr_bits in \\ref osMutexAttr_t).\n#define osMutexRecursive      0x00000001U ///< Recursive mutex.\n#define osMutexPrioInherit    0x00000002U ///< Priority inherit protocol.\n#define osMutexRobust         0x00000008U ///< Robust mutex.\n\n/// Status code values returned by CMSIS-RTOS functions.\ntypedef enum {\n  osOK                      =  0,         ///< Operation completed successfully.\n  osError                   = -1,         ///< Unspecified RTOS error: run-time error but no other error message fits.\n  osErrorTimeout            = -2,         ///< Operation not completed within the timeout period.\n  osErrorResource           = -3,         ///< Resource not available.\n  osErrorParameter          = -4,         ///< Parameter error.\n  osErrorNoMemory           = -5,         ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorISR                = -6,         ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osStatusReserved          = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osStatus_t;\n\n\n/// \\details Thread ID identifies the thread.\ntypedef void *osThreadId_t;\n\n/// \\details Timer ID identifies the timer.\ntypedef void *osTimerId_t;\n\n/// \\details Event Flags ID identifies the event flags.\ntypedef void *osEventFlagsId_t;\n\n/// \\details Mutex ID identifies the mutex.\ntypedef void *osMutexId_t;\n\n/// \\details Semaphore ID identifies the semaphore.\ntypedef void *osSemaphoreId_t;\n\n/// \\details Memory Pool ID identifies the memory pool.\ntypedef void *osMemoryPoolId_t;\n\n/// \\details Message Queue ID identifies the message queue.\ntypedef void *osMessageQueueId_t;\n\n\n#ifndef TZ_MODULEID_T\n#define TZ_MODULEID_T\n/// \\details Data type that identifies secure software modules called by a process.\ntypedef uint32_t TZ_ModuleId_t;\n#endif\n\n\n/// Attributes structure for thread.\ntypedef struct {\n  const char                   *name;   ///< name of the thread\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                   *stack_mem;    ///< memory for stack\n  uint32_t                stack_size;   ///< size of stack\n  osPriority_t              priority;   ///< initial thread priority (default: osPriorityNormal)\n  TZ_ModuleId_t            tz_module;   ///< TrustZone module identifier\n  uint32_t                  reserved;   ///< reserved (must be 0)\n} osThreadAttr_t;\n\n/// Attributes structure for timer.\ntypedef struct {\n  const char                   *name;   ///< name of the timer\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osTimerAttr_t;\n\n/// Attributes structure for event flags.\ntypedef struct {\n  const char                   *name;   ///< name of the event flags\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osEventFlagsAttr_t;\n\n/// Attributes structure for mutex.\ntypedef struct {\n  const char                   *name;   ///< name of the mutex\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osMutexAttr_t;\n\n/// Attributes structure for semaphore.\ntypedef struct {\n  const char                   *name;   ///< name of the semaphore\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osSemaphoreAttr_t;\n\n/// Attributes structure for memory pool.\ntypedef struct {\n  const char                   *name;   ///< name of the memory pool\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                      *mp_mem;    ///< memory for data storage\n  uint32_t                   mp_size;   ///< size of provided memory for data storage\n} osMemoryPoolAttr_t;\n\n/// Attributes structure for message queue.\ntypedef struct {\n  const char                   *name;   ///< name of the message queue\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                      *mq_mem;    ///< memory for data storage\n  uint32_t                   mq_size;   ///< size of provided memory for data storage\n} osMessageQueueAttr_t;\n\n\n//  ==== Kernel Management Functions ====\n\n/// Initialize the RTOS Kernel.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelInitialize (void);\n\n///  Get RTOS Kernel Information.\n/// \\param[out]    version       pointer to buffer for retrieving version information.\n/// \\param[out]    id_buf        pointer to buffer for retrieving kernel identification string.\n/// \\param[in]     id_size       size of buffer for kernel identification string.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);\n\n/// Get the current RTOS Kernel state.\n/// \\return current RTOS Kernel state.\nosKernelState_t osKernelGetState (void);\n\n/// Start the RTOS Kernel scheduler.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelStart (void);\n\n/// Lock the RTOS Kernel scheduler.\n/// \\return previous lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelLock (void);\n\n/// Unlock the RTOS Kernel scheduler.\n/// \\return previous lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelUnlock (void);\n\n/// Restore the RTOS Kernel scheduler lock state.\n/// \\param[in]     lock          lock state obtained by \\ref osKernelLock or \\ref osKernelUnlock.\n/// \\return new lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelRestoreLock (int32_t lock);\n\n/// Suspend the RTOS Kernel scheduler.\n/// \\return time in ticks, for how long the system can sleep or power-down.\nuint32_t osKernelSuspend (void);\n\n/// Resume the RTOS Kernel scheduler.\n/// \\param[in]     sleep_ticks   time in ticks for how long the system was in sleep or power-down mode.\nvoid osKernelResume (uint32_t sleep_ticks);\n\n/// Get the RTOS kernel tick count.\n/// \\return RTOS kernel current tick count.\nuint32_t osKernelGetTickCount (void);\n\n/// Get the RTOS kernel tick frequency.\n/// \\return frequency of the kernel tick in hertz, i.e. kernel ticks per second.\nuint32_t osKernelGetTickFreq (void);\n\n/// Get the RTOS kernel system timer count.\n/// \\return RTOS kernel current system timer count as 32-bit value.\nuint32_t osKernelGetSysTimerCount (void);\n\n/// Get the RTOS kernel system timer frequency.\n/// \\return frequency of the system timer in hertz, i.e. timer ticks per second.\nuint32_t osKernelGetSysTimerFreq (void);\n\n\n//  ==== Thread Management Functions ====\n\n/// Create a thread and add it to Active Threads.\n/// \\param[in]     func          thread function.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\param[in]     attr          thread attributes; NULL: default values.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);\n\n/// Get name of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return name as NULL terminated string.\nconst char *osThreadGetName (osThreadId_t thread_id);\n\n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId_t osThreadGetId (void);\n\n/// Get current thread state of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return current thread state of the specified thread.\nosThreadState_t osThreadGetState (osThreadId_t thread_id);\n\n/// Get stack size of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return stack size in bytes.\nuint32_t osThreadGetStackSize (osThreadId_t thread_id);\n\n/// Get available stack space of a thread based on stack watermark recording during execution.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return remaining stack space in bytes.\nuint32_t osThreadGetStackSpace (osThreadId_t thread_id);\n\n/// Change priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);\n\n/// Get current priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return current priority value of the specified thread.\nosPriority_t osThreadGetPriority (osThreadId_t thread_id);\n\n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadYield (void);\n\n/// Suspend execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadSuspend (osThreadId_t thread_id);\n\n/// Resume execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadResume (osThreadId_t thread_id);\n\n/// Detach a thread (thread storage can be reclaimed when thread terminates).\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadDetach (osThreadId_t thread_id);\n\n/// Wait for specified thread to terminate.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadJoin (osThreadId_t thread_id);\n\n/// Terminate execution of current running thread.\n__NO_RETURN void osThreadExit (void);\n\n/// Terminate execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadTerminate (osThreadId_t thread_id);\n\n/// Get number of active threads.\n/// \\return number of active threads.\nuint32_t osThreadGetCount (void);\n\n/// Enumerate active threads.\n/// \\param[out]    thread_array  pointer to array for retrieving thread IDs.\n/// \\param[in]     array_items   maximum number of items in array for retrieving thread IDs.\n/// \\return number of enumerated threads.\nuint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);\n\n\n//  ==== Thread Flags Functions ====\n\n/// Set the specified Thread Flags of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\param[in]     flags         specifies the flags of the thread that shall be set.\n/// \\return thread flags after setting or error code if highest bit set.\nuint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);\n\n/// Clear the specified Thread Flags of current running thread.\n/// \\param[in]     flags         specifies the flags of the thread that shall be cleared.\n/// \\return thread flags before clearing or error code if highest bit set.\nuint32_t osThreadFlagsClear (uint32_t flags);\n\n/// Get the current Thread Flags of current running thread.\n/// \\return current thread flags.\nuint32_t osThreadFlagsGet (void);\n\n/// Wait for one or more Thread Flags of the current running thread to become signaled.\n/// \\param[in]     flags         specifies the flags to wait for.\n/// \\param[in]     options       specifies flags options (osFlagsXxxx).\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return thread flags before clearing or error code if highest bit set.\nuint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);\n\n\n//  ==== Generic Wait Functions ====\n\n/// Wait for Timeout (Time Delay).\n/// \\param[in]     ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osDelay (uint32_t ticks);\n\n/// Wait until specified time.\n/// \\param[in]     ticks         absolute time in ticks\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osDelayUntil (uint32_t ticks);\n\n\n//  ==== Timer Management Functions ====\n\n/// Create and Initialize a timer.\n/// \\param[in]     func          function pointer to callback function.\n/// \\param[in]     type          \\ref osTimerOnce for one-shot or \\ref osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer callback function.\n/// \\param[in]     attr          timer attributes; NULL: default values.\n/// \\return timer ID for reference by other functions or NULL in case of error.\nosTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);\n\n/// Get name of a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return name as NULL terminated string.\nconst char *osTimerGetName (osTimerId_t timer_id);\n\n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\param[in]     ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);\n\n/// Stop a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerStop (osTimerId_t timer_id);\n\n/// Check if a timer is running.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return 0 not running, 1 running.\nuint32_t osTimerIsRunning (osTimerId_t timer_id);\n\n/// Delete a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerDelete (osTimerId_t timer_id);\n\n\n//  ==== Event Flags Management Functions ====\n\n/// Create and Initialize an Event Flags object.\n/// \\param[in]     attr          event flags attributes; NULL: default values.\n/// \\return event flags ID for reference by other functions or NULL in case of error.\nosEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);\n\n/// Get name of an Event Flags object.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return name as NULL terminated string.\nconst char *osEventFlagsGetName (osEventFlagsId_t ef_id);\n\n/// Set the specified Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags that shall be set.\n/// \\return event flags after setting or error code if highest bit set.\nuint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);\n\n/// Clear the specified Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags that shall be cleared.\n/// \\return event flags before clearing or error code if highest bit set.\nuint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);\n\n/// Get the current Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return current event flags.\nuint32_t osEventFlagsGet (osEventFlagsId_t ef_id);\n\n/// Wait for one or more Event Flags to become signaled.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags to wait for.\n/// \\param[in]     options       specifies flags options (osFlagsXxxx).\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flags before clearing or error code if highest bit set.\nuint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);\n\n/// Delete an Event Flags object.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);\n\n\n//  ==== Mutex Management Functions ====\n\n/// Create and Initialize a Mutex object.\n/// \\param[in]     attr          mutex attributes; NULL: default values.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\nosMutexId_t osMutexNew (const osMutexAttr_t *attr);\n\n/// Get name of a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return name as NULL terminated string.\nconst char *osMutexGetName (osMutexId_t mutex_id);\n\n/// Acquire a Mutex or timeout if it is locked.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);\n\n/// Release a Mutex that was acquired by \\ref osMutexAcquire.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexRelease (osMutexId_t mutex_id);\n\n/// Get Thread which owns a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return thread ID of owner thread or NULL when mutex was not acquired.\nosThreadId_t osMutexGetOwner (osMutexId_t mutex_id);\n\n/// Delete a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexDelete (osMutexId_t mutex_id);\n\n\n//  ==== Semaphore Management Functions ====\n\n/// Create and Initialize a Semaphore object.\n/// \\param[in]     max_count     maximum number of available tokens.\n/// \\param[in]     initial_count initial number of available tokens.\n/// \\param[in]     attr          semaphore attributes; NULL: default values.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\nosSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);\n\n/// Get name of a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return name as NULL terminated string.\nconst char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);\n\n/// Acquire a Semaphore token or timeout if no tokens are available.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);\n\n/// Release a Semaphore token up to the initial maximum count.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);\n\n/// Get current Semaphore token count.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return number of tokens available.\nuint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);\n\n/// Delete a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);\n\n\n//  ==== Memory Pool Management Functions ====\n\n/// Create and Initialize a Memory Pool object.\n/// \\param[in]     block_count   maximum number of memory blocks in memory pool.\n/// \\param[in]     block_size    memory block size in bytes.\n/// \\param[in]     attr          memory pool attributes; NULL: default values.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\nosMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);\n\n/// Get name of a Memory Pool object.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return name as NULL terminated string.\nconst char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);\n\n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return address of the allocated memory block or NULL in case of no memory is available.\nvoid *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);\n\n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\param[in]     block         address of the allocated memory block to be returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);\n\n/// Get maximum number of memory blocks in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return maximum number of memory blocks.\nuint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);\n\n/// Get memory block size in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return memory block size in bytes.\nuint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);\n\n/// Get number of memory blocks used in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return number of memory blocks used.\nuint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);\n\n/// Get number of memory blocks available in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return number of memory blocks available.\nuint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);\n\n/// Delete a Memory Pool object.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);\n\n\n//  ==== Message Queue Management Functions ====\n\n/// Create and Initialize a Message Queue object.\n/// \\param[in]     msg_count     maximum number of messages in queue.\n/// \\param[in]     msg_size      maximum message size in bytes.\n/// \\param[in]     attr          message queue attributes; NULL: default values.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\nosMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);\n\n/// Get name of a Message Queue object.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return name as NULL terminated string.\nconst char *osMessageQueueGetName (osMessageQueueId_t mq_id);\n\n/// Put a Message into a Queue or timeout if Queue is full.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\param[in]     msg_ptr       pointer to buffer with message to put into a queue.\n/// \\param[in]     msg_prio      message priority.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);\n\n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\param[out]    msg_ptr       pointer to buffer for message to get from a queue.\n/// \\param[out]    msg_prio      pointer to buffer for message priority or NULL.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);\n\n/// Get maximum number of messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return maximum number of messages.\nuint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);\n\n/// Get maximum message size in a Memory Pool.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return maximum message size in bytes.\nuint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);\n\n/// Get number of queued messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return number of queued messages.\nuint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);\n\n/// Get number of available slots for messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return number of available slots for messages.\nuint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);\n\n/// Reset a Message Queue to initial empty state.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);\n\n/// Delete a Message Queue object.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);\n\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif  // CMSIS_OS2_H_\n"
  },
  {
    "path": "examples/lib/FreeRTOS/croutine.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"croutine.h\"\n\n/* Remove the whole file is co-routines are not being used. */\n#if( configUSE_CO_ROUTINES != 0 )\n\n/*\n * Some kernel aware debuggers require data to be viewed to be global, rather\n * than file scope.\n */\n#ifdef portREMOVE_STATIC_QUALIFIER\n\t#define static\n#endif\n\n\n/* Lists for ready and blocked co-routines. --------------------*/\nstatic List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];\t/*< Prioritised ready co-routines. */\nstatic List_t xDelayedCoRoutineList1;\t\t\t\t\t\t\t\t\t/*< Delayed co-routines. */\nstatic List_t xDelayedCoRoutineList2;\t\t\t\t\t\t\t\t\t/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */\nstatic List_t * pxDelayedCoRoutineList;\t\t\t\t\t\t\t\t\t/*< Points to the delayed co-routine list currently being used. */\nstatic List_t * pxOverflowDelayedCoRoutineList;\t\t\t\t\t\t\t/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */\nstatic List_t xPendingReadyCoRoutineList;\t\t\t\t\t\t\t\t/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */\n\n/* Other file private variables. --------------------------------*/\nCRCB_t * pxCurrentCoRoutine = NULL;\nstatic UBaseType_t uxTopCoRoutineReadyPriority = 0;\nstatic TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;\n\n/* The initial state of the co-routine when it is created. */\n#define corINITIAL_STATE\t( 0 )\n\n/*\n * Place the co-routine represented by pxCRCB into the appropriate ready queue\n * for the priority.  It is inserted at the end of the list.\n *\n * This macro accesses the co-routine ready lists and therefore must not be\n * used from within an ISR.\n */\n#define prvAddCoRoutineToReadyQueue( pxCRCB )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tuxTopCoRoutineReadyPriority = pxCRCB->uxPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tvListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );\t\\\n}\n\n/*\n * Utility to ready all the lists used by the scheduler.  This is called\n * automatically upon the creation of the first co-routine.\n */\nstatic void prvInitialiseCoRoutineLists( void );\n\n/*\n * Co-routines that are readied by an interrupt cannot be placed directly into\n * the ready lists (there is no mutual exclusion).  Instead they are placed in\n * in the pending ready list in order that they can later be moved to the ready\n * list by the co-routine scheduler.\n */\nstatic void prvCheckPendingReadyList( void );\n\n/*\n * Macro that looks at the list of co-routines that are currently delayed to\n * see if any require waking.\n *\n * Co-routines are stored in the queue in the order of their wake time -\n * meaning once one co-routine has been found whose timer has not expired\n * we need not look any further down the list.\n */\nstatic void prvCheckDelayedList( void );\n\n/*-----------------------------------------------------------*/\n\nBaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )\n{\nBaseType_t xReturn;\nCRCB_t *pxCoRoutine;\n\n\t/* Allocate the memory that will store the co-routine control block. */\n\tpxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );\n\tif( pxCoRoutine )\n\t{\n\t\t/* If pxCurrentCoRoutine is NULL then this is the first co-routine to\n\t\tbe created and the co-routine data structures need initialising. */\n\t\tif( pxCurrentCoRoutine == NULL )\n\t\t{\n\t\t\tpxCurrentCoRoutine = pxCoRoutine;\n\t\t\tprvInitialiseCoRoutineLists();\n\t\t}\n\n\t\t/* Check the priority is within limits. */\n\t\tif( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )\n\t\t{\n\t\t\tuxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;\n\t\t}\n\n\t\t/* Fill out the co-routine control block from the function parameters. */\n\t\tpxCoRoutine->uxState = corINITIAL_STATE;\n\t\tpxCoRoutine->uxPriority = uxPriority;\n\t\tpxCoRoutine->uxIndex = uxIndex;\n\t\tpxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;\n\n\t\t/* Initialise all the other co-routine control block parameters. */\n\t\tvListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );\n\t\tvListInitialiseItem( &( pxCoRoutine->xEventListItem ) );\n\n\t\t/* Set the co-routine control block as a link back from the ListItem_t.\n\t\tThis is so we can get back to the containing CRCB from a generic item\n\t\tin a list. */\n\t\tlistSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );\n\t\tlistSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );\n\n\t\t/* Event lists are always in priority order. */\n\t\tlistSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );\n\n\t\t/* Now the co-routine has been initialised it can be added to the ready\n\t\tlist at the correct priority. */\n\t\tprvAddCoRoutineToReadyQueue( pxCoRoutine );\n\n\t\txReturn = pdPASS;\n\t}\n\telse\n\t{\n\t\txReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )\n{\nTickType_t xTimeToWake;\n\n\t/* Calculate the time to wake - this may overflow but this is\n\tnot a problem. */\n\txTimeToWake = xCoRoutineTickCount + xTicksToDelay;\n\n\t/* We must remove ourselves from the ready list before adding\n\tourselves to the blocked list as the same list item is used for\n\tboth lists. */\n\t( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n\n\t/* The list item will be inserted in wake time order. */\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );\n\n\tif( xTimeToWake < xCoRoutineTickCount )\n\t{\n\t\t/* Wake time has overflowed.  Place this item in the\n\t\toverflow list. */\n\t\tvListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n\t}\n\telse\n\t{\n\t\t/* The wake time has not overflowed, so we can use the\n\t\tcurrent block list. */\n\t\tvListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n\t}\n\n\tif( pxEventList )\n\t{\n\t\t/* Also add the co-routine to an event list.  If this is done then the\n\t\tfunction must be called with interrupts disabled. */\n\t\tvListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckPendingReadyList( void )\n{\n\t/* Are there any co-routines waiting to get moved to the ready list?  These\n\tare co-routines that have been readied by an ISR.  The ISR cannot access\n\tthe\tready lists itself. */\n\twhile( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )\n\t{\n\t\tCRCB_t *pxUnblockedCRCB;\n\n\t\t/* The pending ready list can be accessed by an ISR. */\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tpxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );\n\t\t\t( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\t( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );\n\t\tprvAddCoRoutineToReadyQueue( pxUnblockedCRCB );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckDelayedList( void )\n{\nCRCB_t *pxCRCB;\n\n\txPassedTicks = xTaskGetTickCount() - xLastTickCount;\n\twhile( xPassedTicks )\n\t{\n\t\txCoRoutineTickCount++;\n\t\txPassedTicks--;\n\n\t\t/* If the tick count has overflowed we need to swap the ready lists. */\n\t\tif( xCoRoutineTickCount == 0 )\n\t\t{\n\t\t\tList_t * pxTemp;\n\n\t\t\t/* Tick count has overflowed so we need to swap the delay lists.  If there are\n\t\t\tany items in pxDelayedCoRoutineList here then there is an error! */\n\t\t\tpxTemp = pxDelayedCoRoutineList;\n\t\t\tpxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;\n\t\t\tpxOverflowDelayedCoRoutineList = pxTemp;\n\t\t}\n\n\t\t/* See if this tick has made a timeout expire. */\n\t\twhile( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )\n\t\t{\n\t\t\tpxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );\n\n\t\t\tif( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )\n\t\t\t{\n\t\t\t\t/* Timeout not yet expired. */\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tportDISABLE_INTERRUPTS();\n\t\t\t{\n\t\t\t\t/* The event could have occurred just before this critical\n\t\t\t\tsection.  If this is the case then the generic list item will\n\t\t\t\thave been moved to the pending ready list and the following\n\t\t\t\tline is still valid.  Also the pvContainer parameter will have\n\t\t\t\tbeen set to NULL so the following lines are also valid. */\n\t\t\t\t( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );\n\n\t\t\t\t/* Is the co-routine waiting on an event also? */\n\t\t\t\tif( pxCRCB->xEventListItem.pxContainer )\n\t\t\t\t{\n\t\t\t\t\t( void ) uxListRemove( &( pxCRCB->xEventListItem ) );\n\t\t\t\t}\n\t\t\t}\n\t\t\tportENABLE_INTERRUPTS();\n\n\t\t\tprvAddCoRoutineToReadyQueue( pxCRCB );\n\t\t}\n\t}\n\n\txLastTickCount = xCoRoutineTickCount;\n}\n/*-----------------------------------------------------------*/\n\nvoid vCoRoutineSchedule( void )\n{\n\t/* See if any co-routines readied by events need moving to the ready lists. */\n\tprvCheckPendingReadyList();\n\n\t/* See if any delayed co-routines have timed out. */\n\tprvCheckDelayedList();\n\n\t/* Find the highest priority queue that contains ready co-routines. */\n\twhile( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )\n\t{\n\t\tif( uxTopCoRoutineReadyPriority == 0 )\n\t\t{\n\t\t\t/* No more co-routines to check. */\n\t\t\treturn;\n\t\t}\n\t\t--uxTopCoRoutineReadyPriority;\n\t}\n\n\t/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines\n\t of the\tsame priority get an equal share of the processor time. */\n\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );\n\n\t/* Call the co-routine. */\n\t( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );\n\n\treturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseCoRoutineLists( void )\n{\nUBaseType_t uxPriority;\n\n\tfor( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )\n\t{\n\t\tvListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );\n\t}\n\n\tvListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );\n\tvListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );\n\tvListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );\n\n\t/* Start with pxDelayedCoRoutineList using list1 and the\n\tpxOverflowDelayedCoRoutineList using list2. */\n\tpxDelayedCoRoutineList = &xDelayedCoRoutineList1;\n\tpxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )\n{\nCRCB_t *pxUnblockedCRCB;\nBaseType_t xReturn;\n\n\t/* This function is called from within an interrupt.  It can only access\n\tevent lists and the pending ready list.  This function assumes that a\n\tcheck has already been made to ensure pxEventList is not empty. */\n\tpxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\n\t( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );\n\tvListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );\n\n\tif( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n\n#endif /* configUSE_CO_ROUTINES == 0 */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/event_groups.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"timers.h\"\n#include \"event_groups.h\"\n\n/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */\n\n/* The following bit fields convey control information in a task's event list\nitem value.  It is important they don't clash with the\ntaskEVENT_LIST_ITEM_VALUE_IN_USE definition. */\n#if configUSE_16_BIT_TICKS == 1\n\t#define eventCLEAR_EVENTS_ON_EXIT_BIT\t0x0100U\n\t#define eventUNBLOCKED_DUE_TO_BIT_SET\t0x0200U\n\t#define eventWAIT_FOR_ALL_BITS\t\t\t0x0400U\n\t#define eventEVENT_BITS_CONTROL_BYTES\t0xff00U\n#else\n\t#define eventCLEAR_EVENTS_ON_EXIT_BIT\t0x01000000UL\n\t#define eventUNBLOCKED_DUE_TO_BIT_SET\t0x02000000UL\n\t#define eventWAIT_FOR_ALL_BITS\t\t\t0x04000000UL\n\t#define eventEVENT_BITS_CONTROL_BYTES\t0xff000000UL\n#endif\n\ntypedef struct EventGroupDef_t\n{\n\tEventBits_t uxEventBits;\n\tList_t xTasksWaitingForBits;\t\t/*< List of tasks waiting for a bit to be set. */\n\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxEventGroupNumber;\n\t#endif\n\n\t#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\t\tuint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */\n\t#endif\n} EventGroup_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Test the bits set in uxCurrentEventBits to see if the wait condition is met.\n * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is\n * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor\n * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the\n * wait condition is met if any of the bits set in uxBitsToWait for are also set\n * in uxCurrentEventBits.\n */\nstatic BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tEventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )\n\t{\n\tEventGroup_t *pxEventBits;\n\n\t\t/* A StaticEventGroup_t object must be provided. */\n\t\tconfigASSERT( pxEventGroupBuffer );\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticEventGroup_t equals the size of the real\n\t\t\tevent group structure. */\n\t\t\tvolatile size_t xSize = sizeof( StaticEventGroup_t );\n\t\t\tconfigASSERT( xSize == sizeof( EventGroup_t ) );\n\t\t} /*lint !e529 xSize is referenced if configASSERT() is defined. */\n\t\t#endif /* configASSERT_DEFINED */\n\n\t\t/* The user has provided a statically allocated event group - use it. */\n\t\tpxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */\n\n\t\tif( pxEventBits != NULL )\n\t\t{\n\t\t\tpxEventBits->uxEventBits = 0;\n\t\t\tvListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\n\n\t\t\t#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* Both static and dynamic allocation can be used, so note that\n\t\t\t\tthis event group was created statically in case the event group\n\t\t\t\tis later deleted. */\n\t\t\t\tpxEventBits->ucStaticallyAllocated = pdTRUE;\n\t\t\t}\n\t\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\n\t\t\ttraceEVENT_GROUP_CREATE( pxEventBits );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* xEventGroupCreateStatic should only ever be called with\n\t\t\tpxEventGroupBuffer pointing to a pre-allocated (compile time\n\t\t\tallocated) StaticEventGroup_t variable. */\n\t\t\ttraceEVENT_GROUP_CREATE_FAILED();\n\t\t}\n\n\t\treturn pxEventBits;\n\t}\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tEventGroupHandle_t xEventGroupCreate( void )\n\t{\n\tEventGroup_t *pxEventBits;\n\n\t\t/* Allocate the event group.  Justification for MISRA deviation as\n\t\tfollows:  pvPortMalloc() always ensures returned memory blocks are\n\t\taligned per the requirements of the MCU stack.  In this case\n\t\tpvPortMalloc() must return a pointer that is guaranteed to meet the\n\t\talignment requirements of the EventGroup_t structure - which (if you\n\t\tfollow it through) is the alignment requirements of the TickType_t type\n\t\t(EventBits_t being of TickType_t itself).  Therefore, whenever the\n\t\tstack alignment requirements are greater than or equal to the\n\t\tTickType_t alignment requirements the cast is safe.  In other cases,\n\t\twhere the natural word size of the architecture is less than\n\t\tsizeof( TickType_t ), the TickType_t variables will be accessed in two\n\t\tor more reads operations, and the alignment requirements is only that\n\t\tof each individual read. */\n\t\tpxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */\n\n\t\tif( pxEventBits != NULL )\n\t\t{\n\t\t\tpxEventBits->uxEventBits = 0;\n\t\t\tvListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\n\n\t\t\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* Both static and dynamic allocation can be used, so note this\n\t\t\t\tevent group was allocated statically in case the event group is\n\t\t\t\tlater deleted. */\n\t\t\t\tpxEventBits->ucStaticallyAllocated = pdFALSE;\n\t\t\t}\n\t\t\t#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n\t\t\ttraceEVENT_GROUP_CREATE( pxEventBits );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */\n\t\t}\n\n\t\treturn pxEventBits;\n\t}\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )\n{\nEventBits_t uxOriginalBitValue, uxReturn;\nEventGroup_t *pxEventBits = xEventGroup;\nBaseType_t xAlreadyYielded;\nBaseType_t xTimeoutOccurred = pdFALSE;\n\n\tconfigASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\tconfigASSERT( uxBitsToWaitFor != 0 );\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\tvTaskSuspendAll();\n\t{\n\t\tuxOriginalBitValue = pxEventBits->uxEventBits;\n\n\t\t( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );\n\n\t\tif( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )\n\t\t{\n\t\t\t/* All the rendezvous bits are now set - no need to block. */\n\t\t\tuxReturn = ( uxOriginalBitValue | uxBitsToSet );\n\n\t\t\t/* Rendezvous always clear the bits.  They will have been cleared\n\t\t\talready unless this is the only task in the rendezvous. */\n\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\n\t\t\txTicksToWait = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif( xTicksToWait != ( TickType_t ) 0 )\n\t\t\t{\n\t\t\t\ttraceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );\n\n\t\t\t\t/* Store the bits that the calling task is waiting for in the\n\t\t\t\ttask's event list item so the kernel knows when a match is\n\t\t\t\tfound.  Then enter the blocked state. */\n\t\t\t\tvTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );\n\n\t\t\t\t/* This assignment is obsolete as uxReturn will get set after\n\t\t\t\tthe task unblocks, but some compilers mistakenly generate a\n\t\t\t\twarning about uxReturn being returned without being set if the\n\t\t\t\tassignment is omitted. */\n\t\t\t\tuxReturn = 0;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The rendezvous bits were not set, but no block time was\n\t\t\t\tspecified - just return the current event bit value. */\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\n\t\t\t\txTimeoutOccurred = pdTRUE;\n\t\t\t}\n\t\t}\n\t}\n\txAlreadyYielded = xTaskResumeAll();\n\n\tif( xTicksToWait != ( TickType_t ) 0 )\n\t{\n\t\tif( xAlreadyYielded == pdFALSE )\n\t\t{\n\t\t\tportYIELD_WITHIN_API();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* The task blocked to wait for its required bits to be set - at this\n\t\tpoint either the required bits were set or the block time expired.  If\n\t\tthe required bits were set they will have been stored in the task's\n\t\tevent list item, and they should now be retrieved then cleared. */\n\t\tuxReturn = uxTaskResetEventItemValue();\n\n\t\tif( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\n\t\t{\n\t\t\t/* The task timed out, just return the current event bit value. */\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\n\n\t\t\t\t/* Although the task got here because it timed out before the\n\t\t\t\tbits it was waiting for were set, it is possible that since it\n\t\t\t\tunblocked another task has set the bits.  If this is the case\n\t\t\t\tthen it needs to clear the bits before exiting. */\n\t\t\t\tif( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )\n\t\t\t\t{\n\t\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\txTimeoutOccurred = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The task unblocked because the bits were set. */\n\t\t}\n\n\t\t/* Control bits might be set as the task had blocked should not be\n\t\treturned. */\n\t\tuxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\n\t}\n\n\ttraceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );\n\n\t/* Prevent compiler warnings when trace macros are not used. */\n\t( void ) xTimeoutOccurred;\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )\n{\nEventGroup_t *pxEventBits = xEventGroup;\nEventBits_t uxReturn, uxControlBits = 0;\nBaseType_t xWaitConditionMet, xAlreadyYielded;\nBaseType_t xTimeoutOccurred = pdFALSE;\n\n\t/* Check the user is not attempting to wait on the bits used by the kernel\n\titself, and that at least one bit is being requested. */\n\tconfigASSERT( xEventGroup );\n\tconfigASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\tconfigASSERT( uxBitsToWaitFor != 0 );\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\tvTaskSuspendAll();\n\t{\n\t\tconst EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;\n\n\t\t/* Check to see if the wait condition is already met or not. */\n\t\txWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );\n\n\t\tif( xWaitConditionMet != pdFALSE )\n\t\t{\n\t\t\t/* The wait condition has already been met so there is no need to\n\t\t\tblock. */\n\t\t\tuxReturn = uxCurrentEventBits;\n\t\t\txTicksToWait = ( TickType_t ) 0;\n\n\t\t\t/* Clear the wait bits if requested to do so. */\n\t\t\tif( xClearOnExit != pdFALSE )\n\t\t\t{\n\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse if( xTicksToWait == ( TickType_t ) 0 )\n\t\t{\n\t\t\t/* The wait condition has not been met, but no block time was\n\t\t\tspecified, so just return the current value. */\n\t\t\tuxReturn = uxCurrentEventBits;\n\t\t\txTimeoutOccurred = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The task is going to block to wait for its required bits to be\n\t\t\tset.  uxControlBits are used to remember the specified behaviour of\n\t\t\tthis call to xEventGroupWaitBits() - for use when the event bits\n\t\t\tunblock the task. */\n\t\t\tif( xClearOnExit != pdFALSE )\n\t\t\t{\n\t\t\t\tuxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tif( xWaitForAllBits != pdFALSE )\n\t\t\t{\n\t\t\t\tuxControlBits |= eventWAIT_FOR_ALL_BITS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Store the bits that the calling task is waiting for in the\n\t\t\ttask's event list item so the kernel knows when a match is\n\t\t\tfound.  Then enter the blocked state. */\n\t\t\tvTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );\n\n\t\t\t/* This is obsolete as it will get set after the task unblocks, but\n\t\t\tsome compilers mistakenly generate a warning about the variable\n\t\t\tbeing returned without being set if it is not done. */\n\t\t\tuxReturn = 0;\n\n\t\t\ttraceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );\n\t\t}\n\t}\n\txAlreadyYielded = xTaskResumeAll();\n\n\tif( xTicksToWait != ( TickType_t ) 0 )\n\t{\n\t\tif( xAlreadyYielded == pdFALSE )\n\t\t{\n\t\t\tportYIELD_WITHIN_API();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* The task blocked to wait for its required bits to be set - at this\n\t\tpoint either the required bits were set or the block time expired.  If\n\t\tthe required bits were set they will have been stored in the task's\n\t\tevent list item, and they should now be retrieved then cleared. */\n\t\tuxReturn = uxTaskResetEventItemValue();\n\n\t\tif( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\t/* The task timed out, just return the current event bit value. */\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\n\n\t\t\t\t/* It is possible that the event bits were updated between this\n\t\t\t\ttask leaving the Blocked state and running again. */\n\t\t\t\tif( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xClearOnExit != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t\txTimeoutOccurred = pdTRUE;\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The task unblocked because the bits were set. */\n\t\t}\n\n\t\t/* The task blocked so control bits may have been set. */\n\t\tuxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\n\t}\n\ttraceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );\n\n\t/* Prevent compiler warnings when trace macros are not used. */\n\t( void ) xTimeoutOccurred;\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\n{\nEventGroup_t *pxEventBits = xEventGroup;\nEventBits_t uxReturn;\n\n\t/* Check the user is not attempting to clear the bits used by the kernel\n\titself. */\n\tconfigASSERT( xEventGroup );\n\tconfigASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\ttraceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );\n\n\t\t/* The value returned is the event group value prior to the bits being\n\t\tcleared. */\n\t\tuxReturn = pxEventBits->uxEventBits;\n\n\t\t/* Clear the bits. */\n\t\tpxEventBits->uxEventBits &= ~uxBitsToClear;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\n\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\n\t{\n\t\tBaseType_t xReturn;\n\n\t\ttraceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );\n\t\txReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */\n\n\t\treturn xReturn;\n\t}\n\n#endif\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )\n{\nUBaseType_t uxSavedInterruptStatus;\nEventGroup_t const * const pxEventBits = xEventGroup;\nEventBits_t uxReturn;\n\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tuxReturn = pxEventBits->uxEventBits;\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn uxReturn;\n} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )\n{\nListItem_t *pxListItem, *pxNext;\nListItem_t const *pxListEnd;\nList_t const * pxList;\nEventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;\nEventGroup_t *pxEventBits = xEventGroup;\nBaseType_t xMatchFound = pdFALSE;\n\n\t/* Check the user is not attempting to set the bits used by the kernel\n\titself. */\n\tconfigASSERT( xEventGroup );\n\tconfigASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\n\tpxList = &( pxEventBits->xTasksWaitingForBits );\n\tpxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\tvTaskSuspendAll();\n\t{\n\t\ttraceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );\n\n\t\tpxListItem = listGET_HEAD_ENTRY( pxList );\n\n\t\t/* Set the bits. */\n\t\tpxEventBits->uxEventBits |= uxBitsToSet;\n\n\t\t/* See if the new bit value should unblock any tasks. */\n\t\twhile( pxListItem != pxListEnd )\n\t\t{\n\t\t\tpxNext = listGET_NEXT( pxListItem );\n\t\t\tuxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );\n\t\t\txMatchFound = pdFALSE;\n\n\t\t\t/* Split the bits waited for from the control bits. */\n\t\t\tuxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;\n\t\t\tuxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;\n\n\t\t\tif( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Just looking for single bit being set. */\n\t\t\t\tif( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\txMatchFound = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )\n\t\t\t{\n\t\t\t\t/* All bits are set. */\n\t\t\t\txMatchFound = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Need all bits to be set, but not all the bits were set. */\n\t\t\t}\n\n\t\t\tif( xMatchFound != pdFALSE )\n\t\t\t{\n\t\t\t\t/* The bits match.  Should the bits be cleared on exit? */\n\t\t\t\tif( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\tuxBitsToClear |= uxBitsWaitedFor;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t/* Store the actual event flag value in the task's event list\n\t\t\t\titem before removing the task from the event list.  The\n\t\t\t\teventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows\n\t\t\t\tthat is was unblocked due to its required bits matching, rather\n\t\t\t\tthan because it timed out. */\n\t\t\t\tvTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );\n\t\t\t}\n\n\t\t\t/* Move onto the next list item.  Note pxListItem->pxNext is not\n\t\t\tused here as the list item may have been removed from the event list\n\t\t\tand inserted into the ready/pending reading list. */\n\t\t\tpxListItem = pxNext;\n\t\t}\n\n\t\t/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT\n\t\tbit was set in the control word. */\n\t\tpxEventBits->uxEventBits &= ~uxBitsToClear;\n\t}\n\t( void ) xTaskResumeAll();\n\n\treturn pxEventBits->uxEventBits;\n}\n/*-----------------------------------------------------------*/\n\nvoid vEventGroupDelete( EventGroupHandle_t xEventGroup )\n{\nEventGroup_t *pxEventBits = xEventGroup;\nconst List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );\n\n\tvTaskSuspendAll();\n\t{\n\t\ttraceEVENT_GROUP_DELETE( xEventGroup );\n\n\t\twhile( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\t/* Unblock the task, returning 0 as the event list is being deleted\n\t\t\tand cannot therefore have any bits set. */\n\t\t\tconfigASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );\n\t\t\tvTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );\n\t\t}\n\n\t\t#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )\n\t\t{\n\t\t\t/* The event group can only have been allocated dynamically - free\n\t\t\tit again. */\n\t\t\tvPortFree( pxEventBits );\n\t\t}\n\t\t#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\t\t{\n\t\t\t/* The event group could have been allocated statically or\n\t\t\tdynamically, so check before attempting to free the memory. */\n\t\t\tif( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )\n\t\t\t{\n\t\t\t\tvPortFree( pxEventBits );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\t}\n\t( void ) xTaskResumeAll();\n}\n/*-----------------------------------------------------------*/\n\n/* For internal use only - execute a 'set bits' command that was pended from\nan interrupt. */\nvoid vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )\n{\n\t( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */\n}\n/*-----------------------------------------------------------*/\n\n/* For internal use only - execute a 'clear bits' command that was pended from\nan interrupt. */\nvoid vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )\n{\n\t( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */\n}\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )\n{\nBaseType_t xWaitConditionMet = pdFALSE;\n\n\tif( xWaitForAllBits == pdFALSE )\n\t{\n\t\t/* Task only has to wait for one bit within uxBitsToWaitFor to be\n\t\tset.  Is one already set? */\n\t\tif( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )\n\t\t{\n\t\t\txWaitConditionMet = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* Task has to wait for all the bits in uxBitsToWaitFor to be set.\n\t\tAre they set already? */\n\t\tif( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )\n\t\t{\n\t\t\txWaitConditionMet = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n\treturn xWaitConditionMet;\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\n\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )\n\t{\n\tBaseType_t xReturn;\n\n\t\ttraceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );\n\t\txReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */\n\n\t\treturn xReturn;\n\t}\n\n#endif\n/*-----------------------------------------------------------*/\n\n#if (configUSE_TRACE_FACILITY == 1)\n\n\tUBaseType_t uxEventGroupGetNumber( void* xEventGroup )\n\t{\n\tUBaseType_t xReturn;\n\tEventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */\n\n\t\tif( xEventGroup == NULL )\n\t\t{\n\t\t\txReturn = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pxEventBits->uxEventGroupNumber;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber )\n\t{\n\t\t( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/FreeRTOS.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef INC_FREERTOS_H\n#define INC_FREERTOS_H\n\n/*\n * Include the generic headers required for the FreeRTOS port being used.\n */\n#include <stddef.h>\n\n/*\n * If stdint.h cannot be located then:\n *   + If using GCC ensure the -nostdint options is *not* being used.\n *   + Ensure the project's include path includes the directory in which your\n *     compiler stores stdint.h.\n *   + Set any compiler options necessary for it to support C99, as technically\n *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any\n *     other way).\n *   + The FreeRTOS download includes a simple stdint.h definition that can be\n *     used in cases where none is provided by the compiler.  The files only\n *     contains the typedefs required to build FreeRTOS.  Read the instructions\n *     in FreeRTOS/source/stdint.readme for more information.\n */\n#include <stdint.h> /* READ COMMENT ABOVE. */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Application specific configuration options. */\n#include \"FreeRTOSConfig.h\"\n\n/* Basic FreeRTOS definitions. */\n#include \"projdefs.h\"\n\n/* Definitions specific to the port being used. */\n#include \"portable.h\"\n\n/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */\n#ifndef configUSE_NEWLIB_REENTRANT\n\t#define configUSE_NEWLIB_REENTRANT 0\n#endif\n\n/* Required if struct _reent is used. */\n#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t#include <reent.h>\n#endif\n/*\n * Check all the required application specific macros have been defined.\n * These macros are application specific and (as downloaded) are defined\n * within FreeRTOSConfig.h.\n */\n\n#ifndef configMINIMAL_STACK_SIZE\n\t#error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.\n#endif\n\n#ifndef configMAX_PRIORITIES\n\t#error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#if configMAX_PRIORITIES < 1\n\t#error configMAX_PRIORITIES must be defined to be greater than or equal to 1.\n#endif\n\n#ifndef configUSE_PREEMPTION\n\t#error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_IDLE_HOOK\n\t#error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_TICK_HOOK\n\t#error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_16_BIT_TICKS\n\t#error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_CO_ROUTINES\n\t#define configUSE_CO_ROUTINES 0\n#endif\n\n#ifndef INCLUDE_vTaskPrioritySet\n\t#define INCLUDE_vTaskPrioritySet 0\n#endif\n\n#ifndef INCLUDE_uxTaskPriorityGet\n\t#define INCLUDE_uxTaskPriorityGet 0\n#endif\n\n#ifndef INCLUDE_vTaskDelete\n\t#define INCLUDE_vTaskDelete 0\n#endif\n\n#ifndef INCLUDE_vTaskSuspend\n\t#define INCLUDE_vTaskSuspend 0\n#endif\n\n#ifndef INCLUDE_vTaskDelayUntil\n\t#define INCLUDE_vTaskDelayUntil 0\n#endif\n\n#ifndef INCLUDE_vTaskDelay\n\t#define INCLUDE_vTaskDelay 0\n#endif\n\n#ifndef INCLUDE_xTaskGetIdleTaskHandle\n\t#define INCLUDE_xTaskGetIdleTaskHandle 0\n#endif\n\n#ifndef INCLUDE_xTaskAbortDelay\n\t#define INCLUDE_xTaskAbortDelay 0\n#endif\n\n#ifndef INCLUDE_xQueueGetMutexHolder\n\t#define INCLUDE_xQueueGetMutexHolder 0\n#endif\n\n#ifndef INCLUDE_xSemaphoreGetMutexHolder\n\t#define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder\n#endif\n\n#ifndef INCLUDE_xTaskGetHandle\n\t#define INCLUDE_xTaskGetHandle 0\n#endif\n\n#ifndef INCLUDE_uxTaskGetStackHighWaterMark\n\t#define INCLUDE_uxTaskGetStackHighWaterMark 0\n#endif\n\n#ifndef INCLUDE_uxTaskGetStackHighWaterMark2\n\t#define INCLUDE_uxTaskGetStackHighWaterMark2 0\n#endif\n\n#ifndef INCLUDE_eTaskGetState\n\t#define INCLUDE_eTaskGetState 0\n#endif\n\n#ifndef INCLUDE_xTaskResumeFromISR\n\t#define INCLUDE_xTaskResumeFromISR 1\n#endif\n\n#ifndef INCLUDE_xTimerPendFunctionCall\n\t#define INCLUDE_xTimerPendFunctionCall 0\n#endif\n\n#ifndef INCLUDE_xTaskGetSchedulerState\n\t#define INCLUDE_xTaskGetSchedulerState 0\n#endif\n\n#ifndef INCLUDE_xTaskGetCurrentTaskHandle\n\t#define INCLUDE_xTaskGetCurrentTaskHandle 0\n#endif\n\n#if configUSE_CO_ROUTINES != 0\n\t#ifndef configMAX_CO_ROUTINE_PRIORITIES\n\t\t#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.\n\t#endif\n#endif\n\n#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK\n\t#define configUSE_DAEMON_TASK_STARTUP_HOOK 0\n#endif\n\n#ifndef configUSE_APPLICATION_TASK_TAG\n\t#define configUSE_APPLICATION_TASK_TAG 0\n#endif\n\n#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS\n\t#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0\n#endif\n\n#ifndef configUSE_RECURSIVE_MUTEXES\n\t#define configUSE_RECURSIVE_MUTEXES 0\n#endif\n\n#ifndef configUSE_MUTEXES\n\t#define configUSE_MUTEXES 0\n#endif\n\n#ifndef configUSE_TIMERS\n\t#define configUSE_TIMERS 0\n#endif\n\n#ifndef configUSE_COUNTING_SEMAPHORES\n\t#define configUSE_COUNTING_SEMAPHORES 0\n#endif\n\n#ifndef configUSE_ALTERNATIVE_API\n\t#define configUSE_ALTERNATIVE_API 0\n#endif\n\n#ifndef portCRITICAL_NESTING_IN_TCB\n\t#define portCRITICAL_NESTING_IN_TCB 0\n#endif\n\n#ifndef configMAX_TASK_NAME_LEN\n\t#define configMAX_TASK_NAME_LEN 16\n#endif\n\n#ifndef configIDLE_SHOULD_YIELD\n\t#define configIDLE_SHOULD_YIELD\t\t1\n#endif\n\n#if configMAX_TASK_NAME_LEN < 1\n\t#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h\n#endif\n\n#ifndef configASSERT\n\t#define configASSERT( x )\n\t#define configASSERT_DEFINED 0\n#else\n\t#define configASSERT_DEFINED 1\n#endif\n\n#ifndef portMEMORY_BARRIER\n\t#define portMEMORY_BARRIER()\n#endif\n\n/* The timers module relies on xTaskGetSchedulerState(). */\n#if configUSE_TIMERS == 1\n\n\t#ifndef configTIMER_TASK_PRIORITY\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.\n\t#endif /* configTIMER_TASK_PRIORITY */\n\n\t#ifndef configTIMER_QUEUE_LENGTH\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.\n\t#endif /* configTIMER_QUEUE_LENGTH */\n\n\t#ifndef configTIMER_TASK_STACK_DEPTH\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.\n\t#endif /* configTIMER_TASK_STACK_DEPTH */\n\n#endif /* configUSE_TIMERS */\n\n#ifndef portSET_INTERRUPT_MASK_FROM_ISR\n\t#define portSET_INTERRUPT_MASK_FROM_ISR() 0\n#endif\n\n#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR\n\t#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue\n#endif\n\n#ifndef portCLEAN_UP_TCB\n\t#define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB\n#endif\n\n#ifndef portPRE_TASK_DELETE_HOOK\n\t#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )\n#endif\n\n#ifndef portSETUP_TCB\n\t#define portSETUP_TCB( pxTCB ) ( void ) pxTCB\n#endif\n\n#ifndef configQUEUE_REGISTRY_SIZE\n\t#define configQUEUE_REGISTRY_SIZE 0U\n#endif\n\n#if ( configQUEUE_REGISTRY_SIZE < 1 )\n\t#define vQueueAddToRegistry( xQueue, pcName )\n\t#define vQueueUnregisterQueue( xQueue )\n\t#define pcQueueGetName( xQueue )\n#endif\n\n#ifndef portPOINTER_SIZE_TYPE\n\t#define portPOINTER_SIZE_TYPE uint32_t\n#endif\n\n/* Remove any unused trace macros. */\n#ifndef traceSTART\n\t/* Used to perform any necessary initialisation - for example, open a file\n\tinto which trace is to be written. */\n\t#define traceSTART()\n#endif\n\n#ifndef traceEND\n\t/* Use to close a trace, for example close a file into which trace has been\n\twritten. */\n\t#define traceEND()\n#endif\n\n#ifndef traceTASK_SWITCHED_IN\n\t/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer\n\tto the task control block of the selected task. */\n\t#define traceTASK_SWITCHED_IN()\n#endif\n\n#ifndef traceINCREASE_TICK_COUNT\n\t/* Called before stepping the tick count after waking from tickless idle\n\tsleep. */\n\t#define traceINCREASE_TICK_COUNT( x )\n#endif\n\n#ifndef traceLOW_POWER_IDLE_BEGIN\n\t/* Called immediately before entering tickless idle. */\n\t#define traceLOW_POWER_IDLE_BEGIN()\n#endif\n\n#ifndef\ttraceLOW_POWER_IDLE_END\n\t/* Called when returning to the Idle task after a tickless idle. */\n\t#define traceLOW_POWER_IDLE_END()\n#endif\n\n#ifndef traceTASK_SWITCHED_OUT\n\t/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer\n\tto the task control block of the task being switched out. */\n\t#define traceTASK_SWITCHED_OUT()\n#endif\n\n#ifndef traceTASK_PRIORITY_INHERIT\n\t/* Called when a task attempts to take a mutex that is already held by a\n\tlower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task\n\tthat holds the mutex.  uxInheritedPriority is the priority the mutex holder\n\twill inherit (the priority of the task that is attempting to obtain the\n\tmuted. */\n\t#define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )\n#endif\n\n#ifndef traceTASK_PRIORITY_DISINHERIT\n\t/* Called when a task releases a mutex, the holding of which had resulted in\n\tthe task inheriting the priority of a higher priority task.\n\tpxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the\n\tmutex.  uxOriginalPriority is the task's configured (base) priority. */\n\t#define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_RECEIVE\n\t/* Task is about to block because it cannot read from a\n\tqueue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n\tupon which the read was attempted.  pxCurrentTCB points to the TCB of the\n\ttask that attempted the read. */\n\t#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_PEEK\n\t/* Task is about to block because it cannot read from a\n\tqueue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n\tupon which the read was attempted.  pxCurrentTCB points to the TCB of the\n\ttask that attempted the read. */\n\t#define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_SEND\n\t/* Task is about to block because it cannot write to a\n\tqueue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n\tupon which the write was attempted.  pxCurrentTCB points to the TCB of the\n\ttask that attempted the write. */\n\t#define traceBLOCKING_ON_QUEUE_SEND( pxQueue )\n#endif\n\n#ifndef configCHECK_FOR_STACK_OVERFLOW\n\t#define configCHECK_FOR_STACK_OVERFLOW 0\n#endif\n\n#ifndef configRECORD_STACK_HIGH_ADDRESS\n\t#define configRECORD_STACK_HIGH_ADDRESS 0\n#endif\n\n#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H\n\t#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0\n#endif\n\n/* The following event macros are embedded in the kernel API calls. */\n\n#ifndef traceMOVED_TASK_TO_READY_STATE\n\t#define traceMOVED_TASK_TO_READY_STATE( pxTCB )\n#endif\n\n#ifndef tracePOST_MOVED_TASK_TO_READY_STATE\n\t#define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )\n#endif\n\n#ifndef traceQUEUE_CREATE\n\t#define traceQUEUE_CREATE( pxNewQueue )\n#endif\n\n#ifndef traceQUEUE_CREATE_FAILED\n\t#define traceQUEUE_CREATE_FAILED( ucQueueType )\n#endif\n\n#ifndef traceCREATE_MUTEX\n\t#define traceCREATE_MUTEX( pxNewQueue )\n#endif\n\n#ifndef traceCREATE_MUTEX_FAILED\n\t#define traceCREATE_MUTEX_FAILED()\n#endif\n\n#ifndef traceGIVE_MUTEX_RECURSIVE\n\t#define traceGIVE_MUTEX_RECURSIVE( pxMutex )\n#endif\n\n#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED\n\t#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )\n#endif\n\n#ifndef traceTAKE_MUTEX_RECURSIVE\n\t#define traceTAKE_MUTEX_RECURSIVE( pxMutex )\n#endif\n\n#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED\n\t#define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )\n#endif\n\n#ifndef traceCREATE_COUNTING_SEMAPHORE\n\t#define traceCREATE_COUNTING_SEMAPHORE()\n#endif\n\n#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED\n\t#define traceCREATE_COUNTING_SEMAPHORE_FAILED()\n#endif\n\n#ifndef traceQUEUE_SEND\n\t#define traceQUEUE_SEND( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FAILED\n\t#define traceQUEUE_SEND_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE\n\t#define traceQUEUE_RECEIVE( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK\n\t#define traceQUEUE_PEEK( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FAILED\n\t#define traceQUEUE_PEEK_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FROM_ISR\n\t#define traceQUEUE_PEEK_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FAILED\n\t#define traceQUEUE_RECEIVE_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FROM_ISR\n\t#define traceQUEUE_SEND_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FROM_ISR_FAILED\n\t#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FROM_ISR\n\t#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED\n\t#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED\n\t#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_DELETE\n\t#define traceQUEUE_DELETE( pxQueue )\n#endif\n\n#ifndef traceTASK_CREATE\n\t#define traceTASK_CREATE( pxNewTCB )\n#endif\n\n#ifndef traceTASK_CREATE_FAILED\n\t#define traceTASK_CREATE_FAILED()\n#endif\n\n#ifndef traceTASK_DELETE\n\t#define traceTASK_DELETE( pxTaskToDelete )\n#endif\n\n#ifndef traceTASK_DELAY_UNTIL\n\t#define traceTASK_DELAY_UNTIL( x )\n#endif\n\n#ifndef traceTASK_DELAY\n\t#define traceTASK_DELAY()\n#endif\n\n#ifndef traceTASK_PRIORITY_SET\n\t#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )\n#endif\n\n#ifndef traceTASK_SUSPEND\n\t#define traceTASK_SUSPEND( pxTaskToSuspend )\n#endif\n\n#ifndef traceTASK_RESUME\n\t#define traceTASK_RESUME( pxTaskToResume )\n#endif\n\n#ifndef traceTASK_RESUME_FROM_ISR\n\t#define traceTASK_RESUME_FROM_ISR( pxTaskToResume )\n#endif\n\n#ifndef traceTASK_INCREMENT_TICK\n\t#define traceTASK_INCREMENT_TICK( xTickCount )\n#endif\n\n#ifndef traceTIMER_CREATE\n\t#define traceTIMER_CREATE( pxNewTimer )\n#endif\n\n#ifndef traceTIMER_CREATE_FAILED\n\t#define traceTIMER_CREATE_FAILED()\n#endif\n\n#ifndef traceTIMER_COMMAND_SEND\n\t#define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )\n#endif\n\n#ifndef traceTIMER_EXPIRED\n\t#define traceTIMER_EXPIRED( pxTimer )\n#endif\n\n#ifndef traceTIMER_COMMAND_RECEIVED\n\t#define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )\n#endif\n\n#ifndef traceMALLOC\n    #define traceMALLOC( pvAddress, uiSize )\n#endif\n\n#ifndef traceFREE\n    #define traceFREE( pvAddress, uiSize )\n#endif\n\n#ifndef traceEVENT_GROUP_CREATE\n\t#define traceEVENT_GROUP_CREATE( xEventGroup )\n#endif\n\n#ifndef traceEVENT_GROUP_CREATE_FAILED\n\t#define traceEVENT_GROUP_CREATE_FAILED()\n#endif\n\n#ifndef traceEVENT_GROUP_SYNC_BLOCK\n\t#define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )\n#endif\n\n#ifndef traceEVENT_GROUP_SYNC_END\n\t#define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred\n#endif\n\n#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK\n\t#define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )\n#endif\n\n#ifndef traceEVENT_GROUP_WAIT_BITS_END\n\t#define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred\n#endif\n\n#ifndef traceEVENT_GROUP_CLEAR_BITS\n\t#define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )\n#endif\n\n#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR\n\t#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )\n#endif\n\n#ifndef traceEVENT_GROUP_SET_BITS\n\t#define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )\n#endif\n\n#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR\n\t#define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )\n#endif\n\n#ifndef traceEVENT_GROUP_DELETE\n\t#define traceEVENT_GROUP_DELETE( xEventGroup )\n#endif\n\n#ifndef tracePEND_FUNC_CALL\n\t#define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)\n#endif\n\n#ifndef tracePEND_FUNC_CALL_FROM_ISR\n\t#define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)\n#endif\n\n#ifndef traceQUEUE_REGISTRY_ADD\n\t#define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)\n#endif\n\n#ifndef traceTASK_NOTIFY_TAKE_BLOCK\n\t#define traceTASK_NOTIFY_TAKE_BLOCK()\n#endif\n\n#ifndef traceTASK_NOTIFY_TAKE\n\t#define traceTASK_NOTIFY_TAKE()\n#endif\n\n#ifndef traceTASK_NOTIFY_WAIT_BLOCK\n\t#define traceTASK_NOTIFY_WAIT_BLOCK()\n#endif\n\n#ifndef traceTASK_NOTIFY_WAIT\n\t#define traceTASK_NOTIFY_WAIT()\n#endif\n\n#ifndef traceTASK_NOTIFY\n\t#define traceTASK_NOTIFY()\n#endif\n\n#ifndef traceTASK_NOTIFY_FROM_ISR\n\t#define traceTASK_NOTIFY_FROM_ISR()\n#endif\n\n#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR\n\t#define traceTASK_NOTIFY_GIVE_FROM_ISR()\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE_FAILED\n\t#define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED\n\t#define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE\n\t#define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_DELETE\n\t#define traceSTREAM_BUFFER_DELETE( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RESET\n\t#define traceSTREAM_BUFFER_RESET( xStreamBuffer )\n#endif\n\n#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND\n\t#define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND\n\t#define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND_FAILED\n\t#define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR\n\t#define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )\n#endif\n\n#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE\n\t#define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE\n\t#define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED\n\t#define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR\n\t#define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )\n#endif\n\n#ifndef configGENERATE_RUN_TIME_STATS\n\t#define configGENERATE_RUN_TIME_STATS 0\n#endif\n\n#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\n\t#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\n\t\t#error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.\n\t#endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */\n\n\t#ifndef portGET_RUN_TIME_COUNTER_VALUE\n\t\t#ifndef portALT_GET_RUN_TIME_COUNTER_VALUE\n\t\t\t#error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.\n\t\t#endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */\n\t#endif /* portGET_RUN_TIME_COUNTER_VALUE */\n\n#endif /* configGENERATE_RUN_TIME_STATS */\n\n#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\n\t#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\n#endif\n\n#ifndef configUSE_MALLOC_FAILED_HOOK\n\t#define configUSE_MALLOC_FAILED_HOOK 0\n#endif\n\n#ifndef portPRIVILEGE_BIT\n\t#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )\n#endif\n\n#ifndef portYIELD_WITHIN_API\n\t#define portYIELD_WITHIN_API portYIELD\n#endif\n\n#ifndef portSUPPRESS_TICKS_AND_SLEEP\n\t#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )\n#endif\n\n#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP\n\t#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2\n#endif\n\n#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2\n\t#error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2\n#endif\n\n#ifndef configUSE_TICKLESS_IDLE\n\t#define configUSE_TICKLESS_IDLE 0\n#endif\n\n#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING\n\t#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configPRE_SLEEP_PROCESSING\n\t#define configPRE_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configPOST_SLEEP_PROCESSING\n\t#define configPOST_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configUSE_QUEUE_SETS\n\t#define configUSE_QUEUE_SETS 0\n#endif\n\n#ifndef portTASK_USES_FLOATING_POINT\n\t#define portTASK_USES_FLOATING_POINT()\n#endif\n\n#ifndef portALLOCATE_SECURE_CONTEXT\n\t#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\n#endif\n\n#ifndef portDONT_DISCARD\n\t#define portDONT_DISCARD\n#endif\n\n#ifndef configUSE_TIME_SLICING\n\t#define configUSE_TIME_SLICING 1\n#endif\n\n#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS\n\t#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0\n#endif\n\n#ifndef configUSE_STATS_FORMATTING_FUNCTIONS\n\t#define configUSE_STATS_FORMATTING_FUNCTIONS 0\n#endif\n\n#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()\n#endif\n\n#ifndef configUSE_TRACE_FACILITY\n\t#define configUSE_TRACE_FACILITY 0\n#endif\n\n#ifndef mtCOVERAGE_TEST_MARKER\n\t#define mtCOVERAGE_TEST_MARKER()\n#endif\n\n#ifndef mtCOVERAGE_TEST_DELAY\n\t#define mtCOVERAGE_TEST_DELAY()\n#endif\n\n#ifndef portASSERT_IF_IN_ISR\n\t#define portASSERT_IF_IN_ISR()\n#endif\n\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\n#endif\n\n#ifndef configAPPLICATION_ALLOCATED_HEAP\n\t#define configAPPLICATION_ALLOCATED_HEAP 0\n#endif\n\n#ifndef configUSE_TASK_NOTIFICATIONS\n\t#define configUSE_TASK_NOTIFICATIONS 1\n#endif\n\n#ifndef configUSE_POSIX_ERRNO\n\t#define configUSE_POSIX_ERRNO 0\n#endif\n\n#ifndef portTICK_TYPE_IS_ATOMIC\n\t#define portTICK_TYPE_IS_ATOMIC 0\n#endif\n\n#ifndef configSUPPORT_STATIC_ALLOCATION\n\t/* Defaults to 0 for backward compatibility. */\n\t#define configSUPPORT_STATIC_ALLOCATION 0\n#endif\n\n#ifndef configSUPPORT_DYNAMIC_ALLOCATION\n\t/* Defaults to 1 for backward compatibility. */\n\t#define configSUPPORT_DYNAMIC_ALLOCATION 1\n#endif\n\n#ifndef configSTACK_DEPTH_TYPE\n\t/* Defaults to uint16_t for backward compatibility, but can be overridden\n\tin FreeRTOSConfig.h if uint16_t is too restrictive. */\n\t#define configSTACK_DEPTH_TYPE uint16_t\n#endif\n\n#ifndef configMESSAGE_BUFFER_LENGTH_TYPE\n\t/* Defaults to size_t for backward compatibility, but can be overridden\n\tin FreeRTOSConfig.h if lengths will always be less than the number of bytes\n\tin a size_t. */\n\t#define configMESSAGE_BUFFER_LENGTH_TYPE size_t\n#endif\n\n/* Sanity check the configuration. */\n#if( configUSE_TICKLESS_IDLE != 0 )\n\t#if( INCLUDE_vTaskSuspend != 1 )\n\t\t#error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0\n\t#endif /* INCLUDE_vTaskSuspend */\n#endif /* configUSE_TICKLESS_IDLE */\n\n#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )\n\t#error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.\n#endif\n\n#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )\n\t#error configUSE_MUTEXES must be set to 1 to use recursive mutexes\n#endif\n\n#ifndef configINITIAL_TICK_COUNT\n\t#define configINITIAL_TICK_COUNT 0\n#endif\n\n#if( portTICK_TYPE_IS_ATOMIC == 0 )\n\t/* Either variables of tick type cannot be read atomically, or\n\tportTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when\n\tthe tick count is returned to the standard critical section macros. */\n\t#define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL()\n\t#define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL()\n\t#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()\n\t#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )\n#else\n\t/* The tick type can be read atomically, so critical sections used when the\n\ttick count is returned can be defined away. */\n\t#define portTICK_TYPE_ENTER_CRITICAL()\n\t#define portTICK_TYPE_EXIT_CRITICAL()\n\t#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0\n\t#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x\n#endif\n\n/* Definitions to allow backward compatibility with FreeRTOS versions prior to\nV8 if desired. */\n#ifndef configENABLE_BACKWARD_COMPATIBILITY\n\t#define configENABLE_BACKWARD_COMPATIBILITY 1\n#endif\n\n#ifndef configPRINTF\n\t/* configPRINTF() was not defined, so define it away to nothing.  To use\n\tconfigPRINTF() then define it as follows (where MyPrintFunction() is\n\tprovided by the application writer):\n\n\tvoid MyPrintFunction(const char *pcFormat, ... );\n\t#define configPRINTF( X )   MyPrintFunction X\n\n\tThen call like a standard printf() function, but placing brackets around\n\tall parameters so they are passed as a single parameter.  For example:\n\tconfigPRINTF( (\"Value = %d\", MyVariable) ); */\n\t#define configPRINTF( X )\n#endif\n\n#ifndef configMAX\n\t/* The application writer has not provided their own MAX macro, so define\n\tthe following generic implementation. */\n\t#define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )\n#endif\n\n#ifndef configMIN\n\t/* The application writer has not provided their own MAX macro, so define\n\tthe following generic implementation. */\n\t#define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )\n#endif\n\n#if configENABLE_BACKWARD_COMPATIBILITY == 1\n\t#define eTaskStateGet eTaskGetState\n\t#define portTickType TickType_t\n\t#define xTaskHandle TaskHandle_t\n\t#define xQueueHandle QueueHandle_t\n\t#define xSemaphoreHandle SemaphoreHandle_t\n\t#define xQueueSetHandle QueueSetHandle_t\n\t#define xQueueSetMemberHandle QueueSetMemberHandle_t\n\t#define xTimeOutType TimeOut_t\n\t#define xMemoryRegion MemoryRegion_t\n\t#define xTaskParameters TaskParameters_t\n\t#define xTaskStatusType\tTaskStatus_t\n\t#define xTimerHandle TimerHandle_t\n\t#define xCoRoutineHandle CoRoutineHandle_t\n\t#define pdTASK_HOOK_CODE TaskHookFunction_t\n\t#define portTICK_RATE_MS portTICK_PERIOD_MS\n\t#define pcTaskGetTaskName pcTaskGetName\n\t#define pcTimerGetTimerName pcTimerGetName\n\t#define pcQueueGetQueueName pcQueueGetName\n\t#define vTaskGetTaskInfo vTaskGetInfo\n\n\t/* Backward compatibility within the scheduler code only - these definitions\n\tare not really required but are included for completeness. */\n\t#define tmrTIMER_CALLBACK TimerCallbackFunction_t\n\t#define pdTASK_CODE TaskFunction_t\n\t#define xListItem ListItem_t\n\t#define xList List_t\n\n\t/* For libraries that break the list data hiding, and access list structure\n\tmembers directly (which is not supposed to be done). */\n\t#define pxContainer pvContainer\n#endif /* configENABLE_BACKWARD_COMPATIBILITY */\n\n#if( configUSE_ALTERNATIVE_API != 0 )\n\t#error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0\n#endif\n\n/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even\nif floating point hardware is otherwise supported by the FreeRTOS port in use.\nThis constant is not supported by all FreeRTOS ports that include floating\npoint support. */\n#ifndef configUSE_TASK_FPU_SUPPORT\n\t#define configUSE_TASK_FPU_SUPPORT 1\n#endif\n\n/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is\ncurrently used in ARMv8M ports. */\n#ifndef configENABLE_MPU\n\t#define configENABLE_MPU 0\n#endif\n\n/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is\ncurrently used in ARMv8M ports. */\n#ifndef configENABLE_FPU\n\t#define configENABLE_FPU 1\n#endif\n\n/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.\nThis is currently used in ARMv8M ports. */\n#ifndef configENABLE_TRUSTZONE\n\t#define configENABLE_TRUSTZONE 1\n#endif\n\n/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on\nthe Secure Side only. */\n#ifndef configRUN_FREERTOS_SECURE_ONLY\n\t#define configRUN_FREERTOS_SECURE_ONLY 0\n#endif\n\n/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using\n * dynamically allocated RAM, in which case when any task is deleted it is known\n * that both the task's stack and TCB need to be freed.  Sometimes the\n * FreeRTOSConfig.h settings only allow a task to be created using statically\n * allocated RAM, in which case when any task is deleted it is known that neither\n * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h\n * settings allow a task to be created using either statically or dynamically\n * allocated RAM, in which case a member of the TCB is used to record whether the\n * stack and/or TCB were allocated statically or dynamically, so when a task is\n * deleted the RAM that was allocated dynamically is freed again and no attempt is\n * made to free the RAM that was allocated statically.\n * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a\n * task to be created using either statically or dynamically allocated RAM.  Note\n * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with\n * a statically allocated stack and a dynamically allocated TCB.\n *\n * The following table lists various combinations of portUSING_MPU_WRAPPERS,\n * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and\n * when it is possible to have both static and dynamic allocation:\n *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |\n * |     |         |        |                             |                                   | Static Possible  |           |\n * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |\n * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |\n * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |\n * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |\n * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n */\n#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE\t( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \\\n\t\t\t\t\t\t\t\t\t\t\t\t\t  ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )\n\n/*\n * In line with software engineering best practice, FreeRTOS implements a strict\n * data hiding policy, so the real structures used by FreeRTOS to maintain the\n * state of tasks, queues, semaphores, etc. are not accessible to the application\n * code.  However, if the application writer wants to statically allocate such\n * an object then the size of the object needs to be know.  Dummy structures\n * that are guaranteed to have the same size and alignment requirements of the\n * real objects are used for this purpose.  The dummy list and list item\n * structures below are used for inclusion in such a dummy structure.\n */\nstruct xSTATIC_LIST_ITEM\n{\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy1;\n\t#endif\n\tTickType_t xDummy2;\n\tvoid *pvDummy3[ 4 ];\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy4;\n\t#endif\n};\ntypedef struct xSTATIC_LIST_ITEM StaticListItem_t;\n\n/* See the comments above the struct xSTATIC_LIST_ITEM definition. */\nstruct xSTATIC_MINI_LIST_ITEM\n{\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy1;\n\t#endif\n\tTickType_t xDummy2;\n\tvoid *pvDummy3[ 2 ];\n};\ntypedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;\n\n/* See the comments above the struct xSTATIC_LIST_ITEM definition. */\ntypedef struct xSTATIC_LIST\n{\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy1;\n\t#endif\n\tUBaseType_t uxDummy2;\n\tvoid *pvDummy3;\n\tStaticMiniListItem_t xDummy4;\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy5;\n\t#endif\n} StaticList_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the Task structure used internally by\n * FreeRTOS is not accessible to application code.  However, if the application\n * writer wants to statically allocate the memory required to create a task then\n * the size of the task object needs to be know.  The StaticTask_t structure\n * below is provided for this purpose.  Its sizes and alignment requirements are\n * guaranteed to match those of the genuine structure, no matter which\n * architecture is being used, and no matter how the values in FreeRTOSConfig.h\n * are set.  Its contents are somewhat obfuscated in the hope users will\n * recognise that it would be unwise to make direct use of the structure members.\n */\ntypedef struct xSTATIC_TCB\n{\n\tvoid\t\t\t\t*pxDummy1;\n\t#if ( portUSING_MPU_WRAPPERS == 1 )\n\t\txMPU_SETTINGS\txDummy2;\n\t#endif\n\tStaticListItem_t\txDummy3[ 2 ];\n\tUBaseType_t\t\t\tuxDummy5;\n\tvoid\t\t\t\t*pxDummy6;\n\tuint8_t\t\t\t\tucDummy7[ configMAX_TASK_NAME_LEN ];\n\t#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )\n\t\tvoid\t\t\t*pxDummy8;\n\t#endif\n\t#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\t\tUBaseType_t\t\tuxDummy9;\n\t#endif\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t\t\tuxDummy10[ 2 ];\n\t#endif\n\t#if ( configUSE_MUTEXES == 1 )\n\t\tUBaseType_t\t\tuxDummy12[ 2 ];\n\t#endif\n\t#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\t\tvoid\t\t\t*pxDummy14;\n\t#endif\n\t#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n\t\tvoid\t\t\t*pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];\n\t#endif\n\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\t\tuint32_t\t\tulDummy16;\n\t#endif\n\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\tstruct\t_reent\txDummy17;\n\t#endif\n\t#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\tuint32_t \t\tulDummy18;\n\t\tuint8_t \t\tucDummy19;\n\t#endif\n\t#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n\t\tuint8_t\t\t\tuxDummy20;\n\t#endif\n\n\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t\tuint8_t ucDummy21;\n\t#endif\n\t#if ( configUSE_POSIX_ERRNO == 1 )\n\t\tint\t\t\t\tiDummy22;\n\t#endif\n} StaticTask_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the Queue structure used internally by\n * FreeRTOS is not accessible to application code.  However, if the application\n * writer wants to statically allocate the memory required to create a queue\n * then the size of the queue object needs to be know.  The StaticQueue_t\n * structure below is provided for this purpose.  Its sizes and alignment\n * requirements are guaranteed to match those of the genuine structure, no\n * matter which architecture is being used, and no matter how the values in\n * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope\n * users will recognise that it would be unwise to make direct use of the\n * structure members.\n */\ntypedef struct xSTATIC_QUEUE\n{\n\tvoid *pvDummy1[ 3 ];\n\n\tunion\n\t{\n\t\tvoid *pvDummy2;\n\t\tUBaseType_t uxDummy2;\n\t} u;\n\n\tStaticList_t xDummy3[ 2 ];\n\tUBaseType_t uxDummy4[ 3 ];\n\tuint8_t ucDummy5[ 2 ];\n\n\t#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\t\tuint8_t ucDummy6;\n\t#endif\n\n\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\tvoid *pvDummy7;\n\t#endif\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxDummy8;\n\t\tuint8_t ucDummy9;\n\t#endif\n\n} StaticQueue_t;\ntypedef StaticQueue_t StaticSemaphore_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the event group structure used\n * internally by FreeRTOS is not accessible to application code.  However, if\n * the application writer wants to statically allocate the memory required to\n * create an event group then the size of the event group object needs to be\n * know.  The StaticEventGroup_t structure below is provided for this purpose.\n * Its sizes and alignment requirements are guaranteed to match those of the\n * genuine structure, no matter which architecture is being used, and no matter\n * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat\n * obfuscated in the hope users will recognise that it would be unwise to make\n * direct use of the structure members.\n */\ntypedef struct xSTATIC_EVENT_GROUP\n{\n\tTickType_t xDummy1;\n\tStaticList_t xDummy2;\n\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxDummy3;\n\t#endif\n\n\t#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\t\t\tuint8_t ucDummy4;\n\t#endif\n\n} StaticEventGroup_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the software timer structure used\n * internally by FreeRTOS is not accessible to application code.  However, if\n * the application writer wants to statically allocate the memory required to\n * create a software timer then the size of the queue object needs to be know.\n * The StaticTimer_t structure below is provided for this purpose.  Its sizes\n * and alignment requirements are guaranteed to match those of the genuine\n * structure, no matter which architecture is being used, and no matter how the\n * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in\n * the hope users will recognise that it would be unwise to make direct use of\n * the structure members.\n */\ntypedef struct xSTATIC_TIMER\n{\n\tvoid\t\t\t\t*pvDummy1;\n\tStaticListItem_t\txDummy2;\n\tTickType_t\t\t\txDummy3;\n\tvoid \t\t\t\t*pvDummy5;\n\tTaskFunction_t\t\tpvDummy6;\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t\t\tuxDummy7;\n\t#endif\n\tuint8_t \t\t\tucDummy8;\n\n} StaticTimer_t;\n\n/*\n* In line with software engineering best practice, especially when supplying a\n* library that is likely to change in future versions, FreeRTOS implements a\n* strict data hiding policy.  This means the stream buffer structure used\n* internally by FreeRTOS is not accessible to application code.  However, if\n* the application writer wants to statically allocate the memory required to\n* create a stream buffer then the size of the stream buffer object needs to be\n* know.  The StaticStreamBuffer_t structure below is provided for this purpose.\n* Its size and alignment requirements are guaranteed to match those of the\n* genuine structure, no matter which architecture is being used, and no matter\n* how the values in FreeRTOSConfig.h are set.  Its contents are somewhat\n* obfuscated in the hope users will recognise that it would be unwise to make\n* direct use of the structure members.\n*/\ntypedef struct xSTATIC_STREAM_BUFFER\n{\n\tsize_t uxDummy1[ 4 ];\n\tvoid * pvDummy2[ 3 ];\n\tuint8_t ucDummy3;\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxDummy4;\n\t#endif\n} StaticStreamBuffer_t;\n\n/* Message buffers are built on stream buffers. */\ntypedef StaticStreamBuffer_t StaticMessageBuffer_t;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* INC_FREERTOS_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/FreeRTOSConfig_template.h",
    "content": "/*\n * FreeRTOS Kernel V10.0.1\n * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef FREERTOS_CONFIG_H\n#define FREERTOS_CONFIG_H\n\n/*-----------------------------------------------------------\n * this is a template configuration files\n *\n * These definitions should be adjusted for your particular hardware and\n * application requirements.\n *\n * These parameters and more are described within the 'configuration' section of the\n * FreeRTOS API documentation available on the FreeRTOS.org web site.\n *\n * See http://www.freertos.org/a00110.html\n *----------------------------------------------------------*/\n\n/* Ensure stdint is only used by the compiler, and not the assembler. */\n#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)\n #include <stdint.h>\n extern uint32_t SystemCoreClock;\n#endif\n\n/*  CMSIS-RTOSv2 defines 56 levels of priorities. To be able to use them\n *  all and avoid application misbehavior, configUSE_PORT_OPTIMISED_TASK_SELECTION\n *  must be set to 0 and configMAX_PRIORITIES to 56\n *\n */\n/* #define configUSE_PORT_OPTIMISED_TASK_SELECTION\t0*/\n/* #define configMAX_PRIORITIES\t\t\t\t\t( 56 ) */\n#define configUSE_PREEMPTION              1\n#define configUSE_IDLE_HOOK               0\n#define configUSE_TICK_HOOK               0\n#define configMAX_PRIORITIES              (7)\n#define configSUPPORT_STATIC_ALLOCATION   0\n#define configCPU_CLOCK_HZ                (SystemCoreClock)\n#define configTICK_RATE_HZ                ((TickType_t)1000)\n#define configMINIMAL_STACK_SIZE          ((uint16_t)128)\n#define configTOTAL_HEAP_SIZE             ((size_t)(15 * 1024))\n#define configMAX_TASK_NAME_LEN           (16)\n#define configUSE_TRACE_FACILITY          1\n#define configUSE_16_BIT_TICKS            0\n#define configIDLE_SHOULD_YIELD           1\n#define configUSE_MUTEXES                 1\n#define configQUEUE_REGISTRY_SIZE         8\n#define configCHECK_FOR_STACK_OVERFLOW    0\n#define configUSE_RECURSIVE_MUTEXES       1\n#define configUSE_MALLOC_FAILED_HOOK      0\n#define configUSE_APPLICATION_TASK_TAG    0\n#define configUSE_COUNTING_SEMAPHORES     1\n#define configGENERATE_RUN_TIME_STATS     0\n\n/* Co-routine definitions. */\n#define configUSE_CO_ROUTINES           0\n#define configMAX_CO_ROUTINE_PRIORITIES (2)\n\n/* Software timer definitions. */\n#define configUSE_TIMERS             0\n#define configTIMER_TASK_PRIORITY    (2)\n#define configTIMER_QUEUE_LENGTH     10\n#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2)\n\n/* Set the following definitions to 1 to include the API function, or zero\nto exclude the API function. */\n#define INCLUDE_vTaskPrioritySet       1\n#define INCLUDE_uxTaskPriorityGet      1\n#define INCLUDE_vTaskDelete            1\n#define INCLUDE_vTaskCleanUpResources  0\n#define INCLUDE_vTaskSuspend           1\n#define INCLUDE_vTaskDelayUntil        0\n#define INCLUDE_vTaskDelay             1\n#define INCLUDE_xTaskGetSchedulerState 1\n\n/*------------- CMSIS-RTOS V2 specific defines -----------*/\n/* When using CMSIS-RTOSv2 set configSUPPORT_STATIC_ALLOCATION to 1\n * is mandatory to avoid compile errors.\n * CMSIS-RTOS V2 implmentation requires the following defines\n *\n#define configSUPPORT_STATIC_ALLOCATION          1   <-- cmsis_os threads are created using xTaskCreateStatic() API\n#define configMAX_PRIORITIES                    (56) <-- Priority range in CMSIS-RTOS V2 is [0 .. 56]\n#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0    <-- when set to 1, configMAX_PRIORITIES can't be more than 32 which is not suitable for the new CMSIS-RTOS v2 priority range\n*/\n\n/* the CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used\n * by the application thus the correct define need to be enabled from the list\n * below\n *\n//define USE_FreeRTOS_HEAP_1\n//define USE_FreeRTOS_HEAP_2\n//define USE_FreeRTOS_HEAP_3\n//define USE_FreeRTOS_HEAP_4\n//define USE_FreeRTOS_HEAP_5\n\n*/\n\n\n/* Cortex-M specific definitions. */\n#ifdef __NVIC_PRIO_BITS\n /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\n #define configPRIO_BITS         __NVIC_PRIO_BITS\n#else\n #define configPRIO_BITS         4        /* 15 priority levels */\n#endif\n\n/* The lowest interrupt priority that can be used in a call to a \"set priority\"\nfunction. */\n#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   0xf\n\n/* The highest interrupt priority that can be used by any interrupt service\nroutine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL\nINTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\nPRIORITY THAN THIS! (higher priorities are lower numeric values. */\n#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\n\n/* Interrupt priorities used by the kernel port layer itself.  These are generic\nto all Cortex-M ports, and do not rely on any particular library functions. */\n#define configKERNEL_INTERRUPT_PRIORITY   ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\n/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\nSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\n#define configMAX_SYSCALL_INTERRUPT_PRIORITY  ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\n\n/* Normal assert() semantics without relying on the provision of an assert.h\nheader file. */\n#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\n\n/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\n   standard names. */\n#define vPortSVCHandler    SVC_Handler\n#define xPortPendSVHandler PendSV_Handler\n\n/* IMPORTANT: FreeRTOS is using the SysTick as internal time base, thus make sure the system and peripherials are\n              using a different time base (TIM based for example).\n */\n#define xPortSysTickHandler SysTick_Handler\n\n#endif /* FREERTOS_CONFIG_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/StackMacros.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef STACK_MACROS_H\n#define STACK_MACROS_H\n\n#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */\n\t#warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in future released.\n#endif\n\n/*\n * Call the stack overflow hook function if the stack of the task being swapped\n * out is currently overflowed, or looks like it might have overflowed in the\n * past.\n *\n * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check\n * the current stack state only - comparing the current top of stack value to\n * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1\n * will also cause the last few stack bytes to be checked to ensure the value\n * to which the bytes were set when the task was created have not been\n * overwritten.  Note this second test does not guarantee that an overflowed\n * stack will always be recognised.\n */\n\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n\t/* Only the current stack state is to be checked. */\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\n\t\tif( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n\t/* Only the current stack state is to be checked. */\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\n\t\tif( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tconst uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;\t\t\t\t\t\t\t\\\n\t\tconst uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( pulStack[ 0 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 1 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 2 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 3 ] != ulCheckValue ) )\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tint8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tstatic const uint8_t ucExpectedStackBytes[] = {\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tpcEndOfStack -= sizeof( ucExpectedStackBytes );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Has the extremity of the task stack ever been written over? */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n/* Remove stack overflow macro if not being used. */\n#ifndef taskCHECK_FOR_STACK_OVERFLOW\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\n#endif\n\n\n\n#endif /* STACK_MACROS_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/croutine.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef CO_ROUTINE_H\n#define CO_ROUTINE_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include croutine.h\"\n#endif\n\n#include \"list.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Used to hide the implementation of the co-routine control block.  The\ncontrol block structure however has to be included in the header due to\nthe macro implementation of the co-routine functionality. */\ntypedef void * CoRoutineHandle_t;\n\n/* Defines the prototype to which co-routine functions must conform. */\ntypedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );\n\ntypedef struct corCoRoutineControlBlock\n{\n\tcrCOROUTINE_CODE \tpxCoRoutineFunction;\n\tListItem_t\t\t\txGenericListItem;\t/*< List item used to place the CRCB in ready and blocked queues. */\n\tListItem_t\t\t\txEventListItem;\t\t/*< List item used to place the CRCB in event lists. */\n\tUBaseType_t \t\tuxPriority;\t\t\t/*< The priority of the co-routine in relation to other co-routines. */\n\tUBaseType_t \t\tuxIndex;\t\t\t/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */\n\tuint16_t \t\t\tuxState;\t\t\t/*< Used internally by the co-routine implementation. */\n} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */\n\n/**\n * croutine. h\n *<pre>\n BaseType_t xCoRoutineCreate(\n                                 crCOROUTINE_CODE pxCoRoutineCode,\n                                 UBaseType_t uxPriority,\n                                 UBaseType_t uxIndex\n                               );</pre>\n *\n * Create a new co-routine and add it to the list of co-routines that are\n * ready to run.\n *\n * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine\n * functions require special syntax - see the co-routine section of the WEB\n * documentation for more information.\n *\n * @param uxPriority The priority with respect to other co-routines at which\n *  the co-routine will run.\n *\n * @param uxIndex Used to distinguish between different co-routines that\n * execute the same function.  See the example below and the co-routine section\n * of the WEB documentation for further information.\n *\n * @return pdPASS if the co-routine was successfully created and added to a ready\n * list, otherwise an error code defined with ProjDefs.h.\n *\n * Example usage:\n   <pre>\n // Co-routine to be created.\n void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n // This may not be necessary for const variables.\n static const char cLedToFlash[ 2 ] = { 5, 6 };\n static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };\n\n     // Must start every co-routine with a call to crSTART();\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n         // This co-routine just delays for a fixed period, then toggles\n         // an LED.  Two co-routines are created using this function, so\n         // the uxIndex parameter is used to tell the co-routine which\n         // LED to flash and how int32_t to delay.  This assumes xQueue has\n         // already been created.\n         vParTestToggleLED( cLedToFlash[ uxIndex ] );\n         crDELAY( xHandle, uxFlashRates[ uxIndex ] );\n     }\n\n     // Must end every co-routine with a call to crEND();\n     crEND();\n }\n\n // Function that creates two co-routines.\n void vOtherFunction( void )\n {\n uint8_t ucParameterToPass;\n TaskHandle_t xHandle;\n\n     // Create two co-routines at priority 0.  The first is given index 0\n     // so (from the code above) toggles LED 5 every 200 ticks.  The second\n     // is given index 1 so toggles LED 6 every 400 ticks.\n     for( uxIndex = 0; uxIndex < 2; uxIndex++ )\n     {\n         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );\n     }\n }\n   </pre>\n * \\defgroup xCoRoutineCreate xCoRoutineCreate\n * \\ingroup Tasks\n */\nBaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );\n\n\n/**\n * croutine. h\n *<pre>\n void vCoRoutineSchedule( void );</pre>\n *\n * Run a co-routine.\n *\n * vCoRoutineSchedule() executes the highest priority co-routine that is able\n * to run.  The co-routine will execute until it either blocks, yields or is\n * preempted by a task.  Co-routines execute cooperatively so one\n * co-routine cannot be preempted by another, but can be preempted by a task.\n *\n * If an application comprises of both tasks and co-routines then\n * vCoRoutineSchedule should be called from the idle task (in an idle task\n * hook).\n *\n * Example usage:\n   <pre>\n // This idle task hook will schedule a co-routine each time it is called.\n // The rest of the idle task will execute between co-routine calls.\n void vApplicationIdleHook( void )\n {\n\tvCoRoutineSchedule();\n }\n\n // Alternatively, if you do not require any other part of the idle task to\n // execute, the idle task hook can call vCoRoutineScheduler() within an\n // infinite loop.\n void vApplicationIdleHook( void )\n {\n    for( ;; )\n    {\n        vCoRoutineSchedule();\n    }\n }\n </pre>\n * \\defgroup vCoRoutineSchedule vCoRoutineSchedule\n * \\ingroup Tasks\n */\nvoid vCoRoutineSchedule( void );\n\n/**\n * croutine. h\n * <pre>\n crSTART( CoRoutineHandle_t xHandle );</pre>\n *\n * This macro MUST always be called at the start of a co-routine function.\n *\n * Example usage:\n   <pre>\n // Co-routine to be created.\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n static int32_t ulAVariable;\n\n     // Must start every co-routine with a call to crSTART();\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n          // Co-routine functionality goes here.\n     }\n\n     // Must end every co-routine with a call to crEND();\n     crEND();\n }</pre>\n * \\defgroup crSTART crSTART\n * \\ingroup Tasks\n */\n#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:\n\n/**\n * croutine. h\n * <pre>\n crEND();</pre>\n *\n * This macro MUST always be called at the end of a co-routine function.\n *\n * Example usage:\n   <pre>\n // Co-routine to be created.\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n static int32_t ulAVariable;\n\n     // Must start every co-routine with a call to crSTART();\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n          // Co-routine functionality goes here.\n     }\n\n     // Must end every co-routine with a call to crEND();\n     crEND();\n }</pre>\n * \\defgroup crSTART crSTART\n * \\ingroup Tasks\n */\n#define crEND() }\n\n/*\n * These macros are intended for internal use by the co-routine implementation\n * only.  The macros should not be used directly by application writers.\n */\n#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):\n#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):\n\n/**\n * croutine. h\n *<pre>\n crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>\n *\n * Delay a co-routine for a fixed period of time.\n *\n * crDELAY can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * @param xHandle The handle of the co-routine to delay.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param xTickToDelay The number of ticks that the co-routine should delay\n * for.  The actual amount of time this equates to is defined by\n * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS\n * can be used to convert ticks to milliseconds.\n *\n * Example usage:\n   <pre>\n // Co-routine to be created.\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n // This may not be necessary for const variables.\n // We are to delay for 200ms.\n static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;\n\n     // Must start every co-routine with a call to crSTART();\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n        // Delay for 200ms.\n        crDELAY( xHandle, xDelayTime );\n\n        // Do something here.\n     }\n\n     // Must end every co-routine with a call to crEND();\n     crEND();\n }</pre>\n * \\defgroup crDELAY crDELAY\n * \\ingroup Tasks\n */\n#define crDELAY( xHandle, xTicksToDelay )\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( ( xTicksToDelay ) > 0 )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tvCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tcrSET_STATE0( ( xHandle ) );\n\n/**\n * <pre>\n crQUEUE_SEND(\n                  CoRoutineHandle_t xHandle,\n                  QueueHandle_t pxQueue,\n                  void *pvItemToQueue,\n                  TickType_t xTicksToWait,\n                  BaseType_t *pxResult\n             )</pre>\n *\n * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\n * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\n *\n * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\n * xQueueSend() and xQueueReceive() can only be used from tasks.\n *\n * crQUEUE_SEND can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xHandle The handle of the calling co-routine.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param pxQueue The handle of the queue on which the data will be posted.\n * The handle is obtained as the return value when the queue is created using\n * the xQueueCreate() API function.\n *\n * @param pvItemToQueue A pointer to the data being posted onto the queue.\n * The number of bytes of each queued item is specified when the queue is\n * created.  This number of bytes is copied from pvItemToQueue into the queue\n * itself.\n *\n * @param xTickToDelay The number of ticks that the co-routine should block\n * to wait for space to become available on the queue, should space not be\n * available immediately. The actual amount of time this equates to is defined\n * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant\n * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example\n * below).\n *\n * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\n * data was successfully posted onto the queue, otherwise it will be set to an\n * error defined within ProjDefs.h.\n *\n * Example usage:\n   <pre>\n // Co-routine function that blocks for a fixed period then posts a number onto\n // a queue.\n static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n static BaseType_t xNumberToPost = 0;\n static BaseType_t xResult;\n\n    // Co-routines must begin with a call to crSTART().\n    crSTART( xHandle );\n\n    for( ;; )\n    {\n        // This assumes the queue has already been created.\n        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );\n\n        if( xResult != pdPASS )\n        {\n            // The message was not posted!\n        }\n\n        // Increment the number to be posted onto the queue.\n        xNumberToPost++;\n\n        // Delay for 100 ticks.\n        crDELAY( xHandle, 100 );\n    }\n\n    // Co-routines must end with a call to crEND().\n    crEND();\n }</pre>\n * \\defgroup crQUEUE_SEND crQUEUE_SEND\n * \\ingroup Tasks\n */\n#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );\t\\\n\tif( *( pxResult ) == errQUEUE_BLOCKED )\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tcrSET_STATE0( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( *pxResult == errQUEUE_YIELD )\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tcrSET_STATE1( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t*pxResult = pdPASS;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/**\n * croutine. h\n * <pre>\n  crQUEUE_RECEIVE(\n                     CoRoutineHandle_t xHandle,\n                     QueueHandle_t pxQueue,\n                     void *pvBuffer,\n                     TickType_t xTicksToWait,\n                     BaseType_t *pxResult\n                 )</pre>\n *\n * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\n * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\n *\n * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\n * xQueueSend() and xQueueReceive() can only be used from tasks.\n *\n * crQUEUE_RECEIVE can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xHandle The handle of the calling co-routine.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param pxQueue The handle of the queue from which the data will be received.\n * The handle is obtained as the return value when the queue is created using\n * the xQueueCreate() API function.\n *\n * @param pvBuffer The buffer into which the received item is to be copied.\n * The number of bytes of each queued item is specified when the queue is\n * created.  This number of bytes is copied into pvBuffer.\n *\n * @param xTickToDelay The number of ticks that the co-routine should block\n * to wait for data to become available from the queue, should data not be\n * available immediately. The actual amount of time this equates to is defined\n * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant\n * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the\n * crQUEUE_SEND example).\n *\n * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\n * data was successfully retrieved from the queue, otherwise it will be set to\n * an error code as defined within ProjDefs.h.\n *\n * Example usage:\n <pre>\n // A co-routine receives the number of an LED to flash from a queue.  It\n // blocks on the queue until the number is received.\n static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n static BaseType_t xResult;\n static UBaseType_t uxLEDToFlash;\n\n    // All co-routines must start with a call to crSTART().\n    crSTART( xHandle );\n\n    for( ;; )\n    {\n        // Wait for data to become available on the queue.\n        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\n\n        if( xResult == pdPASS )\n        {\n            // We received the LED to flash - flash it!\n            vParTestToggleLED( uxLEDToFlash );\n        }\n    }\n\n    crEND();\n }</pre>\n * \\defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE\n * \\ingroup Tasks\n */\n#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );\t\t\\\n\tif( *( pxResult ) == errQUEUE_BLOCKED ) \t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tcrSET_STATE0( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( *( pxResult ) == errQUEUE_YIELD )\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tcrSET_STATE1( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t*( pxResult ) = pdPASS;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/**\n * croutine. h\n * <pre>\n  crQUEUE_SEND_FROM_ISR(\n                            QueueHandle_t pxQueue,\n                            void *pvItemToQueue,\n                            BaseType_t xCoRoutinePreviouslyWoken\n                       )</pre>\n *\n * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\n * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\n * functions used by tasks.\n *\n * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\n * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\n * xQueueReceiveFromISR() can only be used to pass data between a task and and\n * ISR.\n *\n * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue\n * that is being used from within a co-routine.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto\n * the same queue multiple times from a single interrupt.  The first call\n * should always pass in pdFALSE.  Subsequent calls should pass in\n * the value returned from the previous call.\n *\n * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is\n * used by the ISR to determine if a context switch may be required following\n * the ISR.\n *\n * Example usage:\n <pre>\n // A co-routine that blocks on a queue waiting for characters to be received.\n static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n char cRxedChar;\n BaseType_t xResult;\n\n     // All co-routines must start with a call to crSTART().\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n         // Wait for data to become available on the queue.  This assumes the\n         // queue xCommsRxQueue has already been created!\n         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\n\n         // Was a character received?\n         if( xResult == pdPASS )\n         {\n             // Process the character here.\n         }\n     }\n\n     // All co-routines must end with a call to crEND().\n     crEND();\n }\n\n // An ISR that uses a queue to send characters received on a serial port to\n // a co-routine.\n void vUART_ISR( void )\n {\n char cRxedChar;\n BaseType_t xCRWokenByPost = pdFALSE;\n\n     // We loop around reading characters until there are none left in the UART.\n     while( UART_RX_REG_NOT_EMPTY() )\n     {\n         // Obtain the character from the UART.\n         cRxedChar = UART_RX_REG;\n\n         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE\n         // the first time around the loop.  If the post causes a co-routine\n         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.\n         // In this manner we can ensure that if more than one co-routine is\n         // blocked on the queue only one is woken by this ISR no matter how\n         // many characters are posted to the queue.\n         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );\n     }\n }</pre>\n * \\defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR\n * \\ingroup Tasks\n */\n#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )\n\n\n/**\n * croutine. h\n * <pre>\n  crQUEUE_SEND_FROM_ISR(\n                            QueueHandle_t pxQueue,\n                            void *pvBuffer,\n                            BaseType_t * pxCoRoutineWoken\n                       )</pre>\n *\n * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\n * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\n * functions used by tasks.\n *\n * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\n * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\n * xQueueReceiveFromISR() can only be used to pass data between a task and and\n * ISR.\n *\n * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data\n * from a queue that is being used from within a co-routine (a co-routine\n * posted to the queue).\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvBuffer A pointer to a buffer into which the received item will be\n * placed.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from the queue into\n * pvBuffer.\n *\n * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become\n * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a\n * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise\n * *pxCoRoutineWoken will remain unchanged.\n *\n * @return pdTRUE an item was successfully received from the queue, otherwise\n * pdFALSE.\n *\n * Example usage:\n <pre>\n // A co-routine that posts a character to a queue then blocks for a fixed\n // period.  The character is incremented each time.\n static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // cChar holds its value while this co-routine is blocked and must therefore\n // be declared static.\n static char cCharToTx = 'a';\n BaseType_t xResult;\n\n     // All co-routines must start with a call to crSTART().\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n         // Send the next character to the queue.\n         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );\n\n         if( xResult == pdPASS )\n         {\n             // The character was successfully posted to the queue.\n         }\n\t\t else\n\t\t {\n\t\t\t// Could not post the character to the queue.\n\t\t }\n\n         // Enable the UART Tx interrupt to cause an interrupt in this\n\t\t // hypothetical UART.  The interrupt will obtain the character\n\t\t // from the queue and send it.\n\t\t ENABLE_RX_INTERRUPT();\n\n\t\t // Increment to the next character then block for a fixed period.\n\t\t // cCharToTx will maintain its value across the delay as it is\n\t\t // declared static.\n\t\t cCharToTx++;\n\t\t if( cCharToTx > 'x' )\n\t\t {\n\t\t\tcCharToTx = 'a';\n\t\t }\n\t\t crDELAY( 100 );\n     }\n\n     // All co-routines must end with a call to crEND().\n     crEND();\n }\n\n // An ISR that uses a queue to receive characters to send on a UART.\n void vUART_ISR( void )\n {\n char cCharToTx;\n BaseType_t xCRWokenByPost = pdFALSE;\n\n     while( UART_TX_REG_EMPTY() )\n     {\n         // Are there any characters in the queue waiting to be sent?\n\t\t // xCRWokenByPost will automatically be set to pdTRUE if a co-routine\n\t\t // is woken by the post - ensuring that only a single co-routine is\n\t\t // woken no matter how many times we go around this loop.\n         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )\n\t\t {\n\t\t\t SEND_CHARACTER( cCharToTx );\n\t\t }\n     }\n }</pre>\n * \\defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR\n * \\ingroup Tasks\n */\n#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )\n\n/*\n * This function is intended for internal use by the co-routine macros only.\n * The macro nature of the co-routine implementation requires that the\n * prototype appears here.  The function should not be used by application\n * writers.\n *\n * Removes the current co-routine from its ready list and places it in the\n * appropriate delayed list.\n */\nvoid vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );\n\n/*\n * This function is intended for internal use by the queue implementation only.\n * The function should not be used by application writers.\n *\n * Removes the highest priority co-routine from the event list and places it in\n * the pending ready list.\n */\nBaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* CO_ROUTINE_H */\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/deprecated_definitions.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef DEPRECATED_DEFINITIONS_H\n#define DEPRECATED_DEFINITIONS_H\n\n\n/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a\npre-processor definition was used to ensure the pre-processor found the correct\nportmacro.h file for the port being used.  That scheme was deprecated in favour\nof setting the compiler's include path such that it found the correct\nportmacro.h file - removing the need for the constant and allowing the\nportmacro.h file to be located anywhere in relation to the port being used.  The\ndefinitions below remain in the code for backward compatibility only.  New\nprojects should not use them. */\n\n#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT\n\t#include \"..\\..\\Source\\portable\\owatcom\\16bitdos\\pc\\portmacro.h\"\n\ttypedef void ( __interrupt __far *pxISR )();\n#endif\n\n#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT\n\t#include \"..\\..\\Source\\portable\\owatcom\\16bitdos\\flsh186\\portmacro.h\"\n\ttypedef void ( __interrupt __far *pxISR )();\n#endif\n\n#ifdef GCC_MEGA_AVR\n\t#include \"../portable/GCC/ATMega323/portmacro.h\"\n#endif\n\n#ifdef IAR_MEGA_AVR\n\t#include \"../portable/IAR/ATMega323/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC24_PORT\n\t#include \"../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h\"\n#endif\n\n#ifdef MPLAB_DSPIC_PORT\n\t#include \"../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC18F_PORT\n\t#include \"../../Source/portable/MPLAB/PIC18F/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC32MX_PORT\n\t#include \"../../Source/portable/MPLAB/PIC32MX/portmacro.h\"\n#endif\n\n#ifdef _FEDPICC\n\t#include \"libFreeRTOS/Include/portmacro.h\"\n#endif\n\n#ifdef SDCC_CYGNAL\n\t#include \"../../Source/portable/SDCC/Cygnal/portmacro.h\"\n#endif\n\n#ifdef GCC_ARM7\n\t#include \"../../Source/portable/GCC/ARM7_LPC2000/portmacro.h\"\n#endif\n\n#ifdef GCC_ARM7_ECLIPSE\n\t#include \"portmacro.h\"\n#endif\n\n#ifdef ROWLEY_LPC23xx\n\t#include \"../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h\"\n#endif\n\n#ifdef IAR_MSP430\n\t#include \"..\\..\\Source\\portable\\IAR\\MSP430\\portmacro.h\"\n#endif\n\n#ifdef GCC_MSP430\n\t#include \"../../Source/portable/GCC/MSP430F449/portmacro.h\"\n#endif\n\n#ifdef ROWLEY_MSP430\n\t#include \"../../Source/portable/Rowley/MSP430F449/portmacro.h\"\n#endif\n\n#ifdef ARM7_LPC21xx_KEIL_RVDS\n\t#include \"..\\..\\Source\\portable\\RVDS\\ARM7_LPC21xx\\portmacro.h\"\n#endif\n\n#ifdef SAM7_GCC\n\t#include \"../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h\"\n#endif\n\n#ifdef SAM7_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\AtmelSAM7S64\\portmacro.h\"\n#endif\n\n#ifdef SAM9XE_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\AtmelSAM9XE\\portmacro.h\"\n#endif\n\n#ifdef LPC2000_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\LPC2000\\portmacro.h\"\n#endif\n\n#ifdef STR71X_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\STR71x\\portmacro.h\"\n#endif\n\n#ifdef STR75X_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\STR75x\\portmacro.h\"\n#endif\n\n#ifdef STR75X_GCC\n\t#include \"..\\..\\Source\\portable\\GCC\\STR75x\\portmacro.h\"\n#endif\n\n#ifdef STR91X_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\STR91x\\portmacro.h\"\n#endif\n\n#ifdef GCC_H8S\n\t#include \"../../Source/portable/GCC/H8S2329/portmacro.h\"\n#endif\n\n#ifdef GCC_AT91FR40008\n\t#include \"../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h\"\n#endif\n\n#ifdef RVDS_ARMCM3_LM3S102\n\t#include \"../../Source/portable/RVDS/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef GCC_ARMCM3_LM3S102\n\t#include \"../../Source/portable/GCC/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef GCC_ARMCM3\n\t#include \"../../Source/portable/GCC/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef IAR_ARM_CM3\n\t#include \"../../Source/portable/IAR/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef IAR_ARMCM3_LM\n\t#include \"../../Source/portable/IAR/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef HCS12_CODE_WARRIOR\n\t#include \"../../Source/portable/CodeWarrior/HCS12/portmacro.h\"\n#endif\n\n#ifdef MICROBLAZE_GCC\n\t#include \"../../Source/portable/GCC/MicroBlaze/portmacro.h\"\n#endif\n\n#ifdef TERN_EE\n\t#include \"..\\..\\Source\\portable\\Paradigm\\Tern_EE\\small\\portmacro.h\"\n#endif\n\n#ifdef GCC_HCS12\n\t#include \"../../Source/portable/GCC/HCS12/portmacro.h\"\n#endif\n\n#ifdef GCC_MCF5235\n    #include \"../../Source/portable/GCC/MCF5235/portmacro.h\"\n#endif\n\n#ifdef COLDFIRE_V2_GCC\n\t#include \"../../../Source/portable/GCC/ColdFire_V2/portmacro.h\"\n#endif\n\n#ifdef COLDFIRE_V2_CODEWARRIOR\n\t#include \"../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h\"\n#endif\n\n#ifdef GCC_PPC405\n\t#include \"../../Source/portable/GCC/PPC405_Xilinx/portmacro.h\"\n#endif\n\n#ifdef GCC_PPC440\n\t#include \"../../Source/portable/GCC/PPC440_Xilinx/portmacro.h\"\n#endif\n\n#ifdef _16FX_SOFTUNE\n\t#include \"..\\..\\Source\\portable\\Softune\\MB96340\\portmacro.h\"\n#endif\n\n#ifdef BCC_INDUSTRIAL_PC_PORT\n\t/* A short file name has to be used in place of the normal\n\tFreeRTOSConfig.h when using the Borland compiler. */\n\t#include \"frconfig.h\"\n\t#include \"..\\portable\\BCC\\16BitDOS\\PC\\prtmacro.h\"\n    typedef void ( __interrupt __far *pxISR )();\n#endif\n\n#ifdef BCC_FLASH_LITE_186_PORT\n\t/* A short file name has to be used in place of the normal\n\tFreeRTOSConfig.h when using the Borland compiler. */\n\t#include \"frconfig.h\"\n\t#include \"..\\portable\\BCC\\16BitDOS\\flsh186\\prtmacro.h\"\n    typedef void ( __interrupt __far *pxISR )();\n#endif\n\n#ifdef __GNUC__\n   #ifdef __AVR32_AVR32A__\n\t   #include \"portmacro.h\"\n   #endif\n#endif\n\n#ifdef __ICCAVR32__\n   #ifdef __CORE__\n      #if __CORE__ == __AVR32A__\n\t      #include \"portmacro.h\"\n      #endif\n   #endif\n#endif\n\n#ifdef __91467D\n\t#include \"portmacro.h\"\n#endif\n\n#ifdef __96340\n\t#include \"portmacro.h\"\n#endif\n\n\n#ifdef __IAR_V850ES_Fx3__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx3__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx3_L__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx2__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Hx2__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_78K0R_Kx3__\n\t#include \"../../Source/portable/IAR/78K0R/portmacro.h\"\n#endif\n\n#ifdef __IAR_78K0R_Kx3L__\n\t#include \"../../Source/portable/IAR/78K0R/portmacro.h\"\n#endif\n\n#endif /* DEPRECATED_DEFINITIONS_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/event_groups.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef EVENT_GROUPS_H\n#define EVENT_GROUPS_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include event_groups.h\"\n#endif\n\n/* FreeRTOS includes. */\n#include \"timers.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * An event group is a collection of bits to which an application can assign a\n * meaning.  For example, an application may create an event group to convey\n * the status of various CAN bus related events in which bit 0 might mean \"A CAN\n * message has been received and is ready for processing\", bit 1 might mean \"The\n * application has queued a message that is ready for sending onto the CAN\n * network\", and bit 2 might mean \"It is time to send a SYNC message onto the\n * CAN network\" etc.  A task can then test the bit values to see which events\n * are active, and optionally enter the Blocked state to wait for a specified\n * bit or a group of specified bits to be active.  To continue the CAN bus\n * example, a CAN controlling task can enter the Blocked state (and therefore\n * not consume any processing time) until either bit 0, bit 1 or bit 2 are\n * active, at which time the bit that was actually active would inform the task\n * which action it had to take (process a received message, send a message, or\n * send a SYNC).\n *\n * The event groups implementation contains intelligence to avoid race\n * conditions that would otherwise occur were an application to use a simple\n * variable for the same purpose.  This is particularly important with respect\n * to when a bit within an event group is to be cleared, and when bits have to\n * be set and then tested atomically - as is the case where event groups are\n * used to create a synchronisation point between multiple tasks (a\n * 'rendezvous').\n *\n * \\defgroup EventGroup\n */\n\n\n\n/**\n * event_groups.h\n *\n * Type by which event groups are referenced.  For example, a call to\n * xEventGroupCreate() returns an EventGroupHandle_t variable that can then\n * be used as a parameter to other event group functions.\n *\n * \\defgroup EventGroupHandle_t EventGroupHandle_t\n * \\ingroup EventGroup\n */\nstruct EventGroupDef_t;\ntypedef struct EventGroupDef_t * EventGroupHandle_t;\n\n/*\n * The type that holds event bits always matches TickType_t - therefore the\n * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,\n * 32 bits if set to 0.\n *\n * \\defgroup EventBits_t EventBits_t\n * \\ingroup EventGroup\n */\ntypedef TickType_t EventBits_t;\n\n/**\n * event_groups.h\n *<pre>\n EventGroupHandle_t xEventGroupCreate( void );\n </pre>\n *\n * Create a new event group.\n *\n * Internally, within the FreeRTOS implementation, event groups use a [small]\n * block of memory, in which the event group's structure is stored.  If an event\n * groups is created using xEventGropuCreate() then the required memory is\n * automatically dynamically allocated inside the xEventGroupCreate() function.\n * (see http://www.freertos.org/a00111.html).  If an event group is created\n * using xEventGropuCreateStatic() then the application writer must instead\n * provide the memory that will get used by the event group.\n * xEventGroupCreateStatic() therefore allows an event group to be created\n * without using any dynamic memory allocation.\n *\n * Although event groups are not related to ticks, for internal implementation\n * reasons the number of bits available for use in an event group is dependent\n * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If\n * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit\n * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has\n * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store\n * event bits within an event group.\n *\n * @return If the event group was created then a handle to the event group is\n * returned.  If there was insufficient FreeRTOS heap available to create the\n * event group then NULL is returned.  See http://www.freertos.org/a00111.html\n *\n * Example usage:\n   <pre>\n\t// Declare a variable to hold the created event group.\n\tEventGroupHandle_t xCreatedEventGroup;\n\n\t// Attempt to create the event group.\n\txCreatedEventGroup = xEventGroupCreate();\n\n\t// Was the event group created successfully?\n\tif( xCreatedEventGroup == NULL )\n\t{\n\t\t// The event group was not created because there was insufficient\n\t\t// FreeRTOS heap available.\n\t}\n\telse\n\t{\n\t\t// The event group was created.\n\t}\n   </pre>\n * \\defgroup xEventGroupCreate xEventGroupCreate\n * \\ingroup EventGroup\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tEventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * event_groups.h\n *<pre>\n EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );\n </pre>\n *\n * Create a new event group.\n *\n * Internally, within the FreeRTOS implementation, event groups use a [small]\n * block of memory, in which the event group's structure is stored.  If an event\n * groups is created using xEventGropuCreate() then the required memory is\n * automatically dynamically allocated inside the xEventGroupCreate() function.\n * (see http://www.freertos.org/a00111.html).  If an event group is created\n * using xEventGropuCreateStatic() then the application writer must instead\n * provide the memory that will get used by the event group.\n * xEventGroupCreateStatic() therefore allows an event group to be created\n * without using any dynamic memory allocation.\n *\n * Although event groups are not related to ticks, for internal implementation\n * reasons the number of bits available for use in an event group is dependent\n * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If\n * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit\n * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has\n * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store\n * event bits within an event group.\n *\n * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type\n * StaticEventGroup_t, which will be then be used to hold the event group's data\n * structures, removing the need for the memory to be allocated dynamically.\n *\n * @return If the event group was created then a handle to the event group is\n * returned.  If pxEventGroupBuffer was NULL then NULL is returned.\n *\n * Example usage:\n   <pre>\n\t// StaticEventGroup_t is a publicly accessible structure that has the same\n\t// size and alignment requirements as the real event group structure.  It is\n\t// provided as a mechanism for applications to know the size of the event\n\t// group (which is dependent on the architecture and configuration file\n\t// settings) without breaking the strict data hiding policy by exposing the\n\t// real event group internals.  This StaticEventGroup_t variable is passed\n\t// into the xSemaphoreCreateEventGroupStatic() function and is used to store\n\t// the event group's data structures\n\tStaticEventGroup_t xEventGroupBuffer;\n\n\t// Create the event group without dynamically allocating any memory.\n\txEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );\n   </pre>\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tEventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupWaitBits( \tEventGroupHandle_t xEventGroup,\n\t\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToWaitFor,\n\t\t\t\t\t\t\t\t\t\tconst BaseType_t xClearOnExit,\n\t\t\t\t\t\t\t\t\t\tconst BaseType_t xWaitForAllBits,\n\t\t\t\t\t\t\t\t\t\tconst TickType_t xTicksToWait );\n </pre>\n *\n * [Potentially] block to wait for one or more bits to be set within a\n * previously created event group.\n *\n * This function cannot be called from an interrupt.\n *\n * @param xEventGroup The event group in which the bits are being tested.  The\n * event group must have previously been created using a call to\n * xEventGroupCreate().\n *\n * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test\n * inside the event group.  For example, to wait for bit 0 and/or bit 2 set\n * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set\n * uxBitsToWaitFor to 0x07.  Etc.\n *\n * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within\n * uxBitsToWaitFor that are set within the event group will be cleared before\n * xEventGroupWaitBits() returns if the wait condition was met (if the function\n * returns for a reason other than a timeout).  If xClearOnExit is set to\n * pdFALSE then the bits set in the event group are not altered when the call to\n * xEventGroupWaitBits() returns.\n *\n * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then\n * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor\n * are set or the specified block time expires.  If xWaitForAllBits is set to\n * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set\n * in uxBitsToWaitFor is set or the specified block time expires.  The block\n * time is specified by the xTicksToWait parameter.\n *\n * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait\n * for one/all (depending on the xWaitForAllBits value) of the bits specified by\n * uxBitsToWaitFor to become set.\n *\n * @return The value of the event group at the time either the bits being waited\n * for became set, or the block time expired.  Test the return value to know\n * which bits were set.  If xEventGroupWaitBits() returned because its timeout\n * expired then not all the bits being waited for will be set.  If\n * xEventGroupWaitBits() returned because the bits it was waiting for were set\n * then the returned value is the event group value before any bits were\n * automatically cleared in the case that xClearOnExit parameter was set to\n * pdTRUE.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   void aFunction( EventGroupHandle_t xEventGroup )\n   {\n   EventBits_t uxBits;\n   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;\n\n\t\t// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within\n\t\t// the event group.  Clear the bits before exiting.\n\t\tuxBits = xEventGroupWaitBits(\n\t\t\t\t\txEventGroup,\t// The event group being tested.\n\t\t\t\t\tBIT_0 | BIT_4,\t// The bits within the event group to wait for.\n\t\t\t\t\tpdTRUE,\t\t\t// BIT_0 and BIT_4 should be cleared before returning.\n\t\t\t\t\tpdFALSE,\t\t// Don't wait for both bits, either bit will do.\n\t\t\t\t\txTicksToWait );\t// Wait a maximum of 100ms for either bit to be set.\n\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n\t\t{\n\t\t\t// xEventGroupWaitBits() returned because both bits were set.\n\t\t}\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\n\t\t{\n\t\t\t// xEventGroupWaitBits() returned because just BIT_0 was set.\n\t\t}\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\n\t\t{\n\t\t\t// xEventGroupWaitBits() returned because just BIT_4 was set.\n\t\t}\n\t\telse\n\t\t{\n\t\t\t// xEventGroupWaitBits() returned because xTicksToWait ticks passed\n\t\t\t// without either BIT_0 or BIT_4 becoming set.\n\t\t}\n   }\n   </pre>\n * \\defgroup xEventGroupWaitBits xEventGroupWaitBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );\n </pre>\n *\n * Clear bits within an event group.  This function cannot be called from an\n * interrupt.\n *\n * @param xEventGroup The event group in which the bits are to be cleared.\n *\n * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear\n * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to\n * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.\n *\n * @return The value of the event group before the specified bits were cleared.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   void aFunction( EventGroupHandle_t xEventGroup )\n   {\n   EventBits_t uxBits;\n\n\t\t// Clear bit 0 and bit 4 in xEventGroup.\n\t\tuxBits = xEventGroupClearBits(\n\t\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\n\t\t\t\t\t\t\t\tBIT_0 | BIT_4 );// The bits being cleared.\n\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n\t\t{\n\t\t\t// Both bit 0 and bit 4 were set before xEventGroupClearBits() was\n\t\t\t// called.  Both will now be clear (not set).\n\t\t}\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\n\t\t{\n\t\t\t// Bit 0 was set before xEventGroupClearBits() was called.  It will\n\t\t\t// now be clear.\n\t\t}\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\n\t\t{\n\t\t\t// Bit 4 was set before xEventGroupClearBits() was called.  It will\n\t\t\t// now be clear.\n\t\t}\n\t\telse\n\t\t{\n\t\t\t// Neither bit 0 nor bit 4 were set in the first place.\n\t\t}\n   }\n   </pre>\n * \\defgroup xEventGroupClearBits xEventGroupClearBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n *<pre>\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\n </pre>\n *\n * A version of xEventGroupClearBits() that can be called from an interrupt.\n *\n * Setting bits in an event group is not a deterministic operation because there\n * are an unknown number of tasks that may be waiting for the bit or bits being\n * set.  FreeRTOS does not allow nondeterministic operations to be performed\n * while interrupts are disabled, so protects event groups that are accessed\n * from tasks by suspending the scheduler rather than disabling interrupts.  As\n * a result event groups cannot be accessed directly from an interrupt service\n * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the\n * timer task to have the clear operation performed in the context of the timer\n * task.\n *\n * @param xEventGroup The event group in which the bits are to be cleared.\n *\n * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.\n * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3\n * and bit 0 set uxBitsToClear to 0x09.\n *\n * @return If the request to execute the function was posted successfully then\n * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned\n * if the timer service queue was full.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   // An event group which it is assumed has already been created by a call to\n   // xEventGroupCreate().\n   EventGroupHandle_t xEventGroup;\n\n   void anInterruptHandler( void )\n   {\n\t\t// Clear bit 0 and bit 4 in xEventGroup.\n\t\txResult = xEventGroupClearBitsFromISR(\n\t\t\t\t\t\t\txEventGroup,\t // The event group being updated.\n\t\t\t\t\t\t\tBIT_0 | BIT_4 ); // The bits being set.\n\n\t\tif( xResult == pdPASS )\n\t\t{\n\t\t\t// The message was posted successfully.\n\t\t}\n  }\n   </pre>\n * \\defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR\n * \\ingroup EventGroup\n */\n#if( configUSE_TRACE_FACILITY == 1 )\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;\n#else\n\t#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )\n#endif\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\n </pre>\n *\n * Set bits within an event group.\n * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()\n * is a version that can be called from an interrupt.\n *\n * Setting bits in an event group will automatically unblock tasks that are\n * blocked waiting for the bits.\n *\n * @param xEventGroup The event group in which the bits are to be set.\n *\n * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.\n * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3\n * and bit 0 set uxBitsToSet to 0x09.\n *\n * @return The value of the event group at the time the call to\n * xEventGroupSetBits() returns.  There are two reasons why the returned value\n * might have the bits specified by the uxBitsToSet parameter cleared.  First,\n * if setting a bit results in a task that was waiting for the bit leaving the\n * blocked state then it is possible the bit will be cleared automatically\n * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any\n * unblocked (or otherwise Ready state) task that has a priority above that of\n * the task that called xEventGroupSetBits() will execute and may change the\n * event group value before the call to xEventGroupSetBits() returns.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   void aFunction( EventGroupHandle_t xEventGroup )\n   {\n   EventBits_t uxBits;\n\n\t\t// Set bit 0 and bit 4 in xEventGroup.\n\t\tuxBits = xEventGroupSetBits(\n\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\n\t\t\t\t\t\t\tBIT_0 | BIT_4 );// The bits being set.\n\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n\t\t{\n\t\t\t// Both bit 0 and bit 4 remained set when the function returned.\n\t\t}\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\n\t\t{\n\t\t\t// Bit 0 remained set when the function returned, but bit 4 was\n\t\t\t// cleared.  It might be that bit 4 was cleared automatically as a\n\t\t\t// task that was waiting for bit 4 was removed from the Blocked\n\t\t\t// state.\n\t\t}\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\n\t\t{\n\t\t\t// Bit 4 remained set when the function returned, but bit 0 was\n\t\t\t// cleared.  It might be that bit 0 was cleared automatically as a\n\t\t\t// task that was waiting for bit 0 was removed from the Blocked\n\t\t\t// state.\n\t\t}\n\t\telse\n\t\t{\n\t\t\t// Neither bit 0 nor bit 4 remained set.  It might be that a task\n\t\t\t// was waiting for both of the bits to be set, and the bits were\n\t\t\t// cleared as the task left the Blocked state.\n\t\t}\n   }\n   </pre>\n * \\defgroup xEventGroupSetBits xEventGroupSetBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n *<pre>\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );\n </pre>\n *\n * A version of xEventGroupSetBits() that can be called from an interrupt.\n *\n * Setting bits in an event group is not a deterministic operation because there\n * are an unknown number of tasks that may be waiting for the bit or bits being\n * set.  FreeRTOS does not allow nondeterministic operations to be performed in\n * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()\n * sends a message to the timer task to have the set operation performed in the\n * context of the timer task - where a scheduler lock is used in place of a\n * critical section.\n *\n * @param xEventGroup The event group in which the bits are to be set.\n *\n * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.\n * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3\n * and bit 0 set uxBitsToSet to 0x09.\n *\n * @param pxHigherPriorityTaskWoken As mentioned above, calling this function\n * will result in a message being sent to the timer daemon task.  If the\n * priority of the timer daemon task is higher than the priority of the\n * currently running task (the task the interrupt interrupted) then\n * *pxHigherPriorityTaskWoken will be set to pdTRUE by\n * xEventGroupSetBitsFromISR(), indicating that a context switch should be\n * requested before the interrupt exits.  For that reason\n * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the\n * example code below.\n *\n * @return If the request to execute the function was posted successfully then\n * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned\n * if the timer service queue was full.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   // An event group which it is assumed has already been created by a call to\n   // xEventGroupCreate().\n   EventGroupHandle_t xEventGroup;\n\n   void anInterruptHandler( void )\n   {\n   BaseType_t xHigherPriorityTaskWoken, xResult;\n\n\t\t// xHigherPriorityTaskWoken must be initialised to pdFALSE.\n\t\txHigherPriorityTaskWoken = pdFALSE;\n\n\t\t// Set bit 0 and bit 4 in xEventGroup.\n\t\txResult = xEventGroupSetBitsFromISR(\n\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\n\t\t\t\t\t\t\tBIT_0 | BIT_4   // The bits being set.\n\t\t\t\t\t\t\t&xHigherPriorityTaskWoken );\n\n\t\t// Was the message posted successfully?\n\t\tif( xResult == pdPASS )\n\t\t{\n\t\t\t// If xHigherPriorityTaskWoken is now set to pdTRUE then a context\n\t\t\t// switch should be requested.  The macro used is port specific and\n\t\t\t// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -\n\t\t\t// refer to the documentation page for the port being used.\n\t\t\tportYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n\t\t}\n  }\n   </pre>\n * \\defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR\n * \\ingroup EventGroup\n */\n#if( configUSE_TRACE_FACILITY == 1 )\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n#else\n\t#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )\n#endif\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupSync(\tEventGroupHandle_t xEventGroup,\n\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToSet,\n\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToWaitFor,\n\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait );\n </pre>\n *\n * Atomically set bits within an event group, then wait for a combination of\n * bits to be set within the same event group.  This functionality is typically\n * used to synchronise multiple tasks, where each task has to wait for the other\n * tasks to reach a synchronisation point before proceeding.\n *\n * This function cannot be used from an interrupt.\n *\n * The function will return before its block time expires if the bits specified\n * by the uxBitsToWait parameter are set, or become set within that time.  In\n * this case all the bits specified by uxBitsToWait will be automatically\n * cleared before the function returns.\n *\n * @param xEventGroup The event group in which the bits are being tested.  The\n * event group must have previously been created using a call to\n * xEventGroupCreate().\n *\n * @param uxBitsToSet The bits to set in the event group before determining\n * if, and possibly waiting for, all the bits specified by the uxBitsToWait\n * parameter are set.\n *\n * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test\n * inside the event group.  For example, to wait for bit 0 and bit 2 set\n * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set\n * uxBitsToWaitFor to 0x07.  Etc.\n *\n * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait\n * for all of the bits specified by uxBitsToWaitFor to become set.\n *\n * @return The value of the event group at the time either the bits being waited\n * for became set, or the block time expired.  Test the return value to know\n * which bits were set.  If xEventGroupSync() returned because its timeout\n * expired then not all the bits being waited for will be set.  If\n * xEventGroupSync() returned because all the bits it was waiting for were\n * set then the returned value is the event group value before any bits were\n * automatically cleared.\n *\n * Example usage:\n <pre>\n // Bits used by the three tasks.\n #define TASK_0_BIT\t\t( 1 << 0 )\n #define TASK_1_BIT\t\t( 1 << 1 )\n #define TASK_2_BIT\t\t( 1 << 2 )\n\n #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )\n\n // Use an event group to synchronise three tasks.  It is assumed this event\n // group has already been created elsewhere.\n EventGroupHandle_t xEventBits;\n\n void vTask0( void *pvParameters )\n {\n EventBits_t uxReturn;\n TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;\n\n\t for( ;; )\n\t {\n\t\t// Perform task functionality here.\n\n\t\t// Set bit 0 in the event flag to note this task has reached the\n\t\t// sync point.  The other two tasks will set the other two bits defined\n\t\t// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation\n\t\t// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms\n\t\t// for this to happen.\n\t\tuxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );\n\n\t\tif( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )\n\t\t{\n\t\t\t// All three tasks reached the synchronisation point before the call\n\t\t\t// to xEventGroupSync() timed out.\n\t\t}\n\t}\n }\n\n void vTask1( void *pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t// Perform task functionality here.\n\n\t\t// Set bit 1 in the event flag to note this task has reached the\n\t\t// synchronisation point.  The other two tasks will set the other two\n\t\t// bits defined by ALL_SYNC_BITS.  All three tasks have reached the\n\t\t// synchronisation point when all the ALL_SYNC_BITS are set.  Wait\n\t\t// indefinitely for this to happen.\n\t\txEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );\n\n\t\t// xEventGroupSync() was called with an indefinite block time, so\n\t\t// this task will only reach here if the syncrhonisation was made by all\n\t\t// three tasks, so there is no need to test the return value.\n\t }\n }\n\n void vTask2( void *pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t// Perform task functionality here.\n\n\t\t// Set bit 2 in the event flag to note this task has reached the\n\t\t// synchronisation point.  The other two tasks will set the other two\n\t\t// bits defined by ALL_SYNC_BITS.  All three tasks have reached the\n\t\t// synchronisation point when all the ALL_SYNC_BITS are set.  Wait\n\t\t// indefinitely for this to happen.\n\t\txEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );\n\n\t\t// xEventGroupSync() was called with an indefinite block time, so\n\t\t// this task will only reach here if the syncrhonisation was made by all\n\t\t// three tasks, so there is no need to test the return value.\n\t}\n }\n\n </pre>\n * \\defgroup xEventGroupSync xEventGroupSync\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );\n </pre>\n *\n * Returns the current value of the bits in an event group.  This function\n * cannot be used from an interrupt.\n *\n * @param xEventGroup The event group being queried.\n *\n * @return The event group bits at the time xEventGroupGetBits() was called.\n *\n * \\defgroup xEventGroupGetBits xEventGroupGetBits\n * \\ingroup EventGroup\n */\n#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );\n </pre>\n *\n * A version of xEventGroupGetBits() that can be called from an ISR.\n *\n * @param xEventGroup The event group being queried.\n *\n * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.\n *\n * \\defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n *<pre>\n\tvoid xEventGroupDelete( EventGroupHandle_t xEventGroup );\n </pre>\n *\n * Delete an event group that was previously created by a call to\n * xEventGroupCreate().  Tasks that are blocked on the event group will be\n * unblocked and obtain 0 as the event group's value.\n *\n * @param xEventGroup The event group being deleted.\n */\nvoid vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;\n\n/* For internal use only. */\nvoid vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;\nvoid vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;\n\n\n#if (configUSE_TRACE_FACILITY == 1)\n\tUBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;\n\tvoid vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* EVENT_GROUPS_H */\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/list.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * This is the list implementation used by the scheduler.  While it is tailored\n * heavily for the schedulers needs, it is also available for use by\n * application code.\n *\n * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a\n * numeric value (xItemValue).  Most of the time the lists are sorted in\n * descending item value order.\n *\n * Lists are created already containing one list item.  The value of this\n * item is the maximum possible that can be stored, it is therefore always at\n * the end of the list and acts as a marker.  The list member pxHead always\n * points to this marker - even though it is at the tail of the list.  This\n * is because the tail contains a wrap back pointer to the true head of\n * the list.\n *\n * In addition to it's value, each list item contains a pointer to the next\n * item in the list (pxNext), a pointer to the list it is in (pxContainer)\n * and a pointer to back to the object that contains it.  These later two\n * pointers are included for efficiency of list manipulation.  There is\n * effectively a two way link between the object containing the list item and\n * the list item itself.\n *\n *\n * \\page ListIntroduction List Implementation\n * \\ingroup FreeRTOSIntro\n */\n\n#ifndef INC_FREERTOS_H\n\t#error FreeRTOS.h must be included before list.h\n#endif\n\n#ifndef LIST_H\n#define LIST_H\n\n/*\n * The list structure members are modified from within interrupts, and therefore\n * by rights should be declared volatile.  However, they are only modified in a\n * functionally atomic way (within critical sections of with the scheduler\n * suspended) and are either passed by reference into a function or indexed via\n * a volatile variable.  Therefore, in all use cases tested so far, the volatile\n * qualifier can be omitted in order to provide a moderate performance\n * improvement without adversely affecting functional behaviour.  The assembly\n * instructions generated by the IAR, ARM and GCC compilers when the respective\n * compiler's options were set for maximum optimisation has been inspected and\n * deemed to be as intended.  That said, as compiler technology advances, and\n * especially if aggressive cross module optimisation is used (a use case that\n * has not been exercised to any great extend) then it is feasible that the\n * volatile qualifier will be needed for correct optimisation.  It is expected\n * that a compiler removing essential code because, without the volatile\n * qualifier on the list structure members and with aggressive cross module\n * optimisation, the compiler deemed the code unnecessary will result in\n * complete and obvious failure of the scheduler.  If this is ever experienced\n * then the volatile qualifier can be inserted in the relevant places within the\n * list structures by simply defining configLIST_VOLATILE to volatile in\n * FreeRTOSConfig.h (as per the example at the bottom of this comment block).\n * If configLIST_VOLATILE is not defined then the preprocessor directives below\n * will simply #define configLIST_VOLATILE away completely.\n *\n * To use volatile list structure members then add the following line to\n * FreeRTOSConfig.h (without the quotes):\n * \"#define configLIST_VOLATILE volatile\"\n */\n#ifndef configLIST_VOLATILE\n\t#define configLIST_VOLATILE\n#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Macros that can be used to place known values within the list structures,\nthen check that the known values do not get corrupted during the execution of\nthe application.   These may catch the list data structures being overwritten in\nmemory.  They will not catch data errors caused by incorrect configuration or\nuse of FreeRTOS.*/\n#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )\n\t/* Define the macros to do nothing. */\n\t#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\n\t#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\n\t#define listFIRST_LIST_INTEGRITY_CHECK_VALUE\n\t#define listSECOND_LIST_INTEGRITY_CHECK_VALUE\n\t#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\n\t#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\n\t#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )\n\t#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )\n\t#define listTEST_LIST_ITEM_INTEGRITY( pxItem )\n\t#define listTEST_LIST_INTEGRITY( pxList )\n#else\n\t/* Define macros that add new members into the list structures. */\n\t#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\tTickType_t xListItemIntegrityValue1;\n\t#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\tTickType_t xListItemIntegrityValue2;\n\t#define listFIRST_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t\tTickType_t xListIntegrityValue1;\n\t#define listSECOND_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t\tTickType_t xListIntegrityValue2;\n\n\t/* Define macros that set the new structure members to known values. */\n\t#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\t\t( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE\n\t#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\t( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE\n\t#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )\t\t( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE\n\t#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )\t\t( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE\n\n\t/* Define macros that will assert if one of the structure members does not\n\tcontain its expected value. */\n\t#define listTEST_LIST_ITEM_INTEGRITY( pxItem )\t\tconfigASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )\n\t#define listTEST_LIST_INTEGRITY( pxList )\t\t\tconfigASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )\n#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */\n\n\n/*\n * Definition of the only type of object that a list can contain.\n */\nstruct xLIST;\nstruct xLIST_ITEM\n{\n\tlistFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tconfigLIST_VOLATILE TickType_t xItemValue;\t\t\t/*< The value being listed.  In most cases this is used to sort the list in descending order. */\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxNext;\t\t/*< Pointer to the next ListItem_t in the list. */\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxPrevious;\t/*< Pointer to the previous ListItem_t in the list. */\n\tvoid * pvOwner;\t\t\t\t\t\t\t\t\t\t/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */\n\tstruct xLIST * configLIST_VOLATILE pxContainer;\t\t/*< Pointer to the list in which this list item is placed (if any). */\n\tlistSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n};\ntypedef struct xLIST_ITEM ListItem_t;\t\t\t\t\t/* For some reason lint wants this as two separate definitions. */\n\nstruct xMINI_LIST_ITEM\n{\n\tlistFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tconfigLIST_VOLATILE TickType_t xItemValue;\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxNext;\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxPrevious;\n};\ntypedef struct xMINI_LIST_ITEM MiniListItem_t;\n\n/*\n * Definition of the type of queue used by the scheduler.\n */\ntypedef struct xLIST\n{\n\tlistFIRST_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tvolatile UBaseType_t uxNumberOfItems;\n\tListItem_t * configLIST_VOLATILE pxIndex;\t\t\t/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */\n\tMiniListItem_t xListEnd;\t\t\t\t\t\t\t/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */\n\tlistSECOND_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n} List_t;\n\n/*\n * Access macro to set the owner of a list item.  The owner of a list item\n * is the object (usually a TCB) that contains the list item.\n *\n * \\page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\n * \\ingroup LinkedList\n */\n#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )\t\t( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )\n\n/*\n * Access macro to get the owner of a list item.  The owner of a list item\n * is the object (usually a TCB) that contains the list item.\n *\n * \\page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\n * \\ingroup LinkedList\n */\n#define listGET_LIST_ITEM_OWNER( pxListItem )\t( ( pxListItem )->pvOwner )\n\n/*\n * Access macro to set the value of the list item.  In most cases the value is\n * used to sort the list in descending order.\n *\n * \\page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )\t( ( pxListItem )->xItemValue = ( xValue ) )\n\n/*\n * Access macro to retrieve the value of the list item.  The value can\n * represent anything - for example the priority of a task, or the time at\n * which a task should be unblocked.\n *\n * \\page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listGET_LIST_ITEM_VALUE( pxListItem )\t( ( pxListItem )->xItemValue )\n\n/*\n * Access macro to retrieve the value of the list item at the head of a given\n * list.\n *\n * \\page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )\t( ( ( pxList )->xListEnd ).pxNext->xItemValue )\n\n/*\n * Return the list item at the head of the list.\n *\n * \\page listGET_HEAD_ENTRY listGET_HEAD_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_HEAD_ENTRY( pxList )\t( ( ( pxList )->xListEnd ).pxNext )\n\n/*\n * Return the list item at the head of the list.\n *\n * \\page listGET_NEXT listGET_NEXT\n * \\ingroup LinkedList\n */\n#define listGET_NEXT( pxListItem )\t( ( pxListItem )->pxNext )\n\n/*\n * Return the list item that marks the end of the list\n *\n * \\page listGET_END_MARKER listGET_END_MARKER\n * \\ingroup LinkedList\n */\n#define listGET_END_MARKER( pxList )\t( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )\n\n/*\n * Access macro to determine if a list contains any items.  The macro will\n * only have the value true if the list is empty.\n *\n * \\page listLIST_IS_EMPTY listLIST_IS_EMPTY\n * \\ingroup LinkedList\n */\n#define listLIST_IS_EMPTY( pxList )\t( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )\n\n/*\n * Access macro to return the number of items in the list.\n */\n#define listCURRENT_LIST_LENGTH( pxList )\t( ( pxList )->uxNumberOfItems )\n\n/*\n * Access function to obtain the owner of the next entry in a list.\n *\n * The list member pxIndex is used to walk through a list.  Calling\n * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list\n * and returns that entry's pxOwner parameter.  Using multiple calls to this\n * function it is therefore possible to move through every item contained in\n * a list.\n *\n * The pxOwner parameter of a list item is a pointer to the object that owns\n * the list item.  In the scheduler this is normally a task control block.\n * The pxOwner parameter effectively creates a two way link between the list\n * item and its owner.\n *\n * @param pxTCB pxTCB is set to the address of the owner of the next list item.\n * @param pxList The list from which the next item owner is to be returned.\n *\n * \\page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nList_t * const pxConstList = ( pxList );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Increment the index to the next item and return the item, ensuring */\t\t\t\t\\\n\t/* we don't return the marker used at the end of the list.  */\t\t\t\t\t\t\t\\\n\t( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;\t\t\t\t\t\t\t\\\n\tif( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n\n/*\n * Access function to obtain the owner of the first entry in a list.  Lists\n * are normally sorted in ascending item value order.\n *\n * This function returns the pxOwner member of the first item in the list.\n * The pxOwner parameter of a list item is a pointer to the object that owns\n * the list item.  In the scheduler this is normally a task control block.\n * The pxOwner parameter effectively creates a two way link between the list\n * item and its owner.\n *\n * @param pxList The list from which the owner of the head item is to be\n * returned.\n *\n * \\page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )\n\n/*\n * Check to see if a list item is within a list.  The list item maintains a\n * \"container\" pointer that points to the list it is in.  All this macro does\n * is check to see if the container and the list match.\n *\n * @param pxList The list we want to know if the list item is within.\n * @param pxListItem The list item we want to know if is in the list.\n * @return pdTRUE if the list item is in the list, otherwise pdFALSE.\n */\n#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )\n\n/*\n * Return the list a list item is contained within (referenced from).\n *\n * @param pxListItem The list item being queried.\n * @return A pointer to the List_t object that references the pxListItem\n */\n#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )\n\n/*\n * This provides a crude means of knowing if a list has been initialised, as\n * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()\n * function.\n */\n#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )\n\n/*\n * Must be called before a list is used!  This initialises all the members\n * of the list structure and inserts the xListEnd item into the list as a\n * marker to the back of the list.\n *\n * @param pxList Pointer to the list being initialised.\n *\n * \\page vListInitialise vListInitialise\n * \\ingroup LinkedList\n */\nvoid vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;\n\n/*\n * Must be called before a list item is used.  This sets the list container to\n * null so the item does not think that it is already contained in a list.\n *\n * @param pxItem Pointer to the list item being initialised.\n *\n * \\page vListInitialiseItem vListInitialiseItem\n * \\ingroup LinkedList\n */\nvoid vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert a list item into a list.  The item will be inserted into the list in\n * a position determined by its item value (descending item value order).\n *\n * @param pxList The list into which the item is to be inserted.\n *\n * @param pxNewListItem The item that is to be placed in the list.\n *\n * \\page vListInsert vListInsert\n * \\ingroup LinkedList\n */\nvoid vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert a list item into a list.  The item will be inserted in a position\n * such that it will be the last item within the list returned by multiple\n * calls to listGET_OWNER_OF_NEXT_ENTRY.\n *\n * The list member pxIndex is used to walk through a list.  Calling\n * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.\n * Placing an item in a list using vListInsertEnd effectively places the item\n * in the list position pointed to by pxIndex.  This means that every other\n * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before\n * the pxIndex parameter again points to the item being inserted.\n *\n * @param pxList The list into which the item is to be inserted.\n *\n * @param pxNewListItem The list item to be inserted into the list.\n *\n * \\page vListInsertEnd vListInsertEnd\n * \\ingroup LinkedList\n */\nvoid vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Remove an item from a list.  The list item has a pointer to the list that\n * it is in, so only the list item need be passed into the function.\n *\n * @param uxListRemove The item to be removed.  The item will remove itself from\n * the list pointed to by it's pxContainer parameter.\n *\n * @return The number of items that remain in the list after the list item has\n * been removed.\n *\n * \\page uxListRemove uxListRemove\n * \\ingroup LinkedList\n */\nUBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/message_buffer.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n/*\n * Message buffers build functionality on top of FreeRTOS stream buffers.\n * Whereas stream buffers are used to send a continuous stream of data from one\n * task or interrupt to another, message buffers are used to send variable\n * length discrete messages from one task or interrupt to another.  Their\n * implementation is light weight, making them particularly suited for interrupt\n * to task and core to core communication scenarios.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * timeout to 0.\n *\n * Message buffers hold variable length messages.  To enable that, when a\n * message is written to the message buffer an additional sizeof( size_t ) bytes\n * are also written to store the message's length (that happens internally, with\n * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so writing a 10 byte message to a message buffer on a 32-bit\n * architecture will actually reduce the available space in the message buffer\n * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length\n * of the message).\n */\n\n#ifndef FREERTOS_MESSAGE_BUFFER_H\n#define FREERTOS_MESSAGE_BUFFER_H\n\n/* Message buffers are built onto of stream buffers. */\n#include \"stream_buffer.h\"\n\n#if defined( __cplusplus )\nextern \"C\" {\n#endif\n\n/**\n * Type by which message buffers are referenced.  For example, a call to\n * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can\n * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),\n * etc.\n */\ntypedef void * MessageBufferHandle_t;\n\n/*-----------------------------------------------------------*/\n\n/**\n * message_buffer.h\n *\n<pre>\nMessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );\n</pre>\n *\n * Creates a new message buffer using dynamically allocated memory.  See\n * xMessageBufferCreateStatic() for a version that uses statically allocated\n * memory (memory that is allocated at compile time).\n *\n * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in\n * FreeRTOSConfig.h for xMessageBufferCreate() to be available.\n *\n * @param xBufferSizeBytes The total number of bytes (not messages) the message\n * buffer will be able to hold at any one time.  When a message is written to\n * the message buffer an additional sizeof( size_t ) bytes are also written to\n * store the message's length.  sizeof( size_t ) is typically 4 bytes on a\n * 32-bit architecture, so on most 32-bit architectures a 10 byte message will\n * take up 14 bytes of message buffer space.\n *\n * @return If NULL is returned, then the message buffer cannot be created\n * because there is insufficient heap memory available for FreeRTOS to allocate\n * the message buffer data structures and storage area.  A non-NULL value being\n * returned indicates that the message buffer has been created successfully -\n * the returned value should be stored as the handle to the created message\n * buffer.\n *\n * Example use:\n<pre>\n\nvoid vAFunction( void )\n{\nMessageBufferHandle_t xMessageBuffer;\nconst size_t xMessageBufferSizeBytes = 100;\n\n    // Create a message buffer that can hold 100 bytes.  The memory used to hold\n    // both the message buffer structure and the messages themselves is allocated\n    // dynamically.  Each message added to the buffer consumes an additional 4\n    // bytes which are used to hold the lengh of the message.\n    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );\n\n    if( xMessageBuffer == NULL )\n    {\n        // There was not enough heap memory space available to create the\n        // message buffer.\n    }\n    else\n    {\n        // The message buffer was created successfully and can now be used.\n    }\n\n</pre>\n * \\defgroup xMessageBufferCreate xMessageBufferCreate\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )\n\n/**\n * message_buffer.h\n *\n<pre>\nMessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,\n                                                  uint8_t *pucMessageBufferStorageArea,\n                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );\n</pre>\n * Creates a new message buffer using statically allocated memory.  See\n * xMessageBufferCreate() for a version that uses dynamically allocated memory.\n *\n * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the\n * pucMessageBufferStorageArea parameter.  When a message is written to the\n * message buffer an additional sizeof( size_t ) bytes are also written to store\n * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so on most 32-bit architecture a 10 byte message will take up\n * 14 bytes of message buffer space.  The maximum number of bytes that can be\n * stored in the message buffer is actually (xBufferSizeBytes - 1).\n *\n * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at\n * least xBufferSizeBytes + 1 big.  This is the array to which messages are\n * copied when they are written to the message buffer.\n *\n * @param pxStaticMessageBuffer Must point to a variable of type\n * StaticMessageBuffer_t, which will be used to hold the message buffer's data\n * structure.\n *\n * @return If the message buffer is created successfully then a handle to the\n * created message buffer is returned. If either pucMessageBufferStorageArea or\n * pxStaticmessageBuffer are NULL then NULL is returned.\n *\n * Example use:\n<pre>\n\n// Used to dimension the array used to hold the messages.  The available space\n// will actually be one less than this, so 999.\n#define STORAGE_SIZE_BYTES 1000\n\n// Defines the memory that will actually hold the messages within the message\n// buffer.\nstatic uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];\n\n// The variable used to hold the message buffer structure.\nStaticMessageBuffer_t xMessageBufferStruct;\n\nvoid MyFunction( void )\n{\nMessageBufferHandle_t xMessageBuffer;\n\n    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),\n                                                 ucBufferStorage,\n                                                 &xMessageBufferStruct );\n\n    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer\n    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to\n    // reference the created message buffer in other message buffer API calls.\n\n    // Other code that uses the message buffer can go here.\n}\n\n</pre>\n * \\defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )\n\n/**\n * message_buffer.h\n *\n<pre>\nsize_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,\n                           const void *pvTxData,\n                           size_t xDataLengthBytes,\n                           TickType_t xTicksToWait );\n<pre>\n *\n * Sends a discrete message to the message buffer.  The message can be any\n * length that fits within the buffer's free space, and is copied into the\n * buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferSend() to write to a message buffer from a task.  Use\n * xMessageBufferSendFromISR() to write to a message buffer from an interrupt\n * service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer to which a message is\n * being sent.\n *\n * @param pvTxData A pointer to the message that is to be copied into the\n * message buffer.\n *\n * @param xDataLengthBytes The length of the message.  That is, the number of\n * bytes to copy from pvTxData into the message buffer.  When a message is\n * written to the message buffer an additional sizeof( size_t ) bytes are also\n * written to store the message's length.  sizeof( size_t ) is typically 4 bytes\n * on a 32-bit architecture, so on most 32-bit architecture setting\n * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24\n * bytes (20 bytes of message data and 4 bytes to hold the message length).\n *\n * @param xTicksToWait The maximum amount of time the calling task should remain\n * in the Blocked state to wait for enough space to become available in the\n * message buffer, should the message buffer have insufficient space when\n * xMessageBufferSend() is called.  The calling task will never block if\n * xTicksToWait is zero.  The block time is specified in tick periods, so the\n * absolute time it represents is dependent on the tick frequency.  The macro\n * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into\n * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause\n * the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any\n * CPU time when they are in the Blocked state.\n *\n * @return The number of bytes written to the message buffer.  If the call to\n * xMessageBufferSend() times out before there was enough space to write the\n * message into the message buffer then zero is returned.  If the call did not\n * time out then xDataLengthBytes is returned.\n *\n * Example use:\n<pre>\nvoid vAFunction( MessageBufferHandle_t xMessageBuffer )\n{\nsize_t xBytesSent;\nuint8_t ucArrayToSend[] = { 0, 1, 2, 3 };\nchar *pcStringToSend = \"String to send\";\nconst TickType_t x100ms = pdMS_TO_TICKS( 100 );\n\n    // Send an array to the message buffer, blocking for a maximum of 100ms to\n    // wait for enough space to be available in the message buffer.\n    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );\n\n    if( xBytesSent != sizeof( ucArrayToSend ) )\n    {\n        // The call to xMessageBufferSend() times out before there was enough\n        // space in the buffer for the data to be written.\n    }\n\n    // Send the string to the message buffer.  Return immediately if there is\n    // not enough space in the buffer.\n    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );\n\n    if( xBytesSent != strlen( pcStringToSend ) )\n    {\n        // The string could not be added to the message buffer because there was\n        // not enough free space in the buffer.\n    }\n}\n</pre>\n * \\defgroup xMessageBufferSend xMessageBufferSend\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )\n\n/**\n * message_buffer.h\n *\n<pre>\nsize_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,\n                                  const void *pvTxData,\n                                  size_t xDataLengthBytes,\n                                  BaseType_t *pxHigherPriorityTaskWoken );\n<pre>\n *\n * Interrupt safe version of the API function that sends a discrete message to\n * the message buffer.  The message can be any length that fits within the\n * buffer's free space, and is copied into the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferSend() to write to a message buffer from a task.  Use\n * xMessageBufferSendFromISR() to write to a message buffer from an interrupt\n * service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer to which a message is\n * being sent.\n *\n * @param pvTxData A pointer to the message that is to be copied into the\n * message buffer.\n *\n * @param xDataLengthBytes The length of the message.  That is, the number of\n * bytes to copy from pvTxData into the message buffer.  When a message is\n * written to the message buffer an additional sizeof( size_t ) bytes are also\n * written to store the message's length.  sizeof( size_t ) is typically 4 bytes\n * on a 32-bit architecture, so on most 32-bit architecture setting\n * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24\n * bytes (20 bytes of message data and 4 bytes to hold the message length).\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will\n * have a task blocked on it waiting for data.  Calling\n * xMessageBufferSendFromISR() can make data available, and so cause a task that\n * was waiting for data to leave the Blocked state.  If calling\n * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently executing task (the\n * task that was interrupted), then, internally, xMessageBufferSendFromISR()\n * will set *pxHigherPriorityTaskWoken to pdTRUE.  If\n * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  This will\n * ensure that the interrupt returns directly to the highest priority Ready\n * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it\n * is passed into the function.  See the code example below for an example.\n *\n * @return The number of bytes actually written to the message buffer.  If the\n * message buffer didn't have enough free space for the message to be stored\n * then 0 is returned, otherwise xDataLengthBytes is returned.\n *\n * Example use:\n<pre>\n// A message buffer that has already been created.\nMessageBufferHandle_t xMessageBuffer;\n\nvoid vAnInterruptServiceRoutine( void )\n{\nsize_t xBytesSent;\nchar *pcStringToSend = \"String to send\";\nBaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.\n\n    // Attempt to send the string to the message buffer.\n    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,\n                                            ( void * ) pcStringToSend,\n                                            strlen( pcStringToSend ),\n                                            &xHigherPriorityTaskWoken );\n\n    if( xBytesSent != strlen( pcStringToSend ) )\n    {\n        // The string could not be added to the message buffer because there was\n        // not enough free space in the buffer.\n    }\n\n    // If xHigherPriorityTaskWoken was set to pdTRUE inside\n    // xMessageBufferSendFromISR() then a task that has a priority above the\n    // priority of the currently executing task was unblocked and a context\n    // switch should be performed to ensure the ISR returns to the unblocked\n    // task.  In most FreeRTOS ports this is done by simply passing\n    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the\n    // variables value, and perform the context switch if necessary.  Check the\n    // documentation for the port in use for port specific instructions.\n    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n}\n</pre>\n * \\defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )\n\n/**\n * message_buffer.h\n *\n<pre>\nsize_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,\n                              void *pvRxData,\n                              size_t xBufferLengthBytes,\n                              TickType_t xTicksToWait );\n</pre>\n *\n * Receives a discrete message from a message buffer.  Messages can be of\n * variable length and are copied out of the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferReceive() to read from a message buffer from a task.  Use\n * xMessageBufferReceiveFromISR() to read from a message buffer from an\n * interrupt service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer from which a message\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received message is\n * to be copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData\n * parameter.  This sets the maximum length of the message that can be received.\n * If xBufferLengthBytes is too small to hold the next message then the message\n * will be left in the message buffer and 0 will be returned.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for a message, should the message buffer be empty.\n * xMessageBufferReceive() will return immediately if xTicksToWait is zero and\n * the message buffer is empty.  The block time is specified in tick periods, so\n * the absolute time it represents is dependent on the tick frequency.  The\n * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds\n * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will\n * cause the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any\n * CPU time when they are in the Blocked state.\n *\n * @return The length, in bytes, of the message read from the message buffer, if\n * any.  If xMessageBufferReceive() times out before a message became available\n * then zero is returned.  If the length of the message is greater than\n * xBufferLengthBytes then the message will be left in the message buffer and\n * zero is returned.\n *\n * Example use:\n<pre>\nvoid vAFunction( MessageBuffer_t xMessageBuffer )\n{\nuint8_t ucRxData[ 20 ];\nsize_t xReceivedBytes;\nconst TickType_t xBlockTime = pdMS_TO_TICKS( 20 );\n\n    // Receive the next message from the message buffer.  Wait in the Blocked\n    // state (so not using any CPU processing time) for a maximum of 100ms for\n    // a message to become available.\n    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,\n                                            ( void * ) ucRxData,\n                                            sizeof( ucRxData ),\n                                            xBlockTime );\n\n    if( xReceivedBytes > 0 )\n    {\n        // A ucRxData contains a message that is xReceivedBytes long.  Process\n        // the message here....\n    }\n}\n</pre>\n * \\defgroup xMessageBufferReceive xMessageBufferReceive\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )\n\n\n/**\n * message_buffer.h\n *\n<pre>\nsize_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,\n                                     void *pvRxData,\n                                     size_t xBufferLengthBytes,\n                                     BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * An interrupt safe version of the API function that receives a discrete\n * message from a message buffer.  Messages can be of variable length and are\n * copied out of the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferReceive() to read from a message buffer from a task.  Use\n * xMessageBufferReceiveFromISR() to read from a message buffer from an\n * interrupt service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer from which a message\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received message is\n * to be copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData\n * parameter.  This sets the maximum length of the message that can be received.\n * If xBufferLengthBytes is too small to hold the next message then the message\n * will be left in the message buffer and 0 will be returned.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will\n * have a task blocked on it waiting for space to become available.  Calling\n * xMessageBufferReceiveFromISR() can make space available, and so cause a task\n * that is waiting for space to leave the Blocked state.  If calling\n * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and\n * the unblocked task has a priority higher than the currently executing task\n * (the task that was interrupted), then, internally,\n * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.\n * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  That will\n * ensure the interrupt returns directly to the highest priority Ready state\n * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is\n * passed into the function.  See the code example below for an example.\n *\n * @return The length, in bytes, of the message read from the message buffer, if\n * any.\n *\n * Example use:\n<pre>\n// A message buffer that has already been created.\nMessageBuffer_t xMessageBuffer;\n\nvoid vAnInterruptServiceRoutine( void )\n{\nuint8_t ucRxData[ 20 ];\nsize_t xReceivedBytes;\nBaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.\n\n    // Receive the next message from the message buffer.\n    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,\n                                                  ( void * ) ucRxData,\n                                                  sizeof( ucRxData ),\n                                                  &xHigherPriorityTaskWoken );\n\n    if( xReceivedBytes > 0 )\n    {\n        // A ucRxData contains a message that is xReceivedBytes long.  Process\n        // the message here....\n    }\n\n    // If xHigherPriorityTaskWoken was set to pdTRUE inside\n    // xMessageBufferReceiveFromISR() then a task that has a priority above the\n    // priority of the currently executing task was unblocked and a context\n    // switch should be performed to ensure the ISR returns to the unblocked\n    // task.  In most FreeRTOS ports this is done by simply passing\n    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the\n    // variables value, and perform the context switch if necessary.  Check the\n    // documentation for the port in use for port specific instructions.\n    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n}\n</pre>\n * \\defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )\n\n/**\n * message_buffer.h\n *\n<pre>\nvoid vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );\n</pre>\n *\n * Deletes a message buffer that was previously created using a call to\n * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message\n * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),\n * then the allocated memory is freed.\n *\n * A message buffer handle must not be used after the message buffer has been\n * deleted.\n *\n * @param xMessageBuffer The handle of the message buffer to be deleted.\n *\n */\n#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )\n\n/**\n * message_buffer.h\n<pre>\nBaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );\n</pre>\n *\n * Tests to see if a message buffer is full.  A message buffer is full if it\n * cannot accept any more messages, of any size, until space is made available\n * by a message being removed from the message buffer.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return If the message buffer referenced by xMessageBuffer is full then\n * pdTRUE is returned.  Otherwise pdFALSE is returned.\n */\n#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )\n\n/**\n * message_buffer.h\n<pre>\nBaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );\n</pre>\n *\n * Tests to see if a message buffer is empty (does not contain any messages).\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return If the message buffer referenced by xMessageBuffer is empty then\n * pdTRUE is returned.  Otherwise pdFALSE is returned.\n *\n */\n#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )\n\n/**\n * message_buffer.h\n<pre>\nBaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );\n</pre>\n *\n * Resets a message buffer to its initial empty state, discarding any message it\n * contained.\n *\n * A message buffer can only be reset if there are no tasks blocked on it.\n *\n * @param xMessageBuffer The handle of the message buffer being reset.\n *\n * @return If the message buffer was reset then pdPASS is returned.  If the\n * message buffer could not be reset because either there was a task blocked on\n * the message queue to wait for space to become available, or to wait for a\n * a message to be available, then pdFAIL is returned.\n *\n * \\defgroup xMessageBufferReset xMessageBufferReset\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )\n\n\n/**\n * message_buffer.h\n<pre>\nsize_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );\n</pre>\n * Returns the number of bytes of free space in the message buffer.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return The number of bytes that can be written to the message buffer before\n * the message buffer would be full.  When a message is written to the message\n * buffer an additional sizeof( size_t ) bytes are also written to store the\n * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size\n * of the largest message that can be written to the message buffer is 6 bytes.\n *\n * \\defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )\n#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */\n\n/**\n * message_buffer.h\n <pre>\n size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );\n </pre>\n * Returns the length (in bytes) of the next message in a message buffer.\n * Useful if xMessageBufferReceive() returned 0 because the size of the buffer\n * passed into xMessageBufferReceive() was too small to hold the next message.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return The length (in bytes) of the next message in the message buffer, or 0\n * if the message buffer is empty.\n *\n * \\defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * message_buffer.h\n *\n<pre>\nBaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * For advanced users only.\n *\n * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is sent to a message buffer or stream buffer.  If there was a task that\n * was blocked on the message or stream buffer waiting for data to arrive then\n * the sbSEND_COMPLETED() macro sends a notification to the task to remove it\n * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same\n * thing.  It is provided to enable application writers to implement their own\n * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer to which data was\n * written.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xMessageBufferSendCompletedFromISR().  If calling\n * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\n#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )\n\n/**\n * message_buffer.h\n *\n<pre>\nBaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * For advanced users only.\n *\n * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is read out of a message buffer or stream buffer.  If there was a task\n * that was blocked on the message or stream buffer waiting for data to arrive\n * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to\n * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()\n * does the same thing.  It is provided to enable application writers to\n * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT\n * ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer from which data was\n * read.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xMessageBufferReceiveCompletedFromISR().  If calling\n * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\n#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )\n\n#if defined( __cplusplus )\n} /* extern \"C\" */\n#endif\n\n#endif\t/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/mpu_prototypes.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * When the MPU is used the standard (non MPU) API functions are mapped to\n * equivalents that start \"MPU_\", the prototypes for which are defined in this\n * header files.  This will cause the application code to call the MPU_ version\n * which wraps the non-MPU version with privilege promoting then demoting code,\n * so the kernel code always runs will full privileges.\n */\n\n\n#ifndef MPU_PROTOTYPES_H\n#define MPU_PROTOTYPES_H\n\n/* MPU versions of tasks.h API functions. */\nBaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\neTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;\nchar * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nconfigSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;\nTaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;\nvoid * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nuint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of queue.h API functions. */\nBaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nconst char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;\nQueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nuint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of timers.h API functions. */\nTimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;\nTimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;\nvoid * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nconst char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of event_group.h API functions. */\nEventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;\nEventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of message/stream_buffer.h API functions. */\nsize_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;\nStreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;\nStreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;\n\n\n\n#endif /* MPU_PROTOTYPES_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/mpu_wrappers.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef MPU_WRAPPERS_H\n#define MPU_WRAPPERS_H\n\n/* This file redefines API functions to be called through a wrapper macro, but\nonly for ports that are using the MPU. */\n#ifdef portUSING_MPU_WRAPPERS\n\n\t/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is\n\tincluded from queue.c or task.c to prevent it from having an effect within\n\tthose files. */\n\t#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n\t\t/*\n\t\t * Map standard (non MPU) API functions to equivalents that start\n\t\t * \"MPU_\".  This will cause the application code to call the MPU_\n\t\t * version, which wraps the non-MPU version with privilege promoting\n\t\t * then demoting code, so the kernel code always runs will full\n\t\t * privileges.\n\t\t */\n\n\t\t/* Map standard tasks.h API functions to the MPU equivalents. */\n\t\t#define xTaskCreate\t\t\t\t\t\t\t\tMPU_xTaskCreate\n\t\t#define xTaskCreateStatic\t\t\t\t\t\tMPU_xTaskCreateStatic\n\t\t#define xTaskCreateRestricted\t\t\t\t\tMPU_xTaskCreateRestricted\n\t\t#define vTaskAllocateMPURegions\t\t\t\t\tMPU_vTaskAllocateMPURegions\n\t\t#define vTaskDelete\t\t\t\t\t\t\t\tMPU_vTaskDelete\n\t\t#define vTaskDelay\t\t\t\t\t\t\t\tMPU_vTaskDelay\n\t\t#define vTaskDelayUntil\t\t\t\t\t\t\tMPU_vTaskDelayUntil\n\t\t#define xTaskAbortDelay\t\t\t\t\t\t\tMPU_xTaskAbortDelay\n\t\t#define uxTaskPriorityGet\t\t\t\t\t\tMPU_uxTaskPriorityGet\n\t\t#define eTaskGetState\t\t\t\t\t\t\tMPU_eTaskGetState\n\t\t#define vTaskGetInfo\t\t\t\t\t\t\tMPU_vTaskGetInfo\n\t\t#define vTaskPrioritySet\t\t\t\t\t\tMPU_vTaskPrioritySet\n\t\t#define vTaskSuspend\t\t\t\t\t\t\tMPU_vTaskSuspend\n\t\t#define vTaskResume\t\t\t\t\t\t\t\tMPU_vTaskResume\n\t\t#define vTaskSuspendAll\t\t\t\t\t\t\tMPU_vTaskSuspendAll\n\t\t#define xTaskResumeAll\t\t\t\t\t\t\tMPU_xTaskResumeAll\n\t\t#define xTaskGetTickCount\t\t\t\t\t\tMPU_xTaskGetTickCount\n\t\t#define uxTaskGetNumberOfTasks\t\t\t\t\tMPU_uxTaskGetNumberOfTasks\n\t\t#define pcTaskGetName\t\t\t\t\t\t\tMPU_pcTaskGetName\n\t\t#define xTaskGetHandle\t\t\t\t\t\t\tMPU_xTaskGetHandle\n\t\t#define uxTaskGetStackHighWaterMark\t\t\t\tMPU_uxTaskGetStackHighWaterMark\n\t\t#define uxTaskGetStackHighWaterMark2\t\t\tMPU_uxTaskGetStackHighWaterMark2\n\t\t#define vTaskSetApplicationTaskTag\t\t\t\tMPU_vTaskSetApplicationTaskTag\n\t\t#define xTaskGetApplicationTaskTag\t\t\t\tMPU_xTaskGetApplicationTaskTag\n\t\t#define vTaskSetThreadLocalStoragePointer\t\tMPU_vTaskSetThreadLocalStoragePointer\n\t\t#define pvTaskGetThreadLocalStoragePointer\t\tMPU_pvTaskGetThreadLocalStoragePointer\n\t\t#define xTaskCallApplicationTaskHook\t\t\tMPU_xTaskCallApplicationTaskHook\n\t\t#define xTaskGetIdleTaskHandle\t\t\t\t\tMPU_xTaskGetIdleTaskHandle\n\t\t#define uxTaskGetSystemState\t\t\t\t\tMPU_uxTaskGetSystemState\n\t\t#define vTaskList\t\t\t\t\t\t\t\tMPU_vTaskList\n\t\t#define vTaskGetRunTimeStats\t\t\t\t\tMPU_vTaskGetRunTimeStats\n\t\t#define xTaskGetIdleRunTimeCounter\t\t\t\tMPU_xTaskGetIdleRunTimeCounter\n\t\t#define xTaskGenericNotify\t\t\t\t\t\tMPU_xTaskGenericNotify\n\t\t#define xTaskNotifyWait\t\t\t\t\t\t\tMPU_xTaskNotifyWait\n\t\t#define ulTaskNotifyTake\t\t\t\t\t\tMPU_ulTaskNotifyTake\n\t\t#define xTaskNotifyStateClear\t\t\t\t\tMPU_xTaskNotifyStateClear\n\n\t\t#define xTaskGetCurrentTaskHandle\t\t\t\tMPU_xTaskGetCurrentTaskHandle\n\t\t#define vTaskSetTimeOutState\t\t\t\t\tMPU_vTaskSetTimeOutState\n\t\t#define xTaskCheckForTimeOut\t\t\t\t\tMPU_xTaskCheckForTimeOut\n\t\t#define xTaskGetSchedulerState\t\t\t\t\tMPU_xTaskGetSchedulerState\n\n\t\t/* Map standard queue.h API functions to the MPU equivalents. */\n\t\t#define xQueueGenericSend\t\t\t\t\t\tMPU_xQueueGenericSend\n\t\t#define xQueueReceive\t\t\t\t\t\t\tMPU_xQueueReceive\n\t\t#define xQueuePeek\t\t\t\t\t\t\t\tMPU_xQueuePeek\n\t\t#define xQueueSemaphoreTake\t\t\t\t\t\tMPU_xQueueSemaphoreTake\n\t\t#define uxQueueMessagesWaiting\t\t\t\t\tMPU_uxQueueMessagesWaiting\n\t\t#define uxQueueSpacesAvailable\t\t\t\t\tMPU_uxQueueSpacesAvailable\n\t\t#define vQueueDelete\t\t\t\t\t\t\tMPU_vQueueDelete\n\t\t#define xQueueCreateMutex\t\t\t\t\t\tMPU_xQueueCreateMutex\n\t\t#define xQueueCreateMutexStatic\t\t\t\t\tMPU_xQueueCreateMutexStatic\n\t\t#define xQueueCreateCountingSemaphore\t\t\tMPU_xQueueCreateCountingSemaphore\n\t\t#define xQueueCreateCountingSemaphoreStatic\t\tMPU_xQueueCreateCountingSemaphoreStatic\n\t\t#define xQueueGetMutexHolder\t\t\t\t\tMPU_xQueueGetMutexHolder\n\t\t#define xQueueTakeMutexRecursive\t\t\t\tMPU_xQueueTakeMutexRecursive\n\t\t#define xQueueGiveMutexRecursive\t\t\t\tMPU_xQueueGiveMutexRecursive\n\t\t#define xQueueGenericCreate\t\t\t\t\t\tMPU_xQueueGenericCreate\n\t\t#define xQueueGenericCreateStatic\t\t\t\tMPU_xQueueGenericCreateStatic\n\t\t#define xQueueCreateSet\t\t\t\t\t\t\tMPU_xQueueCreateSet\n\t\t#define xQueueAddToSet\t\t\t\t\t\t\tMPU_xQueueAddToSet\n\t\t#define xQueueRemoveFromSet\t\t\t\t\t\tMPU_xQueueRemoveFromSet\n\t\t#define xQueueSelectFromSet\t\t\t\t\t\tMPU_xQueueSelectFromSet\n\t\t#define xQueueGenericReset\t\t\t\t\t\tMPU_xQueueGenericReset\n\n\t\t#if( configQUEUE_REGISTRY_SIZE > 0 )\n\t\t\t#define vQueueAddToRegistry\t\t\t\t\t\tMPU_vQueueAddToRegistry\n\t\t\t#define vQueueUnregisterQueue\t\t\t\t\tMPU_vQueueUnregisterQueue\n\t\t\t#define pcQueueGetName\t\t\t\t\t\t\tMPU_pcQueueGetName\n\t\t#endif\n\n\t\t/* Map standard timer.h API functions to the MPU equivalents. */\n\t\t#define xTimerCreate\t\t\t\t\t\t\tMPU_xTimerCreate\n\t\t#define xTimerCreateStatic\t\t\t\t\t\tMPU_xTimerCreateStatic\n\t\t#define pvTimerGetTimerID\t\t\t\t\t\tMPU_pvTimerGetTimerID\n\t\t#define vTimerSetTimerID\t\t\t\t\t\tMPU_vTimerSetTimerID\n\t\t#define xTimerIsTimerActive\t\t\t\t\t\tMPU_xTimerIsTimerActive\n\t\t#define xTimerGetTimerDaemonTaskHandle\t\t\tMPU_xTimerGetTimerDaemonTaskHandle\n\t\t#define xTimerPendFunctionCall\t\t\t\t\tMPU_xTimerPendFunctionCall\n\t\t#define pcTimerGetName\t\t\t\t\t\t\tMPU_pcTimerGetName\n\t\t#define vTimerSetReloadMode\t\t\t\t\t\tMPU_vTimerSetReloadMode\n\t\t#define xTimerGetPeriod\t\t\t\t\t\t\tMPU_xTimerGetPeriod\n\t\t#define xTimerGetExpiryTime\t\t\t\t\t\tMPU_xTimerGetExpiryTime\n\t\t#define xTimerGenericCommand\t\t\t\t\tMPU_xTimerGenericCommand\n\n\t\t/* Map standard event_group.h API functions to the MPU equivalents. */\n\t\t#define xEventGroupCreate\t\t\t\t\t\tMPU_xEventGroupCreate\n\t\t#define xEventGroupCreateStatic\t\t\t\t\tMPU_xEventGroupCreateStatic\n\t\t#define xEventGroupWaitBits\t\t\t\t\t\tMPU_xEventGroupWaitBits\n\t\t#define xEventGroupClearBits\t\t\t\t\tMPU_xEventGroupClearBits\n\t\t#define xEventGroupSetBits\t\t\t\t\t\tMPU_xEventGroupSetBits\n\t\t#define xEventGroupSync\t\t\t\t\t\t\tMPU_xEventGroupSync\n\t\t#define vEventGroupDelete\t\t\t\t\t\tMPU_vEventGroupDelete\n\n\t\t/* Map standard message/stream_buffer.h API functions to the MPU\n\t\tequivalents. */\n\t\t#define xStreamBufferSend\t\t\t\t\t\tMPU_xStreamBufferSend\n\t\t#define xStreamBufferReceive\t\t\t\t\tMPU_xStreamBufferReceive\n\t\t#define xStreamBufferNextMessageLengthBytes\t\tMPU_xStreamBufferNextMessageLengthBytes\n\t\t#define vStreamBufferDelete\t\t\t\t\t\tMPU_vStreamBufferDelete\n\t\t#define xStreamBufferIsFull\t\t\t\t\t\tMPU_xStreamBufferIsFull\n\t\t#define xStreamBufferIsEmpty\t\t\t\t\tMPU_xStreamBufferIsEmpty\n\t\t#define xStreamBufferReset\t\t\t\t\t\tMPU_xStreamBufferReset\n\t\t#define xStreamBufferSpacesAvailable\t\t\tMPU_xStreamBufferSpacesAvailable\n\t\t#define xStreamBufferBytesAvailable\t\t\t\tMPU_xStreamBufferBytesAvailable\n\t\t#define xStreamBufferSetTriggerLevel\t\t\tMPU_xStreamBufferSetTriggerLevel\n\t\t#define xStreamBufferGenericCreate\t\t\t\tMPU_xStreamBufferGenericCreate\n\t\t#define xStreamBufferGenericCreateStatic\t\tMPU_xStreamBufferGenericCreateStatic\n\n\n\t\t/* Remove the privileged function macro, but keep the PRIVILEGED_DATA\n\t\tmacro so applications can place data in privileged access sections\n\t\t(useful when using statically allocated objects). */\n\t\t#define PRIVILEGED_FUNCTION\n\t\t#define PRIVILEGED_DATA __attribute__((section(\"privileged_data\")))\n\t\t#define FREERTOS_SYSTEM_CALL\n\n\t#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\n\n\t\t/* Ensure API functions go in the privileged execution section. */\n\t\t#define PRIVILEGED_FUNCTION __attribute__((section(\"privileged_functions\")))\n\t\t#define PRIVILEGED_DATA __attribute__((section(\"privileged_data\")))\n\t\t#define FREERTOS_SYSTEM_CALL __attribute__((section( \"freertos_system_calls\")))\n\n\t#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\n\n#else /* portUSING_MPU_WRAPPERS */\n\n\t#define PRIVILEGED_FUNCTION\n\t#define PRIVILEGED_DATA\n\t#define FREERTOS_SYSTEM_CALL\n\t#define portUSING_MPU_WRAPPERS 0\n\n#endif /* portUSING_MPU_WRAPPERS */\n\n\n#endif /* MPU_WRAPPERS_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/portable.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*-----------------------------------------------------------\n * Portable layer API.  Each function must be defined for each port.\n *----------------------------------------------------------*/\n\n#ifndef PORTABLE_H\n#define PORTABLE_H\n\n/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a\npre-processor definition was used to ensure the pre-processor found the correct\nportmacro.h file for the port being used.  That scheme was deprecated in favour\nof setting the compiler's include path such that it found the correct\nportmacro.h file - removing the need for the constant and allowing the\nportmacro.h file to be located anywhere in relation to the port being used.\nPurely for reasons of backward compatibility the old method is still valid, but\nto make it clear that new projects should not use it, support for the port\nspecific constants has been moved into the deprecated_definitions.h header\nfile. */\n#include \"deprecated_definitions.h\"\n\n/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h\ndid not result in a portmacro.h header file being included - and it should be\nincluded here.  In this case the path to the correct portmacro.h header file\nmust be set in the compiler's include path. */\n#ifndef portENTER_CRITICAL\n\t#include \"portmacro.h\"\n#endif\n\n#if portBYTE_ALIGNMENT == 32\n\t#define portBYTE_ALIGNMENT_MASK ( 0x001f )\n#endif\n\n#if portBYTE_ALIGNMENT == 16\n\t#define portBYTE_ALIGNMENT_MASK ( 0x000f )\n#endif\n\n#if portBYTE_ALIGNMENT == 8\n\t#define portBYTE_ALIGNMENT_MASK ( 0x0007 )\n#endif\n\n#if portBYTE_ALIGNMENT == 4\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0003 )\n#endif\n\n#if portBYTE_ALIGNMENT == 2\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0001 )\n#endif\n\n#if portBYTE_ALIGNMENT == 1\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0000 )\n#endif\n\n#ifndef portBYTE_ALIGNMENT_MASK\n\t#error \"Invalid portBYTE_ALIGNMENT definition\"\n#endif\n\n#ifndef portNUM_CONFIGURABLE_REGIONS\n\t#define portNUM_CONFIGURABLE_REGIONS 1\n#endif\n\n#ifndef portHAS_STACK_OVERFLOW_CHECKING\n\t#define portHAS_STACK_OVERFLOW_CHECKING 0\n#endif\n\n#ifndef portARCH_NAME\n\t#define portARCH_NAME NULL\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"mpu_wrappers.h\"\n\n/*\n * Setup the stack of a new task so it is ready to be placed under the\n * scheduler control.  The registers have to be placed on the stack in\n * the order that the port expects to find them.\n *\n */\n#if( portUSING_MPU_WRAPPERS == 1 )\n\t#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n\t\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\n\t#else\n\t\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\n\t#endif\n#else\n\t#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n\t\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;\n\t#else\n\t\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;\n\t#endif\n#endif\n\n/* Used by heap_5.c. */\ntypedef struct HeapRegion\n{\n\tuint8_t *pucStartAddress;\n\tsize_t xSizeInBytes;\n} HeapRegion_t;\n\n/*\n * Used to define multiple heap regions for use by heap_5.c.  This function\n * must be called before any calls to pvPortMalloc() - not creating a task,\n * queue, semaphore, mutex, software timer, event group, etc. will result in\n * pvPortMalloc being called.\n *\n * pxHeapRegions passes in an array of HeapRegion_t structures - each of which\n * defines a region of memory that can be used as the heap.  The array is\n * terminated by a HeapRegions_t structure that has a size of 0.  The region\n * with the lowest start address must appear first in the array.\n */\nvoid vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;\n\n\n/*\n * Map to the memory management routines required for the port.\n */\nvoid *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;\nvoid vPortFree( void *pv ) PRIVILEGED_FUNCTION;\nvoid vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;\nsize_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;\nsize_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Setup the hardware ready for the scheduler to take control.  This generally\n * sets up a tick interrupt and sets timers for the correct tick frequency.\n */\nBaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so\n * the hardware is left in its original condition after the scheduler stops\n * executing.\n */\nvoid vPortEndScheduler( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The structures and methods of manipulating the MPU are contained within the\n * port layer.\n *\n * Fills the xMPUSettings structure with the memory region information\n * contained in xRegions.\n */\n#if( portUSING_MPU_WRAPPERS == 1 )\n\tstruct xMEMORY_REGION;\n\tvoid vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* PORTABLE_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/projdefs.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef PROJDEFS_H\n#define PROJDEFS_H\n\n/*\n * Defines the prototype to which task functions must conform.  Defined in this\n * file to ensure the type is known before portable.h is included.\n */\ntypedef void (*TaskFunction_t)( void * );\n\n/* Converts a time in milliseconds to a time in ticks.  This macro can be\noverridden by a macro of the same name defined in FreeRTOSConfig.h in case the\ndefinition here is not suitable for your application. */\n#ifndef pdMS_TO_TICKS\n\t#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )\n#endif\n\n#define pdFALSE\t\t\t( ( BaseType_t ) 0 )\n#define pdTRUE\t\t\t( ( BaseType_t ) 1 )\n\n#define pdPASS\t\t\t( pdTRUE )\n#define pdFAIL\t\t\t( pdFALSE )\n#define errQUEUE_EMPTY\t( ( BaseType_t ) 0 )\n#define errQUEUE_FULL\t( ( BaseType_t ) 0 )\n\n/* FreeRTOS error definitions. */\n#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY\t( -1 )\n#define errQUEUE_BLOCKED\t\t\t\t\t\t( -4 )\n#define errQUEUE_YIELD\t\t\t\t\t\t\t( -5 )\n\n/* Macros used for basic data corruption checks. */\n#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES\n\t#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0\n#endif\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\t#define pdINTEGRITY_CHECK_VALUE 0x5a5a\n#else\n\t#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL\n#endif\n\n/* The following errno values are used by FreeRTOS+ components, not FreeRTOS\nitself. */\n#define pdFREERTOS_ERRNO_NONE\t\t\t0\t/* No errors */\n#define\tpdFREERTOS_ERRNO_ENOENT\t\t\t2\t/* No such file or directory */\n#define\tpdFREERTOS_ERRNO_EINTR\t\t\t4\t/* Interrupted system call */\n#define\tpdFREERTOS_ERRNO_EIO\t\t\t5\t/* I/O error */\n#define\tpdFREERTOS_ERRNO_ENXIO\t\t\t6\t/* No such device or address */\n#define\tpdFREERTOS_ERRNO_EBADF\t\t\t9\t/* Bad file number */\n#define\tpdFREERTOS_ERRNO_EAGAIN\t\t\t11\t/* No more processes */\n#define\tpdFREERTOS_ERRNO_EWOULDBLOCK\t11\t/* Operation would block */\n#define\tpdFREERTOS_ERRNO_ENOMEM\t\t\t12\t/* Not enough memory */\n#define\tpdFREERTOS_ERRNO_EACCES\t\t\t13\t/* Permission denied */\n#define\tpdFREERTOS_ERRNO_EFAULT\t\t\t14\t/* Bad address */\n#define\tpdFREERTOS_ERRNO_EBUSY\t\t\t16\t/* Mount device busy */\n#define\tpdFREERTOS_ERRNO_EEXIST\t\t\t17\t/* File exists */\n#define\tpdFREERTOS_ERRNO_EXDEV\t\t\t18\t/* Cross-device link */\n#define\tpdFREERTOS_ERRNO_ENODEV\t\t\t19\t/* No such device */\n#define\tpdFREERTOS_ERRNO_ENOTDIR\t\t20\t/* Not a directory */\n#define\tpdFREERTOS_ERRNO_EISDIR\t\t\t21\t/* Is a directory */\n#define\tpdFREERTOS_ERRNO_EINVAL\t\t\t22\t/* Invalid argument */\n#define\tpdFREERTOS_ERRNO_ENOSPC\t\t\t28\t/* No space left on device */\n#define\tpdFREERTOS_ERRNO_ESPIPE\t\t\t29\t/* Illegal seek */\n#define\tpdFREERTOS_ERRNO_EROFS\t\t\t30\t/* Read only file system */\n#define\tpdFREERTOS_ERRNO_EUNATCH\t\t42\t/* Protocol driver not attached */\n#define\tpdFREERTOS_ERRNO_EBADE\t\t\t50\t/* Invalid exchange */\n#define\tpdFREERTOS_ERRNO_EFTYPE\t\t\t79\t/* Inappropriate file type or format */\n#define\tpdFREERTOS_ERRNO_ENMFILE\t\t89\t/* No more files */\n#define\tpdFREERTOS_ERRNO_ENOTEMPTY\t\t90\t/* Directory not empty */\n#define\tpdFREERTOS_ERRNO_ENAMETOOLONG \t91\t/* File or path name too long */\n#define\tpdFREERTOS_ERRNO_EOPNOTSUPP\t\t95\t/* Operation not supported on transport endpoint */\n#define\tpdFREERTOS_ERRNO_ENOBUFS\t\t105\t/* No buffer space available */\n#define\tpdFREERTOS_ERRNO_ENOPROTOOPT\t109\t/* Protocol not available */\n#define\tpdFREERTOS_ERRNO_EADDRINUSE\t\t112\t/* Address already in use */\n#define\tpdFREERTOS_ERRNO_ETIMEDOUT\t\t116\t/* Connection timed out */\n#define\tpdFREERTOS_ERRNO_EINPROGRESS\t119\t/* Connection already in progress */\n#define\tpdFREERTOS_ERRNO_EALREADY\t\t120\t/* Socket already connected */\n#define\tpdFREERTOS_ERRNO_EADDRNOTAVAIL \t125\t/* Address not available */\n#define\tpdFREERTOS_ERRNO_EISCONN\t\t127\t/* Socket is already connected */\n#define\tpdFREERTOS_ERRNO_ENOTCONN\t\t128\t/* Socket is not connected */\n#define\tpdFREERTOS_ERRNO_ENOMEDIUM\t\t135\t/* No medium inserted */\n#define\tpdFREERTOS_ERRNO_EILSEQ\t\t\t138\t/* An invalid UTF-16 sequence was encountered. */\n#define\tpdFREERTOS_ERRNO_ECANCELED\t\t140\t/* Operation canceled. */\n\n/* The following endian values are used by FreeRTOS+ components, not FreeRTOS\nitself. */\n#define pdFREERTOS_LITTLE_ENDIAN\t\t0\n#define pdFREERTOS_BIG_ENDIAN\t\t\t1\n\n/* Re-defining endian values for generic naming. */\n#define pdLITTLE_ENDIAN\t\t\t\t\tpdFREERTOS_LITTLE_ENDIAN\n#define pdBIG_ENDIAN\t\t\t\t\tpdFREERTOS_BIG_ENDIAN\n\n\n#endif /* PROJDEFS_H */\n\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/queue.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#ifndef QUEUE_H\n#define QUEUE_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include queue.h\"\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"task.h\"\n\n/**\n * Type by which queues are referenced.  For example, a call to xQueueCreate()\n * returns an QueueHandle_t variable that can then be used as a parameter to\n * xQueueSend(), xQueueReceive(), etc.\n */\nstruct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */\ntypedef struct QueueDefinition * QueueHandle_t;\n\n/**\n * Type by which queue sets are referenced.  For example, a call to\n * xQueueCreateSet() returns an xQueueSet variable that can then be used as a\n * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.\n */\ntypedef struct QueueDefinition * QueueSetHandle_t;\n\n/**\n * Queue sets can contain both queues and semaphores, so the\n * QueueSetMemberHandle_t is defined as a type to be used where a parameter or\n * return value can be either an QueueHandle_t or an SemaphoreHandle_t.\n */\ntypedef struct QueueDefinition * QueueSetMemberHandle_t;\n\n/* For internal use only. */\n#define\tqueueSEND_TO_BACK\t\t( ( BaseType_t ) 0 )\n#define\tqueueSEND_TO_FRONT\t\t( ( BaseType_t ) 1 )\n#define queueOVERWRITE\t\t\t( ( BaseType_t ) 2 )\n\n/* For internal use only.  These definitions *must* match those in queue.c. */\n#define queueQUEUE_TYPE_BASE\t\t\t\t( ( uint8_t ) 0U )\n#define queueQUEUE_TYPE_SET\t\t\t\t\t( ( uint8_t ) 0U )\n#define queueQUEUE_TYPE_MUTEX \t\t\t\t( ( uint8_t ) 1U )\n#define queueQUEUE_TYPE_COUNTING_SEMAPHORE\t( ( uint8_t ) 2U )\n#define queueQUEUE_TYPE_BINARY_SEMAPHORE\t( ( uint8_t ) 3U )\n#define queueQUEUE_TYPE_RECURSIVE_MUTEX\t\t( ( uint8_t ) 4U )\n\n/**\n * queue. h\n * <pre>\n QueueHandle_t xQueueCreate(\n\t\t\t\t\t\t\t  UBaseType_t uxQueueLength,\n\t\t\t\t\t\t\t  UBaseType_t uxItemSize\n\t\t\t\t\t\t  );\n * </pre>\n *\n * Creates a new queue instance, and returns a handle by which the new queue\n * can be referenced.\n *\n * Internally, within the FreeRTOS implementation, queues use two blocks of\n * memory.  The first block is used to hold the queue's data structures.  The\n * second block is used to hold items placed into the queue.  If a queue is\n * created using xQueueCreate() then both blocks of memory are automatically\n * dynamically allocated inside the xQueueCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a queue is created using\n * xQueueCreateStatic() then the application writer must provide the memory that\n * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to\n * be created without using any dynamic memory allocation.\n *\n * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html\n *\n * @param uxQueueLength The maximum number of items that the queue can contain.\n *\n * @param uxItemSize The number of bytes each item in the queue will require.\n * Items are queued by copy, not by reference, so this is the number of bytes\n * that will be copied for each posted item.  Each item on the queue must be\n * the same size.\n *\n * @return If the queue is successfully create then a handle to the newly\n * created queue is returned.  If the queue cannot be created then 0 is\n * returned.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n };\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\tif( xQueue1 == 0 )\n\t{\n\t\t// Queue was not created and must not be used.\n\t}\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\tif( xQueue2 == 0 )\n\t{\n\t\t// Queue was not created and must not be used.\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueCreate xQueueCreate\n * \\ingroup QueueManagement\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )\n#endif\n\n/**\n * queue. h\n * <pre>\n QueueHandle_t xQueueCreateStatic(\n\t\t\t\t\t\t\t  UBaseType_t uxQueueLength,\n\t\t\t\t\t\t\t  UBaseType_t uxItemSize,\n\t\t\t\t\t\t\t  uint8_t *pucQueueStorageBuffer,\n\t\t\t\t\t\t\t  StaticQueue_t *pxQueueBuffer\n\t\t\t\t\t\t  );\n * </pre>\n *\n * Creates a new queue instance, and returns a handle by which the new queue\n * can be referenced.\n *\n * Internally, within the FreeRTOS implementation, queues use two blocks of\n * memory.  The first block is used to hold the queue's data structures.  The\n * second block is used to hold items placed into the queue.  If a queue is\n * created using xQueueCreate() then both blocks of memory are automatically\n * dynamically allocated inside the xQueueCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a queue is created using\n * xQueueCreateStatic() then the application writer must provide the memory that\n * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to\n * be created without using any dynamic memory allocation.\n *\n * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html\n *\n * @param uxQueueLength The maximum number of items that the queue can contain.\n *\n * @param uxItemSize The number of bytes each item in the queue will require.\n * Items are queued by copy, not by reference, so this is the number of bytes\n * that will be copied for each posted item.  Each item on the queue must be\n * the same size.\n *\n * @param pucQueueStorageBuffer If uxItemSize is not zero then\n * pucQueueStorageBuffer must point to a uint8_t array that is at least large\n * enough to hold the maximum number of items that can be in the queue at any\n * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is\n * zero then pucQueueStorageBuffer can be NULL.\n *\n * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which\n * will be used to hold the queue's data structure.\n *\n * @return If the queue is created then a handle to the created queue is\n * returned.  If pxQueueBuffer is NULL then NULL is returned.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n };\n\n #define QUEUE_LENGTH 10\n #define ITEM_SIZE sizeof( uint32_t )\n\n // xQueueBuffer will hold the queue structure.\n StaticQueue_t xQueueBuffer;\n\n // ucQueueStorage will hold the items posted to the queue.  Must be at least\n // [(queue length) * ( queue item size)] bytes long.\n uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.\n\t\t\t\t\t\t\tITEM_SIZE\t  // The size of each item in the queue\n\t\t\t\t\t\t\t&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.\n\t\t\t\t\t\t\t&xQueueBuffer ); // The buffer that will hold the queue structure.\n\n\t// The queue is guaranteed to be created successfully as no dynamic memory\n\t// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueCreateStatic xQueueCreateStatic\n * \\ingroup QueueManagement\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendToToFront(\n\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\n\t\t\t\t\t\t\t\t   const void\t\t*pvItemToQueue,\n\t\t\t\t\t\t\t\t   TickType_t\t\txTicksToWait\n\t\t\t\t\t\t\t   );\n * </pre>\n *\n * Post an item to the front of a queue.  The item is queued by copy, not by\n * reference.  This function must not be called from an interrupt service\n * routine.  See xQueueSendFromISR () for an alternative which may be used\n * in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n uint32_t ulVar = 10UL;\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\n\t// ...\n\n\tif( xQueue1 != 0 )\n\t{\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\n\t\t// available if necessary.\n\t\tif( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n\t\t{\n\t\t\t// Failed to post the message, even after 10 ticks.\n\t\t}\n\t}\n\n\tif( xQueue2 != 0 )\n\t{\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t\t// queue is already full.\n\t\tpxMessage = & xMessage;\n\t\txQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendToBack(\n\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\n\t\t\t\t\t\t\t\t   const void\t\t*pvItemToQueue,\n\t\t\t\t\t\t\t\t   TickType_t\t\txTicksToWait\n\t\t\t\t\t\t\t   );\n * </pre>\n *\n * This is a macro that calls xQueueGenericSend().\n *\n * Post an item to the back of a queue.  The item is queued by copy, not by\n * reference.  This function must not be called from an interrupt service\n * routine.  See xQueueSendFromISR () for an alternative which may be used\n * in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the queue\n * is full.  The  time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n uint32_t ulVar = 10UL;\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\n\t// ...\n\n\tif( xQueue1 != 0 )\n\t{\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\n\t\t// available if necessary.\n\t\tif( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n\t\t{\n\t\t\t// Failed to post the message, even after 10 ticks.\n\t\t}\n\t}\n\n\tif( xQueue2 != 0 )\n\t{\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t\t// queue is already full.\n\t\tpxMessage = & xMessage;\n\t\txQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSend(\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\n\t\t\t\t\t\t\t  const void * pvItemToQueue,\n\t\t\t\t\t\t\t  TickType_t xTicksToWait\n\t\t\t\t\t\t );\n * </pre>\n *\n * This is a macro that calls xQueueGenericSend().  It is included for\n * backward compatibility with versions of FreeRTOS.org that did not\n * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is\n * equivalent to xQueueSendToBack().\n *\n * Post an item on a queue.  The item is queued by copy, not by reference.\n * This function must not be called from an interrupt service routine.\n * See xQueueSendFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n uint32_t ulVar = 10UL;\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\n\t// ...\n\n\tif( xQueue1 != 0 )\n\t{\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\n\t\t// available if necessary.\n\t\tif( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n\t\t{\n\t\t\t// Failed to post the message, even after 10 ticks.\n\t\t}\n\t}\n\n\tif( xQueue2 != 0 )\n\t{\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t\t// queue is already full.\n\t\tpxMessage = & xMessage;\n\t\txQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueOverwrite(\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\n\t\t\t\t\t\t\t  const void * pvItemToQueue\n\t\t\t\t\t\t );\n * </pre>\n *\n * Only for use with queues that have a length of one - so the queue is either\n * empty or full.\n *\n * Post an item on a queue.  If the queue is already full then overwrite the\n * value held in the queue.  The item is queued by copy, not by reference.\n *\n * This function must not be called from an interrupt service routine.\n * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle of the queue to which the data is being sent.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and\n * therefore has the same return values as xQueueSendToFront().  However, pdPASS\n * is the only value that can be returned because xQueueOverwrite() will write\n * to the queue even when the queue is already full.\n *\n * Example usage:\n   <pre>\n\n void vFunction( void *pvParameters )\n {\n QueueHandle_t xQueue;\n uint32_t ulVarToSend, ulValReceived;\n\n\t// Create a queue to hold one uint32_t value.  It is strongly\n\t// recommended *not* to use xQueueOverwrite() on queues that can\n\t// contain more than one value, and doing so will trigger an assertion\n\t// if configASSERT() is defined.\n\txQueue = xQueueCreate( 1, sizeof( uint32_t ) );\n\n\t// Write the value 10 to the queue using xQueueOverwrite().\n\tulVarToSend = 10;\n\txQueueOverwrite( xQueue, &ulVarToSend );\n\n\t// Peeking the queue should now return 10, but leave the value 10 in\n\t// the queue.  A block time of zero is used as it is known that the\n\t// queue holds a value.\n\tulValReceived = 0;\n\txQueuePeek( xQueue, &ulValReceived, 0 );\n\n\tif( ulValReceived != 10 )\n\t{\n\t\t// Error unless the item was removed by a different task.\n\t}\n\n\t// The queue is still full.  Use xQueueOverwrite() to overwrite the\n\t// value held in the queue with 100.\n\tulVarToSend = 100;\n\txQueueOverwrite( xQueue, &ulVarToSend );\n\n\t// This time read from the queue, leaving the queue empty once more.\n\t// A block time of 0 is used again.\n\txQueueReceive( xQueue, &ulValReceived, 0 );\n\n\t// The value read should be the last value written, even though the\n\t// queue was already full when the value was written.\n\tif( ulValReceived != 100 )\n\t{\n\t\t// Error!\n\t}\n\n\t// ...\n}\n </pre>\n * \\defgroup xQueueOverwrite xQueueOverwrite\n * \\ingroup QueueManagement\n */\n#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )\n\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueGenericSend(\n\t\t\t\t\t\t\t\t\tQueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\tconst void * pvItemToQueue,\n\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait\n\t\t\t\t\t\t\t\t\tBaseType_t xCopyPosition\n\t\t\t\t\t\t\t\t);\n * </pre>\n *\n * It is preferred that the macros xQueueSend(), xQueueSendToFront() and\n * xQueueSendToBack() are used in place of calling this function directly.\n *\n * Post an item on a queue.  The item is queued by copy, not by reference.\n * This function must not be called from an interrupt service routine.\n * See xQueueSendFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\n * item at the back of the queue, or queueSEND_TO_FRONT to place the item\n * at the front of the queue (for high priority messages).\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n uint32_t ulVar = 10UL;\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\n\t// ...\n\n\tif( xQueue1 != 0 )\n\t{\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\n\t\t// available if necessary.\n\t\tif( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )\n\t\t{\n\t\t\t// Failed to post the message, even after 10 ticks.\n\t\t}\n\t}\n\n\tif( xQueue2 != 0 )\n\t{\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t\t// queue is already full.\n\t\tpxMessage = & xMessage;\n\t\txQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueuePeek(\n\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t void * const pvBuffer,\n\t\t\t\t\t\t\t TickType_t xTicksToWait\n\t\t\t\t\t\t );</pre>\n *\n * Receive an item from a queue without removing the item from the queue.\n * The item is received by copy so a buffer of adequate size must be\n * provided.  The number of bytes copied into the buffer was defined when\n * the queue was created.\n *\n * Successfully received items remain on the queue so will be returned again\n * by the next call, or a call to xQueueReceive().\n *\n * This macro must not be used in an interrupt service routine.  See\n * xQueuePeekFromISR() for an alternative that can be called from an interrupt\n * service routine.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for an item to receive should the queue be empty at the time\n * of the call.\t The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue\n * is empty.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n QueueHandle_t xQueue;\n\n // Task to create a queue and post a value.\n void vATask( void *pvParameters )\n {\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\tif( xQueue == 0 )\n\t{\n\t\t// Failed to create the queue.\n\t}\n\n\t// ...\n\n\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t// queue is already full.\n\tpxMessage = & xMessage;\n\txQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\n\t// ... Rest of task code.\n }\n\n // Task to peek the data from the queue.\n void vADifferentTask( void *pvParameters )\n {\n struct AMessage *pxRxedMessage;\n\n\tif( xQueue != 0 )\n\t{\n\t\t// Peek a message on the created queue.  Block for 10 ticks if a\n\t\t// message is not immediately available.\n\t\tif( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\n\t\t{\n\t\t\t// pcRxedMessage now points to the struct AMessage variable posted\n\t\t\t// by vATask, but the item still remains on the queue.\n\t\t}\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueuePeek xQueuePeek\n * \\ingroup QueueManagement\n */\nBaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueuePeekFromISR(\n\t\t\t\t\t\t\t\t\tQueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\tvoid *pvBuffer,\n\t\t\t\t\t\t\t\t);</pre>\n *\n * A version of xQueuePeek() that can be called from an interrupt service\n * routine (ISR).\n *\n * Receive an item from a queue without removing the item from the queue.\n * The item is received by copy so a buffer of adequate size must be\n * provided.  The number of bytes copied into the buffer was defined when\n * the queue was created.\n *\n * Successfully received items remain on the queue so will be returned again\n * by the next call, or a call to xQueueReceive().\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * \\defgroup xQueuePeekFromISR xQueuePeekFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueReceive(\n\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t void *pvBuffer,\n\t\t\t\t\t\t\t\t TickType_t xTicksToWait\n\t\t\t\t\t\t\t);</pre>\n *\n * Receive an item from a queue.  The item is received by copy so a buffer of\n * adequate size must be provided.  The number of bytes copied into the buffer\n * was defined when the queue was created.\n *\n * Successfully received items are removed from the queue.\n *\n * This function must not be used in an interrupt service routine.  See\n * xQueueReceiveFromISR for an alternative that can.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for an item to receive should the queue be empty at the time\n * of the call.\t xQueueReceive() will return immediately if xTicksToWait\n * is zero and the queue is empty.  The time is defined in tick periods so the\n * constant portTICK_PERIOD_MS should be used to convert to real time if this is\n * required.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n QueueHandle_t xQueue;\n\n // Task to create a queue and post a value.\n void vATask( void *pvParameters )\n {\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\tif( xQueue == 0 )\n\t{\n\t\t// Failed to create the queue.\n\t}\n\n\t// ...\n\n\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t// queue is already full.\n\tpxMessage = & xMessage;\n\txQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\n\t// ... Rest of task code.\n }\n\n // Task to receive from the queue.\n void vADifferentTask( void *pvParameters )\n {\n struct AMessage *pxRxedMessage;\n\n\tif( xQueue != 0 )\n\t{\n\t\t// Receive a message on the created queue.  Block for 10 ticks if a\n\t\t// message is not immediately available.\n\t\tif( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\n\t\t{\n\t\t\t// pcRxedMessage now points to the struct AMessage variable posted\n\t\t\t// by vATask.\n\t\t}\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueReceive xQueueReceive\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );</pre>\n *\n * Return the number of messages stored in a queue.\n *\n * @param xQueue A handle to the queue being queried.\n *\n * @return The number of messages available in the queue.\n *\n * \\defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting\n * \\ingroup QueueManagement\n */\nUBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );</pre>\n *\n * Return the number of free spaces available in a queue.  This is equal to the\n * number of items that can be sent to the queue before the queue becomes full\n * if no items are removed.\n *\n * @param xQueue A handle to the queue being queried.\n *\n * @return The number of spaces available in the queue.\n *\n * \\defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting\n * \\ingroup QueueManagement\n */\nUBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>void vQueueDelete( QueueHandle_t xQueue );</pre>\n *\n * Delete a queue - freeing all the memory allocated for storing of items\n * placed on the queue.\n *\n * @param xQueue A handle to the queue to be deleted.\n *\n * \\defgroup vQueueDelete vQueueDelete\n * \\ingroup QueueManagement\n */\nvoid vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendToFrontFromISR(\n\t\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\n\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\n\t\t\t\t\t\t\t\t\t  );\n </pre>\n *\n * This is a macro that calls xQueueGenericSendFromISR().\n *\n * Post an item to the front of a queue.  It is safe to use this macro from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n   <pre>\n void vBufferISR( void )\n {\n char cIn;\n BaseType_t xHigherPrioritTaskWoken;\n\n\t// We have not woken a task at the start of the ISR.\n\txHigherPriorityTaskWoken = pdFALSE;\n\n\t// Loop until the buffer is empty.\n\tdo\n\t{\n\t\t// Obtain a byte from the buffer.\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n\n\t\t// Post the byte.\n\t\txQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\n\n\t// Now the buffer is empty we can switch context if necessary.\n\tif( xHigherPriorityTaskWoken )\n\t{\n\t\ttaskYIELD ();\n\t}\n }\n </pre>\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )\n\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendToBackFromISR(\n\t\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\n\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\n\t\t\t\t\t\t\t\t\t  );\n </pre>\n *\n * This is a macro that calls xQueueGenericSendFromISR().\n *\n * Post an item to the back of a queue.  It is safe to use this macro from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n   <pre>\n void vBufferISR( void )\n {\n char cIn;\n BaseType_t xHigherPriorityTaskWoken;\n\n\t// We have not woken a task at the start of the ISR.\n\txHigherPriorityTaskWoken = pdFALSE;\n\n\t// Loop until the buffer is empty.\n\tdo\n\t{\n\t\t// Obtain a byte from the buffer.\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n\n\t\t// Post the byte.\n\t\txQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\n\n\t// Now the buffer is empty we can switch context if necessary.\n\tif( xHigherPriorityTaskWoken )\n\t{\n\t\ttaskYIELD ();\n\t}\n }\n </pre>\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueOverwriteFromISR(\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\n\t\t\t\t\t\t\t  const void * pvItemToQueue,\n\t\t\t\t\t\t\t  BaseType_t *pxHigherPriorityTaskWoken\n\t\t\t\t\t\t );\n * </pre>\n *\n * A version of xQueueOverwrite() that can be used in an interrupt service\n * routine (ISR).\n *\n * Only for use with queues that can hold a single item - so the queue is either\n * empty or full.\n *\n * Post an item on a queue.  If the queue is already full then overwrite the\n * value held in the queue.  The item is queued by copy, not by reference.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return xQueueOverwriteFromISR() is a macro that calls\n * xQueueGenericSendFromISR(), and therefore has the same return values as\n * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be\n * returned because xQueueOverwriteFromISR() will write to the queue even when\n * the queue is already full.\n *\n * Example usage:\n   <pre>\n\n QueueHandle_t xQueue;\n\n void vFunction( void *pvParameters )\n {\n \t// Create a queue to hold one uint32_t value.  It is strongly\n\t// recommended *not* to use xQueueOverwriteFromISR() on queues that can\n\t// contain more than one value, and doing so will trigger an assertion\n\t// if configASSERT() is defined.\n\txQueue = xQueueCreate( 1, sizeof( uint32_t ) );\n}\n\nvoid vAnInterruptHandler( void )\n{\n// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.\nBaseType_t xHigherPriorityTaskWoken = pdFALSE;\nuint32_t ulVarToSend, ulValReceived;\n\n\t// Write the value 10 to the queue using xQueueOverwriteFromISR().\n\tulVarToSend = 10;\n\txQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );\n\n\t// The queue is full, but calling xQueueOverwriteFromISR() again will still\n\t// pass because the value held in the queue will be overwritten with the\n\t// new value.\n\tulVarToSend = 100;\n\txQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );\n\n\t// Reading from the queue will now return 100.\n\n\t// ...\n\n\tif( xHigherPrioritytaskWoken == pdTRUE )\n\t{\n\t\t// Writing to the queue caused a task to unblock and the unblocked task\n\t\t// has a priority higher than or equal to the priority of the currently\n\t\t// executing task (the task this interrupt interrupted).  Perform a context\n\t\t// switch so this interrupt returns directly to the unblocked task.\n\t\tportYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.\n\t}\n}\n </pre>\n * \\defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendFromISR(\n\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\n\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\n\t\t\t\t\t\t\t\t);\n </pre>\n *\n * This is a macro that calls xQueueGenericSendFromISR().  It is included\n * for backward compatibility with versions of FreeRTOS.org that did not\n * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()\n * macros.\n *\n * Post an item to the back of a queue.  It is safe to use this function from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n   <pre>\n void vBufferISR( void )\n {\n char cIn;\n BaseType_t xHigherPriorityTaskWoken;\n\n\t// We have not woken a task at the start of the ISR.\n\txHigherPriorityTaskWoken = pdFALSE;\n\n\t// Loop until the buffer is empty.\n\tdo\n\t{\n\t\t// Obtain a byte from the buffer.\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n\n\t\t// Post the byte.\n\t\txQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\n\n\t// Now the buffer is empty we can switch context if necessary.\n\tif( xHigherPriorityTaskWoken )\n\t{\n\t\t// Actual macro used here is port specific.\n\t\tportYIELD_FROM_ISR ();\n\t}\n }\n </pre>\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueGenericSendFromISR(\n\t\t\t\t\t\t\t\t\t\t   QueueHandle_t\t\txQueue,\n\t\t\t\t\t\t\t\t\t\t   const\tvoid\t*pvItemToQueue,\n\t\t\t\t\t\t\t\t\t\t   BaseType_t\t*pxHigherPriorityTaskWoken,\n\t\t\t\t\t\t\t\t\t\t   BaseType_t\txCopyPosition\n\t\t\t\t\t\t\t\t\t   );\n </pre>\n *\n * It is preferred that the macros xQueueSendFromISR(),\n * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place\n * of calling this function directly.  xQueueGiveFromISR() is an\n * equivalent for use by semaphores that don't actually copy any data.\n *\n * Post an item on a queue.  It is safe to use this function from within an\n * interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\n * item at the back of the queue, or queueSEND_TO_FRONT to place the item\n * at the front of the queue (for high priority messages).\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n   <pre>\n void vBufferISR( void )\n {\n char cIn;\n BaseType_t xHigherPriorityTaskWokenByPost;\n\n\t// We have not woken a task at the start of the ISR.\n\txHigherPriorityTaskWokenByPost = pdFALSE;\n\n\t// Loop until the buffer is empty.\n\tdo\n\t{\n\t\t// Obtain a byte from the buffer.\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n\n\t\t// Post each byte.\n\t\txQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );\n\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\n\n\t// Now the buffer is empty we can switch context if necessary.  Note that the\n\t// name of the yield function required is port specific.\n\tif( xHigherPriorityTaskWokenByPost )\n\t{\n\t\ttaskYIELD_YIELD_FROM_ISR();\n\t}\n }\n </pre>\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueReceiveFromISR(\n\t\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\n\t\t\t\t\t\t\t\t\t   void\t*pvBuffer,\n\t\t\t\t\t\t\t\t\t   BaseType_t *pxTaskWoken\n\t\t\t\t\t\t\t\t   );\n * </pre>\n *\n * Receive an item from a queue.  It is safe to use this function from within an\n * interrupt service routine.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param pxTaskWoken A task may be blocked waiting for space to become\n * available on the queue.  If xQueueReceiveFromISR causes such a task to\n * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will\n * remain unchanged.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n   <pre>\n\n QueueHandle_t xQueue;\n\n // Function to create a queue and post some values.\n void vAFunction( void *pvParameters )\n {\n char cValueToPost;\n const TickType_t xTicksToWait = ( TickType_t )0xff;\n\n\t// Create a queue capable of containing 10 characters.\n\txQueue = xQueueCreate( 10, sizeof( char ) );\n\tif( xQueue == 0 )\n\t{\n\t\t// Failed to create the queue.\n\t}\n\n\t// ...\n\n\t// Post some characters that will be used within an ISR.  If the queue\n\t// is full then this task will block for xTicksToWait ticks.\n\tcValueToPost = 'a';\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n\tcValueToPost = 'b';\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n\n\t// ... keep posting characters ... this task may block when the queue\n\t// becomes full.\n\n\tcValueToPost = 'c';\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n }\n\n // ISR that outputs all the characters received on the queue.\n void vISR_Routine( void )\n {\n BaseType_t xTaskWokenByReceive = pdFALSE;\n char cRxedChar;\n\n\twhile( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )\n\t{\n\t\t// A character was received.  Output the character now.\n\t\tvOutputCharacter( cRxedChar );\n\n\t\t// If removing the character from the queue woke the task that was\n\t\t// posting onto the queue cTaskWokenByReceive will have been set to\n\t\t// pdTRUE.  No matter how many times this loop iterates only one\n\t\t// task will be woken.\n\t}\n\n\tif( cTaskWokenByPost != ( char ) pdFALSE;\n\t{\n\t\ttaskYIELD ();\n\t}\n }\n </pre>\n * \\defgroup xQueueReceiveFromISR xQueueReceiveFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/*\n * Utilities to query queues that are safe to use from an ISR.  These utilities\n * should be used only from witin an ISR, or within a critical section.\n */\nBaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nUBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * The functions defined above are for passing data to and from tasks.  The\n * functions below are the equivalents for passing data to and from\n * co-routines.\n *\n * These functions are called from the co-routine macro implementation and\n * should not be called directly from application code.  Instead use the macro\n * wrappers defined within croutine.h.\n */\nBaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );\nBaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );\nBaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );\nBaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );\n\n/*\n * For internal use only.  Use xSemaphoreCreateMutex(),\n * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling\n * these functions directly.\n */\nQueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nTaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;\nTaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Use xSemaphoreTakeMutexRecursive() or\n * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.\n */\nBaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;\n\n/*\n * Reset a queue back to its original empty state.  The return value is now\n * obsolete and is always set to pdPASS.\n */\n#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )\n\n/*\n * The registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add\n * a queue, semaphore or mutex handle to the registry if you want the handle\n * to be available to a kernel aware debugger.  If you are not using a kernel\n * aware debugger then this function can be ignored.\n *\n * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the\n * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0\n * within FreeRTOSConfig.h for the registry to be available.  Its value\n * does not effect the number of queues, semaphores and mutexes that can be\n * created - just the number that the registry can hold.\n *\n * @param xQueue The handle of the queue being added to the registry.  This\n * is the handle returned by a call to xQueueCreate().  Semaphore and mutex\n * handles can also be passed in here.\n *\n * @param pcName The name to be associated with the handle.  This is the\n * name that the kernel aware debugger will display.  The queue registry only\n * stores a pointer to the string - so the string must be persistent (global or\n * preferably in ROM/Flash), not on the stack.\n */\n#if( configQUEUE_REGISTRY_SIZE > 0 )\n\tvoid vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n#endif\n\n/*\n * The registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add\n * a queue, semaphore or mutex handle to the registry if you want the handle\n * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to\n * remove the queue, semaphore or mutex from the register.  If you are not using\n * a kernel aware debugger then this function can be ignored.\n *\n * @param xQueue The handle of the queue being removed from the registry.\n */\n#if( configQUEUE_REGISTRY_SIZE > 0 )\n\tvoid vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * The queue registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look\n * up and return the name of a queue in the queue registry from the queue's\n * handle.\n *\n * @param xQueue The handle of the queue the name of which will be returned.\n * @return If the queue is in the registry then a pointer to the name of the\n * queue is returned.  If the queue is not in the registry then NULL is\n * returned.\n */\n#if( configQUEUE_REGISTRY_SIZE > 0 )\n\tconst char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n#endif\n\n/*\n * Generic version of the function used to creaet a queue using dynamic memory\n * allocation.  This is called by other functions and macros that create other\n * RTOS objects that use the queue structure as their base.\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tQueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Generic version of the function used to creaet a queue using dynamic memory\n * allocation.  This is called by other functions and macros that create other\n * RTOS objects that use the queue structure as their base.\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tQueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Queue sets provide a mechanism to allow a task to block (pend) on a read\n * operation from multiple queues or semaphores simultaneously.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * A queue set must be explicitly created using a call to xQueueCreateSet()\n * before it can be used.  Once created, standard FreeRTOS queues and semaphores\n * can be added to the set using calls to xQueueAddToSet().\n * xQueueSelectFromSet() is then used to determine which, if any, of the queues\n * or semaphores contained in the set is in a state where a queue read or\n * semaphore take operation would be successful.\n *\n * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html\n * for reasons why queue sets are very rarely needed in practice as there are\n * simpler methods of blocking on multiple objects.\n *\n * Note 2:  Blocking on a queue set that contains a mutex will not cause the\n * mutex holder to inherit the priority of the blocked task.\n *\n * Note 3:  An additional 4 bytes of RAM is required for each space in a every\n * queue added to a queue set.  Therefore counting semaphores that have a high\n * maximum count value should not be added to a queue set.\n *\n * Note 4:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param uxEventQueueLength Queue sets store events that occur on\n * the queues and semaphores contained in the set.  uxEventQueueLength specifies\n * the maximum number of events that can be queued at once.  To be absolutely\n * certain that events are not lost uxEventQueueLength should be set to the\n * total sum of the length of the queues added to the set, where binary\n * semaphores and mutexes have a length of 1, and counting semaphores have a\n * length set by their maximum count value.  Examples:\n *  + If a queue set is to hold a queue of length 5, another queue of length 12,\n *    and a binary semaphore, then uxEventQueueLength should be set to\n *    (5 + 12 + 1), or 18.\n *  + If a queue set is to hold three binary semaphores then uxEventQueueLength\n *    should be set to (1 + 1 + 1 ), or 3.\n *  + If a queue set is to hold a counting semaphore that has a maximum count of\n *    5, and a counting semaphore that has a maximum count of 3, then\n *    uxEventQueueLength should be set to (5 + 3), or 8.\n *\n * @return If the queue set is created successfully then a handle to the created\n * queue set is returned.  Otherwise NULL is returned.\n */\nQueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;\n\n/*\n * Adds a queue or semaphore to a queue set that was previously created by a\n * call to xQueueCreateSet().\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * Note 1:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param xQueueOrSemaphore The handle of the queue or semaphore being added to\n * the queue set (cast to an QueueSetMemberHandle_t type).\n *\n * @param xQueueSet The handle of the queue set to which the queue or semaphore\n * is being added.\n *\n * @return If the queue or semaphore was successfully added to the queue set\n * then pdPASS is returned.  If the queue could not be successfully added to the\n * queue set because it is already a member of a different queue set then pdFAIL\n * is returned.\n */\nBaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/*\n * Removes a queue or semaphore from a queue set.  A queue or semaphore can only\n * be removed from a set if the queue or semaphore is empty.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * @param xQueueOrSemaphore The handle of the queue or semaphore being removed\n * from the queue set (cast to an QueueSetMemberHandle_t type).\n *\n * @param xQueueSet The handle of the queue set in which the queue or semaphore\n * is included.\n *\n * @return If the queue or semaphore was successfully removed from the queue set\n * then pdPASS is returned.  If the queue was not in the queue set, or the\n * queue (or semaphore) was not empty, then pdFAIL is returned.\n */\nBaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/*\n * xQueueSelectFromSet() selects from the members of a queue set a queue or\n * semaphore that either contains data (in the case of a queue) or is available\n * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively\n * allows a task to block (pend) on a read operation on all the queues and\n * semaphores in a queue set simultaneously.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html\n * for reasons why queue sets are very rarely needed in practice as there are\n * simpler methods of blocking on multiple objects.\n *\n * Note 2:  Blocking on a queue set that contains a mutex will not cause the\n * mutex holder to inherit the priority of the blocked task.\n *\n * Note 3:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param xQueueSet The queue set on which the task will (potentially) block.\n *\n * @param xTicksToWait The maximum time, in ticks, that the calling task will\n * remain in the Blocked state (with other tasks executing) to wait for a member\n * of the queue set to be ready for a successful queue read or semaphore take\n * operation.\n *\n * @return xQueueSelectFromSet() will return the handle of a queue (cast to\n * a QueueSetMemberHandle_t type) contained in the queue set that contains data,\n * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained\n * in the queue set that is available, or NULL if no such queue or semaphore\n * exists before before the specified block time expires.\n */\nQueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/*\n * A version of xQueueSelectFromSet() that can be used from an ISR.\n */\nQueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/* Not public API functions. */\nvoid vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;\nvoid vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;\nUBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nuint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* QUEUE_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/semphr.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef SEMAPHORE_H\n#define SEMAPHORE_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include semphr.h\"\n#endif\n\n#include \"queue.h\"\n\ntypedef QueueHandle_t SemaphoreHandle_t;\n\n#define semBINARY_SEMAPHORE_QUEUE_LENGTH\t( ( uint8_t ) 1U )\n#define semSEMAPHORE_QUEUE_ITEM_LENGTH\t\t( ( uint8_t ) 0U )\n#define semGIVE_BLOCK_TIME\t\t\t\t\t( ( TickType_t ) 0U )\n\n\n/**\n * semphr. h\n * <pre>vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )</pre>\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the\n * xSemaphoreCreateBinary() function.  Note that binary semaphores created using\n * the vSemaphoreCreateBinary() macro are created in a state such that the\n * first call to 'take' the semaphore would pass, whereas binary semaphores\n * created using xSemaphoreCreateBinary() are created in a state such that the\n * the semaphore must first be 'given' before it can be 'taken'.\n *\n * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.\n * The queue length is 1 as this is a binary semaphore.  The data size is 0\n * as we don't want to actually store any data - we just want to know if the\n * queue is empty or full.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().\n    // This is a macro so pass the variable in directly.\n    vSemaphoreCreateBinary( xSemaphore );\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define vSemaphoreCreateBinary( xSemaphore )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );\t\\\n\t\t\tif( ( xSemaphore ) != NULL )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xSemaphoreGive( ( xSemaphore ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateBinary( void )</pre>\n *\n * Creates a new binary semaphore instance, and returns a handle by which the\n * new semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, binary semaphores use a block\n * of memory, in which the semaphore structure is stored.  If a binary semaphore\n * is created using xSemaphoreCreateBinary() then the required memory is\n * automatically dynamically allocated inside the xSemaphoreCreateBinary()\n * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore\n * is created using xSemaphoreCreateBinaryStatic() then the application writer\n * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a\n * binary semaphore to be created without using any dynamic memory allocation.\n *\n * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this\n * xSemaphoreCreateBinary() function.  Note that binary semaphores created using\n * the vSemaphoreCreateBinary() macro are created in a state such that the\n * first call to 'take' the semaphore would pass, whereas binary semaphores\n * created using xSemaphoreCreateBinary() are created in a state such that the\n * the semaphore must first be 'given' before it can be 'taken'.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @return Handle to the created semaphore, or NULL if the memory required to\n * hold the semaphore's data structures could not be allocated.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().\n    // This is a macro so pass the variable in directly.\n    xSemaphore = xSemaphoreCreateBinary();\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )</pre>\n *\n * Creates a new binary semaphore instance, and returns a handle by which the\n * new semaphore can be referenced.\n *\n * NOTE: In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, binary semaphores use a block\n * of memory, in which the semaphore structure is stored.  If a binary semaphore\n * is created using xSemaphoreCreateBinary() then the required memory is\n * automatically dynamically allocated inside the xSemaphoreCreateBinary()\n * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore\n * is created using xSemaphoreCreateBinaryStatic() then the application writer\n * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a\n * binary semaphore to be created without using any dynamic memory allocation.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the semaphore's data structure, removing the\n * need for the memory to be allocated dynamically.\n *\n * @return If the semaphore is created then a handle to the created semaphore is\n * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n StaticSemaphore_t xSemaphoreBuffer;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().\n    // The semaphore's data structures will be placed in the xSemaphoreBuffer\n    // variable, the address of which is passed into the function.  The\n    // function's parameter is not NULL, so the function will not attempt any\n    // dynamic memory allocation, and therefore the function will not return\n    // return NULL.\n    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );\n\n    // Rest of task code goes here.\n }\n </pre>\n * \\defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * <pre>xSemaphoreTake(\n *                   SemaphoreHandle_t xSemaphore,\n *                   TickType_t xBlockTime\n *               )</pre>\n *\n * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\n * xSemaphoreCreateCounting().\n *\n * @param xSemaphore A handle to the semaphore being taken - obtained when\n * the semaphore was created.\n *\n * @param xBlockTime The time in ticks to wait for the semaphore to become\n * available.  The macro portTICK_PERIOD_MS can be used to convert this to a\n * real time.  A block time of zero can be used to poll the semaphore.  A block\n * time of portMAX_DELAY can be used to block indefinitely (provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).\n *\n * @return pdTRUE if the semaphore was obtained.  pdFALSE\n * if xBlockTime expired without the semaphore becoming available.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n\n // A task that creates a semaphore.\n void vATask( void * pvParameters )\n {\n    // Create the semaphore to guard a shared resource.\n    xSemaphore = xSemaphoreCreateBinary();\n }\n\n // A task that uses the semaphore.\n void vAnotherTask( void * pvParameters )\n {\n    // ... Do other things.\n\n    if( xSemaphore != NULL )\n    {\n        // See if we can obtain the semaphore.  If the semaphore is not available\n        // wait 10 ticks to see if it becomes free.\n        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )\n        {\n            // We were able to obtain the semaphore and can now access the\n            // shared resource.\n\n            // ...\n\n            // We have finished accessing the shared resource.  Release the\n            // semaphore.\n            xSemaphoreGive( xSemaphore );\n        }\n        else\n        {\n            // We could not obtain the semaphore and can therefore not access\n            // the shared resource safely.\n        }\n    }\n }\n </pre>\n * \\defgroup xSemaphoreTake xSemaphoreTake\n * \\ingroup Semaphores\n */\n#define xSemaphoreTake( xSemaphore, xBlockTime )\t\txQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )\n\n/**\n * semphr. h\n * xSemaphoreTakeRecursive(\n *                          SemaphoreHandle_t xMutex,\n *                          TickType_t xBlockTime\n *                        )\n *\n * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.\n * The mutex must have previously been created using a call to\n * xSemaphoreCreateRecursiveMutex();\n *\n * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\n * macro to be available.\n *\n * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * @param xMutex A handle to the mutex being obtained.  This is the\n * handle returned by xSemaphoreCreateRecursiveMutex();\n *\n * @param xBlockTime The time in ticks to wait for the semaphore to become\n * available.  The macro portTICK_PERIOD_MS can be used to convert this to a\n * real time.  A block time of zero can be used to poll the semaphore.  If\n * the task already owns the semaphore then xSemaphoreTakeRecursive() will\n * return immediately no matter what the value of xBlockTime.\n *\n * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime\n * expired without the semaphore becoming available.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xMutex = NULL;\n\n // A task that creates a mutex.\n void vATask( void * pvParameters )\n {\n    // Create the mutex to guard a shared resource.\n    xMutex = xSemaphoreCreateRecursiveMutex();\n }\n\n // A task that uses the mutex.\n void vAnotherTask( void * pvParameters )\n {\n    // ... Do other things.\n\n    if( xMutex != NULL )\n    {\n        // See if we can obtain the mutex.  If the mutex is not available\n        // wait 10 ticks to see if it becomes free.\n        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )\n        {\n            // We were able to obtain the mutex and can now access the\n            // shared resource.\n\n            // ...\n            // For some reason due to the nature of the code further calls to\n            // xSemaphoreTakeRecursive() are made on the same mutex.  In real\n            // code these would not be just sequential calls as this would make\n            // no sense.  Instead the calls are likely to be buried inside\n            // a more complex call structure.\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n\n            // The mutex has now been 'taken' three times, so will not be\n            // available to another task until it has also been given back\n            // three times.  Again it is unlikely that real code would have\n            // these calls sequentially, but instead buried in a more complex\n            // call structure.  This is just for illustrative purposes.\n            xSemaphoreGiveRecursive( xMutex );\n            xSemaphoreGiveRecursive( xMutex );\n            xSemaphoreGiveRecursive( xMutex );\n\n            // Now the mutex can be taken by other tasks.\n        }\n        else\n        {\n            // We could not obtain the mutex and can therefore not access\n            // the shared resource safely.\n        }\n    }\n }\n </pre>\n * \\defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive\n * \\ingroup Semaphores\n */\n#if( configUSE_RECURSIVE_MUTEXES == 1 )\n\t#define xSemaphoreTakeRecursive( xMutex, xBlockTime )\txQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )\n#endif\n\n/**\n * semphr. h\n * <pre>xSemaphoreGive( SemaphoreHandle_t xSemaphore )</pre>\n *\n * <i>Macro</i> to release a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\n * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().\n *\n * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for\n * an alternative which can be used from an ISR.\n *\n * This macro must also not be used on semaphores created using\n * xSemaphoreCreateRecursiveMutex().\n *\n * @param xSemaphore A handle to the semaphore being released.  This is the\n * handle returned when the semaphore was created.\n *\n * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.\n * Semaphores are implemented using queues.  An error can occur if there is\n * no space on the queue to post a message - indicating that the\n * semaphore was not first obtained correctly.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n\n void vATask( void * pvParameters )\n {\n    // Create the semaphore to guard a shared resource.\n    xSemaphore = vSemaphoreCreateBinary();\n\n    if( xSemaphore != NULL )\n    {\n        if( xSemaphoreGive( xSemaphore ) != pdTRUE )\n        {\n            // We would expect this call to fail because we cannot give\n            // a semaphore without first \"taking\" it!\n        }\n\n        // Obtain the semaphore - don't block if the semaphore is not\n        // immediately available.\n        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )\n        {\n            // We now have the semaphore and can access the shared resource.\n\n            // ...\n\n            // We have finished accessing the shared resource so can free the\n            // semaphore.\n            if( xSemaphoreGive( xSemaphore ) != pdTRUE )\n            {\n                // We would not expect this call to fail because we must have\n                // obtained the semaphore to get here.\n            }\n        }\n    }\n }\n </pre>\n * \\defgroup xSemaphoreGive xSemaphoreGive\n * \\ingroup Semaphores\n */\n#define xSemaphoreGive( xSemaphore )\t\txQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\n\n/**\n * semphr. h\n * <pre>xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )</pre>\n *\n * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.\n * The mutex must have previously been created using a call to\n * xSemaphoreCreateRecursiveMutex();\n *\n * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\n * macro to be available.\n *\n * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * @param xMutex A handle to the mutex being released, or 'given'.  This is the\n * handle returned by xSemaphoreCreateMutex();\n *\n * @return pdTRUE if the semaphore was given.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xMutex = NULL;\n\n // A task that creates a mutex.\n void vATask( void * pvParameters )\n {\n    // Create the mutex to guard a shared resource.\n    xMutex = xSemaphoreCreateRecursiveMutex();\n }\n\n // A task that uses the mutex.\n void vAnotherTask( void * pvParameters )\n {\n    // ... Do other things.\n\n    if( xMutex != NULL )\n    {\n        // See if we can obtain the mutex.  If the mutex is not available\n        // wait 10 ticks to see if it becomes free.\n        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )\n        {\n            // We were able to obtain the mutex and can now access the\n            // shared resource.\n\n            // ...\n            // For some reason due to the nature of the code further calls to\n\t\t\t// xSemaphoreTakeRecursive() are made on the same mutex.  In real\n\t\t\t// code these would not be just sequential calls as this would make\n\t\t\t// no sense.  Instead the calls are likely to be buried inside\n\t\t\t// a more complex call structure.\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n\n            // The mutex has now been 'taken' three times, so will not be\n\t\t\t// available to another task until it has also been given back\n\t\t\t// three times.  Again it is unlikely that real code would have\n\t\t\t// these calls sequentially, it would be more likely that the calls\n\t\t\t// to xSemaphoreGiveRecursive() would be called as a call stack\n\t\t\t// unwound.  This is just for demonstrative purposes.\n            xSemaphoreGiveRecursive( xMutex );\n\t\t\txSemaphoreGiveRecursive( xMutex );\n\t\t\txSemaphoreGiveRecursive( xMutex );\n\n\t\t\t// Now the mutex can be taken by other tasks.\n        }\n        else\n        {\n            // We could not obtain the mutex and can therefore not access\n            // the shared resource safely.\n        }\n    }\n }\n </pre>\n * \\defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive\n * \\ingroup Semaphores\n */\n#if( configUSE_RECURSIVE_MUTEXES == 1 )\n\t#define xSemaphoreGiveRecursive( xMutex )\txQueueGiveMutexRecursive( ( xMutex ) )\n#endif\n\n/**\n * semphr. h\n * <pre>\n xSemaphoreGiveFromISR(\n                          SemaphoreHandle_t xSemaphore,\n                          BaseType_t *pxHigherPriorityTaskWoken\n                      )</pre>\n *\n * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().\n *\n * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\n * must not be used with this macro.\n *\n * This macro can be used from an ISR.\n *\n * @param xSemaphore A handle to the semaphore being released.  This is the\n * handle returned when the semaphore was created.\n *\n * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.\n *\n * Example usage:\n <pre>\n \\#define LONG_TIME 0xffff\n \\#define TICKS_TO_WAIT\t10\n SemaphoreHandle_t xSemaphore = NULL;\n\n // Repetitive task.\n void vATask( void * pvParameters )\n {\n    for( ;; )\n    {\n        // We want this task to run every 10 ticks of a timer.  The semaphore\n        // was created before this task was started.\n\n        // Block waiting for the semaphore to become available.\n        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )\n        {\n            // It is time to execute.\n\n            // ...\n\n            // We have finished our task.  Return to the top of the loop where\n            // we will block on the semaphore until it is time to execute\n            // again.  Note when using the semaphore for synchronisation with an\n\t\t\t// ISR in this manner there is no need to 'give' the semaphore back.\n        }\n    }\n }\n\n // Timer ISR\n void vTimerISR( void * pvParameters )\n {\n static uint8_t ucLocalTickCount = 0;\n static BaseType_t xHigherPriorityTaskWoken;\n\n    // A timer tick has occurred.\n\n    // ... Do other time functions.\n\n    // Is it time for vATask () to run?\n\txHigherPriorityTaskWoken = pdFALSE;\n    ucLocalTickCount++;\n    if( ucLocalTickCount >= TICKS_TO_WAIT )\n    {\n        // Unblock the task by releasing the semaphore.\n        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );\n\n        // Reset the count so we release the semaphore again in 10 ticks time.\n        ucLocalTickCount = 0;\n    }\n\n    if( xHigherPriorityTaskWoken != pdFALSE )\n    {\n        // We can force a context switch here.  Context switching from an\n        // ISR uses port specific syntax.  Check the demo task for your port\n        // to find the syntax required.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR\n * \\ingroup Semaphores\n */\n#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )\txQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * semphr. h\n * <pre>\n xSemaphoreTakeFromISR(\n                          SemaphoreHandle_t xSemaphore,\n                          BaseType_t *pxHigherPriorityTaskWoken\n                      )</pre>\n *\n * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have\n * previously been created with a call to xSemaphoreCreateBinary() or\n * xSemaphoreCreateCounting().\n *\n * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\n * must not be used with this macro.\n *\n * This macro can be used from an ISR, however taking a semaphore from an ISR\n * is not a common operation.  It is likely to only be useful when taking a\n * counting semaphore when an interrupt is obtaining an object from a resource\n * pool (when the semaphore count indicates the number of resources available).\n *\n * @param xSemaphore A handle to the semaphore being taken.  This is the\n * handle returned when the semaphore was created.\n *\n * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the semaphore was successfully taken, otherwise\n * pdFALSE\n */\n#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )\txQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateMutex( void )</pre>\n *\n * Creates a new mutex type semaphore instance, and returns a handle by which\n * the new mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, mutex semaphores use a block\n * of memory, in which the mutex structure is stored.  If a mutex is created\n * using xSemaphoreCreateMutex() then the required memory is automatically\n * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see\n * http://www.freertos.org/a00111.html).  If a mutex is created using\n * xSemaphoreCreateMutexStatic() then the application writer must provided the\n * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created\n * without using any dynamic memory allocation.\n *\n * Mutexes created using this function can be accessed using the xSemaphoreTake()\n * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and\n * xSemaphoreGiveRecursive() macros must not be used.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @return If the mutex was successfully created then a handle to the created\n * semaphore is returned.  If there was not enough heap to allocate the mutex\n * data structures then NULL is returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\n    // This is a macro so pass the variable in directly.\n    xSemaphore = xSemaphoreCreateMutex();\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>\n *\n * Creates a new mutex type semaphore instance, and returns a handle by which\n * the new mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, mutex semaphores use a block\n * of memory, in which the mutex structure is stored.  If a mutex is created\n * using xSemaphoreCreateMutex() then the required memory is automatically\n * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see\n * http://www.freertos.org/a00111.html).  If a mutex is created using\n * xSemaphoreCreateMutexStatic() then the application writer must provided the\n * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created\n * without using any dynamic memory allocation.\n *\n * Mutexes created using this function can be accessed using the xSemaphoreTake()\n * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and\n * xSemaphoreGiveRecursive() macros must not be used.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,\n * which will be used to hold the mutex's data structure, removing the need for\n * the memory to be allocated dynamically.\n *\n * @return If the mutex was successfully created then a handle to the created\n * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n StaticSemaphore_t xMutexBuffer;\n\n void vATask( void * pvParameters )\n {\n    // A mutex cannot be used before it has been created.  xMutexBuffer is\n    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is\n    // attempted.\n    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );\n\n    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,\n    // so there is no need to check it.\n }\n </pre>\n * \\defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic\n * \\ingroup Semaphores\n */\n #if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )</pre>\n *\n * Creates a new recursive mutex type semaphore instance, and returns a handle\n * by which the new recursive mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, recursive mutexs use a block\n * of memory, in which the mutex structure is stored.  If a recursive mutex is\n * created using xSemaphoreCreateRecursiveMutex() then the required memory is\n * automatically dynamically allocated inside the\n * xSemaphoreCreateRecursiveMutex() function.  (see\n * http://www.freertos.org/a00111.html).  If a recursive mutex is created using\n * xSemaphoreCreateRecursiveMutexStatic() then the application writer must\n * provide the memory that will get used by the mutex.\n * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to\n * be created without using any dynamic memory allocation.\n *\n * Mutexes created using this macro can be accessed using the\n * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The\n * xSemaphoreTake() and xSemaphoreGive() macros must not be used.\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @return xSemaphore Handle to the created mutex semaphore.  Should be of type\n * SemaphoreHandle_t.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\n    // This is a macro so pass the variable in directly.\n    xSemaphore = xSemaphoreCreateRecursiveMutex();\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex\n * \\ingroup Semaphores\n */\n#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )\n\t#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>\n *\n * Creates a new recursive mutex type semaphore instance, and returns a handle\n * by which the new recursive mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, recursive mutexs use a block\n * of memory, in which the mutex structure is stored.  If a recursive mutex is\n * created using xSemaphoreCreateRecursiveMutex() then the required memory is\n * automatically dynamically allocated inside the\n * xSemaphoreCreateRecursiveMutex() function.  (see\n * http://www.freertos.org/a00111.html).  If a recursive mutex is created using\n * xSemaphoreCreateRecursiveMutexStatic() then the application writer must\n * provide the memory that will get used by the mutex.\n * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to\n * be created without using any dynamic memory allocation.\n *\n * Mutexes created using this macro can be accessed using the\n * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The\n * xSemaphoreTake() and xSemaphoreGive() macros must not be used.\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the recursive mutex's data structure,\n * removing the need for the memory to be allocated dynamically.\n *\n * @return If the recursive mutex was successfully created then a handle to the\n * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is\n * returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n StaticSemaphore_t xMutexBuffer;\n\n void vATask( void * pvParameters )\n {\n    // A recursive semaphore cannot be used before it is created.  Here a\n    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().\n    // The address of xMutexBuffer is passed into the function, and will hold\n    // the mutexes data structures - so no dynamic memory allocation will be\n    // attempted.\n    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );\n\n    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,\n    // so there is no need to check it.\n }\n </pre>\n * \\defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic\n * \\ingroup Semaphores\n */\n#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )\n\t#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )</pre>\n *\n * Creates a new counting semaphore instance, and returns a handle by which the\n * new counting semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a counting semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, counting semaphores use a\n * block of memory, in which the counting semaphore structure is stored.  If a\n * counting semaphore is created using xSemaphoreCreateCounting() then the\n * required memory is automatically dynamically allocated inside the\n * xSemaphoreCreateCounting() function.  (see\n * http://www.freertos.org/a00111.html).  If a counting semaphore is created\n * using xSemaphoreCreateCountingStatic() then the application writer can\n * instead optionally provide the memory that will get used by the counting\n * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting\n * semaphore to be created without using any dynamic memory allocation.\n *\n * Counting semaphores are typically used for two things:\n *\n * 1) Counting events.\n *\n *    In this usage scenario an event handler will 'give' a semaphore each time\n *    an event occurs (incrementing the semaphore count value), and a handler\n *    task will 'take' a semaphore each time it processes an event\n *    (decrementing the semaphore count value).  The count value is therefore\n *    the difference between the number of events that have occurred and the\n *    number that have been processed.  In this case it is desirable for the\n *    initial count value to be zero.\n *\n * 2) Resource management.\n *\n *    In this usage scenario the count value indicates the number of resources\n *    available.  To obtain control of a resource a task must first obtain a\n *    semaphore - decrementing the semaphore count value.  When the count value\n *    reaches zero there are no free resources.  When a task finishes with the\n *    resource it 'gives' the semaphore back - incrementing the semaphore count\n *    value.  In this case it is desirable for the initial count value to be\n *    equal to the maximum count value, indicating that all resources are free.\n *\n * @param uxMaxCount The maximum count value that can be reached.  When the\n *        semaphore reaches this value it can no longer be 'given'.\n *\n * @param uxInitialCount The count value assigned to the semaphore when it is\n *        created.\n *\n * @return Handle to the created semaphore.  Null if the semaphore could not be\n *         created.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n\n void vATask( void * pvParameters )\n {\n SemaphoreHandle_t xSemaphore = NULL;\n\n    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().\n    // The max value to which the semaphore can count should be 10, and the\n    // initial value assigned to the count should be 0.\n    xSemaphore = xSemaphoreCreateCounting( 10, 0 );\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )</pre>\n *\n * Creates a new counting semaphore instance, and returns a handle by which the\n * new counting semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a counting semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, counting semaphores use a\n * block of memory, in which the counting semaphore structure is stored.  If a\n * counting semaphore is created using xSemaphoreCreateCounting() then the\n * required memory is automatically dynamically allocated inside the\n * xSemaphoreCreateCounting() function.  (see\n * http://www.freertos.org/a00111.html).  If a counting semaphore is created\n * using xSemaphoreCreateCountingStatic() then the application writer must\n * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a\n * counting semaphore to be created without using any dynamic memory allocation.\n *\n * Counting semaphores are typically used for two things:\n *\n * 1) Counting events.\n *\n *    In this usage scenario an event handler will 'give' a semaphore each time\n *    an event occurs (incrementing the semaphore count value), and a handler\n *    task will 'take' a semaphore each time it processes an event\n *    (decrementing the semaphore count value).  The count value is therefore\n *    the difference between the number of events that have occurred and the\n *    number that have been processed.  In this case it is desirable for the\n *    initial count value to be zero.\n *\n * 2) Resource management.\n *\n *    In this usage scenario the count value indicates the number of resources\n *    available.  To obtain control of a resource a task must first obtain a\n *    semaphore - decrementing the semaphore count value.  When the count value\n *    reaches zero there are no free resources.  When a task finishes with the\n *    resource it 'gives' the semaphore back - incrementing the semaphore count\n *    value.  In this case it is desirable for the initial count value to be\n *    equal to the maximum count value, indicating that all resources are free.\n *\n * @param uxMaxCount The maximum count value that can be reached.  When the\n *        semaphore reaches this value it can no longer be 'given'.\n *\n * @param uxInitialCount The count value assigned to the semaphore when it is\n *        created.\n *\n * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the semaphore's data structure, removing the\n * need for the memory to be allocated dynamically.\n *\n * @return If the counting semaphore was successfully created then a handle to\n * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL\n * then NULL is returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n StaticSemaphore_t xSemaphoreBuffer;\n\n void vATask( void * pvParameters )\n {\n SemaphoreHandle_t xSemaphore = NULL;\n\n    // Counting semaphore cannot be used before they have been created.  Create\n    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max\n    // value to which the semaphore can count is 10, and the initial value\n    // assigned to the count will be 0.  The address of xSemaphoreBuffer is\n    // passed in and will be used to hold the semaphore structure, so no dynamic\n    // memory allocation will be used.\n    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );\n\n    // No memory allocation was attempted so xSemaphore cannot be NULL, so there\n    // is no need to check its value.\n }\n </pre>\n * \\defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * <pre>void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );</pre>\n *\n * Delete a semaphore.  This function must be used with care.  For example,\n * do not delete a mutex type semaphore if the mutex is held by a task.\n *\n * @param xSemaphore A handle to the semaphore to be deleted.\n *\n * \\defgroup vSemaphoreDelete vSemaphoreDelete\n * \\ingroup Semaphores\n */\n#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )\n\n/**\n * semphr.h\n * <pre>TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );</pre>\n *\n * If xMutex is indeed a mutex type semaphore, return the current mutex holder.\n * If xMutex is not a mutex type semaphore, or the mutex is available (not held\n * by a task), return NULL.\n *\n * Note: This is a good way of determining if the calling task is the mutex\n * holder, but not a good way of determining the identity of the mutex holder as\n * the holder may change between the function exiting and the returned value\n * being tested.\n */\n#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )\n\n/**\n * semphr.h\n * <pre>TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );</pre>\n *\n * If xMutex is indeed a mutex type semaphore, return the current mutex holder.\n * If xMutex is not a mutex type semaphore, or the mutex is available (not held\n * by a task), return NULL.\n *\n */\n#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )\n\n/**\n * semphr.h\n * <pre>UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );</pre>\n *\n * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns\n * its current count value.  If the semaphore is a binary semaphore then\n * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the\n * semaphore is not available.\n *\n */\n#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )\n\n#endif /* SEMAPHORE_H */\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/stack_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef STACK_MACROS_H\n#define STACK_MACROS_H\n\n/*\n * Call the stack overflow hook function if the stack of the task being swapped\n * out is currently overflowed, or looks like it might have overflowed in the\n * past.\n *\n * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check\n * the current stack state only - comparing the current top of stack value to\n * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1\n * will also cause the last few stack bytes to be checked to ensure the value\n * to which the bytes were set when the task was created have not been\n * overwritten.  Note this second test does not guarantee that an overflowed\n * stack will always be recognised.\n */\n\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n\t/* Only the current stack state is to be checked. */\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\n\t\tif( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n\t/* Only the current stack state is to be checked. */\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\n\t\tif( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tconst uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;\t\t\t\t\t\t\t\\\n\t\tconst uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( pulStack[ 0 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 1 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 2 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 3 ] != ulCheckValue ) )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tint8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tstatic const uint8_t ucExpectedStackBytes[] = {\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tpcEndOfStack -= sizeof( ucExpectedStackBytes );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Has the extremity of the task stack ever been written over? */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n/* Remove stack overflow macro if not being used. */\n#ifndef taskCHECK_FOR_STACK_OVERFLOW\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\n#endif\n\n\n\n#endif /* STACK_MACROS_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/stdint.readme",
    "content": "\n#ifndef FREERTOS_STDINT\n#define FREERTOS_STDINT\n\n/*******************************************************************************\n * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions\n * necessary to build the FreeRTOS code.  It is provided to allow FreeRTOS to be\n * built using compilers that do not provide their own stdint.h definition.\n *\n * To use this file:\n *\n *    1) Copy this file into the directory that contains your FreeRTOSConfig.h\n *       header file, as that directory will already be in the compilers include\n *       path.\n *\n *    2) Rename the copied file stdint.h.\n *\n */\n\ntypedef signed char int8_t;\ntypedef unsigned char uint8_t;\ntypedef short int16_t;\ntypedef unsigned short uint16_t;\ntypedef long int32_t;\ntypedef unsigned long uint32_t;\n\n#endif /* FREERTOS_STDINT */\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/stream_buffer.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * Stream buffers are used to send a continuous stream of data from one task or\n * interrupt to another.  Their implementation is light weight, making them\n * particularly suited for interrupt to task and core to core communication\n * scenarios.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferRead()) inside a critical section section and set the\n * receive block time to 0.\n *\n */\n\n#ifndef STREAM_BUFFER_H\n#define STREAM_BUFFER_H\n\n#if defined( __cplusplus )\nextern \"C\" {\n#endif\n\n/**\n * Type by which stream buffers are referenced.  For example, a call to\n * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can\n * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),\n * etc.\n */\nstruct StreamBufferDef_t;\ntypedef struct StreamBufferDef_t * StreamBufferHandle_t;\n\n\n/**\n * message_buffer.h\n *\n<pre>\nStreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );\n</pre>\n *\n * Creates a new stream buffer using dynamically allocated memory.  See\n * xStreamBufferCreateStatic() for a version that uses statically allocated\n * memory (memory that is allocated at compile time).\n *\n * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in\n * FreeRTOSConfig.h for xStreamBufferCreate() to be available.\n *\n * @param xBufferSizeBytes The total number of bytes the stream buffer will be\n * able to hold at any one time.\n *\n * @param xTriggerLevelBytes The number of bytes that must be in the stream\n * buffer before a task that is blocked on the stream buffer to wait for data is\n * moved out of the blocked state.  For example, if a task is blocked on a read\n * of an empty stream buffer that has a trigger level of 1 then the task will be\n * unblocked when a single byte is written to the buffer or the task's block\n * time expires.  As another example, if a task is blocked on a read of an empty\n * stream buffer that has a trigger level of 10 then the task will not be\n * unblocked until the stream buffer contains at least 10 bytes or the task's\n * block time expires.  If a reading task's block time expires before the\n * trigger level is reached then the task will still receive however many bytes\n * are actually available.  Setting a trigger level of 0 will result in a\n * trigger level of 1 being used.  It is not valid to specify a trigger level\n * that is greater than the buffer size.\n *\n * @return If NULL is returned, then the stream buffer cannot be created\n * because there is insufficient heap memory available for FreeRTOS to allocate\n * the stream buffer data structures and storage area.  A non-NULL value being\n * returned indicates that the stream buffer has been created successfully -\n * the returned value should be stored as the handle to the created stream\n * buffer.\n *\n * Example use:\n<pre>\n\nvoid vAFunction( void )\n{\nStreamBufferHandle_t xStreamBuffer;\nconst size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;\n\n    // Create a stream buffer that can hold 100 bytes.  The memory used to hold\n    // both the stream buffer structure and the data in the stream buffer is\n    // allocated dynamically.\n    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );\n\n    if( xStreamBuffer == NULL )\n    {\n        // There was not enough heap memory space available to create the\n        // stream buffer.\n    }\n    else\n    {\n        // The stream buffer was created successfully and can now be used.\n    }\n}\n</pre>\n * \\defgroup xStreamBufferCreate xStreamBufferCreate\n * \\ingroup StreamBufferManagement\n */\n#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )\n\n/**\n * stream_buffer.h\n *\n<pre>\nStreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,\n                                                size_t xTriggerLevelBytes,\n                                                uint8_t *pucStreamBufferStorageArea,\n                                                StaticStreamBuffer_t *pxStaticStreamBuffer );\n</pre>\n * Creates a new stream buffer using statically allocated memory.  See\n * xStreamBufferCreate() for a version that uses dynamically allocated memory.\n *\n * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for\n * xStreamBufferCreateStatic() to be available.\n *\n * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the\n * pucStreamBufferStorageArea parameter.\n *\n * @param xTriggerLevelBytes The number of bytes that must be in the stream\n * buffer before a task that is blocked on the stream buffer to wait for data is\n * moved out of the blocked state.  For example, if a task is blocked on a read\n * of an empty stream buffer that has a trigger level of 1 then the task will be\n * unblocked when a single byte is written to the buffer or the task's block\n * time expires.  As another example, if a task is blocked on a read of an empty\n * stream buffer that has a trigger level of 10 then the task will not be\n * unblocked until the stream buffer contains at least 10 bytes or the task's\n * block time expires.  If a reading task's block time expires before the\n * trigger level is reached then the task will still receive however many bytes\n * are actually available.  Setting a trigger level of 0 will result in a\n * trigger level of 1 being used.  It is not valid to specify a trigger level\n * that is greater than the buffer size.\n *\n * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at\n * least xBufferSizeBytes + 1 big.  This is the array to which streams are\n * copied when they are written to the stream buffer.\n *\n * @param pxStaticStreamBuffer Must point to a variable of type\n * StaticStreamBuffer_t, which will be used to hold the stream buffer's data\n * structure.\n *\n * @return If the stream buffer is created successfully then a handle to the\n * created stream buffer is returned. If either pucStreamBufferStorageArea or\n * pxStaticstreamBuffer are NULL then NULL is returned.\n *\n * Example use:\n<pre>\n\n// Used to dimension the array used to hold the streams.  The available space\n// will actually be one less than this, so 999.\n#define STORAGE_SIZE_BYTES 1000\n\n// Defines the memory that will actually hold the streams within the stream\n// buffer.\nstatic uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];\n\n// The variable used to hold the stream buffer structure.\nStaticStreamBuffer_t xStreamBufferStruct;\n\nvoid MyFunction( void )\n{\nStreamBufferHandle_t xStreamBuffer;\nconst size_t xTriggerLevel = 1;\n\n    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),\n                                               xTriggerLevel,\n                                               ucBufferStorage,\n                                               &xStreamBufferStruct );\n\n    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer\n    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to\n    // reference the created stream buffer in other stream buffer API calls.\n\n    // Other code that uses the stream buffer can go here.\n}\n\n</pre>\n * \\defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic\n * \\ingroup StreamBufferManagement\n */\n#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n                          const void *pvTxData,\n                          size_t xDataLengthBytes,\n                          TickType_t xTicksToWait );\n</pre>\n *\n * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferSend() to write to a stream buffer from a task.  Use\n * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt\n * service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer to which a stream is\n * being sent.\n *\n * @param pvTxData A pointer to the buffer that holds the bytes to be copied\n * into the stream buffer.\n *\n * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData\n * into the stream buffer.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for enough space to become available in the stream\n * buffer, should the stream buffer contain too little space to hold the\n * another xDataLengthBytes bytes.  The block time is specified in tick periods,\n * so the absolute time it represents is dependent on the tick frequency.  The\n * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds\n * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will\n * cause the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out\n * before it can write all xDataLengthBytes into the buffer it will still write\n * as many bytes as possible.  A task does not use any CPU time when it is in\n * the blocked state.\n *\n * @return The number of bytes written to the stream buffer.  If a task times\n * out before it can write all xDataLengthBytes into the buffer it will still\n * write as many bytes as possible.\n *\n * Example use:\n<pre>\nvoid vAFunction( StreamBufferHandle_t xStreamBuffer )\n{\nsize_t xBytesSent;\nuint8_t ucArrayToSend[] = { 0, 1, 2, 3 };\nchar *pcStringToSend = \"String to send\";\nconst TickType_t x100ms = pdMS_TO_TICKS( 100 );\n\n    // Send an array to the stream buffer, blocking for a maximum of 100ms to\n    // wait for enough space to be available in the stream buffer.\n    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );\n\n    if( xBytesSent != sizeof( ucArrayToSend ) )\n    {\n        // The call to xStreamBufferSend() times out before there was enough\n        // space in the buffer for the data to be written, but it did\n        // successfully write xBytesSent bytes.\n    }\n\n    // Send the string to the stream buffer.  Return immediately if there is not\n    // enough space in the buffer.\n    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );\n\n    if( xBytesSent != strlen( pcStringToSend ) )\n    {\n        // The entire string could not be added to the stream buffer because\n        // there was not enough free space in the buffer, but xBytesSent bytes\n        // were sent.  Could try again to send the remaining bytes.\n    }\n}\n</pre>\n * \\defgroup xStreamBufferSend xStreamBufferSend\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t  const void *pvTxData,\n\t\t\t\t\t\t  size_t xDataLengthBytes,\n\t\t\t\t\t\t  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n                                 const void *pvTxData,\n                                 size_t xDataLengthBytes,\n                                 BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * Interrupt safe version of the API function that sends a stream of bytes to\n * the stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferSend() to write to a stream buffer from a task.  Use\n * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt\n * service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer to which a stream is\n * being sent.\n *\n * @param pvTxData A pointer to the data that is to be copied into the stream\n * buffer.\n *\n * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData\n * into the stream buffer.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will\n * have a task blocked on it waiting for data.  Calling\n * xStreamBufferSendFromISR() can make data available, and so cause a task that\n * was waiting for data to leave the Blocked state.  If calling\n * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently executing task (the\n * task that was interrupted), then, internally, xStreamBufferSendFromISR()\n * will set *pxHigherPriorityTaskWoken to pdTRUE.  If\n * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  This will\n * ensure that the interrupt returns directly to the highest priority Ready\n * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it\n * is passed into the function.  See the example code below for an example.\n *\n * @return The number of bytes actually written to the stream buffer, which will\n * be less than xDataLengthBytes if the stream buffer didn't have enough free\n * space for all the bytes to be written.\n *\n * Example use:\n<pre>\n// A stream buffer that has already been created.\nStreamBufferHandle_t xStreamBuffer;\n\nvoid vAnInterruptServiceRoutine( void )\n{\nsize_t xBytesSent;\nchar *pcStringToSend = \"String to send\";\nBaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.\n\n    // Attempt to send the string to the stream buffer.\n    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,\n                                           ( void * ) pcStringToSend,\n                                           strlen( pcStringToSend ),\n                                           &xHigherPriorityTaskWoken );\n\n    if( xBytesSent != strlen( pcStringToSend ) )\n    {\n        // There was not enough free space in the stream buffer for the entire\n        // string to be written, ut xBytesSent bytes were written.\n    }\n\n    // If xHigherPriorityTaskWoken was set to pdTRUE inside\n    // xStreamBufferSendFromISR() then a task that has a priority above the\n    // priority of the currently executing task was unblocked and a context\n    // switch should be performed to ensure the ISR returns to the unblocked\n    // task.  In most FreeRTOS ports this is done by simply passing\n    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the\n    // variables value, and perform the context switch if necessary.  Check the\n    // documentation for the port in use for port specific instructions.\n    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n}\n</pre>\n * \\defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t\t const void *pvTxData,\n\t\t\t\t\t\t\t\t size_t xDataLengthBytes,\n\t\t\t\t\t\t\t\t BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n                             void *pvRxData,\n                             size_t xBufferLengthBytes,\n                             TickType_t xTicksToWait );\n</pre>\n *\n * Receives bytes from a stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use\n * xStreamBufferReceiveFromISR() to read from a stream buffer from an\n * interrupt service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer from which bytes are to\n * be received.\n *\n * @param pvRxData A pointer to the buffer into which the received bytes will be\n * copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the\n * pvRxData parameter.  This sets the maximum number of bytes to receive in one\n * call.  xStreamBufferReceive will return as many bytes as possible up to a\n * maximum set by xBufferLengthBytes.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for data to become available if the stream buffer is\n * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is\n * zero.  The block time is specified in tick periods, so the absolute time it\n * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can\n * be used to convert a time specified in milliseconds into a time specified in\n * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait\n * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1\n * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the\n * Blocked state.\n *\n * @return The number of bytes actually read from the stream buffer, which will\n * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed\n * out before xBufferLengthBytes were available.\n *\n * Example use:\n<pre>\nvoid vAFunction( StreamBuffer_t xStreamBuffer )\n{\nuint8_t ucRxData[ 20 ];\nsize_t xReceivedBytes;\nconst TickType_t xBlockTime = pdMS_TO_TICKS( 20 );\n\n    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.\n    // Wait in the Blocked state (so not using any CPU processing time) for a\n    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be\n    // available.\n    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,\n                                           ( void * ) ucRxData,\n                                           sizeof( ucRxData ),\n                                           xBlockTime );\n\n    if( xReceivedBytes > 0 )\n    {\n        // A ucRxData contains another xRecievedBytes bytes of data, which can\n        // be processed here....\n    }\n}\n</pre>\n * \\defgroup xStreamBufferReceive xStreamBufferReceive\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t void *pvRxData,\n\t\t\t\t\t\t\t size_t xBufferLengthBytes,\n\t\t\t\t\t\t\t TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n                                    void *pvRxData,\n                                    size_t xBufferLengthBytes,\n                                    BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * An interrupt safe version of the API function that receives bytes from a\n * stream buffer.\n *\n * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.\n * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an\n * interrupt service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer from which a stream\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received bytes are\n * copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the\n * pvRxData parameter.  This sets the maximum number of bytes to receive in one\n * call.  xStreamBufferReceive will return as many bytes as possible up to a\n * maximum set by xBufferLengthBytes.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will\n * have a task blocked on it waiting for space to become available.  Calling\n * xStreamBufferReceiveFromISR() can make space available, and so cause a task\n * that is waiting for space to leave the Blocked state.  If calling\n * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and\n * the unblocked task has a priority higher than the currently executing task\n * (the task that was interrupted), then, internally,\n * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.\n * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  That will\n * ensure the interrupt returns directly to the highest priority Ready state\n * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is\n * passed into the function.  See the code example below for an example.\n *\n * @return The number of bytes read from the stream buffer, if any.\n *\n * Example use:\n<pre>\n// A stream buffer that has already been created.\nStreamBuffer_t xStreamBuffer;\n\nvoid vAnInterruptServiceRoutine( void )\n{\nuint8_t ucRxData[ 20 ];\nsize_t xReceivedBytes;\nBaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.\n\n    // Receive the next stream from the stream buffer.\n    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,\n                                                  ( void * ) ucRxData,\n                                                  sizeof( ucRxData ),\n                                                  &xHigherPriorityTaskWoken );\n\n    if( xReceivedBytes > 0 )\n    {\n        // ucRxData contains xReceivedBytes read from the stream buffer.\n        // Process the stream here....\n    }\n\n    // If xHigherPriorityTaskWoken was set to pdTRUE inside\n    // xStreamBufferReceiveFromISR() then a task that has a priority above the\n    // priority of the currently executing task was unblocked and a context\n    // switch should be performed to ensure the ISR returns to the unblocked\n    // task.  In most FreeRTOS ports this is done by simply passing\n    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the\n    // variables value, and perform the context switch if necessary.  Check the\n    // documentation for the port in use for port specific instructions.\n    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n}\n</pre>\n * \\defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t\t\tvoid *pvRxData,\n\t\t\t\t\t\t\t\t\tsize_t xBufferLengthBytes,\n\t\t\t\t\t\t\t\t\tBaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nvoid vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Deletes a stream buffer that was previously created using a call to\n * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream\n * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),\n * then the allocated memory is freed.\n *\n * A stream buffer handle must not be used after the stream buffer has been\n * deleted.\n *\n * @param xStreamBuffer The handle of the stream buffer to be deleted.\n *\n * \\defgroup vStreamBufferDelete vStreamBufferDelete\n * \\ingroup StreamBufferManagement\n */\nvoid vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Queries a stream buffer to see if it is full.  A stream buffer is full if it\n * does not have any free space, and therefore cannot accept any more data.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return If the stream buffer is full then pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferIsFull xStreamBufferIsFull\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Queries a stream buffer to see if it is empty.  A stream buffer is empty if\n * it does not contain any data.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Resets a stream buffer to its initial, empty, state.  Any data that was in\n * the stream buffer is discarded.  A stream buffer can only be reset if there\n * are no tasks blocked waiting to either send to or receive from the stream\n * buffer.\n *\n * @param xStreamBuffer The handle of the stream buffer being reset.\n *\n * @return If the stream buffer is reset then pdPASS is returned.  If there was\n * a task blocked waiting to send to or read from the stream buffer then the\n * stream buffer is not reset and pdFAIL is returned.\n *\n * \\defgroup xStreamBufferReset xStreamBufferReset\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Queries a stream buffer to see how much free space it contains, which is\n * equal to the amount of data that can be sent to the stream buffer before it\n * is full.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return The number of bytes that can be written to the stream buffer before\n * the stream buffer would be full.\n *\n * \\defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Queries a stream buffer to see how much data it contains, which is equal to\n * the number of bytes that can be read from the stream buffer before the stream\n * buffer would be empty.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return The number of bytes that can be read from the stream buffer before\n * the stream buffer would be empty.\n *\n * \\defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );\n</pre>\n *\n * A stream buffer's trigger level is the number of bytes that must be in the\n * stream buffer before a task that is blocked on the stream buffer to\n * wait for data is moved out of the blocked state.  For example, if a task is\n * blocked on a read of an empty stream buffer that has a trigger level of 1\n * then the task will be unblocked when a single byte is written to the buffer\n * or the task's block time expires.  As another example, if a task is blocked\n * on a read of an empty stream buffer that has a trigger level of 10 then the\n * task will not be unblocked until the stream buffer contains at least 10 bytes\n * or the task's block time expires.  If a reading task's block time expires\n * before the trigger level is reached then the task will still receive however\n * many bytes are actually available.  Setting a trigger level of 0 will result\n * in a trigger level of 1 being used.  It is not valid to specify a trigger\n * level that is greater than the buffer size.\n *\n * A trigger level is set when the stream buffer is created, and can be modified\n * using xStreamBufferSetTriggerLevel().\n *\n * @param xStreamBuffer The handle of the stream buffer being updated.\n *\n * @param xTriggerLevel The new trigger level for the stream buffer.\n *\n * @return If xTriggerLevel was less than or equal to the stream buffer's length\n * then the trigger level will be updated and pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * For advanced users only.\n *\n * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is sent to a message buffer or stream buffer.  If there was a task that\n * was blocked on the message or stream buffer waiting for data to arrive then\n * the sbSEND_COMPLETED() macro sends a notification to the task to remove it\n * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same\n * thing.  It is provided to enable application writers to implement their own\n * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer to which data was\n * written.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xStreamBufferSendCompletedFromISR().  If calling\n * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * For advanced users only.\n *\n * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is read out of a message buffer or stream buffer.  If there was a task\n * that was blocked on the message or stream buffer waiting for data to arrive\n * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to\n * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()\n * does the same thing.  It is provided to enable application writers to\n * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT\n * ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer from which data was\n * read.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xStreamBufferReceiveCompletedFromISR().  If calling\n * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/* Functions below here are not part of the public API. */\nStreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;\n\nStreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t\t   size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t\t   BaseType_t xIsMessageBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\t\t   uint8_t * const pucStreamBufferStorageArea,\n\t\t\t\t\t\t\t\t\t\t\t\t\t   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;\n\nsize_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\tvoid vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;\n\tUBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\tuint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n#endif\n\n#if defined( __cplusplus )\n}\n#endif\n\n#endif\t/* !defined( STREAM_BUFFER_H ) */\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/task.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#ifndef INC_TASK_H\n#define INC_TASK_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include task.h\"\n#endif\n\n#include \"list.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * MACROS AND DEFINITIONS\n *----------------------------------------------------------*/\n\n#define tskKERNEL_VERSION_NUMBER \"V10.2.0\"\n#define tskKERNEL_VERSION_MAJOR 10\n#define tskKERNEL_VERSION_MINOR 2\n#define tskKERNEL_VERSION_BUILD 0\n\n/* MPU region parameters passed in ulParameters\n * of MemoryRegion_t struct. */\n#define tskMPU_REGION_READ_ONLY\t\t\t( 1UL << 0UL )\n#define tskMPU_REGION_READ_WRITE\t\t( 1UL << 1UL )\n#define tskMPU_REGION_EXECUTE_NEVER\t\t( 1UL << 2UL )\n#define tskMPU_REGION_NORMAL_MEMORY\t\t( 1UL << 3UL )\n#define tskMPU_REGION_DEVICE_MEMORY\t\t( 1UL << 4UL )\n\n/**\n * task. h\n *\n * Type by which tasks are referenced.  For example, a call to xTaskCreate\n * returns (via a pointer parameter) an TaskHandle_t variable that can then\n * be used as a parameter to vTaskDelete to delete the task.\n *\n * \\defgroup TaskHandle_t TaskHandle_t\n * \\ingroup Tasks\n */\nstruct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */\ntypedef struct tskTaskControlBlock* TaskHandle_t;\n\n/*\n * Defines the prototype to which the application task hook function must\n * conform.\n */\ntypedef BaseType_t (*TaskHookFunction_t)( void * );\n\n/* Task states returned by eTaskGetState. */\ntypedef enum\n{\n\teRunning = 0,\t/* A task is querying the state of itself, so must be running. */\n\teReady,\t\t\t/* The task being queried is in a read or pending ready list. */\n\teBlocked,\t\t/* The task being queried is in the Blocked state. */\n\teSuspended,\t\t/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */\n\teDeleted,\t\t/* The task being queried has been deleted, but its TCB has not yet been freed. */\n\teInvalid\t\t/* Used as an 'invalid state' value. */\n} eTaskState;\n\n/* Actions that can be performed when vTaskNotify() is called. */\ntypedef enum\n{\n\teNoAction = 0,\t\t\t\t/* Notify the task without updating its notify value. */\n\teSetBits,\t\t\t\t\t/* Set bits in the task's notification value. */\n\teIncrement,\t\t\t\t\t/* Increment the task's notification value. */\n\teSetValueWithOverwrite,\t\t/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */\n\teSetValueWithoutOverwrite\t/* Set the task's notification value if the previous value has been read by the task. */\n} eNotifyAction;\n\n/*\n * Used internally only.\n */\ntypedef struct xTIME_OUT\n{\n\tBaseType_t xOverflowCount;\n\tTickType_t xTimeOnEntering;\n} TimeOut_t;\n\n/*\n * Defines the memory ranges allocated to the task when an MPU is used.\n */\ntypedef struct xMEMORY_REGION\n{\n\tvoid *pvBaseAddress;\n\tuint32_t ulLengthInBytes;\n\tuint32_t ulParameters;\n} MemoryRegion_t;\n\n/*\n * Parameters required to create an MPU protected task.\n */\ntypedef struct xTASK_PARAMETERS\n{\n\tTaskFunction_t pvTaskCode;\n\tconst char * const pcName;\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\tconfigSTACK_DEPTH_TYPE usStackDepth;\n\tvoid *pvParameters;\n\tUBaseType_t uxPriority;\n\tStackType_t *puxStackBuffer;\n\tMemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];\n\t#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\t\tStaticTask_t * const pxTaskBuffer;\n\t#endif\n} TaskParameters_t;\n\n/* Used with the uxTaskGetSystemState() function to return the state of each task\nin the system. */\ntypedef struct xTASK_STATUS\n{\n\tTaskHandle_t xHandle;\t\t\t/* The handle of the task to which the rest of the information in the structure relates. */\n\tconst char *pcTaskName;\t\t\t/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\tUBaseType_t xTaskNumber;\t\t/* A number unique to the task. */\n\teTaskState eCurrentState;\t\t/* The state in which the task existed when the structure was populated. */\n\tUBaseType_t uxCurrentPriority;\t/* The priority at which the task was running (may be inherited) when the structure was populated. */\n\tUBaseType_t uxBasePriority;\t\t/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */\n\tuint32_t ulRunTimeCounter;\t\t/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */\n\tStackType_t *pxStackBase;\t\t/* Points to the lowest address of the task's stack area. */\n\tconfigSTACK_DEPTH_TYPE usStackHighWaterMark;\t/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */\n} TaskStatus_t;\n\n/* Possible return values for eTaskConfirmSleepModeStatus(). */\ntypedef enum\n{\n\teAbortSleep = 0,\t\t/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */\n\teStandardSleep,\t\t\t/* Enter a sleep mode that will not last any longer than the expected idle time. */\n\teNoTasksWaitingTimeout\t/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */\n} eSleepModeStatus;\n\n/**\n * Defines the priority used by the idle task.  This must not be modified.\n *\n * \\ingroup TaskUtils\n */\n#define tskIDLE_PRIORITY\t\t\t( ( UBaseType_t ) 0U )\n\n/**\n * task. h\n *\n * Macro for forcing a context switch.\n *\n * \\defgroup taskYIELD taskYIELD\n * \\ingroup SchedulerControl\n */\n#define taskYIELD()\t\t\t\t\tportYIELD()\n\n/**\n * task. h\n *\n * Macro to mark the start of a critical code region.  Preemptive context\n * switches cannot occur when in a critical region.\n *\n * NOTE: This may alter the stack (depending on the portable implementation)\n * so must be used with care!\n *\n * \\defgroup taskENTER_CRITICAL taskENTER_CRITICAL\n * \\ingroup SchedulerControl\n */\n#define taskENTER_CRITICAL()\t\tportENTER_CRITICAL()\n#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()\n\n/**\n * task. h\n *\n * Macro to mark the end of a critical code region.  Preemptive context\n * switches cannot occur when in a critical region.\n *\n * NOTE: This may alter the stack (depending on the portable implementation)\n * so must be used with care!\n *\n * \\defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL\n * \\ingroup SchedulerControl\n */\n#define taskEXIT_CRITICAL()\t\t\tportEXIT_CRITICAL()\n#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )\n/**\n * task. h\n *\n * Macro to disable all maskable interrupts.\n *\n * \\defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS\n * \\ingroup SchedulerControl\n */\n#define taskDISABLE_INTERRUPTS()\tportDISABLE_INTERRUPTS()\n\n/**\n * task. h\n *\n * Macro to enable microcontroller interrupts.\n *\n * \\defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS\n * \\ingroup SchedulerControl\n */\n#define taskENABLE_INTERRUPTS()\t\tportENABLE_INTERRUPTS()\n\n/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is\n0 to generate more optimal code when configASSERT() is defined as the constant\nis used in assert() statements. */\n#define taskSCHEDULER_SUSPENDED\t\t( ( BaseType_t ) 0 )\n#define taskSCHEDULER_NOT_STARTED\t( ( BaseType_t ) 1 )\n#define taskSCHEDULER_RUNNING\t\t( ( BaseType_t ) 2 )\n\n\n/*-----------------------------------------------------------\n * TASK CREATION API\n *----------------------------------------------------------*/\n\n/**\n * task. h\n *<pre>\n BaseType_t xTaskCreate(\n\t\t\t\t\t\t\t  TaskFunction_t pvTaskCode,\n\t\t\t\t\t\t\t  const char * const pcName,\n\t\t\t\t\t\t\t  configSTACK_DEPTH_TYPE usStackDepth,\n\t\t\t\t\t\t\t  void *pvParameters,\n\t\t\t\t\t\t\t  UBaseType_t uxPriority,\n\t\t\t\t\t\t\t  TaskHandle_t *pvCreatedTask\n\t\t\t\t\t\t  );</pre>\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreate() then both blocks of memory are automatically dynamically\n * allocated inside the xTaskCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a task is created using\n * xTaskCreateStatic() then the application writer must provide the required\n * memory.  xTaskCreateStatic() therefore allows a task to be created without\n * using any dynamic memory allocation.\n *\n * See xTaskCreateStatic() for a version that does not use any dynamic memory\n * allocation.\n *\n * xTaskCreate() can only be used to create a task that has unrestricted\n * access to the entire microcontroller memory map.  Systems that include MPU\n * support can alternatively create an MPU constrained task using\n * xTaskCreateRestricted().\n *\n * @param pvTaskCode Pointer to the task entry function.  Tasks\n * must be implemented to never return (i.e. continuous loop).\n *\n * @param pcName A descriptive name for the task.  This is mainly used to\n * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default\n * is 16.\n *\n * @param usStackDepth The size of the task stack specified as the number of\n * variables the stack can hold - not the number of bytes.  For example, if\n * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes\n * will be allocated for stack storage.\n *\n * @param pvParameters Pointer that will be used as the parameter for the task\n * being created.\n *\n * @param uxPriority The priority at which the task should run.  Systems that\n * include MPU support can optionally create tasks in a privileged (system)\n * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For\n * example, to create a privileged task at priority 2 the uxPriority parameter\n * should be set to ( 2 | portPRIVILEGE_BIT ).\n *\n * @param pvCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n   <pre>\n // Task to be created.\n void vTaskCode( void * pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t // Task code goes here.\n\t }\n }\n\n // Function that creates a task.\n void vOtherFunction( void )\n {\n static uint8_t ucParameterToPass;\n TaskHandle_t xHandle = NULL;\n\n\t // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass\n\t // must exist for the lifetime of the task, so in this case is declared static.  If it was just an\n\t // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time\n\t // the new task attempts to access it.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );\n     configASSERT( xHandle );\n\n\t // Use the handle to delete the task.\n     if( xHandle != NULL )\n     {\n\t     vTaskDelete( xHandle );\n     }\n }\n   </pre>\n * \\defgroup xTaskCreate xTaskCreate\n * \\ingroup Tasks\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tBaseType_t xTaskCreate(\tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\tconst char * const pcName,\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\tconst configSTACK_DEPTH_TYPE usStackDepth,\n\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\tTaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n *<pre>\n TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,\n\t\t\t\t\t\t\t\t const char * const pcName,\n\t\t\t\t\t\t\t\t uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t void *pvParameters,\n\t\t\t\t\t\t\t\t UBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t StackType_t *pxStackBuffer,\n\t\t\t\t\t\t\t\t StaticTask_t *pxTaskBuffer );</pre>\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreate() then both blocks of memory are automatically dynamically\n * allocated inside the xTaskCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a task is created using\n * xTaskCreateStatic() then the application writer must provide the required\n * memory.  xTaskCreateStatic() therefore allows a task to be created without\n * using any dynamic memory allocation.\n *\n * @param pvTaskCode Pointer to the task entry function.  Tasks\n * must be implemented to never return (i.e. continuous loop).\n *\n * @param pcName A descriptive name for the task.  This is mainly used to\n * facilitate debugging.  The maximum length of the string is defined by\n * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.\n *\n * @param ulStackDepth The size of the task stack specified as the number of\n * variables the stack can hold - not the number of bytes.  For example, if\n * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes\n * will be allocated for stack storage.\n *\n * @param pvParameters Pointer that will be used as the parameter for the task\n * being created.\n *\n * @param uxPriority The priority at which the task will run.\n *\n * @param pxStackBuffer Must point to a StackType_t array that has at least\n * ulStackDepth indexes - the array will then be used as the task's stack,\n * removing the need for the stack to be allocated dynamically.\n *\n * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will\n * then be used to hold the task's data structures, removing the need for the\n * memory to be allocated dynamically.\n *\n * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will\n * be created and a handle to the created task is returned.  If either\n * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and\n * NULL is returned.\n *\n * Example usage:\n   <pre>\n\n    // Dimensions the buffer that the task being created will use as its stack.\n    // NOTE:  This is the number of words the stack will hold, not the number of\n    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,\n    // then 400 bytes (100 * 32-bits) will be allocated.\n    #define STACK_SIZE 200\n\n    // Structure that will hold the TCB of the task being created.\n    StaticTask_t xTaskBuffer;\n\n    // Buffer that the task being created will use as its stack.  Note this is\n    // an array of StackType_t variables.  The size of StackType_t is dependent on\n    // the RTOS port.\n    StackType_t xStack[ STACK_SIZE ];\n\n    // Function that implements the task being created.\n    void vTaskCode( void * pvParameters )\n    {\n        // The parameter value is expected to be 1 as 1 is passed in the\n        // pvParameters value in the call to xTaskCreateStatic().\n        configASSERT( ( uint32_t ) pvParameters == 1UL );\n\n        for( ;; )\n        {\n            // Task code goes here.\n        }\n    }\n\n    // Function that creates a task.\n    void vOtherFunction( void )\n    {\n        TaskHandle_t xHandle = NULL;\n\n        // Create the task without using any dynamic memory allocation.\n        xHandle = xTaskCreateStatic(\n                      vTaskCode,       // Function that implements the task.\n                      \"NAME\",          // Text name for the task.\n                      STACK_SIZE,      // Stack size in words, not bytes.\n                      ( void * ) 1,    // Parameter passed into the task.\n                      tskIDLE_PRIORITY,// Priority at which the task is created.\n                      xStack,          // Array to use as the task's stack.\n                      &xTaskBuffer );  // Variable to hold the task's data structure.\n\n        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have\n        // been created, and xHandle will be the task's handle.  Use the handle\n        // to suspend the task.\n        vTaskSuspend( xHandle );\n    }\n   </pre>\n * \\defgroup xTaskCreateStatic xTaskCreateStatic\n * \\ingroup Tasks\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tTaskHandle_t xTaskCreateStatic(\tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\t\t\tconst char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t\tStackType_t * const puxStackBuffer,\n\t\t\t\t\t\t\t\t\tStaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * task. h\n *<pre>\n BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>\n *\n * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.\n *\n * xTaskCreateRestricted() should only be used in systems that include an MPU\n * implementation.\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n * The function parameters define the memory regions and associated access\n * permissions allocated to the task.\n *\n * See xTaskCreateRestrictedStatic() for a version that does not use any\n * dynamic memory allocation.\n *\n * @param pxTaskDefinition Pointer to a structure that contains a member\n * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\n * documentation) plus an optional stack buffer and the memory region\n * definitions.\n *\n * @param pxCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n   <pre>\n// Create an TaskParameters_t structure that defines the task to be created.\nstatic const TaskParameters_t xCheckTaskParameters =\n{\n\tvATask,\t\t// pvTaskCode - the function that implements the task.\n\t\"ATask\",\t// pcName - just a text name for the task to assist debugging.\n\t100,\t\t// usStackDepth\t- the stack size DEFINED IN WORDS.\n\tNULL,\t\t// pvParameters - passed into the task function as the function parameters.\n\t( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\n\tcStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\n\n\t// xRegions - Allocate up to three separate memory regions for access by\n\t// the task, with appropriate access permissions.  Different processors have\n\t// different memory alignment requirements - refer to the FreeRTOS documentation\n\t// for full information.\n\t{\n\t\t// Base address\t\t\t\t\tLength\tParameters\n        { cReadWriteArray,\t\t\t\t32,\t\tportMPU_REGION_READ_WRITE },\n        { cReadOnlyArray,\t\t\t\t32,\t\tportMPU_REGION_READ_ONLY },\n        { cPrivilegedOnlyAccessArray,\t128,\tportMPU_REGION_PRIVILEGED_READ_WRITE }\n\t}\n};\n\nint main( void )\n{\nTaskHandle_t xHandle;\n\n\t// Create a task from the const structure defined above.  The task handle\n\t// is requested (the second parameter is not NULL) but in this case just for\n\t// demonstration purposes as its not actually used.\n\txTaskCreateRestricted( &xRegTest1Parameters, &xHandle );\n\n\t// Start the scheduler.\n\tvTaskStartScheduler();\n\n\t// Will only get here if there was insufficient memory to create the idle\n\t// and/or timer task.\n\tfor( ;; );\n}\n   </pre>\n * \\defgroup xTaskCreateRestricted xTaskCreateRestricted\n * \\ingroup Tasks\n */\n#if( portUSING_MPU_WRAPPERS == 1 )\n\tBaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n *<pre>\n BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>\n *\n * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.\n *\n * xTaskCreateRestrictedStatic() should only be used in systems that include an\n * MPU implementation.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreateRestricted() then the stack is provided by the application writer,\n * and the memory used to hold the task's data structure is automatically\n * dynamically allocated inside the xTaskCreateRestricted() function.  If a task\n * is created using xTaskCreateRestrictedStatic() then the application writer\n * must provide the memory used to hold the task's data structures too.\n * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be\n * created without using any dynamic memory allocation.\n *\n * @param pxTaskDefinition Pointer to a structure that contains a member\n * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\n * documentation) plus an optional stack buffer and the memory region\n * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure\n * contains an additional member, which is used to point to a variable of type\n * StaticTask_t - which is then used to hold the task's data structure.\n *\n * @param pxCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n   <pre>\n// Create an TaskParameters_t structure that defines the task to be created.\n// The StaticTask_t variable is only included in the structure when\n// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can\n// be used to force the variable into the RTOS kernel's privileged data area.\nstatic PRIVILEGED_DATA StaticTask_t xTaskBuffer;\nstatic const TaskParameters_t xCheckTaskParameters =\n{\n\tvATask,\t\t// pvTaskCode - the function that implements the task.\n\t\"ATask\",\t// pcName - just a text name for the task to assist debugging.\n\t100,\t\t// usStackDepth\t- the stack size DEFINED IN WORDS.\n\tNULL,\t\t// pvParameters - passed into the task function as the function parameters.\n\t( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\n\tcStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\n\n\t// xRegions - Allocate up to three separate memory regions for access by\n\t// the task, with appropriate access permissions.  Different processors have\n\t// different memory alignment requirements - refer to the FreeRTOS documentation\n\t// for full information.\n\t{\n\t\t// Base address\t\t\t\t\tLength\tParameters\n        { cReadWriteArray,\t\t\t\t32,\t\tportMPU_REGION_READ_WRITE },\n        { cReadOnlyArray,\t\t\t\t32,\t\tportMPU_REGION_READ_ONLY },\n        { cPrivilegedOnlyAccessArray,\t128,\tportMPU_REGION_PRIVILEGED_READ_WRITE }\n\t}\n\n\t&xTaskBuffer; // Holds the task's data structure.\n};\n\nint main( void )\n{\nTaskHandle_t xHandle;\n\n\t// Create a task from the const structure defined above.  The task handle\n\t// is requested (the second parameter is not NULL) but in this case just for\n\t// demonstration purposes as its not actually used.\n\txTaskCreateRestricted( &xRegTest1Parameters, &xHandle );\n\n\t// Start the scheduler.\n\tvTaskStartScheduler();\n\n\t// Will only get here if there was insufficient memory to create the idle\n\t// and/or timer task.\n\tfor( ;; );\n}\n   </pre>\n * \\defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic\n * \\ingroup Tasks\n */\n#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\tBaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n *<pre>\n void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );</pre>\n *\n * Memory regions are assigned to a restricted task when the task is created by\n * a call to xTaskCreateRestricted().  These regions can be redefined using\n * vTaskAllocateMPURegions().\n *\n * @param xTask The handle of the task being updated.\n *\n * @param xRegions A pointer to an MemoryRegion_t structure that contains the\n * new memory region definitions.\n *\n * Example usage:\n   <pre>\n// Define an array of MemoryRegion_t structures that configures an MPU region\n// allowing read/write access for 1024 bytes starting at the beginning of the\n// ucOneKByte array.  The other two of the maximum 3 definable regions are\n// unused so set to zero.\nstatic const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =\n{\n\t// Base address\t\tLength\t\tParameters\n\t{ ucOneKByte,\t\t1024,\t\tportMPU_REGION_READ_WRITE },\n\t{ 0,\t\t\t\t0,\t\t\t0 },\n\t{ 0,\t\t\t\t0,\t\t\t0 }\n};\n\nvoid vATask( void *pvParameters )\n{\n\t// This task was created such that it has access to certain regions of\n\t// memory as defined by the MPU configuration.  At some point it is\n\t// desired that these MPU regions are replaced with that defined in the\n\t// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()\n\t// for this purpose.  NULL is used as the task handle to indicate that this\n\t// function should modify the MPU regions of the calling task.\n\tvTaskAllocateMPURegions( NULL, xAltRegions );\n\n\t// Now the task can continue its function, but from this point on can only\n\t// access its stack and the ucOneKByte array (unless any other statically\n\t// defined or shared regions have been declared elsewhere).\n}\n   </pre>\n * \\defgroup xTaskCreateRestricted xTaskCreateRestricted\n * \\ingroup Tasks\n */\nvoid vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskDelete( TaskHandle_t xTask );</pre>\n *\n * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Remove a task from the RTOS real time kernel's management.  The task being\n * deleted will be removed from all ready, blocked, suspended and event lists.\n *\n * NOTE:  The idle task is responsible for freeing the kernel allocated\n * memory from tasks that have been deleted.  It is therefore important that\n * the idle task is not starved of microcontroller processing time if your\n * application makes any calls to vTaskDelete ().  Memory allocated by the\n * task code is not automatically freed, and should be freed before the task\n * is deleted.\n *\n * See the demo application file death.c for sample code that utilises\n * vTaskDelete ().\n *\n * @param xTask The handle of the task to be deleted.  Passing NULL will\n * cause the calling task to be deleted.\n *\n * Example usage:\n   <pre>\n void vOtherFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create the task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // Use the handle to delete the task.\n\t vTaskDelete( xHandle );\n }\n   </pre>\n * \\defgroup vTaskDelete vTaskDelete\n * \\ingroup Tasks\n */\nvoid vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n * TASK CONTROL API\n *----------------------------------------------------------*/\n\n/**\n * task. h\n * <pre>void vTaskDelay( const TickType_t xTicksToDelay );</pre>\n *\n * Delay a task for a given number of ticks.  The actual time that the\n * task remains blocked depends on the tick rate.  The constant\n * portTICK_PERIOD_MS can be used to calculate real time from the tick\n * rate - with the resolution of one tick period.\n *\n * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n *\n * vTaskDelay() specifies a time at which the task wishes to unblock relative to\n * the time at which vTaskDelay() is called.  For example, specifying a block\n * period of 100 ticks will cause the task to unblock 100 ticks after\n * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method\n * of controlling the frequency of a periodic task as the path taken through the\n * code, as well as other task and interrupt activity, will effect the frequency\n * at which vTaskDelay() gets called and therefore the time at which the task\n * next executes.  See vTaskDelayUntil() for an alternative API function designed\n * to facilitate fixed frequency execution.  It does this by specifying an\n * absolute time (rather than a relative time) at which the calling task should\n * unblock.\n *\n * @param xTicksToDelay The amount of time, in tick periods, that\n * the calling task should block.\n *\n * Example usage:\n\n void vTaskFunction( void * pvParameters )\n {\n // Block for 500ms.\n const TickType_t xDelay = 500 / portTICK_PERIOD_MS;\n\n\t for( ;; )\n\t {\n\t\t // Simply toggle the LED every 500ms, blocking between each toggle.\n\t\t vToggleLED();\n\t\t vTaskDelay( xDelay );\n\t }\n }\n\n * \\defgroup vTaskDelay vTaskDelay\n * \\ingroup TaskCtrl\n */\nvoid vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );</pre>\n *\n * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Delay a task until a specified time.  This function can be used by periodic\n * tasks to ensure a constant execution frequency.\n *\n * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will\n * cause a task to block for the specified number of ticks from the time vTaskDelay () is\n * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed\n * execution frequency as the time between a task starting to execute and that task\n * calling vTaskDelay () may not be fixed [the task may take a different path though the\n * code between calls, or may get interrupted or preempted a different number of times\n * each time it executes].\n *\n * Whereas vTaskDelay () specifies a wake time relative to the time at which the function\n * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to\n * unblock.\n *\n * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick\n * rate - with the resolution of one tick period.\n *\n * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the\n * task was last unblocked.  The variable must be initialised with the current time\n * prior to its first use (see the example below).  Following this the variable is\n * automatically updated within vTaskDelayUntil ().\n *\n * @param xTimeIncrement The cycle time period.  The task will be unblocked at\n * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the\n * same xTimeIncrement parameter value will cause the task to execute with\n * a fixed interface period.\n *\n * Example usage:\n   <pre>\n // Perform an action every 10 ticks.\n void vTaskFunction( void * pvParameters )\n {\n TickType_t xLastWakeTime;\n const TickType_t xFrequency = 10;\n\n\t // Initialise the xLastWakeTime variable with the current time.\n\t xLastWakeTime = xTaskGetTickCount ();\n\t for( ;; )\n\t {\n\t\t // Wait for the next cycle.\n\t\t vTaskDelayUntil( &xLastWakeTime, xFrequency );\n\n\t\t // Perform action here.\n\t }\n }\n   </pre>\n * \\defgroup vTaskDelayUntil vTaskDelayUntil\n * \\ingroup TaskCtrl\n */\nvoid vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>BaseType_t xTaskAbortDelay( TaskHandle_t xTask );</pre>\n *\n * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this\n * function to be available.\n *\n * A task will enter the Blocked state when it is waiting for an event.  The\n * event it is waiting for can be a temporal event (waiting for a time), such\n * as when vTaskDelay() is called, or an event on an object, such as when\n * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task\n * that is in the Blocked state is used in a call to xTaskAbortDelay() then the\n * task will leave the Blocked state, and return from whichever function call\n * placed the task into the Blocked state.\n *\n * @param xTask The handle of the task to remove from the Blocked state.\n *\n * @return If the task referenced by xTask was not in the Blocked state then\n * pdFAIL is returned.  Otherwise pdPASS is returned.\n *\n * \\defgroup xTaskAbortDelay xTaskAbortDelay\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );</pre>\n *\n * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Obtain the priority of any task.\n *\n * @param xTask Handle of the task to be queried.  Passing a NULL\n * handle results in the priority of the calling task being returned.\n *\n * @return The priority of xTask.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create a task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // ...\n\n\t // Use the handle to obtain the priority of the created task.\n\t // It was created with tskIDLE_PRIORITY, but may have changed\n\t // it itself.\n\t if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )\n\t {\n\t\t // The task has changed it's priority.\n\t }\n\n\t // ...\n\n\t // Is our priority higher than the created task?\n\t if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )\n\t {\n\t\t // Our priority (obtained using NULL handle) is higher.\n\t }\n }\n   </pre>\n * \\defgroup uxTaskPriorityGet uxTaskPriorityGet\n * \\ingroup TaskCtrl\n */\nUBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );</pre>\n *\n * A version of uxTaskPriorityGet() that can be used from an ISR.\n */\nUBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>eTaskState eTaskGetState( TaskHandle_t xTask );</pre>\n *\n * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Obtain the state of any task.  States are encoded by the eTaskState\n * enumerated type.\n *\n * @param xTask Handle of the task to be queried.\n *\n * @return The state of xTask at the time the function was called.  Note the\n * state of the task might change between the function being called, and the\n * functions return value being tested by the calling task.\n */\neTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );</pre>\n *\n * configUSE_TRACE_FACILITY must be defined as 1 for this function to be\n * available.  See the configuration section for more information.\n *\n * Populates a TaskStatus_t structure with information about a task.\n *\n * @param xTask Handle of the task being queried.  If xTask is NULL then\n * information will be returned about the calling task.\n *\n * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be\n * filled with information about the task referenced by the handle passed using\n * the xTask parameter.\n *\n * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report\n * the stack high water mark of the task being queried.  Calculating the stack\n * high water mark takes a relatively long time, and can make the system\n * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to\n * allow the high water mark checking to be skipped.  The high watermark value\n * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is\n * not set to pdFALSE;\n *\n * @param eState The TaskStatus_t structure contains a member to report the\n * state of the task being queried.  Obtaining the task state is not as fast as\n * a simple assignment - so the eState parameter is provided to allow the state\n * information to be omitted from the TaskStatus_t structure.  To obtain state\n * information then set eState to eInvalid - otherwise the value passed in\n * eState will be reported as the task state in the TaskStatus_t structure.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n TaskStatus_t xTaskDetails;\n\n    // Obtain the handle of a task from its name.\n    xHandle = xTaskGetHandle( \"Task_Name\" );\n\n    // Check the handle is not NULL.\n    configASSERT( xHandle );\n\n    // Use the handle to obtain further information about the task.\n    vTaskGetInfo( xHandle,\n                  &xTaskDetails,\n                  pdTRUE, // Include the high water mark in xTaskDetails.\n                  eInvalid ); // Include the task state in xTaskDetails.\n }\n   </pre>\n * \\defgroup vTaskGetInfo vTaskGetInfo\n * \\ingroup TaskCtrl\n */\nvoid vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );</pre>\n *\n * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Set the priority of any task.\n *\n * A context switch will occur before the function returns if the priority\n * being set is higher than the currently executing task.\n *\n * @param xTask Handle to the task for which the priority is being set.\n * Passing a NULL handle results in the priority of the calling task being set.\n *\n * @param uxNewPriority The priority to which the task will be set.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create a task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // ...\n\n\t // Use the handle to raise the priority of the created task.\n\t vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );\n\n\t // ...\n\n\t // Use a NULL handle to raise our priority to the same value.\n\t vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );\n }\n   </pre>\n * \\defgroup vTaskPrioritySet vTaskPrioritySet\n * \\ingroup TaskCtrl\n */\nvoid vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskSuspend( TaskHandle_t xTaskToSuspend );</pre>\n *\n * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Suspend any task.  When suspended a task will never get any microcontroller\n * processing time, no matter what its priority.\n *\n * Calls to vTaskSuspend are not accumulative -\n * i.e. calling vTaskSuspend () twice on the same task still only requires one\n * call to vTaskResume () to ready the suspended task.\n *\n * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL\n * handle will cause the calling task to be suspended.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create a task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // ...\n\n\t // Use the handle to suspend the created task.\n\t vTaskSuspend( xHandle );\n\n\t // ...\n\n\t // The created task will not run during this period, unless\n\t // another task calls vTaskResume( xHandle ).\n\n\t //...\n\n\n\t // Suspend ourselves.\n\t vTaskSuspend( NULL );\n\n\t // We cannot get here unless another task calls vTaskResume\n\t // with our handle as the parameter.\n }\n   </pre>\n * \\defgroup vTaskSuspend vTaskSuspend\n * \\ingroup TaskCtrl\n */\nvoid vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskResume( TaskHandle_t xTaskToResume );</pre>\n *\n * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Resumes a suspended task.\n *\n * A task that has been suspended by one or more calls to vTaskSuspend ()\n * will be made available for running again by a single call to\n * vTaskResume ().\n *\n * @param xTaskToResume Handle to the task being readied.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create a task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // ...\n\n\t // Use the handle to suspend the created task.\n\t vTaskSuspend( xHandle );\n\n\t // ...\n\n\t // The created task will not run during this period, unless\n\t // another task calls vTaskResume( xHandle ).\n\n\t //...\n\n\n\t // Resume the suspended task ourselves.\n\t vTaskResume( xHandle );\n\n\t // The created task will once again get microcontroller processing\n\t // time in accordance with its priority within the system.\n }\n   </pre>\n * \\defgroup vTaskResume vTaskResume\n * \\ingroup TaskCtrl\n */\nvoid vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void xTaskResumeFromISR( TaskHandle_t xTaskToResume );</pre>\n *\n * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be\n * available.  See the configuration section for more information.\n *\n * An implementation of vTaskResume() that can be called from within an ISR.\n *\n * A task that has been suspended by one or more calls to vTaskSuspend ()\n * will be made available for running again by a single call to\n * xTaskResumeFromISR ().\n *\n * xTaskResumeFromISR() should not be used to synchronise a task with an\n * interrupt if there is a chance that the interrupt could arrive prior to the\n * task being suspended - as this can lead to interrupts being missed. Use of a\n * semaphore as a synchronisation mechanism would avoid this eventuality.\n *\n * @param xTaskToResume Handle to the task being readied.\n *\n * @return pdTRUE if resuming the task should result in a context switch,\n * otherwise pdFALSE. This is used by the ISR to determine if a context switch\n * may be required following the ISR.\n *\n * \\defgroup vTaskResumeFromISR vTaskResumeFromISR\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n * SCHEDULER CONTROL\n *----------------------------------------------------------*/\n\n/**\n * task. h\n * <pre>void vTaskStartScheduler( void );</pre>\n *\n * Starts the real time kernel tick processing.  After calling the kernel\n * has control over which tasks are executed and when.\n *\n * See the demo application file main.c for an example of creating\n * tasks and starting the kernel.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n\t // Create at least one task before starting the kernel.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\n\n\t // Start the real time kernel with preemption.\n\t vTaskStartScheduler ();\n\n\t // Will not get here unless a task calls vTaskEndScheduler ()\n }\n   </pre>\n *\n * \\defgroup vTaskStartScheduler vTaskStartScheduler\n * \\ingroup SchedulerControl\n */\nvoid vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskEndScheduler( void );</pre>\n *\n * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC\n * in place of DOS, implements this function.\n *\n * Stops the real time kernel tick.  All created tasks will be automatically\n * deleted and multitasking (either preemptive or cooperative) will\n * stop.  Execution then resumes from the point where vTaskStartScheduler ()\n * was called, as if vTaskStartScheduler () had just returned.\n *\n * See the demo application file main. c in the demo/PC directory for an\n * example that uses vTaskEndScheduler ().\n *\n * vTaskEndScheduler () requires an exit function to be defined within the\n * portable layer (see vPortEndScheduler () in port. c for the PC port).  This\n * performs hardware specific operations such as stopping the kernel tick.\n *\n * vTaskEndScheduler () will cause all of the resources allocated by the\n * kernel to be freed - but will not free resources allocated by application\n * tasks.\n *\n * Example usage:\n   <pre>\n void vTaskCode( void * pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t // Task code goes here.\n\n\t\t // At some point we want to end the real time kernel processing\n\t\t // so call ...\n\t\t vTaskEndScheduler ();\n\t }\n }\n\n void vAFunction( void )\n {\n\t // Create at least one task before starting the kernel.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\n\n\t // Start the real time kernel with preemption.\n\t vTaskStartScheduler ();\n\n\t // Will only get here when the vTaskCode () task has called\n\t // vTaskEndScheduler ().  When we get here we are back to single task\n\t // execution.\n }\n   </pre>\n *\n * \\defgroup vTaskEndScheduler vTaskEndScheduler\n * \\ingroup SchedulerControl\n */\nvoid vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskSuspendAll( void );</pre>\n *\n * Suspends the scheduler without disabling interrupts.  Context switches will\n * not occur while the scheduler is suspended.\n *\n * After calling vTaskSuspendAll () the calling task will continue to execute\n * without risk of being swapped out until a call to xTaskResumeAll () has been\n * made.\n *\n * API functions that have the potential to cause a context switch (for example,\n * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler\n * is suspended.\n *\n * Example usage:\n   <pre>\n void vTask1( void * pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t // Task code goes here.\n\n\t\t // ...\n\n\t\t // At some point the task wants to perform a long operation during\n\t\t // which it does not want to get swapped out.  It cannot use\n\t\t // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\n\t\t // operation may cause interrupts to be missed - including the\n\t\t // ticks.\n\n\t\t // Prevent the real time kernel swapping out the task.\n\t\t vTaskSuspendAll ();\n\n\t\t // Perform the operation here.  There is no need to use critical\n\t\t // sections as we have all the microcontroller processing time.\n\t\t // During this time interrupts will still operate and the kernel\n\t\t // tick count will be maintained.\n\n\t\t // ...\n\n\t\t // The operation is complete.  Restart the kernel.\n\t\t xTaskResumeAll ();\n\t }\n }\n   </pre>\n * \\defgroup vTaskSuspendAll vTaskSuspendAll\n * \\ingroup SchedulerControl\n */\nvoid vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>BaseType_t xTaskResumeAll( void );</pre>\n *\n * Resumes scheduler activity after it was suspended by a call to\n * vTaskSuspendAll().\n *\n * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks\n * that were previously suspended by a call to vTaskSuspend().\n *\n * @return If resuming the scheduler caused a context switch then pdTRUE is\n *\t\t  returned, otherwise pdFALSE is returned.\n *\n * Example usage:\n   <pre>\n void vTask1( void * pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t // Task code goes here.\n\n\t\t // ...\n\n\t\t // At some point the task wants to perform a long operation during\n\t\t // which it does not want to get swapped out.  It cannot use\n\t\t // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\n\t\t // operation may cause interrupts to be missed - including the\n\t\t // ticks.\n\n\t\t // Prevent the real time kernel swapping out the task.\n\t\t vTaskSuspendAll ();\n\n\t\t // Perform the operation here.  There is no need to use critical\n\t\t // sections as we have all the microcontroller processing time.\n\t\t // During this time interrupts will still operate and the real\n\t\t // time kernel tick count will be maintained.\n\n\t\t // ...\n\n\t\t // The operation is complete.  Restart the kernel.  We want to force\n\t\t // a context switch - but there is no point if resuming the scheduler\n\t\t // caused a context switch already.\n\t\t if( !xTaskResumeAll () )\n\t\t {\n\t\t\t  taskYIELD ();\n\t\t }\n\t }\n }\n   </pre>\n * \\defgroup xTaskResumeAll xTaskResumeAll\n * \\ingroup SchedulerControl\n */\nBaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n * TASK UTILITIES\n *----------------------------------------------------------*/\n\n/**\n * task. h\n * <PRE>TickType_t xTaskGetTickCount( void );</PRE>\n *\n * @return The count of ticks since vTaskStartScheduler was called.\n *\n * \\defgroup xTaskGetTickCount xTaskGetTickCount\n * \\ingroup TaskUtils\n */\nTickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>\n *\n * @return The count of ticks since vTaskStartScheduler was called.\n *\n * This is a version of xTaskGetTickCount() that is safe to be called from an\n * ISR - provided that TickType_t is the natural word size of the\n * microcontroller being used or interrupt nesting is either not supported or\n * not being used.\n *\n * \\defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR\n * \\ingroup TaskUtils\n */\nTickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>\n *\n * @return The number of tasks that the real time kernel is currently managing.\n * This includes all ready, blocked and suspended tasks.  A task that\n * has been deleted but not yet freed by the idle task will also be\n * included in the count.\n *\n * \\defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks\n * \\ingroup TaskUtils\n */\nUBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>char *pcTaskGetName( TaskHandle_t xTaskToQuery );</PRE>\n *\n * @return The text (human readable) name of the task referenced by the handle\n * xTaskToQuery.  A task can query its own name by either passing in its own\n * handle, or by setting xTaskToQuery to NULL.\n *\n * \\defgroup pcTaskGetName pcTaskGetName\n * \\ingroup TaskUtils\n */\nchar *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task. h\n * <PRE>TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );</PRE>\n *\n * NOTE:  This function takes a relatively long time to complete and should be\n * used sparingly.\n *\n * @return The handle of the task that has the human readable name pcNameToQuery.\n * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle\n * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.\n *\n * \\defgroup pcTaskGetHandle pcTaskGetHandle\n * \\ingroup TaskUtils\n */\nTaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task.h\n * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>\n *\n * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for\n * this function to be available.\n *\n * Returns the high water mark of the stack associated with xTask.  That is,\n * the minimum free stack space there has been (in words, so on a 32 bit machine\n * a value of 1 means 4 bytes) since the task started.  The smaller the returned\n * number the closer the task has come to overflowing its stack.\n *\n * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n * user to determine the return type.  It gets around the problem of the value\n * overflowing on 8-bit types without breaking backward compatibility for\n * applications that expect an 8-bit return type.\n *\n * @param xTask Handle of the task associated with the stack to be checked.\n * Set xTask to NULL to check the stack of the calling task.\n *\n * @return The smallest amount of free stack space there has been (in words, so\n * actual spaces on the stack rather than bytes) since the task referenced by\n * xTask was created.\n */\nUBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * <PRE>configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );</PRE>\n *\n * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for\n * this function to be available.\n *\n * Returns the high water mark of the stack associated with xTask.  That is,\n * the minimum free stack space there has been (in words, so on a 32 bit machine\n * a value of 1 means 4 bytes) since the task started.  The smaller the returned\n * number the closer the task has come to overflowing its stack.\n *\n * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n * user to determine the return type.  It gets around the problem of the value\n * overflowing on 8-bit types without breaking backward compatibility for\n * applications that expect an 8-bit return type.\n *\n * @param xTask Handle of the task associated with the stack to be checked.\n * Set xTask to NULL to check the stack of the calling task.\n *\n * @return The smallest amount of free stack space there has been (in words, so\n * actual spaces on the stack rather than bytes) since the task referenced by\n * xTask was created.\n */\nconfigSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/* When using trace macros it is sometimes necessary to include task.h before\nFreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,\nso the following two prototypes will cause a compilation error.  This can be\nfixed by simply guarding against the inclusion of these two prototypes unless\nthey are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration\nconstant. */\n#ifdef configUSE_APPLICATION_TASK_TAG\n\t#if configUSE_APPLICATION_TASK_TAG == 1\n\t\t/**\n\t\t * task.h\n\t\t * <pre>void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );</pre>\n\t\t *\n\t\t * Sets pxHookFunction to be the task hook function used by the task xTask.\n\t\t * Passing xTask as NULL has the effect of setting the calling tasks hook\n\t\t * function.\n\t\t */\n\t\tvoid vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;\n\n\t\t/**\n\t\t * task.h\n\t\t * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>\n\t\t *\n\t\t * Returns the pxHookFunction value assigned to the task xTask.  Do not\n\t\t * call from an interrupt service routine - call\n\t\t * xTaskGetApplicationTaskTagFromISR() instead.\n\t\t */\n\t\tTaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n\t\t/**\n\t\t * task.h\n\t\t * <pre>void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );</pre>\n\t\t *\n\t\t * Returns the pxHookFunction value assigned to the task xTask.  Can\n\t\t * be called from an interrupt service routine.\n\t\t */\n\t\tTaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\t#endif /* configUSE_APPLICATION_TASK_TAG ==1 */\n#endif /* ifdef configUSE_APPLICATION_TASK_TAG */\n\n#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n\n\t/* Each task contains an array of pointers that is dimensioned by the\n\tconfigNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The\n\tkernel does not use the pointers itself, so the application writer can use\n\tthe pointers for any purpose they wish.  The following two functions are\n\tused to set and query a pointer respectively. */\n\tvoid vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;\n\tvoid *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/**\n * task.h\n * <pre>BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );</pre>\n *\n * Calls the hook function associated with xTask.  Passing xTask as NULL has\n * the effect of calling the Running tasks (the calling task) hook function.\n *\n * pvParameter is passed to the hook function for the task to interpret as it\n * wants.  The return value is the value returned by the task hook function\n * registered by the user.\n */\nBaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;\n\n/**\n * xTaskGetIdleTaskHandle() is only available if\n * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.\n *\n * Simply returns the handle of the idle task.  It is not valid to call\n * xTaskGetIdleTaskHandle() before the scheduler has been started.\n */\nTaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/**\n * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for\n * uxTaskGetSystemState() to be available.\n *\n * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in\n * the system.  TaskStatus_t structures contain, among other things, members\n * for the task handle, task name, task priority, task state, and total amount\n * of run time consumed by the task.  See the TaskStatus_t structure\n * definition in this file for the full member list.\n *\n * NOTE:  This function is intended for debugging use only as its use results in\n * the scheduler remaining suspended for an extended period.\n *\n * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.\n * The array must contain at least one TaskStatus_t structure for each task\n * that is under the control of the RTOS.  The number of tasks under the control\n * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.\n *\n * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray\n * parameter.  The size is specified as the number of indexes in the array, or\n * the number of TaskStatus_t structures contained in the array, not by the\n * number of bytes in the array.\n *\n * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in\n * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the\n * total run time (as defined by the run time stats clock, see\n * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.\n * pulTotalRunTime can be set to NULL to omit the total run time information.\n *\n * @return The number of TaskStatus_t structures that were populated by\n * uxTaskGetSystemState().  This should equal the number returned by the\n * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed\n * in the uxArraySize parameter was too small.\n *\n * Example usage:\n   <pre>\n    // This example demonstrates how a human readable table of run time stats\n\t// information is generated from raw data provided by uxTaskGetSystemState().\n\t// The human readable table is written to pcWriteBuffer\n\tvoid vTaskGetRunTimeStats( char *pcWriteBuffer )\n\t{\n\tTaskStatus_t *pxTaskStatusArray;\n\tvolatile UBaseType_t uxArraySize, x;\n\tuint32_t ulTotalRunTime, ulStatsAsPercentage;\n\n\t\t// Make sure the write buffer does not contain a string.\n\t\t*pcWriteBuffer = 0x00;\n\n\t\t// Take a snapshot of the number of tasks in case it changes while this\n\t\t// function is executing.\n\t\tuxArraySize = uxTaskGetNumberOfTasks();\n\n\t\t// Allocate a TaskStatus_t structure for each task.  An array could be\n\t\t// allocated statically at compile time.\n\t\tpxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );\n\n\t\tif( pxTaskStatusArray != NULL )\n\t\t{\n\t\t\t// Generate raw status information about each task.\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );\n\n\t\t\t// For percentage calculations.\n\t\t\tulTotalRunTime /= 100UL;\n\n\t\t\t// Avoid divide by zero errors.\n\t\t\tif( ulTotalRunTime > 0 )\n\t\t\t{\n\t\t\t\t// For each populated position in the pxTaskStatusArray array,\n\t\t\t\t// format the raw data as human readable ASCII data\n\t\t\t\tfor( x = 0; x < uxArraySize; x++ )\n\t\t\t\t{\n\t\t\t\t\t// What percentage of the total run time has the task used?\n\t\t\t\t\t// This will always be rounded down to the nearest integer.\n\t\t\t\t\t// ulTotalRunTimeDiv100 has already been divided by 100.\n\t\t\t\t\tulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;\n\n\t\t\t\t\tif( ulStatsAsPercentage > 0UL )\n\t\t\t\t\t{\n\t\t\t\t\t\tsprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t// If the percentage is zero here then the task has\n\t\t\t\t\t\t// consumed less than 1% of the total run time.\n\t\t\t\t\t\tsprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );\n\t\t\t\t\t}\n\n\t\t\t\t\tpcWriteBuffer += strlen( ( char * ) pcWriteBuffer );\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t// The array is no longer needed, free the memory it consumes.\n\t\t\tvPortFree( pxTaskStatusArray );\n\t\t}\n\t}\n\t</pre>\n */\nUBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>\n *\n * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must\n * both be defined as 1 for this function to be available.  See the\n * configuration section of the FreeRTOS.org website for more information.\n *\n * NOTE 1: This function will disable interrupts for its duration.  It is\n * not intended for normal application runtime use but as a debug aid.\n *\n * Lists all the current tasks, along with their current state and stack\n * usage high water mark.\n *\n * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or\n * suspended ('S').\n *\n * PLEASE NOTE:\n *\n * This function is provided for convenience only, and is used by many of the\n * demo applications.  Do not consider it to be part of the scheduler.\n *\n * vTaskList() calls uxTaskGetSystemState(), then formats part of the\n * uxTaskGetSystemState() output into a human readable table that displays task\n * names, states and stack usage.\n *\n * vTaskList() has a dependency on the sprintf() C library function that might\n * bloat the code size, use a lot of stack, and provide different results on\n * different platforms.  An alternative, tiny, third party, and limited\n * functionality implementation of sprintf() is provided in many of the\n * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note\n * printf-stdarg.c does not provide a full snprintf() implementation!).\n *\n * It is recommended that production systems call uxTaskGetSystemState()\n * directly to get access to raw stats data, rather than indirectly through a\n * call to vTaskList().\n *\n * @param pcWriteBuffer A buffer into which the above mentioned details\n * will be written, in ASCII form.  This buffer is assumed to be large\n * enough to contain the generated report.  Approximately 40 bytes per\n * task should be sufficient.\n *\n * \\defgroup vTaskList vTaskList\n * \\ingroup TaskUtils\n */\nvoid vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task. h\n * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>\n *\n * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS\n * must both be defined as 1 for this function to be available.  The application\n * must also then provide definitions for\n * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()\n * to configure a peripheral timer/counter and return the timers current count\n * value respectively.  The counter should be at least 10 times the frequency of\n * the tick count.\n *\n * NOTE 1: This function will disable interrupts for its duration.  It is\n * not intended for normal application runtime use but as a debug aid.\n *\n * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\n * accumulated execution time being stored for each task.  The resolution\n * of the accumulated time value depends on the frequency of the timer\n * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\n * Calling vTaskGetRunTimeStats() writes the total execution time of each\n * task into a buffer, both as an absolute count value and as a percentage\n * of the total system execution time.\n *\n * NOTE 2:\n *\n * This function is provided for convenience only, and is used by many of the\n * demo applications.  Do not consider it to be part of the scheduler.\n *\n * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the\n * uxTaskGetSystemState() output into a human readable table that displays the\n * amount of time each task has spent in the Running state in both absolute and\n * percentage terms.\n *\n * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function\n * that might bloat the code size, use a lot of stack, and provide different\n * results on different platforms.  An alternative, tiny, third party, and\n * limited functionality implementation of sprintf() is provided in many of the\n * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note\n * printf-stdarg.c does not provide a full snprintf() implementation!).\n *\n * It is recommended that production systems call uxTaskGetSystemState() directly\n * to get access to raw stats data, rather than indirectly through a call to\n * vTaskGetRunTimeStats().\n *\n * @param pcWriteBuffer A buffer into which the execution times will be\n * written, in ASCII form.  This buffer is assumed to be large enough to\n * contain the generated report.  Approximately 40 bytes per task should\n * be sufficient.\n *\n * \\defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats\n * \\ingroup TaskUtils\n */\nvoid vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n* task. h\n* <PRE>TickType_t xTaskGetIdleRunTimeCounter( void );</PRE>\n*\n* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS\n* must both be defined as 1 for this function to be available.  The application\n* must also then provide definitions for\n* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()\n* to configure a peripheral timer/counter and return the timers current count\n* value respectively.  The counter should be at least 10 times the frequency of\n* the tick count.\n*\n* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\n* accumulated execution time being stored for each task.  The resolution\n* of the accumulated time value depends on the frequency of the timer\n* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\n* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total\n* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()\n* returns the total execution time of just the idle task.\n*\n* @return The total run time of the idle task.  This is the amount of time the\n* idle task has actually been executing.  The unit of time is dependent on the\n* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and\n* portGET_RUN_TIME_COUNTER_VALUE() macros.\n*\n* \\defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter\n* \\ingroup TaskUtils\n*/\nTickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\n * already in the Blocked state to wait for a notification when the notification\n * arrives then the task will automatically be removed from the Blocked state\n * (unblocked) and the notification cleared.\n *\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\n * to wait for its notification value to have a non-zero value.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param ulValue Data that can be sent with the notification.  How the data is\n * used depends on the value of the eAction parameter.\n *\n * @param eAction Specifies how the notification updates the task's notification\n * value, if at all.  Valid values for eAction are as follows:\n *\n * eSetBits -\n * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()\n * always returns pdPASS in this case.\n *\n * eIncrement -\n * The task's notification value is incremented.  ulValue is not used and\n * xTaskNotify() always returns pdPASS in this case.\n *\n * eSetValueWithOverwrite -\n * The task's notification value is set to the value of ulValue, even if the\n * task being notified had not yet processed the previous notification (the\n * task already had a notification pending).  xTaskNotify() always returns\n * pdPASS in this case.\n *\n * eSetValueWithoutOverwrite -\n * If the task being notified did not already have a notification pending then\n * the task's notification value is set to ulValue and xTaskNotify() will\n * return pdPASS.  If the task being notified already had a notification\n * pending then no action is performed and pdFAIL is returned.\n *\n * eNoAction -\n * The task receives a notification without its notification value being\n * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in\n * this case.\n *\n *  pulPreviousNotificationValue -\n *  Can be used to pass out the subject task's notification value before any\n *  bits are modified by the notify function.\n *\n * @return Dependent on the value of eAction.  See the description of the\n * eAction parameter.\n *\n * \\defgroup xTaskNotify xTaskNotify\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;\n#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )\n#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * A version of xTaskNotify() that can be used from an interrupt service routine\n * (ISR).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\n * already in the Blocked state to wait for a notification when the notification\n * arrives then the task will automatically be removed from the Blocked state\n * (unblocked) and the notification cleared.\n *\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\n * to wait for its notification value to have a non-zero value.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param ulValue Data that can be sent with the notification.  How the data is\n * used depends on the value of the eAction parameter.\n *\n * @param eAction Specifies how the notification updates the task's notification\n * value, if at all.  Valid values for eAction are as follows:\n *\n * eSetBits -\n * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()\n * always returns pdPASS in this case.\n *\n * eIncrement -\n * The task's notification value is incremented.  ulValue is not used and\n * xTaskNotify() always returns pdPASS in this case.\n *\n * eSetValueWithOverwrite -\n * The task's notification value is set to the value of ulValue, even if the\n * task being notified had not yet processed the previous notification (the\n * task already had a notification pending).  xTaskNotify() always returns\n * pdPASS in this case.\n *\n * eSetValueWithoutOverwrite -\n * If the task being notified did not already have a notification pending then\n * the task's notification value is set to ulValue and xTaskNotify() will\n * return pdPASS.  If the task being notified already had a notification\n * pending then no action is performed and pdFAIL is returned.\n *\n * eNoAction -\n * The task receives a notification without its notification value being\n * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in\n * this case.\n *\n * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the\n * task to which the notification was sent to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently running task.  If\n * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should\n * be requested before the interrupt is exited.  How a context switch is\n * requested from an ISR is dependent on the port - see the documentation page\n * for the port in use.\n *\n * @return Dependent on the value of eAction.  See the description of the\n * eAction parameter.\n *\n * \\defgroup xTaskNotify xTaskNotify\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )\n#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );</pre>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\n * already in the Blocked state to wait for a notification when the notification\n * arrives then the task will automatically be removed from the Blocked state\n * (unblocked) and the notification cleared.\n *\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\n * to wait for its notification value to have a non-zero value.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value\n * will be cleared in the calling task's notification value before the task\n * checks to see if any notifications are pending, and optionally blocks if no\n * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if\n * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have\n * the effect of resetting the task's notification value to 0.  Setting\n * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.\n *\n * @param ulBitsToClearOnExit If a notification is pending or received before\n * the calling task exits the xTaskNotifyWait() function then the task's\n * notification value (see the xTaskNotify() API function) is passed out using\n * the pulNotificationValue parameter.  Then any bits that are set in\n * ulBitsToClearOnExit will be cleared in the task's notification value (note\n * *pulNotificationValue is set before any bits are cleared).  Setting\n * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL\n * (if limits.h is not included) will have the effect of resetting the task's\n * notification value to 0 before the function exits.  Setting\n * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged\n * when the function exits (in which case the value passed out in\n * pulNotificationValue will match the task's notification value).\n *\n * @param pulNotificationValue Used to pass the task's notification value out\n * of the function.  Note the value passed out will not be effected by the\n * clearing of any bits caused by ulBitsToClearOnExit being non-zero.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait in\n * the Blocked state for a notification to be received, should a notification\n * not already be pending when xTaskNotifyWait() was called.  The task\n * will not consume any processing time while it is in the Blocked state.  This\n * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be\n * used to convert a time specified in milliseconds to a time specified in\n * ticks.\n *\n * @return If a notification was received (including notifications that were\n * already pending when xTaskNotifyWait was called) then pdPASS is\n * returned.  Otherwise pdFAIL is returned.\n *\n * \\defgroup xTaskNotifyWait xTaskNotifyWait\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );</PRE>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro\n * to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * xTaskNotifyGive() is a helper macro intended for use when task notifications\n * are used as light weight and faster binary or counting semaphore equivalents.\n * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,\n * the equivalent action that instead uses a task notification is\n * xTaskNotifyGive().\n *\n * When task notifications are being used as a binary or counting semaphore\n * equivalent then the task being notified should wait for the notification\n * using the ulTaskNotificationTake() API function rather than the\n * xTaskNotifyWait() API function.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the\n * eAction parameter set to eIncrement - so pdPASS is always returned.\n *\n * \\defgroup xTaskNotifyGive xTaskNotifyGive\n * \\ingroup TaskNotifications\n */\n#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )\n\n/**\n * task. h\n * <PRE>void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro\n * to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * A version of xTaskNotifyGive() that can be called from an interrupt service\n * routine (ISR).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * vTaskNotifyGiveFromISR() is intended for use when task notifications are\n * used as light weight and faster binary or counting semaphore equivalents.\n * Actual FreeRTOS semaphores are given from an ISR using the\n * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses\n * a task notification is vTaskNotifyGiveFromISR().\n *\n * When task notifications are being used as a binary or counting semaphore\n * equivalent then the task being notified should wait for the notification\n * using the ulTaskNotificationTake() API function rather than the\n * xTaskNotifyWait() API function.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the\n * task to which the notification was sent to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently running task.  If\n * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch\n * should be requested before the interrupt is exited.  How a context switch is\n * requested from an ISR is dependent on the port - see the documentation page\n * for the port in use.\n *\n * \\defgroup xTaskNotifyWait xTaskNotifyWait\n * \\ingroup TaskNotifications\n */\nvoid vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );</pre>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * ulTaskNotifyTake() is intended for use when a task notification is used as a\n * faster and lighter weight binary or counting semaphore alternative.  Actual\n * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the\n * equivalent action that instead uses a task notification is\n * ulTaskNotifyTake().\n *\n * When a task is using its notification value as a binary or counting semaphore\n * other tasks should send notifications to it using the xTaskNotifyGive()\n * macro, or xTaskNotify() function with the eAction parameter set to\n * eIncrement.\n *\n * ulTaskNotifyTake() can either clear the task's notification value to\n * zero on exit, in which case the notification value acts like a binary\n * semaphore, or decrement the task's notification value on exit, in which case\n * the notification value acts like a counting semaphore.\n *\n * A task can use ulTaskNotifyTake() to [optionally] block to wait for a\n * the task's notification value to be non-zero.  The task does not consume any\n * CPU time while it is in the Blocked state.\n *\n * Where as xTaskNotifyWait() will return when a notification is pending,\n * ulTaskNotifyTake() will return when the task's notification value is\n * not zero.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's\n * notification value is decremented when the function exits.  In this way the\n * notification value acts like a counting semaphore.  If xClearCountOnExit is\n * not pdFALSE then the task's notification value is cleared to zero when the\n * function exits.  In this way the notification value acts like a binary\n * semaphore.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait in\n * the Blocked state for the task's notification value to be greater than zero,\n * should the count not already be greater than zero when\n * ulTaskNotifyTake() was called.  The task will not consume any processing\n * time while it is in the Blocked state.  This is specified in kernel ticks,\n * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time\n * specified in milliseconds to a time specified in ticks.\n *\n * @return The task's notification count before it is either cleared to zero or\n * decremented (see the xClearCountOnExit parameter).\n *\n * \\defgroup ulTaskNotifyTake ulTaskNotifyTake\n * \\ingroup TaskNotifications\n */\nuint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );</pre>\n *\n * If the notification state of the task referenced by the handle xTask is\n * eNotified, then set the task's notification state to eNotWaitingNotification.\n * The task's notification value is not altered.  Set xTask to NULL to clear the\n * notification state of the calling task.\n *\n * @return pdTRUE if the task's notification state was set to\n * eNotWaitingNotification, otherwise pdFALSE.\n * \\defgroup xTaskNotifyStateClear xTaskNotifyStateClear\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );\n\n/*-----------------------------------------------------------\n * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\n *----------------------------------------------------------*/\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY\n * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\n * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * Called from the real time kernel tick (either preemptive or cooperative),\n * this increments the tick count and checks if any tasks that are blocked\n * for a finite period required removing from a blocked list and placing on\n * a ready list.  If a non-zero value is returned then a context switch is\n * required because either:\n *   + A task was removed from a blocked list because its timeout had expired,\n *     or\n *   + Time slicing is in use and there is a task of equal priority to the\n *     currently running task.\n */\nBaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * Removes the calling task from the ready list and places it both\n * on the list of tasks waiting for a particular event, and the\n * list of delayed tasks.  The task will be removed from both lists\n * and replaced on the ready list should either the event occur (and\n * there be no higher priority tasks waiting on the same event) or\n * the delay period expires.\n *\n * The 'unordered' version replaces the event list item value with the\n * xItemValue value, and inserts the list item at the end of the list.\n *\n * The 'ordered' version uses the existing event list item value (which is the\n * owning tasks priority) to insert the list item into the event list is task\n * priority order.\n *\n * @param pxEventList The list containing tasks that are blocked waiting\n * for the event to occur.\n *\n * @param xItemValue The item value to use for the event list item when the\n * event list is not ordered by task priority.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait\n * for the event to occur.  This is specified in kernel ticks,the constant\n * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time\n * period.\n */\nvoid vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nvoid vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * This function performs nearly the same function as vTaskPlaceOnEventList().\n * The difference being that this function does not permit tasks to block\n * indefinitely, whereas vTaskPlaceOnEventList() does.\n *\n */\nvoid vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * Removes a task from both the specified event list and the list of blocked\n * tasks, and places it on a ready queue.\n *\n * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called\n * if either an event occurs to unblock a task, or the block timeout period\n * expires.\n *\n * xTaskRemoveFromEventList() is used when the event list is in task priority\n * order.  It removes the list item from the head of the event list as that will\n * have the highest priority owning task of all the tasks on the event list.\n * vTaskRemoveFromUnorderedEventList() is used when the event list is not\n * ordered and the event list items hold something other than the owning tasks\n * priority.  In this case the event list item value is updated to the value\n * passed in the xItemValue parameter.\n *\n * @return pdTRUE if the task being removed has a higher priority than the task\n * making the call, otherwise pdFALSE.\n */\nBaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;\nvoid vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY\n * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\n * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * Sets the pointer to the current TCB to the TCB of the highest priority task\n * that is ready to run.\n */\nportDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;\n\n/*\n * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY\n * THE EVENT BITS MODULE.\n */\nTickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Return the handle of the calling task.\n */\nTaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Capture the current time status for future reference.\n */\nvoid vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;\n\n/*\n * Compare the time status now with that previously captured to see if the\n * timeout has expired.\n */\nBaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;\n\n/*\n * Shortcut used by the queue implementation to prevent unnecessary call to\n * taskYIELD();\n */\nvoid vTaskMissedYield( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Returns the scheduler state as taskSCHEDULER_RUNNING,\n * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.\n */\nBaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Raises the priority of the mutex holder to that of the calling task should\n * the mutex holder have a priority less than the calling task.\n */\nBaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;\n\n/*\n * Set the priority of a task back to its proper priority in the case that it\n * inherited a higher priority while it was holding a semaphore.\n */\nBaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;\n\n/*\n * If a higher priority task attempting to obtain a mutex caused a lower\n * priority task to inherit the higher priority task's priority - but the higher\n * priority task then timed out without obtaining the mutex, then the lower\n * priority task will disinherit the priority again - but only down as far as\n * the highest priority task that is still waiting for the mutex (if there were\n * more than one task waiting for the mutex).\n */\nvoid vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;\n\n/*\n * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.\n */\nUBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/*\n * Set the uxTaskNumber of the task referenced by the xTask parameter to\n * uxHandle.\n */\nvoid vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;\n\n/*\n * Only available when configUSE_TICKLESS_IDLE is set to 1.\n * If tickless mode is being used, or a low power mode is implemented, then\n * the tick interrupt will not execute during idle periods.  When this is the\n * case, the tick count value maintained by the scheduler needs to be kept up\n * to date with the actual execution time by being skipped forward by a time\n * equal to the idle period.\n */\nvoid vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;\n\n/*\n * Only available when configUSE_TICKLESS_IDLE is set to 1.\n * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port\n * specific sleep function to determine if it is ok to proceed with the sleep,\n * and if it is ok to proceed, if it is ok to sleep indefinitely.\n *\n * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only\n * called with the scheduler suspended, not from within a critical section.  It\n * is therefore possible for an interrupt to request a context switch between\n * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being\n * entered.  eTaskConfirmSleepModeStatus() should be called from a short\n * critical section between the timer being stopped and the sleep mode being\n * entered to ensure it is ok to proceed into the sleep mode.\n */\neSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Increment the mutex held count when a mutex is\n * taken and return the handle of the task that has taken the mutex.\n */\nTaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial\n * section.\n */\nvoid vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;\n\n\n#ifdef __cplusplus\n}\n#endif\n#endif /* INC_TASK_H */\n\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/include/timers.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#ifndef TIMERS_H\n#define TIMERS_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include timers.h\"\n#endif\n\n/*lint -save -e537 This headers are only multiply included if the application code\nhappens to also be including task.h. */\n#include \"task.h\"\n/*lint -restore */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * MACROS AND DEFINITIONS\n *----------------------------------------------------------*/\n\n/* IDs for commands that can be sent/received on the timer queue.  These are to\nbe used solely through the macros that make up the public software timer API,\nas defined below.  The commands that are sent from interrupts must use the\nhighest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task\nor interrupt version of the queue send function should be used. */\n#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR \t( ( BaseType_t ) -2 )\n#define tmrCOMMAND_EXECUTE_CALLBACK\t\t\t\t( ( BaseType_t ) -1 )\n#define tmrCOMMAND_START_DONT_TRACE\t\t\t\t( ( BaseType_t ) 0 )\n#define tmrCOMMAND_START\t\t\t\t\t    ( ( BaseType_t ) 1 )\n#define tmrCOMMAND_RESET\t\t\t\t\t\t( ( BaseType_t ) 2 )\n#define tmrCOMMAND_STOP\t\t\t\t\t\t\t( ( BaseType_t ) 3 )\n#define tmrCOMMAND_CHANGE_PERIOD\t\t\t\t( ( BaseType_t ) 4 )\n#define tmrCOMMAND_DELETE\t\t\t\t\t\t( ( BaseType_t ) 5 )\n\n#define tmrFIRST_FROM_ISR_COMMAND\t\t\t\t( ( BaseType_t ) 6 )\n#define tmrCOMMAND_START_FROM_ISR\t\t\t\t( ( BaseType_t ) 6 )\n#define tmrCOMMAND_RESET_FROM_ISR\t\t\t\t( ( BaseType_t ) 7 )\n#define tmrCOMMAND_STOP_FROM_ISR\t\t\t\t( ( BaseType_t ) 8 )\n#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR\t\t( ( BaseType_t ) 9 )\n\n\n/**\n * Type by which software timers are referenced.  For example, a call to\n * xTimerCreate() returns an TimerHandle_t variable that can then be used to\n * reference the subject timer in calls to other software timer API functions\n * (for example, xTimerStart(), xTimerReset(), etc.).\n */\nstruct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */\ntypedef struct tmrTimerControl * TimerHandle_t;\n\n/*\n * Defines the prototype to which timer callback functions must conform.\n */\ntypedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );\n\n/*\n * Defines the prototype to which functions used with the\n * xTimerPendFunctionCallFromISR() function must conform.\n */\ntypedef void (*PendedFunction_t)( void *, uint32_t );\n\n/**\n * TimerHandle_t xTimerCreate( \tconst char * const pcTimerName,\n * \t\t\t\t\t\t\t\tTickType_t xTimerPeriodInTicks,\n * \t\t\t\t\t\t\t\tUBaseType_t uxAutoReload,\n * \t\t\t\t\t\t\t\tvoid * pvTimerID,\n * \t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction );\n *\n * Creates a new software timer instance, and returns a handle by which the\n * created software timer can be referenced.\n *\n * Internally, within the FreeRTOS implementation, software timers use a block\n * of memory, in which the timer data structure is stored.  If a software timer\n * is created using xTimerCreate() then the required memory is automatically\n * dynamically allocated inside the xTimerCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a software timer is created using\n * xTimerCreateStatic() then the application writer must provide the memory that\n * will get used by the software timer.  xTimerCreateStatic() therefore allows a\n * software timer to be created without using any dynamic memory allocation.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a\n * timer into the active state.\n *\n * @param pcTimerName A text name that is assigned to the timer.  This is done\n * purely to assist debugging.  The kernel itself only ever references a timer\n * by its handle, and never by its name.\n *\n * @param xTimerPeriodInTicks The timer period.  The time is defined in tick\n * periods so the constant portTICK_PERIOD_MS can be used to convert a time that\n * has been specified in milliseconds.  For example, if the timer must expire\n * after 100 ticks, then xTimerPeriodInTicks should be set to 100.\n * Alternatively, if the timer must expire after 500ms, then xPeriod can be set\n * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or\n * equal to 1000.\n *\n * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.\n * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n *\n * @param pvTimerID An identifier that is assigned to the timer being created.\n * Typically this would be used in the timer callback function to identify which\n * timer expired when the same callback function is assigned to more than one\n * timer.\n *\n * @param pxCallbackFunction The function to call when the timer expires.\n * Callback functions must have the prototype defined by TimerCallbackFunction_t,\n * which is\t\"void vCallbackFunction( TimerHandle_t xTimer );\".\n *\n * @return If the timer is successfully created then a handle to the newly\n * created timer is returned.  If the timer cannot be created (because either\n * there is insufficient FreeRTOS heap remaining to allocate the timer\n * structures, or the timer period was set to 0) then NULL is returned.\n *\n * Example usage:\n * @verbatim\n * #define NUM_TIMERS 5\n *\n * // An array to hold handles to the created timers.\n * TimerHandle_t xTimers[ NUM_TIMERS ];\n *\n * // An array to hold a count of the number of times each timer expires.\n * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };\n *\n * // Define a callback function that will be used by multiple timer instances.\n * // The callback function does nothing but count the number of times the\n * // associated timer expires, and stop the timer once the timer has expired\n * // 10 times.\n * void vTimerCallback( TimerHandle_t pxTimer )\n * {\n * int32_t lArrayIndex;\n * const int32_t xMaxExpiryCountBeforeStopping = 10;\n *\n * \t   // Optionally do something if the pxTimer parameter is NULL.\n * \t   configASSERT( pxTimer );\n *\n *     // Which timer expired?\n *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );\n *\n *     // Increment the number of times that pxTimer has expired.\n *     lExpireCounters[ lArrayIndex ] += 1;\n *\n *     // If the timer has expired 10 times then stop it from running.\n *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )\n *     {\n *         // Do not use a block time if calling a timer API function from a\n *         // timer callback function, as doing so could cause a deadlock!\n *         xTimerStop( pxTimer, 0 );\n *     }\n * }\n *\n * void main( void )\n * {\n * int32_t x;\n *\n *     // Create then start some timers.  Starting the timers before the scheduler\n *     // has been started means the timers will start running immediately that\n *     // the scheduler starts.\n *     for( x = 0; x < NUM_TIMERS; x++ )\n *     {\n *         xTimers[ x ] = xTimerCreate(    \"Timer\",       // Just a text name, not used by the kernel.\n *                                         ( 100 * x ),   // The timer period in ticks.\n *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.\n *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.\n *                                         vTimerCallback // Each timer calls the same callback when it expires.\n *                                     );\n *\n *         if( xTimers[ x ] == NULL )\n *         {\n *             // The timer was not created.\n *         }\n *         else\n *         {\n *             // Start the timer.  No block time is specified, and even if one was\n *             // it would be ignored because the scheduler has not yet been\n *             // started.\n *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )\n *             {\n *                 // The timer could not be set into the Active state.\n *             }\n *         }\n *     }\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timers running as they have already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tTimerHandle_t xTimerCreate(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,\n * \t\t\t\t\t\t\t\t\tTickType_t xTimerPeriodInTicks,\n * \t\t\t\t\t\t\t\t\tUBaseType_t uxAutoReload,\n * \t\t\t\t\t\t\t\t\tvoid * pvTimerID,\n * \t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n *\t\t\t\t\t\t\t\t\tStaticTimer_t *pxTimerBuffer );\n *\n * Creates a new software timer instance, and returns a handle by which the\n * created software timer can be referenced.\n *\n * Internally, within the FreeRTOS implementation, software timers use a block\n * of memory, in which the timer data structure is stored.  If a software timer\n * is created using xTimerCreate() then the required memory is automatically\n * dynamically allocated inside the xTimerCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a software timer is created using\n * xTimerCreateStatic() then the application writer must provide the memory that\n * will get used by the software timer.  xTimerCreateStatic() therefore allows a\n * software timer to be created without using any dynamic memory allocation.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a\n * timer into the active state.\n *\n * @param pcTimerName A text name that is assigned to the timer.  This is done\n * purely to assist debugging.  The kernel itself only ever references a timer\n * by its handle, and never by its name.\n *\n * @param xTimerPeriodInTicks The timer period.  The time is defined in tick\n * periods so the constant portTICK_PERIOD_MS can be used to convert a time that\n * has been specified in milliseconds.  For example, if the timer must expire\n * after 100 ticks, then xTimerPeriodInTicks should be set to 100.\n * Alternatively, if the timer must expire after 500ms, then xPeriod can be set\n * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or\n * equal to 1000.\n *\n * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.\n * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n *\n * @param pvTimerID An identifier that is assigned to the timer being created.\n * Typically this would be used in the timer callback function to identify which\n * timer expired when the same callback function is assigned to more than one\n * timer.\n *\n * @param pxCallbackFunction The function to call when the timer expires.\n * Callback functions must have the prototype defined by TimerCallbackFunction_t,\n * which is \"void vCallbackFunction( TimerHandle_t xTimer );\".\n *\n * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which\n * will be then be used to hold the software timer's data structures, removing\n * the need for the memory to be allocated dynamically.\n *\n * @return If the timer is created then a handle to the created timer is\n * returned.  If pxTimerBuffer was NULL then NULL is returned.\n *\n * Example usage:\n * @verbatim\n *\n * // The buffer used to hold the software timer's data structure.\n * static StaticTimer_t xTimerBuffer;\n *\n * // A variable that will be incremented by the software timer's callback\n * // function.\n * UBaseType_t uxVariableToIncrement = 0;\n *\n * // A software timer callback function that increments a variable passed to\n * // it when the software timer was created.  After the 5th increment the\n * // callback function stops the software timer.\n * static void prvTimerCallback( TimerHandle_t xExpiredTimer )\n * {\n * UBaseType_t *puxVariableToIncrement;\n * BaseType_t xReturned;\n *\n *     // Obtain the address of the variable to increment from the timer ID.\n *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );\n *\n *     // Increment the variable to show the timer callback has executed.\n *     ( *puxVariableToIncrement )++;\n *\n *     // If this callback has executed the required number of times, stop the\n *     // timer.\n *     if( *puxVariableToIncrement == 5 )\n *     {\n *         // This is called from a timer callback so must not block.\n *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );\n *     }\n * }\n *\n *\n * void main( void )\n * {\n *     // Create the software time.  xTimerCreateStatic() has an extra parameter\n *     // than the normal xTimerCreate() API function.  The parameter is a pointer\n *     // to the StaticTimer_t structure that will hold the software timer\n *     // structure.  If the parameter is passed as NULL then the structure will be\n *     // allocated dynamically, just as if xTimerCreate() had been called.\n *     xTimer = xTimerCreateStatic( \"T1\",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.\n *                                  xTimerPeriod,     // The period of the timer in ticks.\n *                                  pdTRUE,           // This is an auto-reload timer.\n *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function\n *                                  prvTimerCallback, // The function to execute when the timer expires.\n *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.\n *\n *     // The scheduler has not started yet so a block time is not used.\n *     xReturned = xTimerStart( xTimer, 0 );\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timers running as they have already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tTimerHandle_t xTimerCreateStatic(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n\t\t\t\t\t\t\t\t\t\tStaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * void *pvTimerGetTimerID( TimerHandle_t xTimer );\n *\n * Returns the ID assigned to the timer.\n *\n * IDs are assigned to timers using the pvTimerID parameter of the call to\n * xTimerCreated() that was used to create the timer, and by calling the\n * vTimerSetTimerID() API function.\n *\n * If the same callback function is assigned to multiple timers then the timer\n * ID can be used as time specific (timer local) storage.\n *\n * @param xTimer The timer being queried.\n *\n * @return The ID assigned to the timer being queried.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n */\nvoid *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );\n *\n * Sets the ID assigned to the timer.\n *\n * IDs are assigned to timers using the pvTimerID parameter of the call to\n * xTimerCreated() that was used to create the timer.\n *\n * If the same callback function is assigned to multiple timers then the timer\n * ID can be used as time specific (timer local) storage.\n *\n * @param xTimer The timer being updated.\n *\n * @param pvNewID The ID to assign to the timer.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n */\nvoid vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;\n\n/**\n * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );\n *\n * Queries a timer to see if it is active or dormant.\n *\n * A timer will be dormant if:\n *     1) It has been created but not started, or\n *     2) It is an expired one-shot timer that has not been restarted.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the\n * active state.\n *\n * @param xTimer The timer being queried.\n *\n * @return pdFALSE will be returned if the timer is dormant.  A value other than\n * pdFALSE will be returned if the timer is active.\n *\n * Example usage:\n * @verbatim\n * // This function assumes xTimer has already been created.\n * void vAFunction( TimerHandle_t xTimer )\n * {\n *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently \"if( xTimerIsTimerActive( xTimer ) )\"\n *     {\n *         // xTimer is active, do something.\n *     }\n *     else\n *     {\n *         // xTimer is not active, do something else.\n *     }\n * }\n * @endverbatim\n */\nBaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );\n *\n * Simply returns the handle of the timer service/daemon task.  It it not valid\n * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.\n */\nTaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/**\n * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerStart() starts a timer that was previously created using the\n * xTimerCreate() API function.  If the timer had already been started and was\n * already in the active state, then xTimerStart() has equivalent functionality\n * to the xTimerReset() API function.\n *\n * Starting a timer ensures the timer is in the active state.  If the timer\n * is not stopped, deleted, or reset in the mean time, the callback function\n * associated with the timer will get called 'n' ticks after xTimerStart() was\n * called, where 'n' is the timers defined period.\n *\n * It is valid to call xTimerStart() before the scheduler has been started, but\n * when this is done the timer will not actually start until the scheduler is\n * started, and the timers expiry time will be relative to when the scheduler is\n * started, not relative to when xTimerStart() was called.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()\n * to be available.\n *\n * @param xTimer The handle of the timer being started/restarted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the start command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the start command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system, although the\n * timers expiry time is relative to when xTimerStart() is actually called.  The\n * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n *\n */\n#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerStop() stops a timer that was previously started using either of the\n * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),\n * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.\n *\n * Stopping a timer ensures the timer is not in the active state.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()\n * to be available.\n *\n * @param xTimer The handle of the timer being stopped.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the stop command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the stop command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n *\n */\n#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerChangePeriod( \tTimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\t\tTickType_t xNewPeriod,\n *\t\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerChangePeriod() changes the period of a timer that was previously\n * created using the xTimerCreate() API function.\n *\n * xTimerChangePeriod() can be called to change the period of an active or\n * dormant state timer.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for\n * xTimerChangePeriod() to be available.\n *\n * @param xTimer The handle of the timer that is having its period changed.\n *\n * @param xNewPeriod The new period for xTimer. Timer periods are specified in\n * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time\n * that has been specified in milliseconds.  For example, if the timer must\n * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,\n * if the timer must expire after 500ms, then xNewPeriod can be set to\n * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than\n * or equal to 1000.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the change period command to be\n * successfully sent to the timer command queue, should the queue already be\n * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if\n * xTimerChangePeriod() is called before the scheduler is started.\n *\n * @return pdFAIL will be returned if the change period command could not be\n * sent to the timer command queue even after xTicksToWait ticks had passed.\n * pdPASS will be returned if the command was successfully sent to the timer\n * command queue.  When the command is actually processed will depend on the\n * priority of the timer service/daemon task relative to other tasks in the\n * system.  The timer service/daemon task priority is set by the\n * configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This function assumes xTimer has already been created.  If the timer\n * // referenced by xTimer is already active when it is called, then the timer\n * // is deleted.  If the timer referenced by xTimer is not active when it is\n * // called, then the period of the timer is set to 500ms and the timer is\n * // started.\n * void vAFunction( TimerHandle_t xTimer )\n * {\n *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently \"if( xTimerIsTimerActive( xTimer ) )\"\n *     {\n *         // xTimer is already active - delete it.\n *         xTimerDelete( xTimer );\n *     }\n *     else\n *     {\n *         // xTimer is not active, change its period to 500ms.  This will also\n *         // cause the timer to start.  Block for a maximum of 100 ticks if the\n *         // change period command cannot immediately be sent to the timer\n *         // command queue.\n *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )\n *         {\n *             // The command was successfully sent.\n *         }\n *         else\n *         {\n *             // The command could not be sent, even after waiting for 100 ticks\n *             // to pass.  Take appropriate action here.\n *         }\n *     }\n * }\n * @endverbatim\n */\n #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerDelete() deletes a timer that was previously created using the\n * xTimerCreate() API function.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for\n * xTimerDelete() to be available.\n *\n * @param xTimer The handle of the timer being deleted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the delete command to be\n * successfully sent to the timer command queue, should the queue already be\n * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()\n * is called before the scheduler is started.\n *\n * @return pdFAIL will be returned if the delete command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerChangePeriod() API function example usage scenario.\n */\n#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerReset() re-starts a timer that was previously created using the\n * xTimerCreate() API function.  If the timer had already been started and was\n * already in the active state, then xTimerReset() will cause the timer to\n * re-evaluate its expiry time so that it is relative to when xTimerReset() was\n * called.  If the timer was in the dormant state then xTimerReset() has\n * equivalent functionality to the xTimerStart() API function.\n *\n * Resetting a timer ensures the timer is in the active state.  If the timer\n * is not stopped, deleted, or reset in the mean time, the callback function\n * associated with the timer will get called 'n' ticks after xTimerReset() was\n * called, where 'n' is the timers defined period.\n *\n * It is valid to call xTimerReset() before the scheduler has been started, but\n * when this is done the timer will not actually start until the scheduler is\n * started, and the timers expiry time will be relative to when the scheduler is\n * started, not relative to when xTimerReset() was called.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()\n * to be available.\n *\n * @param xTimer The handle of the timer being reset/started/restarted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the reset command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the reset command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system, although the\n * timers expiry time is relative to when xTimerStart() is actually called.  The\n * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n * @verbatim\n * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer.\n *\n * TimerHandle_t xBacklightTimer = NULL;\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press event handler.\n * void vKeyPressEventHandler( char cKey )\n * {\n *     // Ensure the LCD back-light is on, then reset the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  Wait 10 ticks for the command to be successfully sent\n *     // if it cannot be sent immediately.\n *     vSetBacklightState( BACKLIGHT_ON );\n *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )\n *     {\n *         // The reset command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n * }\n *\n * void main( void )\n * {\n * int32_t x;\n *\n *     // Create then start the one-shot timer that is responsible for turning\n *     // the back-light off if no keys are pressed within a 5 second period.\n *     xBacklightTimer = xTimerCreate( \"BacklightTimer\",           // Just a text name, not used by the kernel.\n *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.\n *                                     pdFALSE,                    // The timer is a one-shot timer.\n *                                     0,                          // The id is not used by the callback so can take any value.\n *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.\n *                                   );\n *\n *     if( xBacklightTimer == NULL )\n *     {\n *         // The timer was not created.\n *     }\n *     else\n *     {\n *         // Start the timer.  No block time is specified, and even if one was\n *         // it would be ignored because the scheduler has not yet been\n *         // started.\n *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )\n *         {\n *             // The timer could not be set into the Active state.\n *         }\n *     }\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timer running as it has already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerStartFromISR( \tTimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerStart() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer being started/restarted.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerStartFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerStartFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerStartFromISR() function.  If\n * xTimerStartFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the start command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system, although the timers expiry time is\n * relative to when xTimerStartFromISR() is actually called.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xBacklightTimer has already been created.  When a\n * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer, and unlike the example given for\n * // the xTimerReset() function, the key press event handler is an interrupt\n * // service routine.\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press interrupt service routine.\n * void vKeyPressEventInterruptHandler( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // Ensure the LCD back-light is on, then restart the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  This is an interrupt service routine so can only\n *     // call FreeRTOS API functions that end in \"FromISR\".\n *     vSetBacklightState( BACKLIGHT_ON );\n *\n *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here\n *     // as both cause the timer to re-calculate its expiry time.\n *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\n *     // declared (in this function).\n *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The start command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerStopFromISR( \tTimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerStop() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer being stopped.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerStopFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerStopFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerStopFromISR() function.  If\n * xTimerStopFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the stop command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system.  The timer service/daemon task\n * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xTimer has already been created and started.  When\n * // an interrupt occurs, the timer should be simply stopped.\n *\n * // The interrupt service routine that stops the timer.\n * void vAnExampleInterruptServiceRoutine( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // The interrupt has occurred - simply stop the timer.\n *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\n *     // (within this function).  As this is an interrupt service routine, only\n *     // FreeRTOS API functions that end in \"FromISR\" can be used.\n *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The stop command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\t\t TickType_t xNewPeriod,\n *\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerChangePeriod() that can be called from an interrupt\n * service routine.\n *\n * @param xTimer The handle of the timer that is having its period changed.\n *\n * @param xNewPeriod The new period for xTimer. Timer periods are specified in\n * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time\n * that has been specified in milliseconds.  For example, if the timer must\n * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,\n * if the timer must expire after 500ms, then xNewPeriod can be set to\n * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than\n * or equal to 1000.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the\n * timer command queue, so has the potential to transition the timer service/\n * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()\n * causes the timer service/daemon task to leave the Blocked state, and the\n * timer service/daemon task has a priority equal to or greater than the\n * currently executing task (the task that was interrupted), then\n * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the\n * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets\n * this value to pdTRUE then a context switch should be performed before the\n * interrupt exits.\n *\n * @return pdFAIL will be returned if the command to change the timers period\n * could not be sent to the timer command queue.  pdPASS will be returned if the\n * command was successfully sent to the timer command queue.  When the command\n * is actually processed will depend on the priority of the timer service/daemon\n * task relative to other tasks in the system.  The timer service/daemon task\n * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xTimer has already been created and started.  When\n * // an interrupt occurs, the period of xTimer should be changed to 500ms.\n *\n * // The interrupt service routine that changes the period of xTimer.\n * void vAnExampleInterruptServiceRoutine( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // The interrupt has occurred - change the period of xTimer to 500ms.\n *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\n *     // (within this function).  As this is an interrupt service routine, only\n *     // FreeRTOS API functions that end in \"FromISR\" can be used.\n *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The command to change the timers period was not executed\n *         // successfully.  Take appropriate action here.\n *     }\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerResetFromISR( \tTimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerReset() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer that is to be started, reset, or\n * restarted.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerResetFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerResetFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerResetFromISR() function.  If\n * xTimerResetFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the reset command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system, although the timers expiry time is\n * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon\n * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xBacklightTimer has already been created.  When a\n * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer, and unlike the example given for\n * // the xTimerReset() function, the key press event handler is an interrupt\n * // service routine.\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press interrupt service routine.\n * void vKeyPressEventInterruptHandler( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // Ensure the LCD back-light is on, then reset the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  This is an interrupt service routine so can only\n *     // call FreeRTOS API functions that end in \"FromISR\".\n *     vSetBacklightState( BACKLIGHT_ON );\n *\n *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here\n *     // as both cause the timer to re-calculate its expiry time.\n *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\n *     // declared (in this function).\n *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The reset command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\n\n\n/**\n * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,\n *                                          void *pvParameter1,\n *                                          uint32_t ulParameter2,\n *                                          BaseType_t *pxHigherPriorityTaskWoken );\n *\n *\n * Used from application interrupt service routines to defer the execution of a\n * function to the RTOS daemon task (the timer service task, hence this function\n * is implemented in timers.c and is prefixed with 'Timer').\n *\n * Ideally an interrupt service routine (ISR) is kept as short as possible, but\n * sometimes an ISR either has a lot of processing to do, or needs to perform\n * processing that is not deterministic.  In these cases\n * xTimerPendFunctionCallFromISR() can be used to defer processing of a function\n * to the RTOS daemon task.\n *\n * A mechanism is provided that allows the interrupt to return directly to the\n * task that will subsequently execute the pended callback function.  This\n * allows the callback function to execute contiguously in time with the\n * interrupt - just as if the callback had executed in the interrupt itself.\n *\n * @param xFunctionToPend The function to execute from the timer service/\n * daemon task.  The function must conform to the PendedFunction_t\n * prototype.\n *\n * @param pvParameter1 The value of the callback function's first parameter.\n * The parameter has a void * type to allow it to be used to pass any type.\n * For example, unsigned longs can be cast to a void *, or the void * can be\n * used to point to a structure.\n *\n * @param ulParameter2 The value of the callback function's second parameter.\n *\n * @param pxHigherPriorityTaskWoken As mentioned above, calling this function\n * will result in a message being sent to the timer daemon task.  If the\n * priority of the timer daemon task (which is set using\n * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of\n * the currently running task (the task the interrupt interrupted) then\n * *pxHigherPriorityTaskWoken will be set to pdTRUE within\n * xTimerPendFunctionCallFromISR(), indicating that a context switch should be\n * requested before the interrupt exits.  For that reason\n * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the\n * example code below.\n *\n * @return pdPASS is returned if the message was successfully sent to the\n * timer daemon task, otherwise pdFALSE is returned.\n *\n * Example usage:\n * @verbatim\n *\n *\t// The callback function that will execute in the context of the daemon task.\n *  // Note callback functions must all use this same prototype.\n *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )\n *\t{\n *\t\tBaseType_t xInterfaceToService;\n *\n *\t\t// The interface that requires servicing is passed in the second\n *      // parameter.  The first parameter is not used in this case.\n *\t\txInterfaceToService = ( BaseType_t ) ulParameter2;\n *\n *\t\t// ...Perform the processing here...\n *\t}\n *\n *\t// An ISR that receives data packets from multiple interfaces\n *  void vAnISR( void )\n *\t{\n *\t\tBaseType_t xInterfaceToService, xHigherPriorityTaskWoken;\n *\n *\t\t// Query the hardware to determine which interface needs processing.\n *\t\txInterfaceToService = prvCheckInterfaces();\n *\n *      // The actual processing is to be deferred to a task.  Request the\n *      // vProcessInterface() callback function is executed, passing in the\n *\t\t// number of the interface that needs processing.  The interface to\n *\t\t// service is passed in the second parameter.  The first parameter is\n *\t\t// not used in this case.\n *\t\txHigherPriorityTaskWoken = pdFALSE;\n *\t\txTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );\n *\n *\t\t// If xHigherPriorityTaskWoken is now set to pdTRUE then a context\n *\t\t// switch should be requested.  The macro used is port specific and will\n *\t\t// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to\n *\t\t// the documentation page for the port being used.\n *\t\tportYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n *\n *\t}\n * @endverbatim\n */\nBaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n /**\n  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,\n  *                                    void *pvParameter1,\n  *                                    uint32_t ulParameter2,\n  *                                    TickType_t xTicksToWait );\n  *\n  *\n  * Used to defer the execution of a function to the RTOS daemon task (the timer\n  * service task, hence this function is implemented in timers.c and is prefixed\n  * with 'Timer').\n  *\n  * @param xFunctionToPend The function to execute from the timer service/\n  * daemon task.  The function must conform to the PendedFunction_t\n  * prototype.\n  *\n  * @param pvParameter1 The value of the callback function's first parameter.\n  * The parameter has a void * type to allow it to be used to pass any type.\n  * For example, unsigned longs can be cast to a void *, or the void * can be\n  * used to point to a structure.\n  *\n  * @param ulParameter2 The value of the callback function's second parameter.\n  *\n  * @param xTicksToWait Calling this function will result in a message being\n  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of\n  * time the calling task should remain in the Blocked state (so not using any\n  * processing time) for space to become available on the timer queue if the\n  * queue is found to be full.\n  *\n  * @return pdPASS is returned if the message was successfully sent to the\n  * timer daemon task, otherwise pdFALSE is returned.\n  *\n  */\nBaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * const char * const pcTimerGetName( TimerHandle_t xTimer );\n *\n * Returns the name that was assigned to a timer when the timer was created.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return The name assigned to the timer specified by the xTimer parameter.\n */\nconst char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );\n *\n * Updates a timer to be either an autoreload timer, in which case the timer\n * automatically resets itself each time it expires, or a one shot timer, in\n * which case the timer will only expire once unless it is manually restarted.\n *\n * @param xTimer The handle of the timer being updated.\n *\n * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the timer's period (see the\n * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If\n * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n */\nvoid vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;\n\n/**\n * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );\n *\n * Returns the period of a timer.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return The period of the timer in ticks.\n */\nTickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );\n*\n* Returns the time in ticks at which the timer will expire.  If this is less\n* than the current tick count then the expiry time has overflowed from the\n* current time.\n*\n* @param xTimer The handle of the timer being queried.\n*\n* @return If the timer is running then the time in ticks at which the timer\n* will next expire is returned.  If the timer is not running then the return\n* value is undefined.\n*/\nTickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/*\n * Functions beyond this part are not part of the public API and are intended\n * for use by the kernel only.\n */\nBaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;\nBaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\tvoid vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;\n\tUBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n#endif /* TIMERS_H */\n\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/list.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#include <stdlib.h>\n#include \"FreeRTOS.h\"\n#include \"list.h\"\n\n/*-----------------------------------------------------------\n * PUBLIC LIST API documented in list.h\n *----------------------------------------------------------*/\n\nvoid vListInitialise( List_t * const pxList )\n{\n\t/* The list structure contains a list item which is used to mark the\n\tend of the list.  To initialise the list the list end is inserted\n\tas the only list entry. */\n\tpxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );\t\t\t/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\n\t/* The list end value is the highest possible value in the list to\n\tensure it remains at the end of the list. */\n\tpxList->xListEnd.xItemValue = portMAX_DELAY;\n\n\t/* The list end next and previous pointers point to itself so we know\n\twhen the list is empty. */\n\tpxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );\t/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\tpxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\n\tpxList->uxNumberOfItems = ( UBaseType_t ) 0U;\n\n\t/* Write known values into the list if\n\tconfigUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tlistSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );\n\tlistSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInitialiseItem( ListItem_t * const pxItem )\n{\n\t/* Make sure the list item is not recorded as being on a list. */\n\tpxItem->pxContainer = NULL;\n\n\t/* Write known values into the list item if\n\tconfigUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tlistSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\n\tlistSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )\n{\nListItem_t * const pxIndex = pxList->pxIndex;\n\n\t/* Only effective when configASSERT() is also defined, these tests may catch\n\tthe list data structures being overwritten in memory.  They will not catch\n\tdata errors caused by incorrect configuration or use of FreeRTOS. */\n\tlistTEST_LIST_INTEGRITY( pxList );\n\tlistTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\n\n\t/* Insert a new list item into pxList, but rather than sort the list,\n\tmakes the new list item the last item to be removed by a call to\n\tlistGET_OWNER_OF_NEXT_ENTRY(). */\n\tpxNewListItem->pxNext = pxIndex;\n\tpxNewListItem->pxPrevious = pxIndex->pxPrevious;\n\n\t/* Only used during decision coverage testing. */\n\tmtCOVERAGE_TEST_DELAY();\n\n\tpxIndex->pxPrevious->pxNext = pxNewListItem;\n\tpxIndex->pxPrevious = pxNewListItem;\n\n\t/* Remember which list the item is in. */\n\tpxNewListItem->pxContainer = pxList;\n\n\t( pxList->uxNumberOfItems )++;\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )\n{\nListItem_t *pxIterator;\nconst TickType_t xValueOfInsertion = pxNewListItem->xItemValue;\n\n\t/* Only effective when configASSERT() is also defined, these tests may catch\n\tthe list data structures being overwritten in memory.  They will not catch\n\tdata errors caused by incorrect configuration or use of FreeRTOS. */\n\tlistTEST_LIST_INTEGRITY( pxList );\n\tlistTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\n\n\t/* Insert the new list item into the list, sorted in xItemValue order.\n\n\tIf the list already contains a list item with the same item value then the\n\tnew list item should be placed after it.  This ensures that TCBs which are\n\tstored in ready lists (all of which have the same xItemValue value) get a\n\tshare of the CPU.  However, if the xItemValue is the same as the back marker\n\tthe iteration loop below will not end.  Therefore the value is checked\n\tfirst, and the algorithm slightly modified if necessary. */\n\tif( xValueOfInsertion == portMAX_DELAY )\n\t{\n\t\tpxIterator = pxList->xListEnd.pxPrevious;\n\t}\n\telse\n\t{\n\t\t/* *** NOTE ***********************************************************\n\t\tIf you find your application is crashing here then likely causes are\n\t\tlisted below.  In addition see https://www.freertos.org/FAQHelp.html for\n\t\tmore tips, and ensure configASSERT() is defined!\n\t\thttps://www.freertos.org/a00110.html#configASSERT\n\n\t\t\t1) Stack overflow -\n\t\t\t   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html\n\t\t\t2) Incorrect interrupt priority assignment, especially on Cortex-M\n\t\t\t   parts where numerically high priority values denote low actual\n\t\t\t   interrupt priorities, which can seem counter intuitive.  See\n\t\t\t   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition\n\t\t\t   of configMAX_SYSCALL_INTERRUPT_PRIORITY on\n\t\t\t   https://www.freertos.org/a00110.html\n\t\t\t3) Calling an API function from within a critical section or when\n\t\t\t   the scheduler is suspended, or calling an API function that does\n\t\t\t   not end in \"FromISR\" from an interrupt.\n\t\t\t4) Using a queue or semaphore before it has been initialised or\n\t\t\t   before the scheduler has been started (are interrupts firing\n\t\t\t   before vTaskStartScheduler() has been called?).\n\t\t**********************************************************************/\n\n\t\tfor( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */\n\t\t{\n\t\t\t/* There is nothing to do here, just iterating to the wanted\n\t\t\tinsertion position. */\n\t\t}\n\t}\n\n\tpxNewListItem->pxNext = pxIterator->pxNext;\n\tpxNewListItem->pxNext->pxPrevious = pxNewListItem;\n\tpxNewListItem->pxPrevious = pxIterator;\n\tpxIterator->pxNext = pxNewListItem;\n\n\t/* Remember which list the item is in.  This allows fast removal of the\n\titem later. */\n\tpxNewListItem->pxContainer = pxList;\n\n\t( pxList->uxNumberOfItems )++;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )\n{\n/* The list item knows which list it is in.  Obtain the list from the list\nitem. */\nList_t * const pxList = pxItemToRemove->pxContainer;\n\n\tpxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\n\tpxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\n\n\t/* Only used during decision coverage testing. */\n\tmtCOVERAGE_TEST_DELAY();\n\n\t/* Make sure the index is left pointing to a valid item. */\n\tif( pxList->pxIndex == pxItemToRemove )\n\t{\n\t\tpxList->pxIndex = pxItemToRemove->pxPrevious;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tpxItemToRemove->pxContainer = NULL;\n\t( pxList->uxNumberOfItems )--;\n\n\treturn pxList->uxNumberOfItems;\n}\n/*-----------------------------------------------------------*/\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/Common/mpu_wrappers.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * Implementation of the wrapper functions used to raise the processor privilege\n * before calling a standard FreeRTOS API function.\n */\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n#include \"timers.h\"\n#include \"event_groups.h\"\n#include \"stream_buffer.h\"\n#include \"mpu_prototypes.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/**\n * @brief Calls the port specific code to raise the privilege.\n *\n * @return pdFALSE if privilege was raised, pdTRUE otherwise.\n */\nBaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;\n\n/**\n * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\n * code to reset the privilege, otherwise does nothing.\n */\nvoid vPortResetPrivilege( BaseType_t xRunningPrivileged );\n/*-----------------------------------------------------------*/\n\nBaseType_t xPortRaisePrivilege( void ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged;\n\n\t/* Check whether the processor is already privileged. */\n\txRunningPrivileged = portIS_PRIVILEGED();\n\n\t/* If the processor is not already privileged, raise privilege. */\n\tif( xRunningPrivileged != pdTRUE )\n\t{\n\t\tportRAISE_PRIVILEGE();\n\t}\n\n\treturn xRunningPrivileged;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortResetPrivilege( BaseType_t xRunningPrivileged )\n{\n\tif( xRunningPrivileged != pdTRUE )\n\t{\n\t\tportRESET_PRIVILEGE();\n\t}\n}\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tBaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif /* conifgSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tBaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif /* conifgSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tBaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tTaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTaskHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nvoid MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tvTaskAllocateMPURegions( xTask, xRegions );\n\tvPortResetPrivilege( xRunningPrivileged );\n}\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelete == 1 )\n\tvoid MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskDelete( pxTaskToDelete );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelayUntil == 1 )\n\tvoid MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskAbortDelay == 1 )\n\tBaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskAbortDelay( xTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelay == 1 )\n\tvoid MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskDelay( xTicksToDelay );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\n\tUBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tUBaseType_t uxReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tuxReturn = uxTaskPriorityGet( pxTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn uxReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskPrioritySet == 1 )\n\tvoid MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskPrioritySet( pxTask, uxNewPriority );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_eTaskGetState == 1 )\n\teTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\teTaskState eReturn;\n\n\t\teReturn = eTaskGetState( pxTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn eReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\tvoid MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\n\tTaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTaskHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskGetIdleTaskHandle();\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\tvoid MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskSuspend( pxTaskToSuspend );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\tvoid MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskResume( pxTaskToResume );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\nvoid MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tvTaskSuspendAll();\n\tvPortResetPrivilege( xRunningPrivileged );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xTaskResumeAll();\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */\n{\nTickType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xTaskGetTickCount();\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */\n{\nUBaseType_t uxReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tuxReturn = uxTaskGetNumberOfTasks();\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nchar * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */\n{\nchar *pcReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tpcReturn = pcTaskGetName( xTaskToQuery );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn pcReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\tTaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTaskHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskGetHandle( pcNameToQuery );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\tvoid MPU_vTaskList( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskList( pcWriteBuffer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\tvoid MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskGetRunTimeStats( pcWriteBuffer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )\n\tTickType_t MPU_xTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTickType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskGetIdleRunTimeCounter();\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\tvoid MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskSetApplicationTaskTag( xTask, pxTagValue );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\tTaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTaskHookFunction_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskGetApplicationTaskTag( xTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\tvoid MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\tvoid *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tvoid *pvReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tpvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn pvReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\tBaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\tUBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tUBaseType_t uxReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tuxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn uxReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\n\tUBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tUBaseType_t uxReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tuxReturn = uxTaskGetStackHighWaterMark( xTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn uxReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )\n\tconfigSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tconfigSTACK_DEPTH_TYPE uxReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tuxReturn = uxTaskGetStackHighWaterMark2( xTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn uxReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\n\tTaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTaskHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskGetCurrentTaskHandle();\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetSchedulerState == 1 )\n\tBaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskGetSchedulerState();\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\nvoid MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tvTaskSetTimeOutState( pxTimeOut );\n\tvPortResetPrivilege( xRunningPrivileged );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\tBaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskGenericNotify( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\tBaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\tuint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tuint32_t ulReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tulReturn = ulTaskNotifyTake( xClearCountOnExit, xTicksToWait );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn ulReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\tBaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTaskNotifyStateClear( xTask );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tQueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tQueueHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tQueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tQueueHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xQueueGenericReset( pxQueue, xNewQueue );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\nUBaseType_t uxReturn;\n\n\tuxReturn = uxQueueMessagesWaiting( pxQueue );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\nUBaseType_t uxReturn;\n\n\tuxReturn = uxQueueSpacesAvailable( xQueue );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\nBaseType_t xReturn;\n\n\txReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\nBaseType_t xReturn;\n\n\txReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\nBaseType_t xReturn;\n\n\txReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );\n\tvPortResetPrivilege( xRunningPrivileged );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n\tTaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\tvoid * xReturn;\n\n\t\txReturn = xQueueGetMutexHolder( xSemaphore );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\tQueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tQueueHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueCreateMutex( ucQueueType );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\tQueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tQueueHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\tQueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tQueueHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tQueueHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n\tBaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n\tBaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueGiveMutexRecursive( xMutex );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\tQueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tQueueSetHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueCreateSet( uxEventQueueLength );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\tQueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tQueueSetMemberHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\tBaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\tBaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if configQUEUE_REGISTRY_SIZE > 0\n\tvoid MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvQueueAddToRegistry( xQueue, pcName );\n\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if configQUEUE_REGISTRY_SIZE > 0\n\tvoid MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvQueueUnregisterQueue( xQueue );\n\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if configQUEUE_REGISTRY_SIZE > 0\n\tconst char *MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\tconst char *pcReturn;\n\n\t\tpcReturn = pcQueueGetName( xQueue );\n\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t\treturn pcReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\nvoid MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tvQueueDelete( xQueue );\n\n\tvPortResetPrivilege( xRunningPrivileged );\n}\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tvoid *MPU_pvPortMalloc( size_t xSize ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tvoid *pvReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tpvReturn = pvPortMalloc( xSize );\n\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn pvReturn;\n\t}\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tvoid MPU_vPortFree( void *pv ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvPortFree( pv );\n\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tvoid MPU_vPortInitialiseBlocks( void ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvPortInitialiseBlocks();\n\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tsize_t MPU_xPortGetFreeHeapSize( void ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tsize_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xPortGetFreeHeapSize();\n\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )\n\tTimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTimerHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )\n\tTimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTimerHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tvoid *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tvoid * pvReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tpvReturn = pvTimerGetTimerID( xTimer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn pvReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tvoid MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTimerSetTimerID( xTimer, pvNewID );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tBaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTimerIsTimerActive( xTimer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tTaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTaskHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTimerGetTimerDaemonTaskHandle();\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\n\tBaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tvoid MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tvTimerSetReloadMode( xTimer, uxAutoReload );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tconst char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tconst char * pcReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\tpcReturn = pcTimerGetName( xTimer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn pcReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tTickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTickType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTimerGetPeriod( xTimer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tTickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tTickType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTimerGetExpiryTime( xTimer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\tBaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tBaseType_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tEventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tEventGroupHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xEventGroupCreate();\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tEventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tEventGroupHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xEventGroupCreateStatic( pxEventGroupBuffer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\nEventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n{\nEventBits_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */\n{\nEventBits_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */\n{\nEventBits_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n{\nEventBits_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tvEventGroupDelete( xEventGroup );\n\tvPortResetPrivilege( xRunningPrivileged );\n}\n/*-----------------------------------------------------------*/\n\nsize_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n{\nsize_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n{\nsize_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */\n{\nsize_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tvStreamBufferDelete( xStreamBuffer );\n\tvPortResetPrivilege( xRunningPrivileged );\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferIsFull( xStreamBuffer );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferIsEmpty( xStreamBuffer );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferReset( xStreamBuffer );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n{\nsize_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferSpacesAvailable( xStreamBuffer );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n{\nsize_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferBytesAvailable( xStreamBuffer );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */\n{\nBaseType_t xReturn;\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\txReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );\n\tvPortResetPrivilege( xRunningPrivileged );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tStreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tStreamBufferHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tStreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */\n\t{\n\tStreamBufferHandle_t xReturn;\n\tBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\t\txReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer );\n\t\tvPortResetPrivilege( xRunningPrivileged );\n\n\t\treturn xReturn;\n\t}\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n\n/* Functions that the application writer wants to execute in privileged mode\ncan be defined in application_defined_privileged_functions.h.  The functions\nmust take the same format as those above whereby the privilege state on exit\nequals the privilege state on entry.  For example:\n\nvoid MPU_FunctionName( [parameters ] )\n{\nBaseType_t xRunningPrivileged = xPortRaisePrivilege();\n\n\tFunctionName( [parameters ] );\n\n\tvPortResetPrivilege( xRunningPrivileged );\n}\n*/\n\n#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1\n\t#include \"application_defined_privileged_functions.h\"\n#endif\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/GCC/ARM_CM4F/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*-----------------------------------------------------------\n * Implementation of functions defined in portable.h for the ARM CM4F port.\n *----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __VFP_FP__\n\t#error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#ifndef configSYSTICK_CLOCK_HZ\n\t#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\n\t/* Ensure the SysTick is clocked at the same frequency as the core. */\n\t#define portNVIC_SYSTICK_CLK_BIT\t( 1UL << 2UL )\n#else\n\t/* The way the SysTick is clocked is not modified in case it is not the same\n\tas the core. */\n\t#define portNVIC_SYSTICK_CLK_BIT\t( 0 )\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG\t\t\t( * ( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG\t\t\t( * ( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG\t( * ( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SYSPRI2_REG\t\t\t\t( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_INT_BIT\t\t\t( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT\t\t\t( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT\t\t( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT \t\t\t( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT\t\t( 1UL << 25UL )\n\n/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\nr0p1 port. */\n#define portCPUID\t\t\t\t\t\t\t( * ( ( volatile uint32_t * ) 0xE000ed00 ) )\n#define portCORTEX_M7_r0p1_ID\t\t\t\t( 0x410FC271UL )\n#define portCORTEX_M7_r0p0_ID\t\t\t\t( 0x410FC270UL )\n\n#define portNVIC_PENDSV_PRI\t\t\t\t\t( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI\t\t\t\t( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER\t\t( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16 \t( 0xE000E3F0 )\n#define portAIRCR_REG\t\t\t\t\t\t( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE\t\t\t\t\t( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE\t\t\t\t\t( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS\t\t\t\t( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK\t\t\t\t( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT\t\t\t\t\t( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK\t\t\t\t\t( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR\t\t\t\t\t\t\t( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS\t\t\t( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR\t\t\t\t\t( 0x01000000 )\n#define portINITIAL_EXC_RETURN\t\t\t\t( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER\t\t\t\t( 0xffffffUL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\nhave bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK\t\t( ( StackType_t ) 0xfffffffeUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\noccurred while the SysTick counter is stopped during tickless idle\ncalculations. */\n#define portMISSED_COUNTS_FACTOR\t\t\t( 45UL )\n\n/* Let the user override the pre-loading of the initial LR with the address of\nprvTaskExitError() in case it messes up unwinding of the stack in the\ndebugger. */\n#ifdef configTASK_RETURN_ADDRESS\n\t#define portTASK_RETURN_ADDRESS\tconfigTASK_RETURN_ADDRESS\n#else\n\t#define portTASK_RETURN_ADDRESS\tprvTaskExitError\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void ) __attribute__ (( naked ));\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void ) __attribute__ (( naked ));\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvPortStartFirstTask( void ) __attribute__ (( naked ));\n\n/*\n * Function to enable the VFP.\n */\nstatic void vPortEnableVFP( void ) __attribute__ (( naked ));\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\nvariable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if( configUSE_TICKLESS_IDLE == 1 )\n\tstatic uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if( configUSE_TICKLESS_IDLE == 1 )\n\tstatic uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if( configUSE_TICKLESS_IDLE == 1 )\n\tstatic uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if( configASSERT_DEFINED == 1 )\n\t static uint8_t ucMaxSysCallPriority = 0;\n\t static uint32_t ulMaxPRIGROUPValue = 0;\n\t static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Simulate the stack frame as it would be created by a context switch\n\tinterrupt. */\n\n\t/* Offset added to account for the way the MCU uses the stack on entry/exit\n\tof interrupts, and to ensure alignment. */\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = portINITIAL_XPSR;\t/* xPSR */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;\t/* PC */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;\t/* LR */\n\n\t/* Save code space by skipping register initialisation. */\n\tpxTopOfStack -= 5;\t/* R12, R3, R2 and R1. */\n\t*pxTopOfStack = ( StackType_t ) pvParameters;\t/* R0 */\n\n\t/* A save method is being used that requires each task to maintain its\n\town exec return value. */\n\tpxTopOfStack--;\n\t*pxTopOfStack = portINITIAL_EXC_RETURN;\n\n\tpxTopOfStack -= 8;\t/* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\nvolatile uint32_t ulDummy = 0;\n\n\t/* A function that implements a task must not exit or attempt to return to\n\tits caller as there is nothing to return to.  If a task wants to exit it\n\tshould instead call vTaskDelete( NULL ).\n\n\tArtificially force an assert() to be triggered if configASSERT() is\n\tdefined, then stop here so application writers can catch the error. */\n\tconfigASSERT( uxCriticalNesting == ~0UL );\n\tportDISABLE_INTERRUPTS();\n\twhile( ulDummy == 0 )\n\t{\n\t\t/* This file calls prvTaskExitError() after the scheduler has been\n\t\tstarted to remove a compiler warning about the function being defined\n\t\tbut never called.  ulDummy is used purely to quieten other warnings\n\t\tabout code appearing after this function is called - making ulDummy\n\t\tvolatile makes the compiler think the function could return and\n\t\ttherefore not output an 'unreachable code' warning for code that appears\n\t\tafter it. */\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n\t__asm volatile (\n\t\t\t\t\t\"\tldr\tr3, pxCurrentTCBConst2\t\t\\n\" /* Restore the context. */\n\t\t\t\t\t\"\tldr r1, [r3]\t\t\t\t\t\\n\" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\n\t\t\t\t\t\"\tldr r0, [r1]\t\t\t\t\t\\n\" /* The first item in pxCurrentTCB is the task top of stack. */\n\t\t\t\t\t\"\tldmia r0!, {r4-r11, r14}\t\t\\n\" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\n\t\t\t\t\t\"\tmsr psp, r0\t\t\t\t\t\t\\n\" /* Restore the task stack pointer. */\n\t\t\t\t\t\"\tisb\t\t\t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\tmov r0, #0 \t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\tmsr\tbasepri, r0\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\tbx r14\t\t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\t\t\t\t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\t.align 4\t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n\t\t\t\t);\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvPortStartFirstTask( void )\n{\n\t/* Start the first task.  This also clears the bit that indicates the FPU is\n\tin use in case the FPU was used before the scheduler was started - which\n\twould otherwise result in the unnecessary leaving of space in the SVC stack\n\tfor lazy saving of FPU registers. */\n\t__asm volatile(\n\t\t\t\t\t\" ldr r0, =0xE000ED08 \t\\n\" /* Use the NVIC offset register to locate the stack. */\n\t\t\t\t\t\" ldr r0, [r0] \t\t\t\\n\"\n\t\t\t\t\t\" ldr r0, [r0] \t\t\t\\n\"\n\t\t\t\t\t\" msr msp, r0\t\t\t\\n\" /* Set the msp back to the start of the stack. */\n\t\t\t\t\t\" mov r0, #0\t\t\t\\n\" /* Clear the bit that indicates the FPU is in use, see comment above. */\n\t\t\t\t\t\" msr control, r0\t\t\\n\"\n\t\t\t\t\t\" cpsie i\t\t\t\t\\n\" /* Globally enable interrupts. */\n\t\t\t\t\t\" cpsie f\t\t\t\t\\n\"\n\t\t\t\t\t\" dsb\t\t\t\t\t\\n\"\n\t\t\t\t\t\" isb\t\t\t\t\t\\n\"\n\t\t\t\t\t\" svc 0\t\t\t\t\t\\n\" /* System call to start first task. */\n\t\t\t\t\t\" nop\t\t\t\t\t\\n\"\n\t\t\t\t);\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n\t/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n\tSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n\tconfigASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n\t/* This port can be used on all revisions of the Cortex-M7 core other than\n\tthe r0p1 parts.  r0p1 parts should use the port from the\n\t/source/portable/GCC/ARM_CM7/r0p1 directory. */\n\tconfigASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\n\tconfigASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\n\n\t#if( configASSERT_DEFINED == 1 )\n\t{\n\t\tvolatile uint32_t ulOriginalPriority;\n\t\tvolatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n\t\tvolatile uint8_t ucMaxPriorityValue;\n\n\t\t/* Determine the maximum priority from which ISR safe FreeRTOS API\n\t\tfunctions can be called.  ISR safe functions are those that end in\n\t\t\"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n\t\tensure interrupt entry is as fast and simple as possible.\n\n\t\tSave the interrupt priority value that is about to be clobbered. */\n\t\tulOriginalPriority = *pucFirstUserPriorityRegister;\n\n\t\t/* Determine the number of priority bits available.  First write to all\n\t\tpossible bits. */\n\t\t*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n\t\t/* Read the value back to see how many bits stuck. */\n\t\tucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n\t\t/* Use the same mask on the maximum system call priority. */\n\t\tucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n\t\t/* Calculate the maximum acceptable priority group value for the number\n\t\tof bits read back. */\n\t\tulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\t\twhile( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n\t\t{\n\t\t\tulMaxPRIGROUPValue--;\n\t\t\tucMaxPriorityValue <<= ( uint8_t ) 0x01;\n\t\t}\n\n\t\t#ifdef __NVIC_PRIO_BITS\n\t\t{\n\t\t\t/* Check the CMSIS configuration that defines the number of\n\t\t\tpriority bits matches the number of priority bits actually queried\n\t\t\tfrom the hardware. */\n\t\t\tconfigASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n\t\t}\n\t\t#endif\n\n\t\t#ifdef configPRIO_BITS\n\t\t{\n\t\t\t/* Check the FreeRTOS configuration that defines the number of\n\t\t\tpriority bits matches the number of priority bits actually queried\n\t\t\tfrom the hardware. */\n\t\t\tconfigASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n\t\t}\n\t\t#endif\n\n\t\t/* Shift the priority group value back to its position within the AIRCR\n\t\tregister. */\n\t\tulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n\t\tulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n\t\t/* Restore the clobbered interrupt priority register to its original\n\t\tvalue. */\n\t\t*pucFirstUserPriorityRegister = ulOriginalPriority;\n\t}\n\t#endif /* conifgASSERT_DEFINED */\n\n\t/* Make PendSV and SysTick the lowest priority interrupts. */\n\tportNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\n\tportNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\n\n\t/* Start the timer that generates the tick ISR.  Interrupts are disabled\n\there already. */\n\tvPortSetupTimerInterrupt();\n\n\t/* Initialise the critical nesting count ready for the first task. */\n\tuxCriticalNesting = 0;\n\n\t/* Ensure the VFP is enabled - it should be anyway. */\n\tvPortEnableVFP();\n\n\t/* Lazy save always. */\n\t*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n\t/* Start the first task. */\n\tprvPortStartFirstTask();\n\n\t/* Should never get here as the tasks will now be executing!  Call the task\n\texit error function to prevent compiler warnings about a static function\n\tnot being called in the case that the application writer overrides this\n\tfunctionality by defining configTASK_RETURN_ADDRESS.  Call\n\tvTaskSwitchContext() so link time optimisation does not remove the\n\tsymbol. */\n\tvTaskSwitchContext();\n\tprvTaskExitError();\n\n\t/* Should not get here! */\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\tportDISABLE_INTERRUPTS();\n\tuxCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( uxCriticalNesting == 1 )\n\t{\n\t\tconfigASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tconfigASSERT( uxCriticalNesting );\n\tuxCriticalNesting--;\n\tif( uxCriticalNesting == 0 )\n\t{\n\t\tportENABLE_INTERRUPTS();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortPendSVHandler( void )\n{\n\t/* This is a naked function. */\n\n\t__asm volatile\n\t(\n\t\"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\n\t\"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\" /* Get the location of the current TCB. */\n\t\"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\ttst r14, #0x10\t\t\t\t\t\t\\n\" /* Is the task using the FPU context?  If so, push high vfp registers. */\n\t\"\tit eq\t\t\t\t\t\t\t\t\\n\"\n\t\"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tstmdb r0!, {r4-r11, r14}\t\t\t\\n\" /* Save the core registers. */\n\t\"\tstr r0, [r2]\t\t\t\t\t\t\\n\" /* Save the new top of stack into the first member of the TCB. */\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tstmdb sp!, {r0, r3}\t\t\t\t\t\\n\"\n\t\"\tmov r0, %0 \t\t\t\t\t\t\t\\n\"\n\t\"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n\t\"\tdsb\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tbl vTaskSwitchContext\t\t\t\t\\n\"\n\t\"\tmov r0, #0\t\t\t\t\t\t\t\\n\"\n\t\"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n\t\"\tldmia sp!, {r0, r3}\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tldr r1, [r3]\t\t\t\t\t\t\\n\" /* The first item in pxCurrentTCB is the task top of stack. */\n\t\"\tldr r0, [r1]\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tldmia r0!, {r4-r11, r14}\t\t\t\\n\" /* Pop the core registers. */\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\ttst r14, #0x10\t\t\t\t\t\t\\n\" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\n\t\"\tit eq\t\t\t\t\t\t\t\t\\n\"\n\t\"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"\n\t\"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\n\t\t#if WORKAROUND_PMU_CM001 == 1\n\t\"\t\t\tpush { r14 }\t\t\t\t\\n\"\n\t\"\t\t\tpop { pc }\t\t\t\t\t\\n\"\n\t\t#endif\n\t#endif\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tbx r14\t\t\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\t.align 4\t\t\t\t\t\t\t\\n\"\n\t\"pxCurrentTCBConst: .word pxCurrentTCB\t\\n\"\n\t::\"i\"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\n\t);\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n\t/* The SysTick runs at the lowest interrupt priority, so when this interrupt\n\texecutes all interrupts must be unmasked.  There is therefore no need to\n\tsave and then restore the interrupt mask value as its value is already\n\tknown. */\n\tportDISABLE_INTERRUPTS();\n\t{\n\t\t/* Increment the RTOS tick. */\n\t\tif( xTaskIncrementTick() != pdFALSE )\n\t\t{\n\t\t\t/* A context switch is required.  Context switching is performed in\n\t\t\tthe PendSV interrupt.  Pend the PendSV interrupt. */\n\t\t\tportNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\t\t}\n\t}\n\tportENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TICKLESS_IDLE == 1 )\n\n\t__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n\t{\n\tuint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\n\tTickType_t xModifiableIdleTime;\n\n\t\t/* Make sure the SysTick reload value does not overflow the counter. */\n\t\tif( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n\t\t{\n\t\t\txExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n\t\t}\n\n\t\t/* Stop the SysTick momentarily.  The time the SysTick is stopped for\n\t\tis accounted for as best it can be, but using the tickless mode will\n\t\tinevitably result in some tiny drift of the time maintained by the\n\t\tkernel with respect to calendar time. */\n\t\tportNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\n\n\t\t/* Calculate the reload value required to wait xExpectedIdleTime\n\t\ttick periods.  -1 is used because this code will execute part way\n\t\tthrough one of the tick periods. */\n\t\tulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\t\tif( ulReloadValue > ulStoppedTimerCompensation )\n\t\t{\n\t\t\tulReloadValue -= ulStoppedTimerCompensation;\n\t\t}\n\n\t\t/* Enter a critical section but don't use the taskENTER_CRITICAL()\n\t\tmethod as that will mask interrupts that should exit sleep mode. */\n\t\t__asm volatile( \"cpsid i\" ::: \"memory\" );\n\t\t__asm volatile( \"dsb\" );\n\t\t__asm volatile( \"isb\" );\n\n\t\t/* If a context switch is pending or a task is waiting for the scheduler\n\t\tto be unsuspended then abandon the low power entry. */\n\t\tif( eTaskConfirmSleepModeStatus() == eAbortSleep )\n\t\t{\n\t\t\t/* Restart from whatever is left in the count register to complete\n\t\t\tthis tick period. */\n\t\t\tportNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n\t\t\t/* Restart SysTick. */\n\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n\t\t\t/* Reset the reload register to the value required for normal tick\n\t\t\tperiods. */\n\t\t\tportNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n\n\t\t\t/* Re-enable interrupts - see comments above the cpsid instruction()\n\t\t\tabove. */\n\t\t\t__asm volatile( \"cpsie i\" ::: \"memory\" );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Set the new reload value. */\n\t\t\tportNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n\t\t\t/* Clear the SysTick count flag and set the count value back to\n\t\t\tzero. */\n\t\t\tportNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n\t\t\t/* Restart SysTick. */\n\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n\t\t\t/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n\t\t\tset its parameter to 0 to indicate that its implementation contains\n\t\t\tits own wait for interrupt or wait for event instruction, and so wfi\n\t\t\tshould not be executed again.  However, the original expected idle\n\t\t\ttime variable must remain unmodified, so a copy is taken. */\n\t\t\txModifiableIdleTime = xExpectedIdleTime;\n\t\t\tconfigPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\t\t\tif( xModifiableIdleTime > 0 )\n\t\t\t{\n\t\t\t\t__asm volatile( \"dsb\" ::: \"memory\" );\n\t\t\t\t__asm volatile( \"wfi\" );\n\t\t\t\t__asm volatile( \"isb\" );\n\t\t\t}\n\t\t\tconfigPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n\t\t\t/* Re-enable interrupts to allow the interrupt that brought the MCU\n\t\t\tout of sleep mode to execute immediately.  see comments above\n\t\t\t__disable_interrupt() call above. */\n\t\t\t__asm volatile( \"cpsie i\" ::: \"memory\" );\n\t\t\t__asm volatile( \"dsb\" );\n\t\t\t__asm volatile( \"isb\" );\n\n\t\t\t/* Disable interrupts again because the clock is about to be stopped\n\t\t\tand interrupts that execute while the clock is stopped will increase\n\t\t\tany slippage between the time maintained by the RTOS and calendar\n\t\t\ttime. */\n\t\t\t__asm volatile( \"cpsid i\" ::: \"memory\" );\n\t\t\t__asm volatile( \"dsb\" );\n\t\t\t__asm volatile( \"isb\" );\n\n\t\t\t/* Disable the SysTick clock without reading the\n\t\t\tportNVIC_SYSTICK_CTRL_REG register to ensure the\n\t\t\tportNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n\t\t\tthe time the SysTick is stopped for is accounted for as best it can\n\t\t\tbe, but using the tickless mode will inevitably result in some tiny\n\t\t\tdrift of the time maintained by the kernel with respect to calendar\n\t\t\ttime*/\n\t\t\tportNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\n\n\t\t\t/* Determine if the SysTick clock has already counted to zero and\n\t\t\tbeen set back to the current reload value (the reload back being\n\t\t\tcorrect for the entire expected idle time) or if the SysTick is yet\n\t\t\tto count to zero (in which case an interrupt other than the SysTick\n\t\t\tmust have brought the system out of sleep mode). */\n\t\t\tif( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n\t\t\t{\n\t\t\t\tuint32_t ulCalculatedLoadValue;\n\n\t\t\t\t/* The tick interrupt is already pending, and the SysTick count\n\t\t\t\treloaded with ulReloadValue.  Reset the\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\n\t\t\t\tperiod. */\n\t\t\t\tulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n\t\t\t\t/* Don't allow a tiny value, or values that have somehow\n\t\t\t\tunderflowed because the post sleep hook did something\n\t\t\t\tthat took too long. */\n\t\t\t\tif( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n\t\t\t\t{\n\t\t\t\t\tulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n\t\t\t\t}\n\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n\t\t\t\t/* As the pending tick will be processed as soon as this\n\t\t\t\tfunction exits, the tick value maintained by the tick is stepped\n\t\t\t\tforward by one less than the time spent waiting. */\n\t\t\t\tulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Something other than the tick interrupt ended the sleep.\n\t\t\t\tWork out how long the sleep lasted rounded to complete tick\n\t\t\t\tperiods (not the ulReload value which accounted for part\n\t\t\t\tticks). */\n\t\t\t\tulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n\t\t\t\t/* How many complete tick periods passed while the processor\n\t\t\t\twas waiting? */\n\t\t\t\tulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n\t\t\t\t/* The reload value is set to whatever fraction of a single tick\n\t\t\t\tperiod remains. */\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n\t\t\t}\n\n\t\t\t/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\n\t\t\tagain, then set portNVIC_SYSTICK_LOAD_REG back to its standard\n\t\t\tvalue. */\n\t\t\tportNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\t\t\tvTaskStepTick( ulCompleteTickPeriods );\n\t\t\tportNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n\n\t\t\t/* Exit with interrpts enabled. */\n\t\t\t__asm volatile( \"cpsie i\" ::: \"memory\" );\n\t\t}\n\t}\n\n#endif /* #if configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\n{\n\t/* Calculate the constants required to configure the tick interrupt. */\n\t#if( configUSE_TICKLESS_IDLE == 1 )\n\t{\n\t\tulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n\t\txMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n\t\tulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n\t}\n\t#endif /* configUSE_TICKLESS_IDLE */\n\n\t/* Stop and clear the SysTick. */\n\tportNVIC_SYSTICK_CTRL_REG = 0UL;\n\tportNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n\t/* Configure SysTick to interrupt at the requested rate. */\n\tportNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n\tportNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n/* This is a naked function. */\nstatic void vPortEnableVFP( void )\n{\n\t__asm volatile\n\t(\n\t\t\"\tldr.w r0, =0xE000ED88\t\t\\n\" /* The FPU enable bits are in the CPACR. */\n\t\t\"\tldr r1, [r0]\t\t\t\t\\n\"\n\t\t\"\t\t\t\t\t\t\t\t\\n\"\n\t\t\"\torr r1, r1, #( 0xf << 20 )\t\\n\" /* Enable CP10 and CP11 coprocessors, then save back. */\n\t\t\"\tstr r1, [r0]\t\t\t\t\\n\"\n\t\t\"\tbx r14\t\t\t\t\t\t\"\n\t);\n}\n/*-----------------------------------------------------------*/\n\n#if( configASSERT_DEFINED == 1 )\n\n\tvoid vPortValidateInterruptPriority( void )\n\t{\n\tuint32_t ulCurrentInterrupt;\n\tuint8_t ucCurrentPriority;\n\n\t\t/* Obtain the number of the currently executing interrupt. */\n\t\t__asm volatile( \"mrs %0, ipsr\" : \"=r\"( ulCurrentInterrupt ) :: \"memory\" );\n\n\t\t/* Is the interrupt number a user defined interrupt? */\n\t\tif( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n\t\t{\n\t\t\t/* Look up the interrupt's priority. */\n\t\t\tucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n\t\t\t/* The following assertion will fail if a service routine (ISR) for\n\t\t\tan interrupt that has been assigned a priority above\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n\t\t\tfunction.  ISR safe FreeRTOS API functions must *only* be called\n\t\t\tfrom interrupts that have been assigned a priority at or below\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\t\tNumerically low interrupt priority numbers represent logically high\n\t\t\tinterrupt priorities, therefore the priority of the interrupt must\n\t\t\tbe set to a value equal to or numerically *higher* than\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\t\tInterrupts that\tuse the FreeRTOS API must not be left at their\n\t\t\tdefault priority of\tzero as that is the highest possible priority,\n\t\t\twhich is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n\t\t\tand\ttherefore also guaranteed to be invalid.\n\n\t\t\tFreeRTOS maintains separate thread and ISR API functions to ensure\n\t\t\tinterrupt entry is as fast and simple as possible.\n\n\t\t\tThe following links provide detailed information:\n\t\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html\n\t\t\thttp://www.freertos.org/FAQHelp.html */\n\t\t\tconfigASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n\t\t}\n\n\t\t/* Priority grouping:  The interrupt controller (NVIC) allows the bits\n\t\tthat define each interrupt's priority to be split between bits that\n\t\tdefine the interrupt's pre-emption priority bits and bits that define\n\t\tthe interrupt's sub-priority.  For simplicity all bits must be defined\n\t\tto be pre-emption priority bits.  The following assertion will fail if\n\t\tthis is not the case (if some bits represent a sub-priority).\n\n\t\tIf the application only uses CMSIS libraries for interrupt\n\t\tconfiguration then the correct setting can be achieved on all Cortex-M\n\t\tdevices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n\t\tscheduler.  Note however that some vendor specific peripheral libraries\n\t\tassume a non-zero priority group setting, in which cases using a value\n\t\tof zero will result in unpredictable behaviour. */\n\t\tconfigASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n\t}\n\n#endif /* configASSERT_DEFINED */\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/GCC/ARM_CM4F/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tuint32_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\ttypedef uint16_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\n#else\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n\n\t/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n\tnot need to be guarded with a critical section. */\n\t#define portTICK_TYPE_IS_ATOMIC 1\n#endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t8\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n#define portYIELD() \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Set a PendSV to request a context switch. */\t\t\t\t\t\t\t\t\\\n\tportNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Barriers are normally not required but do ensure the code is completely\t\\\n\twithin the specified behaviour for the architecture. */\t\t\t\t\t\t\\\n\t__asm volatile( \"dsb\" ::: \"memory\" );\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile( \"isb\" );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portNVIC_INT_CTRL_REG\t\t( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\n#define portNVIC_PENDSVSET_BIT\t\t( 1UL << 28UL )\n#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\n#define portSET_INTERRUPT_MASK_FROM_ISR()\t\tulPortRaiseBASEPRI()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tvPortSetBASEPRI(x)\n#define portDISABLE_INTERRUPTS()\t\t\t\tvPortRaiseBASEPRI()\n#define portENABLE_INTERRUPTS()\t\t\t\t\tvPortSetBASEPRI(0)\n#define portENTER_CRITICAL()\t\t\t\t\tvPortEnterCritical()\n#define portEXIT_CRITICAL()\t\t\t\t\t\tvPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\nnot necessary for to use this port.  They are defined so the common demo files\n(which build with all the ports) will build. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n#ifndef portSUPPRESS_TICKS_AND_SLEEP\n\textern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n\t#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\n#endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Generic helper function. */\n\t__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\n\t{\n\tuint8_t ucReturn;\n\n\t\t__asm volatile ( \"clz %0, %1\" : \"=r\" ( ucReturn ) : \"r\" ( ulBitmap ) : \"memory\" );\n\t\treturn ucReturn;\n\t}\n\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n#ifdef configASSERT\n\tvoid vPortValidateInterruptPriority( void );\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() \tvPortValidateInterruptPriority()\n#endif\n\n/* portNOP() is not required by this port. */\n#define portNOP()\n\n#define portINLINE\t__inline\n\n#ifndef portFORCE_INLINE\n\t#define portFORCE_INLINE inline __attribute__(( always_inline))\n#endif\n\nportFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n{\nuint32_t ulCurrentInterrupt;\nBaseType_t xReturn;\n\n\t/* Obtain the number of the currently executing interrupt. */\n\t__asm volatile( \"mrs %0, ipsr\" : \"=r\"( ulCurrentInterrupt ) :: \"memory\" );\n\n\tif( ulCurrentInterrupt == 0 )\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\telse\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\n\treturn xReturn;\n}\n\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static void vPortRaiseBASEPRI( void )\n{\nuint32_t ulNewBASEPRI;\n\n\t__asm volatile\n\t(\n\t\t\"\tmov %0, %1\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\t\\\n\t\t\"\tmsr basepri, %0\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t:\"=r\" (ulNewBASEPRI) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n\t);\n}\n\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\n{\nuint32_t ulOriginalBASEPRI, ulNewBASEPRI;\n\n\t__asm volatile\n\t(\n\t\t\"\tmrs %0, basepri\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tmov %1, %2\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\t\\\n\t\t\"\tmsr basepri, %1\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t:\"=r\" (ulOriginalBASEPRI), \"=r\" (ulNewBASEPRI) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n\t);\n\n\t/* This return will not be reached but is necessary to prevent compiler\n\twarnings. */\n\treturn ulOriginalBASEPRI;\n}\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\n{\n\t__asm volatile\n\t(\n\t\t\"\tmsr basepri, %0\t\" :: \"r\" ( ulNewMaskValue ) : \"memory\"\n\t);\n}\n/*-----------------------------------------------------------*/\n\n#define portMEMORY_BARRIER() __asm volatile( \"\" ::: \"memory\" )\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/MemMang/ReadMe.url",
    "content": "[{000214A0-0000-0000-C000-000000000046}]\nProp3=19,2\n[InternetShortcut]\nURL=http://www.freertos.org/a00111.html\nIDList=\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/MemMang/heap_1.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n/*\n * The simplest possible implementation of pvPortMalloc().  Note that this\n * implementation does NOT allow allocated memory to be freed again.\n *\n * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the\n * memory management pages of http://www.FreeRTOS.org for more information.\n */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n\t#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n/* A few bytes might be lost to byte aligning the heap start address. */\n#define configADJUSTED_HEAP_SIZE\t( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )\n\n/* Allocate the memory for the heap. */\n#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\t/* The application writer has already defined the array used for the RTOS\n\theap - probably so it can be placed in a special segment or address. */\n\textern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#else\n\tstatic uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/* Index into the ucHeap array. */\nstatic size_t xNextFreeByte = ( size_t ) 0;\n\n/*-----------------------------------------------------------*/\n\nvoid *pvPortMalloc( size_t xWantedSize )\n{\nvoid *pvReturn = NULL;\nstatic uint8_t *pucAlignedHeap = NULL;\n\n\t/* Ensure that blocks are always aligned to the required number of bytes. */\n\t#if( portBYTE_ALIGNMENT != 1 )\n\t{\n\t\tif( xWantedSize & portBYTE_ALIGNMENT_MASK )\n\t\t{\n\t\t\t/* Byte alignment required. */\n\t\t\txWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\n\t\t}\n\t}\n\t#endif\n\n\tvTaskSuspendAll();\n\t{\n\t\tif( pucAlignedHeap == NULL )\n\t\t{\n\t\t\t/* Ensure the heap starts on a correctly aligned boundary. */\n\t\t\tpucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );\n\t\t}\n\n\t\t/* Check there is enough room left for the allocation. */\n\t\tif( ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&\n\t\t\t( ( xNextFreeByte + xWantedSize ) > xNextFreeByte )\t)/* Check for overflow. */\n\t\t{\n\t\t\t/* Return the next free byte then increment the index past this\n\t\t\tblock. */\n\t\t\tpvReturn = pucAlignedHeap + xNextFreeByte;\n\t\t\txNextFreeByte += xWantedSize;\n\t\t}\n\n\t\ttraceMALLOC( pvReturn, xWantedSize );\n\t}\n\t( void ) xTaskResumeAll();\n\n\t#if( configUSE_MALLOC_FAILED_HOOK == 1 )\n\t{\n\t\tif( pvReturn == NULL )\n\t\t{\n\t\t\textern void vApplicationMallocFailedHook( void );\n\t\t\tvApplicationMallocFailedHook();\n\t\t}\n\t}\n\t#endif\n\n\treturn pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void *pv )\n{\n\t/* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and\n\theap_4.c for alternative implementations, and the memory management pages of\n\thttp://www.FreeRTOS.org for more information. */\n\t( void ) pv;\n\n\t/* Force an assert as it is invalid to call this function. */\n\tconfigASSERT( pv == NULL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortInitialiseBlocks( void )\n{\n\t/* Only required when static memory is not cleared. */\n\txNextFreeByte = ( size_t ) 0;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n\treturn ( configADJUSTED_HEAP_SIZE - xNextFreeByte );\n}\n\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/MemMang/heap_2.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * A sample implementation of pvPortMalloc() and vPortFree() that permits\n * allocated blocks to be freed, but does not combine adjacent free blocks\n * into a single larger block (and so will fragment memory).  See heap_4.c for\n * an equivalent that does combine adjacent blocks into single larger blocks.\n *\n * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the\n * memory management pages of http://www.FreeRTOS.org for more information.\n */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n\t#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n/* A few bytes might be lost to byte aligning the heap start address. */\n#define configADJUSTED_HEAP_SIZE\t( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )\n\n/*\n * Initialises the heap structures before their first use.\n */\nstatic void prvHeapInit( void );\n\n/* Allocate the memory for the heap. */\n#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\t/* The application writer has already defined the array used for the RTOS\n\theap - probably so it can be placed in a special segment or address. */\n\textern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#else\n\tstatic uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n\n/* Define the linked list structure.  This is used to link free blocks in order\nof their size. */\ntypedef struct A_BLOCK_LINK\n{\n\tstruct A_BLOCK_LINK *pxNextFreeBlock;\t/*<< The next free block in the list. */\n\tsize_t xBlockSize;\t\t\t\t\t\t/*<< The size of the free block. */\n} BlockLink_t;\n\n\nstatic const uint16_t heapSTRUCT_SIZE\t= ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );\n#define heapMINIMUM_BLOCK_SIZE\t( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )\n\n/* Create a couple of list links to mark the start and end of the list. */\nstatic BlockLink_t xStart, xEnd;\n\n/* Keeps track of the number of free bytes remaining, but says nothing about\nfragmentation. */\nstatic size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;\n\n/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */\n\n/*\n * Insert a block into the list of free blocks - which is ordered by size of\n * the block.  Small blocks at the start of the list and large blocks at the end\n * of the list.\n */\n#define prvInsertBlockIntoFreeList( pxBlockToInsert )\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nBlockLink_t *pxIterator;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nsize_t xBlockSize;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\txBlockSize = pxBlockToInsert->xBlockSize;\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Iterate through the list until a block is found that has a larger size */\t\\\n\t/* than the block we are inserting. */\t\t\t\t\t\t\t\t\t\t\t\\\n\tfor( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock )\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* There is nothing to do here - just iterate to the correct position. */\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Update the list to include the block being inserted in the correct */\t\t\\\n\t/* position. */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tpxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\t\t\t\t\t\\\n\tpxIterator->pxNextFreeBlock = pxBlockToInsert;\t\t\t\t\t\t\t\t\t\\\n}\n/*-----------------------------------------------------------*/\n\nvoid *pvPortMalloc( size_t xWantedSize )\n{\nBlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\nstatic BaseType_t xHeapHasBeenInitialised = pdFALSE;\nvoid *pvReturn = NULL;\n\n\tvTaskSuspendAll();\n\t{\n\t\t/* If this is the first call to malloc then the heap will require\n\t\tinitialisation to setup the list of free blocks. */\n\t\tif( xHeapHasBeenInitialised == pdFALSE )\n\t\t{\n\t\t\tprvHeapInit();\n\t\t\txHeapHasBeenInitialised = pdTRUE;\n\t\t}\n\n\t\t/* The wanted size is increased so it can contain a BlockLink_t\n\t\tstructure in addition to the requested amount of bytes. */\n\t\tif( xWantedSize > 0 )\n\t\t{\n\t\t\txWantedSize += heapSTRUCT_SIZE;\n\n\t\t\t/* Ensure that blocks are always aligned to the required number of bytes. */\n\t\t\tif( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )\n\t\t\t{\n\t\t\t\t/* Byte alignment required. */\n\t\t\t\txWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\n\t\t\t}\n\t\t}\n\n\t\tif( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )\n\t\t{\n\t\t\t/* Blocks are stored in byte order - traverse the list from the start\n\t\t\t(smallest) block until one of adequate size is found. */\n\t\t\tpxPreviousBlock = &xStart;\n\t\t\tpxBlock = xStart.pxNextFreeBlock;\n\t\t\twhile( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n\t\t\t{\n\t\t\t\tpxPreviousBlock = pxBlock;\n\t\t\t\tpxBlock = pxBlock->pxNextFreeBlock;\n\t\t\t}\n\n\t\t\t/* If we found the end marker then a block of adequate size was not found. */\n\t\t\tif( pxBlock != &xEnd )\n\t\t\t{\n\t\t\t\t/* Return the memory space - jumping over the BlockLink_t structure\n\t\t\t\tat its start. */\n\t\t\t\tpvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );\n\n\t\t\t\t/* This block is being returned for use so must be taken out of the\n\t\t\t\tlist of free blocks. */\n\t\t\t\tpxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n\t\t\t\t/* If the block is larger than required it can be split into two. */\n\t\t\t\tif( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\n\t\t\t\t{\n\t\t\t\t\t/* This block is to be split into two.  Create a new block\n\t\t\t\t\tfollowing the number of bytes requested. The void cast is\n\t\t\t\t\tused to prevent byte alignment warnings from the compiler. */\n\t\t\t\t\tpxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n\n\t\t\t\t\t/* Calculate the sizes of two blocks split from the single\n\t\t\t\t\tblock. */\n\t\t\t\t\tpxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n\t\t\t\t\tpxBlock->xBlockSize = xWantedSize;\n\n\t\t\t\t\t/* Insert the new block into the list of free blocks. */\n\t\t\t\t\tprvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\n\t\t\t\t}\n\n\t\t\t\txFreeBytesRemaining -= pxBlock->xBlockSize;\n\t\t\t}\n\t\t}\n\n\t\ttraceMALLOC( pvReturn, xWantedSize );\n\t}\n\t( void ) xTaskResumeAll();\n\n\t#if( configUSE_MALLOC_FAILED_HOOK == 1 )\n\t{\n\t\tif( pvReturn == NULL )\n\t\t{\n\t\t\textern void vApplicationMallocFailedHook( void );\n\t\t\tvApplicationMallocFailedHook();\n\t\t}\n\t}\n\t#endif\n\n\treturn pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void *pv )\n{\nuint8_t *puc = ( uint8_t * ) pv;\nBlockLink_t *pxLink;\n\n\tif( pv != NULL )\n\t{\n\t\t/* The memory being freed will have an BlockLink_t structure immediately\n\t\tbefore it. */\n\t\tpuc -= heapSTRUCT_SIZE;\n\n\t\t/* This unexpected casting is to keep some compilers from issuing\n\t\tbyte alignment warnings. */\n\t\tpxLink = ( void * ) puc;\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* Add this block to the list of free blocks. */\n\t\t\tprvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n\t\t\txFreeBytesRemaining += pxLink->xBlockSize;\n\t\t\ttraceFREE( pv, pxLink->xBlockSize );\n\t\t}\n\t\t( void ) xTaskResumeAll();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n\treturn xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortInitialiseBlocks( void )\n{\n\t/* This just exists to keep the linker quiet. */\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\nBlockLink_t *pxFirstFreeBlock;\nuint8_t *pucAlignedHeap;\n\n\t/* Ensure the heap starts on a correctly aligned boundary. */\n\tpucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );\n\n\t/* xStart is used to hold a pointer to the first item in the list of free\n\tblocks.  The void cast is used to prevent compiler warnings. */\n\txStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n\txStart.xBlockSize = ( size_t ) 0;\n\n\t/* xEnd is used to mark the end of the list of free blocks. */\n\txEnd.xBlockSize = configADJUSTED_HEAP_SIZE;\n\txEnd.pxNextFreeBlock = NULL;\n\n\t/* To start with there is a single free block that is sized to take up the\n\tentire heap space. */\n\tpxFirstFreeBlock = ( void * ) pucAlignedHeap;\n\tpxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;\n\tpxFirstFreeBlock->pxNextFreeBlock = &xEnd;\n}\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/MemMang/heap_3.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n/*\n * Implementation of pvPortMalloc() and vPortFree() that relies on the\n * compilers own malloc() and free() implementations.\n *\n * This file can only be used if the linker is configured to to generate\n * a heap memory area.\n *\n * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the\n * memory management pages of http://www.FreeRTOS.org for more information.\n */\n\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n\t#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n/*-----------------------------------------------------------*/\n\nvoid *pvPortMalloc( size_t xWantedSize )\n{\nvoid *pvReturn;\n\n\tvTaskSuspendAll();\n\t{\n\t\tpvReturn = malloc( xWantedSize );\n\t\ttraceMALLOC( pvReturn, xWantedSize );\n\t}\n\t( void ) xTaskResumeAll();\n\n\t#if( configUSE_MALLOC_FAILED_HOOK == 1 )\n\t{\n\t\tif( pvReturn == NULL )\n\t\t{\n\t\t\textern void vApplicationMallocFailedHook( void );\n\t\t\tvApplicationMallocFailedHook();\n\t\t}\n\t}\n\t#endif\n\n\treturn pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void *pv )\n{\n\tif( pv )\n\t{\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\tfree( pv );\n\t\t\ttraceFREE( pv, 0 );\n\t\t}\n\t\t( void ) xTaskResumeAll();\n\t}\n}\n\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/MemMang/heap_4.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * A sample implementation of pvPortMalloc() and vPortFree() that combines\n * (coalescences) adjacent memory blocks as they are freed, and in so doing\n * limits memory fragmentation.\n *\n * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the\n * memory management pages of http://www.FreeRTOS.org for more information.\n */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n\t#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n/* Block sizes must not get too small. */\n#define heapMINIMUM_BLOCK_SIZE\t( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define heapBITS_PER_BYTE\t\t( ( size_t ) 8 )\n\n/* Allocate the memory for the heap. */\n#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\t/* The application writer has already defined the array used for the RTOS\n\theap - probably so it can be placed in a special segment or address. */\n\textern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#else\n\tstatic uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/* Define the linked list structure.  This is used to link free blocks in order\nof their memory address. */\ntypedef struct A_BLOCK_LINK\n{\n\tstruct A_BLOCK_LINK *pxNextFreeBlock;\t/*<< The next free block in the list. */\n\tsize_t xBlockSize;\t\t\t\t\t\t/*<< The size of the free block. */\n} BlockLink_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Inserts a block of memory that is being freed into the correct position in\n * the list of free memory blocks.  The block being freed will be merged with\n * the block in front it and/or the block behind it if the memory blocks are\n * adjacent to each other.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );\n\n/*\n * Called automatically to setup the required heap structures the first time\n * pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/*-----------------------------------------------------------*/\n\n/* The size of the structure placed at the beginning of each allocated memory\nblock must by correctly byte aligned. */\nstatic const size_t xHeapStructSize\t= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\n/* Create a couple of list links to mark the start and end of the list. */\nstatic BlockLink_t xStart, *pxEnd = NULL;\n\n/* Keeps track of the number of free bytes remaining, but says nothing about\nfragmentation. */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize\nmember of an BlockLink_t structure is set then the block belongs to the\napplication.  When the bit is free the block is still part of the free heap\nspace. */\nstatic size_t xBlockAllocatedBit = 0;\n\n/*-----------------------------------------------------------*/\n\nvoid *pvPortMalloc( size_t xWantedSize )\n{\nBlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\nvoid *pvReturn = NULL;\n\n\tvTaskSuspendAll();\n\t{\n\t\t/* If this is the first call to malloc then the heap will require\n\t\tinitialisation to setup the list of free blocks. */\n\t\tif( pxEnd == NULL )\n\t\t{\n\t\t\tprvHeapInit();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* Check the requested block size is not so large that the top bit is\n\t\tset.  The top bit of the block size member of the BlockLink_t structure\n\t\tis used to determine who owns the block - the application or the\n\t\tkernel, so it must be free. */\n\t\tif( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n\t\t{\n\t\t\t/* The wanted size is increased so it can contain a BlockLink_t\n\t\t\tstructure in addition to the requested amount of bytes. */\n\t\t\tif( xWantedSize > 0 )\n\t\t\t{\n\t\t\t\txWantedSize += xHeapStructSize;\n\n\t\t\t\t/* Ensure that blocks are always aligned to the required number\n\t\t\t\tof bytes. */\n\t\t\t\tif( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )\n\t\t\t\t{\n\t\t\t\t\t/* Byte alignment required. */\n\t\t\t\t\txWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\n\t\t\t\t\tconfigASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tif( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n\t\t\t{\n\t\t\t\t/* Traverse the list from the start\t(lowest address) block until\n\t\t\t\tone\tof adequate size is found. */\n\t\t\t\tpxPreviousBlock = &xStart;\n\t\t\t\tpxBlock = xStart.pxNextFreeBlock;\n\t\t\t\twhile( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n\t\t\t\t{\n\t\t\t\t\tpxPreviousBlock = pxBlock;\n\t\t\t\t\tpxBlock = pxBlock->pxNextFreeBlock;\n\t\t\t\t}\n\n\t\t\t\t/* If the end marker was reached then a block of adequate size\n\t\t\t\twas\tnot found. */\n\t\t\t\tif( pxBlock != pxEnd )\n\t\t\t\t{\n\t\t\t\t\t/* Return the memory space pointed to - jumping over the\n\t\t\t\t\tBlockLink_t structure at its start. */\n\t\t\t\t\tpvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n\t\t\t\t\t/* This block is being returned for use so must be taken out\n\t\t\t\t\tof the list of free blocks. */\n\t\t\t\t\tpxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n\t\t\t\t\t/* If the block is larger than required it can be split into\n\t\t\t\t\ttwo. */\n\t\t\t\t\tif( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* This block is to be split into two.  Create a new\n\t\t\t\t\t\tblock following the number of bytes requested. The void\n\t\t\t\t\t\tcast is used to prevent byte alignment warnings from the\n\t\t\t\t\t\tcompiler. */\n\t\t\t\t\t\tpxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n\t\t\t\t\t\tconfigASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );\n\n\t\t\t\t\t\t/* Calculate the sizes of two blocks split from the\n\t\t\t\t\t\tsingle block. */\n\t\t\t\t\t\tpxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n\t\t\t\t\t\tpxBlock->xBlockSize = xWantedSize;\n\n\t\t\t\t\t\t/* Insert the new block into the list of free blocks. */\n\t\t\t\t\t\tprvInsertBlockIntoFreeList( pxNewBlockLink );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\txFreeBytesRemaining -= pxBlock->xBlockSize;\n\n\t\t\t\t\tif( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n\t\t\t\t\t{\n\t\t\t\t\t\txMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* The block is being returned - it is allocated and owned\n\t\t\t\t\tby the application and has no \"next\" block. */\n\t\t\t\t\tpxBlock->xBlockSize |= xBlockAllocatedBit;\n\t\t\t\t\tpxBlock->pxNextFreeBlock = NULL;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\ttraceMALLOC( pvReturn, xWantedSize );\n\t}\n\t( void ) xTaskResumeAll();\n\n\t#if( configUSE_MALLOC_FAILED_HOOK == 1 )\n\t{\n\t\tif( pvReturn == NULL )\n\t\t{\n\t\t\textern void vApplicationMallocFailedHook( void );\n\t\t\tvApplicationMallocFailedHook();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\t#endif\n\n\tconfigASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );\n\treturn pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void *pv )\n{\nuint8_t *puc = ( uint8_t * ) pv;\nBlockLink_t *pxLink;\n\n\tif( pv != NULL )\n\t{\n\t\t/* The memory being freed will have an BlockLink_t structure immediately\n\t\tbefore it. */\n\t\tpuc -= xHeapStructSize;\n\n\t\t/* This casting is to keep the compiler from issuing warnings. */\n\t\tpxLink = ( void * ) puc;\n\n\t\t/* Check the block is actually allocated. */\n\t\tconfigASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n\t\tconfigASSERT( pxLink->pxNextFreeBlock == NULL );\n\n\t\tif( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n\t\t{\n\t\t\tif( pxLink->pxNextFreeBlock == NULL )\n\t\t\t{\n\t\t\t\t/* The block is being returned to the heap - it is no longer\n\t\t\t\tallocated. */\n\t\t\t\tpxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n\t\t\t\tvTaskSuspendAll();\n\t\t\t\t{\n\t\t\t\t\t/* Add this block to the list of free blocks. */\n\t\t\t\t\txFreeBytesRemaining += pxLink->xBlockSize;\n\t\t\t\t\ttraceFREE( pv, pxLink->xBlockSize );\n\t\t\t\t\tprvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n\t\t\t\t}\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n\treturn xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n\treturn xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortInitialiseBlocks( void )\n{\n\t/* This just exists to keep the linker quiet. */\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\nBlockLink_t *pxFirstFreeBlock;\nuint8_t *pucAlignedHeap;\nsize_t uxAddress;\nsize_t xTotalHeapSize = configTOTAL_HEAP_SIZE;\n\n\t/* Ensure the heap starts on a correctly aligned boundary. */\n\tuxAddress = ( size_t ) ucHeap;\n\n\tif( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )\n\t{\n\t\tuxAddress += ( portBYTE_ALIGNMENT - 1 );\n\t\tuxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\t\txTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n\t}\n\n\tpucAlignedHeap = ( uint8_t * ) uxAddress;\n\n\t/* xStart is used to hold a pointer to the first item in the list of free\n\tblocks.  The void cast is used to prevent compiler warnings. */\n\txStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n\txStart.xBlockSize = ( size_t ) 0;\n\n\t/* pxEnd is used to mark the end of the list of free blocks and is inserted\n\tat the end of the heap space. */\n\tuxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n\tuxAddress -= xHeapStructSize;\n\tuxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\tpxEnd = ( void * ) uxAddress;\n\tpxEnd->xBlockSize = 0;\n\tpxEnd->pxNextFreeBlock = NULL;\n\n\t/* To start with there is a single free block that is sized to take up the\n\tentire heap space, minus the space taken by pxEnd. */\n\tpxFirstFreeBlock = ( void * ) pucAlignedHeap;\n\tpxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n\tpxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n\t/* Only one block exists - and it covers the entire usable heap space. */\n\txMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\txFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n\t/* Work out the position of the top bit in a size_t variable. */\n\txBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )\n{\nBlockLink_t *pxIterator;\nuint8_t *puc;\n\n\t/* Iterate through the list until a block is found that has a higher address\n\tthan the block being inserted. */\n\tfor( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n\t{\n\t\t/* Nothing to do here, just iterate to the right position. */\n\t}\n\n\t/* Do the block being inserted, and the block it is being inserted after\n\tmake a contiguous block of memory? */\n\tpuc = ( uint8_t * ) pxIterator;\n\tif( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n\t{\n\t\tpxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n\t\tpxBlockToInsert = pxIterator;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\t/* Do the block being inserted, and the block it is being inserted before\n\tmake a contiguous block of memory? */\n\tpuc = ( uint8_t * ) pxBlockToInsert;\n\tif( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n\t{\n\t\tif( pxIterator->pxNextFreeBlock != pxEnd )\n\t\t{\n\t\t\t/* Form one big block from the two blocks. */\n\t\t\tpxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n\t\t\tpxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxBlockToInsert->pxNextFreeBlock = pxEnd;\n\t\t}\n\t}\n\telse\n\t{\n\t\tpxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n\t}\n\n\t/* If the block being inserted plugged a gab, so was merged with the block\n\tbefore and the block after, then it's pxNextFreeBlock pointer will have\n\talready been set, and should not be set here as that would make it point\n\tto itself. */\n\tif( pxIterator != pxBlockToInsert )\n\t{\n\t\tpxIterator->pxNextFreeBlock = pxBlockToInsert;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n}\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/portable/MemMang/heap_5.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * A sample implementation of pvPortMalloc() that allows the heap to be defined\n * across multiple non-contigous blocks and combines (coalescences) adjacent\n * memory blocks as they are freed.\n *\n * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative\n * implementations, and the memory management pages of http://www.FreeRTOS.org\n * for more information.\n *\n * Usage notes:\n *\n * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc().\n * pvPortMalloc() will be called if any task objects (tasks, queues, event\n * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be\n * called before any other objects are defined.\n *\n * vPortDefineHeapRegions() takes a single parameter.  The parameter is an array\n * of HeapRegion_t structures.  HeapRegion_t is defined in portable.h as\n *\n * typedef struct HeapRegion\n * {\n *\tuint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap.\n *\tsize_t xSizeInBytes;\t  << Size of the block of memory.\n * } HeapRegion_t;\n *\n * The array is terminated using a NULL zero sized region definition, and the\n * memory regions defined in the array ***must*** appear in address order from\n * low address to high address.  So the following is a valid example of how\n * to use the function.\n *\n * HeapRegion_t xHeapRegions[] =\n * {\n * \t{ ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000\n * \t{ ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000\n * \t{ NULL, 0 }                << Terminates the array.\n * };\n *\n * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions().\n *\n * Note 0x80000000 is the lower address so appears in the array first.\n *\n */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n\t#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n/* Block sizes must not get too small. */\n#define heapMINIMUM_BLOCK_SIZE\t( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define heapBITS_PER_BYTE\t\t( ( size_t ) 8 )\n\n/* Define the linked list structure.  This is used to link free blocks in order\nof their memory address. */\ntypedef struct A_BLOCK_LINK\n{\n\tstruct A_BLOCK_LINK *pxNextFreeBlock;\t/*<< The next free block in the list. */\n\tsize_t xBlockSize;\t\t\t\t\t\t/*<< The size of the free block. */\n} BlockLink_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Inserts a block of memory that is being freed into the correct position in\n * the list of free memory blocks.  The block being freed will be merged with\n * the block in front it and/or the block behind it if the memory blocks are\n * adjacent to each other.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );\n\n/*-----------------------------------------------------------*/\n\n/* The size of the structure placed at the beginning of each allocated memory\nblock must by correctly byte aligned. */\nstatic const size_t xHeapStructSize\t= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\n/* Create a couple of list links to mark the start and end of the list. */\nstatic BlockLink_t xStart, *pxEnd = NULL;\n\n/* Keeps track of the number of free bytes remaining, but says nothing about\nfragmentation. */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\n\n/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize\nmember of an BlockLink_t structure is set then the block belongs to the\napplication.  When the bit is free the block is still part of the free heap\nspace. */\nstatic size_t xBlockAllocatedBit = 0;\n\n/*-----------------------------------------------------------*/\n\nvoid *pvPortMalloc( size_t xWantedSize )\n{\nBlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\nvoid *pvReturn = NULL;\n\n\t/* The heap must be initialised before the first call to\n\tprvPortMalloc(). */\n\tconfigASSERT( pxEnd );\n\n\tvTaskSuspendAll();\n\t{\n\t\t/* Check the requested block size is not so large that the top bit is\n\t\tset.  The top bit of the block size member of the BlockLink_t structure\n\t\tis used to determine who owns the block - the application or the\n\t\tkernel, so it must be free. */\n\t\tif( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n\t\t{\n\t\t\t/* The wanted size is increased so it can contain a BlockLink_t\n\t\t\tstructure in addition to the requested amount of bytes. */\n\t\t\tif( xWantedSize > 0 )\n\t\t\t{\n\t\t\t\txWantedSize += xHeapStructSize;\n\n\t\t\t\t/* Ensure that blocks are always aligned to the required number\n\t\t\t\tof bytes. */\n\t\t\t\tif( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )\n\t\t\t\t{\n\t\t\t\t\t/* Byte alignment required. */\n\t\t\t\t\txWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tif( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n\t\t\t{\n\t\t\t\t/* Traverse the list from the start\t(lowest address) block until\n\t\t\t\tone\tof adequate size is found. */\n\t\t\t\tpxPreviousBlock = &xStart;\n\t\t\t\tpxBlock = xStart.pxNextFreeBlock;\n\t\t\t\twhile( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n\t\t\t\t{\n\t\t\t\t\tpxPreviousBlock = pxBlock;\n\t\t\t\t\tpxBlock = pxBlock->pxNextFreeBlock;\n\t\t\t\t}\n\n\t\t\t\t/* If the end marker was reached then a block of adequate size\n\t\t\t\twas\tnot found. */\n\t\t\t\tif( pxBlock != pxEnd )\n\t\t\t\t{\n\t\t\t\t\t/* Return the memory space pointed to - jumping over the\n\t\t\t\t\tBlockLink_t structure at its start. */\n\t\t\t\t\tpvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n\t\t\t\t\t/* This block is being returned for use so must be taken out\n\t\t\t\t\tof the list of free blocks. */\n\t\t\t\t\tpxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n\t\t\t\t\t/* If the block is larger than required it can be split into\n\t\t\t\t\ttwo. */\n\t\t\t\t\tif( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* This block is to be split into two.  Create a new\n\t\t\t\t\t\tblock following the number of bytes requested. The void\n\t\t\t\t\t\tcast is used to prevent byte alignment warnings from the\n\t\t\t\t\t\tcompiler. */\n\t\t\t\t\t\tpxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n\n\t\t\t\t\t\t/* Calculate the sizes of two blocks split from the\n\t\t\t\t\t\tsingle block. */\n\t\t\t\t\t\tpxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n\t\t\t\t\t\tpxBlock->xBlockSize = xWantedSize;\n\n\t\t\t\t\t\t/* Insert the new block into the list of free blocks. */\n\t\t\t\t\t\tprvInsertBlockIntoFreeList( ( pxNewBlockLink ) );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\txFreeBytesRemaining -= pxBlock->xBlockSize;\n\n\t\t\t\t\tif( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n\t\t\t\t\t{\n\t\t\t\t\t\txMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* The block is being returned - it is allocated and owned\n\t\t\t\t\tby the application and has no \"next\" block. */\n\t\t\t\t\tpxBlock->xBlockSize |= xBlockAllocatedBit;\n\t\t\t\t\tpxBlock->pxNextFreeBlock = NULL;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\ttraceMALLOC( pvReturn, xWantedSize );\n\t}\n\t( void ) xTaskResumeAll();\n\n\t#if( configUSE_MALLOC_FAILED_HOOK == 1 )\n\t{\n\t\tif( pvReturn == NULL )\n\t\t{\n\t\t\textern void vApplicationMallocFailedHook( void );\n\t\t\tvApplicationMallocFailedHook();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\t#endif\n\n\treturn pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void *pv )\n{\nuint8_t *puc = ( uint8_t * ) pv;\nBlockLink_t *pxLink;\n\n\tif( pv != NULL )\n\t{\n\t\t/* The memory being freed will have an BlockLink_t structure immediately\n\t\tbefore it. */\n\t\tpuc -= xHeapStructSize;\n\n\t\t/* This casting is to keep the compiler from issuing warnings. */\n\t\tpxLink = ( void * ) puc;\n\n\t\t/* Check the block is actually allocated. */\n\t\tconfigASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n\t\tconfigASSERT( pxLink->pxNextFreeBlock == NULL );\n\n\t\tif( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n\t\t{\n\t\t\tif( pxLink->pxNextFreeBlock == NULL )\n\t\t\t{\n\t\t\t\t/* The block is being returned to the heap - it is no longer\n\t\t\t\tallocated. */\n\t\t\t\tpxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n\t\t\t\tvTaskSuspendAll();\n\t\t\t\t{\n\t\t\t\t\t/* Add this block to the list of free blocks. */\n\t\t\t\t\txFreeBytesRemaining += pxLink->xBlockSize;\n\t\t\t\t\ttraceFREE( pv, pxLink->xBlockSize );\n\t\t\t\t\tprvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n\t\t\t\t}\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n\treturn xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n\treturn xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )\n{\nBlockLink_t *pxIterator;\nuint8_t *puc;\n\n\t/* Iterate through the list until a block is found that has a higher address\n\tthan the block being inserted. */\n\tfor( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n\t{\n\t\t/* Nothing to do here, just iterate to the right position. */\n\t}\n\n\t/* Do the block being inserted, and the block it is being inserted after\n\tmake a contiguous block of memory? */\n\tpuc = ( uint8_t * ) pxIterator;\n\tif( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n\t{\n\t\tpxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n\t\tpxBlockToInsert = pxIterator;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\t/* Do the block being inserted, and the block it is being inserted before\n\tmake a contiguous block of memory? */\n\tpuc = ( uint8_t * ) pxBlockToInsert;\n\tif( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n\t{\n\t\tif( pxIterator->pxNextFreeBlock != pxEnd )\n\t\t{\n\t\t\t/* Form one big block from the two blocks. */\n\t\t\tpxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n\t\t\tpxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxBlockToInsert->pxNextFreeBlock = pxEnd;\n\t\t}\n\t}\n\telse\n\t{\n\t\tpxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n\t}\n\n\t/* If the block being inserted plugged a gab, so was merged with the block\n\tbefore and the block after, then it's pxNextFreeBlock pointer will have\n\talready been set, and should not be set here as that would make it point\n\tto itself. */\n\tif( pxIterator != pxBlockToInsert )\n\t{\n\t\tpxIterator->pxNextFreeBlock = pxBlockToInsert;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )\n{\nBlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;\nsize_t xAlignedHeap;\nsize_t xTotalRegionSize, xTotalHeapSize = 0;\nBaseType_t xDefinedRegions = 0;\nsize_t xAddress;\nconst HeapRegion_t *pxHeapRegion;\n\n\t/* Can only call once! */\n\tconfigASSERT( pxEnd == NULL );\n\n\tpxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );\n\n\twhile( pxHeapRegion->xSizeInBytes > 0 )\n\t{\n\t\txTotalRegionSize = pxHeapRegion->xSizeInBytes;\n\n\t\t/* Ensure the heap region starts on a correctly aligned boundary. */\n\t\txAddress = ( size_t ) pxHeapRegion->pucStartAddress;\n\t\tif( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )\n\t\t{\n\t\t\txAddress += ( portBYTE_ALIGNMENT - 1 );\n\t\t\txAddress &= ~portBYTE_ALIGNMENT_MASK;\n\n\t\t\t/* Adjust the size for the bytes lost to alignment. */\n\t\t\txTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;\n\t\t}\n\n\t\txAlignedHeap = xAddress;\n\n\t\t/* Set xStart if it has not already been set. */\n\t\tif( xDefinedRegions == 0 )\n\t\t{\n\t\t\t/* xStart is used to hold a pointer to the first item in the list of\n\t\t\tfree blocks.  The void cast is used to prevent compiler warnings. */\n\t\t\txStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;\n\t\t\txStart.xBlockSize = ( size_t ) 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Should only get here if one region has already been added to the\n\t\t\theap. */\n\t\t\tconfigASSERT( pxEnd != NULL );\n\n\t\t\t/* Check blocks are passed in with increasing start addresses. */\n\t\t\tconfigASSERT( xAddress > ( size_t ) pxEnd );\n\t\t}\n\n\t\t/* Remember the location of the end marker in the previous region, if\n\t\tany. */\n\t\tpxPreviousFreeBlock = pxEnd;\n\n\t\t/* pxEnd is used to mark the end of the list of free blocks and is\n\t\tinserted at the end of the region space. */\n\t\txAddress = xAlignedHeap + xTotalRegionSize;\n\t\txAddress -= xHeapStructSize;\n\t\txAddress &= ~portBYTE_ALIGNMENT_MASK;\n\t\tpxEnd = ( BlockLink_t * ) xAddress;\n\t\tpxEnd->xBlockSize = 0;\n\t\tpxEnd->pxNextFreeBlock = NULL;\n\n\t\t/* To start with there is a single free block in this region that is\n\t\tsized to take up the entire heap region minus the space taken by the\n\t\tfree block structure. */\n\t\tpxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;\n\t\tpxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;\n\t\tpxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;\n\n\t\t/* If this is not the first region that makes up the entire heap space\n\t\tthen link the previous region to this region. */\n\t\tif( pxPreviousFreeBlock != NULL )\n\t\t{\n\t\t\tpxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;\n\t\t}\n\n\t\txTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;\n\n\t\t/* Move onto the next HeapRegion_t structure. */\n\t\txDefinedRegions++;\n\t\tpxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );\n\t}\n\n\txMinimumEverFreeBytesRemaining = xTotalHeapSize;\n\txFreeBytesRemaining = xTotalHeapSize;\n\n\t/* Check something was actually defined before it is accessed. */\n\tconfigASSERT( xTotalHeapSize );\n\n\t/* Work out the position of the top bit in a size_t variable. */\n\txBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );\n}\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/queue.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\t#include \"croutine.h\"\n#endif\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n\n/* Constants used with the cRxLock and cTxLock structure members. */\n#define queueUNLOCKED\t\t\t\t\t( ( int8_t ) -1 )\n#define queueLOCKED_UNMODIFIED\t\t\t( ( int8_t ) 0 )\n\n/* When the Queue_t structure is used to represent a base queue its pcHead and\npcTail members are used as pointers into the queue storage area.  When the\nQueue_t structure is used to represent a mutex pcHead and pcTail pointers are\nnot necessary, and the pcHead pointer is set to NULL to indicate that the\nstructure instead holds a pointer to the mutex holder (if any).  Map alternative\nnames to the pcHead and structure member to ensure the readability of the code\nis maintained.  The QueuePointers_t and SemaphoreData_t types are used to form\na union as their usage is mutually exclusive dependent on what the queue is\nbeing used for. */\n#define uxQueueType\t\t\t\t\t\tpcHead\n#define queueQUEUE_IS_MUTEX\t\t\t\tNULL\n\ntypedef struct QueuePointers\n{\n\tint8_t *pcTail;\t\t\t\t\t/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */\n\tint8_t *pcReadFrom;\t\t\t\t/*< Points to the last place that a queued item was read from when the structure is used as a queue. */\n} QueuePointers_t;\n\ntypedef struct SemaphoreData\n{\n\tTaskHandle_t xMutexHolder;\t\t /*< The handle of the task that holds the mutex. */\n\tUBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */\n} SemaphoreData_t;\n\n/* Semaphores do not actually store or copy data, so have an item size of\nzero. */\n#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )\n#define queueMUTEX_GIVE_BLOCK_TIME\t\t ( ( TickType_t ) 0U )\n\n#if( configUSE_PREEMPTION == 0 )\n\t/* If the cooperative scheduler is being used then a yield should not be\n\tperformed just because a higher priority task has been woken. */\n\t#define queueYIELD_IF_USING_PREEMPTION()\n#else\n\t#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()\n#endif\n\n/*\n * Definition of the queue used by the scheduler.\n * Items are queued by copy, not reference.  See the following link for the\n * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html\n */\ntypedef struct QueueDefinition \t\t/* The old naming convention is used to prevent breaking kernel aware debuggers. */\n{\n\tint8_t *pcHead;\t\t\t\t\t/*< Points to the beginning of the queue storage area. */\n\tint8_t *pcWriteTo;\t\t\t\t/*< Points to the free next place in the storage area. */\n\n\tunion\n\t{\n\t\tQueuePointers_t xQueue;\t\t/*< Data required exclusively when this structure is used as a queue. */\n\t\tSemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */\n\t} u;\n\n\tList_t xTasksWaitingToSend;\t\t/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */\n\tList_t xTasksWaitingToReceive;\t/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */\n\n\tvolatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */\n\tUBaseType_t uxLength;\t\t\t/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */\n\tUBaseType_t uxItemSize;\t\t\t/*< The size of each items that the queue will hold. */\n\n\tvolatile int8_t cRxLock;\t\t/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */\n\tvolatile int8_t cTxLock;\t\t/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */\n\n\t#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\t\tuint8_t ucStaticallyAllocated;\t/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */\n\t#endif\n\n\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\tstruct QueueDefinition *pxQueueSetContainer;\n\t#endif\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxQueueNumber;\n\t\tuint8_t ucQueueType;\n\t#endif\n\n} xQUEUE;\n\n/* The old xQUEUE name is maintained above then typedefed to the new Queue_t\nname below to enable the use of older kernel aware debuggers. */\ntypedef xQUEUE Queue_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * The queue registry is just a means for kernel aware debuggers to locate\n * queue structures.  It has no other purpose so is an optional component.\n */\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n\t/* The type stored within the queue registry array.  This allows a name\n\tto be assigned to each queue making kernel aware debugging a little\n\tmore user friendly. */\n\ttypedef struct QUEUE_REGISTRY_ITEM\n\t{\n\t\tconst char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\tQueueHandle_t xHandle;\n\t} xQueueRegistryItem;\n\n\t/* The old xQueueRegistryItem name is maintained above then typedefed to the\n\tnew xQueueRegistryItem name below to enable the use of older kernel aware\n\tdebuggers. */\n\ttypedef xQueueRegistryItem QueueRegistryItem_t;\n\n\t/* The queue registry is simply an array of QueueRegistryItem_t structures.\n\tThe pcQueueName member of a structure being NULL is indicative of the\n\tarray position being vacant. */\n\tPRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n\n/*\n * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not\n * prevent an ISR from adding or removing items to the queue, but does prevent\n * an ISR from removing tasks from the queue event lists.  If an ISR finds a\n * queue is locked it will instead increment the appropriate queue lock count\n * to indicate that a task may require unblocking.  When the queue in unlocked\n * these lock counts are inspected, and the appropriate action taken.\n */\nstatic void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Uses a critical section to determine if there is any data in a queue.\n *\n * @return pdTRUE if the queue contains no items, otherwise pdFALSE.\n */\nstatic BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Uses a critical section to determine if there is any space in a queue.\n *\n * @return pdTRUE if there is no space, otherwise pdFALSE;\n */\nstatic BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Copies an item into the queue, either at the front of the queue or the\n * back of the queue.\n */\nstatic BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;\n\n/*\n * Copies an item out of a queue.\n */\nstatic void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\t/*\n\t * Checks to see if a queue is a member of a queue set, and if so, notifies\n\t * the queue set that the queue contains data.\n\t */\n\tstatic BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Called after a Queue_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\nstatic void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Mutexes are a special type of queue.  When a mutex is created, first the\n * queue is created, then prvInitialiseMutex() is called to configure the queue\n * as a mutex.\n */\n#if( configUSE_MUTEXES == 1 )\n\tstatic void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;\n#endif\n\n#if( configUSE_MUTEXES == 1 )\n\t/*\n\t * If a task waiting for a mutex causes the mutex holder to inherit a\n\t * priority, but the waiting task times out, then the holder should\n\t * disinherit the priority - but only down to the highest priority of any\n\t * other tasks that are waiting for the same mutex.  This function returns\n\t * that priority.\n\t */\n\tstatic UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\n#endif\n/*-----------------------------------------------------------*/\n\n/*\n * Macro to mark a queue as locked.  Locking a queue prevents an ISR from\n * accessing the queue event lists.\n */\n#define prvLockQueue( pxQueue )\t\t\t\t\t\t\t\t\\\n\ttaskENTER_CRITICAL();\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( pxQueue )->cRxLock == queueUNLOCKED )\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( pxQueue )->cTxLock == queueUNLOCKED )\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\ttaskEXIT_CRITICAL()\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )\n{\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n\t\tpxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\n\t\tpxQueue->pcWriteTo = pxQueue->pcHead;\n\t\tpxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n\t\tpxQueue->cRxLock = queueUNLOCKED;\n\t\tpxQueue->cTxLock = queueUNLOCKED;\n\n\t\tif( xNewQueue == pdFALSE )\n\t\t{\n\t\t\t/* If there are tasks blocked waiting to read from the queue, then\n\t\t\tthe tasks will remain blocked as after this function exits the queue\n\t\t\twill still be empty.  If there are tasks blocked waiting to write to\n\t\t\tthe queue, then one should be unblocked as after this function exits\n\t\t\tit will be possible to write to it. */\n\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t{\n\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Ensure the event queues start in the correct state. */\n\t\t\tvListInitialise( &( pxQueue->xTasksWaitingToSend ) );\n\t\t\tvListInitialise( &( pxQueue->xTasksWaitingToReceive ) );\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\t/* A value is returned for calling semantic consistency with previous\n\tversions. */\n\treturn pdPASS;\n}\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tQueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )\n\t{\n\tQueue_t *pxNewQueue;\n\n\t\tconfigASSERT( uxQueueLength > ( UBaseType_t ) 0 );\n\n\t\t/* The StaticQueue_t structure and the queue storage area must be\n\t\tsupplied. */\n\t\tconfigASSERT( pxStaticQueue != NULL );\n\n\t\t/* A queue storage area should be provided if the item size is not 0, and\n\t\tshould not be provided if the item size is 0. */\n\t\tconfigASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );\n\t\tconfigASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticQueue_t or StaticSemaphore_t equals the size of\n\t\t\tthe real queue and semaphore structures. */\n\t\t\tvolatile size_t xSize = sizeof( StaticQueue_t );\n\t\t\tconfigASSERT( xSize == sizeof( Queue_t ) );\n\t\t\t( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */\n\t\t}\n\t\t#endif /* configASSERT_DEFINED */\n\n\t\t/* The address of a statically allocated queue was passed in, use it.\n\t\tThe address of a statically allocated storage area was also passed in\n\t\tbut is already set. */\n\t\tpxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */\n\n\t\tif( pxNewQueue != NULL )\n\t\t{\n\t\t\t#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* Queues can be allocated wither statically or dynamically, so\n\t\t\t\tnote this queue was allocated statically in case the queue is\n\t\t\t\tlater deleted. */\n\t\t\t\tpxNewQueue->ucStaticallyAllocated = pdTRUE;\n\t\t\t}\n\t\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\n\t\t\tprvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceQUEUE_CREATE_FAILED( ucQueueType );\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn pxNewQueue;\n\t}\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tQueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )\n\t{\n\tQueue_t *pxNewQueue;\n\tsize_t xQueueSizeInBytes;\n\tuint8_t *pucQueueStorage;\n\n\t\tconfigASSERT( uxQueueLength > ( UBaseType_t ) 0 );\n\n\t\tif( uxItemSize == ( UBaseType_t ) 0 )\n\t\t{\n\t\t\t/* There is not going to be a queue storage area. */\n\t\t\txQueueSizeInBytes = ( size_t ) 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Allocate enough space to hold the maximum number of items that\n\t\t\tcan be in the queue at any time. */\n\t\t\txQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t}\n\n\t\t/* Allocate the queue and storage area.  Justification for MISRA\n\t\tdeviation as follows:  pvPortMalloc() always ensures returned memory\n\t\tblocks are aligned per the requirements of the MCU stack.  In this case\n\t\tpvPortMalloc() must return a pointer that is guaranteed to meet the\n\t\talignment requirements of the Queue_t structure - which in this case\n\t\tis an int8_t *.  Therefore, whenever the stack alignment requirements\n\t\tare greater than or equal to the pointer to char requirements the cast\n\t\tis safe.  In other cases alignment requirements are not strict (one or\n\t\ttwo bytes). */\n\t\tpxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */\n\n\t\tif( pxNewQueue != NULL )\n\t\t{\n\t\t\t/* Jump past the queue structure to find the location of the queue\n\t\t\tstorage area. */\n\t\t\tpucQueueStorage = ( uint8_t * ) pxNewQueue;\n\t\t\tpucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n\n\t\t\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* Queues can be created either statically or dynamically, so\n\t\t\t\tnote this task was created dynamically in case it is later\n\t\t\t\tdeleted. */\n\t\t\t\tpxNewQueue->ucStaticallyAllocated = pdFALSE;\n\t\t\t}\n\t\t\t#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n\t\t\tprvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceQUEUE_CREATE_FAILED( ucQueueType );\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn pxNewQueue;\n\t}\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )\n{\n\t/* Remove compiler warnings about unused parameters should\n\tconfigUSE_TRACE_FACILITY not be set to 1. */\n\t( void ) ucQueueType;\n\n\tif( uxItemSize == ( UBaseType_t ) 0 )\n\t{\n\t\t/* No RAM was allocated for the queue storage area, but PC head cannot\n\t\tbe set to NULL because NULL is used as a key to say the queue is used as\n\t\ta mutex.  Therefore just set pcHead to point to the queue as a benign\n\t\tvalue that is known to be within the memory map. */\n\t\tpxNewQueue->pcHead = ( int8_t * ) pxNewQueue;\n\t}\n\telse\n\t{\n\t\t/* Set the head to the start of the queue storage area. */\n\t\tpxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;\n\t}\n\n\t/* Initialise the queue members as described where the queue type is\n\tdefined. */\n\tpxNewQueue->uxLength = uxQueueLength;\n\tpxNewQueue->uxItemSize = uxItemSize;\n\t( void ) xQueueGenericReset( pxNewQueue, pdTRUE );\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t{\n\t\tpxNewQueue->ucQueueType = ucQueueType;\n\t}\n\t#endif /* configUSE_TRACE_FACILITY */\n\n\t#if( configUSE_QUEUE_SETS == 1 )\n\t{\n\t\tpxNewQueue->pxQueueSetContainer = NULL;\n\t}\n\t#endif /* configUSE_QUEUE_SETS */\n\n\ttraceQUEUE_CREATE( pxNewQueue );\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_MUTEXES == 1 )\n\n\tstatic void prvInitialiseMutex( Queue_t *pxNewQueue )\n\t{\n\t\tif( pxNewQueue != NULL )\n\t\t{\n\t\t\t/* The queue create function will set all the queue structure members\n\t\t\tcorrectly for a generic queue, but this function is creating a\n\t\t\tmutex.  Overwrite those members that need to be set differently -\n\t\t\tin particular the information required for priority inheritance. */\n\t\t\tpxNewQueue->u.xSemaphore.xMutexHolder = NULL;\n\t\t\tpxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;\n\n\t\t\t/* In case this is a recursive mutex. */\n\t\t\tpxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;\n\n\t\t\ttraceCREATE_MUTEX( pxNewQueue );\n\n\t\t\t/* Start with the semaphore in the expected state. */\n\t\t\t( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceCREATE_MUTEX_FAILED();\n\t\t}\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )\n\t{\n\tQueueHandle_t xNewQueue;\n\tconst UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;\n\n\t\txNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );\n\t\tprvInitialiseMutex( ( Queue_t * ) xNewQueue );\n\n\t\treturn xNewQueue;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )\n\t{\n\tQueueHandle_t xNewQueue;\n\tconst UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;\n\n\t\t/* Prevent compiler warnings about unused parameters if\n\t\tconfigUSE_TRACE_FACILITY does not equal 1. */\n\t\t( void ) ucQueueType;\n\n\t\txNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );\n\t\tprvInitialiseMutex( ( Queue_t * ) xNewQueue );\n\n\t\treturn xNewQueue;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n\n\tTaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )\n\t{\n\tTaskHandle_t pxReturn;\n\tQueue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;\n\n\t\t/* This function is called by xSemaphoreGetMutexHolder(), and should not\n\t\tbe called directly.  Note:  This is a good way of determining if the\n\t\tcalling task is the mutex holder, but not a good way of determining the\n\t\tidentity of the mutex holder, as the holder may change between the\n\t\tfollowing critical section exiting and the function returning. */\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tif( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t\t{\n\t\t\t\tpxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tpxReturn = NULL;\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn pxReturn;\n\t} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */\n\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n\n\tTaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )\n\t{\n\tTaskHandle_t pxReturn;\n\n\t\tconfigASSERT( xSemaphore );\n\n\t\t/* Mutexes cannot be used in interrupt service routines, so the mutex\n\t\tholder should not change in an ISR, and therefore a critical section is\n\t\tnot required here. */\n\t\tif( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t{\n\t\t\tpxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxReturn = NULL;\n\t\t}\n\n\t\treturn pxReturn;\n\t} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */\n\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n\n\tBaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxMutex = ( Queue_t * ) xMutex;\n\n\t\tconfigASSERT( pxMutex );\n\n\t\t/* If this is the task that holds the mutex then xMutexHolder will not\n\t\tchange outside of this task.  If this task does not hold the mutex then\n\t\tpxMutexHolder can never coincidentally equal the tasks handle, and as\n\t\tthis is the only condition we are interested in it does not matter if\n\t\tpxMutexHolder is accessed simultaneously by another task.  Therefore no\n\t\tmutual exclusion is required to test the pxMutexHolder variable. */\n\t\tif( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )\n\t\t{\n\t\t\ttraceGIVE_MUTEX_RECURSIVE( pxMutex );\n\n\t\t\t/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to\n\t\t\tthe task handle, therefore no underflow check is required.  Also,\n\t\t\tuxRecursiveCallCount is only modified by the mutex holder, and as\n\t\t\tthere can only be one, no mutual exclusion is required to modify the\n\t\t\tuxRecursiveCallCount member. */\n\t\t\t( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;\n\n\t\t\t/* Has the recursive call count unwound to 0? */\n\t\t\tif( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Return the mutex.  This will automatically unblock any other\n\t\t\t\ttask that might be waiting to access the mutex. */\n\t\t\t\t( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The mutex cannot be given because the calling task is not the\n\t\t\tholder. */\n\t\t\txReturn = pdFAIL;\n\n\t\t\ttraceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_RECURSIVE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n\n\tBaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxMutex = ( Queue_t * ) xMutex;\n\n\t\tconfigASSERT( pxMutex );\n\n\t\t/* Comments regarding mutual exclusion as per those within\n\t\txQueueGiveMutexRecursive(). */\n\n\t\ttraceTAKE_MUTEX_RECURSIVE( pxMutex );\n\n\t\tif( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )\n\t\t{\n\t\t\t( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );\n\n\t\t\t/* pdPASS will only be returned if the mutex was successfully\n\t\t\tobtained.  The calling task may have entered the Blocked state\n\t\t\tbefore reaching here. */\n\t\t\tif( xReturn != pdFAIL )\n\t\t\t{\n\t\t\t\t( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\ttraceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );\n\t\t\t}\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_RECURSIVE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )\n\t{\n\tQueueHandle_t xHandle;\n\n\t\tconfigASSERT( uxMaxCount != 0 );\n\t\tconfigASSERT( uxInitialCount <= uxMaxCount );\n\n\t\txHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\n\n\t\tif( xHandle != NULL )\n\t\t{\n\t\t\t( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\n\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE();\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE_FAILED();\n\t\t}\n\n\t\treturn xHandle;\n\t}\n\n#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )\n\t{\n\tQueueHandle_t xHandle;\n\n\t\tconfigASSERT( uxMaxCount != 0 );\n\t\tconfigASSERT( uxInitialCount <= uxMaxCount );\n\n\t\txHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\n\n\t\tif( xHandle != NULL )\n\t\t{\n\t\t\t( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\n\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE();\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE_FAILED();\n\t\t}\n\n\t\treturn xHandle;\n\t}\n\n#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )\n{\nBaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;\nTimeOut_t xTimeOut;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tconfigASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\tconfigASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\n\t/*lint -save -e904 This function relaxes the coding standard somewhat to\n\tallow return statements within the function itself.  This is done in the\n\tinterest of execution time efficiency. */\n\tfor( ;; )\n\t{\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Is there room on the queue now?  The running task must be the\n\t\t\thighest priority task wanting to access the queue.  If the head item\n\t\t\tin the queue is to be overwritten then it does not matter if the\n\t\t\tqueue is full. */\n\t\t\tif( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\n\t\t\t{\n\t\t\t\ttraceQUEUE_SEND( pxQueue );\n\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\t\t\t{\n\t\t\t\tUBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t\t\t\txYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* Do not notify the queue set as an existing item\n\t\t\t\t\t\t\twas overwritten in the queue so the number of items\n\t\t\t\t\t\t\tin the queue has not changed. */\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The queue is a member of a queue set, and posting\n\t\t\t\t\t\t\tto the queue set caused a higher priority task to\n\t\t\t\t\t\t\tunblock. A context switch is required. */\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* If there was a task waiting for data to arrive on the\n\t\t\t\t\t\tqueue then unblock it now. */\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t/* The unblocked task has a priority higher than\n\t\t\t\t\t\t\t\tour own so yield immediately.  Yes it is ok to\n\t\t\t\t\t\t\t\tdo this from within the critical section - the\n\t\t\t\t\t\t\t\tkernel takes care of that. */\n\t\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse if( xYieldRequired != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* This path is a special case that will only get\n\t\t\t\t\t\t\texecuted if the task was holding multiple mutexes\n\t\t\t\t\t\t\tand the mutexes were given back in an order that is\n\t\t\t\t\t\t\tdifferent to that in which they were taken. */\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\n\t\t\t\t{\n\t\t\t\t\txYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n\t\t\t\t\t/* If there was a task waiting for data to arrive on the\n\t\t\t\t\tqueue then unblock it now. */\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The unblocked task has a priority higher than\n\t\t\t\t\t\t\tour own so yield immediately.  Yes it is ok to do\n\t\t\t\t\t\t\tthis from within the critical section - the kernel\n\t\t\t\t\t\t\ttakes care of that. */\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse if( xYieldRequired != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* This path is a special case that will only get\n\t\t\t\t\t\texecuted if the task was holding multiple mutexes and\n\t\t\t\t\t\tthe mutexes were given back in an order that is\n\t\t\t\t\t\tdifferent to that in which they were taken. */\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\n\n\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\treturn pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was full and no block time is specified (or\n\t\t\t\t\tthe block time has expired) so leave now. */\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\t\t\t/* Return to the original privilege level before exiting\n\t\t\t\t\tthe function. */\n\t\t\t\t\ttraceQUEUE_SEND_FAILED( pxQueue );\n\t\t\t\t\treturn errQUEUE_FULL;\n\t\t\t\t}\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was full and a block time was specified so\n\t\t\t\t\tconfigure the timeout structure. */\n\t\t\t\t\tvTaskInternalSetTimeOutState( &xTimeOut );\n\t\t\t\t\txEntryTimeSet = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Entry time was already set. */\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Interrupts and other tasks can send to and receive from the queue\n\t\tnow the critical section has been exited. */\n\n\t\tvTaskSuspendAll();\n\t\tprvLockQueue( pxQueue );\n\n\t\t/* Update the timeout state to see if it has expired yet. */\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n\t\t{\n\t\t\tif( prvIsQueueFull( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceBLOCKING_ON_QUEUE_SEND( pxQueue );\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\n\n\t\t\t\t/* Unlocking the queue means queue events can effect the\n\t\t\t\tevent list.  It is possible that interrupts occurring now\n\t\t\t\tremove this task from the event list again - but as the\n\t\t\t\tscheduler is suspended the task will go onto the pending\n\t\t\t\tready last instead of the actual ready list. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\n\t\t\t\t/* Resuming the scheduler will move tasks from the pending\n\t\t\t\tready list into the ready list - so it is feasible that this\n\t\t\t\ttask is already in a ready list before it yields - in which\n\t\t\t\tcase the yield will not cause a context switch unless there\n\t\t\t\tis also a higher priority task in the pending ready list. */\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Try again. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The timeout has expired. */\n\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t( void ) xTaskResumeAll();\n\n\t\t\ttraceQUEUE_SEND_FAILED( pxQueue );\n\t\t\treturn errQUEUE_FULL;\n\t\t}\n\t} /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )\n{\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tconfigASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\tconfigASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t/* Similar to xQueueGenericSend, except without blocking if there is no room\n\tin the queue.  Also don't directly wake a task that was blocked on a queue\n\tread, instead return a flag to say whether a context switch is required or\n\tnot (i.e. has a task with a higher priority than us been woken by this\n\tpost). */\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tif( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\n\t\t{\n\t\t\tconst int8_t cTxLock = pxQueue->cTxLock;\n\n\t\t\ttraceQUEUE_SEND_FROM_ISR( pxQueue );\n\n\t\t\t/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a\n\t\t\tsemaphore or mutex.  That means prvCopyDataToQueue() cannot result\n\t\t\tin a task disinheriting a priority and prvCopyDataToQueue() can be\n\t\t\tcalled here even though the disinherit function does not check if\n\t\t\tthe scheduler is suspended before accessing the ready lists. */\n\t\t\t( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n\t\t\t/* The event list is not altered if the queue is locked.  This will\n\t\t\tbe done when the queue is unlocked later. */\n\t\t\tif( cTxLock == queueUNLOCKED )\n\t\t\t{\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\t\t\t{\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The queue is a member of a queue set, and posting\n\t\t\t\t\t\t\tto the queue set caused a higher priority task to\n\t\t\t\t\t\t\tunblock.  A context switch is required. */\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t/* The task waiting has a higher priority so\n\t\t\t\t\t\t\t\trecord that a context switch is required. */\n\t\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\n\t\t\t\t{\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\n\t\t\t\t\t\t\tcontext\tswitch is required. */\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\n\t\t\t\tknows that data was posted while it was locked. */\n\t\t\t\tpxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\n\t\t\txReturn = errQUEUE_FULL;\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )\n{\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\nQueue_t * const pxQueue = xQueue;\n\n\t/* Similar to xQueueGenericSendFromISR() but used with semaphores where the\n\titem size is 0.  Don't directly wake a task that was blocked on a queue\n\tread, instead return a flag to say whether a context switch is required or\n\tnot (i.e. has a task with a higher priority than us been woken by this\n\tpost). */\n\n\tconfigASSERT( pxQueue );\n\n\t/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()\n\tif the item size is not 0. */\n\tconfigASSERT( pxQueue->uxItemSize == 0 );\n\n\t/* Normally a mutex would not be given from an interrupt, especially if\n\tthere is a mutex holder, as priority inheritance makes no sense for an\n\tinterrupts, only tasks. */\n\tconfigASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tconst UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t/* When the queue is used to implement a semaphore no data is ever\n\t\tmoved through the queue but it is still valid to see if the queue 'has\n\t\tspace'. */\n\t\tif( uxMessagesWaiting < pxQueue->uxLength )\n\t\t{\n\t\t\tconst int8_t cTxLock = pxQueue->cTxLock;\n\n\t\t\ttraceQUEUE_SEND_FROM_ISR( pxQueue );\n\n\t\t\t/* A task can only have an inherited priority if it is a mutex\n\t\t\tholder - and if there is a mutex holder then the mutex cannot be\n\t\t\tgiven from an ISR.  As this is the ISR version of the function it\n\t\t\tcan be assumed there is no mutex holder and no need to determine if\n\t\t\tpriority disinheritance is needed.  Simply increase the count of\n\t\t\tmessages (semaphores) available. */\n\t\t\tpxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;\n\n\t\t\t/* The event list is not altered if the queue is locked.  This will\n\t\t\tbe done when the queue is unlocked later. */\n\t\t\tif( cTxLock == queueUNLOCKED )\n\t\t\t{\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\t\t\t{\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The semaphore is a member of a queue set, and\n\t\t\t\t\t\t\tposting\tto the queue set caused a higher priority\n\t\t\t\t\t\t\ttask to\tunblock.  A context switch is required. */\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t/* The task waiting has a higher priority so\n\t\t\t\t\t\t\t\trecord that a context switch is required. */\n\t\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\n\t\t\t\t{\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\n\t\t\t\t\t\t\tcontext\tswitch is required. */\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\n\t\t\t\tknows that data was posted while it was locked. */\n\t\t\t\tpxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\n\t\t\txReturn = errQUEUE_FULL;\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )\n{\nBaseType_t xEntryTimeSet = pdFALSE;\nTimeOut_t xTimeOut;\nQueue_t * const pxQueue = xQueue;\n\n\t/* Check the pointer is not NULL. */\n\tconfigASSERT( ( pxQueue ) );\n\n\t/* The buffer into which data is received can only be NULL if the data size\n\tis zero (so no data is copied into the buffer. */\n\tconfigASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n\t/* Cannot block if the scheduler is suspended. */\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\n\t/*lint -save -e904  This function relaxes the coding standard somewhat to\n\tallow return statements within the function itself.  This is done in the\n\tinterest of execution time efficiency. */\n\tfor( ;; )\n\t{\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tconst UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t\t/* Is there data in the queue now?  To be running the calling task\n\t\t\tmust be the highest priority task wanting to access the queue. */\n\t\t\tif( uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Data available, remove one item. */\n\t\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\n\t\t\t\ttraceQUEUE_RECEIVE( pxQueue );\n\t\t\t\tpxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;\n\n\t\t\t\t/* There is now space in the queue, were any tasks waiting to\n\t\t\t\tpost to the queue?  If so, unblock the highest priority waiting\n\t\t\t\ttask. */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\treturn pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was empty and no block time is specified (or\n\t\t\t\t\tthe block time has expired) so leave now. */\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\n\t\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t\t}\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was empty and a block time was specified so\n\t\t\t\t\tconfigure the timeout structure. */\n\t\t\t\t\tvTaskInternalSetTimeOutState( &xTimeOut );\n\t\t\t\t\txEntryTimeSet = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Entry time was already set. */\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Interrupts and other tasks can send to and receive from the queue\n\t\tnow the critical section has been exited. */\n\n\t\tvTaskSuspendAll();\n\t\tprvLockQueue( pxQueue );\n\n\t\t/* Update the timeout state to see if it has expired yet. */\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n\t\t{\n\t\t\t/* The timeout has not expired.  If the queue is still empty place\n\t\t\tthe task on the list of tasks waiting to receive from the queue. */\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The queue contains data again.  Loop back to try and read the\n\t\t\t\tdata. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Timed out.  If there is no data in the queue exit, otherwise loop\n\t\t\tback and attempt to read the data. */\n\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t( void ) xTaskResumeAll();\n\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\n\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t} /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )\n{\nBaseType_t xEntryTimeSet = pdFALSE;\nTimeOut_t xTimeOut;\nQueue_t * const pxQueue = xQueue;\n\n#if( configUSE_MUTEXES == 1 )\n\tBaseType_t xInheritanceOccurred = pdFALSE;\n#endif\n\n\t/* Check the queue pointer is not NULL. */\n\tconfigASSERT( ( pxQueue ) );\n\n\t/* Check this really is a semaphore, in which case the item size will be\n\t0. */\n\tconfigASSERT( pxQueue->uxItemSize == 0 );\n\n\t/* Cannot block if the scheduler is suspended. */\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\n\t/*lint -save -e904 This function relaxes the coding standard somewhat to allow return\n\tstatements within the function itself.  This is done in the interest\n\tof execution time efficiency. */\n\tfor( ;; )\n\t{\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Semaphores are queues with an item size of 0, and where the\n\t\t\tnumber of messages in the queue is the semaphore's count value. */\n\t\t\tconst UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;\n\n\t\t\t/* Is there data in the queue now?  To be running the calling task\n\t\t\tmust be the highest priority task wanting to access the queue. */\n\t\t\tif( uxSemaphoreCount > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\ttraceQUEUE_RECEIVE( pxQueue );\n\n\t\t\t\t/* Semaphores are queues with a data size of zero and where the\n\t\t\t\tmessages waiting is the semaphore's count.  Reduce the count. */\n\t\t\t\tpxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;\n\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t\t{\n\t\t\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Record the information required to implement\n\t\t\t\t\t\tpriority inheritance should it become necessary. */\n\t\t\t\t\t\tpxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_MUTEXES */\n\n\t\t\t\t/* Check to see if other tasks are blocked waiting to give the\n\t\t\t\tsemaphore, and if so, unblock the highest priority such task. */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\treturn pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* For inheritance to have occurred there must have been an\n\t\t\t\t\tinitial timeout, and an adjusted timeout cannot become 0, as\n\t\t\t\t\tif it were 0 the function would have exited. */\n\t\t\t\t\t#if( configUSE_MUTEXES == 1 )\n\t\t\t\t\t{\n\t\t\t\t\t\tconfigASSERT( xInheritanceOccurred == pdFALSE );\n\t\t\t\t\t}\n\t\t\t\t\t#endif /* configUSE_MUTEXES */\n\n\t\t\t\t\t/* The semaphore count was 0 and no block time is specified\n\t\t\t\t\t(or the block time has expired) so exit now. */\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\n\t\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t\t}\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The semaphore count was 0 and a block time was specified\n\t\t\t\t\tso configure the timeout structure ready to block. */\n\t\t\t\t\tvTaskInternalSetTimeOutState( &xTimeOut );\n\t\t\t\t\txEntryTimeSet = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Entry time was already set. */\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Interrupts and other tasks can give to and take from the semaphore\n\t\tnow the critical section has been exited. */\n\n\t\tvTaskSuspendAll();\n\t\tprvLockQueue( pxQueue );\n\n\t\t/* Update the timeout state to see if it has expired yet. */\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n\t\t{\n\t\t\t/* A block time is specified and not expired.  If the semaphore\n\t\t\tcount is 0 then enter the Blocked state to wait for a semaphore to\n\t\t\tbecome available.  As semaphores are implemented with queues the\n\t\t\tqueue being empty is equivalent to the semaphore count being 0. */\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\n\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t\t{\n\t\t\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t\t\t\t{\n\t\t\t\t\t\ttaskENTER_CRITICAL();\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\txInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );\n\t\t\t\t\t\t}\n\t\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* There was no timeout and the semaphore count was not 0, so\n\t\t\t\tattempt to take the semaphore again. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Timed out. */\n\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t( void ) xTaskResumeAll();\n\n\t\t\t/* If the semaphore count is 0 exit now as the timeout has\n\t\t\texpired.  Otherwise return to attempt to take the semaphore that is\n\t\t\tknown to be available.  As semaphores are implemented by queues the\n\t\t\tqueue being empty is equivalent to the semaphore count being 0. */\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* xInheritanceOccurred could only have be set if\n\t\t\t\t\tpxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to\n\t\t\t\t\ttest the mutex type again to check it is actually a mutex. */\n\t\t\t\t\tif( xInheritanceOccurred != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\ttaskENTER_CRITICAL();\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tUBaseType_t uxHighestWaitingPriority;\n\n\t\t\t\t\t\t\t/* This task blocking on the mutex caused another\n\t\t\t\t\t\t\ttask to inherit this task's priority.  Now this task\n\t\t\t\t\t\t\thas timed out the priority should be disinherited\n\t\t\t\t\t\t\tagain, but only as low as the next highest priority\n\t\t\t\t\t\t\ttask that is waiting for the same mutex. */\n\t\t\t\t\t\t\tuxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );\n\t\t\t\t\t\t\tvTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );\n\t\t\t\t\t\t}\n\t\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_MUTEXES */\n\n\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\n\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t} /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )\n{\nBaseType_t xEntryTimeSet = pdFALSE;\nTimeOut_t xTimeOut;\nint8_t *pcOriginalReadPosition;\nQueue_t * const pxQueue = xQueue;\n\n\t/* Check the pointer is not NULL. */\n\tconfigASSERT( ( pxQueue ) );\n\n\t/* The buffer into which data is received can only be NULL if the data size\n\tis zero (so no data is copied into the buffer. */\n\tconfigASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n\t/* Cannot block if the scheduler is suspended. */\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\n\t/*lint -save -e904  This function relaxes the coding standard somewhat to\n\tallow return statements within the function itself.  This is done in the\n\tinterest of execution time efficiency. */\n\tfor( ;; )\n\t{\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tconst UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t\t/* Is there data in the queue now?  To be running the calling task\n\t\t\tmust be the highest priority task wanting to access the queue. */\n\t\t\tif( uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Remember the read position so it can be reset after the data\n\t\t\t\tis read from the queue as this function is only peeking the\n\t\t\t\tdata, not removing it. */\n\t\t\t\tpcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;\n\n\t\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\n\t\t\t\ttraceQUEUE_PEEK( pxQueue );\n\n\t\t\t\t/* The data is not being removed, so reset the read pointer. */\n\t\t\t\tpxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;\n\n\t\t\t\t/* The data is being left in the queue, so see if there are\n\t\t\t\tany other tasks waiting for the data. */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The task waiting has a higher priority than this task. */\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\treturn pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was empty and no block time is specified (or\n\t\t\t\t\tthe block time has expired) so leave now. */\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\ttraceQUEUE_PEEK_FAILED( pxQueue );\n\t\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t\t}\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was empty and a block time was specified so\n\t\t\t\t\tconfigure the timeout structure ready to enter the blocked\n\t\t\t\t\tstate. */\n\t\t\t\t\tvTaskInternalSetTimeOutState( &xTimeOut );\n\t\t\t\t\txEntryTimeSet = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Entry time was already set. */\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Interrupts and other tasks can send to and receive from the queue\n\t\tnow the critical section has been exited. */\n\n\t\tvTaskSuspendAll();\n\t\tprvLockQueue( pxQueue );\n\n\t\t/* Update the timeout state to see if it has expired yet. */\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n\t\t{\n\t\t\t/* Timeout has not expired yet, check to see if there is data in the\n\t\t\tqueue now, and if not enter the Blocked state to wait for data. */\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceBLOCKING_ON_QUEUE_PEEK( pxQueue );\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* There is data in the queue now, so don't enter the blocked\n\t\t\t\tstate, instead return to try and obtain the data. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The timeout has expired.  If there is still no data in the queue\n\t\t\texit, otherwise go back and try to read the data again. */\n\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t( void ) xTaskResumeAll();\n\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceQUEUE_PEEK_FAILED( pxQueue );\n\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t} /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )\n{\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tconfigASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tconst UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t/* Cannot block in an ISR, so check there is data available. */\n\t\tif( uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\tconst int8_t cRxLock = pxQueue->cRxLock;\n\n\t\t\ttraceQUEUE_RECEIVE_FROM_ISR( pxQueue );\n\n\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\n\t\t\tpxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;\n\n\t\t\t/* If the queue is locked the event list will not be modified.\n\t\t\tInstead update the lock count so the task that unlocks the queue\n\t\t\twill know that an ISR has removed data while the queue was\n\t\t\tlocked. */\n\t\t\tif( cRxLock == queueUNLOCKED )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The task waiting has a higher priority than us so\n\t\t\t\t\t\tforce a context switch. */\n\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\n\t\t\t\tknows that data was removed while it was locked. */\n\t\t\t\tpxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t\ttraceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )\n{\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\nint8_t *pcOriginalReadPosition;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tconfigASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\tconfigASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\t/* Cannot block in an ISR, so check there is data available. */\n\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\ttraceQUEUE_PEEK_FROM_ISR( pxQueue );\n\n\t\t\t/* Remember the read position so it can be reset as nothing is\n\t\t\tactually being removed from the queue. */\n\t\t\tpcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;\n\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\n\t\t\tpxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t\ttraceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )\n{\nUBaseType_t uxReturn;\n\n\tconfigASSERT( xQueue );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tuxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )\n{\nUBaseType_t uxReturn;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tuxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )\n{\nUBaseType_t uxReturn;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tuxReturn = pxQueue->uxMessagesWaiting;\n\n\treturn uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nvoid vQueueDelete( QueueHandle_t xQueue )\n{\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\ttraceQUEUE_DELETE( pxQueue );\n\n\t#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\t{\n\t\tvQueueUnregisterQueue( pxQueue );\n\t}\n\t#endif\n\n\t#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )\n\t{\n\t\t/* The queue can only have been allocated dynamically - free it\n\t\tagain. */\n\t\tvPortFree( pxQueue );\n\t}\n\t#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\t{\n\t\t/* The queue could have been allocated statically or dynamically, so\n\t\tcheck before attempting to free the memory. */\n\t\tif( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )\n\t\t{\n\t\t\tvPortFree( pxQueue );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\t#else\n\t{\n\t\t/* The queue must have been statically allocated, so is not going to be\n\t\tdeleted.  Avoid compiler warnings about the unused parameter. */\n\t\t( void ) pxQueue;\n\t}\n\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )\n\t{\n\t\treturn ( ( Queue_t * ) xQueue )->uxQueueNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )\n\t{\n\t\t( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tuint8_t ucQueueGetQueueType( QueueHandle_t xQueue )\n\t{\n\t\treturn ( ( Queue_t * ) xQueue )->ucQueueType;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_MUTEXES == 1 )\n\n\tstatic UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )\n\t{\n\tUBaseType_t uxHighestPriorityOfWaitingTasks;\n\n\t\t/* If a task waiting for a mutex causes the mutex holder to inherit a\n\t\tpriority, but the waiting task times out, then the holder should\n\t\tdisinherit the priority - but only down to the highest priority of any\n\t\tother tasks that are waiting for the same mutex.  For this purpose,\n\t\treturn the priority of the highest priority task that is waiting for the\n\t\tmutex. */\n\t\tif( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )\n\t\t{\n\t\t\tuxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tuxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;\n\t\t}\n\n\t\treturn uxHighestPriorityOfWaitingTasks;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )\n{\nBaseType_t xReturn = pdFALSE;\nUBaseType_t uxMessagesWaiting;\n\n\t/* This function is called from a critical section. */\n\n\tuxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\tif( pxQueue->uxItemSize == ( UBaseType_t ) 0 )\n\t{\n\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t{\n\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t\t{\n\t\t\t\t/* The mutex is no longer being held. */\n\t\t\t\txReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );\n\t\t\t\tpxQueue->u.xSemaphore.xMutexHolder = NULL;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configUSE_MUTEXES */\n\t}\n\telse if( xPosition == queueSEND_TO_BACK )\n\t{\n\t\t( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */\n\t\tpxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */\n\t\tif( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\n\t\t{\n\t\t\tpxQueue->pcWriteTo = pxQueue->pcHead;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\t( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */\n\t\tpxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;\n\t\tif( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\n\t\t{\n\t\t\tpxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\tif( xPosition == queueOVERWRITE )\n\t\t{\n\t\t\tif( uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* An item is not being added but overwritten, so subtract\n\t\t\t\tone from the recorded number of items in the queue so when\n\t\t\t\tone is added again below the number of recorded items remains\n\t\t\t\tcorrect. */\n\t\t\t\t--uxMessagesWaiting;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n\tpxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )\n{\n\tif( pxQueue->uxItemSize != ( UBaseType_t ) 0 )\n\t{\n\t\tpxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */\n\t\tif( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */\n\t\t{\n\t\t\tpxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvUnlockQueue( Queue_t * const pxQueue )\n{\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\n\n\t/* The lock counts contains the number of extra data items placed or\n\tremoved from the queue while the queue was locked.  When a queue is\n\tlocked items can be added or removed, but the event lists cannot be\n\tupdated. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tint8_t cTxLock = pxQueue->cTxLock;\n\n\t\t/* See if data was added to the queue while it was locked. */\n\t\twhile( cTxLock > queueLOCKED_UNMODIFIED )\n\t\t{\n\t\t\t/* Data was posted while the queue was locked.  Are any tasks\n\t\t\tblocked waiting for data to become available? */\n\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\t\t{\n\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\n\t\t\t\t{\n\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The queue is a member of a queue set, and posting to\n\t\t\t\t\t\tthe queue set caused a higher priority task to unblock.\n\t\t\t\t\t\tA context switch is required. */\n\t\t\t\t\t\tvTaskMissedYield();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Tasks that are removed from the event list will get\n\t\t\t\t\tadded to the pending ready list as the scheduler is still\n\t\t\t\t\tsuspended. */\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\n\t\t\t\t\t\t\tcontext\tswitch is required. */\n\t\t\t\t\t\t\tvTaskMissedYield();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\t#else /* configUSE_QUEUE_SETS */\n\t\t\t{\n\t\t\t\t/* Tasks that are removed from the event list will get added to\n\t\t\t\tthe pending ready list as the scheduler is still suspended. */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The task waiting has a higher priority so record that\n\t\t\t\t\t\ta context switch is required. */\n\t\t\t\t\t\tvTaskMissedYield();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif /* configUSE_QUEUE_SETS */\n\n\t\t\t--cTxLock;\n\t\t}\n\n\t\tpxQueue->cTxLock = queueUNLOCKED;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\t/* Do the same for the Rx lock. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tint8_t cRxLock = pxQueue->cRxLock;\n\n\t\twhile( cRxLock > queueLOCKED_UNMODIFIED )\n\t\t{\n\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t{\n\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tvTaskMissedYield();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t--cRxLock;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tpxQueue->cRxLock = queueUNLOCKED;\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )\n{\nBaseType_t xReturn;\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )\n\t\t{\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )\n{\nBaseType_t xReturn;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvIsQueueFull( const Queue_t *pxQueue )\n{\nBaseType_t xReturn;\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\n\t\t{\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )\n{\nBaseType_t xReturn;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tif( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n\tBaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* If the queue is already full we may have to block.  A critical section\n\t\tis required to prevent an interrupt removing something from the queue\n\t\tbetween the check to see if the queue is full and blocking on the queue. */\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tif( prvIsQueueFull( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\t/* The queue is full - do we want to block or just leave without\n\t\t\t\tposting? */\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* As this is called from a coroutine we cannot block directly, but\n\t\t\t\t\treturn indicating that we need to block. */\n\t\t\t\t\tvCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t\treturn errQUEUE_BLOCKED;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t\treturn errQUEUE_FULL;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tif( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\n\t\t\t{\n\t\t\t\t/* There is room in the queue, copy the data into the queue. */\n\t\t\t\tprvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\n\t\t\t\txReturn = pdPASS;\n\n\t\t\t\t/* Were any co-routines waiting for data to become available? */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* In this instance the co-routine could be placed directly\n\t\t\t\t\tinto the ready list as we are within a critical section.\n\t\t\t\t\tInstead the same pending ready list mechanism is used as if\n\t\t\t\t\tthe event were caused from within an interrupt. */\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The co-routine waiting has a higher priority so record\n\t\t\t\t\t\tthat a yield might be appropriate. */\n\t\t\t\t\t\txReturn = errQUEUE_YIELD;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = errQUEUE_FULL;\n\t\t\t}\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n\tBaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* If the queue is already empty we may have to block.  A critical section\n\t\tis required to prevent an interrupt adding something to the queue\n\t\tbetween the check to see if the queue is empty and blocking on the queue. */\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* There are no messages in the queue, do we want to block or just\n\t\t\t\tleave with nothing? */\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* As this is a co-routine we cannot block directly, but return\n\t\t\t\t\tindicating that we need to block. */\n\t\t\t\t\tvCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t\treturn errQUEUE_BLOCKED;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t\treturn errQUEUE_FULL;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Data is available from the queue. */\n\t\t\t\tpxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;\n\t\t\t\tif( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )\n\t\t\t\t{\n\t\t\t\t\tpxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t\t--( pxQueue->uxMessagesWaiting );\n\t\t\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\n\n\t\t\t\txReturn = pdPASS;\n\n\t\t\t\t/* Were any co-routines waiting for space to become available? */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* In this instance the co-routine could be placed directly\n\t\t\t\t\tinto the ready list as we are within a critical section.\n\t\t\t\t\tInstead the same pending ready list mechanism is used as if\n\t\t\t\t\tthe event were caused from within an interrupt. */\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\txReturn = errQUEUE_YIELD;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n\tBaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )\n\t{\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* Cannot block within an ISR so if there is no space on the queue then\n\t\texit without doing anything. */\n\t\tif( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\n\t\t{\n\t\t\tprvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\n\n\t\t\t/* We only want to wake one co-routine per ISR, so check that a\n\t\t\tco-routine has not already been woken. */\n\t\t\tif( xCoRoutinePreviouslyWoken == pdFALSE )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\treturn pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xCoRoutinePreviouslyWoken;\n\t}\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n\tBaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* We cannot block from an ISR, so check there is data available. If\n\t\tnot then just leave without doing anything. */\n\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\t/* Copy the data from the queue. */\n\t\t\tpxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;\n\t\t\tif( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )\n\t\t\t{\n\t\t\t\tpxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t\t--( pxQueue->uxMessagesWaiting );\n\t\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\n\n\t\t\tif( ( *pxCoRoutineWoken ) == pdFALSE )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t*pxCoRoutineWoken = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n\tvoid vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t{\n\tUBaseType_t ux;\n\n\t\t/* See if there is an empty space in the registry.  A NULL name denotes\n\t\ta free slot. */\n\t\tfor( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n\t\t{\n\t\t\tif( xQueueRegistry[ ux ].pcQueueName == NULL )\n\t\t\t{\n\t\t\t\t/* Store the information on this queue. */\n\t\t\t\txQueueRegistry[ ux ].pcQueueName = pcQueueName;\n\t\t\t\txQueueRegistry[ ux ].xHandle = xQueue;\n\n\t\t\t\ttraceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t}\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n\tconst char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t{\n\tUBaseType_t ux;\n\tconst char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n\t\t/* Note there is nothing here to protect against another task adding or\n\t\tremoving entries from the registry while it is being searched. */\n\t\tfor( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n\t\t{\n\t\t\tif( xQueueRegistry[ ux ].xHandle == xQueue )\n\t\t\t{\n\t\t\t\tpcReturn = xQueueRegistry[ ux ].pcQueueName;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\treturn pcReturn;\n\t} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n\tvoid vQueueUnregisterQueue( QueueHandle_t xQueue )\n\t{\n\tUBaseType_t ux;\n\n\t\t/* See if the handle of the queue being unregistered in actually in the\n\t\tregistry. */\n\t\tfor( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n\t\t{\n\t\t\tif( xQueueRegistry[ ux ].xHandle == xQueue )\n\t\t\t{\n\t\t\t\t/* Set the name to NULL to show that this slot if free again. */\n\t\t\t\txQueueRegistry[ ux ].pcQueueName = NULL;\n\n\t\t\t\t/* Set the handle to NULL to ensure the same queue handle cannot\n\t\t\t\tappear in the registry twice if it is added, removed, then\n\t\t\t\tadded again. */\n\t\t\t\txQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TIMERS == 1 )\n\n\tvoid vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )\n\t{\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* This function should not be called by application code hence the\n\t\t'Restricted' in its name.  It is not part of the public API.  It is\n\t\tdesigned for use by kernel code, and has special calling requirements.\n\t\tIt can result in vListInsert() being called on a list that can only\n\t\tpossibly ever have one item in it, so the list will be fast, but even\n\t\tso it should be called with the scheduler locked and not from a critical\n\t\tsection. */\n\n\t\t/* Only do anything if there are no messages in the queue.  This function\n\t\twill not actually cause the task to block, just place it on a blocked\n\t\tlist.  It will not block until the scheduler is unlocked - at which\n\t\ttime a yield will be performed.  If an item is added to the queue while\n\t\tthe queue is locked, and the calling task blocks on the queue, then the\n\t\tcalling task will be immediately unblocked when the queue is unlocked. */\n\t\tprvLockQueue( pxQueue );\n\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )\n\t\t{\n\t\t\t/* There is nothing in the queue, block for the specified period. */\n\t\t\tvTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t\tprvUnlockQueue( pxQueue );\n\t}\n\n#endif /* configUSE_TIMERS */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tQueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )\n\t{\n\tQueueSetHandle_t pxQueue;\n\n\t\tpxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );\n\n\t\treturn pxQueue;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tBaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\n\t{\n\tBaseType_t xReturn;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tif( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )\n\t\t\t{\n\t\t\t\t/* Cannot add a queue/semaphore to more than one queue set. */\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t\telse if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Cannot add a queue/semaphore to a queue set if there are already\n\t\t\t\titems in the queue/semaphore. */\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;\n\t\t\t\txReturn = pdPASS;\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tBaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;\n\n\t\tif( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )\n\t\t{\n\t\t\t/* The queue was not a member of the set. */\n\t\t\txReturn = pdFAIL;\n\t\t}\n\t\telse if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )\n\t\t{\n\t\t\t/* It is dangerous to remove a queue from a set when the queue is\n\t\t\tnot empty because the queue set will still hold pending events for\n\t\t\tthe queue. */\n\t\t\txReturn = pdFAIL;\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\t/* The queue is no longer contained in the set. */\n\t\t\t\tpxQueueOrSemaphore->pxQueueSetContainer = NULL;\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\t\t\txReturn = pdPASS;\n\t\t}\n\n\t\treturn xReturn;\n\t} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tQueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )\n\t{\n\tQueueSetMemberHandle_t xReturn = NULL;\n\n\t\t( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tQueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )\n\t{\n\tQueueSetMemberHandle_t xReturn = NULL;\n\n\t\t( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tstatic BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )\n\t{\n\tQueue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;\n\tBaseType_t xReturn = pdFALSE;\n\n\t\t/* This function must be called form a critical section. */\n\n\t\tconfigASSERT( pxQueueSetContainer );\n\t\tconfigASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );\n\n\t\tif( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )\n\t\t{\n\t\t\tconst int8_t cTxLock = pxQueueSetContainer->cTxLock;\n\n\t\t\ttraceQUEUE_SEND( pxQueueSetContainer );\n\n\t\t\t/* The data copied is the handle of the queue that contains data. */\n\t\t\txReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );\n\n\t\t\tif( cTxLock == queueUNLOCKED )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The task waiting has a higher priority. */\n\t\t\t\t\t\txReturn = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tpxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n\n\n\n\n\n\n\n\n\n\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/stream_buffer.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/* Standard includes. */\n#include <stdint.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"stream_buffer.h\"\n\n#if( configUSE_TASK_NOTIFICATIONS != 1 )\n\t#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c\n#endif\n\n/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n/* If the user has not provided application specific Rx notification macros,\nor #defined the notification macros away, them provide default implementations\nthat uses task notifications. */\n/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */\n#ifndef sbRECEIVE_COMPLETED\n\t#define sbRECEIVE_COMPLETED( pxStreamBuffer )\t\t\t\t\t\t\t\t\t\t\\\n\t\tvTaskSuspendAll();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tif( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,\t\t\t\\\n\t\t\t\t\t\t\t\t\t  ( uint32_t ) 0,\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t  eNoAction );\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( pxStreamBuffer )->xTaskWaitingToSend = NULL;\t\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t( void ) xTaskResumeAll();\n#endif /* sbRECEIVE_COMPLETED */\n\n#ifndef sbRECEIVE_COMPLETED_FROM_ISR\n\t#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t  pxHigherPriorityTaskWoken )\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tUBaseType_t uxSavedInterruptStatus;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tuxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tif( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,\t\\\n\t\t\t\t\t\t\t\t\t\t\t ( uint32_t ) 0,\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t eNoAction,\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t pxHigherPriorityTaskWoken );\t\t\t\t\\\n\t\t\t\t( pxStreamBuffer )->xTaskWaitingToSend = NULL;\t\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\t\t\t\t\t\\\n\t}\n#endif /* sbRECEIVE_COMPLETED_FROM_ISR */\n\n/* If the user has not provided an application specific Tx notification macro,\nor #defined the notification macro away, them provide a default implementation\nthat uses task notifications. */\n#ifndef sbSEND_COMPLETED\n\t#define sbSEND_COMPLETED( pxStreamBuffer )\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tvTaskSuspendAll();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tif( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,\t\t\\\n\t\t\t\t\t\t\t\t\t  ( uint32_t ) 0,\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t  eNoAction );\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( pxStreamBuffer )->xTaskWaitingToReceive = NULL;\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t( void ) xTaskResumeAll();\n#endif /* sbSEND_COMPLETED */\n\n#ifndef sbSEND_COMPLETE_FROM_ISR\n\t#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tUBaseType_t uxSavedInterruptStatus;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tuxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tif( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,\t\\\n\t\t\t\t\t\t\t\t\t\t\t ( uint32_t ) 0,\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t eNoAction,\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t pxHigherPriorityTaskWoken );\t\t\t\t\\\n\t\t\t\t( pxStreamBuffer )->xTaskWaitingToReceive = NULL;\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\t\t\t\t\t\\\n\t}\n#endif /* sbSEND_COMPLETE_FROM_ISR */\n/*lint -restore (9026) */\n\n/* The number of bytes used to hold the length of a message in the buffer. */\n#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )\n\n/* Bits stored in the ucFlags field of the stream buffer. */\n#define sbFLAGS_IS_MESSAGE_BUFFER\t\t( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */\n#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */\n\n/*-----------------------------------------------------------*/\n\n/* Structure that hold state information on the buffer. */\ntypedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */\n{\n\tvolatile size_t xTail;\t\t\t\t/* Index to the next item to read within the buffer. */\n\tvolatile size_t xHead;\t\t\t\t/* Index to the next item to write within the buffer. */\n\tsize_t xLength;\t\t\t\t\t\t/* The length of the buffer pointed to by pucBuffer. */\n\tsize_t xTriggerLevelBytes;\t\t\t/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */\n\tvolatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */\n\tvolatile TaskHandle_t xTaskWaitingToSend;\t/* Holds the handle of a task waiting to send data to a message buffer that is full. */\n\tuint8_t *pucBuffer;\t\t\t\t\t/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */\n\tuint8_t ucFlags;\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxStreamBufferNumber;\t\t/* Used for tracing purposes. */\n\t#endif\n} StreamBuffer_t;\n\n/*\n * The number of bytes available to be read from the buffer.\n */\nstatic size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/*\n * Add xCount bytes from pucData into the pxStreamBuffer message buffer.\n * Returns the number of bytes written, which will either equal xCount in the\n * success case, or 0 if there was not enough space in the buffer (in which case\n * no data is written into the buffer).\n */\nstatic size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;\n\n/*\n * If the stream buffer is being used as a message buffer, then reads an entire\n * message out of the buffer.  If the stream buffer is being used as a stream\n * buffer then read as many bytes as possible from the buffer.\n * prvReadBytesFromBuffer() is called to actually extract the bytes from the\n * buffer's data storage area.\n */\nstatic size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\tvoid *pvRxData,\n\t\t\t\t\t\t\t\t\t\tsize_t xBufferLengthBytes,\n\t\t\t\t\t\t\t\t\t\tsize_t xBytesAvailable,\n\t\t\t\t\t\t\t\t\t\tsize_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;\n\n/*\n * If the stream buffer is being used as a message buffer, then writes an entire\n * message to the buffer.  If the stream buffer is being used as a stream\n * buffer then write as many bytes as possible to the buffer.\n * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's\n * data storage area.\n */\nstatic size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\tconst void * pvTxData,\n\t\t\t\t\t\t\t\t\t\tsize_t xDataLengthBytes,\n\t\t\t\t\t\t\t\t\t\tsize_t xSpace,\n\t\t\t\t\t\t\t\t\t\tsize_t xRequiredSpace ) PRIVILEGED_FUNCTION;\n\n/*\n * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them\n * to pucData.\n */\nstatic size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t  uint8_t *pucData,\n\t\t\t\t\t\t\t\t\t  size_t xMaxCount,\n\t\t\t\t\t\t\t\t\t  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;\n\n/*\n * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to\n * initialise the members of the newly created stream buffer structure.\n */\nstatic void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\t  uint8_t * const pucBuffer,\n\t\t\t\t\t\t\t\t\t\t  size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t  size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t  uint8_t ucFlags ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tStreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )\n\t{\n\tuint8_t *pucAllocatedMemory;\n\tuint8_t ucFlags;\n\n\t\t/* In case the stream buffer is going to be used as a message buffer\n\t\t(that is, it will hold discrete messages with a little meta data that\n\t\tsays how big the next message is) check the buffer will be large enough\n\t\tto hold at least one message. */\n\t\tif( xIsMessageBuffer == pdTRUE )\n\t\t{\n\t\t\t/* Is a message buffer but not statically allocated. */\n\t\t\tucFlags = sbFLAGS_IS_MESSAGE_BUFFER;\n\t\t\tconfigASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Not a message buffer and not statically allocated. */\n\t\t\tucFlags = 0;\n\t\t\tconfigASSERT( xBufferSizeBytes > 0 );\n\t\t}\n\t\tconfigASSERT( xTriggerLevelBytes <= xBufferSizeBytes );\n\n\t\t/* A trigger level of 0 would cause a waiting task to unblock even when\n\t\tthe buffer was empty. */\n\t\tif( xTriggerLevelBytes == ( size_t ) 0 )\n\t\t{\n\t\t\txTriggerLevelBytes = ( size_t ) 1;\n\t\t}\n\n\t\t/* A stream buffer requires a StreamBuffer_t structure and a buffer.\n\t\tBoth are allocated in a single call to pvPortMalloc().  The\n\t\tStreamBuffer_t structure is placed at the start of the allocated memory\n\t\tand the buffer follows immediately after.  The requested size is\n\t\tincremented so the free space is returned as the user would expect -\n\t\tthis is a quirk of the implementation that means otherwise the free\n\t\tspace would be reported as one byte smaller than would be logically\n\t\texpected. */\n\t\txBufferSizeBytes++;\n\t\tpucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */\n\n\t\tif( pucAllocatedMemory != NULL )\n\t\t{\n\t\t\tprvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */\n\t\t\t\t\t\t\t\t\t\t   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */\n\t\t\t\t\t\t\t\t\t\t   xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t   xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t   ucFlags );\n\n\t\t\ttraceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );\n\t\t}\n\n\t\treturn ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */\n\t}\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tStreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t   size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t   BaseType_t xIsMessageBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t   uint8_t * const pucStreamBufferStorageArea,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t   StaticStreamBuffer_t * const pxStaticStreamBuffer )\n\t{\n\tStreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */\n\tStreamBufferHandle_t xReturn;\n\tuint8_t ucFlags;\n\n\t\tconfigASSERT( pucStreamBufferStorageArea );\n\t\tconfigASSERT( pxStaticStreamBuffer );\n\t\tconfigASSERT( xTriggerLevelBytes <= xBufferSizeBytes );\n\n\t\t/* A trigger level of 0 would cause a waiting task to unblock even when\n\t\tthe buffer was empty. */\n\t\tif( xTriggerLevelBytes == ( size_t ) 0 )\n\t\t{\n\t\t\txTriggerLevelBytes = ( size_t ) 1;\n\t\t}\n\n\t\tif( xIsMessageBuffer != pdFALSE )\n\t\t{\n\t\t\t/* Statically allocated message buffer. */\n\t\t\tucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Statically allocated stream buffer. */\n\t\t\tucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;\n\t\t}\n\n\t\t/* In case the stream buffer is going to be used as a message buffer\n\t\t(that is, it will hold discrete messages with a little meta data that\n\t\tsays how big the next message is) check the buffer will be large enough\n\t\tto hold at least one message. */\n\t\tconfigASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticStreamBuffer_t equals the size of the real\n\t\t\tmessage buffer structure. */\n\t\t\tvolatile size_t xSize = sizeof( StaticStreamBuffer_t );\n\t\t\tconfigASSERT( xSize == sizeof( StreamBuffer_t ) );\n\t\t} /*lint !e529 xSize is referenced is configASSERT() is defined. */\n\t\t#endif /* configASSERT_DEFINED */\n\n\t\tif( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )\n\t\t{\n\t\t\tprvInitialiseNewStreamBuffer( pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\t  pucStreamBufferStorageArea,\n\t\t\t\t\t\t\t\t\t\t  xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t  xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t  ucFlags );\n\n\t\t\t/* Remember this was statically allocated in case it is ever deleted\n\t\t\tagain. */\n\t\t\tpxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;\n\n\t\t\ttraceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );\n\n\t\t\txReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = NULL;\n\t\t\ttraceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\nvoid vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )\n{\nStreamBuffer_t * pxStreamBuffer = xStreamBuffer;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\ttraceSTREAM_BUFFER_DELETE( xStreamBuffer );\n\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )\n\t{\n\t\t#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t\t{\n\t\t\t/* Both the structure and the buffer were allocated using a single call\n\t\t\tto pvPortMalloc(), hence only one call to vPortFree() is required. */\n\t\t\tvPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */\n\t\t}\n\t\t#else\n\t\t{\n\t\t\t/* Should not be possible to get here, ucFlags must be corrupt.\n\t\t\tForce an assert. */\n\t\t\tconfigASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );\n\t\t}\n\t\t#endif\n\t}\n\telse\n\t{\n\t\t/* The structure and buffer were not allocated dynamically and cannot be\n\t\tfreed - just scrub the structure so future use will assert. */\n\t\t( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn = pdFAIL;\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\tUBaseType_t uxStreamBufferNumber;\n#endif\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t{\n\t\t/* Store the stream buffer number so it can be restored after the\n\t\treset. */\n\t\tuxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;\n\t}\n\t#endif\n\n\t/* Can only reset a message buffer if there are no tasks blocked on it. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( pxStreamBuffer->xTaskWaitingToReceive == NULL )\n\t\t{\n\t\t\tif( pxStreamBuffer->xTaskWaitingToSend == NULL )\n\t\t\t{\n\t\t\t\tprvInitialiseNewStreamBuffer( pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\t\t  pxStreamBuffer->pucBuffer,\n\t\t\t\t\t\t\t\t\t\t\t  pxStreamBuffer->xLength,\n\t\t\t\t\t\t\t\t\t\t\t  pxStreamBuffer->xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t\t  pxStreamBuffer->ucFlags );\n\t\t\t\txReturn = pdPASS;\n\n\t\t\t\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\t\t\t{\n\t\t\t\t\tpxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\ttraceSTREAM_BUFFER_RESET( xStreamBuffer );\n\t\t\t}\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* It is not valid for the trigger level to be 0. */\n\tif( xTriggerLevel == ( size_t ) 0 )\n\t{\n\t\txTriggerLevel = ( size_t ) 1;\n\t}\n\n\t/* The trigger level is the number of bytes that must be in the stream\n\tbuffer before a task that is waiting for data is unblocked. */\n\tif( xTriggerLevel <= pxStreamBuffer->xLength )\n\t{\n\t\tpxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;\n\t\txReturn = pdPASS;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )\n{\nconst StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xSpace;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\txSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;\n\txSpace -= pxStreamBuffer->xHead;\n\txSpace -= ( size_t ) 1;\n\n\tif( xSpace >= pxStreamBuffer->xLength )\n\t{\n\t\txSpace -= pxStreamBuffer->xLength;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xSpace;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )\n{\nconst StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReturn;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\txReturn = prvBytesInBuffer( pxStreamBuffer );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t  const void *pvTxData,\n\t\t\t\t\t\t  size_t xDataLengthBytes,\n\t\t\t\t\t\t  TickType_t xTicksToWait )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReturn, xSpace = 0;\nsize_t xRequiredSpace = xDataLengthBytes;\nTimeOut_t xTimeOut;\n\n\tconfigASSERT( pvTxData );\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This send function is used to write to both message buffers and stream\n\tbuffers.  If this is a message buffer then the space needed must be\n\tincreased by the amount of bytes needed to store the length of the\n\tmessage. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\n\t\t/* Overflow? */\n\t\tconfigASSERT( xRequiredSpace > xDataLengthBytes );\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tif( xTicksToWait != ( TickType_t ) 0 )\n\t{\n\t\tvTaskSetTimeOutState( &xTimeOut );\n\n\t\tdo\n\t\t{\n\t\t\t/* Wait until the required number of bytes are free in the message\n\t\t\tbuffer. */\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\txSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n\n\t\t\t\tif( xSpace < xRequiredSpace )\n\t\t\t\t{\n\t\t\t\t\t/* Clear notification state as going to wait for space. */\n\t\t\t\t\t( void ) xTaskNotifyStateClear( NULL );\n\n\t\t\t\t\t/* Should only be one writer. */\n\t\t\t\t\tconfigASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );\n\t\t\t\t\tpxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\ttraceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );\n\t\t\t( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );\n\t\t\tpxStreamBuffer->xTaskWaitingToSend = NULL;\n\n\t\t} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tif( xSpace == ( size_t ) 0 )\n\t{\n\t\txSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\txReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );\n\n\tif( xReturn > ( size_t ) 0 )\n\t{\n\t\ttraceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );\n\n\t\t/* Was a task waiting for the data? */\n\t\tif( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )\n\t\t{\n\t\t\tsbSEND_COMPLETED( pxStreamBuffer );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t\ttraceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t\t const void *pvTxData,\n\t\t\t\t\t\t\t\t size_t xDataLengthBytes,\n\t\t\t\t\t\t\t\t BaseType_t * const pxHigherPriorityTaskWoken )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReturn, xSpace;\nsize_t xRequiredSpace = xDataLengthBytes;\n\n\tconfigASSERT( pvTxData );\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This send function is used to write to both message buffers and stream\n\tbuffers.  If this is a message buffer then the space needed must be\n\tincreased by the amount of bytes needed to store the length of the\n\tmessage. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\txSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n\txReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );\n\n\tif( xReturn > ( size_t ) 0 )\n\t{\n\t\t/* Was a task waiting for the data? */\n\t\tif( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )\n\t\t{\n\t\t\tsbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\ttraceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t   const void * pvTxData,\n\t\t\t\t\t\t\t\t\t   size_t xDataLengthBytes,\n\t\t\t\t\t\t\t\t\t   size_t xSpace,\n\t\t\t\t\t\t\t\t\t   size_t xRequiredSpace )\n{\n\tBaseType_t xShouldWrite;\n\tsize_t xReturn;\n\n\tif( xSpace == ( size_t ) 0 )\n\t{\n\t\t/* Doesn't matter if this is a stream buffer or a message buffer, there\n\t\tis no space to write. */\n\t\txShouldWrite = pdFALSE;\n\t}\n\telse if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )\n\t{\n\t\t/* This is a stream buffer, as opposed to a message buffer, so writing a\n\t\tstream of bytes rather than discrete messages.  Write as many bytes as\n\t\tpossible. */\n\t\txShouldWrite = pdTRUE;\n\t\txDataLengthBytes = configMIN( xDataLengthBytes, xSpace );\n\t}\n\telse if( xSpace >= xRequiredSpace )\n\t{\n\t\t/* This is a message buffer, as opposed to a stream buffer, and there\n\t\tis enough space to write both the message length and the message itself\n\t\tinto the buffer.  Start by writing the length of the data, the data\n\t\titself will be written later in this function. */\n\t\txShouldWrite = pdTRUE;\n\t\t( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );\n\t}\n\telse\n\t{\n\t\t/* There is space available, but not enough space. */\n\t\txShouldWrite = pdFALSE;\n\t}\n\n\tif( xShouldWrite != pdFALSE )\n\t{\n\t\t/* Writes the data itself. */\n\t\txReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */\n\t}\n\telse\n\t{\n\t\txReturn = 0;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t void *pvRxData,\n\t\t\t\t\t\t\t size_t xBufferLengthBytes,\n\t\t\t\t\t\t\t TickType_t xTicksToWait )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;\n\n\tconfigASSERT( pvRxData );\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This receive function is used by both message buffers, which store\n\tdiscrete messages, and stream buffers, which store a continuous stream of\n\tbytes.  Discrete messages include an additional\n\tsbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the\n\tmessage. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\t}\n\telse\n\t{\n\t\txBytesToStoreMessageLength = 0;\n\t}\n\n\tif( xTicksToWait != ( TickType_t ) 0 )\n\t{\n\t\t/* Checking if there is data and clearing the notification state must be\n\t\tperformed atomically. */\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\n\t\t\t/* If this function was invoked by a message buffer read then\n\t\t\txBytesToStoreMessageLength holds the number of bytes used to hold\n\t\t\tthe length of the next discrete message.  If this function was\n\t\t\tinvoked by a stream buffer read then xBytesToStoreMessageLength will\n\t\t\tbe 0. */\n\t\t\tif( xBytesAvailable <= xBytesToStoreMessageLength )\n\t\t\t{\n\t\t\t\t/* Clear notification state as going to wait for data. */\n\t\t\t\t( void ) xTaskNotifyStateClear( NULL );\n\n\t\t\t\t/* Should only be one reader. */\n\t\t\t\tconfigASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );\n\t\t\t\tpxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\tif( xBytesAvailable <= xBytesToStoreMessageLength )\n\t\t{\n\t\t\t/* Wait for data to be available. */\n\t\t\ttraceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );\n\t\t\t( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );\n\t\t\tpxStreamBuffer->xTaskWaitingToReceive = NULL;\n\n\t\t\t/* Recheck the data available after blocking. */\n\t\t\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\t}\n\n\t/* Whether receiving a discrete message (where xBytesToStoreMessageLength\n\tholds the number of bytes used to store the message length) or a stream of\n\tbytes (where xBytesToStoreMessageLength is zero), the number of bytes\n\tavailable must be greater than xBytesToStoreMessageLength to be able to\n\tread bytes from the buffer. */\n\tif( xBytesAvailable > xBytesToStoreMessageLength )\n\t{\n\t\txReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );\n\n\t\t/* Was a task waiting for space in the buffer? */\n\t\tif( xReceivedLength != ( size_t ) 0 )\n\t\t{\n\t\t\ttraceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );\n\t\t\tsbRECEIVE_COMPLETED( pxStreamBuffer );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\ttraceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xReceivedLength;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReturn, xBytesAvailable, xOriginalTail;\nconfigMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* Ensure the stream buffer is being used as a message buffer. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\t\tif( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )\n\t\t{\n\t\t\t/* The number of bytes available is greater than the number of bytes\n\t\t\trequired to hold the length of the next message, so another message\n\t\t\tis available.  Return its length without removing the length bytes\n\t\t\tfrom the buffer.  A copy of the tail is stored so the buffer can be\n\t\t\treturned to its prior state as the message is not actually being\n\t\t\tremoved from the buffer. */\n\t\t\txOriginalTail = pxStreamBuffer->xTail;\n\t\t\t( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );\n\t\t\txReturn = ( size_t ) xTempReturn;\n\t\t\tpxStreamBuffer->xTail = xOriginalTail;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The minimum amount of bytes in a message buffer is\n\t\t\t( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is\n\t\t\tless than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid\n\t\t\tvalue is 0. */\n\t\t\tconfigASSERT( xBytesAvailable == 0 );\n\t\t\txReturn = 0;\n\t\t}\n\t}\n\telse\n\t{\n\t\txReturn = 0;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t\t\tvoid *pvRxData,\n\t\t\t\t\t\t\t\t\tsize_t xBufferLengthBytes,\n\t\t\t\t\t\t\t\t\tBaseType_t * const pxHigherPriorityTaskWoken )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;\n\n\tconfigASSERT( pvRxData );\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This receive function is used by both message buffers, which store\n\tdiscrete messages, and stream buffers, which store a continuous stream of\n\tbytes.  Discrete messages include an additional\n\tsbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the\n\tmessage. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\t}\n\telse\n\t{\n\t\txBytesToStoreMessageLength = 0;\n\t}\n\n\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\n\t/* Whether receiving a discrete message (where xBytesToStoreMessageLength\n\tholds the number of bytes used to store the message length) or a stream of\n\tbytes (where xBytesToStoreMessageLength is zero), the number of bytes\n\tavailable must be greater than xBytesToStoreMessageLength to be able to\n\tread bytes from the buffer. */\n\tif( xBytesAvailable > xBytesToStoreMessageLength )\n\t{\n\t\txReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );\n\n\t\t/* Was a task waiting for space in the buffer? */\n\t\tif( xReceivedLength != ( size_t ) 0 )\n\t\t{\n\t\t\tsbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\ttraceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );\n\n\treturn xReceivedLength;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\tvoid *pvRxData,\n\t\t\t\t\t\t\t\t\t\tsize_t xBufferLengthBytes,\n\t\t\t\t\t\t\t\t\t\tsize_t xBytesAvailable,\n\t\t\t\t\t\t\t\t\t\tsize_t xBytesToStoreMessageLength )\n{\nsize_t xOriginalTail, xReceivedLength, xNextMessageLength;\nconfigMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;\n\n\tif( xBytesToStoreMessageLength != ( size_t ) 0 )\n\t{\n\t\t/* A discrete message is being received.  First receive the length\n\t\tof the message.  A copy of the tail is stored so the buffer can be\n\t\treturned to its prior state if the length of the message is too\n\t\tlarge for the provided buffer. */\n\t\txOriginalTail = pxStreamBuffer->xTail;\n\t\t( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );\n\t\txNextMessageLength = ( size_t ) xTempNextMessageLength;\n\n\t\t/* Reduce the number of bytes available by the number of bytes just\n\t\tread out. */\n\t\txBytesAvailable -= xBytesToStoreMessageLength;\n\n\t\t/* Check there is enough space in the buffer provided by the\n\t\tuser. */\n\t\tif( xNextMessageLength > xBufferLengthBytes )\n\t\t{\n\t\t\t/* The user has provided insufficient space to read the message\n\t\t\tso return the buffer to its previous state (so the length of\n\t\t\tthe message is in the buffer again). */\n\t\t\tpxStreamBuffer->xTail = xOriginalTail;\n\t\t\txNextMessageLength = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* A stream of bytes is being received (as opposed to a discrete\n\t\tmessage), so read as many bytes as possible. */\n\t\txNextMessageLength = xBufferLengthBytes;\n\t}\n\n\t/* Read the actual data. */\n\txReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */\n\n\treturn xReceivedLength;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )\n{\nconst StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn;\nsize_t xTail;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* True if no bytes are available. */\n\txTail = pxStreamBuffer->xTail;\n\tif( pxStreamBuffer->xHead == xTail )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )\n{\nBaseType_t xReturn;\nsize_t xBytesToStoreMessageLength;\nconst StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This generic version of the receive function is used by both message\n\tbuffers, which store discrete messages, and stream buffers, which store a\n\tcontinuous stream of bytes.  Discrete messages include an additional\n\tsbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\t}\n\telse\n\t{\n\t\txBytesToStoreMessageLength = 0;\n\t}\n\n\t/* True if the available space equals zero. */\n\tif( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\tuxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tif( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )\n\t\t{\n\t\t\t( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,\n\t\t\t\t\t\t\t\t\t\t ( uint32_t ) 0,\n\t\t\t\t\t\t\t\t\t\t eNoAction,\n\t\t\t\t\t\t\t\t\t\t pxHigherPriorityTaskWoken );\n\t\t\t( pxStreamBuffer )->xTaskWaitingToReceive = NULL;\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\tuxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tif( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )\n\t\t{\n\t\t\t( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,\n\t\t\t\t\t\t\t\t\t\t ( uint32_t ) 0,\n\t\t\t\t\t\t\t\t\t\t eNoAction,\n\t\t\t\t\t\t\t\t\t\t pxHigherPriorityTaskWoken );\n\t\t\t( pxStreamBuffer )->xTaskWaitingToSend = NULL;\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )\n{\nsize_t xNextHead, xFirstLength;\n\n\tconfigASSERT( xCount > ( size_t ) 0 );\n\n\txNextHead = pxStreamBuffer->xHead;\n\n\t/* Calculate the number of bytes that can be added in the first write -\n\twhich may be less than the total number of bytes that need to be added if\n\tthe buffer will wrap back to the beginning. */\n\txFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );\n\n\t/* Write as many bytes as can be written in the first write. */\n\tconfigASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );\n\t( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\n\t/* If the number of bytes written was less than the number that could be\n\twritten in the first write... */\n\tif( xCount > xFirstLength )\n\t{\n\t\t/* ...then write the remaining bytes to the start of the buffer. */\n\t\tconfigASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );\n\t\t( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\txNextHead += xCount;\n\tif( xNextHead >= pxStreamBuffer->xLength )\n\t{\n\t\txNextHead -= pxStreamBuffer->xLength;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tpxStreamBuffer->xHead = xNextHead;\n\n\treturn xCount;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )\n{\nsize_t xCount, xFirstLength, xNextTail;\n\n\t/* Use the minimum of the wanted bytes and the available bytes. */\n\txCount = configMIN( xBytesAvailable, xMaxCount );\n\n\tif( xCount > ( size_t ) 0 )\n\t{\n\t\txNextTail = pxStreamBuffer->xTail;\n\n\t\t/* Calculate the number of bytes that can be read - which may be\n\t\tless than the number wanted if the data wraps around to the start of\n\t\tthe buffer. */\n\t\txFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );\n\n\t\t/* Obtain the number of bytes it is possible to obtain in the first\n\t\tread.  Asserts check bounds of read and write. */\n\t\tconfigASSERT( xFirstLength <= xMaxCount );\n\t\tconfigASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );\n\t\t( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\n\t\t/* If the total number of wanted bytes is greater than the number\n\t\tthat could be read in the first read... */\n\t\tif( xCount > xFirstLength )\n\t\t{\n\t\t\t/*...then read the remaining bytes from the start of the buffer. */\n\t\t\tconfigASSERT( xCount <= xMaxCount );\n\t\t\t( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* Move the tail pointer to effectively remove the data read from\n\t\tthe buffer. */\n\t\txNextTail += xCount;\n\n\t\tif( xNextTail >= pxStreamBuffer->xLength )\n\t\t{\n\t\t\txNextTail -= pxStreamBuffer->xLength;\n\t\t}\n\n\t\tpxStreamBuffer->xTail = xNextTail;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xCount;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )\n{\n/* Returns the distance between xTail and xHead. */\nsize_t xCount;\n\n\txCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;\n\txCount -= pxStreamBuffer->xTail;\n\tif ( xCount >= pxStreamBuffer->xLength )\n\t{\n\t\txCount -= pxStreamBuffer->xLength;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xCount;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\t  uint8_t * const pucBuffer,\n\t\t\t\t\t\t\t\t\t\t  size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t  size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t  uint8_t ucFlags )\n{\n\t/* Assert here is deliberately writing to the entire buffer to ensure it can\n\tbe written to without generating exceptions, and is setting the buffer to a\n\tknown value to assist in development/debugging. */\n\t#if( configASSERT_DEFINED == 1 )\n\t{\n\t\t/* The value written just has to be identifiable when looking at the\n\t\tmemory.  Don't use 0xA5 as that is the stack fill value and could\n\t\tresult in confusion as to what is actually being observed. */\n\t\tconst BaseType_t xWriteValue = 0x55;\n\t\tconfigASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );\n\t} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */\n\t#endif\n\n\t( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */\n\tpxStreamBuffer->pucBuffer = pucBuffer;\n\tpxStreamBuffer->xLength = xBufferSizeBytes;\n\tpxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;\n\tpxStreamBuffer->ucFlags = ucFlags;\n}\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )\n\t{\n\t\treturn xStreamBuffer->uxStreamBufferNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )\n\t{\n\t\txStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tuint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )\n\t{\n\t\treturn ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "examples/lib/FreeRTOS/tasks.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"timers.h\"\n#include \"stack_macros.h\"\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting\nfunctions but without including stdio.h here. */\n#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )\n\t/* At the bottom of this file are two optional functions that can be used\n\tto generate human readable text from the raw data generated by the\n\tuxTaskGetSystemState() function.  Note the formatting functions are provided\n\tfor convenience only, and are NOT considered part of the kernel. */\n\t#include <stdio.h>\n#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */\n\n#if( configUSE_PREEMPTION == 0 )\n\t/* If the cooperative scheduler is being used then a yield should not be\n\tperformed just because a higher priority task has been woken. */\n\t#define taskYIELD_IF_USING_PREEMPTION()\n#else\n\t#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()\n#endif\n\n/* Values that can be assigned to the ucNotifyState member of the TCB. */\n#define taskNOT_WAITING_NOTIFICATION\t( ( uint8_t ) 0 )\n#define taskWAITING_NOTIFICATION\t\t( ( uint8_t ) 1 )\n#define taskNOTIFICATION_RECEIVED\t\t( ( uint8_t ) 2 )\n\n/*\n * The value used to fill the stack of a task when the task is created.  This\n * is used purely for checking the high water mark for tasks.\n */\n#define tskSTACK_FILL_BYTE\t( 0xa5U )\n\n/* Bits used to recored how a task's stack and TCB were allocated. */\n#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB \t\t( ( uint8_t ) 0 )\n#define tskSTATICALLY_ALLOCATED_STACK_ONLY \t\t\t( ( uint8_t ) 1 )\n#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB\t\t( ( uint8_t ) 2 )\n\n/* If any of the following are set then task stacks are filled with a known\nvalue so the high water mark can be determined.  If none of the following are\nset then don't fill the stack so there is no unnecessary dependency on memset. */\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n\t#define tskSET_NEW_STACKS_TO_KNOWN_VALUE\t1\n#else\n\t#define tskSET_NEW_STACKS_TO_KNOWN_VALUE\t0\n#endif\n\n/*\n * Macros used by vListTask to indicate which state a task is in.\n */\n#define tskRUNNING_CHAR\t\t( 'X' )\n#define tskBLOCKED_CHAR\t\t( 'B' )\n#define tskREADY_CHAR\t\t( 'R' )\n#define tskDELETED_CHAR\t\t( 'D' )\n#define tskSUSPENDED_CHAR\t( 'S' )\n\n/*\n * Some kernel aware debuggers require the data the debugger needs access to be\n * global, rather than file scope.\n */\n#ifdef portREMOVE_STATIC_QUALIFIER\n\t#define static\n#endif\n\n/* The name allocated to the Idle task.  This can be overridden by defining\nconfigIDLE_TASK_NAME in FreeRTOSConfig.h. */\n#ifndef configIDLE_TASK_NAME\n\t#define configIDLE_TASK_NAME \"IDLE\"\n#endif\n\n#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )\n\n\t/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is\n\tperformed in a generic way that is not optimised to any particular\n\tmicrocontroller architecture. */\n\n\t/* uxTopReadyPriority holds the priority of the highest priority ready\n\tstate task. */\n\t#define taskRECORD_READY_PRIORITY( uxPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( uxPriority ) > uxTopReadyPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tuxTopReadyPriority = ( uxPriority );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t} /* taskRECORD_READY_PRIORITY */\n\n\t/*-----------------------------------------------------------*/\n\n\t#define taskSELECT_HIGHEST_PRIORITY_TASK()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tUBaseType_t uxTopPriority = uxTopReadyPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Find the highest priority queue that contains ready tasks. */\t\t\t\t\t\t\t\t\\\n\t\twhile( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tconfigASSERT( uxTopPriority );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t--uxTopPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of\t\t\t\t\t\t\\\n\t\tthe\tsame priority get an equal share of the processor time. */\t\t\t\t\t\t\t\t\t\\\n\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );\t\t\t\\\n\t\tuxTopReadyPriority = uxTopPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t} /* taskSELECT_HIGHEST_PRIORITY_TASK */\n\n\t/*-----------------------------------------------------------*/\n\n\t/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as\n\tthey are only required when a port optimised method of task selection is\n\tbeing used. */\n\t#define taskRESET_READY_PRIORITY( uxPriority )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )\n\n#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n\t/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is\n\tperformed in a way that is tailored to the particular microcontroller\n\tarchitecture being used. */\n\n\t/* A port optimised version is provided.  Call the port defined macros. */\n\t#define taskRECORD_READY_PRIORITY( uxPriority )\tportRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define taskSELECT_HIGHEST_PRIORITY_TASK()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tUBaseType_t uxTopPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Find the highest priority list that contains ready tasks. */\t\t\t\t\t\t\t\t\\\n\t\tportGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );\t\t\t\t\t\t\t\t\\\n\t\tconfigASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );\t\t\\\n\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );\t\t\\\n\t} /* taskSELECT_HIGHEST_PRIORITY_TASK() */\n\n\t/*-----------------------------------------------------------*/\n\n\t/* A port optimised version is provided, call it only if the TCB being reset\n\tis being referenced from a ready list.  If it is referenced from a delayed\n\tor suspended list then it won't be in a ready list. */\n\t#define taskRESET_READY_PRIORITY( uxPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tportRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick\ncount overflows. */\n#define taskSWITCH_DELAYED_LISTS()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tList_t *pxTemp;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* The delayed tasks list should be empty when the lists are switched. */\t\t\t\t\t\t\\\n\tconfigASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tpxTemp = pxDelayedTaskList;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tpxDelayedTaskList = pxOverflowDelayedTaskList;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tpxOverflowDelayedTaskList = pxTemp;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\txNumOfOverflows++;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tprvResetNextTaskUnblockTime();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/*-----------------------------------------------------------*/\n\n/*\n * Place the task represented by pxTCB into the appropriate ready list for\n * the task.  It is inserted at the end of the list.\n */\n#define prvAddTaskToReadyList( pxTCB )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\ttraceMOVED_TASK_TO_READY_STATE( pxTCB );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\ttaskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tvListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \\\n\ttracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )\n/*-----------------------------------------------------------*/\n\n/*\n * Several functions take an TaskHandle_t parameter that can optionally be NULL,\n * where NULL is used to indicate that the handle of the currently executing\n * task should be used in place of the parameter.  This macro simply checks to\n * see if the parameter is NULL and returns a pointer to the appropriate TCB.\n */\n#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )\n\n/* The item value of the event list item is normally used to hold the priority\nof the task to which it belongs (coded to allow it to be held in reverse\npriority order).  However, it is occasionally borrowed for other purposes.  It\nis important its value is not updated due to a task priority change while it is\nbeing used for another purpose.  The following bit definition is used to inform\nthe scheduler that the value should not be changed - in which case it is the\nresponsibility of whichever module is using the value to ensure it gets set back\nto its original value when it is released. */\n#if( configUSE_16_BIT_TICKS == 1 )\n\t#define taskEVENT_LIST_ITEM_VALUE_IN_USE\t0x8000U\n#else\n\t#define taskEVENT_LIST_ITEM_VALUE_IN_USE\t0x80000000UL\n#endif\n\n/*\n * Task control block.  A task control block (TCB) is allocated for each task,\n * and stores task state information, including a pointer to the task's context\n * (the task's run time environment, including register values)\n */\ntypedef struct tskTaskControlBlock \t\t\t/* The old naming convention is used to prevent breaking kernel aware debuggers. */\n{\n\tvolatile StackType_t\t*pxTopOfStack;\t/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */\n\n\t#if ( portUSING_MPU_WRAPPERS == 1 )\n\t\txMPU_SETTINGS\txMPUSettings;\t\t/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */\n\t#endif\n\n\tListItem_t\t\t\txStateListItem;\t/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */\n\tListItem_t\t\t\txEventListItem;\t\t/*< Used to reference a task from an event list. */\n\tUBaseType_t\t\t\tuxPriority;\t\t\t/*< The priority of the task.  0 is the lowest priority. */\n\tStackType_t\t\t\t*pxStack;\t\t\t/*< Points to the start of the stack. */\n\tchar\t\t\t\tpcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n\t#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )\n\t\tStackType_t\t\t*pxEndOfStack;\t\t/*< Points to the highest valid address for the stack. */\n\t#endif\n\n\t#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\t\tUBaseType_t\t\tuxCriticalNesting;\t/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */\n\t#endif\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t\t\tuxTCBNumber;\t\t/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */\n\t\tUBaseType_t\t\tuxTaskNumber;\t\t/*< Stores a number specifically for use by third party trace code. */\n\t#endif\n\n\t#if ( configUSE_MUTEXES == 1 )\n\t\tUBaseType_t\t\tuxBasePriority;\t\t/*< The priority last assigned to the task - used by the priority inheritance mechanism. */\n\t\tUBaseType_t\t\tuxMutexesHeld;\n\t#endif\n\n\t#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\t\tTaskHookFunction_t pxTaskTag;\n\t#endif\n\n\t#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n\t\tvoid\t\t\t*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];\n\t#endif\n\n\t#if( configGENERATE_RUN_TIME_STATS == 1 )\n\t\tuint32_t\t\tulRunTimeCounter;\t/*< Stores the amount of time the task has spent in the Running state. */\n\t#endif\n\n\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\t/* Allocate a Newlib reent structure that is specific to this task.\n\t\tNote Newlib support has been included by popular demand, but is not\n\t\tused by the FreeRTOS maintainers themselves.  FreeRTOS is not\n\t\tresponsible for resulting newlib operation.  User must be familiar with\n\t\tnewlib and must provide system-wide implementations of the necessary\n\t\tstubs. Be warned that (at the time of writing) the current newlib design\n\t\timplements a system-wide malloc() that must be provided with locks. */\n\t\tstruct\t_reent xNewLib_reent;\n\t#endif\n\n\t#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\tvolatile uint32_t ulNotifiedValue;\n\t\tvolatile uint8_t ucNotifyState;\n\t#endif\n\n\t/* See the comments in FreeRTOS.h with the definition of\n\ttskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */\n\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n\t\tuint8_t\tucStaticallyAllocated; \t\t/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */\n\t#endif\n\n\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t\tuint8_t ucDelayAborted;\n\t#endif\n\n\t#if( configUSE_POSIX_ERRNO == 1 )\n\t\tint iTaskErrno;\n\t#endif\n\n} tskTCB;\n\n/* The old tskTCB name is maintained above then typedefed to the new TCB_t name\nbelow to enable the use of older kernel aware debuggers. */\ntypedef tskTCB TCB_t;\n\n/*lint -save -e956 A manual analysis and inspection has been used to determine\nwhich static variables must be declared volatile. */\nPRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;\n\n/* Lists for ready and blocked tasks. --------------------\nxDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but\ndoing so breaks some kernel aware debuggers and debuggers that rely on removing\nthe static qualifier. */\nPRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */\nPRIVILEGED_DATA static List_t xDelayedTaskList1;\t\t\t\t\t\t/*< Delayed tasks. */\nPRIVILEGED_DATA static List_t xDelayedTaskList2;\t\t\t\t\t\t/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */\nPRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;\t\t\t\t/*< Points to the delayed task list currently being used. */\nPRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;\t\t/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */\nPRIVILEGED_DATA static List_t xPendingReadyList;\t\t\t\t\t\t/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */\n\n#if( INCLUDE_vTaskDelete == 1 )\n\n\tPRIVILEGED_DATA static List_t xTasksWaitingTermination;\t\t\t\t/*< Tasks that have been deleted - but their memory not yet freed. */\n\tPRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;\n\n#endif\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tPRIVILEGED_DATA static List_t xSuspendedTaskList;\t\t\t\t\t/*< Tasks that are currently suspended. */\n\n#endif\n\n/* Global POSIX errno. Its value is changed upon context switching to match\nthe errno of the currently running task. */\n#if ( configUSE_POSIX_ERRNO == 1 )\n\tint FreeRTOS_errno = 0;\n#endif\n\n/* Other file private variables. --------------------------------*/\nPRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks \t= ( UBaseType_t ) 0U;\nPRIVILEGED_DATA static volatile TickType_t xTickCount \t\t\t\t= ( TickType_t ) configINITIAL_TICK_COUNT;\nPRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority \t\t= tskIDLE_PRIORITY;\nPRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning \t\t= pdFALSE;\nPRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks \t\t\t= ( UBaseType_t ) 0U;\nPRIVILEGED_DATA static volatile BaseType_t xYieldPending \t\t\t= pdFALSE;\nPRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows \t\t\t= ( BaseType_t ) 0;\nPRIVILEGED_DATA static UBaseType_t uxTaskNumber \t\t\t\t\t= ( UBaseType_t ) 0U;\nPRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime\t\t= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */\nPRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle\t\t\t\t\t= NULL;\t\t\t/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */\n\n/* Context switches are held pending while the scheduler is suspended.  Also,\ninterrupts must not manipulate the xStateListItem of a TCB, or any of the\nlists the xStateListItem can be referenced from, if the scheduler is suspended.\nIf an interrupt needs to unblock a task while the scheduler is suspended then it\nmoves the task's event list item into the xPendingReadyList, ready for the\nkernel to move the task from the pending ready list into the real ready list\nwhen the scheduler is unsuspended.  The pending ready list itself can only be\naccessed from a critical section. */\nPRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended\t= ( UBaseType_t ) pdFALSE;\n\n#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\n\t/* Do not move these variables to function scope as doing so prevents the\n\tcode working with debuggers that need to remove the static qualifier. */\n\tPRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;\t/*< Holds the value of a timer/counter the last time a task was switched in. */\n\tPRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;\t\t/*< Holds the total amount of execution time as defined by the run time counter clock. */\n\n#endif\n\n/*lint -restore */\n\n/*-----------------------------------------------------------*/\n\n/* Callback function prototypes. --------------------------*/\n#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )\n\n\textern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );\n\n#endif\n\n#if( configUSE_TICK_HOOK > 0 )\n\n\textern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */\n\n#endif\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\textern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */\n\n#endif\n\n/* File private functions. --------------------------------*/\n\n/**\n * Utility task that simply returns pdTRUE if the task referenced by xTask is\n * currently in the Suspended state, or pdFALSE if the task referenced by xTask\n * is in any other state.\n */\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tstatic BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n#endif /* INCLUDE_vTaskSuspend */\n\n/*\n * Utility to ready all the lists used by the scheduler.  This is called\n * automatically upon the creation of the first task.\n */\nstatic void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The idle task, which as all tasks is implemented as a never ending loop.\n * The idle task is automatically created and added to the ready lists upon\n * creation of the first user task.\n *\n * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific\n * language extensions.  The equivalent prototype for this function is:\n *\n * void prvIdleTask( void *pvParameters );\n *\n */\nstatic portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );\n\n/*\n * Utility to free all memory allocated by the scheduler to hold a TCB,\n * including the stack pointed to by the TCB.\n *\n * This does not free memory allocated by the task itself (i.e. memory\n * allocated by calls to pvPortMalloc from within the tasks application code).\n */\n#if ( INCLUDE_vTaskDelete == 1 )\n\n\tstatic void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Used only by the idle task.  This checks to see if anything has been placed\n * in the list of tasks waiting to be deleted.  If so the task is cleaned up\n * and its TCB deleted.\n */\nstatic void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The currently executing task is entering the Blocked state.  Add the task to\n * either the current or the overflow delayed task list.\n */\nstatic void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;\n\n/*\n * Fills an TaskStatus_t structure with information on each task that is\n * referenced from the pxList list (which may be a ready list, a delayed list,\n * a suspended list, etc.).\n *\n * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM\n * NORMAL APPLICATION CODE.\n */\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tstatic UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Searches pxList for a task with name pcNameToQuery - returning a handle to\n * the task if it is found, or NULL if the task is not found.\n */\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n\tstatic TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * When a task is created, the stack of the task is filled with a known value.\n * This function determines the 'high water mark' of the task stack by\n * determining how much of the stack remains at the original preset value.\n */\n#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n\n\tstatic configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Return the amount of time, in ticks, that will pass before the kernel will\n * next move a task from the Blocked state to the Running state.\n *\n * This conditional compilation should use inequality to 0, not equality to 1.\n * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user\n * defined low power mode implementations require configUSE_TICKLESS_IDLE to be\n * set to a value other than 1.\n */\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n\tstatic TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Set xNextTaskUnblockTime to the time at which the next Blocked state task\n * will exit the Blocked state.\n */\nstatic void prvResetNextTaskUnblockTime( void );\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\n\n\t/*\n\t * Helper function used to pad task names with spaces when printing out\n\t * human readable tables of task information.\n\t */\n\tstatic char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Called after a Task_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\nstatic void prvInitialiseNewTask( \tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\t\t\tconst char * const pcName, \t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t\tTaskHandle_t * const pxCreatedTask,\n\t\t\t\t\t\t\t\t\tTCB_t *pxNewTCB,\n\t\t\t\t\t\t\t\t\tconst MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;\n\n/*\n * Called after a new task has been created and initialised to place the task\n * under the control of the scheduler.\n */\nstatic void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;\n\n/*\n * freertos_tasks_c_additions_init() should only be called if the user definable\n * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro\n * called by the function.\n */\n#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n\n\tstatic void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tTaskHandle_t xTaskCreateStatic(\tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\t\t\tconst char * const pcName,\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t\tStackType_t * const puxStackBuffer,\n\t\t\t\t\t\t\t\t\tStaticTask_t * const pxTaskBuffer )\n\t{\n\tTCB_t *pxNewTCB;\n\tTaskHandle_t xReturn;\n\n\t\tconfigASSERT( puxStackBuffer != NULL );\n\t\tconfigASSERT( pxTaskBuffer != NULL );\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticTask_t equals the size of the real task\n\t\t\tstructure. */\n\t\t\tvolatile size_t xSize = sizeof( StaticTask_t );\n\t\t\tconfigASSERT( xSize == sizeof( TCB_t ) );\n\t\t\t( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */\n\t\t}\n\t\t#endif /* configASSERT_DEFINED */\n\n\n\t\tif( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )\n\t\t{\n\t\t\t/* The memory used for the task's TCB and stack are passed into this\n\t\t\tfunction - use them. */\n\t\t\tpxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */\n\t\t\tpxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;\n\n\t\t\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n\t\t\t{\n\t\t\t\t/* Tasks can be created statically or dynamically, so note this\n\t\t\t\ttask was created statically in case the task is later deleted. */\n\t\t\t\tpxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;\n\t\t\t}\n\t\t\t#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n\t\t\tprvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );\n\t\t\tprvAddNewTaskToReadyList( pxNewTCB );\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = NULL;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* SUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n\tBaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )\n\t{\n\tTCB_t *pxNewTCB;\n\tBaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\n\t\tconfigASSERT( pxTaskDefinition->puxStackBuffer != NULL );\n\t\tconfigASSERT( pxTaskDefinition->pxTaskBuffer != NULL );\n\n\t\tif( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )\n\t\t{\n\t\t\t/* Allocate space for the TCB.  Where the memory comes from depends\n\t\t\ton the implementation of the port malloc function and whether or\n\t\t\tnot static allocation is being used. */\n\t\t\tpxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;\n\n\t\t\t/* Store the stack location in the TCB. */\n\t\t\tpxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;\n\n\t\t\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n\t\t\t{\n\t\t\t\t/* Tasks can be created statically or dynamically, so note this\n\t\t\t\ttask was created statically in case the task is later deleted. */\n\t\t\t\tpxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;\n\t\t\t}\n\t\t\t#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n\t\t\tprvInitialiseNewTask(\tpxTaskDefinition->pvTaskCode,\n\t\t\t\t\t\t\t\t\tpxTaskDefinition->pcName,\n\t\t\t\t\t\t\t\t\t( uint32_t ) pxTaskDefinition->usStackDepth,\n\t\t\t\t\t\t\t\t\tpxTaskDefinition->pvParameters,\n\t\t\t\t\t\t\t\t\tpxTaskDefinition->uxPriority,\n\t\t\t\t\t\t\t\t\tpxCreatedTask, pxNewTCB,\n\t\t\t\t\t\t\t\t\tpxTaskDefinition->xRegions );\n\n\t\t\tprvAddNewTaskToReadyList( pxNewTCB );\n\t\t\txReturn = pdPASS;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\n#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tBaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )\n\t{\n\tTCB_t *pxNewTCB;\n\tBaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\n\t\tconfigASSERT( pxTaskDefinition->puxStackBuffer );\n\n\t\tif( pxTaskDefinition->puxStackBuffer != NULL )\n\t\t{\n\t\t\t/* Allocate space for the TCB.  Where the memory comes from depends\n\t\t\ton the implementation of the port malloc function and whether or\n\t\t\tnot static allocation is being used. */\n\t\t\tpxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\n\n\t\t\tif( pxNewTCB != NULL )\n\t\t\t{\n\t\t\t\t/* Store the stack location in the TCB. */\n\t\t\t\tpxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;\n\n\t\t\t\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n\t\t\t\t{\n\t\t\t\t\t/* Tasks can be created statically or dynamically, so note\n\t\t\t\t\tthis task had a statically allocated stack in case it is\n\t\t\t\t\tlater deleted.  The TCB was allocated dynamically. */\n\t\t\t\t\tpxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;\n\t\t\t\t}\n\t\t\t\t#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n\t\t\t\tprvInitialiseNewTask(\tpxTaskDefinition->pvTaskCode,\n\t\t\t\t\t\t\t\t\t\tpxTaskDefinition->pcName,\n\t\t\t\t\t\t\t\t\t\t( uint32_t ) pxTaskDefinition->usStackDepth,\n\t\t\t\t\t\t\t\t\t\tpxTaskDefinition->pvParameters,\n\t\t\t\t\t\t\t\t\t\tpxTaskDefinition->uxPriority,\n\t\t\t\t\t\t\t\t\t\tpxCreatedTask, pxNewTCB,\n\t\t\t\t\t\t\t\t\t\tpxTaskDefinition->xRegions );\n\n\t\t\t\tprvAddNewTaskToReadyList( pxNewTCB );\n\t\t\t\txReturn = pdPASS;\n\t\t\t}\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* portUSING_MPU_WRAPPERS */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tBaseType_t xTaskCreate(\tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\tconst char * const pcName,\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\tconst configSTACK_DEPTH_TYPE usStackDepth,\n\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\tTaskHandle_t * const pxCreatedTask )\n\t{\n\tTCB_t *pxNewTCB;\n\tBaseType_t xReturn;\n\n\t\t/* If the stack grows down then allocate the stack then the TCB so the stack\n\t\tdoes not grow into the TCB.  Likewise if the stack grows up then allocate\n\t\tthe TCB then the stack. */\n\t\t#if( portSTACK_GROWTH > 0 )\n\t\t{\n\t\t\t/* Allocate space for the TCB.  Where the memory comes from depends on\n\t\t\tthe implementation of the port malloc function and whether or not static\n\t\t\tallocation is being used. */\n\t\t\tpxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\n\n\t\t\tif( pxNewTCB != NULL )\n\t\t\t{\n\t\t\t\t/* Allocate space for the stack used by the task being created.\n\t\t\t\tThe base of the stack memory stored in the TCB so the task can\n\t\t\t\tbe deleted later if required. */\n\t\t\t\tpxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\t\t\t\tif( pxNewTCB->pxStack == NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Could not allocate the stack.  Delete the allocated TCB. */\n\t\t\t\t\tvPortFree( pxNewTCB );\n\t\t\t\t\tpxNewTCB = NULL;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t#else /* portSTACK_GROWTH */\n\t\t{\n\t\tStackType_t *pxStack;\n\n\t\t\t/* Allocate space for the stack used by the task being created. */\n\t\t\tpxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */\n\n\t\t\tif( pxStack != NULL )\n\t\t\t{\n\t\t\t\t/* Allocate space for the TCB. */\n\t\t\t\tpxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */\n\n\t\t\t\tif( pxNewTCB != NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Store the stack location in the TCB. */\n\t\t\t\t\tpxNewTCB->pxStack = pxStack;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The stack cannot be used as the TCB was not created.  Free\n\t\t\t\t\tit again. */\n\t\t\t\t\tvPortFree( pxStack );\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tpxNewTCB = NULL;\n\t\t\t}\n\t\t}\n\t\t#endif /* portSTACK_GROWTH */\n\n\t\tif( pxNewTCB != NULL )\n\t\t{\n\t\t\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */\n\t\t\t{\n\t\t\t\t/* Tasks can be created statically or dynamically, so note this\n\t\t\t\ttask was created dynamically in case it is later deleted. */\n\t\t\t\tpxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;\n\t\t\t}\n\t\t\t#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n\t\t\tprvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );\n\t\t\tprvAddNewTaskToReadyList( pxNewTCB );\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewTask( \tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\t\t\tconst char * const pcName,\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t\tTaskHandle_t * const pxCreatedTask,\n\t\t\t\t\t\t\t\t\tTCB_t *pxNewTCB,\n\t\t\t\t\t\t\t\t\tconst MemoryRegion_t * const xRegions )\n{\nStackType_t *pxTopOfStack;\nUBaseType_t x;\n\n\t#if( portUSING_MPU_WRAPPERS == 1 )\n\t\t/* Should the task be created in privileged mode? */\n\t\tBaseType_t xRunPrivileged;\n\t\tif( ( uxPriority & portPRIVILEGE_BIT ) != 0U )\n\t\t{\n\t\t\txRunPrivileged = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txRunPrivileged = pdFALSE;\n\t\t}\n\t\tuxPriority &= ~portPRIVILEGE_BIT;\n\t#endif /* portUSING_MPU_WRAPPERS == 1 */\n\n\t/* Avoid dependency on memset() if it is not required. */\n\t#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )\n\t{\n\t\t/* Fill the stack with a known value to assist debugging. */\n\t\t( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );\n\t}\n\t#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */\n\n\t/* Calculate the top of stack address.  This depends on whether the stack\n\tgrows from high memory to low (as per the 80x86) or vice versa.\n\tportSTACK_GROWTH is used to make the result positive or negative as required\n\tby the port. */\n\t#if( portSTACK_GROWTH < 0 )\n\t{\n\t\tpxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );\n\t\tpxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */\n\n\t\t/* Check the alignment of the calculated top of stack is correct. */\n\t\tconfigASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\n\n\t\t#if( configRECORD_STACK_HIGH_ADDRESS == 1 )\n\t\t{\n\t\t\t/* Also record the stack's high address, which may assist\n\t\t\tdebugging. */\n\t\t\tpxNewTCB->pxEndOfStack = pxTopOfStack;\n\t\t}\n\t\t#endif /* configRECORD_STACK_HIGH_ADDRESS */\n\t}\n\t#else /* portSTACK_GROWTH */\n\t{\n\t\tpxTopOfStack = pxNewTCB->pxStack;\n\n\t\t/* Check the alignment of the stack buffer is correct. */\n\t\tconfigASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\n\n\t\t/* The other extreme of the stack space is required if stack checking is\n\t\tperformed. */\n\t\tpxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );\n\t}\n\t#endif /* portSTACK_GROWTH */\n\n\t/* Store the task name in the TCB. */\n\tif( pcName != NULL )\n\t{\n\t\tfor( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\n\t\t{\n\t\t\tpxNewTCB->pcTaskName[ x ] = pcName[ x ];\n\n\t\t\t/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than\n\t\t\tconfigMAX_TASK_NAME_LEN characters just in case the memory after the\n\t\t\tstring is not accessible (extremely unlikely). */\n\t\t\tif( pcName[ x ] == ( char ) 0x00 )\n\t\t\t{\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\t/* Ensure the name string is terminated in the case that the string length\n\t\twas greater or equal to configMAX_TASK_NAME_LEN. */\n\t\tpxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\\0';\n\t}\n\telse\n\t{\n\t\t/* The task has not been given a name, so just ensure there is a NULL\n\t\tterminator when it is read out. */\n\t\tpxNewTCB->pcTaskName[ 0 ] = 0x00;\n\t}\n\n\t/* This is used as an array index so must ensure it's not too large.  First\n\tremove the privilege bit if one is present. */\n\tif( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\n\t{\n\t\tuxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tpxNewTCB->uxPriority = uxPriority;\n\t#if ( configUSE_MUTEXES == 1 )\n\t{\n\t\tpxNewTCB->uxBasePriority = uxPriority;\n\t\tpxNewTCB->uxMutexesHeld = 0;\n\t}\n\t#endif /* configUSE_MUTEXES */\n\n\tvListInitialiseItem( &( pxNewTCB->xStateListItem ) );\n\tvListInitialiseItem( &( pxNewTCB->xEventListItem ) );\n\n\t/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get\n\tback to\tthe containing TCB from a generic item in a list. */\n\tlistSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );\n\n\t/* Event lists are always in priority order. */\n\tlistSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\tlistSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );\n\n\t#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\t{\n\t\tpxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;\n\t}\n\t#endif /* portCRITICAL_NESTING_IN_TCB */\n\n\t#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\t{\n\t\tpxNewTCB->pxTaskTag = NULL;\n\t}\n\t#endif /* configUSE_APPLICATION_TASK_TAG */\n\n\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\t{\n\t\tpxNewTCB->ulRunTimeCounter = 0UL;\n\t}\n\t#endif /* configGENERATE_RUN_TIME_STATS */\n\n\t#if ( portUSING_MPU_WRAPPERS == 1 )\n\t{\n\t\tvPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );\n\t}\n\t#else\n\t{\n\t\t/* Avoid compiler warning about unreferenced parameter. */\n\t\t( void ) xRegions;\n\t}\n\t#endif\n\n\t#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\t{\n\t\tfor( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )\n\t\t{\n\t\t\tpxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;\n\t\t}\n\t}\n\t#endif\n\n\t#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\t{\n\t\tpxNewTCB->ulNotifiedValue = 0;\n\t\tpxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t}\n\t#endif\n\n\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t{\n\t\t/* Initialise this task's Newlib reent structure. */\n\t\t_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );\n\t}\n\t#endif\n\n\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t{\n\t\tpxNewTCB->ucDelayAborted = pdFALSE;\n\t}\n\t#endif\n\n\t/* Initialize the TCB stack to look as if the task was already running,\n\tbut had been interrupted by the scheduler.  The return address is set\n\tto the start of the task function. Once the stack has been initialised\n\tthe top of stack variable is updated. */\n\t#if( portUSING_MPU_WRAPPERS == 1 )\n\t{\n\t\t/* If the port has capability to detect stack overflow,\n\t\tpass the stack end address to the stack initialization\n\t\tfunction as well. */\n\t\t#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n\t\t{\n\t\t\t#if( portSTACK_GROWTH < 0 )\n\t\t\t{\n\t\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );\n\t\t\t}\n\t\t\t#else /* portSTACK_GROWTH */\n\t\t\t{\n\t\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );\n\t\t\t}\n\t\t\t#endif /* portSTACK_GROWTH */\n\t\t}\n\t\t#else /* portHAS_STACK_OVERFLOW_CHECKING */\n\t\t{\n\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\n\t\t}\n\t\t#endif /* portHAS_STACK_OVERFLOW_CHECKING */\n\t}\n\t#else /* portUSING_MPU_WRAPPERS */\n\t{\n\t\t/* If the port has capability to detect stack overflow,\n\t\tpass the stack end address to the stack initialization\n\t\tfunction as well. */\n\t\t#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n\t\t{\n\t\t\t#if( portSTACK_GROWTH < 0 )\n\t\t\t{\n\t\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );\n\t\t\t}\n\t\t\t#else /* portSTACK_GROWTH */\n\t\t\t{\n\t\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );\n\t\t\t}\n\t\t\t#endif /* portSTACK_GROWTH */\n\t\t}\n\t\t#else /* portHAS_STACK_OVERFLOW_CHECKING */\n\t\t{\n\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\n\t\t}\n\t\t#endif /* portHAS_STACK_OVERFLOW_CHECKING */\n\t}\n\t#endif /* portUSING_MPU_WRAPPERS */\n\n\tif( pxCreatedTask != NULL )\n\t{\n\t\t/* Pass the handle out in an anonymous way.  The handle can be used to\n\t\tchange the created task's priority, delete the created task, etc.*/\n\t\t*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )\n{\n\t/* Ensure interrupts don't access the task lists while the lists are being\n\tupdated. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tuxCurrentNumberOfTasks++;\n\t\tif( pxCurrentTCB == NULL )\n\t\t{\n\t\t\t/* There are no other tasks, or all the other tasks are in\n\t\t\tthe suspended state - make this the current task. */\n\t\t\tpxCurrentTCB = pxNewTCB;\n\n\t\t\tif( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )\n\t\t\t{\n\t\t\t\t/* This is the first task to be created so do the preliminary\n\t\t\t\tinitialisation required.  We will not recover if this call\n\t\t\t\tfails, but we will report the failure. */\n\t\t\t\tprvInitialiseTaskLists();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* If the scheduler is not already running, make this task the\n\t\t\tcurrent task if it is the highest priority task to be created\n\t\t\tso far. */\n\t\t\tif( xSchedulerRunning == pdFALSE )\n\t\t\t{\n\t\t\t\tif( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\tpxCurrentTCB = pxNewTCB;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\tuxTaskNumber++;\n\n\t\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\t{\n\t\t\t/* Add a counter into the TCB for tracing only. */\n\t\t\tpxNewTCB->uxTCBNumber = uxTaskNumber;\n\t\t}\n\t\t#endif /* configUSE_TRACE_FACILITY */\n\t\ttraceTASK_CREATE( pxNewTCB );\n\n\t\tprvAddTaskToReadyList( pxNewTCB );\n\n\t\tportSETUP_TCB( pxNewTCB );\n\t}\n\ttaskEXIT_CRITICAL();\n\n\tif( xSchedulerRunning != pdFALSE )\n\t{\n\t\t/* If the created task is of a higher priority than the current task\n\t\tthen it should run now. */\n\t\tif( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )\n\t\t{\n\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n}\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelete == 1 )\n\n\tvoid vTaskDelete( TaskHandle_t xTaskToDelete )\n\t{\n\tTCB_t *pxTCB;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* If null is passed in here then it is the calling task that is\n\t\t\tbeing deleted. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToDelete );\n\n\t\t\t/* Remove task from the ready list. */\n\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Is the task waiting on an event also? */\n\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t{\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Increment the uxTaskNumber also so kernel aware debuggers can\n\t\t\tdetect that the task lists need re-generating.  This is done before\n\t\t\tportPRE_TASK_DELETE_HOOK() as in the Windows port that macro will\n\t\t\tnot return. */\n\t\t\tuxTaskNumber++;\n\n\t\t\tif( pxTCB == pxCurrentTCB )\n\t\t\t{\n\t\t\t\t/* A task is deleting itself.  This cannot complete within the\n\t\t\t\ttask itself, as a context switch to another task is required.\n\t\t\t\tPlace the task in the termination list.  The idle task will\n\t\t\t\tcheck the termination list and free up any memory allocated by\n\t\t\t\tthe scheduler for the TCB and stack of the deleted task. */\n\t\t\t\tvListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );\n\n\t\t\t\t/* Increment the ucTasksDeleted variable so the idle task knows\n\t\t\t\tthere is a task that has been deleted and that it should therefore\n\t\t\t\tcheck the xTasksWaitingTermination list. */\n\t\t\t\t++uxDeletedTasksWaitingCleanUp;\n\n\t\t\t\t/* The pre-delete hook is primarily for the Windows simulator,\n\t\t\t\tin which Windows specific clean up operations are performed,\n\t\t\t\tafter which it is not possible to yield away from this task -\n\t\t\t\thence xYieldPending is used to latch that a context switch is\n\t\t\t\trequired. */\n\t\t\t\tportPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t--uxCurrentNumberOfTasks;\n\t\t\t\tprvDeleteTCB( pxTCB );\n\n\t\t\t\t/* Reset the next expected unblock time in case it referred to\n\t\t\t\tthe task that has just been deleted. */\n\t\t\t\tprvResetNextTaskUnblockTime();\n\t\t\t}\n\n\t\t\ttraceTASK_DELETE( pxTCB );\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Force a reschedule if it is the currently running task that has just\n\t\tbeen deleted. */\n\t\tif( xSchedulerRunning != pdFALSE )\n\t\t{\n\t\t\tif( pxTCB == pxCurrentTCB )\n\t\t\t{\n\t\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\n\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskDelete */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelayUntil == 1 )\n\n\tvoid vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )\n\t{\n\tTickType_t xTimeToWake;\n\tBaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;\n\n\t\tconfigASSERT( pxPreviousWakeTime );\n\t\tconfigASSERT( ( xTimeIncrement > 0U ) );\n\t\tconfigASSERT( uxSchedulerSuspended == 0 );\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* Minor optimisation.  The tick count cannot change in this\n\t\t\tblock. */\n\t\t\tconst TickType_t xConstTickCount = xTickCount;\n\n\t\t\t/* Generate the tick time at which the task wants to wake. */\n\t\t\txTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\n\n\t\t\tif( xConstTickCount < *pxPreviousWakeTime )\n\t\t\t{\n\t\t\t\t/* The tick count has overflowed since this function was\n\t\t\t\tlasted called.  In this case the only time we should ever\n\t\t\t\tactually delay is if the wake time has also\toverflowed,\n\t\t\t\tand the wake time is greater than the tick time.  When this\n\t\t\t\tis the case it is as if neither time had overflowed. */\n\t\t\t\tif( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )\n\t\t\t\t{\n\t\t\t\t\txShouldDelay = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The tick time has not overflowed.  In this case we will\n\t\t\t\tdelay if either the wake time has overflowed, and/or the\n\t\t\t\ttick time is less than the wake time. */\n\t\t\t\tif( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )\n\t\t\t\t{\n\t\t\t\t\txShouldDelay = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Update the wake time ready for the next call. */\n\t\t\t*pxPreviousWakeTime = xTimeToWake;\n\n\t\t\tif( xShouldDelay != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceTASK_DELAY_UNTIL( xTimeToWake );\n\n\t\t\t\t/* prvAddCurrentTaskToDelayedList() needs the block time, not\n\t\t\t\tthe time to wake, so subtract the current tick count. */\n\t\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\txAlreadyYielded = xTaskResumeAll();\n\n\t\t/* Force a reschedule if xTaskResumeAll has not already done so, we may\n\t\thave put ourselves to sleep. */\n\t\tif( xAlreadyYielded == pdFALSE )\n\t\t{\n\t\t\tportYIELD_WITHIN_API();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskDelayUntil */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelay == 1 )\n\n\tvoid vTaskDelay( const TickType_t xTicksToDelay )\n\t{\n\tBaseType_t xAlreadyYielded = pdFALSE;\n\n\t\t/* A delay time of zero just forces a reschedule. */\n\t\tif( xTicksToDelay > ( TickType_t ) 0U )\n\t\t{\n\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\n\t\t\tvTaskSuspendAll();\n\t\t\t{\n\t\t\t\ttraceTASK_DELAY();\n\n\t\t\t\t/* A task that is removed from the event list while the\n\t\t\t\tscheduler is suspended will not get placed in the ready\n\t\t\t\tlist or removed from the blocked list until the scheduler\n\t\t\t\tis resumed.\n\n\t\t\t\tThis task cannot be in an event list as it is the currently\n\t\t\t\texecuting task. */\n\t\t\t\tprvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );\n\t\t\t}\n\t\t\txAlreadyYielded = xTaskResumeAll();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* Force a reschedule if xTaskResumeAll has not already done so, we may\n\t\thave put ourselves to sleep. */\n\t\tif( xAlreadyYielded == pdFALSE )\n\t\t{\n\t\t\tportYIELD_WITHIN_API();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskDelay */\n/*-----------------------------------------------------------*/\n\n#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )\n\n\teTaskState eTaskGetState( TaskHandle_t xTask )\n\t{\n\teTaskState eReturn;\n\tList_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;\n\tconst TCB_t * const pxTCB = xTask;\n\n\t\tconfigASSERT( pxTCB );\n\n\t\tif( pxTCB == pxCurrentTCB )\n\t\t{\n\t\t\t/* The task calling this function is querying its own state. */\n\t\t\teReturn = eRunning;\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tpxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );\n\t\t\t\tpxDelayedList = pxDelayedTaskList;\n\t\t\t\tpxOverflowedDelayedList = pxOverflowDelayedTaskList;\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\tif( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )\n\t\t\t{\n\t\t\t\t/* The task being queried is referenced from one of the Blocked\n\t\t\t\tlists. */\n\t\t\t\teReturn = eBlocked;\n\t\t\t}\n\n\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\t\telse if( pxStateList == &xSuspendedTaskList )\n\t\t\t\t{\n\t\t\t\t\t/* The task being queried is referenced from the suspended\n\t\t\t\t\tlist.  Is it genuinely suspended or is it blocked\n\t\t\t\t\tindefinitely? */\n\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The task does not appear on the event list item of\n\t\t\t\t\t\t\tand of the RTOS objects, but could still be in the\n\t\t\t\t\t\t\tblocked state if it is waiting on its notification\n\t\t\t\t\t\t\trather than waiting on an object. */\n\t\t\t\t\t\t\tif( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\teReturn = eBlocked;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\teReturn = eSuspended;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#else\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\teReturn = eSuspended;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\teReturn = eBlocked;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t#endif\n\n\t\t\t#if ( INCLUDE_vTaskDelete == 1 )\n\t\t\t\telse if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )\n\t\t\t\t{\n\t\t\t\t\t/* The task being queried is referenced from the deleted\n\t\t\t\t\ttasks list, or it is not referenced from any lists at\n\t\t\t\t\tall. */\n\t\t\t\t\teReturn = eDeleted;\n\t\t\t\t}\n\t\t\t#endif\n\n\t\t\telse /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */\n\t\t\t{\n\t\t\t\t/* If the task is not in any other state, it must be in the\n\t\t\t\tReady (including pending ready) state. */\n\t\t\t\teReturn = eReady;\n\t\t\t}\n\t\t}\n\n\t\treturn eReturn;\n\t} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\n\n#endif /* INCLUDE_eTaskGetState */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\n\n\tUBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )\n\t{\n\tTCB_t const *pxTCB;\n\tUBaseType_t uxReturn;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* If null is passed in here then it is the priority of the task\n\t\t\tthat called uxTaskPriorityGet() that is being queried. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\t\t\tuxReturn = pxTCB->uxPriority;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* INCLUDE_uxTaskPriorityGet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\n\n\tUBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )\n\t{\n\tTCB_t const *pxTCB;\n\tUBaseType_t uxReturn, uxSavedInterruptState;\n\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\n\t\tInterrupts that are\tabove the maximum system call priority are keep\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\n\t\tis defined in FreeRTOSConfig.h then\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\n\t\tbeen assigned a priority above the configured maximum system call\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\n\t\tprovided on the following link:\n\t\thttps://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t\tuxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\t/* If null is passed in here then it is the priority of the calling\n\t\t\ttask that is being queried. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\t\t\tuxReturn = pxTCB->uxPriority;\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* INCLUDE_uxTaskPriorityGet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskPrioritySet == 1 )\n\n\tvoid vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )\n\t{\n\tTCB_t *pxTCB;\n\tUBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;\n\tBaseType_t xYieldRequired = pdFALSE;\n\n\t\tconfigASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );\n\n\t\t/* Ensure the new priority is valid. */\n\t\tif( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\n\t\t{\n\t\t\tuxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* If null is passed in here then it is the priority of the calling\n\t\t\ttask that is being changed. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t\ttraceTASK_PRIORITY_SET( pxTCB, uxNewPriority );\n\n\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t{\n\t\t\t\tuxCurrentBasePriority = pxTCB->uxBasePriority;\n\t\t\t}\n\t\t\t#else\n\t\t\t{\n\t\t\t\tuxCurrentBasePriority = pxTCB->uxPriority;\n\t\t\t}\n\t\t\t#endif\n\n\t\t\tif( uxCurrentBasePriority != uxNewPriority )\n\t\t\t{\n\t\t\t\t/* The priority change may have readied a task of higher\n\t\t\t\tpriority than the calling task. */\n\t\t\t\tif( uxNewPriority > uxCurrentBasePriority )\n\t\t\t\t{\n\t\t\t\t\tif( pxTCB != pxCurrentTCB )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The priority of a task other than the currently\n\t\t\t\t\t\trunning task is being raised.  Is the priority being\n\t\t\t\t\t\traised above that of the running task? */\n\t\t\t\t\t\tif( uxNewPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\txYieldRequired = pdTRUE;\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The priority of the running task is being raised,\n\t\t\t\t\t\tbut the running task must already be the highest\n\t\t\t\t\t\tpriority task able to run so no yield is required. */\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse if( pxTCB == pxCurrentTCB )\n\t\t\t\t{\n\t\t\t\t\t/* Setting the priority of the running task down means\n\t\t\t\t\tthere may now be another task of higher priority that\n\t\t\t\t\tis ready to execute. */\n\t\t\t\t\txYieldRequired = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Setting the priority of any other task down does not\n\t\t\t\t\trequire a yield as the running task must be above the\n\t\t\t\t\tnew priority of the task being modified. */\n\t\t\t\t}\n\n\t\t\t\t/* Remember the ready list the task might be referenced from\n\t\t\t\tbefore its uxPriority member is changed so the\n\t\t\t\ttaskRESET_READY_PRIORITY() macro can function correctly. */\n\t\t\t\tuxPriorityUsedOnEntry = pxTCB->uxPriority;\n\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* Only change the priority being used if the task is not\n\t\t\t\t\tcurrently using an inherited priority. */\n\t\t\t\t\tif( pxTCB->uxBasePriority == pxTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\tpxTCB->uxPriority = uxNewPriority;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* The base priority gets set whatever. */\n\t\t\t\t\tpxTCB->uxBasePriority = uxNewPriority;\n\t\t\t\t}\n\t\t\t\t#else\n\t\t\t\t{\n\t\t\t\t\tpxTCB->uxPriority = uxNewPriority;\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\t/* Only reset the event list item value if the value is not\n\t\t\t\tbeing used for anything else. */\n\t\t\t\tif( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n\t\t\t\t{\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t/* If the task is in the blocked or suspended list we need do\n\t\t\t\tnothing more than change its priority variable. However, if\n\t\t\t\tthe task is in a ready list it needs to be removed and placed\n\t\t\t\tin the list appropriate to its new priority. */\n\t\t\t\tif( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The task is currently in its ready list - remove before\n\t\t\t\t\tadding it to it's new ready list.  As we are in a critical\n\t\t\t\t\tsection we can do this even if the scheduler is suspended. */\n\t\t\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* It is known that the task is in its ready list so\n\t\t\t\t\t\tthere is no need to check again and the port level\n\t\t\t\t\t\treset macro can be called directly. */\n\t\t\t\t\t\tportRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\tif( xYieldRequired != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t/* Remove compiler warning about unused variables when the port\n\t\t\t\toptimised task selection is not being used. */\n\t\t\t\t( void ) uxPriorityUsedOnEntry;\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\t}\n\n#endif /* INCLUDE_vTaskPrioritySet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tvoid vTaskSuspend( TaskHandle_t xTaskToSuspend )\n\t{\n\tTCB_t *pxTCB;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* If null is passed in here then it is the running task that is\n\t\t\tbeing suspended. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToSuspend );\n\n\t\t\ttraceTASK_SUSPEND( pxTCB );\n\n\t\t\t/* Remove task from the ready/delayed list and place in the\n\t\t\tsuspended list. */\n\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Is the task waiting on an event also? */\n\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t{\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );\n\n\t\t\t#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\t\t{\n\t\t\t\tif( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t\t{\n\t\t\t\t\t/* The task was blocked to wait for a notification, but is\n\t\t\t\t\tnow suspended, so no notification was received. */\n\t\t\t\t\tpxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\tif( xSchedulerRunning != pdFALSE )\n\t\t{\n\t\t\t/* Reset the next expected unblock time in case it referred to the\n\t\t\ttask that is now in the Suspended state. */\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tprvResetNextTaskUnblockTime();\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\tif( pxTCB == pxCurrentTCB )\n\t\t{\n\t\t\tif( xSchedulerRunning != pdFALSE )\n\t\t\t{\n\t\t\t\t/* The current task has just been suspended. */\n\t\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\n\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The scheduler is not running, but the task that was pointed\n\t\t\t\tto by pxCurrentTCB has just been suspended and pxCurrentTCB\n\t\t\t\tmust be adjusted to point to a different task. */\n\t\t\t\tif( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */\n\t\t\t\t{\n\t\t\t\t\t/* No other tasks are ready, so set pxCurrentTCB back to\n\t\t\t\t\tNULL so when the next task is created pxCurrentTCB will\n\t\t\t\t\tbe set to point to it no matter what its relative priority\n\t\t\t\t\tis. */\n\t\t\t\t\tpxCurrentTCB = NULL;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tvTaskSwitchContext();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskSuspend */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tstatic BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )\n\t{\n\tBaseType_t xReturn = pdFALSE;\n\tconst TCB_t * const pxTCB = xTask;\n\n\t\t/* Accesses xPendingReadyList so must be called from a critical\n\t\tsection. */\n\n\t\t/* It does not make sense to check if the calling task is suspended. */\n\t\tconfigASSERT( xTask );\n\n\t\t/* Is the task being resumed actually in the suspended list? */\n\t\tif( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )\n\t\t{\n\t\t\t/* Has the task already been resumed from within an ISR? */\n\t\t\tif( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )\n\t\t\t{\n\t\t\t\t/* Is it in the suspended list because it is in the\tSuspended\n\t\t\t\tstate, or because is is blocked with no timeout? */\n\t\t\t\tif( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */\n\t\t\t\t{\n\t\t\t\t\txReturn = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xReturn;\n\t} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\n\n#endif /* INCLUDE_vTaskSuspend */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tvoid vTaskResume( TaskHandle_t xTaskToResume )\n\t{\n\tTCB_t * const pxTCB = xTaskToResume;\n\n\t\t/* It does not make sense to resume the calling task. */\n\t\tconfigASSERT( xTaskToResume );\n\n\t\t/* The parameter cannot be NULL as it is impossible to resume the\n\t\tcurrently executing task. */\n\t\tif( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tif( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\ttraceTASK_RESUME( pxTCB );\n\n\t\t\t\t\t/* The ready list can be accessed even if the scheduler is\n\t\t\t\t\tsuspended because this is inside a critical section. */\n\t\t\t\t\t( void ) uxListRemove(  &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t\t/* A higher priority task may have just been resumed. */\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* This yield may not cause the task just resumed to run,\n\t\t\t\t\t\tbut will leave the lists in the correct state for the\n\t\t\t\t\t\tnext yield. */\n\t\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskSuspend */\n\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\n\n\tBaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )\n\t{\n\tBaseType_t xYieldRequired = pdFALSE;\n\tTCB_t * const pxTCB = xTaskToResume;\n\tUBaseType_t uxSavedInterruptStatus;\n\n\t\tconfigASSERT( xTaskToResume );\n\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\n\t\tInterrupts that are\tabove the maximum system call priority are keep\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\n\t\tis defined in FreeRTOSConfig.h then\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\n\t\tbeen assigned a priority above the configured maximum system call\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\n\t\tprovided on the following link:\n\t\thttps://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\tif( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceTASK_RESUME_FROM_ISR( pxTCB );\n\n\t\t\t\t/* Check the ready lists can be accessed. */\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* Ready lists can be accessed so move the task from the\n\t\t\t\t\tsuspended list to the ready list directly. */\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\txYieldRequired = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The delayed or ready lists cannot be accessed so the task\n\t\t\t\t\tis held in the pending ready list until the scheduler is\n\t\t\t\t\tunsuspended. */\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\t\treturn xYieldRequired;\n\t}\n\n#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nvoid vTaskStartScheduler( void )\n{\nBaseType_t xReturn;\n\n\t/* Add the idle task at the lowest priority. */\n\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t{\n\t\tStaticTask_t *pxIdleTaskTCBBuffer = NULL;\n\t\tStackType_t *pxIdleTaskStackBuffer = NULL;\n\t\tuint32_t ulIdleTaskStackSize;\n\n\t\t/* The Idle task is created using user provided RAM - obtain the\n\t\taddress of the RAM then create the idle task. */\n\t\tvApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );\n\t\txIdleTaskHandle = xTaskCreateStatic(\tprvIdleTask,\n\t\t\t\t\t\t\t\t\t\t\t\tconfigIDLE_TASK_NAME,\n\t\t\t\t\t\t\t\t\t\t\t\tulIdleTaskStackSize,\n\t\t\t\t\t\t\t\t\t\t\t\t( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */\n\t\t\t\t\t\t\t\t\t\t\t\tportPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */\n\t\t\t\t\t\t\t\t\t\t\t\tpxIdleTaskStackBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\tpxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\n\n\t\tif( xIdleTaskHandle != NULL )\n\t\t{\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t}\n\t}\n\t#else\n\t{\n\t\t/* The Idle task is being created using dynamically allocated RAM. */\n\t\txReturn = xTaskCreate(\tprvIdleTask,\n\t\t\t\t\t\t\t\tconfigIDLE_TASK_NAME,\n\t\t\t\t\t\t\t\tconfigMINIMAL_STACK_SIZE,\n\t\t\t\t\t\t\t\t( void * ) NULL,\n\t\t\t\t\t\t\t\tportPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */\n\t\t\t\t\t\t\t\t&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\n\t}\n\t#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n\t#if ( configUSE_TIMERS == 1 )\n\t{\n\t\tif( xReturn == pdPASS )\n\t\t{\n\t\t\txReturn = xTimerCreateTimerTask();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\t#endif /* configUSE_TIMERS */\n\n\tif( xReturn == pdPASS )\n\t{\n\t\t/* freertos_tasks_c_additions_init() should only be called if the user\n\t\tdefinable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is\n\t\tthe only macro called by the function. */\n\t\t#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n\t\t{\n\t\t\tfreertos_tasks_c_additions_init();\n\t\t}\n\t\t#endif\n\n\t\t/* Interrupts are turned off here, to ensure a tick does not occur\n\t\tbefore or during the call to xPortStartScheduler().  The stacks of\n\t\tthe created tasks contain a status word with interrupts switched on\n\t\tso interrupts will automatically get re-enabled when the first task\n\t\tstarts to run. */\n\t\tportDISABLE_INTERRUPTS();\n\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\t{\n\t\t\t/* Switch Newlib's _impure_ptr variable to point to the _reent\n\t\t\tstructure specific to the task that will run first. */\n\t\t\t_impure_ptr = &( pxCurrentTCB->xNewLib_reent );\n\t\t}\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\n\n\t\txNextTaskUnblockTime = portMAX_DELAY;\n\t\txSchedulerRunning = pdTRUE;\n\t\txTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;\n\n\t\t/* If configGENERATE_RUN_TIME_STATS is defined then the following\n\t\tmacro must be defined to configure the timer/counter used to generate\n\t\tthe run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS\n\t\tis set to 0 and the following line fails to build then ensure you do not\n\t\thave portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your\n\t\tFreeRTOSConfig.h file. */\n\t\tportCONFIGURE_TIMER_FOR_RUN_TIME_STATS();\n\n\t\ttraceTASK_SWITCHED_IN();\n\n\t\t/* Setting up the timer tick is hardware specific and thus in the\n\t\tportable interface. */\n\t\tif( xPortStartScheduler() != pdFALSE )\n\t\t{\n\t\t\t/* Should not reach here as if the scheduler is running the\n\t\t\tfunction will not return. */\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Should only reach here if a task calls xTaskEndScheduler(). */\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* This line will only be reached if the kernel could not be started,\n\t\tbecause there was not enough FreeRTOS heap to create the idle task\n\t\tor the timer task. */\n\t\tconfigASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );\n\t}\n\n\t/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,\n\tmeaning xIdleTaskHandle is not used anywhere else. */\n\t( void ) xIdleTaskHandle;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskEndScheduler( void )\n{\n\t/* Stop the scheduler interrupts and call the portable scheduler end\n\troutine so the original ISRs can be restored if necessary.  The port\n\tlayer must ensure interrupts enable\tbit is left in the correct state. */\n\tportDISABLE_INTERRUPTS();\n\txSchedulerRunning = pdFALSE;\n\tvPortEndScheduler();\n}\n/*----------------------------------------------------------*/\n\nvoid vTaskSuspendAll( void )\n{\n\t/* A critical section is not required as the variable is of type\n\tBaseType_t.  Please read Richard Barry's reply in the following link to a\n\tpost in the FreeRTOS support forum before reporting this as a bug! -\n\thttp://goo.gl/wu4acr */\n\t++uxSchedulerSuspended;\n\tportMEMORY_BARRIER();\n}\n/*----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n\tstatic TickType_t prvGetExpectedIdleTime( void )\n\t{\n\tTickType_t xReturn;\n\tUBaseType_t uxHigherPriorityReadyTasks = pdFALSE;\n\n\t\t/* uxHigherPriorityReadyTasks takes care of the case where\n\t\tconfigUSE_PREEMPTION is 0, so there may be tasks above the idle priority\n\t\ttask that are in the Ready state, even though the idle task is\n\t\trunning. */\n\t\t#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )\n\t\t{\n\t\t\tif( uxTopReadyPriority > tskIDLE_PRIORITY )\n\t\t\t{\n\t\t\t\tuxHigherPriorityReadyTasks = pdTRUE;\n\t\t\t}\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tconst UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;\n\n\t\t\t/* When port optimised task selection is used the uxTopReadyPriority\n\t\t\tvariable is used as a bit map.  If bits other than the least\n\t\t\tsignificant bit are set then there are tasks that have a priority\n\t\t\tabove the idle priority that are in the Ready state.  This takes\n\t\t\tcare of the case where the co-operative scheduler is in use. */\n\t\t\tif( uxTopReadyPriority > uxLeastSignificantBit )\n\t\t\t{\n\t\t\t\tuxHigherPriorityReadyTasks = pdTRUE;\n\t\t\t}\n\t\t}\n\t\t#endif\n\n\t\tif( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )\n\t\t{\n\t\t\txReturn = 0;\n\t\t}\n\t\telse if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )\n\t\t{\n\t\t\t/* There are other idle priority tasks in the ready state.  If\n\t\t\ttime slicing is used then the very next tick interrupt must be\n\t\t\tprocessed. */\n\t\t\txReturn = 0;\n\t\t}\n\t\telse if( uxHigherPriorityReadyTasks != pdFALSE )\n\t\t{\n\t\t\t/* There are tasks in the Ready state that have a priority above the\n\t\t\tidle priority.  This path can only be reached if\n\t\t\tconfigUSE_PREEMPTION is 0. */\n\t\t\txReturn = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = xNextTaskUnblockTime - xTickCount;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*----------------------------------------------------------*/\n\nBaseType_t xTaskResumeAll( void )\n{\nTCB_t *pxTCB = NULL;\nBaseType_t xAlreadyYielded = pdFALSE;\n\n\t/* If uxSchedulerSuspended is zero then this function does not match a\n\tprevious call to vTaskSuspendAll(). */\n\tconfigASSERT( uxSchedulerSuspended );\n\n\t/* It is possible that an ISR caused a task to be removed from an event\n\tlist while the scheduler was suspended.  If this was the case then the\n\tremoved task will have been added to the xPendingReadyList.  Once the\n\tscheduler has been resumed it is safe to move all the pending ready\n\ttasks from this list into their appropriate ready list. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\t--uxSchedulerSuspended;\n\n\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t{\n\t\t\tif( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )\n\t\t\t{\n\t\t\t\t/* Move any readied tasks from the pending list into the\n\t\t\t\tappropriate ready list. */\n\t\t\t\twhile( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tpxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t\t/* If the moved task has a priority higher than the current\n\t\t\t\t\ttask then a yield must be performed. */\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif( pxTCB != NULL )\n\t\t\t\t{\n\t\t\t\t\t/* A task was unblocked while the scheduler was suspended,\n\t\t\t\t\twhich may have prevented the next unblock time from being\n\t\t\t\t\tre-calculated, in which case re-calculate it now.  Mainly\n\t\t\t\t\timportant for low power tickless implementations, where\n\t\t\t\t\tthis can prevent an unnecessary exit from low power\n\t\t\t\t\tstate. */\n\t\t\t\t\tprvResetNextTaskUnblockTime();\n\t\t\t\t}\n\n\t\t\t\t/* If any ticks occurred while the scheduler was suspended then\n\t\t\t\tthey should be processed now.  This ensures the tick count does\n\t\t\t\tnot\tslip, and that any delayed tasks are resumed at the correct\n\t\t\t\ttime. */\n\t\t\t\t{\n\t\t\t\t\tUBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */\n\n\t\t\t\t\tif( uxPendedCounts > ( UBaseType_t ) 0U )\n\t\t\t\t\t{\n\t\t\t\t\t\tdo\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( xTaskIncrementTick() != pdFALSE )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t--uxPendedCounts;\n\t\t\t\t\t\t} while( uxPendedCounts > ( UBaseType_t ) 0U );\n\n\t\t\t\t\t\tuxPendedTicks = 0;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif( xYieldPending != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t#if( configUSE_PREEMPTION != 0 )\n\t\t\t\t\t{\n\t\t\t\t\t\txAlreadyYielded = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\t#endif\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xAlreadyYielded;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTaskGetTickCount( void )\n{\nTickType_t xTicks;\n\n\t/* Critical section required if running on a 16 bit processor. */\n\tportTICK_TYPE_ENTER_CRITICAL();\n\t{\n\t\txTicks = xTickCount;\n\t}\n\tportTICK_TYPE_EXIT_CRITICAL();\n\n\treturn xTicks;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTaskGetTickCountFromISR( void )\n{\nTickType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: https://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\tuxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\txReturn = xTickCount;\n\t}\n\tportTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxTaskGetNumberOfTasks( void )\n{\n\t/* A critical section is not required because the variables are of type\n\tBaseType_t. */\n\treturn uxCurrentNumberOfTasks;\n}\n/*-----------------------------------------------------------*/\n\nchar *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n{\nTCB_t *pxTCB;\n\n\t/* If null is passed in here then the name of the calling task is being\n\tqueried. */\n\tpxTCB = prvGetTCBFromHandle( xTaskToQuery );\n\tconfigASSERT( pxTCB );\n\treturn &( pxTCB->pcTaskName[ 0 ] );\n}\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n\tstatic TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )\n\t{\n\tTCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;\n\tUBaseType_t x;\n\tchar cNextChar;\n\tBaseType_t xBreakLoop;\n\n\t\t/* This function is called with the scheduler suspended. */\n\n\t\tif( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n\t\t\tdo\n\t\t\t{\n\t\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n\t\t\t\t/* Check each character in the name looking for a match or\n\t\t\t\tmismatch. */\n\t\t\t\txBreakLoop = pdFALSE;\n\t\t\t\tfor( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\n\t\t\t\t{\n\t\t\t\t\tcNextChar = pxNextTCB->pcTaskName[ x ];\n\n\t\t\t\t\tif( cNextChar != pcNameToQuery[ x ] )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Characters didn't match. */\n\t\t\t\t\t\txBreakLoop = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse if( cNextChar == ( char ) 0x00 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Both strings terminated, a match must have been\n\t\t\t\t\t\tfound. */\n\t\t\t\t\t\tpxReturn = pxNextTCB;\n\t\t\t\t\t\txBreakLoop = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\tif( xBreakLoop != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif( pxReturn != NULL )\n\t\t\t\t{\n\t\t\t\t\t/* The handle has been found. */\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t} while( pxNextTCB != pxFirstTCB );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn pxReturn;\n\t}\n\n#endif /* INCLUDE_xTaskGetHandle */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n\tTaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t{\n\tUBaseType_t uxQueue = configMAX_PRIORITIES;\n\tTCB_t* pxTCB;\n\n\t\t/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */\n\t\tconfigASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* Search the ready lists. */\n\t\t\tdo\n\t\t\t{\n\t\t\t\tuxQueue--;\n\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );\n\n\t\t\t\tif( pxTCB != NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Found the handle. */\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\t\t\t/* Search the delayed lists. */\n\t\t\tif( pxTCB == NULL )\n\t\t\t{\n\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );\n\t\t\t}\n\n\t\t\tif( pxTCB == NULL )\n\t\t\t{\n\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );\n\t\t\t}\n\n\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\t{\n\t\t\t\tif( pxTCB == NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Search the suspended list. */\n\t\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t#if( INCLUDE_vTaskDelete == 1 )\n\t\t\t{\n\t\t\t\tif( pxTCB == NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Search the deleted list. */\n\t\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t\t( void ) xTaskResumeAll();\n\n\t\treturn pxTCB;\n\t}\n\n#endif /* INCLUDE_xTaskGetHandle */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )\n\t{\n\tUBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* Is there a space in the array for each task in the system? */\n\t\t\tif( uxArraySize >= uxCurrentNumberOfTasks )\n\t\t\t{\n\t\t\t\t/* Fill in an TaskStatus_t structure with information on each\n\t\t\t\ttask in the Ready state. */\n\t\t\t\tdo\n\t\t\t\t{\n\t\t\t\t\tuxQueue--;\n\t\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );\n\n\t\t\t\t} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\t\t\t\t/* Fill in an TaskStatus_t structure with information on each\n\t\t\t\ttask in the Blocked state. */\n\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );\n\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );\n\n\t\t\t\t#if( INCLUDE_vTaskDelete == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* Fill in an TaskStatus_t structure with information on\n\t\t\t\t\teach task that has been deleted but not yet cleaned up. */\n\t\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* Fill in an TaskStatus_t structure with information on\n\t\t\t\t\teach task in the Suspended state. */\n\t\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\t#if ( configGENERATE_RUN_TIME_STATS == 1)\n\t\t\t\t{\n\t\t\t\t\tif( pulTotalRunTime != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\n\t\t\t\t\t\t\tportALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );\n\t\t\t\t\t\t#else\n\t\t\t\t\t\t\t*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#else\n\t\t\t\t{\n\t\t\t\t\tif( pulTotalRunTime != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t*pulTotalRunTime = 0;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t( void ) xTaskResumeAll();\n\n\t\treturn uxTask;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\n\n\tTaskHandle_t xTaskGetIdleTaskHandle( void )\n\t{\n\t\t/* If xTaskGetIdleTaskHandle() is called before the scheduler has been\n\t\tstarted, then xIdleTaskHandle will be NULL. */\n\t\tconfigASSERT( ( xIdleTaskHandle != NULL ) );\n\t\treturn xIdleTaskHandle;\n\t}\n\n#endif /* INCLUDE_xTaskGetIdleTaskHandle */\n/*----------------------------------------------------------*/\n\n/* This conditional compilation should use inequality to 0, not equality to 1.\nThis is to ensure vTaskStepTick() is available when user defined low power mode\nimplementations require configUSE_TICKLESS_IDLE to be set to a value other than\n1. */\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n\tvoid vTaskStepTick( const TickType_t xTicksToJump )\n\t{\n\t\t/* Correct the tick count value after a period during which the tick\n\t\twas suppressed.  Note this does *not* call the tick hook function for\n\t\teach stepped tick. */\n\t\tconfigASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );\n\t\txTickCount += xTicksToJump;\n\t\ttraceINCREASE_TICK_COUNT( xTicksToJump );\n\t}\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskAbortDelay == 1 )\n\n\tBaseType_t xTaskAbortDelay( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB = xTask;\n\tBaseType_t xReturn;\n\n\t\tconfigASSERT( pxTCB );\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* A task can only be prematurely removed from the Blocked state if\n\t\t\tit is actually in the Blocked state. */\n\t\t\tif( eTaskGetState( xTask ) == eBlocked )\n\t\t\t{\n\t\t\t\txReturn = pdPASS;\n\n\t\t\t\t/* Remove the reference to the task from the blocked list.  An\n\t\t\t\tinterrupt won't touch the xStateListItem because the\n\t\t\t\tscheduler is suspended. */\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\n\t\t\t\t/* Is the task waiting on an event also?  If so remove it from\n\t\t\t\tthe event list too.  Interrupts can touch the event list item,\n\t\t\t\teven though the scheduler is suspended, so a critical section\n\t\t\t\tis used. */\n\t\t\t\ttaskENTER_CRITICAL();\n\t\t\t\t{\n\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t\t\t\tpxTCB->ucDelayAborted = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\t\t/* Place the unblocked task into the appropriate ready list. */\n\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t/* A task being unblocked cannot cause an immediate context\n\t\t\t\tswitch if preemption is turned off. */\n\t\t\t\t#if (  configUSE_PREEMPTION == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* Preemption is on, but a context switch should only be\n\t\t\t\t\tperformed if the unblocked task has a priority that is\n\t\t\t\t\tequal to or higher than the currently executing task. */\n\t\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Pend the yield to be performed when the scheduler\n\t\t\t\t\t\tis unsuspended. */\n\t\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_PREEMPTION */\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t}\n\t\t( void ) xTaskResumeAll();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* INCLUDE_xTaskAbortDelay */\n/*----------------------------------------------------------*/\n\nBaseType_t xTaskIncrementTick( void )\n{\nTCB_t * pxTCB;\nTickType_t xItemValue;\nBaseType_t xSwitchRequired = pdFALSE;\n\n\t/* Called by the portable layer each time a tick interrupt occurs.\n\tIncrements the tick then checks to see if the new tick value will cause any\n\ttasks to be unblocked. */\n\ttraceTASK_INCREMENT_TICK( xTickCount );\n\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t{\n\t\t/* Minor optimisation.  The tick count cannot change in this\n\t\tblock. */\n\t\tconst TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;\n\n\t\t/* Increment the RTOS tick, switching the delayed and overflowed\n\t\tdelayed lists if it wraps to 0. */\n\t\txTickCount = xConstTickCount;\n\n\t\tif( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */\n\t\t{\n\t\t\ttaskSWITCH_DELAYED_LISTS();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* See if this tick has made a timeout expire.  Tasks are stored in\n\t\tthe\tqueue in the order of their wake time - meaning once one task\n\t\thas been found whose block time has not expired there is no need to\n\t\tlook any further down the list. */\n\t\tif( xConstTickCount >= xNextTaskUnblockTime )\n\t\t{\n\t\t\tfor( ;; )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The delayed list is empty.  Set xNextTaskUnblockTime\n\t\t\t\t\tto the maximum possible value so it is extremely\n\t\t\t\t\tunlikely that the\n\t\t\t\t\tif( xTickCount >= xNextTaskUnblockTime ) test will pass\n\t\t\t\t\tnext time through. */\n\t\t\t\t\txNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The delayed list is not empty, get the value of the\n\t\t\t\t\titem at the head of the delayed list.  This is the time\n\t\t\t\t\tat which the task at the head of the delayed list must\n\t\t\t\t\tbe removed from the Blocked state. */\n\t\t\t\t\tpxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t\t\t\txItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );\n\n\t\t\t\t\tif( xConstTickCount < xItemValue )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* It is not time to unblock this item yet, but the\n\t\t\t\t\t\titem value is the time at which the task at the head\n\t\t\t\t\t\tof the blocked list must be removed from the Blocked\n\t\t\t\t\t\tstate -\tso record the item value in\n\t\t\t\t\t\txNextTaskUnblockTime. */\n\t\t\t\t\t\txNextTaskUnblockTime = xItemValue;\n\t\t\t\t\t\tbreak; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* It is time to remove the item from the Blocked state. */\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\n\t\t\t\t\t/* Is the task waiting on an event also?  If so remove\n\t\t\t\t\tit from the event list. */\n\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Place the unblocked task into the appropriate ready\n\t\t\t\t\tlist. */\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t\t/* A task being unblocked cannot cause an immediate\n\t\t\t\t\tcontext switch if preemption is turned off. */\n\t\t\t\t\t#if (  configUSE_PREEMPTION == 1 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Preemption is on, but a context switch should\n\t\t\t\t\t\tonly be performed if the unblocked task has a\n\t\t\t\t\t\tpriority that is equal to or higher than the\n\t\t\t\t\t\tcurrently executing task. */\n\t\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\txSwitchRequired = pdTRUE;\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\t#endif /* configUSE_PREEMPTION */\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Tasks of equal priority to the currently running task will share\n\t\tprocessing time (time slice) if preemption is on, and the application\n\t\twriter has not explicitly turned time slicing off. */\n\t\t#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )\n\t\t{\n\t\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )\n\t\t\t{\n\t\t\t\txSwitchRequired = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */\n\n\t\t#if ( configUSE_TICK_HOOK == 1 )\n\t\t{\n\t\t\t/* Guard against the tick hook being called when the pended tick\n\t\t\tcount is being unwound (when the scheduler is being unlocked). */\n\t\t\tif( uxPendedTicks == ( UBaseType_t ) 0U )\n\t\t\t{\n\t\t\t\tvApplicationTickHook();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configUSE_TICK_HOOK */\n\t}\n\telse\n\t{\n\t\t++uxPendedTicks;\n\n\t\t/* The tick hook gets called at regular intervals, even if the\n\t\tscheduler is locked. */\n\t\t#if ( configUSE_TICK_HOOK == 1 )\n\t\t{\n\t\t\tvApplicationTickHook();\n\t\t}\n\t\t#endif\n\t}\n\n\t#if ( configUSE_PREEMPTION == 1 )\n\t{\n\t\tif( xYieldPending != pdFALSE )\n\t\t{\n\t\t\txSwitchRequired = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\t#endif /* configUSE_PREEMPTION */\n\n\treturn xSwitchRequired;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n\tvoid vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )\n\t{\n\tTCB_t *xTCB;\n\n\t\t/* If xTask is NULL then it is the task hook of the calling task that is\n\t\tgetting set. */\n\t\tif( xTask == NULL )\n\t\t{\n\t\t\txTCB = ( TCB_t * ) pxCurrentTCB;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txTCB = xTask;\n\t\t}\n\n\t\t/* Save the hook function in the TCB.  A critical section is required as\n\t\tthe value can be accessed from an interrupt. */\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\txTCB->pxTaskTag = pxHookFunction;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\t}\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n\tTaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tTaskHookFunction_t xReturn;\n\n\t\t/* If xTask is NULL then set the calling task's hook. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t/* Save the hook function in the TCB.  A critical section is required as\n\t\tthe value can be accessed from an interrupt. */\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\txReturn = pxTCB->pxTaskTag;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n\tTaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tTaskHookFunction_t xReturn;\n\tUBaseType_t uxSavedInterruptStatus;\n\n\t\t/* If xTask is NULL then set the calling task's hook. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t/* Save the hook function in the TCB.  A critical section is required as\n\t\tthe value can be accessed from an interrupt. */\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\txReturn = pxTCB->pxTaskTag;\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n\tBaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )\n\t{\n\tTCB_t *xTCB;\n\tBaseType_t xReturn;\n\n\t\t/* If xTask is NULL then we are calling our own task hook. */\n\t\tif( xTask == NULL )\n\t\t{\n\t\t\txTCB = pxCurrentTCB;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txTCB = xTask;\n\t\t}\n\n\t\tif( xTCB->pxTaskTag != NULL )\n\t\t{\n\t\t\txReturn = xTCB->pxTaskTag( pvParameter );\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\nvoid vTaskSwitchContext( void )\n{\n\tif( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )\n\t{\n\t\t/* The scheduler is currently suspended - do not allow a context\n\t\tswitch. */\n\t\txYieldPending = pdTRUE;\n\t}\n\telse\n\t{\n\t\txYieldPending = pdFALSE;\n\t\ttraceTASK_SWITCHED_OUT();\n\n\t\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\t\t{\n\t\t\t#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\n\t\t\t\tportALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );\n\t\t\t#else\n\t\t\t\tulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\n\t\t\t#endif\n\n\t\t\t/* Add the amount of time the task has been running to the\n\t\t\taccumulated time so far.  The time the task started running was\n\t\t\tstored in ulTaskSwitchedInTime.  Note that there is no overflow\n\t\t\tprotection here so count values are only valid until the timer\n\t\t\toverflows.  The guard against negative values is to protect\n\t\t\tagainst suspect run time stat counter implementations - which\n\t\t\tare provided by the application, not the kernel. */\n\t\t\tif( ulTotalRunTime > ulTaskSwitchedInTime )\n\t\t\t{\n\t\t\t\tpxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t\tulTaskSwitchedInTime = ulTotalRunTime;\n\t\t}\n\t\t#endif /* configGENERATE_RUN_TIME_STATS */\n\n\t\t/* Check for stack overflow, if configured. */\n\t\ttaskCHECK_FOR_STACK_OVERFLOW();\n\n\t\t/* Before the currently running task is switched out, save its errno. */\n\t\t#if( configUSE_POSIX_ERRNO == 1 )\n\t\t{\n\t\t\tpxCurrentTCB->iTaskErrno = FreeRTOS_errno;\n\t\t}\n\t\t#endif\n\n\t\t/* Select a new task to run using either the generic C or port\n\t\toptimised asm code. */\n\t\ttaskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\ttraceTASK_SWITCHED_IN();\n\n\t\t/* After the new task is switched in, update the global errno. */\n\t\t#if( configUSE_POSIX_ERRNO == 1 )\n\t\t{\n\t\t\tFreeRTOS_errno = pxCurrentTCB->iTaskErrno;\n\t\t}\n\t\t#endif\n\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\t{\n\t\t\t/* Switch Newlib's _impure_ptr variable to point to the _reent\n\t\t\tstructure specific to this task. */\n\t\t\t_impure_ptr = &( pxCurrentTCB->xNewLib_reent );\n\t\t}\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )\n{\n\tconfigASSERT( pxEventList );\n\n\t/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE\n\tSCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */\n\n\t/* Place the event list item of the TCB in the appropriate event list.\n\tThis is placed in the list in priority order so the highest priority task\n\tis the first to be woken by the event.  The queue that contains the event\n\tlist is locked, preventing simultaneous access from interrupts. */\n\tvListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n\tprvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )\n{\n\tconfigASSERT( pxEventList );\n\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by\n\tthe event groups implementation. */\n\tconfigASSERT( uxSchedulerSuspended != 0 );\n\n\t/* Store the item value in the event list item.  It is safe to access the\n\tevent list item here as interrupts won't access the event list item of a\n\ttask that is not in the Blocked state. */\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\n\n\t/* Place the event list item of the TCB at the end of the appropriate event\n\tlist.  It is safe to access the event list here because it is part of an\n\tevent group implementation - and interrupts don't access event groups\n\tdirectly (instead they access them indirectly by pending function calls to\n\tthe task level). */\n\tvListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n\tprvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\n\tvoid vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )\n\t{\n\t\tconfigASSERT( pxEventList );\n\n\t\t/* This function should not be called by application code hence the\n\t\t'Restricted' in its name.  It is not part of the public API.  It is\n\t\tdesigned for use by kernel code, and has special calling requirements -\n\t\tit should be called with the scheduler suspended. */\n\n\n\t\t/* Place the event list item of the TCB in the appropriate event list.\n\t\tIn this case it is assume that this is the only task that is going to\n\t\tbe waiting on this event list, so the faster vListInsertEnd() function\n\t\tcan be used in place of vListInsert. */\n\t\tvListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n\t\t/* If the task should block indefinitely then set the block time to a\n\t\tvalue that will be recognised as an indefinite delay inside the\n\t\tprvAddCurrentTaskToDelayedList() function. */\n\t\tif( xWaitIndefinitely != pdFALSE )\n\t\t{\n\t\t\txTicksToWait = portMAX_DELAY;\n\t\t}\n\n\t\ttraceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );\n\t\tprvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );\n\t}\n\n#endif /* configUSE_TIMERS */\n/*-----------------------------------------------------------*/\n\nBaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )\n{\nTCB_t *pxUnblockedTCB;\nBaseType_t xReturn;\n\n\t/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be\n\tcalled from a critical section within an ISR. */\n\n\t/* The event list is sorted in priority order, so the first in the list can\n\tbe removed as it is known to be the highest priority.  Remove the TCB from\n\tthe delayed list, and add it to the ready list.\n\n\tIf an event is for a queue that is locked then this function will never\n\tget called - the lock count on the queue will get modified instead.  This\n\tmeans exclusive access to the event list is guaranteed here.\n\n\tThis function assumes that a check has already been made to ensure that\n\tpxEventList is not empty. */\n\tpxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\tconfigASSERT( pxUnblockedTCB );\n\t( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );\n\n\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t{\n\t\t( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );\n\t\tprvAddTaskToReadyList( pxUnblockedTCB );\n\n\t\t#if( configUSE_TICKLESS_IDLE != 0 )\n\t\t{\n\t\t\t/* If a task is blocked on a kernel object then xNextTaskUnblockTime\n\t\t\tmight be set to the blocked task's time out time.  If the task is\n\t\t\tunblocked for a reason other than a timeout xNextTaskUnblockTime is\n\t\t\tnormally left unchanged, because it is automatically reset to a new\n\t\t\tvalue when the tick count equals xNextTaskUnblockTime.  However if\n\t\t\ttickless idling is used it might be more important to enter sleep mode\n\t\t\tat the earliest possible time - so reset xNextTaskUnblockTime here to\n\t\t\tensure it is updated at the earliest possible time. */\n\t\t\tprvResetNextTaskUnblockTime();\n\t\t}\n\t\t#endif\n\t}\n\telse\n\t{\n\t\t/* The delayed and ready lists cannot be accessed, so hold this task\n\t\tpending until the scheduler is resumed. */\n\t\tvListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\n\t}\n\n\tif( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t{\n\t\t/* Return true if the task removed from the event list has a higher\n\t\tpriority than the calling task.  This allows the calling task to know if\n\t\tit should force a context switch now. */\n\t\txReturn = pdTRUE;\n\n\t\t/* Mark that a yield is pending in case the user is not using the\n\t\t\"xHigherPriorityTaskWoken\" parameter to an ISR safe FreeRTOS function. */\n\t\txYieldPending = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )\n{\nTCB_t *pxUnblockedTCB;\n\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by\n\tthe event flags implementation. */\n\tconfigASSERT( uxSchedulerSuspended != pdFALSE );\n\n\t/* Store the new item value in the event list. */\n\tlistSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\n\n\t/* Remove the event list form the event flag.  Interrupts do not access\n\tevent flags. */\n\tpxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\tconfigASSERT( pxUnblockedTCB );\n\t( void ) uxListRemove( pxEventListItem );\n\n\t/* Remove the task from the delayed list and add it to the ready list.  The\n\tscheduler is suspended so interrupts will not be accessing the ready\n\tlists. */\n\t( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );\n\tprvAddTaskToReadyList( pxUnblockedTCB );\n\n\tif( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t{\n\t\t/* The unblocked task has a priority above that of the calling task, so\n\t\ta context switch is required.  This function is called with the\n\t\tscheduler suspended so xYieldPending is set so the context switch\n\t\toccurs immediately that the scheduler is resumed (unsuspended). */\n\t\txYieldPending = pdTRUE;\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )\n{\n\tconfigASSERT( pxTimeOut );\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpxTimeOut->xOverflowCount = xNumOfOverflows;\n\t\tpxTimeOut->xTimeOnEntering = xTickCount;\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )\n{\n\t/* For internal use only as it does not use a critical section. */\n\tpxTimeOut->xOverflowCount = xNumOfOverflows;\n\tpxTimeOut->xTimeOnEntering = xTickCount;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )\n{\nBaseType_t xReturn;\n\n\tconfigASSERT( pxTimeOut );\n\tconfigASSERT( pxTicksToWait );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\t/* Minor optimisation.  The tick count cannot change in this block. */\n\t\tconst TickType_t xConstTickCount = xTickCount;\n\t\tconst TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;\n\n\t\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t\t\tif( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )\n\t\t\t{\n\t\t\t\t/* The delay was aborted, which is not the same as a time out,\n\t\t\t\tbut has the same result. */\n\t\t\t\tpxCurrentTCB->ucDelayAborted = pdFALSE;\n\t\t\t\txReturn = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t#endif\n\n\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\tif( *pxTicksToWait == portMAX_DELAY )\n\t\t\t{\n\t\t\t\t/* If INCLUDE_vTaskSuspend is set to 1 and the block time\n\t\t\t\tspecified is the maximum block time then the task should block\n\t\t\t\tindefinitely, and therefore never time out. */\n\t\t\t\txReturn = pdFALSE;\n\t\t\t}\n\t\t\telse\n\t\t#endif\n\n\t\tif( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */\n\t\t{\n\t\t\t/* The tick count is greater than the time at which\n\t\t\tvTaskSetTimeout() was called, but has also overflowed since\n\t\t\tvTaskSetTimeOut() was called.  It must have wrapped all the way\n\t\t\taround and gone past again. This passed since vTaskSetTimeout()\n\t\t\twas called. */\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */\n\t\t{\n\t\t\t/* Not a genuine timeout. Adjust parameters for time remaining. */\n\t\t\t*pxTicksToWait -= xElapsedTime;\n\t\t\tvTaskInternalSetTimeOutState( pxTimeOut );\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t*pxTicksToWait = 0;\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskMissedYield( void )\n{\n\txYieldPending = pdTRUE;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )\n\t{\n\tUBaseType_t uxReturn;\n\tTCB_t const *pxTCB;\n\n\t\tif( xTask != NULL )\n\t\t{\n\t\t\tpxTCB = xTask;\n\t\t\tuxReturn = pxTCB->uxTaskNumber;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tuxReturn = 0U;\n\t\t}\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )\n\t{\n\tTCB_t * pxTCB;\n\n\t\tif( xTask != NULL )\n\t\t{\n\t\t\tpxTCB = xTask;\n\t\t\tpxTCB->uxTaskNumber = uxHandle;\n\t\t}\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n\n/*\n * -----------------------------------------------------------\n * The Idle task.\n * ----------------------------------------------------------\n *\n * The portTASK_FUNCTION() macro is used to allow port/compiler specific\n * language extensions.  The equivalent prototype for this function is:\n *\n * void prvIdleTask( void *pvParameters );\n *\n */\nstatic portTASK_FUNCTION( prvIdleTask, pvParameters )\n{\n\t/* Stop warnings. */\n\t( void ) pvParameters;\n\n\t/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE\n\tSCHEDULER IS STARTED. **/\n\n\t/* In case a task that has a secure context deletes itself, in which case\n\tthe idle task is responsible for deleting the task's secure context, if\n\tany. */\n\tportALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );\n\n\tfor( ;; )\n\t{\n\t\t/* See if any tasks have deleted themselves - if so then the idle task\n\t\tis responsible for freeing the deleted task's TCB and stack. */\n\t\tprvCheckTasksWaitingTermination();\n\n\t\t#if ( configUSE_PREEMPTION == 0 )\n\t\t{\n\t\t\t/* If we are not using preemption we keep forcing a task switch to\n\t\t\tsee if any other task has become available.  If we are using\n\t\t\tpreemption we don't need to do this as any task becoming available\n\t\t\twill automatically get the processor anyway. */\n\t\t\ttaskYIELD();\n\t\t}\n\t\t#endif /* configUSE_PREEMPTION */\n\n\t\t#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )\n\t\t{\n\t\t\t/* When using preemption tasks of equal priority will be\n\t\t\ttimesliced.  If a task that is sharing the idle priority is ready\n\t\t\tto run then the idle task should yield before the end of the\n\t\t\ttimeslice.\n\n\t\t\tA critical region is not required here as we are just reading from\n\t\t\tthe list, and an occasional incorrect value will not matter.  If\n\t\t\tthe ready list at the idle priority contains more than one task\n\t\t\tthen a task other than the idle task is ready to execute. */\n\t\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )\n\t\t\t{\n\t\t\t\ttaskYIELD();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */\n\n\t\t#if ( configUSE_IDLE_HOOK == 1 )\n\t\t{\n\t\t\textern void vApplicationIdleHook( void );\n\n\t\t\t/* Call the user defined function from within the idle task.  This\n\t\t\tallows the application designer to add background functionality\n\t\t\twithout the overhead of a separate task.\n\t\t\tNOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,\n\t\t\tCALL A FUNCTION THAT MIGHT BLOCK. */\n\t\t\tvApplicationIdleHook();\n\t\t}\n\t\t#endif /* configUSE_IDLE_HOOK */\n\n\t\t/* This conditional compilation should use inequality to 0, not equality\n\t\tto 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when\n\t\tuser defined low power mode\timplementations require\n\t\tconfigUSE_TICKLESS_IDLE to be set to a value other than 1. */\n\t\t#if ( configUSE_TICKLESS_IDLE != 0 )\n\t\t{\n\t\tTickType_t xExpectedIdleTime;\n\n\t\t\t/* It is not desirable to suspend then resume the scheduler on\n\t\t\teach iteration of the idle task.  Therefore, a preliminary\n\t\t\ttest of the expected idle time is performed without the\n\t\t\tscheduler suspended.  The result here is not necessarily\n\t\t\tvalid. */\n\t\t\txExpectedIdleTime = prvGetExpectedIdleTime();\n\n\t\t\tif( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\n\t\t\t{\n\t\t\t\tvTaskSuspendAll();\n\t\t\t\t{\n\t\t\t\t\t/* Now the scheduler is suspended, the expected idle\n\t\t\t\t\ttime can be sampled again, and this time its value can\n\t\t\t\t\tbe used. */\n\t\t\t\t\tconfigASSERT( xNextTaskUnblockTime >= xTickCount );\n\t\t\t\t\txExpectedIdleTime = prvGetExpectedIdleTime();\n\n\t\t\t\t\t/* Define the following macro to set xExpectedIdleTime to 0\n\t\t\t\t\tif the application does not want\n\t\t\t\t\tportSUPPRESS_TICKS_AND_SLEEP() to be called. */\n\t\t\t\t\tconfigPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );\n\n\t\t\t\t\tif( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\n\t\t\t\t\t{\n\t\t\t\t\t\ttraceLOW_POWER_IDLE_BEGIN();\n\t\t\t\t\t\tportSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );\n\t\t\t\t\t\ttraceLOW_POWER_IDLE_END();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configUSE_TICKLESS_IDLE */\n\t}\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TICKLESS_IDLE != 0 )\n\n\teSleepModeStatus eTaskConfirmSleepModeStatus( void )\n\t{\n\t/* The idle task exists in addition to the application tasks. */\n\tconst UBaseType_t uxNonApplicationTasks = 1;\n\teSleepModeStatus eReturn = eStandardSleep;\n\n\t\tif( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )\n\t\t{\n\t\t\t/* A task was made ready while the scheduler was suspended. */\n\t\t\teReturn = eAbortSleep;\n\t\t}\n\t\telse if( xYieldPending != pdFALSE )\n\t\t{\n\t\t\t/* A yield was pended while the scheduler was suspended. */\n\t\t\teReturn = eAbortSleep;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* If all the tasks are in the suspended list (which might mean they\n\t\t\thave an infinite block time rather than actually being suspended)\n\t\t\tthen it is safe to turn all clocks off and just wait for external\n\t\t\tinterrupts. */\n\t\t\tif( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )\n\t\t\t{\n\t\t\t\teReturn = eNoTasksWaitingTimeout;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\treturn eReturn;\n\t}\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\n\tvoid vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )\n\t{\n\tTCB_t *pxTCB;\n\n\t\tif( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )\n\t\t{\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToSet );\n\t\t\tpxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;\n\t\t}\n\t}\n\n#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\n/*-----------------------------------------------------------*/\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\n\tvoid *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )\n\t{\n\tvoid *pvReturn = NULL;\n\tTCB_t *pxTCB;\n\n\t\tif( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )\n\t\t{\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToQuery );\n\t\t\tpvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpvReturn = NULL;\n\t\t}\n\n\t\treturn pvReturn;\n\t}\n\n#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\n/*-----------------------------------------------------------*/\n\n#if ( portUSING_MPU_WRAPPERS == 1 )\n\n\tvoid vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )\n\t{\n\tTCB_t *pxTCB;\n\n\t\t/* If null is passed in here then we are modifying the MPU settings of\n\t\tthe calling task. */\n\t\tpxTCB = prvGetTCBFromHandle( xTaskToModify );\n\n\t\tvPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );\n\t}\n\n#endif /* portUSING_MPU_WRAPPERS */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseTaskLists( void )\n{\nUBaseType_t uxPriority;\n\n\tfor( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )\n\t{\n\t\tvListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );\n\t}\n\n\tvListInitialise( &xDelayedTaskList1 );\n\tvListInitialise( &xDelayedTaskList2 );\n\tvListInitialise( &xPendingReadyList );\n\n\t#if ( INCLUDE_vTaskDelete == 1 )\n\t{\n\t\tvListInitialise( &xTasksWaitingTermination );\n\t}\n\t#endif /* INCLUDE_vTaskDelete */\n\n\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t{\n\t\tvListInitialise( &xSuspendedTaskList );\n\t}\n\t#endif /* INCLUDE_vTaskSuspend */\n\n\t/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\n\tusing list2. */\n\tpxDelayedTaskList = &xDelayedTaskList1;\n\tpxOverflowDelayedTaskList = &xDelayedTaskList2;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckTasksWaitingTermination( void )\n{\n\n\t/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/\n\n\t#if ( INCLUDE_vTaskDelete == 1 )\n\t{\n\t\tTCB_t *pxTCB;\n\n\t\t/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()\n\t\tbeing called too often in the idle task. */\n\t\twhile( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tpxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t--uxCurrentNumberOfTasks;\n\t\t\t\t--uxDeletedTasksWaitingCleanUp;\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\tprvDeleteTCB( pxTCB );\n\t\t}\n\t}\n\t#endif /* INCLUDE_vTaskDelete */\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )\n\t{\n\tTCB_t *pxTCB;\n\n\t\t/* xTask is NULL then get the state of the calling task. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\tpxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;\n\t\tpxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );\n\t\tpxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;\n\t\tpxTaskStatus->pxStackBase = pxTCB->pxStack;\n\t\tpxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;\n\n\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t{\n\t\t\tpxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tpxTaskStatus->uxBasePriority = 0;\n\t\t}\n\t\t#endif\n\n\t\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\t\t{\n\t\t\tpxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tpxTaskStatus->ulRunTimeCounter = 0;\n\t\t}\n\t\t#endif\n\n\t\t/* Obtaining the task state is a little fiddly, so is only done if the\n\t\tvalue of eState passed into this function is eInvalid - otherwise the\n\t\tstate is just set to whatever is passed in. */\n\t\tif( eState != eInvalid )\n\t\t{\n\t\t\tif( pxTCB == pxCurrentTCB )\n\t\t\t{\n\t\t\t\tpxTaskStatus->eCurrentState = eRunning;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tpxTaskStatus->eCurrentState = eState;\n\n\t\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* If the task is in the suspended list then there is a\n\t\t\t\t\tchance it is actually just blocked indefinitely - so really\n\t\t\t\t\tit should be reported as being in the Blocked state. */\n\t\t\t\t\tif( eState == eSuspended )\n\t\t\t\t\t{\n\t\t\t\t\t\tvTaskSuspendAll();\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tpxTaskStatus->eCurrentState = eBlocked;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* INCLUDE_vTaskSuspend */\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxTaskStatus->eCurrentState = eTaskGetState( pxTCB );\n\t\t}\n\n\t\t/* Obtaining the stack space takes some time, so the xGetFreeStackSpace\n\t\tparameter is provided to allow it to be skipped. */\n\t\tif( xGetFreeStackSpace != pdFALSE )\n\t\t{\n\t\t\t#if ( portSTACK_GROWTH > 0 )\n\t\t\t{\n\t\t\t\tpxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );\n\t\t\t}\n\t\t\t#else\n\t\t\t{\n\t\t\t\tpxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxTaskStatus->usStackHighWaterMark = 0;\n\t\t}\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tstatic UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )\n\t{\n\tconfigLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;\n\tUBaseType_t uxTask = 0;\n\n\t\tif( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n\t\t\t/* Populate an TaskStatus_t structure within the\n\t\t\tpxTaskStatusArray array for each task that is referenced from\n\t\t\tpxList.  See the definition of TaskStatus_t in task.h for the\n\t\t\tmeaning of each TaskStatus_t structure member. */\n\t\t\tdo\n\t\t\t{\n\t\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t\t\tvTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );\n\t\t\t\tuxTask++;\n\t\t\t} while( pxNextTCB != pxFirstTCB );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn uxTask;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n\n\tstatic configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )\n\t{\n\tuint32_t ulCount = 0U;\n\n\t\twhile( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )\n\t\t{\n\t\t\tpucStackByte -= portSTACK_GROWTH;\n\t\t\tulCount++;\n\t\t}\n\n\t\tulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */\n\n\t\treturn ( configSTACK_DEPTH_TYPE ) ulCount;\n\t}\n\n#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )\n\n\t/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n\tsame except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n\tuser to determine the return type.  It gets around the problem of the value\n\toverflowing on 8-bit types without breaking backward compatibility for\n\tapplications that expect an 8-bit return type. */\n\tconfigSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tuint8_t *pucEndOfStack;\n\tconfigSTACK_DEPTH_TYPE uxReturn;\n\n\t\t/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are\n\t\tthe same except for their return type.  Using configSTACK_DEPTH_TYPE\n\t\tallows the user to determine the return type.  It gets around the\n\t\tproblem of the value overflowing on 8-bit types without breaking\n\t\tbackward compatibility for applications that expect an 8-bit return\n\t\ttype. */\n\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t#if portSTACK_GROWTH < 0\n\t\t{\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;\n\t\t}\n\t\t#endif\n\n\t\tuxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\n\n\tUBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tuint8_t *pucEndOfStack;\n\tUBaseType_t uxReturn;\n\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t#if portSTACK_GROWTH < 0\n\t\t{\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;\n\t\t}\n\t\t#endif\n\n\t\tuxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* INCLUDE_uxTaskGetStackHighWaterMark */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelete == 1 )\n\n\tstatic void prvDeleteTCB( TCB_t *pxTCB )\n\t{\n\t\t/* This call is required specifically for the TriCore port.  It must be\n\t\tabove the vPortFree() calls.  The call is also used by ports/demos that\n\t\twant to allocate and clean RAM statically. */\n\t\tportCLEAN_UP_TCB( pxTCB );\n\n\t\t/* Free up the memory allocated by the scheduler for the task.  It is up\n\t\tto the task to free any memory allocated at the application level. */\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\t{\n\t\t\t_reclaim_reent( &( pxTCB->xNewLib_reent ) );\n\t\t}\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\n\n\t\t#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )\n\t\t{\n\t\t\t/* The task can only have been allocated dynamically - free both\n\t\t\tthe stack and TCB. */\n\t\t\tvPortFree( pxTCB->pxStack );\n\t\t\tvPortFree( pxTCB );\n\t\t}\n\t\t#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n\t\t{\n\t\t\t/* The task could have been allocated statically or dynamically, so\n\t\t\tcheck what was statically allocated before trying to free the\n\t\t\tmemory. */\n\t\t\tif( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )\n\t\t\t{\n\t\t\t\t/* Both the stack and TCB were allocated dynamically, so both\n\t\t\t\tmust be freed. */\n\t\t\t\tvPortFree( pxTCB->pxStack );\n\t\t\t\tvPortFree( pxTCB );\n\t\t\t}\n\t\t\telse if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )\n\t\t\t{\n\t\t\t\t/* Only the stack was statically allocated, so the TCB is the\n\t\t\t\tonly memory that must be freed. */\n\t\t\t\tvPortFree( pxTCB );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Neither the stack nor the TCB were allocated dynamically, so\n\t\t\t\tnothing needs to be freed. */\n\t\t\t\tconfigASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB\t);\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\t}\n\n#endif /* INCLUDE_vTaskDelete */\n/*-----------------------------------------------------------*/\n\nstatic void prvResetNextTaskUnblockTime( void )\n{\nTCB_t *pxTCB;\n\n\tif( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\n\t{\n\t\t/* The new current delayed list is empty.  Set xNextTaskUnblockTime to\n\t\tthe maximum possible value so it is\textremely unlikely that the\n\t\tif( xTickCount >= xNextTaskUnblockTime ) test will pass until\n\t\tthere is an item in the delayed list. */\n\t\txNextTaskUnblockTime = portMAX_DELAY;\n\t}\n\telse\n\t{\n\t\t/* The new current delayed list is not empty, get the value of\n\t\tthe item at the head of the delayed list.  This is the time at\n\t\twhich the task at the head of the delayed list should be removed\n\t\tfrom the Blocked state. */\n\t\t( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\txNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );\n\t}\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\n\n\tTaskHandle_t xTaskGetCurrentTaskHandle( void )\n\t{\n\tTaskHandle_t xReturn;\n\n\t\t/* A critical section is not required as this is not called from\n\t\tan interrupt and the current TCB will always be the same for any\n\t\tindividual execution thread. */\n\t\txReturn = pxCurrentTCB;\n\n\t\treturn xReturn;\n\t}\n\n#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\n\tBaseType_t xTaskGetSchedulerState( void )\n\t{\n\tBaseType_t xReturn;\n\n\t\tif( xSchedulerRunning == pdFALSE )\n\t\t{\n\t\t\txReturn = taskSCHEDULER_NOT_STARTED;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t\t{\n\t\t\t\txReturn = taskSCHEDULER_RUNNING;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = taskSCHEDULER_SUSPENDED;\n\t\t\t}\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n\tBaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )\n\t{\n\tTCB_t * const pxMutexHolderTCB = pxMutexHolder;\n\tBaseType_t xReturn = pdFALSE;\n\n\t\t/* If the mutex was given back by an interrupt while the queue was\n\t\tlocked then the mutex holder might now be NULL.  _RB_ Is this still\n\t\tneeded as interrupts can no longer use mutexes? */\n\t\tif( pxMutexHolder != NULL )\n\t\t{\n\t\t\t/* If the holder of the mutex has a priority below the priority of\n\t\t\tthe task attempting to obtain the mutex then it will temporarily\n\t\t\tinherit the priority of the task attempting to obtain the mutex. */\n\t\t\tif( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )\n\t\t\t{\n\t\t\t\t/* Adjust the mutex holder state to account for its new\n\t\t\t\tpriority.  Only reset the event list item value if the value is\n\t\t\t\tnot being used for anything else. */\n\t\t\t\tif( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n\t\t\t\t{\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t/* If the task being modified is in the ready state it will need\n\t\t\t\tto be moved into a new list. */\n\t\t\t\tif( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t\t\t{\n\t\t\t\t\t\ttaskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Inherit the priority before being moved into the new list. */\n\t\t\t\t\tpxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;\n\t\t\t\t\tprvAddTaskToReadyList( pxMutexHolderTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Just inherit the priority. */\n\t\t\t\t\tpxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;\n\t\t\t\t}\n\n\t\t\t\ttraceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );\n\n\t\t\t\t/* Inheritance occurred. */\n\t\t\t\txReturn = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\t/* The base priority of the mutex holder is lower than the\n\t\t\t\t\tpriority of the task attempting to take the mutex, but the\n\t\t\t\t\tcurrent priority of the mutex holder is not lower than the\n\t\t\t\t\tpriority of the task attempting to take the mutex.\n\t\t\t\t\tTherefore the mutex holder must have already inherited a\n\t\t\t\t\tpriority, but inheritance would have occurred if that had\n\t\t\t\t\tnot been the case. */\n\t\t\t\t\txReturn = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n\tBaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )\n\t{\n\tTCB_t * const pxTCB = pxMutexHolder;\n\tBaseType_t xReturn = pdFALSE;\n\n\t\tif( pxMutexHolder != NULL )\n\t\t{\n\t\t\t/* A task can only have an inherited priority if it holds the mutex.\n\t\t\tIf the mutex is held by a task then it cannot be given from an\n\t\t\tinterrupt, and if a mutex is given by the holding task then it must\n\t\t\tbe the running state task. */\n\t\t\tconfigASSERT( pxTCB == pxCurrentTCB );\n\t\t\tconfigASSERT( pxTCB->uxMutexesHeld );\n\t\t\t( pxTCB->uxMutexesHeld )--;\n\n\t\t\t/* Has the holder of the mutex inherited the priority of another\n\t\t\ttask? */\n\t\t\tif( pxTCB->uxPriority != pxTCB->uxBasePriority )\n\t\t\t{\n\t\t\t\t/* Only disinherit if no other mutexes are held. */\n\t\t\t\tif( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* A task can only have an inherited priority if it holds\n\t\t\t\t\tthe mutex.  If the mutex is held by a task then it cannot be\n\t\t\t\t\tgiven from an interrupt, and if a mutex is given by the\n\t\t\t\t\tholding task then it must be the running state task.  Remove\n\t\t\t\t\tthe holding task from the ready list. */\n\t\t\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t\t\t{\n\t\t\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Disinherit the priority before adding the task into the\n\t\t\t\t\tnew\tready list. */\n\t\t\t\t\ttraceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\n\t\t\t\t\tpxTCB->uxPriority = pxTCB->uxBasePriority;\n\n\t\t\t\t\t/* Reset the event list item value.  It cannot be in use for\n\t\t\t\t\tany other purpose if this task is running, and it must be\n\t\t\t\t\trunning to give back the mutex. */\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t\t/* Return true to indicate that a context switch is required.\n\t\t\t\t\tThis is only actually required in the corner case whereby\n\t\t\t\t\tmultiple mutexes were held and the mutexes were given back\n\t\t\t\t\tin an order different to that in which they were taken.\n\t\t\t\t\tIf a context switch did not occur when the first mutex was\n\t\t\t\t\treturned, even if a task was waiting on it, then a context\n\t\t\t\t\tswitch should occur when the last mutex is returned whether\n\t\t\t\t\ta task is waiting on it or not. */\n\t\t\t\t\txReturn = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n\tvoid vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )\n\t{\n\tTCB_t * const pxTCB = pxMutexHolder;\n\tUBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;\n\tconst UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;\n\n\t\tif( pxMutexHolder != NULL )\n\t\t{\n\t\t\t/* If pxMutexHolder is not NULL then the holder must hold at least\n\t\t\tone mutex. */\n\t\t\tconfigASSERT( pxTCB->uxMutexesHeld );\n\n\t\t\t/* Determine the priority to which the priority of the task that\n\t\t\tholds the mutex should be set.  This will be the greater of the\n\t\t\tholding task's base priority and the priority of the highest\n\t\t\tpriority task that is waiting to obtain the mutex. */\n\t\t\tif( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )\n\t\t\t{\n\t\t\t\tuxPriorityToUse = uxHighestPriorityWaitingTask;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tuxPriorityToUse = pxTCB->uxBasePriority;\n\t\t\t}\n\n\t\t\t/* Does the priority need to change? */\n\t\t\tif( pxTCB->uxPriority != uxPriorityToUse )\n\t\t\t{\n\t\t\t\t/* Only disinherit if no other mutexes are held.  This is a\n\t\t\t\tsimplification in the priority inheritance implementation.  If\n\t\t\t\tthe task that holds the mutex is also holding other mutexes then\n\t\t\t\tthe other mutexes may have caused the priority inheritance. */\n\t\t\t\tif( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )\n\t\t\t\t{\n\t\t\t\t\t/* If a task has timed out because it already holds the\n\t\t\t\t\tmutex it was trying to obtain then it cannot of inherited\n\t\t\t\t\tits own priority. */\n\t\t\t\t\tconfigASSERT( pxTCB != pxCurrentTCB );\n\n\t\t\t\t\t/* Disinherit the priority, remembering the previous\n\t\t\t\t\tpriority to facilitate determining the subject task's\n\t\t\t\t\tstate. */\n\t\t\t\t\ttraceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\n\t\t\t\t\tuxPriorityUsedOnEntry = pxTCB->uxPriority;\n\t\t\t\t\tpxTCB->uxPriority = uxPriorityToUse;\n\n\t\t\t\t\t/* Only reset the event list item value if the value is not\n\t\t\t\t\tbeing used for anything else. */\n\t\t\t\t\tif( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n\t\t\t\t\t{\n\t\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* If the running task is not the task that holds the mutex\n\t\t\t\t\tthen the task that holds the mutex could be in either the\n\t\t\t\t\tReady, Blocked or Suspended states.  Only remove the task\n\t\t\t\t\tfrom its current state list if it is in the Ready state as\n\t\t\t\t\tthe task's priority is going to change and there is one\n\t\t\t\t\tReady list per priority. */\n\t\t\t\t\tif( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\n\tvoid vTaskEnterCritical( void )\n\t{\n\t\tportDISABLE_INTERRUPTS();\n\n\t\tif( xSchedulerRunning != pdFALSE )\n\t\t{\n\t\t\t( pxCurrentTCB->uxCriticalNesting )++;\n\n\t\t\t/* This is not the interrupt safe version of the enter critical\n\t\t\tfunction so\tassert() if it is being called from an interrupt\n\t\t\tcontext.  Only API functions that end in \"FromISR\" can be used in an\n\t\t\tinterrupt.  Only assert if the critical nesting count is 1 to\n\t\t\tprotect against recursive calls if the assert function also uses a\n\t\t\tcritical section. */\n\t\t\tif( pxCurrentTCB->uxCriticalNesting == 1 )\n\t\t\t{\n\t\t\t\tportASSERT_IF_IN_ISR();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* portCRITICAL_NESTING_IN_TCB */\n/*-----------------------------------------------------------*/\n\n#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\n\tvoid vTaskExitCritical( void )\n\t{\n\t\tif( xSchedulerRunning != pdFALSE )\n\t\t{\n\t\t\tif( pxCurrentTCB->uxCriticalNesting > 0U )\n\t\t\t{\n\t\t\t\t( pxCurrentTCB->uxCriticalNesting )--;\n\n\t\t\t\tif( pxCurrentTCB->uxCriticalNesting == 0U )\n\t\t\t\t{\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* portCRITICAL_NESTING_IN_TCB */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\n\n\tstatic char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )\n\t{\n\tsize_t x;\n\n\t\t/* Start by copying the entire string. */\n\t\tstrcpy( pcBuffer, pcTaskName );\n\n\t\t/* Pad the end of the string with spaces to ensure columns line up when\n\t\tprinted out. */\n\t\tfor( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )\n\t\t{\n\t\t\tpcBuffer[ x ] = ' ';\n\t\t}\n\n\t\t/* Terminate. */\n\t\tpcBuffer[ x ] = ( char ) 0x00;\n\n\t\t/* Return the new end of string. */\n\t\treturn &( pcBuffer[ x ] );\n\t}\n\n#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tvoid vTaskList( char * pcWriteBuffer )\n\t{\n\tTaskStatus_t *pxTaskStatusArray;\n\tUBaseType_t uxArraySize, x;\n\tchar cStatus;\n\n\t\t/*\n\t\t * PLEASE NOTE:\n\t\t *\n\t\t * This function is provided for convenience only, and is used by many\n\t\t * of the demo applications.  Do not consider it to be part of the\n\t\t * scheduler.\n\t\t *\n\t\t * vTaskList() calls uxTaskGetSystemState(), then formats part of the\n\t\t * uxTaskGetSystemState() output into a human readable table that\n\t\t * displays task names, states and stack usage.\n\t\t *\n\t\t * vTaskList() has a dependency on the sprintf() C library function that\n\t\t * might bloat the code size, use a lot of stack, and provide different\n\t\t * results on different platforms.  An alternative, tiny, third party,\n\t\t * and limited functionality implementation of sprintf() is provided in\n\t\t * many of the FreeRTOS/Demo sub-directories in a file called\n\t\t * printf-stdarg.c (note printf-stdarg.c does not provide a full\n\t\t * snprintf() implementation!).\n\t\t *\n\t\t * It is recommended that production systems call uxTaskGetSystemState()\n\t\t * directly to get access to raw stats data, rather than indirectly\n\t\t * through a call to vTaskList().\n\t\t */\n\n\n\t\t/* Make sure the write buffer does not contain a string. */\n\t\t*pcWriteBuffer = ( char ) 0x00;\n\n\t\t/* Take a snapshot of the number of tasks in case it changes while this\n\t\tfunction is executing. */\n\t\tuxArraySize = uxCurrentNumberOfTasks;\n\n\t\t/* Allocate an array index for each task.  NOTE!  if\n\t\tconfigSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will\n\t\tequate to NULL. */\n\t\tpxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */\n\n\t\tif( pxTaskStatusArray != NULL )\n\t\t{\n\t\t\t/* Generate the (binary) data. */\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );\n\n\t\t\t/* Create a human readable table from the binary data. */\n\t\t\tfor( x = 0; x < uxArraySize; x++ )\n\t\t\t{\n\t\t\t\tswitch( pxTaskStatusArray[ x ].eCurrentState )\n\t\t\t\t{\n\t\t\t\t\tcase eRunning:\t\tcStatus = tskRUNNING_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eReady:\t\tcStatus = tskREADY_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eBlocked:\t\tcStatus = tskBLOCKED_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eSuspended:\tcStatus = tskSUSPENDED_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eDeleted:\t\tcStatus = tskDELETED_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eInvalid:\t\t/* Fall through. */\n\t\t\t\t\tdefault:\t\t\t/* Should not get here, but it is included\n\t\t\t\t\t\t\t\t\t\tto prevent static checking errors. */\n\t\t\t\t\t\t\t\t\t\tcStatus = ( char ) 0x00;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\t/* Write the task name to the string, padding with spaces so it\n\t\t\t\tcan be printed in tabular form more easily. */\n\t\t\t\tpcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\n\n\t\t\t\t/* Write the rest of the string. */\n\t\t\t\tsprintf( pcWriteBuffer, \"\\t%c\\t%u\\t%u\\t%u\\r\\n\", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n\t\t\t\tpcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */\n\t\t\t}\n\n\t\t\t/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION\n\t\t\tis 0 then vPortFree() will be #defined to nothing. */\n\t\t\tvPortFree( pxTaskStatusArray );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*----------------------------------------------------------*/\n\n#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tvoid vTaskGetRunTimeStats( char *pcWriteBuffer )\n\t{\n\tTaskStatus_t *pxTaskStatusArray;\n\tUBaseType_t uxArraySize, x;\n\tuint32_t ulTotalTime, ulStatsAsPercentage;\n\n\t\t#if( configUSE_TRACE_FACILITY != 1 )\n\t\t{\n\t\t\t#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().\n\t\t}\n\t\t#endif\n\n\t\t/*\n\t\t * PLEASE NOTE:\n\t\t *\n\t\t * This function is provided for convenience only, and is used by many\n\t\t * of the demo applications.  Do not consider it to be part of the\n\t\t * scheduler.\n\t\t *\n\t\t * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part\n\t\t * of the uxTaskGetSystemState() output into a human readable table that\n\t\t * displays the amount of time each task has spent in the Running state\n\t\t * in both absolute and percentage terms.\n\t\t *\n\t\t * vTaskGetRunTimeStats() has a dependency on the sprintf() C library\n\t\t * function that might bloat the code size, use a lot of stack, and\n\t\t * provide different results on different platforms.  An alternative,\n\t\t * tiny, third party, and limited functionality implementation of\n\t\t * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in\n\t\t * a file called printf-stdarg.c (note printf-stdarg.c does not provide\n\t\t * a full snprintf() implementation!).\n\t\t *\n\t\t * It is recommended that production systems call uxTaskGetSystemState()\n\t\t * directly to get access to raw stats data, rather than indirectly\n\t\t * through a call to vTaskGetRunTimeStats().\n\t\t */\n\n\t\t/* Make sure the write buffer does not contain a string. */\n\t\t*pcWriteBuffer = ( char ) 0x00;\n\n\t\t/* Take a snapshot of the number of tasks in case it changes while this\n\t\tfunction is executing. */\n\t\tuxArraySize = uxCurrentNumberOfTasks;\n\n\t\t/* Allocate an array index for each task.  NOTE!  If\n\t\tconfigSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will\n\t\tequate to NULL. */\n\t\tpxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */\n\n\t\tif( pxTaskStatusArray != NULL )\n\t\t{\n\t\t\t/* Generate the (binary) data. */\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );\n\n\t\t\t/* For percentage calculations. */\n\t\t\tulTotalTime /= 100UL;\n\n\t\t\t/* Avoid divide by zero errors. */\n\t\t\tif( ulTotalTime > 0UL )\n\t\t\t{\n\t\t\t\t/* Create a human readable table from the binary data. */\n\t\t\t\tfor( x = 0; x < uxArraySize; x++ )\n\t\t\t\t{\n\t\t\t\t\t/* What percentage of the total run time has the task used?\n\t\t\t\t\tThis will always be rounded down to the nearest integer.\n\t\t\t\t\tulTotalRunTimeDiv100 has already been divided by 100. */\n\t\t\t\t\tulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;\n\n\t\t\t\t\t/* Write the task name to the string, padding with\n\t\t\t\t\tspaces so it can be printed in tabular form more\n\t\t\t\t\teasily. */\n\t\t\t\t\tpcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\n\n\t\t\t\t\tif( ulStatsAsPercentage > 0UL )\n\t\t\t\t\t{\n\t\t\t\t\t\t#ifdef portLU_PRINTF_SPECIFIER_REQUIRED\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#else\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* sizeof( int ) == sizeof( long ) so a smaller\n\t\t\t\t\t\t\tprintf() library can be used. */\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%u\\t\\t%u%%\\r\\n\", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* If the percentage is zero here then the task has\n\t\t\t\t\t\tconsumed less than 1% of the total run time. */\n\t\t\t\t\t\t#ifdef portLU_PRINTF_SPECIFIER_REQUIRED\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].ulRunTimeCounter );\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#else\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* sizeof( int ) == sizeof( long ) so a smaller\n\t\t\t\t\t\t\tprintf() library can be used. */\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%u\\t\\t<1%%\\r\\n\", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\n\t\t\t\t\tpcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION\n\t\t\tis 0 then vPortFree() will be #defined to nothing. */\n\t\t\tvPortFree( pxTaskStatusArray );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nTickType_t uxTaskResetEventItemValue( void )\n{\nTickType_t uxReturn;\n\n\tuxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );\n\n\t/* Reset the event list item to its normal value - so it can be used with\n\tqueues and semaphores. */\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n\tTaskHandle_t pvTaskIncrementMutexHeldCount( void )\n\t{\n\t\t/* If xSemaphoreCreateMutex() is called before any tasks have been created\n\t\tthen pxCurrentTCB will be NULL. */\n\t\tif( pxCurrentTCB != NULL )\n\t\t{\n\t\t\t( pxCurrentTCB->uxMutexesHeld )++;\n\t\t}\n\n\t\treturn pxCurrentTCB;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tuint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )\n\t{\n\tuint32_t ulReturn;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Only block if the notification count is not already non-zero. */\n\t\t\tif( pxCurrentTCB->ulNotifiedValue == 0UL )\n\t\t\t{\n\t\t\t\t/* Mark this task as waiting for a notification. */\n\t\t\t\tpxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;\n\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\tprvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n\t\t\t\t\ttraceTASK_NOTIFY_TAKE_BLOCK();\n\n\t\t\t\t\t/* All ports are written to allow a yield in a critical\n\t\t\t\t\tsection (some will yield immediately, others wait until the\n\t\t\t\t\tcritical section exits) - but it is not something that\n\t\t\t\t\tapplication code should ever do. */\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\ttraceTASK_NOTIFY_TAKE();\n\t\t\tulReturn = pxCurrentTCB->ulNotifiedValue;\n\n\t\t\tif( ulReturn != 0UL )\n\t\t\t{\n\t\t\t\tif( xClearCountOnExit != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tpxCurrentTCB->ulNotifiedValue = 0UL;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tpxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tpxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn ulReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tBaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )\n\t{\n\tBaseType_t xReturn;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Only block if a notification is not already pending. */\n\t\t\tif( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )\n\t\t\t{\n\t\t\t\t/* Clear bits in the task's notification value as bits may get\n\t\t\t\tset\tby the notifying task or interrupt.  This can be used to\n\t\t\t\tclear the value to zero. */\n\t\t\t\tpxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;\n\n\t\t\t\t/* Mark this task as waiting for a notification. */\n\t\t\t\tpxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;\n\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\tprvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n\t\t\t\t\ttraceTASK_NOTIFY_WAIT_BLOCK();\n\n\t\t\t\t\t/* All ports are written to allow a yield in a critical\n\t\t\t\t\tsection (some will yield immediately, others wait until the\n\t\t\t\t\tcritical section exits) - but it is not something that\n\t\t\t\t\tapplication code should ever do. */\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\ttraceTASK_NOTIFY_WAIT();\n\n\t\t\tif( pulNotificationValue != NULL )\n\t\t\t{\n\t\t\t\t/* Output the current notification value, which may or may not\n\t\t\t\thave changed. */\n\t\t\t\t*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;\n\t\t\t}\n\n\t\t\t/* If ucNotifyValue is set then either the task never entered the\n\t\t\tblocked state (because a notification was already pending) or the\n\t\t\ttask unblocked because of a notification.  Otherwise the task\n\t\t\tunblocked because of a timeout. */\n\t\t\tif( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )\n\t\t\t{\n\t\t\t\t/* A notification was not received. */\n\t\t\t\txReturn = pdFALSE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* A notification was already pending or a notification was\n\t\t\t\treceived while the task was waiting. */\n\t\t\t\tpxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;\n\t\t\t\txReturn = pdTRUE;\n\t\t\t}\n\n\t\t\tpxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tBaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )\n\t{\n\tTCB_t * pxTCB;\n\tBaseType_t xReturn = pdPASS;\n\tuint8_t ucOriginalNotifyState;\n\n\t\tconfigASSERT( xTaskToNotify );\n\t\tpxTCB = xTaskToNotify;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tif( pulPreviousNotificationValue != NULL )\n\t\t\t{\n\t\t\t\t*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;\n\t\t\t}\n\n\t\t\tucOriginalNotifyState = pxTCB->ucNotifyState;\n\n\t\t\tpxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;\n\n\t\t\tswitch( eAction )\n\t\t\t{\n\t\t\t\tcase eSetBits\t:\n\t\t\t\t\tpxTCB->ulNotifiedValue |= ulValue;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eIncrement\t:\n\t\t\t\t\t( pxTCB->ulNotifiedValue )++;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eSetValueWithOverwrite\t:\n\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eSetValueWithoutOverwrite :\n\t\t\t\t\tif( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )\n\t\t\t\t\t{\n\t\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The value could not be written to the task. */\n\t\t\t\t\t\txReturn = pdFAIL;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eNoAction:\n\t\t\t\t\t/* The task is being notified without its notify value being\n\t\t\t\t\tupdated. */\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\t/* Should not get here if all enums are handled.\n\t\t\t\t\tArtificially force an assert by testing a value the\n\t\t\t\t\tcompiler can't assume is const. */\n\t\t\t\t\tconfigASSERT( pxTCB->ulNotifiedValue == ~0UL );\n\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\ttraceTASK_NOTIFY();\n\n\t\t\t/* If the task is in the blocked state specifically to wait for a\n\t\t\tnotification then unblock it now. */\n\t\t\tif( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t{\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t/* The task should not have been on an event list. */\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n\t\t\t\t#if( configUSE_TICKLESS_IDLE != 0 )\n\t\t\t\t{\n\t\t\t\t\t/* If a task is blocked waiting for a notification then\n\t\t\t\t\txNextTaskUnblockTime might be set to the blocked task's time\n\t\t\t\t\tout time.  If the task is unblocked for a reason other than\n\t\t\t\t\ta timeout xNextTaskUnblockTime is normally left unchanged,\n\t\t\t\t\tbecause it will automatically get reset to a new value when\n\t\t\t\t\tthe tick count equals xNextTaskUnblockTime.  However if\n\t\t\t\t\ttickless idling is used it might be more important to enter\n\t\t\t\t\tsleep mode at the earliest possible time - so reset\n\t\t\t\t\txNextTaskUnblockTime here to ensure it is updated at the\n\t\t\t\t\tearliest possible time. */\n\t\t\t\t\tprvResetNextTaskUnblockTime();\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\t/* The notified task has a priority above the currently\n\t\t\t\t\texecuting task so a yield is required. */\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tBaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )\n\t{\n\tTCB_t * pxTCB;\n\tuint8_t ucOriginalNotifyState;\n\tBaseType_t xReturn = pdPASS;\n\tUBaseType_t uxSavedInterruptStatus;\n\n\t\tconfigASSERT( xTaskToNotify );\n\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\n\t\tInterrupts that are\tabove the maximum system call priority are keep\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\n\t\tis defined in FreeRTOSConfig.h then\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\n\t\tbeen assigned a priority above the configured maximum system call\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\n\t\tprovided on the following link:\n\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t\tpxTCB = xTaskToNotify;\n\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\tif( pulPreviousNotificationValue != NULL )\n\t\t\t{\n\t\t\t\t*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;\n\t\t\t}\n\n\t\t\tucOriginalNotifyState = pxTCB->ucNotifyState;\n\t\t\tpxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;\n\n\t\t\tswitch( eAction )\n\t\t\t{\n\t\t\t\tcase eSetBits\t:\n\t\t\t\t\tpxTCB->ulNotifiedValue |= ulValue;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eIncrement\t:\n\t\t\t\t\t( pxTCB->ulNotifiedValue )++;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eSetValueWithOverwrite\t:\n\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eSetValueWithoutOverwrite :\n\t\t\t\t\tif( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )\n\t\t\t\t\t{\n\t\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The value could not be written to the task. */\n\t\t\t\t\t\txReturn = pdFAIL;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eNoAction :\n\t\t\t\t\t/* The task is being notified without its notify value being\n\t\t\t\t\tupdated. */\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\t/* Should not get here if all enums are handled.\n\t\t\t\t\tArtificially force an assert by testing a value the\n\t\t\t\t\tcompiler can't assume is const. */\n\t\t\t\t\tconfigASSERT( pxTCB->ulNotifiedValue == ~0UL );\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\ttraceTASK_NOTIFY_FROM_ISR();\n\n\t\t\t/* If the task is in the blocked state specifically to wait for a\n\t\t\tnotification then unblock it now. */\n\t\t\tif( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t{\n\t\t\t\t/* The task should not have been on an event list. */\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The delayed and ready lists cannot be accessed, so hold\n\t\t\t\t\tthis task pending until the scheduler is resumed. */\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n\t\t\t\t}\n\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\t/* The notified task has a priority above the currently\n\t\t\t\t\texecuting task so a yield is required. */\n\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Mark that a yield is pending in case the user is not\n\t\t\t\t\tusing the \"xHigherPriorityTaskWoken\" parameter to an ISR\n\t\t\t\t\tsafe FreeRTOS function. */\n\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tvoid vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )\n\t{\n\tTCB_t * pxTCB;\n\tuint8_t ucOriginalNotifyState;\n\tUBaseType_t uxSavedInterruptStatus;\n\n\t\tconfigASSERT( xTaskToNotify );\n\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\n\t\tInterrupts that are\tabove the maximum system call priority are keep\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\n\t\tis defined in FreeRTOSConfig.h then\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\n\t\tbeen assigned a priority above the configured maximum system call\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\n\t\tprovided on the following link:\n\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t\tpxTCB = xTaskToNotify;\n\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\tucOriginalNotifyState = pxTCB->ucNotifyState;\n\t\t\tpxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;\n\n\t\t\t/* 'Giving' is equivalent to incrementing a count in a counting\n\t\t\tsemaphore. */\n\t\t\t( pxTCB->ulNotifiedValue )++;\n\n\t\t\ttraceTASK_NOTIFY_GIVE_FROM_ISR();\n\n\t\t\t/* If the task is in the blocked state specifically to wait for a\n\t\t\tnotification then unblock it now. */\n\t\t\tif( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t{\n\t\t\t\t/* The task should not have been on an event list. */\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The delayed and ready lists cannot be accessed, so hold\n\t\t\t\t\tthis task pending until the scheduler is resumed. */\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n\t\t\t\t}\n\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\t/* The notified task has a priority above the currently\n\t\t\t\t\texecuting task so a yield is required. */\n\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Mark that a yield is pending in case the user is not\n\t\t\t\t\tusing the \"xHigherPriorityTaskWoken\" parameter in an ISR\n\t\t\t\t\tsafe FreeRTOS function. */\n\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tBaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tBaseType_t xReturn;\n\n\t\t/* If null is passed in here then it is the calling task that is having\n\t\tits notification state cleared. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tif( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )\n\t\t\t{\n\t\t\t\tpxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t\t\t\txReturn = pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )\n\tTickType_t xTaskGetIdleRunTimeCounter( void )\n\t{\n\t\treturn xIdleTaskHandle->ulRunTimeCounter;\n\t}\n#endif\n/*-----------------------------------------------------------*/\n\nstatic void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )\n{\nTickType_t xTimeToWake;\nconst TickType_t xConstTickCount = xTickCount;\n\n\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t{\n\t\t/* About to enter a delayed list, so ensure the ucDelayAborted flag is\n\t\treset to pdFALSE so it can be detected as having been set to pdTRUE\n\t\twhen the task leaves the Blocked state. */\n\t\tpxCurrentTCB->ucDelayAborted = pdFALSE;\n\t}\n\t#endif\n\n\t/* Remove the task from the ready list before adding it to the blocked list\n\tas the same list item is used for both lists. */\n\tif( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t{\n\t\t/* The current task must be in a ready list, so there is no need to\n\t\tcheck, and the port reset macro can be called directly. */\n\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t{\n\t\tif( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )\n\t\t{\n\t\t\t/* Add the task to the suspended task list instead of a delayed task\n\t\t\tlist to ensure it is not woken by a timing event.  It will block\n\t\t\tindefinitely. */\n\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Calculate the time at which the task should be woken if the event\n\t\t\tdoes not occur.  This may overflow but this doesn't matter, the\n\t\t\tkernel will manage it correctly. */\n\t\t\txTimeToWake = xConstTickCount + xTicksToWait;\n\n\t\t\t/* The list item will be inserted in wake time order. */\n\t\t\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );\n\n\t\t\tif( xTimeToWake < xConstTickCount )\n\t\t\t{\n\t\t\t\t/* Wake time has overflowed.  Place this item in the overflow\n\t\t\t\tlist. */\n\t\t\t\tvListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The wake time has not overflowed, so the current block list\n\t\t\t\tis used. */\n\t\t\t\tvListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\n\t\t\t\t/* If the task entering the blocked state was placed at the\n\t\t\t\thead of the list of blocked tasks then xNextTaskUnblockTime\n\t\t\t\tneeds to be updated too. */\n\t\t\t\tif( xTimeToWake < xNextTaskUnblockTime )\n\t\t\t\t{\n\t\t\t\t\txNextTaskUnblockTime = xTimeToWake;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t#else /* INCLUDE_vTaskSuspend */\n\t{\n\t\t/* Calculate the time at which the task should be woken if the event\n\t\tdoes not occur.  This may overflow but this doesn't matter, the kernel\n\t\twill manage it correctly. */\n\t\txTimeToWake = xConstTickCount + xTicksToWait;\n\n\t\t/* The list item will be inserted in wake time order. */\n\t\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );\n\n\t\tif( xTimeToWake < xConstTickCount )\n\t\t{\n\t\t\t/* Wake time has overflowed.  Place this item in the overflow list. */\n\t\t\tvListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The wake time has not overflowed, so the current block list is used. */\n\t\t\tvListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\n\t\t\t/* If the task entering the blocked state was placed at the head of the\n\t\t\tlist of blocked tasks then xNextTaskUnblockTime needs to be updated\n\t\t\ttoo. */\n\t\t\tif( xTimeToWake < xNextTaskUnblockTime )\n\t\t\t{\n\t\t\t\txNextTaskUnblockTime = xTimeToWake;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\t/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */\n\t\t( void ) xCanBlockIndefinitely;\n\t}\n\t#endif /* INCLUDE_vTaskSuspend */\n}\n\n/* Code below here allows additional code to be inserted into this source file,\nespecially where access to file scope functions and data is needed (for example\nwhen performing module tests). */\n\n#ifdef FREERTOS_MODULE_TEST\n\t#include \"tasks_test_access_functions.h\"\n#endif\n\n\n#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )\n\n\t#include \"freertos_tasks_c_additions.h\"\n\n\t#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n\t\tstatic void freertos_tasks_c_additions_init( void )\n\t\t{\n\t\t\tFREERTOS_TASKS_C_ADDITIONS_INIT();\n\t\t}\n\t#endif\n\n#endif\n\n\n"
  },
  {
    "path": "examples/lib/FreeRTOS/timers.c",
    "content": "/*\n * FreeRTOS Kernel V10.2.1\n * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n#include \"timers.h\"\n\n#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )\n\t#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.\n#endif\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */\n\n\n/* This entire source file will be skipped if the application is not configured\nto include software timer functionality.  This #if is closed at the very bottom\nof this file.  If you want to include software timer functionality then ensure\nconfigUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\n#if ( configUSE_TIMERS == 1 )\n\n/* Misc definitions. */\n#define tmrNO_DELAY\t\t( TickType_t ) 0U\n\n/* The name assigned to the timer service task.  This can be overridden by\ndefining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */\n#ifndef configTIMER_SERVICE_TASK_NAME\n\t#define configTIMER_SERVICE_TASK_NAME \"Tmr Svc\"\n#endif\n\n/* Bit definitions used in the ucStatus member of a timer structure. */\n#define tmrSTATUS_IS_ACTIVE\t\t\t\t\t( ( uint8_t ) 0x01 )\n#define tmrSTATUS_IS_STATICALLY_ALLOCATED\t( ( uint8_t ) 0x02 )\n#define tmrSTATUS_IS_AUTORELOAD\t\t\t\t( ( uint8_t ) 0x04 )\n\n/* The definition of the timers themselves. */\ntypedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */\n{\n\tconst char\t\t\t\t*pcTimerName;\t\t/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\tListItem_t\t\t\t\txTimerListItem;\t\t/*<< Standard linked list item as used by all kernel features for event management. */\n\tTickType_t\t\t\t\txTimerPeriodInTicks;/*<< How quickly and often the timer expires. */\n\tvoid \t\t\t\t\t*pvTimerID;\t\t\t/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */\n\tTimerCallbackFunction_t\tpxCallbackFunction;\t/*<< The function that will be called when the timer expires. */\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t\t\t\tuxTimerNumber;\t\t/*<< An ID assigned by trace tools such as FreeRTOS+Trace */\n\t#endif\n\tuint8_t \t\t\t\tucStatus;\t\t\t/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */\n} xTIMER;\n\n/* The old xTIMER name is maintained above then typedefed to the new Timer_t\nname below to enable the use of older kernel aware debuggers. */\ntypedef xTIMER Timer_t;\n\n/* The definition of messages that can be sent and received on the timer queue.\nTwo types of message can be queued - messages that manipulate a software timer,\nand messages that request the execution of a non-timer related callback.  The\ntwo message types are defined in two separate structures, xTimerParametersType\nand xCallbackParametersType respectively. */\ntypedef struct tmrTimerParameters\n{\n\tTickType_t\t\t\txMessageValue;\t\t/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */\n\tTimer_t *\t\t\tpxTimer;\t\t\t/*<< The timer to which the command will be applied. */\n} TimerParameter_t;\n\n\ntypedef struct tmrCallbackParameters\n{\n\tPendedFunction_t\tpxCallbackFunction;\t/* << The callback function to execute. */\n\tvoid *pvParameter1;\t\t\t\t\t\t/* << The value that will be used as the callback functions first parameter. */\n\tuint32_t ulParameter2;\t\t\t\t\t/* << The value that will be used as the callback functions second parameter. */\n} CallbackParameters_t;\n\n/* The structure that contains the two message types, along with an identifier\nthat is used to determine which message type is valid. */\ntypedef struct tmrTimerQueueMessage\n{\n\tBaseType_t\t\t\txMessageID;\t\t\t/*<< The command being sent to the timer service task. */\n\tunion\n\t{\n\t\tTimerParameter_t xTimerParameters;\n\n\t\t/* Don't include xCallbackParameters if it is not going to be used as\n\t\tit makes the structure (and therefore the timer queue) larger. */\n\t\t#if ( INCLUDE_xTimerPendFunctionCall == 1 )\n\t\t\tCallbackParameters_t xCallbackParameters;\n\t\t#endif /* INCLUDE_xTimerPendFunctionCall */\n\t} u;\n} DaemonTaskMessage_t;\n\n/*lint -save -e956 A manual analysis and inspection has been used to determine\nwhich static variables must be declared volatile. */\n\n/* The list in which active timers are stored.  Timers are referenced in expire\ntime order, with the nearest expiry time at the front of the list.  Only the\ntimer service task is allowed to access these lists.\nxActiveTimerList1 and xActiveTimerList2 could be at function scope but that\nbreaks some kernel aware debuggers, and debuggers that reply on removing the\nstatic qualifier. */\nPRIVILEGED_DATA static List_t xActiveTimerList1;\nPRIVILEGED_DATA static List_t xActiveTimerList2;\nPRIVILEGED_DATA static List_t *pxCurrentTimerList;\nPRIVILEGED_DATA static List_t *pxOverflowTimerList;\n\n/* A queue that is used to send commands to the timer service task. */\nPRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;\nPRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;\n\n/*lint -restore */\n\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\t/* If static allocation is supported then the application must provide the\n\tfollowing callback function - which enables the application to optionally\n\tprovide the memory that will be used by the timer task as the task's stack\n\tand TCB. */\n\textern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );\n\n#endif\n\n/*\n * Initialise the infrastructure used by the timer service task if it has not\n * been initialised already.\n */\nstatic void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The timer service task (daemon).  Timer functionality is controlled by this\n * task.  Other tasks communicate with the timer service task using the\n * xTimerQueue queue.\n */\nstatic portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;\n\n/*\n * Called by the timer service task to interpret and process a command it\n * received on the timer queue.\n */\nstatic void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,\n * depending on if the expire time causes a timer counter overflow.\n */\nstatic BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;\n\n/*\n * An active timer has reached its expire time.  Reload the timer if it is an\n * auto reload timer, then call its callback.\n */\nstatic void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;\n\n/*\n * The tick count has overflowed.  Switch the timer lists after ensuring the\n * current timer list does not still reference some timers.\n */\nstatic void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE\n * if a tick count overflow occurred since prvSampleTimeNow() was last called.\n */\nstatic TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;\n\n/*\n * If the timer list contains any active timers then return the expire time of\n * the timer that will expire first and set *pxListWasEmpty to false.  If the\n * timer list does not contain any timers then return 0 and set *pxListWasEmpty\n * to pdTRUE.\n */\nstatic TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;\n\n/*\n * If a timer has expired, process it.  Otherwise, block the timer service task\n * until either a timer does expire or a command is received.\n */\nstatic void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;\n\n/*\n * Called after a Timer_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\nstatic void prvInitialiseNewTimer(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n\t\t\t\t\t\t\t\t\tTimer_t *pxNewTimer ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\nBaseType_t xTimerCreateTimerTask( void )\n{\nBaseType_t xReturn = pdFAIL;\n\n\t/* This function is called when the scheduler is started if\n\tconfigUSE_TIMERS is set to 1.  Check that the infrastructure used by the\n\ttimer service task has been created/initialised.  If timers have already\n\tbeen created then the initialisation will already have been performed. */\n\tprvCheckForValidListAndQueue();\n\n\tif( xTimerQueue != NULL )\n\t{\n\t\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t\t{\n\t\t\tStaticTask_t *pxTimerTaskTCBBuffer = NULL;\n\t\t\tStackType_t *pxTimerTaskStackBuffer = NULL;\n\t\t\tuint32_t ulTimerTaskStackSize;\n\n\t\t\tvApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );\n\t\t\txTimerTaskHandle = xTaskCreateStatic(\tprvTimerTask,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconfigTIMER_SERVICE_TASK_NAME,\n\t\t\t\t\t\t\t\t\t\t\t\t\tulTimerTaskStackSize,\n\t\t\t\t\t\t\t\t\t\t\t\t\tNULL,\n\t\t\t\t\t\t\t\t\t\t\t\t\t( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,\n\t\t\t\t\t\t\t\t\t\t\t\t\tpxTimerTaskStackBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\t\tpxTimerTaskTCBBuffer );\n\n\t\t\tif( xTimerTaskHandle != NULL )\n\t\t\t{\n\t\t\t\txReturn = pdPASS;\n\t\t\t}\n\t\t}\n\t\t#else\n\t\t{\n\t\t\txReturn = xTaskCreate(\tprvTimerTask,\n\t\t\t\t\t\t\t\t\tconfigTIMER_SERVICE_TASK_NAME,\n\t\t\t\t\t\t\t\t\tconfigTIMER_TASK_STACK_DEPTH,\n\t\t\t\t\t\t\t\t\tNULL,\n\t\t\t\t\t\t\t\t\t( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,\n\t\t\t\t\t\t\t\t\t&xTimerTaskHandle );\n\t\t}\n\t\t#endif /* configSUPPORT_STATIC_ALLOCATION */\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tconfigASSERT( xReturn );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tTimerHandle_t xTimerCreate(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction )\n\t{\n\tTimer_t *pxNewTimer;\n\n\t\tpxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */\n\n\t\tif( pxNewTimer != NULL )\n\t\t{\n\t\t\t/* Status is thus far zero as the timer is not created statically\n\t\t\tand has not been started.  The autoreload bit may get set in\n\t\t\tprvInitialiseNewTimer. */\n\t\t\tpxNewTimer->ucStatus = 0x00;\n\t\t\tprvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );\n\t\t}\n\n\t\treturn pxNewTimer;\n\t}\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tTimerHandle_t xTimerCreateStatic(\tconst char * const pcTimerName,\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n\t\t\t\t\t\t\t\t\t\tStaticTimer_t *pxTimerBuffer )\n\t{\n\tTimer_t *pxNewTimer;\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticTimer_t equals the size of the real timer\n\t\t\tstructure. */\n\t\t\tvolatile size_t xSize = sizeof( StaticTimer_t );\n\t\t\tconfigASSERT( xSize == sizeof( Timer_t ) );\n\t\t\t( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */\n\t\t}\n\t\t#endif /* configASSERT_DEFINED */\n\n\t\t/* A pointer to a StaticTimer_t structure MUST be provided, use it. */\n\t\tconfigASSERT( pxTimerBuffer );\n\t\tpxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */\n\n\t\tif( pxNewTimer != NULL )\n\t\t{\n\t\t\t/* Timers can be created statically or dynamically so note this\n\t\t\ttimer was created statically in case it is later deleted.  The\n\t\t\tautoreload bit may get set in prvInitialiseNewTimer(). */\n\t\t\tpxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;\n\n\t\t\tprvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );\n\t\t}\n\n\t\treturn pxNewTimer;\n\t}\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewTimer(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n\t\t\t\t\t\t\t\t\tTimer_t *pxNewTimer )\n{\n\t/* 0 is not a valid value for xTimerPeriodInTicks. */\n\tconfigASSERT( ( xTimerPeriodInTicks > 0 ) );\n\n\tif( pxNewTimer != NULL )\n\t{\n\t\t/* Ensure the infrastructure used by the timer service task has been\n\t\tcreated/initialised. */\n\t\tprvCheckForValidListAndQueue();\n\n\t\t/* Initialise the timer structure members using the function\n\t\tparameters. */\n\t\tpxNewTimer->pcTimerName = pcTimerName;\n\t\tpxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;\n\t\tpxNewTimer->pvTimerID = pvTimerID;\n\t\tpxNewTimer->pxCallbackFunction = pxCallbackFunction;\n\t\tvListInitialiseItem( &( pxNewTimer->xTimerListItem ) );\n\t\tif( uxAutoReload != pdFALSE )\n\t\t{\n\t\t\tpxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;\n\t\t}\n\t\ttraceTIMER_CREATE( pxNewTimer );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )\n{\nBaseType_t xReturn = pdFAIL;\nDaemonTaskMessage_t xMessage;\n\n\tconfigASSERT( xTimer );\n\n\t/* Send a message to the timer service task to perform a particular action\n\ton a particular timer definition. */\n\tif( xTimerQueue != NULL )\n\t{\n\t\t/* Send a command to the timer service task to start the xTimer timer. */\n\t\txMessage.xMessageID = xCommandID;\n\t\txMessage.u.xTimerParameters.xMessageValue = xOptionalValue;\n\t\txMessage.u.xTimerParameters.pxTimer = xTimer;\n\n\t\tif( xCommandID < tmrFIRST_FROM_ISR_COMMAND )\n\t\t{\n\t\t\tif( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )\n\t\t\t{\n\t\t\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\n\t\t}\n\n\t\ttraceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nTaskHandle_t xTimerGetTimerDaemonTaskHandle( void )\n{\n\t/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been\n\tstarted, then xTimerTaskHandle will be NULL. */\n\tconfigASSERT( ( xTimerTaskHandle != NULL ) );\n\treturn xTimerTaskHandle;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTimerGetPeriod( TimerHandle_t xTimer )\n{\nTimer_t *pxTimer = xTimer;\n\n\tconfigASSERT( xTimer );\n\treturn pxTimer->xTimerPeriodInTicks;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )\n{\nTimer_t * pxTimer =  xTimer;\n\n\tconfigASSERT( xTimer );\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( uxAutoReload != pdFALSE )\n\t\t{\n\t\t\tpxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )\n{\nTimer_t * pxTimer =  xTimer;\nTickType_t xReturn;\n\n\tconfigASSERT( xTimer );\n\txReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nconst char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n{\nTimer_t *pxTimer = xTimer;\n\n\tconfigASSERT( xTimer );\n\treturn pxTimer->pcTimerName;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )\n{\nBaseType_t xResult;\nTimer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n\t/* Remove the timer from the list of active timers.  A check has already\n\tbeen performed to ensure the list is not empty. */\n\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\n\ttraceTIMER_EXPIRED( pxTimer );\n\n\t/* If the timer is an auto reload timer then calculate the next\n\texpiry time and re-insert the timer in the list of active timers. */\n\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )\n\t{\n\t\t/* The timer is inserted into a list using a time relative to anything\n\t\tother than the current time.  It will therefore be inserted into the\n\t\tcorrect list relative to the time this task thinks it is now. */\n\t\tif( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )\n\t\t{\n\t\t\t/* The timer expired before it was added to the active timer\n\t\t\tlist.  Reload it now.  */\n\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\n\t\t\tconfigASSERT( xResult );\n\t\t\t( void ) xResult;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\t/* Call the timer callback. */\n\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n}\n/*-----------------------------------------------------------*/\n\nstatic portTASK_FUNCTION( prvTimerTask, pvParameters )\n{\nTickType_t xNextExpireTime;\nBaseType_t xListWasEmpty;\n\n\t/* Just to avoid compiler warnings. */\n\t( void ) pvParameters;\n\n\t#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )\n\t{\n\t\textern void vApplicationDaemonTaskStartupHook( void );\n\n\t\t/* Allow the application writer to execute some code in the context of\n\t\tthis task at the point the task starts executing.  This is useful if the\n\t\tapplication includes initialisation code that would benefit from\n\t\texecuting after the scheduler has been started. */\n\t\tvApplicationDaemonTaskStartupHook();\n\t}\n\t#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */\n\n\tfor( ;; )\n\t{\n\t\t/* Query the timers list to see if it contains any timers, and if so,\n\t\tobtain the time at which the next timer will expire. */\n\t\txNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );\n\n\t\t/* If a timer has expired, process it.  Otherwise, block this task\n\t\tuntil either a timer does expire, or a command is received. */\n\t\tprvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );\n\n\t\t/* Empty the command queue. */\n\t\tprvProcessReceivedCommands();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )\n{\nTickType_t xTimeNow;\nBaseType_t xTimerListsWereSwitched;\n\n\tvTaskSuspendAll();\n\t{\n\t\t/* Obtain the time now to make an assessment as to whether the timer\n\t\thas expired or not.  If obtaining the time causes the lists to switch\n\t\tthen don't process this timer as any timers that remained in the list\n\t\twhen the lists were switched will have been processed within the\n\t\tprvSampleTimeNow() function. */\n\t\txTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\n\t\tif( xTimerListsWereSwitched == pdFALSE )\n\t\t{\n\t\t\t/* The tick count has not overflowed, has the timer expired? */\n\t\t\tif( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )\n\t\t\t{\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t\tprvProcessExpiredTimer( xNextExpireTime, xTimeNow );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The tick count has not overflowed, and the next expire\n\t\t\t\ttime has not been reached yet.  This task should therefore\n\t\t\t\tblock to wait for the next expire time or a command to be\n\t\t\t\treceived - whichever comes first.  The following line cannot\n\t\t\t\tbe reached unless xNextExpireTime > xTimeNow, except in the\n\t\t\t\tcase when the current timer list is empty. */\n\t\t\t\tif( xListWasEmpty != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The current timer list is empty - is the overflow list\n\t\t\t\t\talso empty? */\n\t\t\t\t\txListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );\n\t\t\t\t}\n\n\t\t\t\tvQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );\n\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* Yield to wait for either a command to arrive, or the\n\t\t\t\t\tblock time to expire.  If a command arrived between the\n\t\t\t\t\tcritical section being exited and this yield then the yield\n\t\t\t\t\twill not cause the task to block. */\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t( void ) xTaskResumeAll();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )\n{\nTickType_t xNextExpireTime;\n\n\t/* Timers are listed in expiry time order, with the head of the list\n\treferencing the task that will expire first.  Obtain the time at which\n\tthe timer with the nearest expiry time will expire.  If there are no\n\tactive timers then just set the next expire time to 0.  That will cause\n\tthis task to unblock when the tick count overflows, at which point the\n\ttimer lists will be switched and the next expiry time can be\n\tre-assessed.  */\n\t*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );\n\tif( *pxListWasEmpty == pdFALSE )\n\t{\n\t\txNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\n\t}\n\telse\n\t{\n\t\t/* Ensure the task unblocks when the tick count rolls over. */\n\t\txNextExpireTime = ( TickType_t ) 0U;\n\t}\n\n\treturn xNextExpireTime;\n}\n/*-----------------------------------------------------------*/\n\nstatic TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )\n{\nTickType_t xTimeNow;\nPRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */\n\n\txTimeNow = xTaskGetTickCount();\n\n\tif( xTimeNow < xLastTime )\n\t{\n\t\tprvSwitchTimerLists();\n\t\t*pxTimerListsWereSwitched = pdTRUE;\n\t}\n\telse\n\t{\n\t\t*pxTimerListsWereSwitched = pdFALSE;\n\t}\n\n\txLastTime = xTimeNow;\n\n\treturn xTimeNow;\n}\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )\n{\nBaseType_t xProcessTimerNow = pdFALSE;\n\n\tlistSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );\n\tlistSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\n\n\tif( xNextExpiryTime <= xTimeNow )\n\t{\n\t\t/* Has the expiry time elapsed between the command to start/reset a\n\t\ttimer was issued, and the time the command was processed? */\n\t\tif( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t{\n\t\t\t/* The time between a command being issued and the command being\n\t\t\tprocessed actually exceeds the timers period.  */\n\t\t\txProcessTimerNow = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tvListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );\n\t\t}\n\t}\n\telse\n\t{\n\t\tif( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )\n\t\t{\n\t\t\t/* If, since the command was issued, the tick count has overflowed\n\t\t\tbut the expiry time has not, then the timer must have already passed\n\t\t\tits expiry time and should be processed immediately. */\n\t\t\txProcessTimerNow = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tvListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\n\t\t}\n\t}\n\n\treturn xProcessTimerNow;\n}\n/*-----------------------------------------------------------*/\n\nstatic void\tprvProcessReceivedCommands( void )\n{\nDaemonTaskMessage_t xMessage;\nTimer_t *pxTimer;\nBaseType_t xTimerListsWereSwitched, xResult;\nTickType_t xTimeNow;\n\n\twhile( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */\n\t{\n\t\t#if ( INCLUDE_xTimerPendFunctionCall == 1 )\n\t\t{\n\t\t\t/* Negative commands are pended function calls rather than timer\n\t\t\tcommands. */\n\t\t\tif( xMessage.xMessageID < ( BaseType_t ) 0 )\n\t\t\t{\n\t\t\t\tconst CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );\n\n\t\t\t\t/* The timer uses the xCallbackParameters member to request a\n\t\t\t\tcallback be executed.  Check the callback is not NULL. */\n\t\t\t\tconfigASSERT( pxCallback );\n\n\t\t\t\t/* Call the function. */\n\t\t\t\tpxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* INCLUDE_xTimerPendFunctionCall */\n\n\t\t/* Commands that are positive are timer commands rather than pended\n\t\tfunction calls. */\n\t\tif( xMessage.xMessageID >= ( BaseType_t ) 0 )\n\t\t{\n\t\t\t/* The messages uses the xTimerParameters member to work on a\n\t\t\tsoftware timer. */\n\t\t\tpxTimer = xMessage.u.xTimerParameters.pxTimer;\n\n\t\t\tif( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */\n\t\t\t{\n\t\t\t\t/* The timer is in a list, remove it. */\n\t\t\t\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\ttraceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );\n\n\t\t\t/* In this case the xTimerListsWereSwitched parameter is not used, but\n\t\t\tit must be present in the function call.  prvSampleTimeNow() must be\n\t\t\tcalled after the message is received from xTimerQueue so there is no\n\t\t\tpossibility of a higher priority task adding a message to the message\n\t\t\tqueue with a time that is ahead of the timer daemon task (because it\n\t\t\tpre-empted the timer daemon task after the xTimeNow value was set). */\n\t\t\txTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\n\n\t\t\tswitch( xMessage.xMessageID )\n\t\t\t{\n\t\t\t\tcase tmrCOMMAND_START :\n\t\t\t\tcase tmrCOMMAND_START_FROM_ISR :\n\t\t\t\tcase tmrCOMMAND_RESET :\n\t\t\t\tcase tmrCOMMAND_RESET_FROM_ISR :\n\t\t\t\tcase tmrCOMMAND_START_DONT_TRACE :\n\t\t\t\t\t/* Start or restart a timer. */\n\t\t\t\t\tpxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\tif( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The timer expired before it was added to the active\n\t\t\t\t\t\ttimer list.  Process it now. */\n\t\t\t\t\t\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n\t\t\t\t\t\ttraceTIMER_EXPIRED( pxTimer );\n\n\t\t\t\t\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );\n\t\t\t\t\t\t\tconfigASSERT( xResult );\n\t\t\t\t\t\t\t( void ) xResult;\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase tmrCOMMAND_STOP :\n\t\t\t\tcase tmrCOMMAND_STOP_FROM_ISR :\n\t\t\t\t\t/* The timer has already been removed from the active list. */\n\t\t\t\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase tmrCOMMAND_CHANGE_PERIOD :\n\t\t\t\tcase tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :\n\t\t\t\t\tpxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\tpxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;\n\t\t\t\t\tconfigASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );\n\n\t\t\t\t\t/* The new period does not really have a reference, and can\n\t\t\t\t\tbe longer or shorter than the old one.  The command time is\n\t\t\t\t\ttherefore set to the current time, and as the period cannot\n\t\t\t\t\tbe zero the next expiry time can only be in the future,\n\t\t\t\t\tmeaning (unlike for the xTimerStart() case above) there is\n\t\t\t\t\tno fail case that needs to be handled here. */\n\t\t\t\t\t( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase tmrCOMMAND_DELETE :\n\t\t\t\t\t#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The timer has already been removed from the active list,\n\t\t\t\t\t\tjust free up the memory if the memory was dynamically\n\t\t\t\t\t\tallocated. */\n\t\t\t\t\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tvPortFree( pxTimer );\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\t#else\n\t\t\t\t\t{\n\t\t\t\t\t\t/* If dynamic allocation is not enabled, the memory\n\t\t\t\t\t\tcould not have been dynamically allocated. So there is\n\t\t\t\t\t\tno need to free the memory - just mark the timer as\n\t\t\t\t\t\t\"not active\". */\n\t\t\t\t\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\t}\n\t\t\t\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault\t:\n\t\t\t\t\t/* Don't expect to get here. */\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSwitchTimerLists( void )\n{\nTickType_t xNextExpireTime, xReloadTime;\nList_t *pxTemp;\nTimer_t *pxTimer;\nBaseType_t xResult;\n\n\t/* The tick count has overflowed.  The timer lists must be switched.\n\tIf there are any timers still referenced from the current timer list\n\tthen they must have expired and should be processed before the lists\n\tare switched. */\n\twhile( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )\n\t{\n\t\txNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\n\n\t\t/* Remove the timer from the list. */\n\t\tpxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\n\t\ttraceTIMER_EXPIRED( pxTimer );\n\n\t\t/* Execute its callback, then send a command to restart the timer if\n\t\tit is an auto-reload timer.  It cannot be restarted here as the lists\n\t\thave not yet been switched. */\n\t\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n\n\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )\n\t\t{\n\t\t\t/* Calculate the reload value, and if the reload value results in\n\t\t\tthe timer going into the same timer list then it has already expired\n\t\t\tand the timer should be re-inserted into the current list so it is\n\t\t\tprocessed again within this loop.  Otherwise a command should be sent\n\t\t\tto restart the timer to ensure it is only inserted into a list after\n\t\t\tthe lists have been swapped. */\n\t\t\txReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );\n\t\t\tif( xReloadTime > xNextExpireTime )\n\t\t\t{\n\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );\n\t\t\t\tlistSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\n\t\t\t\tvListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\n\t\t\t\tconfigASSERT( xResult );\n\t\t\t\t( void ) xResult;\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n\tpxTemp = pxCurrentTimerList;\n\tpxCurrentTimerList = pxOverflowTimerList;\n\tpxOverflowTimerList = pxTemp;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckForValidListAndQueue( void )\n{\n\t/* Check that the list from which active timers are referenced, and the\n\tqueue used to communicate with the timer service, have been\n\tinitialised. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( xTimerQueue == NULL )\n\t\t{\n\t\t\tvListInitialise( &xActiveTimerList1 );\n\t\t\tvListInitialise( &xActiveTimerList2 );\n\t\t\tpxCurrentTimerList = &xActiveTimerList1;\n\t\t\tpxOverflowTimerList = &xActiveTimerList2;\n\n\t\t\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* The timer queue is allocated statically in case\n\t\t\t\tconfigSUPPORT_DYNAMIC_ALLOCATION is 0. */\n\t\t\t\tstatic StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */\n\t\t\t\tstatic uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */\n\n\t\t\t\txTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );\n\t\t\t}\n\t\t\t#else\n\t\t\t{\n\t\t\t\txTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\t\t\t{\n\t\t\t\tif( xTimerQueue != NULL )\n\t\t\t\t{\n\t\t\t\t\tvQueueAddToRegistry( xTimerQueue, \"TmrQ\" );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif /* configQUEUE_REGISTRY_SIZE */\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )\n{\nBaseType_t xReturn;\nTimer_t *pxTimer = xTimer;\n\n\tconfigASSERT( xTimer );\n\n\t/* Is the timer in the list of active timers? */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n} /*lint !e818 Can't be pointer to const due to the typedef. */\n/*-----------------------------------------------------------*/\n\nvoid *pvTimerGetTimerID( const TimerHandle_t xTimer )\n{\nTimer_t * const pxTimer = xTimer;\nvoid *pvReturn;\n\n\tconfigASSERT( xTimer );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpvReturn = pxTimer->pvTimerID;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )\n{\nTimer_t * const pxTimer = xTimer;\n\n\tconfigASSERT( xTimer );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpxTimer->pvTimerID = pvNewID;\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\n#if( INCLUDE_xTimerPendFunctionCall == 1 )\n\n\tBaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )\n\t{\n\tDaemonTaskMessage_t xMessage;\n\tBaseType_t xReturn;\n\n\t\t/* Complete the message with the function parameters and post it to the\n\t\tdaemon task. */\n\t\txMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;\n\t\txMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\n\t\txMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\n\t\txMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\n\n\t\txReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\n\n\t\ttracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\n\n\t\treturn xReturn;\n\t}\n\n#endif /* INCLUDE_xTimerPendFunctionCall */\n/*-----------------------------------------------------------*/\n\n#if( INCLUDE_xTimerPendFunctionCall == 1 )\n\n\tBaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )\n\t{\n\tDaemonTaskMessage_t xMessage;\n\tBaseType_t xReturn;\n\n\t\t/* This function can only be called after a timer has been created or\n\t\tafter the scheduler has been started because, until then, the timer\n\t\tqueue does not exist. */\n\t\tconfigASSERT( xTimerQueue );\n\n\t\t/* Complete the message with the function parameters and post it to the\n\t\tdaemon task. */\n\t\txMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;\n\t\txMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\n\t\txMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\n\t\txMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\n\n\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\n\n\t\ttracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\n\n\t\treturn xReturn;\n\t}\n\n#endif /* INCLUDE_xTimerPendFunctionCall */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )\n\t{\n\t\treturn ( ( Timer_t * ) xTimer )->uxTimerNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )\n\t{\n\t\t( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n/* This entire source file will be skipped if the application is not configured\nto include software timer functionality.  If you want to include software timer\nfunctionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\n#endif /* configUSE_TIMERS == 1 */\n\n\n\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f429xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32F429xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral’s registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f429xx\n  * @{\n  */\n    \n#ifndef __STM32F429xx_H\n#define __STM32F429xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals \n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n  \n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device \n *        in @ref Library_configuration_section \n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\n  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\n  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */\n  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\n  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\n  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\n  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\n  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */\n  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\n  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */\n  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */\n  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */   \n\n/** \n  * @brief Analog to Digital Converter  \n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/** \n  * @brief Controller Area Network TxMailBox \n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/** \n  * @brief Controller Area Network FIFOMailBox \n  */\n  \ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/** \n  * @brief Controller Area Network FilterRegister \n  */\n  \ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/** \n  * @brief Controller Area Network \n  */\n  \ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ \n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/** \n  * @brief CRC calculation unit \n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/** \n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/** \n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n/** \n  * @brief DCMI\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\n} DCMI_TypeDef;\n\n/** \n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/** \n  * @brief DMA2D Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\n  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\n  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\n  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\n  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\n  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\n  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\n  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\n  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\n  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\n  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\n  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\n  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\n  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\n  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\n  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\n  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\n  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\n  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\n  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\n  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\n  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\n  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\n} DMA2D_TypeDef;\n\n/** \n  * @brief Ethernet MAC\n  */\n\ntypedef struct\n{\n  __IO uint32_t MACCR;\n  __IO uint32_t MACFFR;\n  __IO uint32_t MACHTHR;\n  __IO uint32_t MACHTLR;\n  __IO uint32_t MACMIIAR;\n  __IO uint32_t MACMIIDR;\n  __IO uint32_t MACFCR;\n  __IO uint32_t MACVLANTR;             /*    8 */\n  uint32_t      RESERVED0[2];\n  __IO uint32_t MACRWUFFR;             /*   11 */\n  __IO uint32_t MACPMTCSR;\n  uint32_t      RESERVED1;\n  __IO uint32_t MACDBGR;\n  __IO uint32_t MACSR;                 /*   15 */\n  __IO uint32_t MACIMR;\n  __IO uint32_t MACA0HR;\n  __IO uint32_t MACA0LR;\n  __IO uint32_t MACA1HR;\n  __IO uint32_t MACA1LR;\n  __IO uint32_t MACA2HR;\n  __IO uint32_t MACA2LR;\n  __IO uint32_t MACA3HR;\n  __IO uint32_t MACA3LR;               /*   24 */\n  uint32_t      RESERVED2[40];\n  __IO uint32_t MMCCR;                 /*   65 */\n  __IO uint32_t MMCRIR;\n  __IO uint32_t MMCTIR;\n  __IO uint32_t MMCRIMR;\n  __IO uint32_t MMCTIMR;               /*   69 */\n  uint32_t      RESERVED3[14];\n  __IO uint32_t MMCTGFSCCR;            /*   84 */\n  __IO uint32_t MMCTGFMSCCR;\n  uint32_t      RESERVED4[5];\n  __IO uint32_t MMCTGFCR;\n  uint32_t      RESERVED5[10];\n  __IO uint32_t MMCRFCECR;\n  __IO uint32_t MMCRFAECR;\n  uint32_t      RESERVED6[10];\n  __IO uint32_t MMCRGUFCR;\n  uint32_t      RESERVED7[334];\n  __IO uint32_t PTPTSCR;\n  __IO uint32_t PTPSSIR;\n  __IO uint32_t PTPTSHR;\n  __IO uint32_t PTPTSLR;\n  __IO uint32_t PTPTSHUR;\n  __IO uint32_t PTPTSLUR;\n  __IO uint32_t PTPTSAR;\n  __IO uint32_t PTPTTHR;\n  __IO uint32_t PTPTTLR;\n  __IO uint32_t RESERVED8;\n  __IO uint32_t PTPTSSR;\n  uint32_t      RESERVED9[565];\n  __IO uint32_t DMABMR;\n  __IO uint32_t DMATPDR;\n  __IO uint32_t DMARPDR;\n  __IO uint32_t DMARDLAR;\n  __IO uint32_t DMATDLAR;\n  __IO uint32_t DMASR;\n  __IO uint32_t DMAOMR;\n  __IO uint32_t DMAIER;\n  __IO uint32_t DMAMFBOCR;\n  __IO uint32_t DMARSWTR;\n  uint32_t      RESERVED10[8];\n  __IO uint32_t DMACHTDR;\n  __IO uint32_t DMACHRDR;\n  __IO uint32_t DMACHTBAR;\n  __IO uint32_t DMACHRBAR;\n} ETH_TypeDef;\n\n/** \n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/** \n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n/** \n  * @brief Flexible Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FMC_Bank1_TypeDef; \n\n/** \n  * @brief Flexible Memory Controller Bank1E\n  */\n  \ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FMC_Bank1E_TypeDef;\n/** \n  * @brief Flexible Memory Controller Bank2\n  */\n  \ntypedef struct\n{\n  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\n  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\n  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\n  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\n  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\n  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\n  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */\n  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */\n  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\n  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\n  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\n  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\n  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */\n  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\n} FMC_Bank2_3_TypeDef;\n\n/** \n  * @brief Flexible Memory Controller Bank4\n  */\n  \ntypedef struct\n{\n  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */\n  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */\n  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */\n  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */\n  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */\n} FMC_Bank4_TypeDef;\n\n/** \n  * @brief Flexible Memory Controller Bank5_6\n  */\n  \ntypedef struct\n{\n  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\n  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\n  __IO uint32_t SDCMR;          /*!< SDRAM Command Mode register,   Address offset: 0x150        */\n  __IO uint32_t SDRTR;          /*!< SDRAM Refresh Timer register,  Address offset: 0x154        */\n  __IO uint32_t SDSR;           /*!< SDRAM Status register,         Address offset: 0x158        */\n} FMC_Bank5_6_TypeDef;\n\n/** \n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/** \n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n} SYSCFG_TypeDef;\n\n/** \n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n  __IO uint32_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\n} I2C_TypeDef;\n\n/** \n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n/** \n  * @brief LCD-TFT Display Controller\n  */\n  \ntypedef struct\n{\n  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */\n  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */\n  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */\n  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */\n  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */\n  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */\n  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */\n  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */\n  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */\n  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */\n  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */\n  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */\n  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */\n  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\n  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */\n  __IO uint32_t CDSR;          /*!< LTDC Current Display Status Register,                Address offset: 0x48 */\n} LTDC_TypeDef;\n\n/** \n  * @brief LCD-TFT Display layer x Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */\n  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\n  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */\n  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */\n  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */\n  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */\n  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */\n  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */\n  uint32_t      RESERVED0[2];  /*!< Reserved                                                                           */\n  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */\n  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */\n  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */\n  uint32_t      RESERVED1[3];  /*!< Reserved                                                                           */\n  __IO uint32_t CLUTWR;        /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144*/\n} LTDC_Layer_TypeDef;\n\n/** \n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/** \n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */\n  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\n} RCC_TypeDef;\n\n/** \n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/** \n  * @brief Serial Audio Interface\n  */\n  \ntypedef struct\n{\n  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\n  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\n  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\n  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\n  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\n  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\n  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\n  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/** \n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/** \n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n\n/** \n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/** \n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n \ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/** \n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/** \n  * @brief RNG\n  */\n  \ntypedef struct \n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/** \n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/** \n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct \n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/** \n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct \n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/** \n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct \n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/** \n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct \n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/** \n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region                         */\n#define CCMDATARAM_BASE       0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */\n#define SRAM1_BASE            0x20000000U /*!< SRAM1(112 KB) base address in the alias region                              */\n#define SRAM2_BASE            0x2001C000U /*!< SRAM2(16 KB) base address in the alias region                              */\n#define SRAM3_BASE            0x20020000U /*!< SRAM3(64 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000U /*!< Peripheral base address in the alias region                                */\n#define BKPSRAM_BASE          0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region                         */\n#define FMC_R_BASE            0xA0000000U /*!< FMC registers base address                                                 */\n#define SRAM1_BB_BASE         0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region                           */\n#define SRAM3_BB_BASE         0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000U /*!< Peripheral base address in the bit-band region                             */\n#define BKPSRAM_BB_BASE       0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region                      */\n#define FLASH_END             0x081FFFFFU /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n#define CCMDATARAM_END        0x1000FFFFU /*!< CCM data RAM end address                                                   */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000U)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800U)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00U)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000U)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400U)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000U)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)\n#define UART7_BASE            (APB1PERIPH_BASE + 0x7800U)\n#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00U)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000U)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400U)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000U)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400U)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000U)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100U)\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200U)\n#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300U)\n/* Legacy define */\n#define ADC_BASE               ADC123_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00U)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)\n#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400U)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800U)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00U)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000U)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400U)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800U)\n#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000U)\n#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400U)\n#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800U)\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004U)\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024U)\n#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800U)\n#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84U)\n#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104U)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000U)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400U)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800U)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00U)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000U)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400U)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800U)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00U)\n#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000U)\n#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400U)\n#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800U)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800U)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00U)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000U)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010U)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028U)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040U)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058U)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070U)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088U)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0U)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8U)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400U)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010U)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028U)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040U)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058U)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070U)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088U)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0U)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8U)\n#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000U)\n#define ETH_MAC_BASE          (ETH_BASE)\n#define ETH_MMC_BASE          (ETH_BASE + 0x0100U)\n#define ETH_PTP_BASE          (ETH_BASE + 0x0700U)\n#define ETH_DMA_BASE          (ETH_BASE + 0x1000U)\n#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)\n\n/*!< AHB2 peripherals */\n#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000U)\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800U)\n\n/*!< FMC Bankx registers base address */\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)\n#define FMC_Bank2_3_R_BASE    (FMC_R_BASE + 0x0060U)\n#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0U)\n#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140U)\n\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000U\n/*!< USB registers base address */\n#define USB_OTG_HS_PERIPH_BASE               0x40040000U\n#define USB_OTG_FS_PERIPH_BASE               0x50000000U\n\n#define USB_OTG_GLOBAL_BASE                  0x000U\n#define USB_OTG_DEVICE_BASE                  0x800U\n#define USB_OTG_IN_ENDPOINT_BASE             0x900U\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00U\n#define USB_OTG_EP_REG_SIZE                  0x20U\n#define USB_OTG_HOST_BASE                    0x400U\n#define USB_OTG_HOST_PORT_BASE               0x440U\n#define USB_OTG_HOST_CHANNEL_BASE            0x500U\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20U\n#define USB_OTG_PCGCCTL_BASE                 0xE00U\n#define USB_OTG_FIFO_BASE                    0x1000U\n#define USB_OTG_FIFO_SIZE                    0x1000U\n\n#define UID_BASE                     0x1FFF7A10U           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22U           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0U           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */  \n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\n#define UART7               ((USART_TypeDef *) UART7_BASE)\n#define UART8               ((USART_TypeDef *) UART8_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC123_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\n#define SPI6                ((SPI_TypeDef *) SPI6_BASE)\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)\n#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\n#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\n#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)\n#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define ETH                 ((ETH_TypeDef *) ETH_BASE)  \n#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\n#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\n#define FMC_Bank2_3         ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)\n#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)\n#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n  \n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n    \n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)                                         \n#define ADC_SR_AWD_Msk            (0x1U << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)                                         \n#define ADC_SR_EOC_Msk            (0x1U << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)                                         \n#define ADC_SR_JEOC_Msk           (0x1U << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)                                         \n#define ADC_SR_JSTRT_Msk          (0x1U << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)                                         \n#define ADC_SR_STRT_Msk           (0x1U << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)                                         \n#define ADC_SR_OVR_Msk            (0x1U << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)                                         \n#define ADC_CR1_AWDCH_Msk         (0x1FU << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10U << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)                                         \n#define ADC_CR1_EOCIE_Msk         (0x1U << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)                                         \n#define ADC_CR1_AWDIE_Msk         (0x1U << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)                                         \n#define ADC_CR1_JEOCIE_Msk        (0x1U << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)                                         \n#define ADC_CR1_SCAN_Msk          (0x1U << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)                                         \n#define ADC_CR1_AWDSGL_Msk        (0x1U << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)                                        \n#define ADC_CR1_JAUTO_Msk         (0x1U << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)                                        \n#define ADC_CR1_DISCEN_Msk        (0x1U << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)                                        \n#define ADC_CR1_JDISCEN_Msk       (0x1U << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)                                        \n#define ADC_CR1_DISCNUM_Msk       (0x7U << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4U << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)                                        \n#define ADC_CR1_JAWDEN_Msk        (0x1U << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)                                        \n#define ADC_CR1_AWDEN_Msk         (0x1U << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)                                        \n#define ADC_CR1_RES_Msk           (0x3U << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1U << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2U << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)                                        \n#define ADC_CR1_OVRIE_Msk         (0x1U << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n  \n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)                                         \n#define ADC_CR2_ADON_Msk          (0x1U << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)                                         \n#define ADC_CR2_CONT_Msk          (0x1U << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)                                         \n#define ADC_CR2_DMA_Msk           (0x1U << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)                                         \n#define ADC_CR2_DDS_Msk           (0x1U << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)                                        \n#define ADC_CR2_EOCS_Msk          (0x1U << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)                                        \n#define ADC_CR2_ALIGN_Msk         (0x1U << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)                                        \n#define ADC_CR2_JEXTSEL_Msk       (0xFU << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8U << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)                                        \n#define ADC_CR2_JEXTEN_Msk        (0x3U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2U << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)                                        \n#define ADC_CR2_JSWSTART_Msk      (0x1U << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)                                        \n#define ADC_CR2_EXTSEL_Msk        (0xFU << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8U << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)                                        \n#define ADC_CR2_EXTEN_Msk         (0x3U << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1U << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2U << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)                                        \n#define ADC_CR2_SWSTART_Msk       (0x1U << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)                                         \n#define ADC_SMPR1_SMP10_Msk       (0x7U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4U << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)                                         \n#define ADC_SMPR1_SMP11_Msk       (0x7U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4U << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)                                         \n#define ADC_SMPR1_SMP12_Msk       (0x7U << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4U << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)                                         \n#define ADC_SMPR1_SMP13_Msk       (0x7U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4U << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)                                        \n#define ADC_SMPR1_SMP14_Msk       (0x7U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4U << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)                                        \n#define ADC_SMPR1_SMP15_Msk       (0x7U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4U << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)                                        \n#define ADC_SMPR1_SMP16_Msk       (0x7U << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4U << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)                                        \n#define ADC_SMPR1_SMP17_Msk       (0x7U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4U << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)                                        \n#define ADC_SMPR1_SMP18_Msk       (0x7U << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1U << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2U << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4U << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)                                         \n#define ADC_SMPR2_SMP0_Msk        (0x7U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4U << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)                                         \n#define ADC_SMPR2_SMP1_Msk        (0x7U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4U << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)                                         \n#define ADC_SMPR2_SMP2_Msk        (0x7U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4U << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)                                         \n#define ADC_SMPR2_SMP3_Msk        (0x7U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4U << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)                                        \n#define ADC_SMPR2_SMP4_Msk        (0x7U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4U << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)                                        \n#define ADC_SMPR2_SMP5_Msk        (0x7U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4U << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)                                        \n#define ADC_SMPR2_SMP6_Msk        (0x7U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4U << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)                                        \n#define ADC_SMPR2_SMP7_Msk        (0x7U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4U << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)                                        \n#define ADC_SMPR2_SMP8_Msk        (0x7U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4U << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)                                        \n#define ADC_SMPR2_SMP9_Msk        (0x7U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4U << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)                                         \n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFU << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)                                         \n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFU << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)                                         \n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFU << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)                                         \n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFU << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)                                         \n#define ADC_HTR_HT_Msk            (0xFFFU << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)                                         \n#define ADC_LTR_LT_Msk            (0xFFFU << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)                                         \n#define ADC_SQR1_SQ13_Msk         (0x1FU << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10U << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)                                         \n#define ADC_SQR1_SQ14_Msk         (0x1FU << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10U << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)                                        \n#define ADC_SQR1_SQ15_Msk         (0x1FU << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10U << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)                                        \n#define ADC_SQR1_SQ16_Msk         (0x1FU << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10U << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)                                        \n#define ADC_SQR1_L_Msk            (0xFU << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1U << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2U << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4U << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8U << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)                                         \n#define ADC_SQR2_SQ7_Msk          (0x1FU << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10U << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)                                         \n#define ADC_SQR2_SQ8_Msk          (0x1FU << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10U << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)                                        \n#define ADC_SQR2_SQ9_Msk          (0x1FU << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10U << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)                                        \n#define ADC_SQR2_SQ10_Msk         (0x1FU << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10U << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)                                        \n#define ADC_SQR2_SQ11_Msk         (0x1FU << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08U << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10U << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)                                        \n#define ADC_SQR2_SQ12_Msk         (0x1FU << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01U << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02U << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04U << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08U << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10U << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)                                         \n#define ADC_SQR3_SQ1_Msk          (0x1FU << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10U << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)                                         \n#define ADC_SQR3_SQ2_Msk          (0x1FU << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10U << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)                                        \n#define ADC_SQR3_SQ3_Msk          (0x1FU << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10U << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)                                        \n#define ADC_SQR3_SQ4_Msk          (0x1FU << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10U << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)                                        \n#define ADC_SQR3_SQ5_Msk          (0x1FU << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08U << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10U << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)                                        \n#define ADC_SQR3_SQ6_Msk          (0x1FU << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01U << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02U << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04U << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08U << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10U << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)                                         \n#define ADC_JSQR_JSQ1_Msk         (0x1FU << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  \n#define ADC_JSQR_JSQ1_0           (0x01U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10U << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)                                         \n#define ADC_JSQR_JSQ2_Msk         (0x1FU << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10U << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)                                        \n#define ADC_JSQR_JSQ3_Msk         (0x1FU << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10U << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)                                        \n#define ADC_JSQR_JSQ4_Msk         (0x1FU << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10U << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)                                        \n#define ADC_JSQR_JL_Msk           (0x3U << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1U << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2U << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)                                         \n#define ADC_JDR1_JDATA_Msk        (0xFFFFU << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)                                         \n#define ADC_JDR2_JDATA_Msk        (0xFFFFU << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)                                         \n#define ADC_JDR3_JDATA_Msk        (0xFFFFU << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)                                         \n#define ADC_JDR4_JDATA_Msk        (0xFFFFU << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)                                         \n#define ADC_DR_DATA_Msk           (0xFFFFU << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)                                        \n#define ADC_DR_ADC2DATA_Msk       (0xFFFFU << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)                                         \n#define ADC_CSR_AWD1_Msk          (0x1U << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)                                         \n#define ADC_CSR_EOC1_Msk          (0x1U << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)                                         \n#define ADC_CSR_JEOC1_Msk         (0x1U << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)                                         \n#define ADC_CSR_JSTRT1_Msk        (0x1U << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)                                         \n#define ADC_CSR_STRT1_Msk         (0x1U << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)                                         \n#define ADC_CSR_OVR1_Msk          (0x1U << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n#define ADC_CSR_AWD2_Pos          (8U)                                         \n#define ADC_CSR_AWD2_Msk          (0x1U << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */\n#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */\n#define ADC_CSR_EOC2_Pos          (9U)                                         \n#define ADC_CSR_EOC2_Msk          (0x1U << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */\n#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */\n#define ADC_CSR_JEOC2_Pos         (10U)                                        \n#define ADC_CSR_JEOC2_Msk         (0x1U << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */\n#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */\n#define ADC_CSR_JSTRT2_Pos        (11U)                                        \n#define ADC_CSR_JSTRT2_Msk        (0x1U << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */\n#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */\n#define ADC_CSR_STRT2_Pos         (12U)                                        \n#define ADC_CSR_STRT2_Msk         (0x1U << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */\n#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */\n#define ADC_CSR_OVR2_Pos          (13U)                                        \n#define ADC_CSR_OVR2_Msk          (0x1U << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */\n#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */\n#define ADC_CSR_AWD3_Pos          (16U)                                        \n#define ADC_CSR_AWD3_Msk          (0x1U << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */\n#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */\n#define ADC_CSR_EOC3_Pos          (17U)                                        \n#define ADC_CSR_EOC3_Msk          (0x1U << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */\n#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */\n#define ADC_CSR_JEOC3_Pos         (18U)                                        \n#define ADC_CSR_JEOC3_Msk         (0x1U << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */\n#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */\n#define ADC_CSR_JSTRT3_Pos        (19U)                                        \n#define ADC_CSR_JSTRT3_Msk        (0x1U << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */\n#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */\n#define ADC_CSR_STRT3_Pos         (20U)                                        \n#define ADC_CSR_STRT3_Msk         (0x1U << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */\n#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */\n#define ADC_CSR_OVR3_Pos          (21U)                                        \n#define ADC_CSR_OVR3_Msk          (0x1U << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */\n#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2\n#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)                                         \n#define ADC_CCR_MULTI_Msk         (0x1FU << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  \n#define ADC_CCR_MULTI_0           (0x01U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10U << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)                                         \n#define ADC_CCR_DELAY_Msk         (0xFU << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  \n#define ADC_CCR_DELAY_0           (0x1U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8U << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)                                        \n#define ADC_CCR_DDS_Msk           (0x1U << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)                                        \n#define ADC_CCR_DMA_Msk           (0x3U << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  \n#define ADC_CCR_DMA_0             (0x1U << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2U << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)                                        \n#define ADC_CCR_ADCPRE_Msk        (0x3U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */  \n#define ADC_CCR_ADCPRE_0          (0x1U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2U << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)                                        \n#define ADC_CCR_VBATE_Msk         (0x1U << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)                                        \n#define ADC_CCR_TSVREFE_Msk       (0x1U << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)                                         \n#define ADC_CDR_DATA1_Msk         (0xFFFFU << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)                                        \n#define ADC_CDR_DATA2_Msk         (0xFFFFU << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)                                            \n#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)                                            \n#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)                                            \n#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)                                            \n#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)                                            \n#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)                                            \n#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)                                            \n#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)                                            \n#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)                                           \n#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)                                           \n#define CAN_MCR_DBF_Msk        (0x1U << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)                                            \n#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)                                            \n#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)                                            \n#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)                                            \n#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)                                            \n#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)                                            \n#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)                                            \n#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)                                           \n#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)                                           \n#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)                                            \n#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)                                            \n#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)                                            \n#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)                                            \n#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)                                            \n#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)                                            \n#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)                                            \n#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)                                           \n#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)                                           \n#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)                                           \n#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)                                           \n#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)                                           \n#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)                                           \n#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)                                           \n#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)                                           \n#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)                                           \n#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)                                           \n#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)                                           \n#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)                                           \n#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)                                           \n#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)                                           \n#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)                                           \n#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)                                           \n#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)                                           \n#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)                                            \n#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)                                            \n#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)                                            \n#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)                                            \n#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)                                            \n#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)                                            \n#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)                                            \n#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)                                            \n#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)                                            \n#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)                                            \n#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)                                            \n#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)                                            \n#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)                                            \n#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)                                            \n#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)                                            \n#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)                                            \n#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)                                            \n#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)                                           \n#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)                                           \n#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)                                           \n#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)                                           \n#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)                                           \n#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)                                            \n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)                                            \n#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)                                            \n#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)                                            \n#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)                                            \n#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)                                           \n#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)                                           \n#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)                                            \n#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)                                           \n#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)                                           \n#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)                                           \n#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)                                           \n#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)                                           \n#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)                                            \n#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)                                            \n#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)                                            \n#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)                                            \n#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)                                           \n#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)                                            \n#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)                                            \n#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)                                           \n#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)                                            \n#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)                                            \n#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)                                           \n#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)                                           \n#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)                                            \n#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)                                            \n#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)                                           \n#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)                                           \n#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)                                            \n#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)                                            \n#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)                                            \n#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)                                            \n#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)                                           \n#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)                                            \n#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)                                            \n#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)                                           \n#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)                                            \n#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)                                            \n#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)                                           \n#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)                                           \n#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)                                            \n#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)                                            \n#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)                                           \n#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)                                           \n#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)                                            \n#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)                                            \n#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)                                            \n#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)                                            \n#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)                                           \n#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/  \n#define CAN_TDT2R_DLC_Pos      (0U)                                            \n#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)                                            \n#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)                                           \n#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)                                            \n#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)                                            \n#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)                                           \n#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)                                           \n#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)                                            \n#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)                                            \n#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)                                           \n#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)                                           \n#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)                                            \n#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)                                            \n#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)                                            \n#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)                                           \n#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)                                            \n#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)                                            \n#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)                                           \n#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)                                            \n#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)                                            \n#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)                                           \n#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)                                           \n#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)                                            \n#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)                                            \n#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)                                           \n#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)                                           \n#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)                                            \n#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)                                            \n#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)                                            \n#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)                                           \n#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)                                            \n#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)                                            \n#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)                                           \n#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)                                            \n#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)                                            \n#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)                                           \n#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)                                           \n#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)                                            \n#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)                                            \n#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)                                           \n#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)                                           \n#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)                                            \n#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)                                            \n#define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)                                            \n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFU << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)                                            \n#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)                                            \n#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)                                            \n#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)                                            \n#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)                                            \n#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)                                            \n#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)                                            \n#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)                                            \n#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)                                            \n#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)                                            \n#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)                                           \n#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)                                           \n#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)                                           \n#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)                                           \n#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)                                           \n#define CAN_FM1R_FBM14_Msk     (0x1U << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)                                           \n#define CAN_FM1R_FBM15_Msk     (0x1U << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)                                           \n#define CAN_FM1R_FBM16_Msk     (0x1U << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)                                           \n#define CAN_FM1R_FBM17_Msk     (0x1U << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)                                           \n#define CAN_FM1R_FBM18_Msk     (0x1U << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)                                           \n#define CAN_FM1R_FBM19_Msk     (0x1U << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)                                           \n#define CAN_FM1R_FBM20_Msk     (0x1U << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)                                           \n#define CAN_FM1R_FBM21_Msk     (0x1U << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)                                           \n#define CAN_FM1R_FBM22_Msk     (0x1U << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)                                           \n#define CAN_FM1R_FBM23_Msk     (0x1U << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)                                           \n#define CAN_FM1R_FBM24_Msk     (0x1U << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)                                           \n#define CAN_FM1R_FBM25_Msk     (0x1U << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)                                           \n#define CAN_FM1R_FBM26_Msk     (0x1U << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)                                           \n#define CAN_FM1R_FBM27_Msk     (0x1U << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)                                            \n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFU << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)                                            \n#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)                                            \n#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)                                            \n#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)                                            \n#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)                                            \n#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)                                            \n#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)                                            \n#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)                                            \n#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)                                            \n#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)                                            \n#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)                                           \n#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)                                           \n#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)                                           \n#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)                                           \n#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)                                           \n#define CAN_FS1R_FSC14_Msk     (0x1U << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)                                           \n#define CAN_FS1R_FSC15_Msk     (0x1U << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)                                           \n#define CAN_FS1R_FSC16_Msk     (0x1U << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)                                           \n#define CAN_FS1R_FSC17_Msk     (0x1U << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)                                           \n#define CAN_FS1R_FSC18_Msk     (0x1U << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)                                           \n#define CAN_FS1R_FSC19_Msk     (0x1U << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)                                           \n#define CAN_FS1R_FSC20_Msk     (0x1U << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)                                           \n#define CAN_FS1R_FSC21_Msk     (0x1U << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)                                           \n#define CAN_FS1R_FSC22_Msk     (0x1U << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)                                           \n#define CAN_FS1R_FSC23_Msk     (0x1U << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)                                           \n#define CAN_FS1R_FSC24_Msk     (0x1U << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)                                           \n#define CAN_FS1R_FSC25_Msk     (0x1U << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)                                           \n#define CAN_FS1R_FSC26_Msk     (0x1U << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)                                           \n#define CAN_FS1R_FSC27_Msk     (0x1U << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)                                            \n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFU << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)                                            \n#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)                                            \n#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)                                            \n#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)                                            \n#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)                                            \n#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)                                            \n#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)                                            \n#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)                                            \n#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)                                            \n#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)                                            \n#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)                                           \n#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)                                           \n#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)                                           \n#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)                                           \n#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)                                           \n#define CAN_FFA1R_FFA14_Msk    (0x1U << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)                                           \n#define CAN_FFA1R_FFA15_Msk    (0x1U << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)                                           \n#define CAN_FFA1R_FFA16_Msk    (0x1U << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)                                           \n#define CAN_FFA1R_FFA17_Msk    (0x1U << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)                                           \n#define CAN_FFA1R_FFA18_Msk    (0x1U << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)                                           \n#define CAN_FFA1R_FFA19_Msk    (0x1U << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)                                           \n#define CAN_FFA1R_FFA20_Msk    (0x1U << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)                                           \n#define CAN_FFA1R_FFA21_Msk    (0x1U << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)                                           \n#define CAN_FFA1R_FFA22_Msk    (0x1U << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)                                           \n#define CAN_FFA1R_FFA23_Msk    (0x1U << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)                                           \n#define CAN_FFA1R_FFA24_Msk    (0x1U << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)                                           \n#define CAN_FFA1R_FFA25_Msk    (0x1U << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)                                           \n#define CAN_FFA1R_FFA26_Msk    (0x1U << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)                                           \n#define CAN_FFA1R_FFA27_Msk    (0x1U << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)                                            \n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFU << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)                                            \n#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)                                            \n#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)                                            \n#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)                                            \n#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)                                            \n#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)                                            \n#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)                                            \n#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)                                            \n#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)                                            \n#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)                                            \n#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)                                           \n#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)                                           \n#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)                                           \n#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)                                           \n#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)                                           \n#define CAN_FA1R_FACT14_Msk    (0x1U << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)                                           \n#define CAN_FA1R_FACT15_Msk    (0x1U << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)                                           \n#define CAN_FA1R_FACT16_Msk    (0x1U << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)                                           \n#define CAN_FA1R_FACT17_Msk    (0x1U << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)                                           \n#define CAN_FA1R_FACT18_Msk    (0x1U << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)                                           \n#define CAN_FA1R_FACT19_Msk    (0x1U << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)                                           \n#define CAN_FA1R_FACT20_Msk    (0x1U << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)                                           \n#define CAN_FA1R_FACT21_Msk    (0x1U << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)                                           \n#define CAN_FA1R_FACT22_Msk    (0x1U << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)                                           \n#define CAN_FA1R_FACT23_Msk    (0x1U << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)                                           \n#define CAN_FA1R_FACT24_Msk    (0x1U << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)                                           \n#define CAN_FA1R_FACT25_Msk    (0x1U << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)                                           \n#define CAN_FA1R_FACT26_Msk    (0x1U << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)                                           \n#define CAN_FA1R_FACT27_Msk    (0x1U << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)                                            \n#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)                                            \n#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)                                            \n#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)                                            \n#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)                                            \n#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)                                            \n#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)                                            \n#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)                                            \n#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)                                            \n#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)                                            \n#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)                                           \n#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)                                           \n#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)                                           \n#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)                                           \n#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)                                           \n#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)                                           \n#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)                                           \n#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)                                           \n#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)                                           \n#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)                                           \n#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)                                           \n#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)                                           \n#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)                                           \n#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)                                           \n#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)                                           \n#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)                                           \n#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)                                           \n#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)                                           \n#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)                                           \n#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)                                           \n#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)                                           \n#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)                                           \n#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)                                            \n#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)                                            \n#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)                                            \n#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)                                            \n#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)                                            \n#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)                                            \n#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)                                            \n#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)                                            \n#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)                                            \n#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)                                            \n#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)                                           \n#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)                                           \n#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)                                           \n#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)                                           \n#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)                                           \n#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)                                           \n#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)                                           \n#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)                                           \n#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)                                           \n#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)                                           \n#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)                                           \n#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)                                           \n#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)                                           \n#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)                                           \n#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)                                           \n#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)                                           \n#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)                                           \n#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)                                           \n#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)                                           \n#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)                                           \n#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)                                           \n#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)                                           \n#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)                                            \n#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)                                            \n#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)                                            \n#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)                                            \n#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)                                            \n#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)                                            \n#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)                                            \n#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)                                            \n#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)                                            \n#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)                                            \n#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)                                           \n#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)                                           \n#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)                                           \n#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)                                           \n#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)                                           \n#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)                                           \n#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)                                           \n#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)                                           \n#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)                                           \n#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)                                           \n#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)                                           \n#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)                                           \n#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)                                           \n#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)                                           \n#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)                                           \n#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)                                           \n#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)                                           \n#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)                                           \n#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)                                           \n#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)                                           \n#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)                                           \n#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)                                           \n#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)                                            \n#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)                                            \n#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)                                            \n#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)                                            \n#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)                                            \n#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)                                            \n#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)                                            \n#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)                                            \n#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)                                            \n#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)                                            \n#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)                                           \n#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)                                           \n#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)                                           \n#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)                                           \n#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)                                           \n#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)                                           \n#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)                                           \n#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)                                           \n#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)                                           \n#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)                                           \n#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)                                           \n#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)                                           \n#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)                                           \n#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)                                           \n#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)                                           \n#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)                                           \n#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)                                           \n#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)                                           \n#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)                                           \n#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)                                           \n#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)                                           \n#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)                                           \n#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)                                            \n#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)                                            \n#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)                                            \n#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)                                            \n#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)                                            \n#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)                                            \n#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)                                            \n#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)                                            \n#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)                                            \n#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)                                            \n#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)                                           \n#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)                                           \n#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)                                           \n#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)                                           \n#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)                                           \n#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)                                           \n#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)                                           \n#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)                                           \n#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)                                           \n#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)                                           \n#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)                                           \n#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)                                           \n#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)                                           \n#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)                                           \n#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)                                           \n#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)                                           \n#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)                                           \n#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)                                           \n#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)                                           \n#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)                                           \n#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)                                           \n#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)                                           \n#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)                                            \n#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)                                            \n#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)                                            \n#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)                                            \n#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)                                            \n#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)                                            \n#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)                                            \n#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)                                            \n#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)                                            \n#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)                                            \n#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)                                           \n#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)                                           \n#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)                                           \n#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)                                           \n#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)                                           \n#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)                                           \n#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)                                           \n#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)                                           \n#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)                                           \n#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)                                           \n#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)                                           \n#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)                                           \n#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)                                           \n#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)                                           \n#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)                                           \n#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)                                           \n#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)                                           \n#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)                                           \n#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)                                           \n#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)                                           \n#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)                                           \n#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)                                           \n#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)                                            \n#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)                                            \n#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)                                            \n#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)                                            \n#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)                                            \n#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)                                            \n#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)                                            \n#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)                                            \n#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)                                            \n#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)                                            \n#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)                                           \n#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)                                           \n#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)                                           \n#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)                                           \n#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)                                           \n#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)                                           \n#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)                                           \n#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)                                           \n#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)                                           \n#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)                                           \n#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)                                           \n#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)                                           \n#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)                                           \n#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)                                           \n#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)                                           \n#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)                                           \n#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)                                           \n#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)                                           \n#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)                                           \n#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)                                           \n#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)                                           \n#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)                                           \n#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)                                            \n#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)                                            \n#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)                                            \n#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)                                            \n#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)                                            \n#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)                                            \n#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)                                            \n#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)                                            \n#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)                                            \n#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)                                            \n#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)                                           \n#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)                                           \n#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)                                           \n#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)                                           \n#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)                                           \n#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)                                           \n#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)                                           \n#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)                                           \n#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)                                           \n#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)                                           \n#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)                                           \n#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)                                           \n#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)                                           \n#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)                                           \n#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)                                           \n#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)                                           \n#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)                                           \n#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)                                           \n#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)                                           \n#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)                                           \n#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)                                           \n#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)                                           \n#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)                                            \n#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)                                            \n#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)                                            \n#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)                                            \n#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)                                            \n#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)                                            \n#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)                                            \n#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)                                            \n#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)                                            \n#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)                                            \n#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)                                           \n#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)                                           \n#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)                                           \n#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)                                           \n#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)                                           \n#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)                                           \n#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)                                           \n#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)                                           \n#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)                                           \n#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)                                           \n#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)                                           \n#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)                                           \n#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)                                           \n#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)                                           \n#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)                                           \n#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)                                           \n#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)                                           \n#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)                                           \n#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)                                           \n#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)                                           \n#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)                                           \n#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)                                           \n#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)                                            \n#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)                                            \n#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)                                            \n#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)                                            \n#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)                                            \n#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)                                            \n#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)                                            \n#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)                                            \n#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)                                            \n#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)                                            \n#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)                                           \n#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)                                           \n#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)                                           \n#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)                                           \n#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)                                           \n#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)                                           \n#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)                                           \n#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)                                           \n#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)                                           \n#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)                                           \n#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)                                           \n#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)                                           \n#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)                                           \n#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)                                           \n#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)                                           \n#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)                                           \n#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)                                           \n#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)                                           \n#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)                                           \n#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)                                           \n#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)                                           \n#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)                                           \n#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)                                            \n#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)                                            \n#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)                                            \n#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)                                            \n#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)                                            \n#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)                                            \n#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)                                            \n#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)                                            \n#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)                                            \n#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)                                            \n#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)                                           \n#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)                                           \n#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)                                           \n#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)                                           \n#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)                                           \n#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)                                           \n#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)                                           \n#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)                                           \n#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)                                           \n#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)                                           \n#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)                                           \n#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)                                           \n#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)                                           \n#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)                                           \n#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)                                           \n#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)                                           \n#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)                                           \n#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)                                           \n#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)                                           \n#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)                                           \n#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)                                           \n#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)                                           \n#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)                                            \n#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)                                            \n#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)                                            \n#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)                                            \n#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)                                            \n#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)                                            \n#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)                                            \n#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)                                            \n#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)                                            \n#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)                                            \n#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)                                           \n#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)                                           \n#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)                                           \n#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)                                           \n#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)                                           \n#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)                                           \n#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)                                           \n#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)                                           \n#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)                                           \n#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)                                           \n#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)                                           \n#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)                                           \n#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)                                           \n#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)                                           \n#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)                                           \n#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)                                           \n#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)                                           \n#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)                                           \n#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)                                           \n#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)                                           \n#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)                                           \n#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)                                           \n#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)                                            \n#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)                                            \n#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)                                            \n#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)                                            \n#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)                                            \n#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)                                            \n#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)                                            \n#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)                                            \n#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)                                            \n#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)                                            \n#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)                                           \n#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)                                           \n#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)                                           \n#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)                                           \n#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)                                           \n#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)                                           \n#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)                                           \n#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)                                           \n#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)                                           \n#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)                                           \n#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)                                           \n#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)                                           \n#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)                                           \n#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)                                           \n#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)                                           \n#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)                                           \n#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)                                           \n#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)                                           \n#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)                                           \n#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)                                           \n#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)                                           \n#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)                                           \n#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)                                            \n#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)                                            \n#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)                                            \n#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)                                            \n#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)                                            \n#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)                                            \n#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)                                            \n#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)                                            \n#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)                                            \n#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)                                            \n#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)                                           \n#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)                                           \n#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)                                           \n#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)                                           \n#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)                                           \n#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)                                           \n#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)                                           \n#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)                                           \n#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)                                           \n#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)                                           \n#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)                                           \n#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)                                           \n#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)                                           \n#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)                                           \n#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)                                           \n#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)                                           \n#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)                                           \n#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)                                           \n#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)                                           \n#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)                                           \n#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)                                           \n#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)                                           \n#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)                                            \n#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)                                            \n#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)                                            \n#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)                                            \n#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)                                            \n#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)                                            \n#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)                                            \n#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)                                            \n#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)                                            \n#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)                                            \n#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)                                           \n#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)                                           \n#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)                                           \n#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)                                           \n#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)                                           \n#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)                                           \n#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)                                           \n#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)                                           \n#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)                                           \n#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)                                           \n#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)                                           \n#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)                                           \n#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)                                           \n#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)                                           \n#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)                                           \n#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)                                           \n#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)                                           \n#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)                                           \n#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)                                           \n#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)                                           \n#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)                                           \n#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)                                           \n#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)                                            \n#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)                                            \n#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)                                            \n#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)                                            \n#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)                                            \n#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)                                            \n#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)                                            \n#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)                                            \n#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)                                            \n#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)                                            \n#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)                                           \n#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)                                           \n#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)                                           \n#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)                                           \n#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)                                           \n#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)                                           \n#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)                                           \n#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)                                           \n#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)                                           \n#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)                                           \n#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)                                           \n#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)                                           \n#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)                                           \n#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)                                           \n#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)                                           \n#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)                                           \n#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)                                           \n#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)                                           \n#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)                                           \n#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)                                           \n#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)                                           \n#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)                                           \n#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)                                            \n#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)                                            \n#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)                                            \n#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)                                            \n#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)                                            \n#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)                                            \n#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)                                            \n#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)                                            \n#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)                                            \n#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)                                            \n#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)                                           \n#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)                                           \n#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)                                           \n#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)                                           \n#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)                                           \n#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)                                           \n#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)                                           \n#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)                                           \n#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)                                           \n#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)                                           \n#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)                                           \n#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)                                           \n#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)                                           \n#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)                                           \n#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)                                           \n#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)                                           \n#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)                                           \n#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)                                           \n#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)                                           \n#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)                                           \n#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)                                           \n#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)                                           \n#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)                                            \n#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)                                            \n#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)                                            \n#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)                                            \n#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)                                            \n#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)                                            \n#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)                                            \n#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)                                            \n#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)                                            \n#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)                                            \n#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)                                           \n#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)                                           \n#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)                                           \n#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)                                           \n#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)                                           \n#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)                                           \n#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)                                           \n#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)                                           \n#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)                                           \n#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)                                           \n#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)                                           \n#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)                                           \n#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)                                           \n#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)                                           \n#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)                                           \n#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)                                           \n#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)                                           \n#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)                                           \n#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)                                           \n#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)                                           \n#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)                                           \n#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)                                           \n#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)                                            \n#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)                                            \n#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)                                            \n#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)                                            \n#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)                                            \n#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)                                            \n#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)                                            \n#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)                                            \n#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)                                            \n#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)                                            \n#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)                                           \n#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)                                           \n#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)                                           \n#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)                                           \n#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)                                           \n#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)                                           \n#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)                                           \n#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)                                           \n#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)                                           \n#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)                                           \n#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)                                           \n#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)                                           \n#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)                                           \n#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)                                           \n#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)                                           \n#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)                                           \n#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)                                           \n#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)                                           \n#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)                                           \n#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)                                           \n#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)                                           \n#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)                                           \n#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)                                            \n#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)                                            \n#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)                                            \n#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)                                            \n#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)                                            \n#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)                                            \n#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)                                            \n#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)                                            \n#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)                                            \n#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)                                            \n#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)                                           \n#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)                                           \n#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)                                           \n#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)                                           \n#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)                                           \n#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)                                           \n#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)                                           \n#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)                                           \n#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)                                           \n#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)                                           \n#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)                                           \n#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)                                           \n#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)                                           \n#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)                                           \n#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)                                           \n#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)                                           \n#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)                                           \n#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)                                           \n#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)                                           \n#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)                                           \n#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)                                           \n#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)                                           \n#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)                                            \n#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)                                            \n#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)                                            \n#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)                                            \n#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)                                            \n#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)                                            \n#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)                                            \n#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)                                            \n#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)                                            \n#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)                                            \n#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)                                           \n#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)                                           \n#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)                                           \n#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)                                           \n#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)                                           \n#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)                                           \n#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)                                           \n#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)                                           \n#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)                                           \n#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)                                           \n#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)                                           \n#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)                                           \n#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)                                           \n#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)                                           \n#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)                                           \n#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)                                           \n#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)                                           \n#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)                                           \n#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)                                           \n#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)                                           \n#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)                                           \n#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)                                           \n#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)                                            \n#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)                                            \n#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)                                            \n#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)                                            \n#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)                                            \n#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)                                            \n#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)                                            \n#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)                                            \n#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)                                            \n#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)                                            \n#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)                                           \n#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)                                           \n#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)                                           \n#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)                                           \n#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)                                           \n#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)                                           \n#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)                                           \n#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)                                           \n#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)                                           \n#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)                                           \n#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)                                           \n#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)                                           \n#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)                                           \n#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)                                           \n#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)                                           \n#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)                                           \n#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)                                           \n#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)                                           \n#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)                                           \n#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)                                           \n#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)                                           \n#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)                                           \n#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)                                            \n#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)                                            \n#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)                                            \n#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)                                            \n#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)                                            \n#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)                                            \n#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)                                            \n#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)                                            \n#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)                                            \n#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)                                            \n#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)                                           \n#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)                                           \n#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)                                           \n#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)                                           \n#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)                                           \n#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)                                           \n#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)                                           \n#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)                                           \n#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)                                           \n#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)                                           \n#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)                                           \n#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)                                           \n#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)                                           \n#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)                                           \n#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)                                           \n#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)                                           \n#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)                                           \n#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)                                           \n#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)                                           \n#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)                                           \n#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)                                           \n#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)                                           \n#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)                                            \n#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)                                            \n#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)                                            \n#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)                                            \n#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)                                            \n#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)                                            \n#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)                                            \n#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)                                            \n#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)                                            \n#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)                                            \n#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)                                           \n#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)                                           \n#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)                                           \n#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)                                           \n#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)                                           \n#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)                                           \n#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)                                           \n#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)                                           \n#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)                                           \n#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)                                           \n#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)                                           \n#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)                                           \n#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)                                           \n#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)                                           \n#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)                                           \n#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)                                           \n#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)                                           \n#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)                                           \n#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)                                           \n#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)                                           \n#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)                                           \n#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)                                           \n#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)                                            \n#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)                                            \n#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)                                            \n#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)                                            \n#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)                                            \n#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)                                            \n#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)                                            \n#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)                                            \n#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)                                            \n#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)                                            \n#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)                                           \n#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)                                           \n#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)                                           \n#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)                                           \n#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)                                           \n#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)                                           \n#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)                                           \n#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)                                           \n#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)                                           \n#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)                                           \n#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)                                           \n#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)                                           \n#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)                                           \n#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)                                           \n#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)                                           \n#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)                                           \n#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)                                           \n#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)                                           \n#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)                                           \n#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)                                           \n#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)                                           \n#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)                                           \n#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)                                            \n#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)                                            \n#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)                                            \n#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)                                            \n#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)                                            \n#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)                                            \n#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)                                            \n#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)                                            \n#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)                                            \n#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)                                            \n#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)                                           \n#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)                                           \n#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)                                           \n#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)                                           \n#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)                                           \n#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)                                           \n#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)                                           \n#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)                                           \n#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)                                           \n#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)                                           \n#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)                                           \n#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)                                           \n#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)                                           \n#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)                                           \n#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)                                           \n#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)                                           \n#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)                                           \n#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)                                           \n#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)                                           \n#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)                                           \n#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)                                           \n#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)                                           \n#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)                                            \n#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)                                            \n#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)                                            \n#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)                                            \n#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)                                            \n#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)                                            \n#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)                                            \n#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)                                            \n#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)                                            \n#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)                                            \n#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)                                           \n#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)                                           \n#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)                                           \n#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)                                           \n#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)                                           \n#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)                                           \n#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)                                           \n#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)                                           \n#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)                                           \n#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)                                           \n#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)                                           \n#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)                                           \n#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)                                           \n#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)                                           \n#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)                                           \n#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)                                           \n#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)                                           \n#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)                                           \n#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)                                           \n#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)                                           \n#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)                                           \n#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)                                           \n#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)                                            \n#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)                                            \n#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)                                            \n#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)                                            \n#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)                                            \n#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)                                            \n#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)                                            \n#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)                                            \n#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)                                            \n#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)                                            \n#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)                                           \n#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)                                           \n#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)                                           \n#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)                                           \n#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)                                           \n#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)                                           \n#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)                                           \n#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)                                           \n#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)                                           \n#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)                                           \n#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)                                           \n#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)                                           \n#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)                                           \n#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)                                           \n#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)                                           \n#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)                                           \n#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)                                           \n#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)                                           \n#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)                                           \n#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)                                           \n#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)                                           \n#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)                                           \n#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)                                               \n#define CRC_DR_DR_Msk       (0xFFFFFFFFU << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)                                               \n#define CRC_IDR_IDR_Msk     (0xFFU << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)                                               \n#define CRC_CR_RESET_Msk    (0x1U << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)                                       \n#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos            (1U)                                       \n#define DAC_CR_BOFF1_Msk            (0x1U << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos             (2U)                                       \n#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)                                       \n#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)                                       \n#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)                                       \n#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)                                      \n#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      \n#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/\n#define DAC_CR_EN2_Pos              (16U)                                      \n#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos            (17U)                                      \n#define DAC_CR_BOFF2_Msk            (0x1U << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos             (18U)                                      \n#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)                                      \n#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)                                      \n#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)                                      \n#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)                                      \n#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      \n#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       \n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       \n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       \n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       \n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       \n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       \n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       \n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       \n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       \n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      \n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       \n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      \n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       \n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       \n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       \n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       \n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)                                      \n#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_DMAUDR2_Pos          (29U)                                      \n#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    DCMI                                    */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DCMI_CR register  ******************/\n#define DCMI_CR_CAPTURE_Pos        (0U)                                        \n#define DCMI_CR_CAPTURE_Msk        (0x1U << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */\n#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk                         \n#define DCMI_CR_CM_Pos             (1U)                                        \n#define DCMI_CR_CM_Msk             (0x1U << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */\n#define DCMI_CR_CM                 DCMI_CR_CM_Msk                              \n#define DCMI_CR_CROP_Pos           (2U)                                        \n#define DCMI_CR_CROP_Msk           (0x1U << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */\n#define DCMI_CR_CROP               DCMI_CR_CROP_Msk                            \n#define DCMI_CR_JPEG_Pos           (3U)                                        \n#define DCMI_CR_JPEG_Msk           (0x1U << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */\n#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk                            \n#define DCMI_CR_ESS_Pos            (4U)                                        \n#define DCMI_CR_ESS_Msk            (0x1U << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */\n#define DCMI_CR_ESS                DCMI_CR_ESS_Msk                             \n#define DCMI_CR_PCKPOL_Pos         (5U)                                        \n#define DCMI_CR_PCKPOL_Msk         (0x1U << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */\n#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk                          \n#define DCMI_CR_HSPOL_Pos          (6U)                                        \n#define DCMI_CR_HSPOL_Msk          (0x1U << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */\n#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk                           \n#define DCMI_CR_VSPOL_Pos          (7U)                                        \n#define DCMI_CR_VSPOL_Msk          (0x1U << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */\n#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk                           \n#define DCMI_CR_FCRC_0             0x00000100U                                 \n#define DCMI_CR_FCRC_1             0x00000200U                                 \n#define DCMI_CR_EDM_0              0x00000400U                                 \n#define DCMI_CR_EDM_1              0x00000800U                                 \n#define DCMI_CR_CRE_Pos            (12U)                                       \n#define DCMI_CR_CRE_Msk            (0x1U << DCMI_CR_CRE_Pos)                   /*!< 0x00001000 */\n#define DCMI_CR_CRE                DCMI_CR_CRE_Msk                             \n#define DCMI_CR_ENABLE_Pos         (14U)                                       \n#define DCMI_CR_ENABLE_Msk         (0x1U << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */\n#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk                          \n\n/********************  Bits definition for DCMI_SR register  ******************/\n#define DCMI_SR_HSYNC_Pos          (0U)                                        \n#define DCMI_SR_HSYNC_Msk          (0x1U << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */\n#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk                           \n#define DCMI_SR_VSYNC_Pos          (1U)                                        \n#define DCMI_SR_VSYNC_Msk          (0x1U << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */\n#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk                           \n#define DCMI_SR_FNE_Pos            (2U)                                        \n#define DCMI_SR_FNE_Msk            (0x1U << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */\n#define DCMI_SR_FNE                DCMI_SR_FNE_Msk                             \n\n/********************  Bits definition for DCMI_RIS register  *****************/\n#define DCMI_RIS_FRAME_RIS_Pos     (0U)                                        \n#define DCMI_RIS_FRAME_RIS_Msk     (0x1U << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */\n#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk                      \n#define DCMI_RIS_OVR_RIS_Pos       (1U)                                        \n#define DCMI_RIS_OVR_RIS_Msk       (0x1U << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */\n#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk                        \n#define DCMI_RIS_ERR_RIS_Pos       (2U)                                        \n#define DCMI_RIS_ERR_RIS_Msk       (0x1U << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */\n#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk                        \n#define DCMI_RIS_VSYNC_RIS_Pos     (3U)                                        \n#define DCMI_RIS_VSYNC_RIS_Msk     (0x1U << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */\n#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk                      \n#define DCMI_RIS_LINE_RIS_Pos      (4U)                                        \n#define DCMI_RIS_LINE_RIS_Msk      (0x1U << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */\n#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk                       \n/* Legacy defines */\n#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS\n#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS\n#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS\n#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS\n#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS\n#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS\n\n/********************  Bits definition for DCMI_IER register  *****************/\n#define DCMI_IER_FRAME_IE_Pos      (0U)                                        \n#define DCMI_IER_FRAME_IE_Msk      (0x1U << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */\n#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk                       \n#define DCMI_IER_OVR_IE_Pos        (1U)                                        \n#define DCMI_IER_OVR_IE_Msk        (0x1U << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */\n#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk                         \n#define DCMI_IER_ERR_IE_Pos        (2U)                                        \n#define DCMI_IER_ERR_IE_Msk        (0x1U << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */\n#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk                         \n#define DCMI_IER_VSYNC_IE_Pos      (3U)                                        \n#define DCMI_IER_VSYNC_IE_Msk      (0x1U << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */\n#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk                       \n#define DCMI_IER_LINE_IE_Pos       (4U)                                        \n#define DCMI_IER_LINE_IE_Msk       (0x1U << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */\n#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk                        \n/* Legacy defines */\n#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE\n\n/********************  Bits definition for DCMI_MIS register  *****************/\n#define DCMI_MIS_FRAME_MIS_Pos     (0U)                                        \n#define DCMI_MIS_FRAME_MIS_Msk     (0x1U << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */\n#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk                      \n#define DCMI_MIS_OVR_MIS_Pos       (1U)                                        \n#define DCMI_MIS_OVR_MIS_Msk       (0x1U << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */\n#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk                        \n#define DCMI_MIS_ERR_MIS_Pos       (2U)                                        \n#define DCMI_MIS_ERR_MIS_Msk       (0x1U << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */\n#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk                        \n#define DCMI_MIS_VSYNC_MIS_Pos     (3U)                                        \n#define DCMI_MIS_VSYNC_MIS_Msk     (0x1U << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */\n#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk                      \n#define DCMI_MIS_LINE_MIS_Pos      (4U)                                        \n#define DCMI_MIS_LINE_MIS_Msk      (0x1U << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */\n#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk                       \n\n/* Legacy defines */\n#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS\n#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS\n#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS\n#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS\n#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS\n\n/********************  Bits definition for DCMI_ICR register  *****************/\n#define DCMI_ICR_FRAME_ISC_Pos     (0U)                                        \n#define DCMI_ICR_FRAME_ISC_Msk     (0x1U << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */\n#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk                      \n#define DCMI_ICR_OVR_ISC_Pos       (1U)                                        \n#define DCMI_ICR_OVR_ISC_Msk       (0x1U << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */\n#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk                        \n#define DCMI_ICR_ERR_ISC_Pos       (2U)                                        \n#define DCMI_ICR_ERR_ISC_Msk       (0x1U << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */\n#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk                        \n#define DCMI_ICR_VSYNC_ISC_Pos     (3U)                                        \n#define DCMI_ICR_VSYNC_ISC_Msk     (0x1U << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */\n#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk                      \n#define DCMI_ICR_LINE_ISC_Pos      (4U)                                        \n#define DCMI_ICR_LINE_ISC_Msk      (0x1U << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */\n#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk                       \n\n/* Legacy defines */\n#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC\n\n/********************  Bits definition for DCMI_ESCR register  ******************/\n#define DCMI_ESCR_FSC_Pos          (0U)                                        \n#define DCMI_ESCR_FSC_Msk          (0xFFU << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */\n#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk                           \n#define DCMI_ESCR_LSC_Pos          (8U)                                        \n#define DCMI_ESCR_LSC_Msk          (0xFFU << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */\n#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk                           \n#define DCMI_ESCR_LEC_Pos          (16U)                                       \n#define DCMI_ESCR_LEC_Msk          (0xFFU << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */\n#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk                           \n#define DCMI_ESCR_FEC_Pos          (24U)                                       \n#define DCMI_ESCR_FEC_Msk          (0xFFU << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */\n#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk                           \n\n/********************  Bits definition for DCMI_ESUR register  ******************/\n#define DCMI_ESUR_FSU_Pos          (0U)                                        \n#define DCMI_ESUR_FSU_Msk          (0xFFU << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */\n#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk                           \n#define DCMI_ESUR_LSU_Pos          (8U)                                        \n#define DCMI_ESUR_LSU_Msk          (0xFFU << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */\n#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk                           \n#define DCMI_ESUR_LEU_Pos          (16U)                                       \n#define DCMI_ESUR_LEU_Msk          (0xFFU << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */\n#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk                           \n#define DCMI_ESUR_FEU_Pos          (24U)                                       \n#define DCMI_ESUR_FEU_Msk          (0xFFU << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */\n#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk                           \n\n/********************  Bits definition for DCMI_CWSTRT register  ******************/\n#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)                                        \n#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */\n#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk                     \n#define DCMI_CWSTRT_VST_Pos        (16U)                                       \n#define DCMI_CWSTRT_VST_Msk        (0x1FFFU << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */\n#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk                         \n\n/********************  Bits definition for DCMI_CWSIZE register  ******************/\n#define DCMI_CWSIZE_CAPCNT_Pos     (0U)                                        \n#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */\n#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk                      \n#define DCMI_CWSIZE_VLINE_Pos      (16U)                                       \n#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFU << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */\n#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk                       \n\n/********************  Bits definition for DCMI_DR register  *********************/\n#define DCMI_DR_BYTE0_Pos          (0U)                                        \n#define DCMI_DR_BYTE0_Msk          (0xFFU << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */\n#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk                           \n#define DCMI_DR_BYTE1_Pos          (8U)                                        \n#define DCMI_DR_BYTE1_Msk          (0xFFU << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */\n#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk                           \n#define DCMI_DR_BYTE2_Pos          (16U)                                       \n#define DCMI_DR_BYTE2_Msk          (0xFFU << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */\n#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk                           \n#define DCMI_DR_BYTE3_Pos          (24U)                                       \n#define DCMI_DR_BYTE3_Msk          (0xFFU << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */\n#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk                           \n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)                                         \n#define DMA_SxCR_CHSEL_Msk       (0x7U << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk                            \n#define DMA_SxCR_CHSEL_0         0x02000000U                                   \n#define DMA_SxCR_CHSEL_1         0x04000000U                                   \n#define DMA_SxCR_CHSEL_2         0x08000000U                                   \n#define DMA_SxCR_MBURST_Pos      (23U)                                         \n#define DMA_SxCR_MBURST_Msk      (0x3U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           \n#define DMA_SxCR_MBURST_0        (0x1U << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2U << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)                                         \n#define DMA_SxCR_PBURST_Msk      (0x3U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           \n#define DMA_SxCR_PBURST_0        (0x1U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2U << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)                                         \n#define DMA_SxCR_CT_Msk          (0x1U << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               \n#define DMA_SxCR_DBM_Pos         (18U)                                         \n#define DMA_SxCR_DBM_Msk         (0x1U << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              \n#define DMA_SxCR_PL_Pos          (16U)                                         \n#define DMA_SxCR_PL_Msk          (0x3U << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               \n#define DMA_SxCR_PL_0            (0x1U << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2U << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)                                         \n#define DMA_SxCR_PINCOS_Msk      (0x1U << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           \n#define DMA_SxCR_MSIZE_Pos       (13U)                                         \n#define DMA_SxCR_MSIZE_Msk       (0x3U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            \n#define DMA_SxCR_MSIZE_0         (0x1U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2U << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)                                         \n#define DMA_SxCR_PSIZE_Msk       (0x3U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            \n#define DMA_SxCR_PSIZE_0         (0x1U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2U << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)                                         \n#define DMA_SxCR_MINC_Msk        (0x1U << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             \n#define DMA_SxCR_PINC_Pos        (9U)                                          \n#define DMA_SxCR_PINC_Msk        (0x1U << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             \n#define DMA_SxCR_CIRC_Pos        (8U)                                          \n#define DMA_SxCR_CIRC_Msk        (0x1U << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             \n#define DMA_SxCR_DIR_Pos         (6U)                                          \n#define DMA_SxCR_DIR_Msk         (0x3U << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              \n#define DMA_SxCR_DIR_0           (0x1U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2U << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)                                          \n#define DMA_SxCR_PFCTRL_Msk      (0x1U << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           \n#define DMA_SxCR_TCIE_Pos        (4U)                                          \n#define DMA_SxCR_TCIE_Msk        (0x1U << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             \n#define DMA_SxCR_HTIE_Pos        (3U)                                          \n#define DMA_SxCR_HTIE_Msk        (0x1U << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             \n#define DMA_SxCR_TEIE_Pos        (2U)                                          \n#define DMA_SxCR_TEIE_Msk        (0x1U << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             \n#define DMA_SxCR_DMEIE_Pos       (1U)                                          \n#define DMA_SxCR_DMEIE_Msk       (0x1U << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            \n#define DMA_SxCR_EN_Pos          (0U)                                          \n#define DMA_SxCR_EN_Msk          (0x1U << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               \n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)                                         \n#define DMA_SxCR_ACK_Msk         (0x1U << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk                              \n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)                                          \n#define DMA_SxNDT_Msk            (0xFFFFU << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk                                 \n#define DMA_SxNDT_0              (0x0001U << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002U << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004U << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008U << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010U << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020U << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040U << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080U << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100U << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200U << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400U << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800U << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000U << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000U << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000U << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000U << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/ \n#define DMA_SxFCR_FEIE_Pos       (7U)                                          \n#define DMA_SxFCR_FEIE_Msk       (0x1U << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            \n#define DMA_SxFCR_FS_Pos         (3U)                                          \n#define DMA_SxFCR_FS_Msk         (0x7U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              \n#define DMA_SxFCR_FS_0           (0x1U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4U << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)                                          \n#define DMA_SxFCR_DMDIS_Msk      (0x1U << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           \n#define DMA_SxFCR_FTH_Pos        (0U)                                          \n#define DMA_SxFCR_FTH_Msk        (0x3U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             \n#define DMA_SxFCR_FTH_0          (0x1U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2U << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/ \n#define DMA_LISR_TCIF3_Pos       (27U)                                         \n#define DMA_LISR_TCIF3_Msk       (0x1U << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            \n#define DMA_LISR_HTIF3_Pos       (26U)                                         \n#define DMA_LISR_HTIF3_Msk       (0x1U << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            \n#define DMA_LISR_TEIF3_Pos       (25U)                                         \n#define DMA_LISR_TEIF3_Msk       (0x1U << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            \n#define DMA_LISR_DMEIF3_Pos      (24U)                                         \n#define DMA_LISR_DMEIF3_Msk      (0x1U << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           \n#define DMA_LISR_FEIF3_Pos       (22U)                                         \n#define DMA_LISR_FEIF3_Msk       (0x1U << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            \n#define DMA_LISR_TCIF2_Pos       (21U)                                         \n#define DMA_LISR_TCIF2_Msk       (0x1U << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            \n#define DMA_LISR_HTIF2_Pos       (20U)                                         \n#define DMA_LISR_HTIF2_Msk       (0x1U << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            \n#define DMA_LISR_TEIF2_Pos       (19U)                                         \n#define DMA_LISR_TEIF2_Msk       (0x1U << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            \n#define DMA_LISR_DMEIF2_Pos      (18U)                                         \n#define DMA_LISR_DMEIF2_Msk      (0x1U << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           \n#define DMA_LISR_FEIF2_Pos       (16U)                                         \n#define DMA_LISR_FEIF2_Msk       (0x1U << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            \n#define DMA_LISR_TCIF1_Pos       (11U)                                         \n#define DMA_LISR_TCIF1_Msk       (0x1U << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            \n#define DMA_LISR_HTIF1_Pos       (10U)                                         \n#define DMA_LISR_HTIF1_Msk       (0x1U << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            \n#define DMA_LISR_TEIF1_Pos       (9U)                                          \n#define DMA_LISR_TEIF1_Msk       (0x1U << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            \n#define DMA_LISR_DMEIF1_Pos      (8U)                                          \n#define DMA_LISR_DMEIF1_Msk      (0x1U << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           \n#define DMA_LISR_FEIF1_Pos       (6U)                                          \n#define DMA_LISR_FEIF1_Msk       (0x1U << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            \n#define DMA_LISR_TCIF0_Pos       (5U)                                          \n#define DMA_LISR_TCIF0_Msk       (0x1U << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            \n#define DMA_LISR_HTIF0_Pos       (4U)                                          \n#define DMA_LISR_HTIF0_Msk       (0x1U << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            \n#define DMA_LISR_TEIF0_Pos       (3U)                                          \n#define DMA_LISR_TEIF0_Msk       (0x1U << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            \n#define DMA_LISR_DMEIF0_Pos      (2U)                                          \n#define DMA_LISR_DMEIF0_Msk      (0x1U << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           \n#define DMA_LISR_FEIF0_Pos       (0U)                                          \n#define DMA_LISR_FEIF0_Msk       (0x1U << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            \n\n/********************  Bits definition for DMA_HISR register  *****************/ \n#define DMA_HISR_TCIF7_Pos       (27U)                                         \n#define DMA_HISR_TCIF7_Msk       (0x1U << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            \n#define DMA_HISR_HTIF7_Pos       (26U)                                         \n#define DMA_HISR_HTIF7_Msk       (0x1U << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            \n#define DMA_HISR_TEIF7_Pos       (25U)                                         \n#define DMA_HISR_TEIF7_Msk       (0x1U << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            \n#define DMA_HISR_DMEIF7_Pos      (24U)                                         \n#define DMA_HISR_DMEIF7_Msk      (0x1U << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           \n#define DMA_HISR_FEIF7_Pos       (22U)                                         \n#define DMA_HISR_FEIF7_Msk       (0x1U << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            \n#define DMA_HISR_TCIF6_Pos       (21U)                                         \n#define DMA_HISR_TCIF6_Msk       (0x1U << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            \n#define DMA_HISR_HTIF6_Pos       (20U)                                         \n#define DMA_HISR_HTIF6_Msk       (0x1U << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            \n#define DMA_HISR_TEIF6_Pos       (19U)                                         \n#define DMA_HISR_TEIF6_Msk       (0x1U << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            \n#define DMA_HISR_DMEIF6_Pos      (18U)                                         \n#define DMA_HISR_DMEIF6_Msk      (0x1U << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           \n#define DMA_HISR_FEIF6_Pos       (16U)                                         \n#define DMA_HISR_FEIF6_Msk       (0x1U << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            \n#define DMA_HISR_TCIF5_Pos       (11U)                                         \n#define DMA_HISR_TCIF5_Msk       (0x1U << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            \n#define DMA_HISR_HTIF5_Pos       (10U)                                         \n#define DMA_HISR_HTIF5_Msk       (0x1U << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            \n#define DMA_HISR_TEIF5_Pos       (9U)                                          \n#define DMA_HISR_TEIF5_Msk       (0x1U << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            \n#define DMA_HISR_DMEIF5_Pos      (8U)                                          \n#define DMA_HISR_DMEIF5_Msk      (0x1U << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           \n#define DMA_HISR_FEIF5_Pos       (6U)                                          \n#define DMA_HISR_FEIF5_Msk       (0x1U << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            \n#define DMA_HISR_TCIF4_Pos       (5U)                                          \n#define DMA_HISR_TCIF4_Msk       (0x1U << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            \n#define DMA_HISR_HTIF4_Pos       (4U)                                          \n#define DMA_HISR_HTIF4_Msk       (0x1U << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            \n#define DMA_HISR_TEIF4_Pos       (3U)                                          \n#define DMA_HISR_TEIF4_Msk       (0x1U << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            \n#define DMA_HISR_DMEIF4_Pos      (2U)                                          \n#define DMA_HISR_DMEIF4_Msk      (0x1U << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           \n#define DMA_HISR_FEIF4_Pos       (0U)                                          \n#define DMA_HISR_FEIF4_Msk       (0x1U << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            \n\n/********************  Bits definition for DMA_LIFCR register  ****************/ \n#define DMA_LIFCR_CTCIF3_Pos     (27U)                                         \n#define DMA_LIFCR_CTCIF3_Msk     (0x1U << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          \n#define DMA_LIFCR_CHTIF3_Pos     (26U)                                         \n#define DMA_LIFCR_CHTIF3_Msk     (0x1U << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          \n#define DMA_LIFCR_CTEIF3_Pos     (25U)                                         \n#define DMA_LIFCR_CTEIF3_Msk     (0x1U << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          \n#define DMA_LIFCR_CDMEIF3_Pos    (24U)                                         \n#define DMA_LIFCR_CDMEIF3_Msk    (0x1U << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         \n#define DMA_LIFCR_CFEIF3_Pos     (22U)                                         \n#define DMA_LIFCR_CFEIF3_Msk     (0x1U << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          \n#define DMA_LIFCR_CTCIF2_Pos     (21U)                                         \n#define DMA_LIFCR_CTCIF2_Msk     (0x1U << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          \n#define DMA_LIFCR_CHTIF2_Pos     (20U)                                         \n#define DMA_LIFCR_CHTIF2_Msk     (0x1U << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          \n#define DMA_LIFCR_CTEIF2_Pos     (19U)                                         \n#define DMA_LIFCR_CTEIF2_Msk     (0x1U << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          \n#define DMA_LIFCR_CDMEIF2_Pos    (18U)                                         \n#define DMA_LIFCR_CDMEIF2_Msk    (0x1U << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         \n#define DMA_LIFCR_CFEIF2_Pos     (16U)                                         \n#define DMA_LIFCR_CFEIF2_Msk     (0x1U << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          \n#define DMA_LIFCR_CTCIF1_Pos     (11U)                                         \n#define DMA_LIFCR_CTCIF1_Msk     (0x1U << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          \n#define DMA_LIFCR_CHTIF1_Pos     (10U)                                         \n#define DMA_LIFCR_CHTIF1_Msk     (0x1U << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          \n#define DMA_LIFCR_CTEIF1_Pos     (9U)                                          \n#define DMA_LIFCR_CTEIF1_Msk     (0x1U << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          \n#define DMA_LIFCR_CDMEIF1_Pos    (8U)                                          \n#define DMA_LIFCR_CDMEIF1_Msk    (0x1U << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         \n#define DMA_LIFCR_CFEIF1_Pos     (6U)                                          \n#define DMA_LIFCR_CFEIF1_Msk     (0x1U << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          \n#define DMA_LIFCR_CTCIF0_Pos     (5U)                                          \n#define DMA_LIFCR_CTCIF0_Msk     (0x1U << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          \n#define DMA_LIFCR_CHTIF0_Pos     (4U)                                          \n#define DMA_LIFCR_CHTIF0_Msk     (0x1U << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          \n#define DMA_LIFCR_CTEIF0_Pos     (3U)                                          \n#define DMA_LIFCR_CTEIF0_Msk     (0x1U << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          \n#define DMA_LIFCR_CDMEIF0_Pos    (2U)                                          \n#define DMA_LIFCR_CDMEIF0_Msk    (0x1U << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         \n#define DMA_LIFCR_CFEIF0_Pos     (0U)                                          \n#define DMA_LIFCR_CFEIF0_Msk     (0x1U << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          \n\n/********************  Bits definition for DMA_HIFCR  register  ****************/ \n#define DMA_HIFCR_CTCIF7_Pos     (27U)                                         \n#define DMA_HIFCR_CTCIF7_Msk     (0x1U << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          \n#define DMA_HIFCR_CHTIF7_Pos     (26U)                                         \n#define DMA_HIFCR_CHTIF7_Msk     (0x1U << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          \n#define DMA_HIFCR_CTEIF7_Pos     (25U)                                         \n#define DMA_HIFCR_CTEIF7_Msk     (0x1U << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          \n#define DMA_HIFCR_CDMEIF7_Pos    (24U)                                         \n#define DMA_HIFCR_CDMEIF7_Msk    (0x1U << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         \n#define DMA_HIFCR_CFEIF7_Pos     (22U)                                         \n#define DMA_HIFCR_CFEIF7_Msk     (0x1U << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          \n#define DMA_HIFCR_CTCIF6_Pos     (21U)                                         \n#define DMA_HIFCR_CTCIF6_Msk     (0x1U << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          \n#define DMA_HIFCR_CHTIF6_Pos     (20U)                                         \n#define DMA_HIFCR_CHTIF6_Msk     (0x1U << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          \n#define DMA_HIFCR_CTEIF6_Pos     (19U)                                         \n#define DMA_HIFCR_CTEIF6_Msk     (0x1U << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          \n#define DMA_HIFCR_CDMEIF6_Pos    (18U)                                         \n#define DMA_HIFCR_CDMEIF6_Msk    (0x1U << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         \n#define DMA_HIFCR_CFEIF6_Pos     (16U)                                         \n#define DMA_HIFCR_CFEIF6_Msk     (0x1U << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          \n#define DMA_HIFCR_CTCIF5_Pos     (11U)                                         \n#define DMA_HIFCR_CTCIF5_Msk     (0x1U << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          \n#define DMA_HIFCR_CHTIF5_Pos     (10U)                                         \n#define DMA_HIFCR_CHTIF5_Msk     (0x1U << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          \n#define DMA_HIFCR_CTEIF5_Pos     (9U)                                          \n#define DMA_HIFCR_CTEIF5_Msk     (0x1U << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          \n#define DMA_HIFCR_CDMEIF5_Pos    (8U)                                          \n#define DMA_HIFCR_CDMEIF5_Msk    (0x1U << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         \n#define DMA_HIFCR_CFEIF5_Pos     (6U)                                          \n#define DMA_HIFCR_CFEIF5_Msk     (0x1U << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          \n#define DMA_HIFCR_CTCIF4_Pos     (5U)                                          \n#define DMA_HIFCR_CTCIF4_Msk     (0x1U << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          \n#define DMA_HIFCR_CHTIF4_Pos     (4U)                                          \n#define DMA_HIFCR_CHTIF4_Msk     (0x1U << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          \n#define DMA_HIFCR_CTEIF4_Pos     (3U)                                          \n#define DMA_HIFCR_CTEIF4_Msk     (0x1U << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          \n#define DMA_HIFCR_CDMEIF4_Pos    (2U)                                          \n#define DMA_HIFCR_CDMEIF4_Msk    (0x1U << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         \n#define DMA_HIFCR_CFEIF4_Pos     (0U)                                          \n#define DMA_HIFCR_CFEIF4_Msk     (0x1U << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          \n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)                                          \n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFU << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)                                          \n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)                                          \n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                         AHB Master DMA2D Controller (DMA2D)                */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for DMA2D_CR register  ******************/\n\n#define DMA2D_CR_START_Pos         (0U)                                        \n#define DMA2D_CR_START_Msk         (0x1U << DMA2D_CR_START_Pos)                /*!< 0x00000001 */\n#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */\n#define DMA2D_CR_SUSP_Pos          (1U)                                        \n#define DMA2D_CR_SUSP_Msk          (0x1U << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */\n#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */\n#define DMA2D_CR_ABORT_Pos         (2U)                                        \n#define DMA2D_CR_ABORT_Msk         (0x1U << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */\n#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */\n#define DMA2D_CR_TEIE_Pos          (8U)                                        \n#define DMA2D_CR_TEIE_Msk          (0x1U << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */\n#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */\n#define DMA2D_CR_TCIE_Pos          (9U)                                        \n#define DMA2D_CR_TCIE_Msk          (0x1U << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */\n#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */\n#define DMA2D_CR_TWIE_Pos          (10U)                                       \n#define DMA2D_CR_TWIE_Msk          (0x1U << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */\n#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */\n#define DMA2D_CR_CAEIE_Pos         (11U)                                       \n#define DMA2D_CR_CAEIE_Msk         (0x1U << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */\n#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */\n#define DMA2D_CR_CTCIE_Pos         (12U)                                       \n#define DMA2D_CR_CTCIE_Msk         (0x1U << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */\n#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */\n#define DMA2D_CR_CEIE_Pos          (13U)                                       \n#define DMA2D_CR_CEIE_Msk          (0x1U << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */\n#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */\n#define DMA2D_CR_MODE_Pos          (16U)                                       \n#define DMA2D_CR_MODE_Msk          (0x3U << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */\n#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */\n#define DMA2D_CR_MODE_0            (0x1U << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */\n#define DMA2D_CR_MODE_1            (0x2U << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */\n\n/********************  Bit definition for DMA2D_ISR register  *****************/\n\n#define DMA2D_ISR_TEIF_Pos         (0U)                                        \n#define DMA2D_ISR_TEIF_Msk         (0x1U << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */\n#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */\n#define DMA2D_ISR_TCIF_Pos         (1U)                                        \n#define DMA2D_ISR_TCIF_Msk         (0x1U << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */\n#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */\n#define DMA2D_ISR_TWIF_Pos         (2U)                                        \n#define DMA2D_ISR_TWIF_Msk         (0x1U << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */\n#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */\n#define DMA2D_ISR_CAEIF_Pos        (3U)                                        \n#define DMA2D_ISR_CAEIF_Msk        (0x1U << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */\n#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */\n#define DMA2D_ISR_CTCIF_Pos        (4U)                                        \n#define DMA2D_ISR_CTCIF_Msk        (0x1U << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */\n#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_ISR_CEIF_Pos         (5U)                                        \n#define DMA2D_ISR_CEIF_Msk         (0x1U << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */\n#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */\n\n/********************  Bit definition for DMA2D_IFCR register  ****************/\n\n#define DMA2D_IFCR_CTEIF_Pos       (0U)                                        \n#define DMA2D_IFCR_CTEIF_Msk       (0x1U << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */\n#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */\n#define DMA2D_IFCR_CTCIF_Pos       (1U)                                        \n#define DMA2D_IFCR_CTCIF_Msk       (0x1U << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */\n#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */\n#define DMA2D_IFCR_CTWIF_Pos       (2U)                                        \n#define DMA2D_IFCR_CTWIF_Msk       (0x1U << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */\n#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */\n#define DMA2D_IFCR_CAECIF_Pos      (3U)                                        \n#define DMA2D_IFCR_CAECIF_Msk      (0x1U << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */\n#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */\n#define DMA2D_IFCR_CCTCIF_Pos      (4U)                                        \n#define DMA2D_IFCR_CCTCIF_Msk      (0x1U << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */\n#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_IFCR_CCEIF_Pos       (5U)                                        \n#define DMA2D_IFCR_CCEIF_Msk       (0x1U << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */\n#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */\n\n/* Legacy defines */\n#define DMA2D_IFSR_CTEIF                   DMA2D_IFCR_CTEIF                     /*!< Clears Transfer Error Interrupt Flag         */\n#define DMA2D_IFSR_CTCIF                   DMA2D_IFCR_CTCIF                     /*!< Clears Transfer Complete Interrupt Flag      */\n#define DMA2D_IFSR_CTWIF                   DMA2D_IFCR_CTWIF                     /*!< Clears Transfer Watermark Interrupt Flag     */\n#define DMA2D_IFSR_CCAEIF                  DMA2D_IFCR_CAECIF                    /*!< Clears CLUT Access Error Interrupt Flag      */\n#define DMA2D_IFSR_CCTCIF                  DMA2D_IFCR_CCTCIF                    /*!< Clears CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_IFSR_CCEIF                   DMA2D_IFCR_CCEIF                     /*!< Clears Configuration Error Interrupt Flag    */\n\n/********************  Bit definition for DMA2D_FGMAR register  ***************/\n\n#define DMA2D_FGMAR_MA_Pos         (0U)                                        \n#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */\n#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_FGOR register  ****************/\n\n#define DMA2D_FGOR_LO_Pos          (0U)                                        \n#define DMA2D_FGOR_LO_Msk          (0x3FFFU << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */\n#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_BGMAR register  ***************/\n\n#define DMA2D_BGMAR_MA_Pos         (0U)                                        \n#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */\n#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_BGOR register  ****************/\n\n#define DMA2D_BGOR_LO_Pos          (0U)                                        \n#define DMA2D_BGOR_LO_Msk          (0x3FFFU << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */\n#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_FGPFCCR register  *************/\n\n#define DMA2D_FGPFCCR_CM_Pos       (0U)                                        \n#define DMA2D_FGPFCCR_CM_Msk       (0xFU << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */\n#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\n#define DMA2D_FGPFCCR_CM_0         (0x1U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_FGPFCCR_CM_1         (0x2U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_FGPFCCR_CM_2         (0x4U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_FGPFCCR_CM_3         (0x8U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */\n#define DMA2D_FGPFCCR_CCM_Pos      (4U)                                        \n#define DMA2D_FGPFCCR_CCM_Msk      (0x1U << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */\n#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\n#define DMA2D_FGPFCCR_START_Pos    (5U)                                        \n#define DMA2D_FGPFCCR_START_Msk    (0x1U << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */\n#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */\n#define DMA2D_FGPFCCR_CS_Pos       (8U)                                        \n#define DMA2D_FGPFCCR_CS_Msk       (0xFFU << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */\n#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */\n#define DMA2D_FGPFCCR_AM_Pos       (16U)                                       \n#define DMA2D_FGPFCCR_AM_Msk       (0x3U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */\n#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\n#define DMA2D_FGPFCCR_AM_0         (0x1U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */\n#define DMA2D_FGPFCCR_AM_1         (0x2U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */\n#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)                                       \n#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */\n#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */\n\n/********************  Bit definition for DMA2D_FGCOLR register  **************/\n\n#define DMA2D_FGCOLR_BLUE_Pos      (0U)                                        \n#define DMA2D_FGCOLR_BLUE_Msk      (0xFFU << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */\n#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */\n#define DMA2D_FGCOLR_GREEN_Pos     (8U)                                        \n#define DMA2D_FGCOLR_GREEN_Msk     (0xFFU << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */\n#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */\n#define DMA2D_FGCOLR_RED_Pos       (16U)                                       \n#define DMA2D_FGCOLR_RED_Msk       (0xFFU << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */\n#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */   \n\n/********************  Bit definition for DMA2D_BGPFCCR register  *************/\n\n#define DMA2D_BGPFCCR_CM_Pos       (0U)                                        \n#define DMA2D_BGPFCCR_CM_Msk       (0xFU << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */\n#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\n#define DMA2D_BGPFCCR_CM_0         (0x1U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_BGPFCCR_CM_1         (0x2U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_BGPFCCR_CM_2         (0x4U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_BGPFCCR_CM_3         0x00000008U                                 /*!< Input color mode CM bit 3 */\n#define DMA2D_BGPFCCR_CCM_Pos      (4U)                                        \n#define DMA2D_BGPFCCR_CCM_Msk      (0x1U << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */\n#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\n#define DMA2D_BGPFCCR_START_Pos    (5U)                                        \n#define DMA2D_BGPFCCR_START_Msk    (0x1U << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */\n#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */\n#define DMA2D_BGPFCCR_CS_Pos       (8U)                                        \n#define DMA2D_BGPFCCR_CS_Msk       (0xFFU << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */\n#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */\n#define DMA2D_BGPFCCR_AM_Pos       (16U)                                       \n#define DMA2D_BGPFCCR_AM_Msk       (0x3U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */\n#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\n#define DMA2D_BGPFCCR_AM_0         (0x1U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */\n#define DMA2D_BGPFCCR_AM_1         (0x2U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */\n#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)                                       \n#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */\n#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */\n\n/********************  Bit definition for DMA2D_BGCOLR register  **************/\n\n#define DMA2D_BGCOLR_BLUE_Pos      (0U)                                        \n#define DMA2D_BGCOLR_BLUE_Msk      (0xFFU << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */\n#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */\n#define DMA2D_BGCOLR_GREEN_Pos     (8U)                                        \n#define DMA2D_BGCOLR_GREEN_Msk     (0xFFU << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */\n#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */\n#define DMA2D_BGCOLR_RED_Pos       (16U)                                       \n#define DMA2D_BGCOLR_RED_Msk       (0xFFU << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */\n#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */\n\n/********************  Bit definition for DMA2D_FGCMAR register  **************/\n\n#define DMA2D_FGCMAR_MA_Pos        (0U)                                        \n#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */\n#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_BGCMAR register  **************/\n\n#define DMA2D_BGCMAR_MA_Pos        (0U)                                        \n#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */\n#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_OPFCCR register  **************/\n\n#define DMA2D_OPFCCR_CM_Pos        (0U)                                        \n#define DMA2D_OPFCCR_CM_Msk        (0x7U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */\n#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */\n#define DMA2D_OPFCCR_CM_0          (0x1U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */\n#define DMA2D_OPFCCR_CM_1          (0x2U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */\n#define DMA2D_OPFCCR_CM_2          (0x4U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */\n\n/********************  Bit definition for DMA2D_OCOLR register  ***************/\n\n/*!<Mode_ARGB8888/RGB888 */\n\n#define DMA2D_OCOLR_BLUE_1         0x000000FFU                                 /*!< BLUE Value */\n#define DMA2D_OCOLR_GREEN_1        0x0000FF00U                                 /*!< GREEN Value  */\n#define DMA2D_OCOLR_RED_1          0x00FF0000U                                 /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_1        0xFF000000U                                 /*!< Alpha Channel Value */\n\n/*!<Mode_RGB565 */\n#define DMA2D_OCOLR_BLUE_2         0x0000001FU                                 /*!< BLUE Value */\n#define DMA2D_OCOLR_GREEN_2        0x000007E0U                                 /*!< GREEN Value  */\n#define DMA2D_OCOLR_RED_2          0x0000F800U                                 /*!< Red Value */\n\n/*!<Mode_ARGB1555 */\n#define DMA2D_OCOLR_BLUE_3         0x0000001FU                                 /*!< BLUE Value */\n#define DMA2D_OCOLR_GREEN_3        0x000003E0U                                 /*!< GREEN Value  */\n#define DMA2D_OCOLR_RED_3          0x00007C00U                                 /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_3        0x00008000U                                 /*!< Alpha Channel Value */\n\n/*!<Mode_ARGB4444 */\n#define DMA2D_OCOLR_BLUE_4         0x0000000FU                                 /*!< BLUE Value */\n#define DMA2D_OCOLR_GREEN_4        0x000000F0U                                 /*!< GREEN Value  */\n#define DMA2D_OCOLR_RED_4          0x00000F00U                                 /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_4        0x0000F000U                                 /*!< Alpha Channel Value */\n\n/********************  Bit definition for DMA2D_OMAR register  ****************/\n\n#define DMA2D_OMAR_MA_Pos          (0U)                                        \n#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */\n#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_OOR register  *****************/\n\n#define DMA2D_OOR_LO_Pos           (0U)                                        \n#define DMA2D_OOR_LO_Msk           (0x3FFFU << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */\n#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_NLR register  *****************/\n\n#define DMA2D_NLR_NL_Pos           (0U)                                        \n#define DMA2D_NLR_NL_Msk           (0xFFFFU << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */\n#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */\n#define DMA2D_NLR_PL_Pos           (16U)                                       \n#define DMA2D_NLR_PL_Msk           (0x3FFFU << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */\n#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */\n\n/********************  Bit definition for DMA2D_LWR register  *****************/\n\n#define DMA2D_LWR_LW_Pos           (0U)                                        \n#define DMA2D_LWR_LW_Msk           (0xFFFFU << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */\n#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */\n\n/********************  Bit definition for DMA2D_AMTCR register  ***************/\n\n#define DMA2D_AMTCR_EN_Pos         (0U)                                        \n#define DMA2D_AMTCR_EN_Msk         (0x1U << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */\n#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */\n#define DMA2D_AMTCR_DT_Pos         (8U)                                        \n#define DMA2D_AMTCR_DT_Msk         (0xFFU << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */\n#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */\n\n/********************  Bit definition for DMA2D_FGCLUT register  **************/\n                                                                     \n/********************  Bit definition for DMA2D_BGCLUT register  **************/\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)                                         \n#define EXTI_IMR_MR0_Msk          (0x1U << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)                                         \n#define EXTI_IMR_MR1_Msk          (0x1U << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)                                         \n#define EXTI_IMR_MR2_Msk          (0x1U << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)                                         \n#define EXTI_IMR_MR3_Msk          (0x1U << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)                                         \n#define EXTI_IMR_MR4_Msk          (0x1U << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)                                         \n#define EXTI_IMR_MR5_Msk          (0x1U << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)                                         \n#define EXTI_IMR_MR6_Msk          (0x1U << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)                                         \n#define EXTI_IMR_MR7_Msk          (0x1U << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)                                         \n#define EXTI_IMR_MR8_Msk          (0x1U << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)                                         \n#define EXTI_IMR_MR9_Msk          (0x1U << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)                                        \n#define EXTI_IMR_MR10_Msk         (0x1U << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)                                        \n#define EXTI_IMR_MR11_Msk         (0x1U << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)                                        \n#define EXTI_IMR_MR12_Msk         (0x1U << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)                                        \n#define EXTI_IMR_MR13_Msk         (0x1U << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)                                        \n#define EXTI_IMR_MR14_Msk         (0x1U << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)                                        \n#define EXTI_IMR_MR15_Msk         (0x1U << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)                                        \n#define EXTI_IMR_MR16_Msk         (0x1U << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)                                        \n#define EXTI_IMR_MR17_Msk         (0x1U << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)                                        \n#define EXTI_IMR_MR18_Msk         (0x1U << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)                                        \n#define EXTI_IMR_MR19_Msk         (0x1U << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)                                        \n#define EXTI_IMR_MR20_Msk         (0x1U << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)                                        \n#define EXTI_IMR_MR21_Msk         (0x1U << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)                                        \n#define EXTI_IMR_MR22_Msk         (0x1U << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)                                         \n#define EXTI_IMR_IM_Msk           (0x7FFFFFU << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)                                         \n#define EXTI_EMR_MR0_Msk          (0x1U << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)                                         \n#define EXTI_EMR_MR1_Msk          (0x1U << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)                                         \n#define EXTI_EMR_MR2_Msk          (0x1U << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)                                         \n#define EXTI_EMR_MR3_Msk          (0x1U << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)                                         \n#define EXTI_EMR_MR4_Msk          (0x1U << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)                                         \n#define EXTI_EMR_MR5_Msk          (0x1U << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)                                         \n#define EXTI_EMR_MR6_Msk          (0x1U << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)                                         \n#define EXTI_EMR_MR7_Msk          (0x1U << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)                                         \n#define EXTI_EMR_MR8_Msk          (0x1U << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)                                         \n#define EXTI_EMR_MR9_Msk          (0x1U << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)                                        \n#define EXTI_EMR_MR10_Msk         (0x1U << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)                                        \n#define EXTI_EMR_MR11_Msk         (0x1U << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)                                        \n#define EXTI_EMR_MR12_Msk         (0x1U << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)                                        \n#define EXTI_EMR_MR13_Msk         (0x1U << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)                                        \n#define EXTI_EMR_MR14_Msk         (0x1U << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)                                        \n#define EXTI_EMR_MR15_Msk         (0x1U << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)                                        \n#define EXTI_EMR_MR16_Msk         (0x1U << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)                                        \n#define EXTI_EMR_MR17_Msk         (0x1U << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)                                        \n#define EXTI_EMR_MR18_Msk         (0x1U << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)                                        \n#define EXTI_EMR_MR19_Msk         (0x1U << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)                                        \n#define EXTI_EMR_MR20_Msk         (0x1U << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)                                        \n#define EXTI_EMR_MR21_Msk         (0x1U << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)                                        \n#define EXTI_EMR_MR22_Msk         (0x1U << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)                                         \n#define EXTI_RTSR_TR0_Msk         (0x1U << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)                                         \n#define EXTI_RTSR_TR1_Msk         (0x1U << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)                                         \n#define EXTI_RTSR_TR2_Msk         (0x1U << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)                                         \n#define EXTI_RTSR_TR3_Msk         (0x1U << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)                                         \n#define EXTI_RTSR_TR4_Msk         (0x1U << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)                                         \n#define EXTI_RTSR_TR5_Msk         (0x1U << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)                                         \n#define EXTI_RTSR_TR6_Msk         (0x1U << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)                                         \n#define EXTI_RTSR_TR7_Msk         (0x1U << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)                                         \n#define EXTI_RTSR_TR8_Msk         (0x1U << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)                                         \n#define EXTI_RTSR_TR9_Msk         (0x1U << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)                                        \n#define EXTI_RTSR_TR10_Msk        (0x1U << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)                                        \n#define EXTI_RTSR_TR11_Msk        (0x1U << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)                                        \n#define EXTI_RTSR_TR12_Msk        (0x1U << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)                                        \n#define EXTI_RTSR_TR13_Msk        (0x1U << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)                                        \n#define EXTI_RTSR_TR14_Msk        (0x1U << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)                                        \n#define EXTI_RTSR_TR15_Msk        (0x1U << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)                                        \n#define EXTI_RTSR_TR16_Msk        (0x1U << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)                                        \n#define EXTI_RTSR_TR17_Msk        (0x1U << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)                                        \n#define EXTI_RTSR_TR18_Msk        (0x1U << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)                                        \n#define EXTI_RTSR_TR19_Msk        (0x1U << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)                                        \n#define EXTI_RTSR_TR20_Msk        (0x1U << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)                                        \n#define EXTI_RTSR_TR21_Msk        (0x1U << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)                                        \n#define EXTI_RTSR_TR22_Msk        (0x1U << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)                                         \n#define EXTI_FTSR_TR0_Msk         (0x1U << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)                                         \n#define EXTI_FTSR_TR1_Msk         (0x1U << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)                                         \n#define EXTI_FTSR_TR2_Msk         (0x1U << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)                                         \n#define EXTI_FTSR_TR3_Msk         (0x1U << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)                                         \n#define EXTI_FTSR_TR4_Msk         (0x1U << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)                                         \n#define EXTI_FTSR_TR5_Msk         (0x1U << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)                                         \n#define EXTI_FTSR_TR6_Msk         (0x1U << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)                                         \n#define EXTI_FTSR_TR7_Msk         (0x1U << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)                                         \n#define EXTI_FTSR_TR8_Msk         (0x1U << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)                                         \n#define EXTI_FTSR_TR9_Msk         (0x1U << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)                                        \n#define EXTI_FTSR_TR10_Msk        (0x1U << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)                                        \n#define EXTI_FTSR_TR11_Msk        (0x1U << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)                                        \n#define EXTI_FTSR_TR12_Msk        (0x1U << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)                                        \n#define EXTI_FTSR_TR13_Msk        (0x1U << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)                                        \n#define EXTI_FTSR_TR14_Msk        (0x1U << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)                                        \n#define EXTI_FTSR_TR15_Msk        (0x1U << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)                                        \n#define EXTI_FTSR_TR16_Msk        (0x1U << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)                                        \n#define EXTI_FTSR_TR17_Msk        (0x1U << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)                                        \n#define EXTI_FTSR_TR18_Msk        (0x1U << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)                                        \n#define EXTI_FTSR_TR19_Msk        (0x1U << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)                                        \n#define EXTI_FTSR_TR20_Msk        (0x1U << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)                                        \n#define EXTI_FTSR_TR21_Msk        (0x1U << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)                                        \n#define EXTI_FTSR_TR22_Msk        (0x1U << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)                                         \n#define EXTI_SWIER_SWIER0_Msk     (0x1U << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)                                         \n#define EXTI_SWIER_SWIER1_Msk     (0x1U << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)                                         \n#define EXTI_SWIER_SWIER2_Msk     (0x1U << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)                                         \n#define EXTI_SWIER_SWIER3_Msk     (0x1U << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)                                         \n#define EXTI_SWIER_SWIER4_Msk     (0x1U << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)                                         \n#define EXTI_SWIER_SWIER5_Msk     (0x1U << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)                                         \n#define EXTI_SWIER_SWIER6_Msk     (0x1U << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)                                         \n#define EXTI_SWIER_SWIER7_Msk     (0x1U << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)                                         \n#define EXTI_SWIER_SWIER8_Msk     (0x1U << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)                                         \n#define EXTI_SWIER_SWIER9_Msk     (0x1U << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)                                        \n#define EXTI_SWIER_SWIER10_Msk    (0x1U << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)                                        \n#define EXTI_SWIER_SWIER11_Msk    (0x1U << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)                                        \n#define EXTI_SWIER_SWIER12_Msk    (0x1U << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)                                        \n#define EXTI_SWIER_SWIER13_Msk    (0x1U << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)                                        \n#define EXTI_SWIER_SWIER14_Msk    (0x1U << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)                                        \n#define EXTI_SWIER_SWIER15_Msk    (0x1U << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)                                        \n#define EXTI_SWIER_SWIER16_Msk    (0x1U << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)                                        \n#define EXTI_SWIER_SWIER17_Msk    (0x1U << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)                                        \n#define EXTI_SWIER_SWIER18_Msk    (0x1U << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)                                        \n#define EXTI_SWIER_SWIER19_Msk    (0x1U << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)                                        \n#define EXTI_SWIER_SWIER20_Msk    (0x1U << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)                                        \n#define EXTI_SWIER_SWIER21_Msk    (0x1U << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)                                        \n#define EXTI_SWIER_SWIER22_Msk    (0x1U << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)                                         \n#define EXTI_PR_PR0_Msk           (0x1U << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)                                         \n#define EXTI_PR_PR1_Msk           (0x1U << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)                                         \n#define EXTI_PR_PR2_Msk           (0x1U << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)                                         \n#define EXTI_PR_PR3_Msk           (0x1U << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)                                         \n#define EXTI_PR_PR4_Msk           (0x1U << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)                                         \n#define EXTI_PR_PR5_Msk           (0x1U << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)                                         \n#define EXTI_PR_PR6_Msk           (0x1U << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)                                         \n#define EXTI_PR_PR7_Msk           (0x1U << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)                                         \n#define EXTI_PR_PR8_Msk           (0x1U << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)                                         \n#define EXTI_PR_PR9_Msk           (0x1U << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)                                        \n#define EXTI_PR_PR10_Msk          (0x1U << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)                                        \n#define EXTI_PR_PR11_Msk          (0x1U << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)                                        \n#define EXTI_PR_PR12_Msk          (0x1U << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)                                        \n#define EXTI_PR_PR13_Msk          (0x1U << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)                                        \n#define EXTI_PR_PR14_Msk          (0x1U << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)                                        \n#define EXTI_PR_PR15_Msk          (0x1U << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)                                        \n#define EXTI_PR_PR16_Msk          (0x1U << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)                                        \n#define EXTI_PR_PR17_Msk          (0x1U << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)                                        \n#define EXTI_PR_PR18_Msk          (0x1U << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)                                        \n#define EXTI_PR_PR19_Msk          (0x1U << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)                                        \n#define EXTI_PR_PR20_Msk          (0x1U << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)                                        \n#define EXTI_PR_PR21_Msk          (0x1U << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)                                        \n#define EXTI_PR_PR22_Msk          (0x1U << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)                                    \n#define FLASH_ACR_LATENCY_Msk          (0xFU << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk                   \n#define FLASH_ACR_LATENCY_0WS          0x00000000U                             \n#define FLASH_ACR_LATENCY_1WS          0x00000001U                             \n#define FLASH_ACR_LATENCY_2WS          0x00000002U                             \n#define FLASH_ACR_LATENCY_3WS          0x00000003U                             \n#define FLASH_ACR_LATENCY_4WS          0x00000004U                             \n#define FLASH_ACR_LATENCY_5WS          0x00000005U                             \n#define FLASH_ACR_LATENCY_6WS          0x00000006U                             \n#define FLASH_ACR_LATENCY_7WS          0x00000007U                             \n\n#define FLASH_ACR_LATENCY_8WS          0x00000008U                             \n#define FLASH_ACR_LATENCY_9WS          0x00000009U                             \n#define FLASH_ACR_LATENCY_10WS         0x0000000AU                             \n#define FLASH_ACR_LATENCY_11WS         0x0000000BU                             \n#define FLASH_ACR_LATENCY_12WS         0x0000000CU                             \n#define FLASH_ACR_LATENCY_13WS         0x0000000DU                             \n#define FLASH_ACR_LATENCY_14WS         0x0000000EU                             \n#define FLASH_ACR_LATENCY_15WS         0x0000000FU                             \n#define FLASH_ACR_PRFTEN_Pos           (8U)                                    \n#define FLASH_ACR_PRFTEN_Msk           (0x1U << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk                    \n#define FLASH_ACR_ICEN_Pos             (9U)                                    \n#define FLASH_ACR_ICEN_Msk             (0x1U << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk                      \n#define FLASH_ACR_DCEN_Pos             (10U)                                   \n#define FLASH_ACR_DCEN_Msk             (0x1U << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk                      \n#define FLASH_ACR_ICRST_Pos            (11U)                                   \n#define FLASH_ACR_ICRST_Msk            (0x1U << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk                     \n#define FLASH_ACR_DCRST_Pos            (12U)                                   \n#define FLASH_ACR_DCRST_Msk            (0x1U << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk                     \n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)                                   \n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk             \n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)                                    \n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk             \n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)                                    \n#define FLASH_SR_EOP_Msk               (0x1U << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk                        \n#define FLASH_SR_SOP_Pos               (1U)                                    \n#define FLASH_SR_SOP_Msk               (0x1U << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk                        \n#define FLASH_SR_WRPERR_Pos            (4U)                                    \n#define FLASH_SR_WRPERR_Msk            (0x1U << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk                     \n#define FLASH_SR_PGAERR_Pos            (5U)                                    \n#define FLASH_SR_PGAERR_Msk            (0x1U << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk                     \n#define FLASH_SR_PGPERR_Pos            (6U)                                    \n#define FLASH_SR_PGPERR_Msk            (0x1U << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk                     \n#define FLASH_SR_PGSERR_Pos            (7U)                                    \n#define FLASH_SR_PGSERR_Msk            (0x1U << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk                     \n#define FLASH_SR_RDERR_Pos            (8U)                                    \n#define FLASH_SR_RDERR_Msk            (0x1U << FLASH_SR_RDERR_Pos)             /*!< 0x00000100 */\n#define FLASH_SR_RDERR                FLASH_SR_RDERR_Msk                     \n#define FLASH_SR_BSY_Pos               (16U)                                   \n#define FLASH_SR_BSY_Msk               (0x1U << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk                        \n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)                                    \n#define FLASH_CR_PG_Msk                (0x1U << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk                         \n#define FLASH_CR_SER_Pos               (1U)                                    \n#define FLASH_CR_SER_Msk               (0x1U << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk                        \n#define FLASH_CR_MER_Pos               (2U)                                    \n#define FLASH_CR_MER_Msk               (0x1U << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk                        \n#define FLASH_CR_MER1                        FLASH_CR_MER\n#define FLASH_CR_SNB_Pos               (3U)                                    \n#define FLASH_CR_SNB_Msk               (0x1FU << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk                        \n#define FLASH_CR_SNB_0                 (0x01U << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02U << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04U << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08U << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10U << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)                                    \n#define FLASH_CR_PSIZE_Msk             (0x3U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk                      \n#define FLASH_CR_PSIZE_0               (0x1U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2U << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_MER2_Pos              (15U)                                   \n#define FLASH_CR_MER2_Msk              (0x1U << FLASH_CR_MER2_Pos)             /*!< 0x00008000 */\n#define FLASH_CR_MER2                  FLASH_CR_MER2_Msk                       \n#define FLASH_CR_STRT_Pos              (16U)                                   \n#define FLASH_CR_STRT_Msk              (0x1U << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk                       \n#define FLASH_CR_EOPIE_Pos             (24U)                                   \n#define FLASH_CR_EOPIE_Msk             (0x1U << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk                      \n#define FLASH_CR_LOCK_Pos              (31U)                                   \n#define FLASH_CR_LOCK_Msk              (0x1U << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk                       \n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)                                    \n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1U << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk                 \n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)                                    \n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1U << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk                 \n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U                             \n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U                             \n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)                                    \n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3U << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk                 \n#define FLASH_OPTCR_BFB2_Pos           (4U)                                    \n#define FLASH_OPTCR_BFB2_Msk           (0x1U << FLASH_OPTCR_BFB2_Pos)          /*!< 0x00000010 */\n#define FLASH_OPTCR_BFB2               FLASH_OPTCR_BFB2_Msk                    \n#define FLASH_OPTCR_WDG_SW_Pos         (5U)                                    \n#define FLASH_OPTCR_WDG_SW_Msk         (0x1U << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk                  \n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)                                    \n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1U << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk               \n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)                                    \n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1U << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk              \n#define FLASH_OPTCR_RDP_Pos            (8U)                                    \n#define FLASH_OPTCR_RDP_Msk            (0xFFU << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk                     \n#define FLASH_OPTCR_RDP_0              (0x01U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80U << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)                                   \n#define FLASH_OPTCR_nWRP_Msk           (0xFFFU << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk                    \n#define FLASH_OPTCR_nWRP_0             0x00010000U                             \n#define FLASH_OPTCR_nWRP_1             0x00020000U                             \n#define FLASH_OPTCR_nWRP_2             0x00040000U                             \n#define FLASH_OPTCR_nWRP_3             0x00080000U                             \n#define FLASH_OPTCR_nWRP_4             0x00100000U                             \n#define FLASH_OPTCR_nWRP_5             0x00200000U                             \n#define FLASH_OPTCR_nWRP_6             0x00400000U                             \n#define FLASH_OPTCR_nWRP_7             0x00800000U                             \n#define FLASH_OPTCR_nWRP_8             0x01000000U                             \n#define FLASH_OPTCR_nWRP_9             0x02000000U                             \n#define FLASH_OPTCR_nWRP_10            0x04000000U                             \n#define FLASH_OPTCR_nWRP_11            0x08000000U                             \n#define FLASH_OPTCR_DB1M_Pos           (30U)                                   \n#define FLASH_OPTCR_DB1M_Msk           (0x1U << FLASH_OPTCR_DB1M_Pos)          /*!< 0x40000000 */\n#define FLASH_OPTCR_DB1M               FLASH_OPTCR_DB1M_Msk                    \n#define FLASH_OPTCR_SPRMOD_Pos         (31U)                                   \n#define FLASH_OPTCR_SPRMOD_Msk         (0x1U << FLASH_OPTCR_SPRMOD_Pos)        /*!< 0x80000000 */\n#define FLASH_OPTCR_SPRMOD             FLASH_OPTCR_SPRMOD_Msk                  \n                                             \n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)                                   \n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFU << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk                   \n#define FLASH_OPTCR1_nWRP_0            (0x001U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800U << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Flexible Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FMC_BCR1 register  *******************/\n#define FMC_BCR1_MBKEN_Pos          (0U)                                       \n#define FMC_BCR1_MBKEN_Msk          (0x1U << FMC_BCR1_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR1_MBKEN              FMC_BCR1_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR1_MUXEN_Pos          (1U)                                       \n#define FMC_BCR1_MUXEN_Msk          (0x1U << FMC_BCR1_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR1_MUXEN              FMC_BCR1_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR1_MTYP_Pos           (2U)                                       \n#define FMC_BCR1_MTYP_Msk           (0x3U << FMC_BCR1_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR1_MTYP               FMC_BCR1_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR1_MTYP_0             (0x1U << FMC_BCR1_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR1_MTYP_1             (0x2U << FMC_BCR1_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR1_MWID_Pos           (4U)                                       \n#define FMC_BCR1_MWID_Msk           (0x3U << FMC_BCR1_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR1_MWID               FMC_BCR1_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR1_MWID_0             (0x1U << FMC_BCR1_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR1_MWID_1             (0x2U << FMC_BCR1_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR1_FACCEN_Pos         (6U)                                       \n#define FMC_BCR1_FACCEN_Msk         (0x1U << FMC_BCR1_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR1_FACCEN             FMC_BCR1_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR1_BURSTEN_Pos        (8U)                                       \n#define FMC_BCR1_BURSTEN_Msk        (0x1U << FMC_BCR1_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR1_BURSTEN            FMC_BCR1_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR1_WAITPOL_Pos        (9U)                                       \n#define FMC_BCR1_WAITPOL_Msk        (0x1U << FMC_BCR1_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR1_WAITPOL            FMC_BCR1_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR1_WRAPMOD_Pos        (10U)                                      \n#define FMC_BCR1_WRAPMOD_Msk        (0x1U << FMC_BCR1_WRAPMOD_Pos)             /*!< 0x00000400 */\n#define FMC_BCR1_WRAPMOD            FMC_BCR1_WRAPMOD_Msk                       /*!<Wrapped burst mode support */\n#define FMC_BCR1_WAITCFG_Pos        (11U)                                      \n#define FMC_BCR1_WAITCFG_Msk        (0x1U << FMC_BCR1_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR1_WAITCFG            FMC_BCR1_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR1_WREN_Pos           (12U)                                      \n#define FMC_BCR1_WREN_Msk           (0x1U << FMC_BCR1_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR1_WREN               FMC_BCR1_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR1_WAITEN_Pos         (13U)                                      \n#define FMC_BCR1_WAITEN_Msk         (0x1U << FMC_BCR1_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR1_WAITEN             FMC_BCR1_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR1_EXTMOD_Pos         (14U)                                      \n#define FMC_BCR1_EXTMOD_Msk         (0x1U << FMC_BCR1_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR1_EXTMOD             FMC_BCR1_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR1_ASYNCWAIT_Pos      (15U)                                      \n#define FMC_BCR1_ASYNCWAIT_Msk      (0x1U << FMC_BCR1_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR1_ASYNCWAIT          FMC_BCR1_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR1_CPSIZE_Pos         (16U)                                      \n#define FMC_BCR1_CPSIZE_Msk         (0x7U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00070000 */\n#define FMC_BCR1_CPSIZE             FMC_BCR1_CPSIZE_Msk                        /*!<CRAM page size             */\n#define FMC_BCR1_CPSIZE_0           (0x1U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00010000 */\n#define FMC_BCR1_CPSIZE_1           (0x2U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00020000 */\n#define FMC_BCR1_CPSIZE_2           (0x4U << FMC_BCR1_CPSIZE_Pos)              /*!< 0x00040000 */\n#define FMC_BCR1_CBURSTRW_Pos       (19U)                                      \n#define FMC_BCR1_CBURSTRW_Msk       (0x1U << FMC_BCR1_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR1_CBURSTRW           FMC_BCR1_CBURSTRW_Msk                      /*!<Write burst enable         */\n#define FMC_BCR1_CCLKEN_Pos         (20U)                                      \n#define FMC_BCR1_CCLKEN_Msk         (0x1U << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */\n#define FMC_BCR1_CCLKEN             FMC_BCR1_CCLKEN_Msk                        /*!<Continous clock enable     */\n\n/******************  Bit definition for FMC_BCR2 register  *******************/\n#define FMC_BCR2_MBKEN_Pos          (0U)                                       \n#define FMC_BCR2_MBKEN_Msk          (0x1U << FMC_BCR2_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR2_MBKEN              FMC_BCR2_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR2_MUXEN_Pos          (1U)                                       \n#define FMC_BCR2_MUXEN_Msk          (0x1U << FMC_BCR2_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR2_MUXEN              FMC_BCR2_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR2_MTYP_Pos           (2U)                                       \n#define FMC_BCR2_MTYP_Msk           (0x3U << FMC_BCR2_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR2_MTYP               FMC_BCR2_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR2_MTYP_0             (0x1U << FMC_BCR2_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR2_MTYP_1             (0x2U << FMC_BCR2_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR2_MWID_Pos           (4U)                                       \n#define FMC_BCR2_MWID_Msk           (0x3U << FMC_BCR2_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR2_MWID               FMC_BCR2_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR2_MWID_0             (0x1U << FMC_BCR2_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR2_MWID_1             (0x2U << FMC_BCR2_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR2_FACCEN_Pos         (6U)                                       \n#define FMC_BCR2_FACCEN_Msk         (0x1U << FMC_BCR2_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR2_FACCEN             FMC_BCR2_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR2_BURSTEN_Pos        (8U)                                       \n#define FMC_BCR2_BURSTEN_Msk        (0x1U << FMC_BCR2_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR2_BURSTEN            FMC_BCR2_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR2_WAITPOL_Pos        (9U)                                       \n#define FMC_BCR2_WAITPOL_Msk        (0x1U << FMC_BCR2_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR2_WAITPOL            FMC_BCR2_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR2_WRAPMOD_Pos        (10U)                                      \n#define FMC_BCR2_WRAPMOD_Msk        (0x1U << FMC_BCR2_WRAPMOD_Pos)             /*!< 0x00000400 */\n#define FMC_BCR2_WRAPMOD            FMC_BCR2_WRAPMOD_Msk                       /*!<Wrapped burst mode support */\n#define FMC_BCR2_WAITCFG_Pos        (11U)                                      \n#define FMC_BCR2_WAITCFG_Msk        (0x1U << FMC_BCR2_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR2_WAITCFG            FMC_BCR2_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR2_WREN_Pos           (12U)                                      \n#define FMC_BCR2_WREN_Msk           (0x1U << FMC_BCR2_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR2_WREN               FMC_BCR2_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR2_WAITEN_Pos         (13U)                                      \n#define FMC_BCR2_WAITEN_Msk         (0x1U << FMC_BCR2_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR2_WAITEN             FMC_BCR2_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR2_EXTMOD_Pos         (14U)                                      \n#define FMC_BCR2_EXTMOD_Msk         (0x1U << FMC_BCR2_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR2_EXTMOD             FMC_BCR2_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR2_ASYNCWAIT_Pos      (15U)                                      \n#define FMC_BCR2_ASYNCWAIT_Msk      (0x1U << FMC_BCR2_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR2_ASYNCWAIT          FMC_BCR2_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR2_CPSIZE_Pos         (16U)                                      \n#define FMC_BCR2_CPSIZE_Msk         (0x7U << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00070000 */\n#define FMC_BCR2_CPSIZE             FMC_BCR2_CPSIZE_Msk                        /*!<CRAM page size */\n#define FMC_BCR2_CPSIZE_0           (0x1U << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00010000 */\n#define FMC_BCR2_CPSIZE_1           (0x2U << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00020000 */\n#define FMC_BCR2_CPSIZE_2           (0x4U << FMC_BCR2_CPSIZE_Pos)              /*!< 0x00040000 */\n#define FMC_BCR2_CBURSTRW_Pos       (19U)                                      \n#define FMC_BCR2_CBURSTRW_Msk       (0x1U << FMC_BCR2_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR2_CBURSTRW           FMC_BCR2_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BCR3 register  *******************/\n#define FMC_BCR3_MBKEN_Pos          (0U)                                       \n#define FMC_BCR3_MBKEN_Msk          (0x1U << FMC_BCR3_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR3_MBKEN              FMC_BCR3_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR3_MUXEN_Pos          (1U)                                       \n#define FMC_BCR3_MUXEN_Msk          (0x1U << FMC_BCR3_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR3_MUXEN              FMC_BCR3_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR3_MTYP_Pos           (2U)                                       \n#define FMC_BCR3_MTYP_Msk           (0x3U << FMC_BCR3_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR3_MTYP               FMC_BCR3_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR3_MTYP_0             (0x1U << FMC_BCR3_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR3_MTYP_1             (0x2U << FMC_BCR3_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR3_MWID_Pos           (4U)                                       \n#define FMC_BCR3_MWID_Msk           (0x3U << FMC_BCR3_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR3_MWID               FMC_BCR3_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR3_MWID_0             (0x1U << FMC_BCR3_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR3_MWID_1             (0x2U << FMC_BCR3_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR3_FACCEN_Pos         (6U)                                       \n#define FMC_BCR3_FACCEN_Msk         (0x1U << FMC_BCR3_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR3_FACCEN             FMC_BCR3_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR3_BURSTEN_Pos        (8U)                                       \n#define FMC_BCR3_BURSTEN_Msk        (0x1U << FMC_BCR3_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR3_BURSTEN            FMC_BCR3_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR3_WAITPOL_Pos        (9U)                                       \n#define FMC_BCR3_WAITPOL_Msk        (0x1U << FMC_BCR3_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR3_WAITPOL            FMC_BCR3_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR3_WRAPMOD_Pos        (10U)                                      \n#define FMC_BCR3_WRAPMOD_Msk        (0x1U << FMC_BCR3_WRAPMOD_Pos)             /*!< 0x00000400 */\n#define FMC_BCR3_WRAPMOD            FMC_BCR3_WRAPMOD_Msk                       /*!<Wrapped burst mode support */\n#define FMC_BCR3_WAITCFG_Pos        (11U)                                      \n#define FMC_BCR3_WAITCFG_Msk        (0x1U << FMC_BCR3_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR3_WAITCFG            FMC_BCR3_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR3_WREN_Pos           (12U)                                      \n#define FMC_BCR3_WREN_Msk           (0x1U << FMC_BCR3_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR3_WREN               FMC_BCR3_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR3_WAITEN_Pos         (13U)                                      \n#define FMC_BCR3_WAITEN_Msk         (0x1U << FMC_BCR3_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR3_WAITEN             FMC_BCR3_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR3_EXTMOD_Pos         (14U)                                      \n#define FMC_BCR3_EXTMOD_Msk         (0x1U << FMC_BCR3_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR3_EXTMOD             FMC_BCR3_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR3_ASYNCWAIT_Pos      (15U)                                      \n#define FMC_BCR3_ASYNCWAIT_Msk      (0x1U << FMC_BCR3_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR3_ASYNCWAIT          FMC_BCR3_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR3_CPSIZE_Pos         (16U)                                      \n#define FMC_BCR3_CPSIZE_Msk         (0x7U << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00070000 */\n#define FMC_BCR3_CPSIZE             FMC_BCR3_CPSIZE_Msk                        /*!<CRAM page size */\n#define FMC_BCR3_CPSIZE_0           (0x1U << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00010000 */\n#define FMC_BCR3_CPSIZE_1           (0x2U << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00020000 */\n#define FMC_BCR3_CPSIZE_2           (0x4U << FMC_BCR3_CPSIZE_Pos)              /*!< 0x00040000 */\n#define FMC_BCR3_CBURSTRW_Pos       (19U)                                      \n#define FMC_BCR3_CBURSTRW_Msk       (0x1U << FMC_BCR3_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR3_CBURSTRW           FMC_BCR3_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BCR4 register  *******************/\n#define FMC_BCR4_MBKEN_Pos          (0U)                                       \n#define FMC_BCR4_MBKEN_Msk          (0x1U << FMC_BCR4_MBKEN_Pos)               /*!< 0x00000001 */\n#define FMC_BCR4_MBKEN              FMC_BCR4_MBKEN_Msk                         /*!<Memory bank enable bit                 */\n#define FMC_BCR4_MUXEN_Pos          (1U)                                       \n#define FMC_BCR4_MUXEN_Msk          (0x1U << FMC_BCR4_MUXEN_Pos)               /*!< 0x00000002 */\n#define FMC_BCR4_MUXEN              FMC_BCR4_MUXEN_Msk                         /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCR4_MTYP_Pos           (2U)                                       \n#define FMC_BCR4_MTYP_Msk           (0x3U << FMC_BCR4_MTYP_Pos)                /*!< 0x0000000C */\n#define FMC_BCR4_MTYP               FMC_BCR4_MTYP_Msk                          /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCR4_MTYP_0             (0x1U << FMC_BCR4_MTYP_Pos)                /*!< 0x00000004 */\n#define FMC_BCR4_MTYP_1             (0x2U << FMC_BCR4_MTYP_Pos)                /*!< 0x00000008 */\n\n#define FMC_BCR4_MWID_Pos           (4U)                                       \n#define FMC_BCR4_MWID_Msk           (0x3U << FMC_BCR4_MWID_Pos)                /*!< 0x00000030 */\n#define FMC_BCR4_MWID               FMC_BCR4_MWID_Msk                          /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCR4_MWID_0             (0x1U << FMC_BCR4_MWID_Pos)                /*!< 0x00000010 */\n#define FMC_BCR4_MWID_1             (0x2U << FMC_BCR4_MWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_BCR4_FACCEN_Pos         (6U)                                       \n#define FMC_BCR4_FACCEN_Msk         (0x1U << FMC_BCR4_FACCEN_Pos)              /*!< 0x00000040 */\n#define FMC_BCR4_FACCEN             FMC_BCR4_FACCEN_Msk                        /*!<Flash access enable        */\n#define FMC_BCR4_BURSTEN_Pos        (8U)                                       \n#define FMC_BCR4_BURSTEN_Msk        (0x1U << FMC_BCR4_BURSTEN_Pos)             /*!< 0x00000100 */\n#define FMC_BCR4_BURSTEN            FMC_BCR4_BURSTEN_Msk                       /*!<Burst enable bit           */\n#define FMC_BCR4_WAITPOL_Pos        (9U)                                       \n#define FMC_BCR4_WAITPOL_Msk        (0x1U << FMC_BCR4_WAITPOL_Pos)             /*!< 0x00000200 */\n#define FMC_BCR4_WAITPOL            FMC_BCR4_WAITPOL_Msk                       /*!<Wait signal polarity bit   */\n#define FMC_BCR4_WRAPMOD_Pos        (10U)                                      \n#define FMC_BCR4_WRAPMOD_Msk        (0x1U << FMC_BCR4_WRAPMOD_Pos)             /*!< 0x00000400 */\n#define FMC_BCR4_WRAPMOD            FMC_BCR4_WRAPMOD_Msk                       /*!<Wrapped burst mode support */\n#define FMC_BCR4_WAITCFG_Pos        (11U)                                      \n#define FMC_BCR4_WAITCFG_Msk        (0x1U << FMC_BCR4_WAITCFG_Pos)             /*!< 0x00000800 */\n#define FMC_BCR4_WAITCFG            FMC_BCR4_WAITCFG_Msk                       /*!<Wait timing configuration  */\n#define FMC_BCR4_WREN_Pos           (12U)                                      \n#define FMC_BCR4_WREN_Msk           (0x1U << FMC_BCR4_WREN_Pos)                /*!< 0x00001000 */\n#define FMC_BCR4_WREN               FMC_BCR4_WREN_Msk                          /*!<Write enable bit           */\n#define FMC_BCR4_WAITEN_Pos         (13U)                                      \n#define FMC_BCR4_WAITEN_Msk         (0x1U << FMC_BCR4_WAITEN_Pos)              /*!< 0x00002000 */\n#define FMC_BCR4_WAITEN             FMC_BCR4_WAITEN_Msk                        /*!<Wait enable bit            */\n#define FMC_BCR4_EXTMOD_Pos         (14U)                                      \n#define FMC_BCR4_EXTMOD_Msk         (0x1U << FMC_BCR4_EXTMOD_Pos)              /*!< 0x00004000 */\n#define FMC_BCR4_EXTMOD             FMC_BCR4_EXTMOD_Msk                        /*!<Extended mode enable       */\n#define FMC_BCR4_ASYNCWAIT_Pos      (15U)                                      \n#define FMC_BCR4_ASYNCWAIT_Msk      (0x1U << FMC_BCR4_ASYNCWAIT_Pos)           /*!< 0x00008000 */\n#define FMC_BCR4_ASYNCWAIT          FMC_BCR4_ASYNCWAIT_Msk                     /*!<Asynchronous wait          */\n#define FMC_BCR4_CPSIZE_Pos         (16U)                                      \n#define FMC_BCR4_CPSIZE_Msk         (0x7U << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00070000 */\n#define FMC_BCR4_CPSIZE             FMC_BCR4_CPSIZE_Msk                        /*!<CRAM page size */\n#define FMC_BCR4_CPSIZE_0           (0x1U << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00010000 */\n#define FMC_BCR4_CPSIZE_1           (0x2U << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00020000 */\n#define FMC_BCR4_CPSIZE_2           (0x4U << FMC_BCR4_CPSIZE_Pos)              /*!< 0x00040000 */\n#define FMC_BCR4_CBURSTRW_Pos       (19U)                                      \n#define FMC_BCR4_CBURSTRW_Msk       (0x1U << FMC_BCR4_CBURSTRW_Pos)            /*!< 0x00080000 */\n#define FMC_BCR4_CBURSTRW           FMC_BCR4_CBURSTRW_Msk                      /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BTR1 register  ******************/\n#define FMC_BTR1_ADDSET_Pos         (0U)                                       \n#define FMC_BTR1_ADDSET_Msk         (0xFU << FMC_BTR1_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR1_ADDSET             FMC_BTR1_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR1_ADDSET_0           (0x1U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR1_ADDSET_1           (0x2U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR1_ADDSET_2           (0x4U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR1_ADDSET_3           (0x8U << FMC_BTR1_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR1_ADDHLD_Pos         (4U)                                       \n#define FMC_BTR1_ADDHLD_Msk         (0xFU << FMC_BTR1_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR1_ADDHLD             FMC_BTR1_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\n#define FMC_BTR1_ADDHLD_0           (0x1U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR1_ADDHLD_1           (0x2U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR1_ADDHLD_2           (0x4U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR1_ADDHLD_3           (0x8U << FMC_BTR1_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR1_DATAST_Pos         (8U)                                       \n#define FMC_BTR1_DATAST_Msk         (0xFFU << FMC_BTR1_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR1_DATAST             FMC_BTR1_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR1_DATAST_0           (0x01U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR1_DATAST_1           (0x02U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR1_DATAST_2           (0x04U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR1_DATAST_3           (0x08U << FMC_BTR1_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR1_DATAST_4           (0x10U << FMC_BTR1_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR1_DATAST_5           (0x20U << FMC_BTR1_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR1_DATAST_6           (0x40U << FMC_BTR1_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR1_DATAST_7           (0x80U << FMC_BTR1_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR1_BUSTURN_Pos        (16U)                                      \n#define FMC_BTR1_BUSTURN_Msk        (0xFU << FMC_BTR1_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR1_BUSTURN            FMC_BTR1_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR1_BUSTURN_0          (0x1U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR1_BUSTURN_1          (0x2U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR1_BUSTURN_2          (0x4U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR1_BUSTURN_3          (0x8U << FMC_BTR1_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR1_CLKDIV_Pos         (20U)                                      \n#define FMC_BTR1_CLKDIV_Msk         (0xFU << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR1_CLKDIV             FMC_BTR1_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR1_CLKDIV_0           (0x1U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR1_CLKDIV_1           (0x2U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR1_CLKDIV_2           (0x4U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR1_CLKDIV_3           (0x8U << FMC_BTR1_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR1_DATLAT_Pos         (24U)                                      \n#define FMC_BTR1_DATLAT_Msk         (0xFU << FMC_BTR1_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR1_DATLAT             FMC_BTR1_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR1_DATLAT_0           (0x1U << FMC_BTR1_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR1_DATLAT_1           (0x2U << FMC_BTR1_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR1_DATLAT_2           (0x4U << FMC_BTR1_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR1_DATLAT_3           (0x8U << FMC_BTR1_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR1_ACCMOD_Pos         (28U)                                      \n#define FMC_BTR1_ACCMOD_Msk         (0x3U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR1_ACCMOD             FMC_BTR1_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR1_ACCMOD_0           (0x1U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR1_ACCMOD_1           (0x2U << FMC_BTR1_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BTR2 register  *******************/\n#define FMC_BTR2_ADDSET_Pos         (0U)                                       \n#define FMC_BTR2_ADDSET_Msk         (0xFU << FMC_BTR2_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR2_ADDSET             FMC_BTR2_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR2_ADDSET_0           (0x1U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR2_ADDSET_1           (0x2U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR2_ADDSET_2           (0x4U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR2_ADDSET_3           (0x8U << FMC_BTR2_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR2_ADDHLD_Pos         (4U)                                       \n#define FMC_BTR2_ADDHLD_Msk         (0xFU << FMC_BTR2_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR2_ADDHLD             FMC_BTR2_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR2_ADDHLD_0           (0x1U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR2_ADDHLD_1           (0x2U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR2_ADDHLD_2           (0x4U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR2_ADDHLD_3           (0x8U << FMC_BTR2_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR2_DATAST_Pos         (8U)                                       \n#define FMC_BTR2_DATAST_Msk         (0xFFU << FMC_BTR2_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR2_DATAST             FMC_BTR2_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR2_DATAST_0           (0x01U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR2_DATAST_1           (0x02U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR2_DATAST_2           (0x04U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR2_DATAST_3           (0x08U << FMC_BTR2_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR2_DATAST_4           (0x10U << FMC_BTR2_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR2_DATAST_5           (0x20U << FMC_BTR2_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR2_DATAST_6           (0x40U << FMC_BTR2_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR2_DATAST_7           (0x80U << FMC_BTR2_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR2_BUSTURN_Pos        (16U)                                      \n#define FMC_BTR2_BUSTURN_Msk        (0xFU << FMC_BTR2_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR2_BUSTURN            FMC_BTR2_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR2_BUSTURN_0          (0x1U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR2_BUSTURN_1          (0x2U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR2_BUSTURN_2          (0x4U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR2_BUSTURN_3          (0x8U << FMC_BTR2_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR2_CLKDIV_Pos         (20U)                                      \n#define FMC_BTR2_CLKDIV_Msk         (0xFU << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR2_CLKDIV             FMC_BTR2_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR2_CLKDIV_0           (0x1U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR2_CLKDIV_1           (0x2U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR2_CLKDIV_2           (0x4U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR2_CLKDIV_3           (0x8U << FMC_BTR2_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR2_DATLAT_Pos         (24U)                                      \n#define FMC_BTR2_DATLAT_Msk         (0xFU << FMC_BTR2_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR2_DATLAT             FMC_BTR2_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR2_DATLAT_0           (0x1U << FMC_BTR2_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR2_DATLAT_1           (0x2U << FMC_BTR2_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR2_DATLAT_2           (0x4U << FMC_BTR2_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR2_DATLAT_3           (0x8U << FMC_BTR2_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR2_ACCMOD_Pos         (28U)                                      \n#define FMC_BTR2_ACCMOD_Msk         (0x3U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR2_ACCMOD             FMC_BTR2_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR2_ACCMOD_0           (0x1U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR2_ACCMOD_1           (0x2U << FMC_BTR2_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/*******************  Bit definition for FMC_BTR3 register  *******************/\n#define FMC_BTR3_ADDSET_Pos         (0U)                                       \n#define FMC_BTR3_ADDSET_Msk         (0xFU << FMC_BTR3_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR3_ADDSET             FMC_BTR3_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR3_ADDSET_0           (0x1U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR3_ADDSET_1           (0x2U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR3_ADDSET_2           (0x4U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR3_ADDSET_3           (0x8U << FMC_BTR3_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR3_ADDHLD_Pos         (4U)                                       \n#define FMC_BTR3_ADDHLD_Msk         (0xFU << FMC_BTR3_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR3_ADDHLD             FMC_BTR3_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR3_ADDHLD_0           (0x1U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR3_ADDHLD_1           (0x2U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR3_ADDHLD_2           (0x4U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR3_ADDHLD_3           (0x8U << FMC_BTR3_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR3_DATAST_Pos         (8U)                                       \n#define FMC_BTR3_DATAST_Msk         (0xFFU << FMC_BTR3_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR3_DATAST             FMC_BTR3_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR3_DATAST_0           (0x01U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR3_DATAST_1           (0x02U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR3_DATAST_2           (0x04U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR3_DATAST_3           (0x08U << FMC_BTR3_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR3_DATAST_4           (0x10U << FMC_BTR3_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR3_DATAST_5           (0x20U << FMC_BTR3_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR3_DATAST_6           (0x40U << FMC_BTR3_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR3_DATAST_7           (0x80U << FMC_BTR3_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR3_BUSTURN_Pos        (16U)                                      \n#define FMC_BTR3_BUSTURN_Msk        (0xFU << FMC_BTR3_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR3_BUSTURN            FMC_BTR3_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR3_BUSTURN_0          (0x1U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR3_BUSTURN_1          (0x2U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR3_BUSTURN_2          (0x4U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR3_BUSTURN_3          (0x8U << FMC_BTR3_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR3_CLKDIV_Pos         (20U)                                      \n#define FMC_BTR3_CLKDIV_Msk         (0xFU << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR3_CLKDIV             FMC_BTR3_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR3_CLKDIV_0           (0x1U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR3_CLKDIV_1           (0x2U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR3_CLKDIV_2           (0x4U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR3_CLKDIV_3           (0x8U << FMC_BTR3_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR3_DATLAT_Pos         (24U)                                      \n#define FMC_BTR3_DATLAT_Msk         (0xFU << FMC_BTR3_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR3_DATLAT             FMC_BTR3_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR3_DATLAT_0           (0x1U << FMC_BTR3_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR3_DATLAT_1           (0x2U << FMC_BTR3_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR3_DATLAT_2           (0x4U << FMC_BTR3_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR3_DATLAT_3           (0x8U << FMC_BTR3_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR3_ACCMOD_Pos         (28U)                                      \n#define FMC_BTR3_ACCMOD_Msk         (0x3U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR3_ACCMOD             FMC_BTR3_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR3_ACCMOD_0           (0x1U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR3_ACCMOD_1           (0x2U << FMC_BTR3_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BTR4 register  *******************/\n#define FMC_BTR4_ADDSET_Pos         (0U)                                       \n#define FMC_BTR4_ADDSET_Msk         (0xFU << FMC_BTR4_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BTR4_ADDSET             FMC_BTR4_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTR4_ADDSET_0           (0x1U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BTR4_ADDSET_1           (0x2U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BTR4_ADDSET_2           (0x4U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BTR4_ADDSET_3           (0x8U << FMC_BTR4_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BTR4_ADDHLD_Pos         (4U)                                       \n#define FMC_BTR4_ADDHLD_Msk         (0xFU << FMC_BTR4_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BTR4_ADDHLD             FMC_BTR4_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BTR4_ADDHLD_0           (0x1U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BTR4_ADDHLD_1           (0x2U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BTR4_ADDHLD_2           (0x4U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BTR4_ADDHLD_3           (0x8U << FMC_BTR4_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BTR4_DATAST_Pos         (8U)                                       \n#define FMC_BTR4_DATAST_Msk         (0xFFU << FMC_BTR4_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BTR4_DATAST             FMC_BTR4_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTR4_DATAST_0           (0x01U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BTR4_DATAST_1           (0x02U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BTR4_DATAST_2           (0x04U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BTR4_DATAST_3           (0x08U << FMC_BTR4_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BTR4_DATAST_4           (0x10U << FMC_BTR4_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BTR4_DATAST_5           (0x20U << FMC_BTR4_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BTR4_DATAST_6           (0x40U << FMC_BTR4_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BTR4_DATAST_7           (0x80U << FMC_BTR4_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BTR4_BUSTURN_Pos        (16U)                                      \n#define FMC_BTR4_BUSTURN_Msk        (0xFU << FMC_BTR4_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BTR4_BUSTURN            FMC_BTR4_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTR4_BUSTURN_0          (0x1U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BTR4_BUSTURN_1          (0x2U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BTR4_BUSTURN_2          (0x4U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BTR4_BUSTURN_3          (0x8U << FMC_BTR4_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BTR4_CLKDIV_Pos         (20U)                                      \n#define FMC_BTR4_CLKDIV_Msk         (0xFU << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00F00000 */\n#define FMC_BTR4_CLKDIV             FMC_BTR4_CLKDIV_Msk                        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTR4_CLKDIV_0           (0x1U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00100000 */\n#define FMC_BTR4_CLKDIV_1           (0x2U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00200000 */\n#define FMC_BTR4_CLKDIV_2           (0x4U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00400000 */\n#define FMC_BTR4_CLKDIV_3           (0x8U << FMC_BTR4_CLKDIV_Pos)              /*!< 0x00800000 */\n\n#define FMC_BTR4_DATLAT_Pos         (24U)                                      \n#define FMC_BTR4_DATLAT_Msk         (0xFU << FMC_BTR4_DATLAT_Pos)              /*!< 0x0F000000 */\n#define FMC_BTR4_DATLAT             FMC_BTR4_DATLAT_Msk                        /*!<DATLA[3:0] bits (Data latency) */\n#define FMC_BTR4_DATLAT_0           (0x1U << FMC_BTR4_DATLAT_Pos)              /*!< 0x01000000 */\n#define FMC_BTR4_DATLAT_1           (0x2U << FMC_BTR4_DATLAT_Pos)              /*!< 0x02000000 */\n#define FMC_BTR4_DATLAT_2           (0x4U << FMC_BTR4_DATLAT_Pos)              /*!< 0x04000000 */\n#define FMC_BTR4_DATLAT_3           (0x8U << FMC_BTR4_DATLAT_Pos)              /*!< 0x08000000 */\n\n#define FMC_BTR4_ACCMOD_Pos         (28U)                                      \n#define FMC_BTR4_ACCMOD_Msk         (0x3U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BTR4_ACCMOD             FMC_BTR4_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTR4_ACCMOD_0           (0x1U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BTR4_ACCMOD_1           (0x2U << FMC_BTR4_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR1 register  ******************/\n#define FMC_BWTR1_ADDSET_Pos        (0U)                                       \n#define FMC_BWTR1_ADDSET_Msk        (0xFU << FMC_BWTR1_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR1_ADDSET            FMC_BWTR1_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR1_ADDSET_0          (0x1U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR1_ADDSET_1          (0x2U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR1_ADDSET_2          (0x4U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR1_ADDSET_3          (0x8U << FMC_BWTR1_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR1_ADDHLD_Pos        (4U)                                       \n#define FMC_BWTR1_ADDHLD_Msk        (0xFU << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR1_ADDHLD            FMC_BWTR1_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR1_ADDHLD_0          (0x1U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR1_ADDHLD_1          (0x2U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR1_ADDHLD_2          (0x4U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR1_ADDHLD_3          (0x8U << FMC_BWTR1_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR1_DATAST_Pos        (8U)                                       \n#define FMC_BWTR1_DATAST_Msk        (0xFFU << FMC_BWTR1_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR1_DATAST            FMC_BWTR1_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR1_DATAST_0          (0x01U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR1_DATAST_1          (0x02U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR1_DATAST_2          (0x04U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR1_DATAST_3          (0x08U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR1_DATAST_4          (0x10U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR1_DATAST_5          (0x20U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR1_DATAST_6          (0x40U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR1_DATAST_7          (0x80U << FMC_BWTR1_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR1_BUSTURN_Pos       (16U)                                      \n#define FMC_BWTR1_BUSTURN_Msk       (0xFU << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR1_BUSTURN           FMC_BWTR1_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR1_BUSTURN_0         (0x1U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR1_BUSTURN_1         (0x2U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR1_BUSTURN_2         (0x4U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR1_BUSTURN_3         (0x8U << FMC_BWTR1_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR1_ACCMOD_Pos        (28U)                                      \n#define FMC_BWTR1_ACCMOD_Msk        (0x3U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR1_ACCMOD            FMC_BWTR1_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR1_ACCMOD_0          (0x1U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR1_ACCMOD_1          (0x2U << FMC_BWTR1_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR2 register  ******************/\n#define FMC_BWTR2_ADDSET_Pos        (0U)                                       \n#define FMC_BWTR2_ADDSET_Msk        (0xFU << FMC_BWTR2_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR2_ADDSET            FMC_BWTR2_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR2_ADDSET_0          (0x1U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR2_ADDSET_1          (0x2U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR2_ADDSET_2          (0x4U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR2_ADDSET_3          (0x8U << FMC_BWTR2_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR2_ADDHLD_Pos        (4U)                                       \n#define FMC_BWTR2_ADDHLD_Msk        (0xFU << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR2_ADDHLD            FMC_BWTR2_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR2_ADDHLD_0          (0x1U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR2_ADDHLD_1          (0x2U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR2_ADDHLD_2          (0x4U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR2_ADDHLD_3          (0x8U << FMC_BWTR2_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR2_DATAST_Pos        (8U)                                       \n#define FMC_BWTR2_DATAST_Msk        (0xFFU << FMC_BWTR2_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR2_DATAST            FMC_BWTR2_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR2_DATAST_0          (0x01U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR2_DATAST_1          (0x02U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR2_DATAST_2          (0x04U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR2_DATAST_3          (0x08U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR2_DATAST_4          (0x10U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR2_DATAST_5          (0x20U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR2_DATAST_6          (0x40U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR2_DATAST_7          (0x80U << FMC_BWTR2_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR2_BUSTURN_Pos       (16U)                                      \n#define FMC_BWTR2_BUSTURN_Msk       (0xFU << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR2_BUSTURN           FMC_BWTR2_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR2_BUSTURN_0         (0x1U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR2_BUSTURN_1         (0x2U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR2_BUSTURN_2         (0x4U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR2_BUSTURN_3         (0x8U << FMC_BWTR2_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR2_ACCMOD_Pos        (28U)                                      \n#define FMC_BWTR2_ACCMOD_Msk        (0x3U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR2_ACCMOD            FMC_BWTR2_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR2_ACCMOD_0          (0x1U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR2_ACCMOD_1          (0x2U << FMC_BWTR2_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR3 register  ******************/\n#define FMC_BWTR3_ADDSET_Pos        (0U)                                       \n#define FMC_BWTR3_ADDSET_Msk        (0xFU << FMC_BWTR3_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR3_ADDSET            FMC_BWTR3_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR3_ADDSET_0          (0x1U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR3_ADDSET_1          (0x2U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR3_ADDSET_2          (0x4U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR3_ADDSET_3          (0x8U << FMC_BWTR3_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR3_ADDHLD_Pos        (4U)                                       \n#define FMC_BWTR3_ADDHLD_Msk        (0xFU << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR3_ADDHLD            FMC_BWTR3_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR3_ADDHLD_0          (0x1U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR3_ADDHLD_1          (0x2U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR3_ADDHLD_2          (0x4U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR3_ADDHLD_3          (0x8U << FMC_BWTR3_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR3_DATAST_Pos        (8U)                                       \n#define FMC_BWTR3_DATAST_Msk        (0xFFU << FMC_BWTR3_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR3_DATAST            FMC_BWTR3_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR3_DATAST_0          (0x01U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR3_DATAST_1          (0x02U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR3_DATAST_2          (0x04U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR3_DATAST_3          (0x08U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR3_DATAST_4          (0x10U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR3_DATAST_5          (0x20U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR3_DATAST_6          (0x40U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR3_DATAST_7          (0x80U << FMC_BWTR3_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR3_BUSTURN_Pos       (16U)                                      \n#define FMC_BWTR3_BUSTURN_Msk       (0xFU << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR3_BUSTURN           FMC_BWTR3_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR3_BUSTURN_0         (0x1U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR3_BUSTURN_1         (0x2U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR3_BUSTURN_2         (0x4U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR3_BUSTURN_3         (0x8U << FMC_BWTR3_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR3_ACCMOD_Pos        (28U)                                      \n#define FMC_BWTR3_ACCMOD_Msk        (0x3U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR3_ACCMOD            FMC_BWTR3_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR3_ACCMOD_0          (0x1U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR3_ACCMOD_1          (0x2U << FMC_BWTR3_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTR4 register  ******************/\n#define FMC_BWTR4_ADDSET_Pos        (0U)                                       \n#define FMC_BWTR4_ADDSET_Msk        (0xFU << FMC_BWTR4_ADDSET_Pos)             /*!< 0x0000000F */\n#define FMC_BWTR4_ADDSET            FMC_BWTR4_ADDSET_Msk                       /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTR4_ADDSET_0          (0x1U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000001 */\n#define FMC_BWTR4_ADDSET_1          (0x2U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000002 */\n#define FMC_BWTR4_ADDSET_2          (0x4U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000004 */\n#define FMC_BWTR4_ADDSET_3          (0x8U << FMC_BWTR4_ADDSET_Pos)             /*!< 0x00000008 */\n\n#define FMC_BWTR4_ADDHLD_Pos        (4U)                                       \n#define FMC_BWTR4_ADDHLD_Msk        (0xFU << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x000000F0 */\n#define FMC_BWTR4_ADDHLD            FMC_BWTR4_ADDHLD_Msk                       /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTR4_ADDHLD_0          (0x1U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000010 */\n#define FMC_BWTR4_ADDHLD_1          (0x2U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000020 */\n#define FMC_BWTR4_ADDHLD_2          (0x4U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000040 */\n#define FMC_BWTR4_ADDHLD_3          (0x8U << FMC_BWTR4_ADDHLD_Pos)             /*!< 0x00000080 */\n\n#define FMC_BWTR4_DATAST_Pos        (8U)                                       \n#define FMC_BWTR4_DATAST_Msk        (0xFFU << FMC_BWTR4_DATAST_Pos)            /*!< 0x0000FF00 */\n#define FMC_BWTR4_DATAST            FMC_BWTR4_DATAST_Msk                       /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTR4_DATAST_0          (0x01U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000100 */\n#define FMC_BWTR4_DATAST_1          (0x02U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000200 */\n#define FMC_BWTR4_DATAST_2          (0x04U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000400 */\n#define FMC_BWTR4_DATAST_3          (0x08U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00000800 */\n#define FMC_BWTR4_DATAST_4          (0x10U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00001000 */\n#define FMC_BWTR4_DATAST_5          (0x20U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00002000 */\n#define FMC_BWTR4_DATAST_6          (0x40U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00004000 */\n#define FMC_BWTR4_DATAST_7          (0x80U << FMC_BWTR4_DATAST_Pos)            /*!< 0x00008000 */\n\n#define FMC_BWTR4_BUSTURN_Pos       (16U)                                      \n#define FMC_BWTR4_BUSTURN_Msk       (0xFU << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x000F0000 */\n#define FMC_BWTR4_BUSTURN           FMC_BWTR4_BUSTURN_Msk                      /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FMC_BWTR4_BUSTURN_0         (0x1U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00010000 */\n#define FMC_BWTR4_BUSTURN_1         (0x2U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00020000 */\n#define FMC_BWTR4_BUSTURN_2         (0x4U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00040000 */\n#define FMC_BWTR4_BUSTURN_3         (0x8U << FMC_BWTR4_BUSTURN_Pos)            /*!< 0x00080000 */\n\n#define FMC_BWTR4_ACCMOD_Pos        (28U)                                      \n#define FMC_BWTR4_ACCMOD_Msk        (0x3U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x30000000 */\n#define FMC_BWTR4_ACCMOD            FMC_BWTR4_ACCMOD_Msk                       /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTR4_ACCMOD_0          (0x1U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x10000000 */\n#define FMC_BWTR4_ACCMOD_1          (0x2U << FMC_BWTR4_ACCMOD_Pos)             /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_PCR2 register  *******************/\n\n#define FMC_PCR2_PWAITEN_Pos        (1U)                                       \n#define FMC_PCR2_PWAITEN_Msk        (0x1U << FMC_PCR2_PWAITEN_Pos)             /*!< 0x00000002 */\n#define FMC_PCR2_PWAITEN            FMC_PCR2_PWAITEN_Msk                       /*!<Wait feature enable bit                   */\n#define FMC_PCR2_PBKEN_Pos          (2U)                                       \n#define FMC_PCR2_PBKEN_Msk          (0x1U << FMC_PCR2_PBKEN_Pos)               /*!< 0x00000004 */\n#define FMC_PCR2_PBKEN              FMC_PCR2_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */\n#define FMC_PCR2_PTYP_Pos           (3U)                                       \n#define FMC_PCR2_PTYP_Msk           (0x1U << FMC_PCR2_PTYP_Pos)                /*!< 0x00000008 */\n#define FMC_PCR2_PTYP               FMC_PCR2_PTYP_Msk                          /*!<Memory type                               */\n\n#define FMC_PCR2_PWID_Pos           (4U)                                       \n#define FMC_PCR2_PWID_Msk           (0x3U << FMC_PCR2_PWID_Pos)                /*!< 0x00000030 */\n#define FMC_PCR2_PWID               FMC_PCR2_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FMC_PCR2_PWID_0             (0x1U << FMC_PCR2_PWID_Pos)                /*!< 0x00000010 */\n#define FMC_PCR2_PWID_1             (0x2U << FMC_PCR2_PWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_PCR2_ECCEN_Pos          (6U)                                       \n#define FMC_PCR2_ECCEN_Msk          (0x1U << FMC_PCR2_ECCEN_Pos)               /*!< 0x00000040 */\n#define FMC_PCR2_ECCEN              FMC_PCR2_ECCEN_Msk                         /*!<ECC computation logic enable bit          */\n\n#define FMC_PCR2_TCLR_Pos           (9U)                                       \n#define FMC_PCR2_TCLR_Msk           (0xFU << FMC_PCR2_TCLR_Pos)                /*!< 0x00001E00 */\n#define FMC_PCR2_TCLR               FMC_PCR2_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */\n#define FMC_PCR2_TCLR_0             (0x1U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000200 */\n#define FMC_PCR2_TCLR_1             (0x2U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000400 */\n#define FMC_PCR2_TCLR_2             (0x4U << FMC_PCR2_TCLR_Pos)                /*!< 0x00000800 */\n#define FMC_PCR2_TCLR_3             (0x8U << FMC_PCR2_TCLR_Pos)                /*!< 0x00001000 */\n\n#define FMC_PCR2_TAR_Pos            (13U)                                      \n#define FMC_PCR2_TAR_Msk            (0xFU << FMC_PCR2_TAR_Pos)                 /*!< 0x0001E000 */\n#define FMC_PCR2_TAR                FMC_PCR2_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */\n#define FMC_PCR2_TAR_0              (0x1U << FMC_PCR2_TAR_Pos)                 /*!< 0x00002000 */\n#define FMC_PCR2_TAR_1              (0x2U << FMC_PCR2_TAR_Pos)                 /*!< 0x00004000 */\n#define FMC_PCR2_TAR_2              (0x4U << FMC_PCR2_TAR_Pos)                 /*!< 0x00008000 */\n#define FMC_PCR2_TAR_3              (0x8U << FMC_PCR2_TAR_Pos)                 /*!< 0x00010000 */\n\n#define FMC_PCR2_ECCPS_Pos          (17U)                                      \n#define FMC_PCR2_ECCPS_Msk          (0x7U << FMC_PCR2_ECCPS_Pos)               /*!< 0x000E0000 */\n#define FMC_PCR2_ECCPS              FMC_PCR2_ECCPS_Msk                         /*!<ECCPS[1:0] bits (ECC page size)           */\n#define FMC_PCR2_ECCPS_0            (0x1U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00020000 */\n#define FMC_PCR2_ECCPS_1            (0x2U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00040000 */\n#define FMC_PCR2_ECCPS_2            (0x4U << FMC_PCR2_ECCPS_Pos)               /*!< 0x00080000 */\n\n/******************  Bit definition for FMC_PCR3 register  *******************/\n#define FMC_PCR3_PWAITEN_Pos        (1U)                                       \n#define FMC_PCR3_PWAITEN_Msk        (0x1U << FMC_PCR3_PWAITEN_Pos)             /*!< 0x00000002 */\n#define FMC_PCR3_PWAITEN            FMC_PCR3_PWAITEN_Msk                       /*!<Wait feature enable bit                   */\n#define FMC_PCR3_PBKEN_Pos          (2U)                                       \n#define FMC_PCR3_PBKEN_Msk          (0x1U << FMC_PCR3_PBKEN_Pos)               /*!< 0x00000004 */\n#define FMC_PCR3_PBKEN              FMC_PCR3_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */\n#define FMC_PCR3_PTYP_Pos           (3U)                                       \n#define FMC_PCR3_PTYP_Msk           (0x1U << FMC_PCR3_PTYP_Pos)                /*!< 0x00000008 */\n#define FMC_PCR3_PTYP               FMC_PCR3_PTYP_Msk                          /*!<Memory type                               */\n\n#define FMC_PCR3_PWID_Pos           (4U)                                       \n#define FMC_PCR3_PWID_Msk           (0x3U << FMC_PCR3_PWID_Pos)                /*!< 0x00000030 */\n#define FMC_PCR3_PWID               FMC_PCR3_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FMC_PCR3_PWID_0             (0x1U << FMC_PCR3_PWID_Pos)                /*!< 0x00000010 */\n#define FMC_PCR3_PWID_1             (0x2U << FMC_PCR3_PWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_PCR3_ECCEN_Pos          (6U)                                       \n#define FMC_PCR3_ECCEN_Msk          (0x1U << FMC_PCR3_ECCEN_Pos)               /*!< 0x00000040 */\n#define FMC_PCR3_ECCEN              FMC_PCR3_ECCEN_Msk                         /*!<ECC computation logic enable bit          */\n\n#define FMC_PCR3_TCLR_Pos           (9U)                                       \n#define FMC_PCR3_TCLR_Msk           (0xFU << FMC_PCR3_TCLR_Pos)                /*!< 0x00001E00 */\n#define FMC_PCR3_TCLR               FMC_PCR3_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */\n#define FMC_PCR3_TCLR_0             (0x1U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000200 */\n#define FMC_PCR3_TCLR_1             (0x2U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000400 */\n#define FMC_PCR3_TCLR_2             (0x4U << FMC_PCR3_TCLR_Pos)                /*!< 0x00000800 */\n#define FMC_PCR3_TCLR_3             (0x8U << FMC_PCR3_TCLR_Pos)                /*!< 0x00001000 */\n\n#define FMC_PCR3_TAR_Pos            (13U)                                      \n#define FMC_PCR3_TAR_Msk            (0xFU << FMC_PCR3_TAR_Pos)                 /*!< 0x0001E000 */\n#define FMC_PCR3_TAR                FMC_PCR3_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */\n#define FMC_PCR3_TAR_0              (0x1U << FMC_PCR3_TAR_Pos)                 /*!< 0x00002000 */\n#define FMC_PCR3_TAR_1              (0x2U << FMC_PCR3_TAR_Pos)                 /*!< 0x00004000 */\n#define FMC_PCR3_TAR_2              (0x4U << FMC_PCR3_TAR_Pos)                 /*!< 0x00008000 */\n#define FMC_PCR3_TAR_3              (0x8U << FMC_PCR3_TAR_Pos)                 /*!< 0x00010000 */\n\n#define FMC_PCR3_ECCPS_Pos          (17U)                                      \n#define FMC_PCR3_ECCPS_Msk          (0x7U << FMC_PCR3_ECCPS_Pos)               /*!< 0x000E0000 */\n#define FMC_PCR3_ECCPS              FMC_PCR3_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */\n#define FMC_PCR3_ECCPS_0            (0x1U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00020000 */\n#define FMC_PCR3_ECCPS_1            (0x2U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00040000 */\n#define FMC_PCR3_ECCPS_2            (0x4U << FMC_PCR3_ECCPS_Pos)               /*!< 0x00080000 */\n\n/******************  Bit definition for FMC_PCR4 register  *******************/\n#define FMC_PCR4_PWAITEN_Pos        (1U)                                       \n#define FMC_PCR4_PWAITEN_Msk        (0x1U << FMC_PCR4_PWAITEN_Pos)             /*!< 0x00000002 */\n#define FMC_PCR4_PWAITEN            FMC_PCR4_PWAITEN_Msk                       /*!<Wait feature enable bit                   */\n#define FMC_PCR4_PBKEN_Pos          (2U)                                       \n#define FMC_PCR4_PBKEN_Msk          (0x1U << FMC_PCR4_PBKEN_Pos)               /*!< 0x00000004 */\n#define FMC_PCR4_PBKEN              FMC_PCR4_PBKEN_Msk                         /*!<PC Card/NAND Flash memory bank enable bit */\n#define FMC_PCR4_PTYP_Pos           (3U)                                       \n#define FMC_PCR4_PTYP_Msk           (0x1U << FMC_PCR4_PTYP_Pos)                /*!< 0x00000008 */\n#define FMC_PCR4_PTYP               FMC_PCR4_PTYP_Msk                          /*!<Memory type                               */\n\n#define FMC_PCR4_PWID_Pos           (4U)                                       \n#define FMC_PCR4_PWID_Msk           (0x3U << FMC_PCR4_PWID_Pos)                /*!< 0x00000030 */\n#define FMC_PCR4_PWID               FMC_PCR4_PWID_Msk                          /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FMC_PCR4_PWID_0             (0x1U << FMC_PCR4_PWID_Pos)                /*!< 0x00000010 */\n#define FMC_PCR4_PWID_1             (0x2U << FMC_PCR4_PWID_Pos)                /*!< 0x00000020 */\n\n#define FMC_PCR4_ECCEN_Pos          (6U)                                       \n#define FMC_PCR4_ECCEN_Msk          (0x1U << FMC_PCR4_ECCEN_Pos)               /*!< 0x00000040 */\n#define FMC_PCR4_ECCEN              FMC_PCR4_ECCEN_Msk                         /*!<ECC computation logic enable bit          */\n\n#define FMC_PCR4_TCLR_Pos           (9U)                                       \n#define FMC_PCR4_TCLR_Msk           (0xFU << FMC_PCR4_TCLR_Pos)                /*!< 0x00001E00 */\n#define FMC_PCR4_TCLR               FMC_PCR4_TCLR_Msk                          /*!<TCLR[3:0] bits (CLE to RE delay)          */\n#define FMC_PCR4_TCLR_0             (0x1U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000200 */\n#define FMC_PCR4_TCLR_1             (0x2U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000400 */\n#define FMC_PCR4_TCLR_2             (0x4U << FMC_PCR4_TCLR_Pos)                /*!< 0x00000800 */\n#define FMC_PCR4_TCLR_3             (0x8U << FMC_PCR4_TCLR_Pos)                /*!< 0x00001000 */\n\n#define FMC_PCR4_TAR_Pos            (13U)                                      \n#define FMC_PCR4_TAR_Msk            (0xFU << FMC_PCR4_TAR_Pos)                 /*!< 0x0001E000 */\n#define FMC_PCR4_TAR                FMC_PCR4_TAR_Msk                           /*!<TAR[3:0] bits (ALE to RE delay)           */\n#define FMC_PCR4_TAR_0              (0x1U << FMC_PCR4_TAR_Pos)                 /*!< 0x00002000 */\n#define FMC_PCR4_TAR_1              (0x2U << FMC_PCR4_TAR_Pos)                 /*!< 0x00004000 */\n#define FMC_PCR4_TAR_2              (0x4U << FMC_PCR4_TAR_Pos)                 /*!< 0x00008000 */\n#define FMC_PCR4_TAR_3              (0x8U << FMC_PCR4_TAR_Pos)                 /*!< 0x00010000 */\n\n#define FMC_PCR4_ECCPS_Pos          (17U)                                      \n#define FMC_PCR4_ECCPS_Msk          (0x7U << FMC_PCR4_ECCPS_Pos)               /*!< 0x000E0000 */\n#define FMC_PCR4_ECCPS              FMC_PCR4_ECCPS_Msk                         /*!<ECCPS[2:0] bits (ECC page size)           */\n#define FMC_PCR4_ECCPS_0            (0x1U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00020000 */\n#define FMC_PCR4_ECCPS_1            (0x2U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00040000 */\n#define FMC_PCR4_ECCPS_2            (0x4U << FMC_PCR4_ECCPS_Pos)               /*!< 0x00080000 */\n\n/*******************  Bit definition for FMC_SR2 register  *******************/\n#define FMC_SR2_IRS_Pos             (0U)                                       \n#define FMC_SR2_IRS_Msk             (0x1U << FMC_SR2_IRS_Pos)                  /*!< 0x00000001 */\n#define FMC_SR2_IRS                 FMC_SR2_IRS_Msk                            /*!<Interrupt Rising Edge status                */\n#define FMC_SR2_ILS_Pos             (1U)                                       \n#define FMC_SR2_ILS_Msk             (0x1U << FMC_SR2_ILS_Pos)                  /*!< 0x00000002 */\n#define FMC_SR2_ILS                 FMC_SR2_ILS_Msk                            /*!<Interrupt Level status                      */\n#define FMC_SR2_IFS_Pos             (2U)                                       \n#define FMC_SR2_IFS_Msk             (0x1U << FMC_SR2_IFS_Pos)                  /*!< 0x00000004 */\n#define FMC_SR2_IFS                 FMC_SR2_IFS_Msk                            /*!<Interrupt Falling Edge status               */\n#define FMC_SR2_IREN_Pos            (3U)                                       \n#define FMC_SR2_IREN_Msk            (0x1U << FMC_SR2_IREN_Pos)                 /*!< 0x00000008 */\n#define FMC_SR2_IREN                FMC_SR2_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */\n#define FMC_SR2_ILEN_Pos            (4U)                                       \n#define FMC_SR2_ILEN_Msk            (0x1U << FMC_SR2_ILEN_Pos)                 /*!< 0x00000010 */\n#define FMC_SR2_ILEN                FMC_SR2_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */\n#define FMC_SR2_IFEN_Pos            (5U)                                       \n#define FMC_SR2_IFEN_Msk            (0x1U << FMC_SR2_IFEN_Pos)                 /*!< 0x00000020 */\n#define FMC_SR2_IFEN                FMC_SR2_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */\n#define FMC_SR2_FEMPT_Pos           (6U)                                       \n#define FMC_SR2_FEMPT_Msk           (0x1U << FMC_SR2_FEMPT_Pos)                /*!< 0x00000040 */\n#define FMC_SR2_FEMPT               FMC_SR2_FEMPT_Msk                          /*!<FIFO empty                                  */\n\n/*******************  Bit definition for FMC_SR3 register  *******************/\n#define FMC_SR3_IRS_Pos             (0U)                                       \n#define FMC_SR3_IRS_Msk             (0x1U << FMC_SR3_IRS_Pos)                  /*!< 0x00000001 */\n#define FMC_SR3_IRS                 FMC_SR3_IRS_Msk                            /*!<Interrupt Rising Edge status                */\n#define FMC_SR3_ILS_Pos             (1U)                                       \n#define FMC_SR3_ILS_Msk             (0x1U << FMC_SR3_ILS_Pos)                  /*!< 0x00000002 */\n#define FMC_SR3_ILS                 FMC_SR3_ILS_Msk                            /*!<Interrupt Level status                      */\n#define FMC_SR3_IFS_Pos             (2U)                                       \n#define FMC_SR3_IFS_Msk             (0x1U << FMC_SR3_IFS_Pos)                  /*!< 0x00000004 */\n#define FMC_SR3_IFS                 FMC_SR3_IFS_Msk                            /*!<Interrupt Falling Edge status               */\n#define FMC_SR3_IREN_Pos            (3U)                                       \n#define FMC_SR3_IREN_Msk            (0x1U << FMC_SR3_IREN_Pos)                 /*!< 0x00000008 */\n#define FMC_SR3_IREN                FMC_SR3_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */\n#define FMC_SR3_ILEN_Pos            (4U)                                       \n#define FMC_SR3_ILEN_Msk            (0x1U << FMC_SR3_ILEN_Pos)                 /*!< 0x00000010 */\n#define FMC_SR3_ILEN                FMC_SR3_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */\n#define FMC_SR3_IFEN_Pos            (5U)                                       \n#define FMC_SR3_IFEN_Msk            (0x1U << FMC_SR3_IFEN_Pos)                 /*!< 0x00000020 */\n#define FMC_SR3_IFEN                FMC_SR3_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */\n#define FMC_SR3_FEMPT_Pos           (6U)                                       \n#define FMC_SR3_FEMPT_Msk           (0x1U << FMC_SR3_FEMPT_Pos)                /*!< 0x00000040 */\n#define FMC_SR3_FEMPT               FMC_SR3_FEMPT_Msk                          /*!<FIFO empty                                  */\n\n/*******************  Bit definition for FMC_SR4 register  *******************/\n#define FMC_SR4_IRS_Pos             (0U)                                       \n#define FMC_SR4_IRS_Msk             (0x1U << FMC_SR4_IRS_Pos)                  /*!< 0x00000001 */\n#define FMC_SR4_IRS                 FMC_SR4_IRS_Msk                            /*!<Interrupt Rising Edge status                */\n#define FMC_SR4_ILS_Pos             (1U)                                       \n#define FMC_SR4_ILS_Msk             (0x1U << FMC_SR4_ILS_Pos)                  /*!< 0x00000002 */\n#define FMC_SR4_ILS                 FMC_SR4_ILS_Msk                            /*!<Interrupt Level status                      */\n#define FMC_SR4_IFS_Pos             (2U)                                       \n#define FMC_SR4_IFS_Msk             (0x1U << FMC_SR4_IFS_Pos)                  /*!< 0x00000004 */\n#define FMC_SR4_IFS                 FMC_SR4_IFS_Msk                            /*!<Interrupt Falling Edge status               */\n#define FMC_SR4_IREN_Pos            (3U)                                       \n#define FMC_SR4_IREN_Msk            (0x1U << FMC_SR4_IREN_Pos)                 /*!< 0x00000008 */\n#define FMC_SR4_IREN                FMC_SR4_IREN_Msk                           /*!<Interrupt Rising Edge detection Enable bit  */\n#define FMC_SR4_ILEN_Pos            (4U)                                       \n#define FMC_SR4_ILEN_Msk            (0x1U << FMC_SR4_ILEN_Pos)                 /*!< 0x00000010 */\n#define FMC_SR4_ILEN                FMC_SR4_ILEN_Msk                           /*!<Interrupt Level detection Enable bit        */\n#define FMC_SR4_IFEN_Pos            (5U)                                       \n#define FMC_SR4_IFEN_Msk            (0x1U << FMC_SR4_IFEN_Pos)                 /*!< 0x00000020 */\n#define FMC_SR4_IFEN                FMC_SR4_IFEN_Msk                           /*!<Interrupt Falling Edge detection Enable bit */\n#define FMC_SR4_FEMPT_Pos           (6U)                                       \n#define FMC_SR4_FEMPT_Msk           (0x1U << FMC_SR4_FEMPT_Pos)                /*!< 0x00000040 */\n#define FMC_SR4_FEMPT               FMC_SR4_FEMPT_Msk                          /*!<FIFO empty                                  */\n\n/******************  Bit definition for FMC_PMEM2 register  ******************/\n#define FMC_PMEM2_MEMSET2_Pos       (0U)                                       \n#define FMC_PMEM2_MEMSET2_Msk       (0xFFU << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x000000FF */\n#define FMC_PMEM2_MEMSET2           FMC_PMEM2_MEMSET2_Msk                      /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\n#define FMC_PMEM2_MEMSET2_0         (0x01U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000001 */\n#define FMC_PMEM2_MEMSET2_1         (0x02U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000002 */\n#define FMC_PMEM2_MEMSET2_2         (0x04U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000004 */\n#define FMC_PMEM2_MEMSET2_3         (0x08U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000008 */\n#define FMC_PMEM2_MEMSET2_4         (0x10U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000010 */\n#define FMC_PMEM2_MEMSET2_5         (0x20U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000020 */\n#define FMC_PMEM2_MEMSET2_6         (0x40U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000040 */\n#define FMC_PMEM2_MEMSET2_7         (0x80U << FMC_PMEM2_MEMSET2_Pos)           /*!< 0x00000080 */\n\n#define FMC_PMEM2_MEMWAIT2_Pos      (8U)                                       \n#define FMC_PMEM2_MEMWAIT2_Msk      (0xFFU << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x0000FF00 */\n#define FMC_PMEM2_MEMWAIT2          FMC_PMEM2_MEMWAIT2_Msk                     /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\n#define FMC_PMEM2_MEMWAIT2_0        (0x01U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000100 */\n#define FMC_PMEM2_MEMWAIT2_1        (0x02U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000200 */\n#define FMC_PMEM2_MEMWAIT2_2        (0x04U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000400 */\n#define FMC_PMEM2_MEMWAIT2_3        (0x08U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00000800 */\n#define FMC_PMEM2_MEMWAIT2_4        (0x10U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00001000 */\n#define FMC_PMEM2_MEMWAIT2_5        (0x20U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00002000 */\n#define FMC_PMEM2_MEMWAIT2_6        (0x40U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00004000 */\n#define FMC_PMEM2_MEMWAIT2_7        (0x80U << FMC_PMEM2_MEMWAIT2_Pos)          /*!< 0x00008000 */\n\n#define FMC_PMEM2_MEMHOLD2_Pos      (16U)                                      \n#define FMC_PMEM2_MEMHOLD2_Msk      (0xFFU << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00FF0000 */\n#define FMC_PMEM2_MEMHOLD2          FMC_PMEM2_MEMHOLD2_Msk                     /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\n#define FMC_PMEM2_MEMHOLD2_0        (0x01U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00010000 */\n#define FMC_PMEM2_MEMHOLD2_1        (0x02U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00020000 */\n#define FMC_PMEM2_MEMHOLD2_2        (0x04U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00040000 */\n#define FMC_PMEM2_MEMHOLD2_3        (0x08U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00080000 */\n#define FMC_PMEM2_MEMHOLD2_4        (0x10U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00100000 */\n#define FMC_PMEM2_MEMHOLD2_5        (0x20U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00200000 */\n#define FMC_PMEM2_MEMHOLD2_6        (0x40U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00400000 */\n#define FMC_PMEM2_MEMHOLD2_7        (0x80U << FMC_PMEM2_MEMHOLD2_Pos)          /*!< 0x00800000 */\n\n#define FMC_PMEM2_MEMHIZ2_Pos       (24U)                                      \n#define FMC_PMEM2_MEMHIZ2_Msk       (0xFFU << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0xFF000000 */\n#define FMC_PMEM2_MEMHIZ2           FMC_PMEM2_MEMHIZ2_Msk                      /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\n#define FMC_PMEM2_MEMHIZ2_0         (0x01U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x01000000 */\n#define FMC_PMEM2_MEMHIZ2_1         (0x02U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x02000000 */\n#define FMC_PMEM2_MEMHIZ2_2         (0x04U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x04000000 */\n#define FMC_PMEM2_MEMHIZ2_3         (0x08U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x08000000 */\n#define FMC_PMEM2_MEMHIZ2_4         (0x10U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x10000000 */\n#define FMC_PMEM2_MEMHIZ2_5         (0x20U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x20000000 */\n#define FMC_PMEM2_MEMHIZ2_6         (0x40U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x40000000 */\n#define FMC_PMEM2_MEMHIZ2_7         (0x80U << FMC_PMEM2_MEMHIZ2_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PMEM3 register  ******************/\n#define FMC_PMEM3_MEMSET3_Pos       (0U)                                       \n#define FMC_PMEM3_MEMSET3_Msk       (0xFFU << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x000000FF */\n#define FMC_PMEM3_MEMSET3           FMC_PMEM3_MEMSET3_Msk                      /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\n#define FMC_PMEM3_MEMSET3_0         (0x01U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000001 */\n#define FMC_PMEM3_MEMSET3_1         (0x02U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000002 */\n#define FMC_PMEM3_MEMSET3_2         (0x04U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000004 */\n#define FMC_PMEM3_MEMSET3_3         (0x08U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000008 */\n#define FMC_PMEM3_MEMSET3_4         (0x10U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000010 */\n#define FMC_PMEM3_MEMSET3_5         (0x20U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000020 */\n#define FMC_PMEM3_MEMSET3_6         (0x40U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000040 */\n#define FMC_PMEM3_MEMSET3_7         (0x80U << FMC_PMEM3_MEMSET3_Pos)           /*!< 0x00000080 */\n\n#define FMC_PMEM3_MEMWAIT3_Pos      (8U)                                       \n#define FMC_PMEM3_MEMWAIT3_Msk      (0xFFU << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x0000FF00 */\n#define FMC_PMEM3_MEMWAIT3          FMC_PMEM3_MEMWAIT3_Msk                     /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\n#define FMC_PMEM3_MEMWAIT3_0        (0x01U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000100 */\n#define FMC_PMEM3_MEMWAIT3_1        (0x02U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000200 */\n#define FMC_PMEM3_MEMWAIT3_2        (0x04U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000400 */\n#define FMC_PMEM3_MEMWAIT3_3        (0x08U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00000800 */\n#define FMC_PMEM3_MEMWAIT3_4        (0x10U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00001000 */\n#define FMC_PMEM3_MEMWAIT3_5        (0x20U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00002000 */\n#define FMC_PMEM3_MEMWAIT3_6        (0x40U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00004000 */\n#define FMC_PMEM3_MEMWAIT3_7        (0x80U << FMC_PMEM3_MEMWAIT3_Pos)          /*!< 0x00008000 */\n\n#define FMC_PMEM3_MEMHOLD3_Pos      (16U)                                      \n#define FMC_PMEM3_MEMHOLD3_Msk      (0xFFU << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00FF0000 */\n#define FMC_PMEM3_MEMHOLD3          FMC_PMEM3_MEMHOLD3_Msk                     /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\n#define FMC_PMEM3_MEMHOLD3_0        (0x01U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00010000 */\n#define FMC_PMEM3_MEMHOLD3_1        (0x02U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00020000 */\n#define FMC_PMEM3_MEMHOLD3_2        (0x04U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00040000 */\n#define FMC_PMEM3_MEMHOLD3_3        (0x08U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00080000 */\n#define FMC_PMEM3_MEMHOLD3_4        (0x10U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00100000 */\n#define FMC_PMEM3_MEMHOLD3_5        (0x20U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00200000 */\n#define FMC_PMEM3_MEMHOLD3_6        (0x40U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00400000 */\n#define FMC_PMEM3_MEMHOLD3_7        (0x80U << FMC_PMEM3_MEMHOLD3_Pos)          /*!< 0x00800000 */\n\n#define FMC_PMEM3_MEMHIZ3_Pos       (24U)                                      \n#define FMC_PMEM3_MEMHIZ3_Msk       (0xFFU << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0xFF000000 */\n#define FMC_PMEM3_MEMHIZ3           FMC_PMEM3_MEMHIZ3_Msk                      /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\n#define FMC_PMEM3_MEMHIZ3_0         (0x01U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x01000000 */\n#define FMC_PMEM3_MEMHIZ3_1         (0x02U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x02000000 */\n#define FMC_PMEM3_MEMHIZ3_2         (0x04U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x04000000 */\n#define FMC_PMEM3_MEMHIZ3_3         (0x08U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x08000000 */\n#define FMC_PMEM3_MEMHIZ3_4         (0x10U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x10000000 */\n#define FMC_PMEM3_MEMHIZ3_5         (0x20U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x20000000 */\n#define FMC_PMEM3_MEMHIZ3_6         (0x40U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x40000000 */\n#define FMC_PMEM3_MEMHIZ3_7         (0x80U << FMC_PMEM3_MEMHIZ3_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PMEM4 register  ******************/\n#define FMC_PMEM4_MEMSET4_Pos       (0U)                                       \n#define FMC_PMEM4_MEMSET4_Msk       (0xFFU << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x000000FF */\n#define FMC_PMEM4_MEMSET4           FMC_PMEM4_MEMSET4_Msk                      /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\n#define FMC_PMEM4_MEMSET4_0         (0x01U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000001 */\n#define FMC_PMEM4_MEMSET4_1         (0x02U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000002 */\n#define FMC_PMEM4_MEMSET4_2         (0x04U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000004 */\n#define FMC_PMEM4_MEMSET4_3         (0x08U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000008 */\n#define FMC_PMEM4_MEMSET4_4         (0x10U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000010 */\n#define FMC_PMEM4_MEMSET4_5         (0x20U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000020 */\n#define FMC_PMEM4_MEMSET4_6         (0x40U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000040 */\n#define FMC_PMEM4_MEMSET4_7         (0x80U << FMC_PMEM4_MEMSET4_Pos)           /*!< 0x00000080 */\n\n#define FMC_PMEM4_MEMWAIT4_Pos      (8U)                                       \n#define FMC_PMEM4_MEMWAIT4_Msk      (0xFFU << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x0000FF00 */\n#define FMC_PMEM4_MEMWAIT4          FMC_PMEM4_MEMWAIT4_Msk                     /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\n#define FMC_PMEM4_MEMWAIT4_0        (0x01U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000100 */\n#define FMC_PMEM4_MEMWAIT4_1        (0x02U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000200 */\n#define FMC_PMEM4_MEMWAIT4_2        (0x04U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000400 */\n#define FMC_PMEM4_MEMWAIT4_3        (0x08U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00000800 */\n#define FMC_PMEM4_MEMWAIT4_4        (0x10U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00001000 */\n#define FMC_PMEM4_MEMWAIT4_5        (0x20U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00002000 */\n#define FMC_PMEM4_MEMWAIT4_6        (0x40U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00004000 */\n#define FMC_PMEM4_MEMWAIT4_7        (0x80U << FMC_PMEM4_MEMWAIT4_Pos)          /*!< 0x00008000 */\n\n#define FMC_PMEM4_MEMHOLD4_Pos      (16U)                                      \n#define FMC_PMEM4_MEMHOLD4_Msk      (0xFFU << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00FF0000 */\n#define FMC_PMEM4_MEMHOLD4          FMC_PMEM4_MEMHOLD4_Msk                     /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\n#define FMC_PMEM4_MEMHOLD4_0        (0x01U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00010000 */\n#define FMC_PMEM4_MEMHOLD4_1        (0x02U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00020000 */\n#define FMC_PMEM4_MEMHOLD4_2        (0x04U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00040000 */\n#define FMC_PMEM4_MEMHOLD4_3        (0x08U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00080000 */\n#define FMC_PMEM4_MEMHOLD4_4        (0x10U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00100000 */\n#define FMC_PMEM4_MEMHOLD4_5        (0x20U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00200000 */\n#define FMC_PMEM4_MEMHOLD4_6        (0x40U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00400000 */\n#define FMC_PMEM4_MEMHOLD4_7        (0x80U << FMC_PMEM4_MEMHOLD4_Pos)          /*!< 0x00800000 */\n\n#define FMC_PMEM4_MEMHIZ4_Pos       (24U)                                      \n#define FMC_PMEM4_MEMHIZ4_Msk       (0xFFU << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0xFF000000 */\n#define FMC_PMEM4_MEMHIZ4           FMC_PMEM4_MEMHIZ4_Msk                      /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\n#define FMC_PMEM4_MEMHIZ4_0         (0x01U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x01000000 */\n#define FMC_PMEM4_MEMHIZ4_1         (0x02U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x02000000 */\n#define FMC_PMEM4_MEMHIZ4_2         (0x04U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x04000000 */\n#define FMC_PMEM4_MEMHIZ4_3         (0x08U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x08000000 */\n#define FMC_PMEM4_MEMHIZ4_4         (0x10U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x10000000 */\n#define FMC_PMEM4_MEMHIZ4_5         (0x20U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x20000000 */\n#define FMC_PMEM4_MEMHIZ4_6         (0x40U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x40000000 */\n#define FMC_PMEM4_MEMHIZ4_7         (0x80U << FMC_PMEM4_MEMHIZ4_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PATT2 register  ******************/\n#define FMC_PATT2_ATTSET2_Pos       (0U)                                       \n#define FMC_PATT2_ATTSET2_Msk       (0xFFU << FMC_PATT2_ATTSET2_Pos)           /*!< 0x000000FF */\n#define FMC_PATT2_ATTSET2           FMC_PATT2_ATTSET2_Msk                      /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\n#define FMC_PATT2_ATTSET2_0         (0x01U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000001 */\n#define FMC_PATT2_ATTSET2_1         (0x02U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000002 */\n#define FMC_PATT2_ATTSET2_2         (0x04U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000004 */\n#define FMC_PATT2_ATTSET2_3         (0x08U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000008 */\n#define FMC_PATT2_ATTSET2_4         (0x10U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000010 */\n#define FMC_PATT2_ATTSET2_5         (0x20U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000020 */\n#define FMC_PATT2_ATTSET2_6         (0x40U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000040 */\n#define FMC_PATT2_ATTSET2_7         (0x80U << FMC_PATT2_ATTSET2_Pos)           /*!< 0x00000080 */\n\n#define FMC_PATT2_ATTWAIT2_Pos      (8U)                                       \n#define FMC_PATT2_ATTWAIT2_Msk      (0xFFU << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x0000FF00 */\n#define FMC_PATT2_ATTWAIT2          FMC_PATT2_ATTWAIT2_Msk                     /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\n#define FMC_PATT2_ATTWAIT2_0        (0x01U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000100 */\n#define FMC_PATT2_ATTWAIT2_1        (0x02U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000200 */\n#define FMC_PATT2_ATTWAIT2_2        (0x04U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000400 */\n#define FMC_PATT2_ATTWAIT2_3        (0x08U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00000800 */\n#define FMC_PATT2_ATTWAIT2_4        (0x10U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00001000 */\n#define FMC_PATT2_ATTWAIT2_5        (0x20U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00002000 */\n#define FMC_PATT2_ATTWAIT2_6        (0x40U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00004000 */\n#define FMC_PATT2_ATTWAIT2_7        (0x80U << FMC_PATT2_ATTWAIT2_Pos)          /*!< 0x00008000 */\n\n#define FMC_PATT2_ATTHOLD2_Pos      (16U)                                      \n#define FMC_PATT2_ATTHOLD2_Msk      (0xFFU << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00FF0000 */\n#define FMC_PATT2_ATTHOLD2          FMC_PATT2_ATTHOLD2_Msk                     /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\n#define FMC_PATT2_ATTHOLD2_0        (0x01U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00010000 */\n#define FMC_PATT2_ATTHOLD2_1        (0x02U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00020000 */\n#define FMC_PATT2_ATTHOLD2_2        (0x04U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00040000 */\n#define FMC_PATT2_ATTHOLD2_3        (0x08U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00080000 */\n#define FMC_PATT2_ATTHOLD2_4        (0x10U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00100000 */\n#define FMC_PATT2_ATTHOLD2_5        (0x20U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00200000 */\n#define FMC_PATT2_ATTHOLD2_6        (0x40U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00400000 */\n#define FMC_PATT2_ATTHOLD2_7        (0x80U << FMC_PATT2_ATTHOLD2_Pos)          /*!< 0x00800000 */\n\n#define FMC_PATT2_ATTHIZ2_Pos       (24U)                                      \n#define FMC_PATT2_ATTHIZ2_Msk       (0xFFU << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0xFF000000 */\n#define FMC_PATT2_ATTHIZ2           FMC_PATT2_ATTHIZ2_Msk                      /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\n#define FMC_PATT2_ATTHIZ2_0         (0x01U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x01000000 */\n#define FMC_PATT2_ATTHIZ2_1         (0x02U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x02000000 */\n#define FMC_PATT2_ATTHIZ2_2         (0x04U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x04000000 */\n#define FMC_PATT2_ATTHIZ2_3         (0x08U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x08000000 */\n#define FMC_PATT2_ATTHIZ2_4         (0x10U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x10000000 */\n#define FMC_PATT2_ATTHIZ2_5         (0x20U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x20000000 */\n#define FMC_PATT2_ATTHIZ2_6         (0x40U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x40000000 */\n#define FMC_PATT2_ATTHIZ2_7         (0x80U << FMC_PATT2_ATTHIZ2_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PATT3 register  ******************/\n#define FMC_PATT3_ATTSET3_Pos       (0U)                                       \n#define FMC_PATT3_ATTSET3_Msk       (0xFFU << FMC_PATT3_ATTSET3_Pos)           /*!< 0x000000FF */\n#define FMC_PATT3_ATTSET3           FMC_PATT3_ATTSET3_Msk                      /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\n#define FMC_PATT3_ATTSET3_0         (0x01U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000001 */\n#define FMC_PATT3_ATTSET3_1         (0x02U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000002 */\n#define FMC_PATT3_ATTSET3_2         (0x04U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000004 */\n#define FMC_PATT3_ATTSET3_3         (0x08U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000008 */\n#define FMC_PATT3_ATTSET3_4         (0x10U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000010 */\n#define FMC_PATT3_ATTSET3_5         (0x20U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000020 */\n#define FMC_PATT3_ATTSET3_6         (0x40U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000040 */\n#define FMC_PATT3_ATTSET3_7         (0x80U << FMC_PATT3_ATTSET3_Pos)           /*!< 0x00000080 */\n\n#define FMC_PATT3_ATTWAIT3_Pos      (8U)                                       \n#define FMC_PATT3_ATTWAIT3_Msk      (0xFFU << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x0000FF00 */\n#define FMC_PATT3_ATTWAIT3          FMC_PATT3_ATTWAIT3_Msk                     /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\n#define FMC_PATT3_ATTWAIT3_0        (0x01U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000100 */\n#define FMC_PATT3_ATTWAIT3_1        (0x02U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000200 */\n#define FMC_PATT3_ATTWAIT3_2        (0x04U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000400 */\n#define FMC_PATT3_ATTWAIT3_3        (0x08U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00000800 */\n#define FMC_PATT3_ATTWAIT3_4        (0x10U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00001000 */\n#define FMC_PATT3_ATTWAIT3_5        (0x20U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00002000 */\n#define FMC_PATT3_ATTWAIT3_6        (0x40U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00004000 */\n#define FMC_PATT3_ATTWAIT3_7        (0x80U << FMC_PATT3_ATTWAIT3_Pos)          /*!< 0x00008000 */\n\n#define FMC_PATT3_ATTHOLD3_Pos      (16U)                                      \n#define FMC_PATT3_ATTHOLD3_Msk      (0xFFU << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00FF0000 */\n#define FMC_PATT3_ATTHOLD3          FMC_PATT3_ATTHOLD3_Msk                     /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\n#define FMC_PATT3_ATTHOLD3_0        (0x01U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00010000 */\n#define FMC_PATT3_ATTHOLD3_1        (0x02U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00020000 */\n#define FMC_PATT3_ATTHOLD3_2        (0x04U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00040000 */\n#define FMC_PATT3_ATTHOLD3_3        (0x08U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00080000 */\n#define FMC_PATT3_ATTHOLD3_4        (0x10U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00100000 */\n#define FMC_PATT3_ATTHOLD3_5        (0x20U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00200000 */\n#define FMC_PATT3_ATTHOLD3_6        (0x40U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00400000 */\n#define FMC_PATT3_ATTHOLD3_7        (0x80U << FMC_PATT3_ATTHOLD3_Pos)          /*!< 0x00800000 */\n\n#define FMC_PATT3_ATTHIZ3_Pos       (24U)                                      \n#define FMC_PATT3_ATTHIZ3_Msk       (0xFFU << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0xFF000000 */\n#define FMC_PATT3_ATTHIZ3           FMC_PATT3_ATTHIZ3_Msk                      /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\n#define FMC_PATT3_ATTHIZ3_0         (0x01U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x01000000 */\n#define FMC_PATT3_ATTHIZ3_1         (0x02U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x02000000 */\n#define FMC_PATT3_ATTHIZ3_2         (0x04U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x04000000 */\n#define FMC_PATT3_ATTHIZ3_3         (0x08U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x08000000 */\n#define FMC_PATT3_ATTHIZ3_4         (0x10U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x10000000 */\n#define FMC_PATT3_ATTHIZ3_5         (0x20U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x20000000 */\n#define FMC_PATT3_ATTHIZ3_6         (0x40U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x40000000 */\n#define FMC_PATT3_ATTHIZ3_7         (0x80U << FMC_PATT3_ATTHIZ3_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PATT4 register  ******************/\n#define FMC_PATT4_ATTSET4_Pos       (0U)                                       \n#define FMC_PATT4_ATTSET4_Msk       (0xFFU << FMC_PATT4_ATTSET4_Pos)           /*!< 0x000000FF */\n#define FMC_PATT4_ATTSET4           FMC_PATT4_ATTSET4_Msk                      /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\n#define FMC_PATT4_ATTSET4_0         (0x01U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000001 */\n#define FMC_PATT4_ATTSET4_1         (0x02U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000002 */\n#define FMC_PATT4_ATTSET4_2         (0x04U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000004 */\n#define FMC_PATT4_ATTSET4_3         (0x08U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000008 */\n#define FMC_PATT4_ATTSET4_4         (0x10U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000010 */\n#define FMC_PATT4_ATTSET4_5         (0x20U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000020 */\n#define FMC_PATT4_ATTSET4_6         (0x40U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000040 */\n#define FMC_PATT4_ATTSET4_7         (0x80U << FMC_PATT4_ATTSET4_Pos)           /*!< 0x00000080 */\n\n#define FMC_PATT4_ATTWAIT4_Pos      (8U)                                       \n#define FMC_PATT4_ATTWAIT4_Msk      (0xFFU << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x0000FF00 */\n#define FMC_PATT4_ATTWAIT4          FMC_PATT4_ATTWAIT4_Msk                     /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\n#define FMC_PATT4_ATTWAIT4_0        (0x01U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000100 */\n#define FMC_PATT4_ATTWAIT4_1        (0x02U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000200 */\n#define FMC_PATT4_ATTWAIT4_2        (0x04U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000400 */\n#define FMC_PATT4_ATTWAIT4_3        (0x08U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00000800 */\n#define FMC_PATT4_ATTWAIT4_4        (0x10U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00001000 */\n#define FMC_PATT4_ATTWAIT4_5        (0x20U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00002000 */\n#define FMC_PATT4_ATTWAIT4_6        (0x40U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00004000 */\n#define FMC_PATT4_ATTWAIT4_7        (0x80U << FMC_PATT4_ATTWAIT4_Pos)          /*!< 0x00008000 */\n\n#define FMC_PATT4_ATTHOLD4_Pos      (16U)                                      \n#define FMC_PATT4_ATTHOLD4_Msk      (0xFFU << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00FF0000 */\n#define FMC_PATT4_ATTHOLD4          FMC_PATT4_ATTHOLD4_Msk                     /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\n#define FMC_PATT4_ATTHOLD4_0        (0x01U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00010000 */\n#define FMC_PATT4_ATTHOLD4_1        (0x02U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00020000 */\n#define FMC_PATT4_ATTHOLD4_2        (0x04U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00040000 */\n#define FMC_PATT4_ATTHOLD4_3        (0x08U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00080000 */\n#define FMC_PATT4_ATTHOLD4_4        (0x10U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00100000 */\n#define FMC_PATT4_ATTHOLD4_5        (0x20U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00200000 */\n#define FMC_PATT4_ATTHOLD4_6        (0x40U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00400000 */\n#define FMC_PATT4_ATTHOLD4_7        (0x80U << FMC_PATT4_ATTHOLD4_Pos)          /*!< 0x00800000 */\n\n#define FMC_PATT4_ATTHIZ4_Pos       (24U)                                      \n#define FMC_PATT4_ATTHIZ4_Msk       (0xFFU << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0xFF000000 */\n#define FMC_PATT4_ATTHIZ4           FMC_PATT4_ATTHIZ4_Msk                      /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\n#define FMC_PATT4_ATTHIZ4_0         (0x01U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x01000000 */\n#define FMC_PATT4_ATTHIZ4_1         (0x02U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x02000000 */\n#define FMC_PATT4_ATTHIZ4_2         (0x04U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x04000000 */\n#define FMC_PATT4_ATTHIZ4_3         (0x08U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x08000000 */\n#define FMC_PATT4_ATTHIZ4_4         (0x10U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x10000000 */\n#define FMC_PATT4_ATTHIZ4_5         (0x20U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x20000000 */\n#define FMC_PATT4_ATTHIZ4_6         (0x40U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x40000000 */\n#define FMC_PATT4_ATTHIZ4_7         (0x80U << FMC_PATT4_ATTHIZ4_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PIO4 register  *******************/\n#define FMC_PIO4_IOSET4_Pos         (0U)                                       \n#define FMC_PIO4_IOSET4_Msk         (0xFFU << FMC_PIO4_IOSET4_Pos)             /*!< 0x000000FF */\n#define FMC_PIO4_IOSET4             FMC_PIO4_IOSET4_Msk                        /*!<IOSET4[7:0] bits (I/O 4 setup time) */\n#define FMC_PIO4_IOSET4_0           (0x01U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000001 */\n#define FMC_PIO4_IOSET4_1           (0x02U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000002 */\n#define FMC_PIO4_IOSET4_2           (0x04U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000004 */\n#define FMC_PIO4_IOSET4_3           (0x08U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000008 */\n#define FMC_PIO4_IOSET4_4           (0x10U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000010 */\n#define FMC_PIO4_IOSET4_5           (0x20U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000020 */\n#define FMC_PIO4_IOSET4_6           (0x40U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000040 */\n#define FMC_PIO4_IOSET4_7           (0x80U << FMC_PIO4_IOSET4_Pos)             /*!< 0x00000080 */\n\n#define FMC_PIO4_IOWAIT4_Pos        (8U)                                       \n#define FMC_PIO4_IOWAIT4_Msk        (0xFFU << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x0000FF00 */\n#define FMC_PIO4_IOWAIT4            FMC_PIO4_IOWAIT4_Msk                       /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\n#define FMC_PIO4_IOWAIT4_0          (0x01U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000100 */\n#define FMC_PIO4_IOWAIT4_1          (0x02U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000200 */\n#define FMC_PIO4_IOWAIT4_2          (0x04U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000400 */\n#define FMC_PIO4_IOWAIT4_3          (0x08U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00000800 */\n#define FMC_PIO4_IOWAIT4_4          (0x10U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00001000 */\n#define FMC_PIO4_IOWAIT4_5          (0x20U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00002000 */\n#define FMC_PIO4_IOWAIT4_6          (0x40U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00004000 */\n#define FMC_PIO4_IOWAIT4_7          (0x80U << FMC_PIO4_IOWAIT4_Pos)            /*!< 0x00008000 */\n\n#define FMC_PIO4_IOHOLD4_Pos        (16U)                                      \n#define FMC_PIO4_IOHOLD4_Msk        (0xFFU << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00FF0000 */\n#define FMC_PIO4_IOHOLD4            FMC_PIO4_IOHOLD4_Msk                       /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\n#define FMC_PIO4_IOHOLD4_0          (0x01U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00010000 */\n#define FMC_PIO4_IOHOLD4_1          (0x02U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00020000 */\n#define FMC_PIO4_IOHOLD4_2          (0x04U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00040000 */\n#define FMC_PIO4_IOHOLD4_3          (0x08U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00080000 */\n#define FMC_PIO4_IOHOLD4_4          (0x10U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00100000 */\n#define FMC_PIO4_IOHOLD4_5          (0x20U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00200000 */\n#define FMC_PIO4_IOHOLD4_6          (0x40U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00400000 */\n#define FMC_PIO4_IOHOLD4_7          (0x80U << FMC_PIO4_IOHOLD4_Pos)            /*!< 0x00800000 */\n\n#define FMC_PIO4_IOHIZ4_Pos         (24U)                                      \n#define FMC_PIO4_IOHIZ4_Msk         (0xFFU << FMC_PIO4_IOHIZ4_Pos)             /*!< 0xFF000000 */\n#define FMC_PIO4_IOHIZ4             FMC_PIO4_IOHIZ4_Msk                        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\n#define FMC_PIO4_IOHIZ4_0           (0x01U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x01000000 */\n#define FMC_PIO4_IOHIZ4_1           (0x02U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x02000000 */\n#define FMC_PIO4_IOHIZ4_2           (0x04U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x04000000 */\n#define FMC_PIO4_IOHIZ4_3           (0x08U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x08000000 */\n#define FMC_PIO4_IOHIZ4_4           (0x10U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x10000000 */\n#define FMC_PIO4_IOHIZ4_5           (0x20U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x20000000 */\n#define FMC_PIO4_IOHIZ4_6           (0x40U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x40000000 */\n#define FMC_PIO4_IOHIZ4_7           (0x80U << FMC_PIO4_IOHIZ4_Pos)             /*!< 0x80000000 */\n\n\n/******************  Bit definition for FMC_ECCR2 register  ******************/\n#define FMC_ECCR2_ECC2_Pos          (0U)                                       \n#define FMC_ECCR2_ECC2_Msk          (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos)        /*!< 0xFFFFFFFF */\n#define FMC_ECCR2_ECC2              FMC_ECCR2_ECC2_Msk                         /*!<ECC result */\n\n/******************  Bit definition for FMC_ECCR3 register  ******************/\n#define FMC_ECCR3_ECC3_Pos          (0U)                                       \n#define FMC_ECCR3_ECC3_Msk          (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */\n#define FMC_ECCR3_ECC3              FMC_ECCR3_ECC3_Msk                         /*!<ECC result */\n\n/******************  Bit definition for FMC_SDCR1 register  ******************/\n#define FMC_SDCR1_NC_Pos            (0U)                                       \n#define FMC_SDCR1_NC_Msk            (0x3U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000003 */\n#define FMC_SDCR1_NC                FMC_SDCR1_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */\n#define FMC_SDCR1_NC_0              (0x1U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000001 */\n#define FMC_SDCR1_NC_1              (0x2U << FMC_SDCR1_NC_Pos)                 /*!< 0x00000002 */\n\n#define FMC_SDCR1_NR_Pos            (2U)                                       \n#define FMC_SDCR1_NR_Msk            (0x3U << FMC_SDCR1_NR_Pos)                 /*!< 0x0000000C */\n#define FMC_SDCR1_NR                FMC_SDCR1_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR1_NR_0              (0x1U << FMC_SDCR1_NR_Pos)                 /*!< 0x00000004 */\n#define FMC_SDCR1_NR_1              (0x2U << FMC_SDCR1_NR_Pos)                 /*!< 0x00000008 */\n\n#define FMC_SDCR1_MWID_Pos          (4U)                                       \n#define FMC_SDCR1_MWID_Msk          (0x3U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000030 */\n#define FMC_SDCR1_MWID              FMC_SDCR1_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR1_MWID_0            (0x1U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000010 */\n#define FMC_SDCR1_MWID_1            (0x2U << FMC_SDCR1_MWID_Pos)               /*!< 0x00000020 */\n\n#define FMC_SDCR1_NB_Pos            (6U)                                       \n#define FMC_SDCR1_NB_Msk            (0x1U << FMC_SDCR1_NB_Pos)                 /*!< 0x00000040 */\n#define FMC_SDCR1_NB                FMC_SDCR1_NB_Msk                           /*!<Number of internal bank */\n\n#define FMC_SDCR1_CAS_Pos           (7U)                                       \n#define FMC_SDCR1_CAS_Msk           (0x3U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000180 */\n#define FMC_SDCR1_CAS               FMC_SDCR1_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */\n#define FMC_SDCR1_CAS_0             (0x1U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000080 */\n#define FMC_SDCR1_CAS_1             (0x2U << FMC_SDCR1_CAS_Pos)                /*!< 0x00000100 */\n\n#define FMC_SDCR1_WP_Pos            (9U)                                       \n#define FMC_SDCR1_WP_Msk            (0x1U << FMC_SDCR1_WP_Pos)                 /*!< 0x00000200 */\n#define FMC_SDCR1_WP                FMC_SDCR1_WP_Msk                           /*!<Write protection */\n\n#define FMC_SDCR1_SDCLK_Pos         (10U)                                      \n#define FMC_SDCR1_SDCLK_Msk         (0x3U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000C00 */\n#define FMC_SDCR1_SDCLK             FMC_SDCR1_SDCLK_Msk                        /*!<SDRAM clock configuration */\n#define FMC_SDCR1_SDCLK_0           (0x1U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000400 */\n#define FMC_SDCR1_SDCLK_1           (0x2U << FMC_SDCR1_SDCLK_Pos)              /*!< 0x00000800 */\n\n#define FMC_SDCR1_RBURST_Pos        (12U)                                      \n#define FMC_SDCR1_RBURST_Msk        (0x1U << FMC_SDCR1_RBURST_Pos)             /*!< 0x00001000 */\n#define FMC_SDCR1_RBURST            FMC_SDCR1_RBURST_Msk                       /*!<Read burst */\n\n#define FMC_SDCR1_RPIPE_Pos         (13U)                                      \n#define FMC_SDCR1_RPIPE_Msk         (0x3U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00006000 */\n#define FMC_SDCR1_RPIPE             FMC_SDCR1_RPIPE_Msk                        /*!<Write protection */\n#define FMC_SDCR1_RPIPE_0           (0x1U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00002000 */\n#define FMC_SDCR1_RPIPE_1           (0x2U << FMC_SDCR1_RPIPE_Pos)              /*!< 0x00004000 */\n\n/******************  Bit definition for FMC_SDCR2 register  ******************/\n#define FMC_SDCR2_NC_Pos            (0U)                                       \n#define FMC_SDCR2_NC_Msk            (0x3U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000003 */\n#define FMC_SDCR2_NC                FMC_SDCR2_NC_Msk                           /*!<NC[1:0] bits (Number of column bits) */\n#define FMC_SDCR2_NC_0              (0x1U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000001 */\n#define FMC_SDCR2_NC_1              (0x2U << FMC_SDCR2_NC_Pos)                 /*!< 0x00000002 */\n\n#define FMC_SDCR2_NR_Pos            (2U)                                       \n#define FMC_SDCR2_NR_Msk            (0x3U << FMC_SDCR2_NR_Pos)                 /*!< 0x0000000C */\n#define FMC_SDCR2_NR                FMC_SDCR2_NR_Msk                           /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR2_NR_0              (0x1U << FMC_SDCR2_NR_Pos)                 /*!< 0x00000004 */\n#define FMC_SDCR2_NR_1              (0x2U << FMC_SDCR2_NR_Pos)                 /*!< 0x00000008 */\n\n#define FMC_SDCR2_MWID_Pos          (4U)                                       \n#define FMC_SDCR2_MWID_Msk          (0x3U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000030 */\n#define FMC_SDCR2_MWID              FMC_SDCR2_MWID_Msk                         /*!<NR[1:0] bits (Number of row bits) */\n#define FMC_SDCR2_MWID_0            (0x1U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000010 */\n#define FMC_SDCR2_MWID_1            (0x2U << FMC_SDCR2_MWID_Pos)               /*!< 0x00000020 */\n\n#define FMC_SDCR2_NB_Pos            (6U)                                       \n#define FMC_SDCR2_NB_Msk            (0x1U << FMC_SDCR2_NB_Pos)                 /*!< 0x00000040 */\n#define FMC_SDCR2_NB                FMC_SDCR2_NB_Msk                           /*!<Number of internal bank */\n\n#define FMC_SDCR2_CAS_Pos           (7U)                                       \n#define FMC_SDCR2_CAS_Msk           (0x3U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000180 */\n#define FMC_SDCR2_CAS               FMC_SDCR2_CAS_Msk                          /*!<CAS[1:0] bits (CAS latency) */\n#define FMC_SDCR2_CAS_0             (0x1U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000080 */\n#define FMC_SDCR2_CAS_1             (0x2U << FMC_SDCR2_CAS_Pos)                /*!< 0x00000100 */\n\n#define FMC_SDCR2_WP_Pos            (9U)                                       \n#define FMC_SDCR2_WP_Msk            (0x1U << FMC_SDCR2_WP_Pos)                 /*!< 0x00000200 */\n#define FMC_SDCR2_WP                FMC_SDCR2_WP_Msk                           /*!<Write protection */\n\n#define FMC_SDCR2_SDCLK_Pos         (10U)                                      \n#define FMC_SDCR2_SDCLK_Msk         (0x3U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000C00 */\n#define FMC_SDCR2_SDCLK             FMC_SDCR2_SDCLK_Msk                        /*!<SDCLK[1:0] (SDRAM clock configuration) */\n#define FMC_SDCR2_SDCLK_0           (0x1U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000400 */\n#define FMC_SDCR2_SDCLK_1           (0x2U << FMC_SDCR2_SDCLK_Pos)              /*!< 0x00000800 */\n\n#define FMC_SDCR2_RBURST_Pos        (12U)                                      \n#define FMC_SDCR2_RBURST_Msk        (0x1U << FMC_SDCR2_RBURST_Pos)             /*!< 0x00001000 */\n#define FMC_SDCR2_RBURST            FMC_SDCR2_RBURST_Msk                       /*!<Read burst */\n\n#define FMC_SDCR2_RPIPE_Pos         (13U)                                      \n#define FMC_SDCR2_RPIPE_Msk         (0x3U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00006000 */\n#define FMC_SDCR2_RPIPE             FMC_SDCR2_RPIPE_Msk                        /*!<RPIPE[1:0](Read pipe) */\n#define FMC_SDCR2_RPIPE_0           (0x1U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00002000 */\n#define FMC_SDCR2_RPIPE_1           (0x2U << FMC_SDCR2_RPIPE_Pos)              /*!< 0x00004000 */\n\n/******************  Bit definition for FMC_SDTR1 register  ******************/\n#define FMC_SDTR1_TMRD_Pos          (0U)                                       \n#define FMC_SDTR1_TMRD_Msk          (0xFU << FMC_SDTR1_TMRD_Pos)               /*!< 0x0000000F */\n#define FMC_SDTR1_TMRD              FMC_SDTR1_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */\n#define FMC_SDTR1_TMRD_0            (0x1U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000001 */\n#define FMC_SDTR1_TMRD_1            (0x2U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000002 */\n#define FMC_SDTR1_TMRD_2            (0x4U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000004 */\n#define FMC_SDTR1_TMRD_3            (0x8U << FMC_SDTR1_TMRD_Pos)               /*!< 0x00000008 */\n                                            \n#define FMC_SDTR1_TXSR_Pos          (4U)                                       \n#define FMC_SDTR1_TXSR_Msk          (0xFU << FMC_SDTR1_TXSR_Pos)               /*!< 0x000000F0 */\n#define FMC_SDTR1_TXSR              FMC_SDTR1_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */\n#define FMC_SDTR1_TXSR_0            (0x1U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000010 */\n#define FMC_SDTR1_TXSR_1            (0x2U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000020 */\n#define FMC_SDTR1_TXSR_2            (0x4U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000040 */\n#define FMC_SDTR1_TXSR_3            (0x8U << FMC_SDTR1_TXSR_Pos)               /*!< 0x00000080 */\n\n#define FMC_SDTR1_TRAS_Pos          (8U)                                       \n#define FMC_SDTR1_TRAS_Msk          (0xFU << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000F00 */\n#define FMC_SDTR1_TRAS              FMC_SDTR1_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */\n#define FMC_SDTR1_TRAS_0            (0x1U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000100 */\n#define FMC_SDTR1_TRAS_1            (0x2U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000200 */\n#define FMC_SDTR1_TRAS_2            (0x4U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000400 */\n#define FMC_SDTR1_TRAS_3            (0x8U << FMC_SDTR1_TRAS_Pos)               /*!< 0x00000800 */\n\n#define FMC_SDTR1_TRC_Pos           (12U)                                      \n#define FMC_SDTR1_TRC_Msk           (0xFU << FMC_SDTR1_TRC_Pos)                /*!< 0x0000F000 */\n#define FMC_SDTR1_TRC               FMC_SDTR1_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */\n#define FMC_SDTR1_TRC_0             (0x1U << FMC_SDTR1_TRC_Pos)                /*!< 0x00001000 */\n#define FMC_SDTR1_TRC_1             (0x2U << FMC_SDTR1_TRC_Pos)                /*!< 0x00002000 */\n#define FMC_SDTR1_TRC_2             (0x4U << FMC_SDTR1_TRC_Pos)                /*!< 0x00004000 */\n\n#define FMC_SDTR1_TWR_Pos           (16U)                                      \n#define FMC_SDTR1_TWR_Msk           (0xFU << FMC_SDTR1_TWR_Pos)                /*!< 0x000F0000 */\n#define FMC_SDTR1_TWR               FMC_SDTR1_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */\n#define FMC_SDTR1_TWR_0             (0x1U << FMC_SDTR1_TWR_Pos)                /*!< 0x00010000 */\n#define FMC_SDTR1_TWR_1             (0x2U << FMC_SDTR1_TWR_Pos)                /*!< 0x00020000 */\n#define FMC_SDTR1_TWR_2             (0x4U << FMC_SDTR1_TWR_Pos)                /*!< 0x00040000 */\n\n#define FMC_SDTR1_TRP_Pos           (20U)                                      \n#define FMC_SDTR1_TRP_Msk           (0xFU << FMC_SDTR1_TRP_Pos)                /*!< 0x00F00000 */\n#define FMC_SDTR1_TRP               FMC_SDTR1_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */\n#define FMC_SDTR1_TRP_0             (0x1U << FMC_SDTR1_TRP_Pos)                /*!< 0x00100000 */\n#define FMC_SDTR1_TRP_1             (0x2U << FMC_SDTR1_TRP_Pos)                /*!< 0x00200000 */\n#define FMC_SDTR1_TRP_2             (0x4U << FMC_SDTR1_TRP_Pos)                /*!< 0x00400000 */\n\n#define FMC_SDTR1_TRCD_Pos          (24U)                                      \n#define FMC_SDTR1_TRCD_Msk          (0xFU << FMC_SDTR1_TRCD_Pos)               /*!< 0x0F000000 */\n#define FMC_SDTR1_TRCD              FMC_SDTR1_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */\n#define FMC_SDTR1_TRCD_0            (0x1U << FMC_SDTR1_TRCD_Pos)               /*!< 0x01000000 */\n#define FMC_SDTR1_TRCD_1            (0x2U << FMC_SDTR1_TRCD_Pos)               /*!< 0x02000000 */\n#define FMC_SDTR1_TRCD_2            (0x4U << FMC_SDTR1_TRCD_Pos)               /*!< 0x04000000 */\n\n/******************  Bit definition for FMC_SDTR2 register  ******************/\n#define FMC_SDTR2_TMRD_Pos          (0U)                                       \n#define FMC_SDTR2_TMRD_Msk          (0xFU << FMC_SDTR2_TMRD_Pos)               /*!< 0x0000000F */\n#define FMC_SDTR2_TMRD              FMC_SDTR2_TMRD_Msk                         /*!<TMRD[3:0] bits (Load mode register to active) */\n#define FMC_SDTR2_TMRD_0            (0x1U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000001 */\n#define FMC_SDTR2_TMRD_1            (0x2U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000002 */\n#define FMC_SDTR2_TMRD_2            (0x4U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000004 */\n#define FMC_SDTR2_TMRD_3            (0x8U << FMC_SDTR2_TMRD_Pos)               /*!< 0x00000008 */\n                                            \n#define FMC_SDTR2_TXSR_Pos          (4U)                                       \n#define FMC_SDTR2_TXSR_Msk          (0xFU << FMC_SDTR2_TXSR_Pos)               /*!< 0x000000F0 */\n#define FMC_SDTR2_TXSR              FMC_SDTR2_TXSR_Msk                         /*!<TXSR[3:0] bits (Exit self refresh) */\n#define FMC_SDTR2_TXSR_0            (0x1U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000010 */\n#define FMC_SDTR2_TXSR_1            (0x2U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000020 */\n#define FMC_SDTR2_TXSR_2            (0x4U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000040 */\n#define FMC_SDTR2_TXSR_3            (0x8U << FMC_SDTR2_TXSR_Pos)               /*!< 0x00000080 */\n\n#define FMC_SDTR2_TRAS_Pos          (8U)                                       \n#define FMC_SDTR2_TRAS_Msk          (0xFU << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000F00 */\n#define FMC_SDTR2_TRAS              FMC_SDTR2_TRAS_Msk                         /*!<TRAS[3:0] bits (Self refresh time) */\n#define FMC_SDTR2_TRAS_0            (0x1U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000100 */\n#define FMC_SDTR2_TRAS_1            (0x2U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000200 */\n#define FMC_SDTR2_TRAS_2            (0x4U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000400 */\n#define FMC_SDTR2_TRAS_3            (0x8U << FMC_SDTR2_TRAS_Pos)               /*!< 0x00000800 */\n\n#define FMC_SDTR2_TRC_Pos           (12U)                                      \n#define FMC_SDTR2_TRC_Msk           (0xFU << FMC_SDTR2_TRC_Pos)                /*!< 0x0000F000 */\n#define FMC_SDTR2_TRC               FMC_SDTR2_TRC_Msk                          /*!<TRC[2:0] bits (Row cycle delay) */\n#define FMC_SDTR2_TRC_0             (0x1U << FMC_SDTR2_TRC_Pos)                /*!< 0x00001000 */\n#define FMC_SDTR2_TRC_1             (0x2U << FMC_SDTR2_TRC_Pos)                /*!< 0x00002000 */\n#define FMC_SDTR2_TRC_2             (0x4U << FMC_SDTR2_TRC_Pos)                /*!< 0x00004000 */\n\n#define FMC_SDTR2_TWR_Pos           (16U)                                      \n#define FMC_SDTR2_TWR_Msk           (0xFU << FMC_SDTR2_TWR_Pos)                /*!< 0x000F0000 */\n#define FMC_SDTR2_TWR               FMC_SDTR2_TWR_Msk                          /*!<TRC[2:0] bits (Write recovery delay) */\n#define FMC_SDTR2_TWR_0             (0x1U << FMC_SDTR2_TWR_Pos)                /*!< 0x00010000 */\n#define FMC_SDTR2_TWR_1             (0x2U << FMC_SDTR2_TWR_Pos)                /*!< 0x00020000 */\n#define FMC_SDTR2_TWR_2             (0x4U << FMC_SDTR2_TWR_Pos)                /*!< 0x00040000 */\n\n#define FMC_SDTR2_TRP_Pos           (20U)                                      \n#define FMC_SDTR2_TRP_Msk           (0xFU << FMC_SDTR2_TRP_Pos)                /*!< 0x00F00000 */\n#define FMC_SDTR2_TRP               FMC_SDTR2_TRP_Msk                          /*!<TRP[2:0] bits (Row precharge delay) */\n#define FMC_SDTR2_TRP_0             (0x1U << FMC_SDTR2_TRP_Pos)                /*!< 0x00100000 */\n#define FMC_SDTR2_TRP_1             (0x2U << FMC_SDTR2_TRP_Pos)                /*!< 0x00200000 */\n#define FMC_SDTR2_TRP_2             (0x4U << FMC_SDTR2_TRP_Pos)                /*!< 0x00400000 */\n\n#define FMC_SDTR2_TRCD_Pos          (24U)                                      \n#define FMC_SDTR2_TRCD_Msk          (0xFU << FMC_SDTR2_TRCD_Pos)               /*!< 0x0F000000 */\n#define FMC_SDTR2_TRCD              FMC_SDTR2_TRCD_Msk                         /*!<TRP[2:0] bits (Row to column delay) */\n#define FMC_SDTR2_TRCD_0            (0x1U << FMC_SDTR2_TRCD_Pos)               /*!< 0x01000000 */\n#define FMC_SDTR2_TRCD_1            (0x2U << FMC_SDTR2_TRCD_Pos)               /*!< 0x02000000 */\n#define FMC_SDTR2_TRCD_2            (0x4U << FMC_SDTR2_TRCD_Pos)               /*!< 0x04000000 */\n\n/******************  Bit definition for FMC_SDCMR register  ******************/\n#define FMC_SDCMR_MODE_Pos          (0U)                                       \n#define FMC_SDCMR_MODE_Msk          (0x7U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */\n#define FMC_SDCMR_MODE              FMC_SDCMR_MODE_Msk                         /*!<MODE[2:0] bits (Command mode) */\n#define FMC_SDCMR_MODE_0            (0x1U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000001 */\n#define FMC_SDCMR_MODE_1            (0x2U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000002 */\n#define FMC_SDCMR_MODE_2            (0x4U << FMC_SDCMR_MODE_Pos)               /*!< 0x00000004 */\n                                            \n#define FMC_SDCMR_CTB2_Pos          (3U)                                       \n#define FMC_SDCMR_CTB2_Msk          (0x1U << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */\n#define FMC_SDCMR_CTB2              FMC_SDCMR_CTB2_Msk                         /*!<Command target 2 */\n\n#define FMC_SDCMR_CTB1_Pos          (4U)                                       \n#define FMC_SDCMR_CTB1_Msk          (0x1U << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */\n#define FMC_SDCMR_CTB1              FMC_SDCMR_CTB1_Msk                         /*!<Command target 1 */\n\n#define FMC_SDCMR_NRFS_Pos          (5U)                                       \n#define FMC_SDCMR_NRFS_Msk          (0xFU << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */\n#define FMC_SDCMR_NRFS              FMC_SDCMR_NRFS_Msk                         /*!<NRFS[3:0] bits (Number of auto-refresh) */\n#define FMC_SDCMR_NRFS_0            (0x1U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000020 */\n#define FMC_SDCMR_NRFS_1            (0x2U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000040 */\n#define FMC_SDCMR_NRFS_2            (0x4U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000080 */\n#define FMC_SDCMR_NRFS_3            (0x8U << FMC_SDCMR_NRFS_Pos)               /*!< 0x00000100 */\n\n#define FMC_SDCMR_MRD_Pos           (9U)                                       \n#define FMC_SDCMR_MRD_Msk           (0x1FFFU << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */\n#define FMC_SDCMR_MRD               FMC_SDCMR_MRD_Msk                          /*!<MRD[12:0] bits (Mode register definition) */\n\n/******************  Bit definition for FMC_SDRTR register  ******************/\n#define FMC_SDRTR_CRE_Pos           (0U)                                       \n#define FMC_SDRTR_CRE_Msk           (0x1U << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */\n#define FMC_SDRTR_CRE               FMC_SDRTR_CRE_Msk                          /*!<Clear refresh error flag */\n\n#define FMC_SDRTR_COUNT_Pos         (1U)                                       \n#define FMC_SDRTR_COUNT_Msk         (0x1FFFU << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */\n#define FMC_SDRTR_COUNT             FMC_SDRTR_COUNT_Msk                        /*!<COUNT[12:0] bits (Refresh timer count) */\n\n#define FMC_SDRTR_REIE_Pos          (14U)                                      \n#define FMC_SDRTR_REIE_Msk          (0x1U << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */\n#define FMC_SDRTR_REIE              FMC_SDRTR_REIE_Msk                         /*!<RES interupt enable */\n\n/******************  Bit definition for FMC_SDSR register  ******************/\n#define FMC_SDSR_RE_Pos             (0U)                                       \n#define FMC_SDSR_RE_Msk             (0x1U << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */\n#define FMC_SDSR_RE                 FMC_SDSR_RE_Msk                            /*!<Refresh error flag */\n\n#define FMC_SDSR_MODES1_Pos         (1U)                                       \n#define FMC_SDSR_MODES1_Msk         (0x3U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */\n#define FMC_SDSR_MODES1             FMC_SDSR_MODES1_Msk                        /*!<MODES1[1:0]bits (Status mode for bank 1) */\n#define FMC_SDSR_MODES1_0           (0x1U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000002 */\n#define FMC_SDSR_MODES1_1           (0x2U << FMC_SDSR_MODES1_Pos)              /*!< 0x00000004 */\n\n#define FMC_SDSR_MODES2_Pos         (3U)                                       \n#define FMC_SDSR_MODES2_Msk         (0x3U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */\n#define FMC_SDSR_MODES2             FMC_SDSR_MODES2_Msk                        /*!<MODES2[1:0]bits (Status mode for bank 2) */\n#define FMC_SDSR_MODES2_0           (0x1U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000008 */\n#define FMC_SDSR_MODES2_1           (0x2U << FMC_SDSR_MODES2_Pos)              /*!< 0x00000010 */\n#define FMC_SDSR_BUSY_Pos           (5U)                                       \n#define FMC_SDSR_BUSY_Msk           (0x1U << FMC_SDSR_BUSY_Pos)                /*!< 0x00000020 */\n#define FMC_SDSR_BUSY               FMC_SDSR_BUSY_Msk                          /*!<Busy status */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODE0_Pos             (0U)                                  \n#define GPIO_MODER_MODE0_Msk             (0x3U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000003 */\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODE0_Msk                  \n#define GPIO_MODER_MODE0_0               (0x1U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000001 */\n#define GPIO_MODER_MODE0_1               (0x2U << GPIO_MODER_MODE0_Pos)        /*!< 0x00000002 */\n#define GPIO_MODER_MODE1_Pos             (2U)                                  \n#define GPIO_MODER_MODE1_Msk             (0x3U << GPIO_MODER_MODE1_Pos)        /*!< 0x0000000C */\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODE1_Msk                  \n#define GPIO_MODER_MODE1_0               (0x1U << GPIO_MODER_MODE1_Pos)        /*!< 0x00000004 */\n#define GPIO_MODER_MODE1_1               (0x2U << GPIO_MODER_MODE1_Pos)        /*!< 0x00000008 */\n#define GPIO_MODER_MODE2_Pos             (4U)                                  \n#define GPIO_MODER_MODE2_Msk             (0x3U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000030 */\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODE2_Msk                  \n#define GPIO_MODER_MODE2_0               (0x1U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000010 */\n#define GPIO_MODER_MODE2_1               (0x2U << GPIO_MODER_MODE2_Pos)        /*!< 0x00000020 */\n#define GPIO_MODER_MODE3_Pos             (6U)                                  \n#define GPIO_MODER_MODE3_Msk             (0x3U << GPIO_MODER_MODE3_Pos)        /*!< 0x000000C0 */\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODE3_Msk                  \n#define GPIO_MODER_MODE3_0               (0x1U << GPIO_MODER_MODE3_Pos)        /*!< 0x00000040 */\n#define GPIO_MODER_MODE3_1               (0x2U << GPIO_MODER_MODE3_Pos)        /*!< 0x00000080 */\n#define GPIO_MODER_MODE4_Pos             (8U)                                  \n#define GPIO_MODER_MODE4_Msk             (0x3U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000300 */\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODE4_Msk                  \n#define GPIO_MODER_MODE4_0               (0x1U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000100 */\n#define GPIO_MODER_MODE4_1               (0x2U << GPIO_MODER_MODE4_Pos)        /*!< 0x00000200 */\n#define GPIO_MODER_MODE5_Pos             (10U)                                 \n#define GPIO_MODER_MODE5_Msk             (0x3U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000C00 */\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODE5_Msk                  \n#define GPIO_MODER_MODE5_0               (0x1U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000400 */\n#define GPIO_MODER_MODE5_1               (0x2U << GPIO_MODER_MODE5_Pos)        /*!< 0x00000800 */\n#define GPIO_MODER_MODE6_Pos             (12U)                                 \n#define GPIO_MODER_MODE6_Msk             (0x3U << GPIO_MODER_MODE6_Pos)        /*!< 0x00003000 */\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODE6_Msk                  \n#define GPIO_MODER_MODE6_0               (0x1U << GPIO_MODER_MODE6_Pos)        /*!< 0x00001000 */\n#define GPIO_MODER_MODE6_1               (0x2U << GPIO_MODER_MODE6_Pos)        /*!< 0x00002000 */\n#define GPIO_MODER_MODE7_Pos             (14U)                                 \n#define GPIO_MODER_MODE7_Msk             (0x3U << GPIO_MODER_MODE7_Pos)        /*!< 0x0000C000 */\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODE7_Msk                  \n#define GPIO_MODER_MODE7_0               (0x1U << GPIO_MODER_MODE7_Pos)        /*!< 0x00004000 */\n#define GPIO_MODER_MODE7_1               (0x2U << GPIO_MODER_MODE7_Pos)        /*!< 0x00008000 */\n#define GPIO_MODER_MODE8_Pos             (16U)                                 \n#define GPIO_MODER_MODE8_Msk             (0x3U << GPIO_MODER_MODE8_Pos)        /*!< 0x00030000 */\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODE8_Msk                  \n#define GPIO_MODER_MODE8_0               (0x1U << GPIO_MODER_MODE8_Pos)        /*!< 0x00010000 */\n#define GPIO_MODER_MODE8_1               (0x2U << GPIO_MODER_MODE8_Pos)        /*!< 0x00020000 */\n#define GPIO_MODER_MODE9_Pos             (18U)                                 \n#define GPIO_MODER_MODE9_Msk             (0x3U << GPIO_MODER_MODE9_Pos)        /*!< 0x000C0000 */\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODE9_Msk                  \n#define GPIO_MODER_MODE9_0               (0x1U << GPIO_MODER_MODE9_Pos)        /*!< 0x00040000 */\n#define GPIO_MODER_MODE9_1               (0x2U << GPIO_MODER_MODE9_Pos)        /*!< 0x00080000 */\n#define GPIO_MODER_MODE10_Pos            (20U)                                 \n#define GPIO_MODER_MODE10_Msk            (0x3U << GPIO_MODER_MODE10_Pos)       /*!< 0x00300000 */\n#define GPIO_MODER_MODE10                GPIO_MODER_MODE10_Msk                 \n#define GPIO_MODER_MODE10_0              (0x1U << GPIO_MODER_MODE10_Pos)       /*!< 0x00100000 */\n#define GPIO_MODER_MODE10_1              (0x2U << GPIO_MODER_MODE10_Pos)       /*!< 0x00200000 */\n#define GPIO_MODER_MODE11_Pos            (22U)                                 \n#define GPIO_MODER_MODE11_Msk            (0x3U << GPIO_MODER_MODE11_Pos)       /*!< 0x00C00000 */\n#define GPIO_MODER_MODE11                GPIO_MODER_MODE11_Msk                 \n#define GPIO_MODER_MODE11_0              (0x1U << GPIO_MODER_MODE11_Pos)       /*!< 0x00400000 */\n#define GPIO_MODER_MODE11_1              (0x2U << GPIO_MODER_MODE11_Pos)       /*!< 0x00800000 */\n#define GPIO_MODER_MODE12_Pos            (24U)                                 \n#define GPIO_MODER_MODE12_Msk            (0x3U << GPIO_MODER_MODE12_Pos)       /*!< 0x03000000 */\n#define GPIO_MODER_MODE12                GPIO_MODER_MODE12_Msk                 \n#define GPIO_MODER_MODE12_0              (0x1U << GPIO_MODER_MODE12_Pos)       /*!< 0x01000000 */\n#define GPIO_MODER_MODE12_1              (0x2U << GPIO_MODER_MODE12_Pos)       /*!< 0x02000000 */\n#define GPIO_MODER_MODE13_Pos            (26U)                                 \n#define GPIO_MODER_MODE13_Msk            (0x3U << GPIO_MODER_MODE13_Pos)       /*!< 0x0C000000 */\n#define GPIO_MODER_MODE13                GPIO_MODER_MODE13_Msk                 \n#define GPIO_MODER_MODE13_0              (0x1U << GPIO_MODER_MODE13_Pos)       /*!< 0x04000000 */\n#define GPIO_MODER_MODE13_1              (0x2U << GPIO_MODER_MODE13_Pos)       /*!< 0x08000000 */\n#define GPIO_MODER_MODE14_Pos            (28U)                                 \n#define GPIO_MODER_MODE14_Msk            (0x3U << GPIO_MODER_MODE14_Pos)       /*!< 0x30000000 */\n#define GPIO_MODER_MODE14                GPIO_MODER_MODE14_Msk                 \n#define GPIO_MODER_MODE14_0              (0x1U << GPIO_MODER_MODE14_Pos)       /*!< 0x10000000 */\n#define GPIO_MODER_MODE14_1              (0x2U << GPIO_MODER_MODE14_Pos)       /*!< 0x20000000 */\n#define GPIO_MODER_MODE15_Pos            (30U)                                 \n#define GPIO_MODER_MODE15_Msk            (0x3U << GPIO_MODER_MODE15_Pos)       /*!< 0xC0000000 */\n#define GPIO_MODER_MODE15                GPIO_MODER_MODE15_Msk                 \n#define GPIO_MODER_MODE15_0              (0x1U << GPIO_MODER_MODE15_Pos)       /*!< 0x40000000 */\n#define GPIO_MODER_MODE15_1              (0x2U << GPIO_MODER_MODE15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODER0_Pos            (0U)                                  \n#define GPIO_MODER_MODER0_Msk            (0x3U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk                 \n#define GPIO_MODER_MODER0_0              (0x1U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2U << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)                                  \n#define GPIO_MODER_MODER1_Msk            (0x3U << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk                 \n#define GPIO_MODER_MODER1_0              (0x1U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2U << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)                                  \n#define GPIO_MODER_MODER2_Msk            (0x3U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk                 \n#define GPIO_MODER_MODER2_0              (0x1U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2U << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)                                  \n#define GPIO_MODER_MODER3_Msk            (0x3U << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk                 \n#define GPIO_MODER_MODER3_0              (0x1U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2U << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)                                  \n#define GPIO_MODER_MODER4_Msk            (0x3U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk                 \n#define GPIO_MODER_MODER4_0              (0x1U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2U << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)                                 \n#define GPIO_MODER_MODER5_Msk            (0x3U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk                 \n#define GPIO_MODER_MODER5_0              (0x1U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2U << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)                                 \n#define GPIO_MODER_MODER6_Msk            (0x3U << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk                 \n#define GPIO_MODER_MODER6_0              (0x1U << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2U << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)                                 \n#define GPIO_MODER_MODER7_Msk            (0x3U << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk                 \n#define GPIO_MODER_MODER7_0              (0x1U << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2U << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)                                 \n#define GPIO_MODER_MODER8_Msk            (0x3U << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk                 \n#define GPIO_MODER_MODER8_0              (0x1U << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2U << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)                                 \n#define GPIO_MODER_MODER9_Msk            (0x3U << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk                 \n#define GPIO_MODER_MODER9_0              (0x1U << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2U << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)                                 \n#define GPIO_MODER_MODER10_Msk           (0x3U << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk                \n#define GPIO_MODER_MODER10_0             (0x1U << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2U << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)                                 \n#define GPIO_MODER_MODER11_Msk           (0x3U << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk                \n#define GPIO_MODER_MODER11_0             (0x1U << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2U << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)                                 \n#define GPIO_MODER_MODER12_Msk           (0x3U << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk                \n#define GPIO_MODER_MODER12_0             (0x1U << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2U << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)                                 \n#define GPIO_MODER_MODER13_Msk           (0x3U << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk                \n#define GPIO_MODER_MODER13_0             (0x1U << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2U << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)                                 \n#define GPIO_MODER_MODER14_Msk           (0x3U << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk                \n#define GPIO_MODER_MODER14_0             (0x1U << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2U << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)                                 \n#define GPIO_MODER_MODER15_Msk           (0x3U << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk                \n#define GPIO_MODER_MODER15_0             (0x1U << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2U << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)                                  \n#define GPIO_OTYPER_OT0_Msk              (0x1U << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk                   \n#define GPIO_OTYPER_OT1_Pos              (1U)                                  \n#define GPIO_OTYPER_OT1_Msk              (0x1U << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk                   \n#define GPIO_OTYPER_OT2_Pos              (2U)                                  \n#define GPIO_OTYPER_OT2_Msk              (0x1U << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk                   \n#define GPIO_OTYPER_OT3_Pos              (3U)                                  \n#define GPIO_OTYPER_OT3_Msk              (0x1U << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk                   \n#define GPIO_OTYPER_OT4_Pos              (4U)                                  \n#define GPIO_OTYPER_OT4_Msk              (0x1U << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk                   \n#define GPIO_OTYPER_OT5_Pos              (5U)                                  \n#define GPIO_OTYPER_OT5_Msk              (0x1U << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk                   \n#define GPIO_OTYPER_OT6_Pos              (6U)                                  \n#define GPIO_OTYPER_OT6_Msk              (0x1U << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk                   \n#define GPIO_OTYPER_OT7_Pos              (7U)                                  \n#define GPIO_OTYPER_OT7_Msk              (0x1U << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk                   \n#define GPIO_OTYPER_OT8_Pos              (8U)                                  \n#define GPIO_OTYPER_OT8_Msk              (0x1U << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk                   \n#define GPIO_OTYPER_OT9_Pos              (9U)                                  \n#define GPIO_OTYPER_OT9_Msk              (0x1U << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk                   \n#define GPIO_OTYPER_OT10_Pos             (10U)                                 \n#define GPIO_OTYPER_OT10_Msk             (0x1U << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk                  \n#define GPIO_OTYPER_OT11_Pos             (11U)                                 \n#define GPIO_OTYPER_OT11_Msk             (0x1U << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk                  \n#define GPIO_OTYPER_OT12_Pos             (12U)                                 \n#define GPIO_OTYPER_OT12_Msk             (0x1U << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk                  \n#define GPIO_OTYPER_OT13_Pos             (13U)                                 \n#define GPIO_OTYPER_OT13_Msk             (0x1U << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk                  \n#define GPIO_OTYPER_OT14_Pos             (14U)                                 \n#define GPIO_OTYPER_OT14_Msk             (0x1U << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk                  \n#define GPIO_OTYPER_OT15_Pos             (15U)                                 \n#define GPIO_OTYPER_OT15_Msk             (0x1U << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk                  \n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)                                  \n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk              \n#define GPIO_OSPEEDR_OSPEED0_0           (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)                                  \n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk              \n#define GPIO_OSPEEDR_OSPEED1_0           (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)                                  \n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk              \n#define GPIO_OSPEEDR_OSPEED2_0           (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)                                  \n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk              \n#define GPIO_OSPEEDR_OSPEED3_0           (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)                                  \n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk              \n#define GPIO_OSPEEDR_OSPEED4_0           (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)                                 \n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk              \n#define GPIO_OSPEEDR_OSPEED5_0           (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)                                 \n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk              \n#define GPIO_OSPEEDR_OSPEED6_0           (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)                                 \n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk              \n#define GPIO_OSPEEDR_OSPEED7_0           (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)                                 \n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk              \n#define GPIO_OSPEEDR_OSPEED8_0           (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)                                 \n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk              \n#define GPIO_OSPEEDR_OSPEED9_0           (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)                                 \n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk             \n#define GPIO_OSPEEDR_OSPEED10_0          (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)                                 \n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk             \n#define GPIO_OSPEEDR_OSPEED11_0          (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)                                 \n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk             \n#define GPIO_OSPEEDR_OSPEED12_0          (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)                                 \n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk             \n#define GPIO_OSPEEDR_OSPEED13_0          (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)                                 \n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk             \n#define GPIO_OSPEEDR_OSPEED14_0          (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)                                 \n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk             \n#define GPIO_OSPEEDR_OSPEED15_0          (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)                                  \n#define GPIO_PUPDR_PUPD0_Msk             (0x3U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk                  \n#define GPIO_PUPDR_PUPD0_0               (0x1U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2U << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)                                  \n#define GPIO_PUPDR_PUPD1_Msk             (0x3U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk                  \n#define GPIO_PUPDR_PUPD1_0               (0x1U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2U << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)                                  \n#define GPIO_PUPDR_PUPD2_Msk             (0x3U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk                  \n#define GPIO_PUPDR_PUPD2_0               (0x1U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2U << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)                                  \n#define GPIO_PUPDR_PUPD3_Msk             (0x3U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk                  \n#define GPIO_PUPDR_PUPD3_0               (0x1U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2U << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)                                  \n#define GPIO_PUPDR_PUPD4_Msk             (0x3U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk                  \n#define GPIO_PUPDR_PUPD4_0               (0x1U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2U << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)                                 \n#define GPIO_PUPDR_PUPD5_Msk             (0x3U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk                  \n#define GPIO_PUPDR_PUPD5_0               (0x1U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2U << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)                                 \n#define GPIO_PUPDR_PUPD6_Msk             (0x3U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk                  \n#define GPIO_PUPDR_PUPD6_0               (0x1U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2U << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)                                 \n#define GPIO_PUPDR_PUPD7_Msk             (0x3U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk                  \n#define GPIO_PUPDR_PUPD7_0               (0x1U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2U << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)                                 \n#define GPIO_PUPDR_PUPD8_Msk             (0x3U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk                  \n#define GPIO_PUPDR_PUPD8_0               (0x1U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2U << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)                                 \n#define GPIO_PUPDR_PUPD9_Msk             (0x3U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk                  \n#define GPIO_PUPDR_PUPD9_0               (0x1U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2U << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)                                 \n#define GPIO_PUPDR_PUPD10_Msk            (0x3U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk                 \n#define GPIO_PUPDR_PUPD10_0              (0x1U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2U << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)                                 \n#define GPIO_PUPDR_PUPD11_Msk            (0x3U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk                 \n#define GPIO_PUPDR_PUPD11_0              (0x1U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2U << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)                                 \n#define GPIO_PUPDR_PUPD12_Msk            (0x3U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk                 \n#define GPIO_PUPDR_PUPD12_0              (0x1U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2U << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)                                 \n#define GPIO_PUPDR_PUPD13_Msk            (0x3U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk                 \n#define GPIO_PUPDR_PUPD13_0              (0x1U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2U << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)                                 \n#define GPIO_PUPDR_PUPD14_Msk            (0x3U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk                 \n#define GPIO_PUPDR_PUPD14_0              (0x1U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2U << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)                                 \n#define GPIO_PUPDR_PUPD15_Msk            (0x3U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk                 \n#define GPIO_PUPDR_PUPD15_0              (0x1U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2U << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)                                  \n#define GPIO_IDR_ID0_Msk                 (0x1U << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk                      \n#define GPIO_IDR_ID1_Pos                 (1U)                                  \n#define GPIO_IDR_ID1_Msk                 (0x1U << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk                      \n#define GPIO_IDR_ID2_Pos                 (2U)                                  \n#define GPIO_IDR_ID2_Msk                 (0x1U << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk                      \n#define GPIO_IDR_ID3_Pos                 (3U)                                  \n#define GPIO_IDR_ID3_Msk                 (0x1U << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk                      \n#define GPIO_IDR_ID4_Pos                 (4U)                                  \n#define GPIO_IDR_ID4_Msk                 (0x1U << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk                      \n#define GPIO_IDR_ID5_Pos                 (5U)                                  \n#define GPIO_IDR_ID5_Msk                 (0x1U << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk                      \n#define GPIO_IDR_ID6_Pos                 (6U)                                  \n#define GPIO_IDR_ID6_Msk                 (0x1U << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk                      \n#define GPIO_IDR_ID7_Pos                 (7U)                                  \n#define GPIO_IDR_ID7_Msk                 (0x1U << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk                      \n#define GPIO_IDR_ID8_Pos                 (8U)                                  \n#define GPIO_IDR_ID8_Msk                 (0x1U << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk                      \n#define GPIO_IDR_ID9_Pos                 (9U)                                  \n#define GPIO_IDR_ID9_Msk                 (0x1U << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk                      \n#define GPIO_IDR_ID10_Pos                (10U)                                 \n#define GPIO_IDR_ID10_Msk                (0x1U << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk                     \n#define GPIO_IDR_ID11_Pos                (11U)                                 \n#define GPIO_IDR_ID11_Msk                (0x1U << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk                     \n#define GPIO_IDR_ID12_Pos                (12U)                                 \n#define GPIO_IDR_ID12_Msk                (0x1U << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk                     \n#define GPIO_IDR_ID13_Pos                (13U)                                 \n#define GPIO_IDR_ID13_Msk                (0x1U << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk                     \n#define GPIO_IDR_ID14_Pos                (14U)                                 \n#define GPIO_IDR_ID14_Msk                (0x1U << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk                     \n#define GPIO_IDR_ID15_Pos                (15U)                                 \n#define GPIO_IDR_ID15_Msk                (0x1U << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk                     \n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)                                  \n#define GPIO_ODR_OD0_Msk                 (0x1U << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk                      \n#define GPIO_ODR_OD1_Pos                 (1U)                                  \n#define GPIO_ODR_OD1_Msk                 (0x1U << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk                      \n#define GPIO_ODR_OD2_Pos                 (2U)                                  \n#define GPIO_ODR_OD2_Msk                 (0x1U << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk                      \n#define GPIO_ODR_OD3_Pos                 (3U)                                  \n#define GPIO_ODR_OD3_Msk                 (0x1U << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk                      \n#define GPIO_ODR_OD4_Pos                 (4U)                                  \n#define GPIO_ODR_OD4_Msk                 (0x1U << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk                      \n#define GPIO_ODR_OD5_Pos                 (5U)                                  \n#define GPIO_ODR_OD5_Msk                 (0x1U << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk                      \n#define GPIO_ODR_OD6_Pos                 (6U)                                  \n#define GPIO_ODR_OD6_Msk                 (0x1U << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk                      \n#define GPIO_ODR_OD7_Pos                 (7U)                                  \n#define GPIO_ODR_OD7_Msk                 (0x1U << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk                      \n#define GPIO_ODR_OD8_Pos                 (8U)                                  \n#define GPIO_ODR_OD8_Msk                 (0x1U << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk                      \n#define GPIO_ODR_OD9_Pos                 (9U)                                  \n#define GPIO_ODR_OD9_Msk                 (0x1U << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk                      \n#define GPIO_ODR_OD10_Pos                (10U)                                 \n#define GPIO_ODR_OD10_Msk                (0x1U << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk                     \n#define GPIO_ODR_OD11_Pos                (11U)                                 \n#define GPIO_ODR_OD11_Msk                (0x1U << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk                     \n#define GPIO_ODR_OD12_Pos                (12U)                                 \n#define GPIO_ODR_OD12_Msk                (0x1U << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk                     \n#define GPIO_ODR_OD13_Pos                (13U)                                 \n#define GPIO_ODR_OD13_Msk                (0x1U << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk                     \n#define GPIO_ODR_OD14_Pos                (14U)                                 \n#define GPIO_ODR_OD14_Msk                (0x1U << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk                     \n#define GPIO_ODR_OD15_Pos                (15U)                                 \n#define GPIO_ODR_OD15_Msk                (0x1U << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk                     \n/* Legacy defines */\n#define GPIO_ODR_ODR_0                       GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                       GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                       GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                       GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                       GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                       GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                       GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                       GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                       GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                       GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                      GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                      GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                      GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                      GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                      GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                      GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)                                  \n#define GPIO_BSRR_BS0_Msk                (0x1U << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk                     \n#define GPIO_BSRR_BS1_Pos                (1U)                                  \n#define GPIO_BSRR_BS1_Msk                (0x1U << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk                     \n#define GPIO_BSRR_BS2_Pos                (2U)                                  \n#define GPIO_BSRR_BS2_Msk                (0x1U << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk                     \n#define GPIO_BSRR_BS3_Pos                (3U)                                  \n#define GPIO_BSRR_BS3_Msk                (0x1U << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk                     \n#define GPIO_BSRR_BS4_Pos                (4U)                                  \n#define GPIO_BSRR_BS4_Msk                (0x1U << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk                     \n#define GPIO_BSRR_BS5_Pos                (5U)                                  \n#define GPIO_BSRR_BS5_Msk                (0x1U << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk                     \n#define GPIO_BSRR_BS6_Pos                (6U)                                  \n#define GPIO_BSRR_BS6_Msk                (0x1U << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk                     \n#define GPIO_BSRR_BS7_Pos                (7U)                                  \n#define GPIO_BSRR_BS7_Msk                (0x1U << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk                     \n#define GPIO_BSRR_BS8_Pos                (8U)                                  \n#define GPIO_BSRR_BS8_Msk                (0x1U << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk                     \n#define GPIO_BSRR_BS9_Pos                (9U)                                  \n#define GPIO_BSRR_BS9_Msk                (0x1U << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk                     \n#define GPIO_BSRR_BS10_Pos               (10U)                                 \n#define GPIO_BSRR_BS10_Msk               (0x1U << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk                    \n#define GPIO_BSRR_BS11_Pos               (11U)                                 \n#define GPIO_BSRR_BS11_Msk               (0x1U << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk                    \n#define GPIO_BSRR_BS12_Pos               (12U)                                 \n#define GPIO_BSRR_BS12_Msk               (0x1U << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk                    \n#define GPIO_BSRR_BS13_Pos               (13U)                                 \n#define GPIO_BSRR_BS13_Msk               (0x1U << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk                    \n#define GPIO_BSRR_BS14_Pos               (14U)                                 \n#define GPIO_BSRR_BS14_Msk               (0x1U << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk                    \n#define GPIO_BSRR_BS15_Pos               (15U)                                 \n#define GPIO_BSRR_BS15_Msk               (0x1U << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk                    \n#define GPIO_BSRR_BR0_Pos                (16U)                                 \n#define GPIO_BSRR_BR0_Msk                (0x1U << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk                     \n#define GPIO_BSRR_BR1_Pos                (17U)                                 \n#define GPIO_BSRR_BR1_Msk                (0x1U << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk                     \n#define GPIO_BSRR_BR2_Pos                (18U)                                 \n#define GPIO_BSRR_BR2_Msk                (0x1U << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk                     \n#define GPIO_BSRR_BR3_Pos                (19U)                                 \n#define GPIO_BSRR_BR3_Msk                (0x1U << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk                     \n#define GPIO_BSRR_BR4_Pos                (20U)                                 \n#define GPIO_BSRR_BR4_Msk                (0x1U << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk                     \n#define GPIO_BSRR_BR5_Pos                (21U)                                 \n#define GPIO_BSRR_BR5_Msk                (0x1U << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk                     \n#define GPIO_BSRR_BR6_Pos                (22U)                                 \n#define GPIO_BSRR_BR6_Msk                (0x1U << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk                     \n#define GPIO_BSRR_BR7_Pos                (23U)                                 \n#define GPIO_BSRR_BR7_Msk                (0x1U << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk                     \n#define GPIO_BSRR_BR8_Pos                (24U)                                 \n#define GPIO_BSRR_BR8_Msk                (0x1U << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk                     \n#define GPIO_BSRR_BR9_Pos                (25U)                                 \n#define GPIO_BSRR_BR9_Msk                (0x1U << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk                     \n#define GPIO_BSRR_BR10_Pos               (26U)                                 \n#define GPIO_BSRR_BR10_Msk               (0x1U << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk                    \n#define GPIO_BSRR_BR11_Pos               (27U)                                 \n#define GPIO_BSRR_BR11_Msk               (0x1U << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk                    \n#define GPIO_BSRR_BR12_Pos               (28U)                                 \n#define GPIO_BSRR_BR12_Msk               (0x1U << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk                    \n#define GPIO_BSRR_BR13_Pos               (29U)                                 \n#define GPIO_BSRR_BR13_Msk               (0x1U << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk                    \n#define GPIO_BSRR_BR14_Pos               (30U)                                 \n#define GPIO_BSRR_BR14_Msk               (0x1U << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk                    \n#define GPIO_BSRR_BR15_Pos               (31U)                                 \n#define GPIO_BSRR_BR15_Msk               (0x1U << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk                    \n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)                                  \n#define GPIO_LCKR_LCK0_Msk               (0x1U << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk                    \n#define GPIO_LCKR_LCK1_Pos               (1U)                                  \n#define GPIO_LCKR_LCK1_Msk               (0x1U << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk                    \n#define GPIO_LCKR_LCK2_Pos               (2U)                                  \n#define GPIO_LCKR_LCK2_Msk               (0x1U << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk                    \n#define GPIO_LCKR_LCK3_Pos               (3U)                                  \n#define GPIO_LCKR_LCK3_Msk               (0x1U << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk                    \n#define GPIO_LCKR_LCK4_Pos               (4U)                                  \n#define GPIO_LCKR_LCK4_Msk               (0x1U << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk                    \n#define GPIO_LCKR_LCK5_Pos               (5U)                                  \n#define GPIO_LCKR_LCK5_Msk               (0x1U << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk                    \n#define GPIO_LCKR_LCK6_Pos               (6U)                                  \n#define GPIO_LCKR_LCK6_Msk               (0x1U << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk                    \n#define GPIO_LCKR_LCK7_Pos               (7U)                                  \n#define GPIO_LCKR_LCK7_Msk               (0x1U << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk                    \n#define GPIO_LCKR_LCK8_Pos               (8U)                                  \n#define GPIO_LCKR_LCK8_Msk               (0x1U << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk                    \n#define GPIO_LCKR_LCK9_Pos               (9U)                                  \n#define GPIO_LCKR_LCK9_Msk               (0x1U << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk                    \n#define GPIO_LCKR_LCK10_Pos              (10U)                                 \n#define GPIO_LCKR_LCK10_Msk              (0x1U << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk                   \n#define GPIO_LCKR_LCK11_Pos              (11U)                                 \n#define GPIO_LCKR_LCK11_Msk              (0x1U << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk                   \n#define GPIO_LCKR_LCK12_Pos              (12U)                                 \n#define GPIO_LCKR_LCK12_Msk              (0x1U << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk                   \n#define GPIO_LCKR_LCK13_Pos              (13U)                                 \n#define GPIO_LCKR_LCK13_Msk              (0x1U << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk                   \n#define GPIO_LCKR_LCK14_Pos              (14U)                                 \n#define GPIO_LCKR_LCK14_Msk              (0x1U << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk                   \n#define GPIO_LCKR_LCK15_Pos              (15U)                                 \n#define GPIO_LCKR_LCK15_Msk              (0x1U << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk                   \n#define GPIO_LCKR_LCKK_Pos               (16U)                                 \n#define GPIO_LCKR_LCKK_Msk               (0x1U << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk                    \n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)                                  \n#define GPIO_AFRL_AFSEL0_Msk             (0xFU << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                  \n#define GPIO_AFRL_AFSEL0_0               (0x1U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8U << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)                                  \n#define GPIO_AFRL_AFSEL1_Msk             (0xFU << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                  \n#define GPIO_AFRL_AFSEL1_0               (0x1U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8U << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)                                  \n#define GPIO_AFRL_AFSEL2_Msk             (0xFU << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                  \n#define GPIO_AFRL_AFSEL2_0               (0x1U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8U << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)                                 \n#define GPIO_AFRL_AFSEL3_Msk             (0xFU << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                  \n#define GPIO_AFRL_AFSEL3_0               (0x1U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8U << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)                                 \n#define GPIO_AFRL_AFSEL4_Msk             (0xFU << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                  \n#define GPIO_AFRL_AFSEL4_0               (0x1U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8U << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)                                 \n#define GPIO_AFRL_AFSEL5_Msk             (0xFU << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                  \n#define GPIO_AFRL_AFSEL5_0               (0x1U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8U << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)                                 \n#define GPIO_AFRL_AFSEL6_Msk             (0xFU << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                  \n#define GPIO_AFRL_AFSEL6_0               (0x1U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8U << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)                                 \n#define GPIO_AFRL_AFSEL7_Msk             (0xFU << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                  \n#define GPIO_AFRL_AFSEL7_0               (0x1U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8U << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                    GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                    GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                    GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                    GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                    GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                    GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                    GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                    GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                    GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                    GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                    GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                    GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                    GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                    GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                    GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                    GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                    GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                    GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                    GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                    GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                    GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                    GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                    GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                    GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                    GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                    GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                    GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                    GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                    GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                    GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                    GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                    GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)                                  \n#define GPIO_AFRH_AFSEL8_Msk             (0xFU << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                  \n#define GPIO_AFRH_AFSEL8_0               (0x1U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8U << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)                                  \n#define GPIO_AFRH_AFSEL9_Msk             (0xFU << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                  \n#define GPIO_AFRH_AFSEL9_0               (0x1U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8U << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)                                  \n#define GPIO_AFRH_AFSEL10_Msk            (0xFU << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk                 \n#define GPIO_AFRH_AFSEL10_0              (0x1U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8U << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)                                 \n#define GPIO_AFRH_AFSEL11_Msk            (0xFU << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk                 \n#define GPIO_AFRH_AFSEL11_0              (0x1U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8U << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)                                 \n#define GPIO_AFRH_AFSEL12_Msk            (0xFU << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk                 \n#define GPIO_AFRH_AFSEL12_0              (0x1U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8U << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)                                 \n#define GPIO_AFRH_AFSEL13_Msk            (0xFU << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk                 \n#define GPIO_AFRH_AFSEL13_0              (0x1U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8U << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)                                 \n#define GPIO_AFRH_AFSEL14_Msk            (0xFU << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk                 \n#define GPIO_AFRH_AFSEL14_0              (0x1U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8U << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)                                 \n#define GPIO_AFRH_AFSEL15_Msk            (0xFU << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk                 \n#define GPIO_AFRH_AFSEL15_0              (0x1U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8U << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                    GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                    GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                    GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                    GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                    GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                    GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                    GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                    GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                    GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                    GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                    GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                    GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                    GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                    GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                    GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                    GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                    GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                    GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                    GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                    GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                    GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                    GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                    GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                    GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                    GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                    GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                    GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                    GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                    GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                    GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                    GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                    GPIO_AFRH_AFSEL15_3\n\n/******************  Bits definition for GPIO_BRR register  ******************/\n#define GPIO_BRR_BR0_Pos                 (0U)                                  \n#define GPIO_BRR_BR0_Msk                 (0x1U << GPIO_BRR_BR0_Pos)            /*!< 0x00000001 */\n#define GPIO_BRR_BR0                     GPIO_BRR_BR0_Msk                      \n#define GPIO_BRR_BR1_Pos                 (1U)                                  \n#define GPIO_BRR_BR1_Msk                 (0x1U << GPIO_BRR_BR1_Pos)            /*!< 0x00000002 */\n#define GPIO_BRR_BR1                     GPIO_BRR_BR1_Msk                      \n#define GPIO_BRR_BR2_Pos                 (2U)                                  \n#define GPIO_BRR_BR2_Msk                 (0x1U << GPIO_BRR_BR2_Pos)            /*!< 0x00000004 */\n#define GPIO_BRR_BR2                     GPIO_BRR_BR2_Msk                      \n#define GPIO_BRR_BR3_Pos                 (3U)                                  \n#define GPIO_BRR_BR3_Msk                 (0x1U << GPIO_BRR_BR3_Pos)            /*!< 0x00000008 */\n#define GPIO_BRR_BR3                     GPIO_BRR_BR3_Msk                      \n#define GPIO_BRR_BR4_Pos                 (4U)                                  \n#define GPIO_BRR_BR4_Msk                 (0x1U << GPIO_BRR_BR4_Pos)            /*!< 0x00000010 */\n#define GPIO_BRR_BR4                     GPIO_BRR_BR4_Msk                      \n#define GPIO_BRR_BR5_Pos                 (5U)                                  \n#define GPIO_BRR_BR5_Msk                 (0x1U << GPIO_BRR_BR5_Pos)            /*!< 0x00000020 */\n#define GPIO_BRR_BR5                     GPIO_BRR_BR5_Msk                      \n#define GPIO_BRR_BR6_Pos                 (6U)                                  \n#define GPIO_BRR_BR6_Msk                 (0x1U << GPIO_BRR_BR6_Pos)            /*!< 0x00000040 */\n#define GPIO_BRR_BR6                     GPIO_BRR_BR6_Msk                      \n#define GPIO_BRR_BR7_Pos                 (7U)                                  \n#define GPIO_BRR_BR7_Msk                 (0x1U << GPIO_BRR_BR7_Pos)            /*!< 0x00000080 */\n#define GPIO_BRR_BR7                     GPIO_BRR_BR7_Msk                      \n#define GPIO_BRR_BR8_Pos                 (8U)                                  \n#define GPIO_BRR_BR8_Msk                 (0x1U << GPIO_BRR_BR8_Pos)            /*!< 0x00000100 */\n#define GPIO_BRR_BR8                     GPIO_BRR_BR8_Msk                      \n#define GPIO_BRR_BR9_Pos                 (9U)                                  \n#define GPIO_BRR_BR9_Msk                 (0x1U << GPIO_BRR_BR9_Pos)            /*!< 0x00000200 */\n#define GPIO_BRR_BR9                     GPIO_BRR_BR9_Msk                      \n#define GPIO_BRR_BR10_Pos                (10U)                                 \n#define GPIO_BRR_BR10_Msk                (0x1U << GPIO_BRR_BR10_Pos)           /*!< 0x00000400 */\n#define GPIO_BRR_BR10                    GPIO_BRR_BR10_Msk                     \n#define GPIO_BRR_BR11_Pos                (11U)                                 \n#define GPIO_BRR_BR11_Msk                (0x1U << GPIO_BRR_BR11_Pos)           /*!< 0x00000800 */\n#define GPIO_BRR_BR11                    GPIO_BRR_BR11_Msk                     \n#define GPIO_BRR_BR12_Pos                (12U)                                 \n#define GPIO_BRR_BR12_Msk                (0x1U << GPIO_BRR_BR12_Pos)           /*!< 0x00001000 */\n#define GPIO_BRR_BR12                    GPIO_BRR_BR12_Msk                     \n#define GPIO_BRR_BR13_Pos                (13U)                                 \n#define GPIO_BRR_BR13_Msk                (0x1U << GPIO_BRR_BR13_Pos)           /*!< 0x00002000 */\n#define GPIO_BRR_BR13                    GPIO_BRR_BR13_Msk                     \n#define GPIO_BRR_BR14_Pos                (14U)                                 \n#define GPIO_BRR_BR14_Msk                (0x1U << GPIO_BRR_BR14_Pos)           /*!< 0x00004000 */\n#define GPIO_BRR_BR14                    GPIO_BRR_BR14_Msk                     \n#define GPIO_BRR_BR15_Pos                (15U)                                 \n#define GPIO_BRR_BR15_Msk                (0x1U << GPIO_BRR_BR15_Pos)           /*!< 0x00008000 */\n#define GPIO_BRR_BR15                    GPIO_BRR_BR15_Msk                     \n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)                                         \n#define I2C_CR1_PE_Msk            (0x1U << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)                                         \n#define I2C_CR1_SMBUS_Msk         (0x1U << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)                                         \n#define I2C_CR1_SMBTYPE_Msk       (0x1U << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)                                         \n#define I2C_CR1_ENARP_Msk         (0x1U << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)                                         \n#define I2C_CR1_ENPEC_Msk         (0x1U << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)                                         \n#define I2C_CR1_ENGC_Msk          (0x1U << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)                                         \n#define I2C_CR1_NOSTRETCH_Msk     (0x1U << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)                                         \n#define I2C_CR1_START_Msk         (0x1U << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)                                         \n#define I2C_CR1_STOP_Msk          (0x1U << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)                                        \n#define I2C_CR1_ACK_Msk           (0x1U << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)                                        \n#define I2C_CR1_POS_Msk           (0x1U << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)                                        \n#define I2C_CR1_PEC_Msk           (0x1U << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)                                        \n#define I2C_CR1_ALERT_Msk         (0x1U << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)                                        \n#define I2C_CR1_SWRST_Msk         (0x1U << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)                                         \n#define I2C_CR2_FREQ_Msk          (0x3FU << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20U << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)                                         \n#define I2C_CR2_ITERREN_Msk       (0x1U << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)                                         \n#define I2C_CR2_ITEVTEN_Msk       (0x1U << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)                                        \n#define I2C_CR2_ITBUFEN_Msk       (0x1U << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)                                        \n#define I2C_CR2_DMAEN_Msk         (0x1U << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)                                        \n#define I2C_CR2_LAST_Msk          (0x1U << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)                                         \n#define I2C_OAR1_ADD0_Msk         (0x1U << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)                                         \n#define I2C_OAR1_ADD1_Msk         (0x1U << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)                                         \n#define I2C_OAR1_ADD2_Msk         (0x1U << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)                                         \n#define I2C_OAR1_ADD3_Msk         (0x1U << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)                                         \n#define I2C_OAR1_ADD4_Msk         (0x1U << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)                                         \n#define I2C_OAR1_ADD5_Msk         (0x1U << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)                                         \n#define I2C_OAR1_ADD6_Msk         (0x1U << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)                                         \n#define I2C_OAR1_ADD7_Msk         (0x1U << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)                                         \n#define I2C_OAR1_ADD8_Msk         (0x1U << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)                                         \n#define I2C_OAR1_ADD9_Msk         (0x1U << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)                                        \n#define I2C_OAR1_ADDMODE_Msk      (0x1U << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)                                         \n#define I2C_OAR2_ENDUAL_Msk       (0x1U << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)                                         \n#define I2C_OAR2_ADD2_Msk         (0x7FU << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)                                         \n#define I2C_DR_DR_Msk             (0xFFU << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)                                         \n#define I2C_SR1_SB_Msk            (0x1U << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)                                         \n#define I2C_SR1_ADDR_Msk          (0x1U << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)                                         \n#define I2C_SR1_BTF_Msk           (0x1U << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)                                         \n#define I2C_SR1_ADD10_Msk         (0x1U << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)                                         \n#define I2C_SR1_STOPF_Msk         (0x1U << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)                                         \n#define I2C_SR1_RXNE_Msk          (0x1U << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)                                         \n#define I2C_SR1_TXE_Msk           (0x1U << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)                                         \n#define I2C_SR1_BERR_Msk          (0x1U << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)                                         \n#define I2C_SR1_ARLO_Msk          (0x1U << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)                                        \n#define I2C_SR1_AF_Msk            (0x1U << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)                                        \n#define I2C_SR1_OVR_Msk           (0x1U << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)                                        \n#define I2C_SR1_PECERR_Msk        (0x1U << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)                                        \n#define I2C_SR1_TIMEOUT_Msk       (0x1U << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)                                        \n#define I2C_SR1_SMBALERT_Msk      (0x1U << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)                                         \n#define I2C_SR2_MSL_Msk           (0x1U << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)                                         \n#define I2C_SR2_BUSY_Msk          (0x1U << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)                                         \n#define I2C_SR2_TRA_Msk           (0x1U << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)                                         \n#define I2C_SR2_GENCALL_Msk       (0x1U << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)                                         \n#define I2C_SR2_SMBDEFAULT_Msk    (0x1U << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)                                         \n#define I2C_SR2_SMBHOST_Msk       (0x1U << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)                                         \n#define I2C_SR2_DUALF_Msk         (0x1U << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)                                         \n#define I2C_SR2_PEC_Msk           (0xFFU << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)                                         \n#define I2C_CCR_CCR_Msk           (0xFFFU << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)                                        \n#define I2C_CCR_DUTY_Msk          (0x1U << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)                                        \n#define I2C_CCR_FS_Msk            (0x1U << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)                                         \n#define I2C_TRISE_TRISE_Msk       (0x3FU << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************  Bit definition for I2C_FLTR register  *******************/\n#define I2C_FLTR_DNF_Pos          (0U)                                         \n#define I2C_FLTR_DNF_Msk          (0xFU << I2C_FLTR_DNF_Pos)                   /*!< 0x0000000F */\n#define I2C_FLTR_DNF              I2C_FLTR_DNF_Msk                             /*!<Digital Noise Filter */\n#define I2C_FLTR_ANOFF_Pos        (4U)                                         \n#define I2C_FLTR_ANOFF_Msk        (0x1U << I2C_FLTR_ANOFF_Pos)                 /*!< 0x00000010 */\n#define I2C_FLTR_ANOFF            I2C_FLTR_ANOFF_Msk                           /*!<Analog Noise Filter OFF */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)                                               \n#define IWDG_KR_KEY_Msk     (0xFFFFU << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)                                               \n#define IWDG_PR_PR_Msk      (0x7U << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1U << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2U << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4U << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)                                               \n#define IWDG_RLR_RL_Msk     (0xFFFU << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)                                               \n#define IWDG_SR_PVU_Msk     (0x1U << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)                                               \n#define IWDG_SR_RVU_Msk     (0x1U << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      LCD-TFT Display Controller (LTDC)                     */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for LTDC_SSCR register  *****************/\n\n#define LTDC_SSCR_VSH_Pos            (0U)                                      \n#define LTDC_SSCR_VSH_Msk            (0x7FFU << LTDC_SSCR_VSH_Pos)             /*!< 0x000007FF */\n#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height */\n#define LTDC_SSCR_HSW_Pos            (16U)                                     \n#define LTDC_SSCR_HSW_Msk            (0xFFFU << LTDC_SSCR_HSW_Pos)             /*!< 0x0FFF0000 */\n#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */\n\n/********************  Bit definition for LTDC_BPCR register  *****************/\n\n#define LTDC_BPCR_AVBP_Pos           (0U)                                      \n#define LTDC_BPCR_AVBP_Msk           (0x7FFU << LTDC_BPCR_AVBP_Pos)            /*!< 0x000007FF */\n#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch */\n#define LTDC_BPCR_AHBP_Pos           (16U)                                     \n#define LTDC_BPCR_AHBP_Msk           (0xFFFU << LTDC_BPCR_AHBP_Pos)            /*!< 0x0FFF0000 */\n#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */\n\n/********************  Bit definition for LTDC_AWCR register  *****************/\n\n#define LTDC_AWCR_AAH_Pos            (0U)                                      \n#define LTDC_AWCR_AAH_Msk            (0x7FFU << LTDC_AWCR_AAH_Pos)             /*!< 0x000007FF */\n#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */\n#define LTDC_AWCR_AAW_Pos            (16U)                                     \n#define LTDC_AWCR_AAW_Msk            (0xFFFU << LTDC_AWCR_AAW_Pos)             /*!< 0x0FFF0000 */\n#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */\n\n/********************  Bit definition for LTDC_TWCR register  *****************/\n\n#define LTDC_TWCR_TOTALH_Pos         (0U)                                      \n#define LTDC_TWCR_TOTALH_Msk         (0x7FFU << LTDC_TWCR_TOTALH_Pos)          /*!< 0x000007FF */\n#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */\n#define LTDC_TWCR_TOTALW_Pos         (16U)                                     \n#define LTDC_TWCR_TOTALW_Msk         (0xFFFU << LTDC_TWCR_TOTALW_Pos)          /*!< 0x0FFF0000 */\n#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */\n\n/********************  Bit definition for LTDC_GCR register  ******************/\n\n#define LTDC_GCR_LTDCEN_Pos          (0U)                                      \n#define LTDC_GCR_LTDCEN_Msk          (0x1U << LTDC_GCR_LTDCEN_Pos)             /*!< 0x00000001 */\n#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit */\n#define LTDC_GCR_DBW_Pos             (4U)                                      \n#define LTDC_GCR_DBW_Msk             (0x7U << LTDC_GCR_DBW_Pos)                /*!< 0x00000070 */\n#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width */\n#define LTDC_GCR_DGW_Pos             (8U)                                      \n#define LTDC_GCR_DGW_Msk             (0x7U << LTDC_GCR_DGW_Pos)                /*!< 0x00000700 */\n#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width */\n#define LTDC_GCR_DRW_Pos             (12U)                                     \n#define LTDC_GCR_DRW_Msk             (0x7U << LTDC_GCR_DRW_Pos)                /*!< 0x00007000 */\n#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width */\n#define LTDC_GCR_DEN_Pos             (16U)                                     \n#define LTDC_GCR_DEN_Msk             (0x1U << LTDC_GCR_DEN_Pos)                /*!< 0x00010000 */\n#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable */\n#define LTDC_GCR_PCPOL_Pos           (28U)                                     \n#define LTDC_GCR_PCPOL_Msk           (0x1U << LTDC_GCR_PCPOL_Pos)              /*!< 0x10000000 */\n#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity */\n#define LTDC_GCR_DEPOL_Pos           (29U)                                     \n#define LTDC_GCR_DEPOL_Msk           (0x1U << LTDC_GCR_DEPOL_Pos)              /*!< 0x20000000 */\n#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity */\n#define LTDC_GCR_VSPOL_Pos           (30U)                                     \n#define LTDC_GCR_VSPOL_Msk           (0x1U << LTDC_GCR_VSPOL_Pos)              /*!< 0x40000000 */\n#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity */\n#define LTDC_GCR_HSPOL_Pos           (31U)                                     \n#define LTDC_GCR_HSPOL_Msk           (0x1U << LTDC_GCR_HSPOL_Pos)              /*!< 0x80000000 */\n#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */\n\n/* Legacy defines */\n#define LTDC_GCR_DTEN                       LTDC_GCR_DEN\n\n/********************  Bit definition for LTDC_SRCR register  *****************/\n\n#define LTDC_SRCR_IMR_Pos            (0U)                                      \n#define LTDC_SRCR_IMR_Msk            (0x1U << LTDC_SRCR_IMR_Pos)               /*!< 0x00000001 */\n#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload */\n#define LTDC_SRCR_VBR_Pos            (1U)                                      \n#define LTDC_SRCR_VBR_Msk            (0x1U << LTDC_SRCR_VBR_Pos)               /*!< 0x00000002 */\n#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */\n\n/********************  Bit definition for LTDC_BCCR register  *****************/\n\n#define LTDC_BCCR_BCBLUE_Pos         (0U)                                      \n#define LTDC_BCCR_BCBLUE_Msk         (0xFFU << LTDC_BCCR_BCBLUE_Pos)           /*!< 0x000000FF */\n#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value */\n#define LTDC_BCCR_BCGREEN_Pos        (8U)                                      \n#define LTDC_BCCR_BCGREEN_Msk        (0xFFU << LTDC_BCCR_BCGREEN_Pos)          /*!< 0x0000FF00 */\n#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */\n#define LTDC_BCCR_BCRED_Pos          (16U)                                     \n#define LTDC_BCCR_BCRED_Msk          (0xFFU << LTDC_BCCR_BCRED_Pos)            /*!< 0x00FF0000 */\n#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value */\n\n/********************  Bit definition for LTDC_IER register  ******************/\n\n#define LTDC_IER_LIE_Pos             (0U)                                      \n#define LTDC_IER_LIE_Msk             (0x1U << LTDC_IER_LIE_Pos)                /*!< 0x00000001 */\n#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable */\n#define LTDC_IER_FUIE_Pos            (1U)                                      \n#define LTDC_IER_FUIE_Msk            (0x1U << LTDC_IER_FUIE_Pos)               /*!< 0x00000002 */\n#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable */\n#define LTDC_IER_TERRIE_Pos          (2U)                                      \n#define LTDC_IER_TERRIE_Msk          (0x1U << LTDC_IER_TERRIE_Pos)             /*!< 0x00000004 */\n#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable */\n#define LTDC_IER_RRIE_Pos            (3U)                                      \n#define LTDC_IER_RRIE_Msk            (0x1U << LTDC_IER_RRIE_Pos)               /*!< 0x00000008 */\n#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */\n\n/********************  Bit definition for LTDC_ISR register  ******************/\n\n#define LTDC_ISR_LIF_Pos             (0U)                                      \n#define LTDC_ISR_LIF_Msk             (0x1U << LTDC_ISR_LIF_Pos)                /*!< 0x00000001 */\n#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */\n#define LTDC_ISR_FUIF_Pos            (1U)                                      \n#define LTDC_ISR_FUIF_Msk            (0x1U << LTDC_ISR_FUIF_Pos)               /*!< 0x00000002 */\n#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */\n#define LTDC_ISR_TERRIF_Pos          (2U)                                      \n#define LTDC_ISR_TERRIF_Msk          (0x1U << LTDC_ISR_TERRIF_Pos)             /*!< 0x00000004 */\n#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */\n#define LTDC_ISR_RRIF_Pos            (3U)                                      \n#define LTDC_ISR_RRIF_Msk            (0x1U << LTDC_ISR_RRIF_Pos)               /*!< 0x00000008 */\n#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */\n\n/********************  Bit definition for LTDC_ICR register  ******************/\n\n#define LTDC_ICR_CLIF_Pos            (0U)                                      \n#define LTDC_ICR_CLIF_Msk            (0x1U << LTDC_ICR_CLIF_Pos)               /*!< 0x00000001 */\n#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */\n#define LTDC_ICR_CFUIF_Pos           (1U)                                      \n#define LTDC_ICR_CFUIF_Msk           (0x1U << LTDC_ICR_CFUIF_Pos)              /*!< 0x00000002 */\n#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */\n#define LTDC_ICR_CTERRIF_Pos         (2U)                                      \n#define LTDC_ICR_CTERRIF_Msk         (0x1U << LTDC_ICR_CTERRIF_Pos)            /*!< 0x00000004 */\n#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */\n#define LTDC_ICR_CRRIF_Pos           (3U)                                      \n#define LTDC_ICR_CRRIF_Msk           (0x1U << LTDC_ICR_CRRIF_Pos)              /*!< 0x00000008 */\n#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */\n\n/********************  Bit definition for LTDC_LIPCR register  ****************/\n\n#define LTDC_LIPCR_LIPOS_Pos         (0U)                                      \n#define LTDC_LIPCR_LIPOS_Msk         (0x7FFU << LTDC_LIPCR_LIPOS_Pos)          /*!< 0x000007FF */\n#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */\n\n/********************  Bit definition for LTDC_CPSR register  *****************/\n\n#define LTDC_CPSR_CYPOS_Pos          (0U)                                      \n#define LTDC_CPSR_CYPOS_Msk          (0xFFFFU << LTDC_CPSR_CYPOS_Pos)          /*!< 0x0000FFFF */\n#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */\n#define LTDC_CPSR_CXPOS_Pos          (16U)                                     \n#define LTDC_CPSR_CXPOS_Msk          (0xFFFFU << LTDC_CPSR_CXPOS_Pos)          /*!< 0xFFFF0000 */\n#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */\n\n/********************  Bit definition for LTDC_CDSR register  *****************/\n\n#define LTDC_CDSR_VDES_Pos           (0U)                                      \n#define LTDC_CDSR_VDES_Msk           (0x1U << LTDC_CDSR_VDES_Pos)              /*!< 0x00000001 */\n#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status */\n#define LTDC_CDSR_HDES_Pos           (1U)                                      \n#define LTDC_CDSR_HDES_Msk           (0x1U << LTDC_CDSR_HDES_Pos)              /*!< 0x00000002 */\n#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status */\n#define LTDC_CDSR_VSYNCS_Pos         (2U)                                      \n#define LTDC_CDSR_VSYNCS_Msk         (0x1U << LTDC_CDSR_VSYNCS_Pos)            /*!< 0x00000004 */\n#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status */\n#define LTDC_CDSR_HSYNCS_Pos         (3U)                                      \n#define LTDC_CDSR_HSYNCS_Msk         (0x1U << LTDC_CDSR_HSYNCS_Pos)            /*!< 0x00000008 */\n#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */\n\n/********************  Bit definition for LTDC_LxCR register  *****************/\n\n#define LTDC_LxCR_LEN_Pos            (0U)                                      \n#define LTDC_LxCR_LEN_Msk            (0x1U << LTDC_LxCR_LEN_Pos)               /*!< 0x00000001 */\n#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable */\n#define LTDC_LxCR_COLKEN_Pos         (1U)                                      \n#define LTDC_LxCR_COLKEN_Msk         (0x1U << LTDC_LxCR_COLKEN_Pos)            /*!< 0x00000002 */\n#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable */\n#define LTDC_LxCR_CLUTEN_Pos         (4U)                                      \n#define LTDC_LxCR_CLUTEN_Msk         (0x1U << LTDC_LxCR_CLUTEN_Pos)            /*!< 0x00000010 */\n#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */\n\n/********************  Bit definition for LTDC_LxWHPCR register  **************/\n\n#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)                                      \n#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos)      /*!< 0x00000FFF */\n#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */\n#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)                                     \n#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos)     /*!< 0xFFFF0000 */\n#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position */\n\n/********************  Bit definition for LTDC_LxWVPCR register  **************/\n\n#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)                                      \n#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos)      /*!< 0x00000FFF */\n#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */\n#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)                                     \n#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos)     /*!< 0xFFFF0000 */\n#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position */\n\n/********************  Bit definition for LTDC_LxCKCR register  ***************/\n\n#define LTDC_LxCKCR_CKBLUE_Pos       (0U)                                      \n#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFU << LTDC_LxCKCR_CKBLUE_Pos)         /*!< 0x000000FF */\n#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value */\n#define LTDC_LxCKCR_CKGREEN_Pos      (8U)                                      \n#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFU << LTDC_LxCKCR_CKGREEN_Pos)        /*!< 0x0000FF00 */\n#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */\n#define LTDC_LxCKCR_CKRED_Pos        (16U)                                     \n#define LTDC_LxCKCR_CKRED_Msk        (0xFFU << LTDC_LxCKCR_CKRED_Pos)          /*!< 0x00FF0000 */\n#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value */\n\n/********************  Bit definition for LTDC_LxPFCR register  ***************/\n\n#define LTDC_LxPFCR_PF_Pos           (0U)                                      \n#define LTDC_LxPFCR_PF_Msk           (0x7U << LTDC_LxPFCR_PF_Pos)              /*!< 0x00000007 */\n#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */\n\n/********************  Bit definition for LTDC_LxCACR register  ***************/\n\n#define LTDC_LxCACR_CONSTA_Pos       (0U)                                      \n#define LTDC_LxCACR_CONSTA_Msk       (0xFFU << LTDC_LxCACR_CONSTA_Pos)         /*!< 0x000000FF */\n#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */\n\n/********************  Bit definition for LTDC_LxDCCR register  ***************/\n\n#define LTDC_LxDCCR_DCBLUE_Pos       (0U)                                      \n#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFU << LTDC_LxDCCR_DCBLUE_Pos)         /*!< 0x000000FF */\n#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue */\n#define LTDC_LxDCCR_DCGREEN_Pos      (8U)                                      \n#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFU << LTDC_LxDCCR_DCGREEN_Pos)        /*!< 0x0000FF00 */\n#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */\n#define LTDC_LxDCCR_DCRED_Pos        (16U)                                     \n#define LTDC_LxDCCR_DCRED_Msk        (0xFFU << LTDC_LxDCCR_DCRED_Pos)          /*!< 0x00FF0000 */\n#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red */\n#define LTDC_LxDCCR_DCALPHA_Pos      (24U)                                     \n#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFU << LTDC_LxDCCR_DCALPHA_Pos)        /*!< 0xFF000000 */\n#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */\n                                \n/********************  Bit definition for LTDC_LxBFCR register  ***************/\n\n#define LTDC_LxBFCR_BF2_Pos          (0U)                                      \n#define LTDC_LxBFCR_BF2_Msk          (0x7U << LTDC_LxBFCR_BF2_Pos)             /*!< 0x00000007 */\n#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */\n#define LTDC_LxBFCR_BF1_Pos          (8U)                                      \n#define LTDC_LxBFCR_BF1_Msk          (0x7U << LTDC_LxBFCR_BF1_Pos)             /*!< 0x00000700 */\n#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */\n\n/********************  Bit definition for LTDC_LxCFBAR register  **************/\n\n#define LTDC_LxCFBAR_CFBADD_Pos      (0U)                                      \n#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos)  /*!< 0xFFFFFFFF */\n#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */\n\n/********************  Bit definition for LTDC_LxCFBLR register  **************/\n\n#define LTDC_LxCFBLR_CFBLL_Pos       (0U)                                      \n#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos)       /*!< 0x00001FFF */\n#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length */\n#define LTDC_LxCFBLR_CFBP_Pos        (16U)                                     \n#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos)        /*!< 0x1FFF0000 */\n#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */\n\n/********************  Bit definition for LTDC_LxCFBLNR register  *************/\n\n#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)                                      \n#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos)     /*!< 0x000007FF */\n#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */\n\n/********************  Bit definition for LTDC_LxCLUTWR register  *************/\n\n#define LTDC_LxCLUTWR_BLUE_Pos       (0U)                                      \n#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFU << LTDC_LxCLUTWR_BLUE_Pos)         /*!< 0x000000FF */\n#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value */\n#define LTDC_LxCLUTWR_GREEN_Pos      (8U)                                      \n#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFU << LTDC_LxCLUTWR_GREEN_Pos)        /*!< 0x0000FF00 */\n#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value */\n#define LTDC_LxCLUTWR_RED_Pos        (16U)                                     \n#define LTDC_LxCLUTWR_RED_Msk        (0xFFU << LTDC_LxCLUTWR_RED_Pos)          /*!< 0x00FF0000 */\n#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value */\n#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)                                     \n#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos)      /*!< 0xFF000000 */\n#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)                                            \n#define PWR_CR_LPDS_Msk        (0x1U << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)                                            \n#define PWR_CR_PDDS_Msk        (0x1U << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)                                            \n#define PWR_CR_CWUF_Msk        (0x1U << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)                                            \n#define PWR_CR_CSBF_Msk        (0x1U << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)                                            \n#define PWR_CR_PVDE_Msk        (0x1U << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)                                            \n#define PWR_CR_PLS_Msk         (0x7U << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1U << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2U << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4U << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)                                            \n#define PWR_CR_DBP_Msk         (0x1U << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)                                            \n#define PWR_CR_FPDS_Msk        (0x1U << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_LPLVDS_Pos      (10U)                                           \n#define PWR_CR_LPLVDS_Msk      (0x1U << PWR_CR_LPLVDS_Pos)                     /*!< 0x00000400 */\n#define PWR_CR_LPLVDS          PWR_CR_LPLVDS_Msk                               /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */\n#define PWR_CR_MRLVDS_Pos      (11U)                                           \n#define PWR_CR_MRLVDS_Msk      (0x1U << PWR_CR_MRLVDS_Pos)                     /*!< 0x00000800 */\n#define PWR_CR_MRLVDS          PWR_CR_MRLVDS_Msk                               /*!< Main regulator Low Voltage Scaling in Stop mode            */\n#define PWR_CR_ADCDC1_Pos      (13U)                                           \n#define PWR_CR_ADCDC1_Msk      (0x1U << PWR_CR_ADCDC1_Pos)                     /*!< 0x00002000 */\n#define PWR_CR_ADCDC1          PWR_CR_ADCDC1_Msk                               /*!< Refer to AN4073 on how to use this bit                     */ \n#define PWR_CR_VOS_Pos         (14U)                                           \n#define PWR_CR_VOS_Msk         (0x3U << PWR_CR_VOS_Pos)                        /*!< 0x0000C000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR_VOS_0           0x00004000U                                     /*!< Bit 0 */\n#define PWR_CR_VOS_1           0x00008000U                                     /*!< Bit 1 */\n#define PWR_CR_ODEN_Pos        (16U)                                           \n#define PWR_CR_ODEN_Msk        (0x1U << PWR_CR_ODEN_Pos)                       /*!< 0x00010000 */\n#define PWR_CR_ODEN            PWR_CR_ODEN_Msk                                 /*!< Over Drive enable                   */\n#define PWR_CR_ODSWEN_Pos      (17U)                                           \n#define PWR_CR_ODSWEN_Msk      (0x1U << PWR_CR_ODSWEN_Pos)                     /*!< 0x00020000 */\n#define PWR_CR_ODSWEN          PWR_CR_ODSWEN_Msk                               /*!< Over Drive switch enabled           */\n#define PWR_CR_UDEN_Pos        (18U)                                           \n#define PWR_CR_UDEN_Msk        (0x3U << PWR_CR_UDEN_Pos)                       /*!< 0x000C0000 */\n#define PWR_CR_UDEN            PWR_CR_UDEN_Msk                                 /*!< Under Drive enable in stop mode     */\n#define PWR_CR_UDEN_0          (0x1U << PWR_CR_UDEN_Pos)                       /*!< 0x00040000 */\n#define PWR_CR_UDEN_1          (0x2U << PWR_CR_UDEN_Pos)                       /*!< 0x00080000 */\n\n/* Legacy define */\n#define  PWR_CR_PMODE                        PWR_CR_VOS\n#define  PWR_CR_LPUDS                        PWR_CR_LPLVDS     /*!< Low-Power Regulator in deepsleep under-drive mode        */\n#define  PWR_CR_MRUDS                        PWR_CR_MRLVDS     /*!< Main regulator in deepsleep under-drive mode             */\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)                                            \n#define PWR_CSR_WUF_Msk        (0x1U << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)                                            \n#define PWR_CSR_SBF_Msk        (0x1U << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)                                            \n#define PWR_CSR_PVDO_Msk       (0x1U << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)                                            \n#define PWR_CSR_BRR_Msk        (0x1U << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP_Pos       (8U)                                            \n#define PWR_CSR_EWUP_Msk       (0x1U << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */\n#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */\n#define PWR_CSR_BRE_Pos        (9U)                                            \n#define PWR_CSR_BRE_Msk        (0x1U << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)                                           \n#define PWR_CSR_VOSRDY_Msk     (0x1U << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n#define PWR_CSR_ODRDY_Pos      (16U)                                           \n#define PWR_CSR_ODRDY_Msk      (0x1U << PWR_CSR_ODRDY_Pos)                     /*!< 0x00010000 */\n#define PWR_CSR_ODRDY          PWR_CSR_ODRDY_Msk                               /*!< Over Drive generator ready                       */\n#define PWR_CSR_ODSWRDY_Pos    (17U)                                           \n#define PWR_CSR_ODSWRDY_Msk    (0x1U << PWR_CSR_ODSWRDY_Pos)                   /*!< 0x00020000 */\n#define PWR_CSR_ODSWRDY        PWR_CSR_ODSWRDY_Msk                             /*!< Over Drive Switch ready                          */\n#define PWR_CSR_UDRDY_Pos      (18U)                                           \n#define PWR_CSR_UDRDY_Msk      (0x3U << PWR_CSR_UDRDY_Pos)                     /*!< 0x000C0000 */\n#define PWR_CSR_UDRDY          PWR_CSR_UDRDY_Msk                               /*!< Under Drive ready                                */\n/* Legacy define */\n#define  PWR_CSR_UDSWRDY                     PWR_CSR_UDRDY\n\n/* Legacy define */\n#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)                                \n#define RCC_CR_HSION_Msk                   (0x1U << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk                    \n#define RCC_CR_HSIRDY_Pos                  (1U)                                \n#define RCC_CR_HSIRDY_Msk                  (0x1U << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk                   \n\n#define RCC_CR_HSITRIM_Pos                 (3U)                                \n#define RCC_CR_HSITRIM_Msk                 (0x1FU << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk                  \n#define RCC_CR_HSITRIM_0                   (0x01U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10U << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)                                \n#define RCC_CR_HSICAL_Msk                  (0xFFU << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk                   \n#define RCC_CR_HSICAL_0                    (0x01U << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02U << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04U << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08U << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10U << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20U << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40U << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80U << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)                               \n#define RCC_CR_HSEON_Msk                   (0x1U << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk                    \n#define RCC_CR_HSERDY_Pos                  (17U)                               \n#define RCC_CR_HSERDY_Msk                  (0x1U << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk                   \n#define RCC_CR_HSEBYP_Pos                  (18U)                               \n#define RCC_CR_HSEBYP_Msk                  (0x1U << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk                   \n#define RCC_CR_CSSON_Pos                   (19U)                               \n#define RCC_CR_CSSON_Msk                   (0x1U << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk                    \n#define RCC_CR_PLLON_Pos                   (24U)                               \n#define RCC_CR_PLLON_Msk                   (0x1U << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk                    \n#define RCC_CR_PLLRDY_Pos                  (25U)                               \n#define RCC_CR_PLLRDY_Msk                  (0x1U << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk                   \n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)                               \n#define RCC_CR_PLLI2SON_Msk                (0x1U << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk                 \n#define RCC_CR_PLLI2SRDY_Pos               (27U)                               \n#define RCC_CR_PLLI2SRDY_Msk               (0x1U << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk                \n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLSAI_SUPPORT                                                     /*!< Support PLLSAI oscillator */\n\n#define RCC_CR_PLLSAION_Pos                (28U)                               \n#define RCC_CR_PLLSAION_Msk                (0x1U << RCC_CR_PLLSAION_Pos)       /*!< 0x10000000 */\n#define RCC_CR_PLLSAION                    RCC_CR_PLLSAION_Msk                 \n#define RCC_CR_PLLSAIRDY_Pos               (29U)                               \n#define RCC_CR_PLLSAIRDY_Msk               (0x1U << RCC_CR_PLLSAIRDY_Pos)      /*!< 0x20000000 */\n#define RCC_CR_PLLSAIRDY                   RCC_CR_PLLSAIRDY_Msk                \n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)                                \n#define RCC_PLLCFGR_PLLM_Msk               (0x3FU << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk                \n#define RCC_PLLCFGR_PLLM_0                 (0x01U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20U << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)                                \n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFU << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk                \n#define RCC_PLLCFGR_PLLN_0                 (0x001U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100U << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)                               \n#define RCC_PLLCFGR_PLLP_Msk               (0x3U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk                \n#define RCC_PLLCFGR_PLLP_0                 (0x1U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2U << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)                               \n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1U << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk              \n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)                               \n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk          \n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U                         \n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)                               \n#define RCC_PLLCFGR_PLLQ_Msk               (0xFU << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk                \n#define RCC_PLLCFGR_PLLQ_0                 (0x1U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8U << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)                                \n#define RCC_CFGR_SW_Msk                    (0x3U << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1U << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2U << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)                                \n#define RCC_CFGR_SWS_Msk                   (0x3U << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1U << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2U << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)                                \n#define RCC_CFGR_HPRE_Msk                  (0xFU << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8U << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)                               \n#define RCC_CFGR_PPRE1_Msk                 (0x7U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4U << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)                               \n#define RCC_CFGR_PPRE2_Msk                 (0x7U << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4U << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)                               \n#define RCC_CFGR_RTCPRE_Msk                (0x1FU << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk                 \n#define RCC_CFGR_RTCPRE_0                  (0x01U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10U << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)                               \n#define RCC_CFGR_MCO1_Msk                  (0x3U << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk                   \n#define RCC_CFGR_MCO1_0                    (0x1U << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2U << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n#define RCC_CFGR_I2SSRC_Pos                (23U)                               \n#define RCC_CFGR_I2SSRC_Msk                (0x1U << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */\n#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk                 \n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)                               \n#define RCC_CFGR_MCO1PRE_Msk               (0x7U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk                \n#define RCC_CFGR_MCO1PRE_0                 (0x1U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4U << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)                               \n#define RCC_CFGR_MCO2PRE_Msk               (0x7U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk                \n#define RCC_CFGR_MCO2PRE_0                 (0x1U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4U << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)                               \n#define RCC_CFGR_MCO2_Msk                  (0x3U << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk                   \n#define RCC_CFGR_MCO2_0                    (0x1U << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2U << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)                                \n#define RCC_CIR_LSIRDYF_Msk                (0x1U << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk                 \n#define RCC_CIR_LSERDYF_Pos                (1U)                                \n#define RCC_CIR_LSERDYF_Msk                (0x1U << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk                 \n#define RCC_CIR_HSIRDYF_Pos                (2U)                                \n#define RCC_CIR_HSIRDYF_Msk                (0x1U << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk                 \n#define RCC_CIR_HSERDYF_Pos                (3U)                                \n#define RCC_CIR_HSERDYF_Msk                (0x1U << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk                 \n#define RCC_CIR_PLLRDYF_Pos                (4U)                                \n#define RCC_CIR_PLLRDYF_Msk                (0x1U << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk                 \n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)                                \n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1U << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk              \n\n#define RCC_CIR_PLLSAIRDYF_Pos             (6U)                                \n#define RCC_CIR_PLLSAIRDYF_Msk             (0x1U << RCC_CIR_PLLSAIRDYF_Pos)    /*!< 0x00000040 */\n#define RCC_CIR_PLLSAIRDYF                 RCC_CIR_PLLSAIRDYF_Msk              \n#define RCC_CIR_CSSF_Pos                   (7U)                                \n#define RCC_CIR_CSSF_Msk                   (0x1U << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk                    \n#define RCC_CIR_LSIRDYIE_Pos               (8U)                                \n#define RCC_CIR_LSIRDYIE_Msk               (0x1U << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk                \n#define RCC_CIR_LSERDYIE_Pos               (9U)                                \n#define RCC_CIR_LSERDYIE_Msk               (0x1U << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk                \n#define RCC_CIR_HSIRDYIE_Pos               (10U)                               \n#define RCC_CIR_HSIRDYIE_Msk               (0x1U << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk                \n#define RCC_CIR_HSERDYIE_Pos               (11U)                               \n#define RCC_CIR_HSERDYIE_Msk               (0x1U << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk                \n#define RCC_CIR_PLLRDYIE_Pos               (12U)                               \n#define RCC_CIR_PLLRDYIE_Msk               (0x1U << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk                \n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)                               \n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1U << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk             \n\n#define RCC_CIR_PLLSAIRDYIE_Pos            (14U)                               \n#define RCC_CIR_PLLSAIRDYIE_Msk            (0x1U << RCC_CIR_PLLSAIRDYIE_Pos)   /*!< 0x00004000 */\n#define RCC_CIR_PLLSAIRDYIE                RCC_CIR_PLLSAIRDYIE_Msk             \n#define RCC_CIR_LSIRDYC_Pos                (16U)                               \n#define RCC_CIR_LSIRDYC_Msk                (0x1U << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk                 \n#define RCC_CIR_LSERDYC_Pos                (17U)                               \n#define RCC_CIR_LSERDYC_Msk                (0x1U << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk                 \n#define RCC_CIR_HSIRDYC_Pos                (18U)                               \n#define RCC_CIR_HSIRDYC_Msk                (0x1U << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk                 \n#define RCC_CIR_HSERDYC_Pos                (19U)                               \n#define RCC_CIR_HSERDYC_Msk                (0x1U << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk                 \n#define RCC_CIR_PLLRDYC_Pos                (20U)                               \n#define RCC_CIR_PLLRDYC_Msk                (0x1U << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk                 \n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)                               \n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1U << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk              \n#define RCC_CIR_PLLSAIRDYC_Pos             (22U)                               \n#define RCC_CIR_PLLSAIRDYC_Msk             (0x1U << RCC_CIR_PLLSAIRDYC_Pos)    /*!< 0x00400000 */\n#define RCC_CIR_PLLSAIRDYC                 RCC_CIR_PLLSAIRDYC_Msk              \n\n#define RCC_CIR_CSSC_Pos                   (23U)                               \n#define RCC_CIR_CSSC_Msk                   (0x1U << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk                    \n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)                                \n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk           \n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)                                \n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk           \n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)                                \n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk           \n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)                                \n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk           \n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)                                \n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk           \n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)                                \n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk           \n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)                                \n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk           \n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)                                \n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk           \n#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)                                \n#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\n#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk           \n#define RCC_AHB1RSTR_GPIOJRST_Pos          (9U)                                \n#define RCC_AHB1RSTR_GPIOJRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */\n#define RCC_AHB1RSTR_GPIOJRST              RCC_AHB1RSTR_GPIOJRST_Msk           \n#define RCC_AHB1RSTR_GPIOKRST_Pos          (10U)                               \n#define RCC_AHB1RSTR_GPIOKRST_Msk          (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */\n#define RCC_AHB1RSTR_GPIOKRST              RCC_AHB1RSTR_GPIOKRST_Msk           \n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)                               \n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1U << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk             \n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)                               \n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1U << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk            \n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)                               \n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1U << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk            \n#define RCC_AHB1RSTR_DMA2DRST_Pos          (23U)                               \n#define RCC_AHB1RSTR_DMA2DRST_Msk          (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */\n#define RCC_AHB1RSTR_DMA2DRST              RCC_AHB1RSTR_DMA2DRST_Msk           \n#define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)                               \n#define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */\n#define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk          \n#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)                               \n#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1U << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */\n#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk            \n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)                                \n#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1U << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk            \n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)                                \n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1U << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk             \n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)                                \n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk           \n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FMCRST_Pos            (0U)                                \n#define RCC_AHB3RSTR_FMCRST_Msk            (0x1U << RCC_AHB3RSTR_FMCRST_Pos)   /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FMCRST                RCC_AHB3RSTR_FMCRST_Msk             \n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)                                \n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1U << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk            \n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)                                \n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1U << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk            \n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)                                \n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1U << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk            \n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)                                \n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1U << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk            \n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)                                \n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1U << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk            \n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)                                \n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1U << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk            \n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)                                \n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk           \n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)                                \n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk           \n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)                                \n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk           \n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)                               \n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1U << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk            \n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)                               \n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1U << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk            \n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)                               \n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1U << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk            \n#define RCC_APB1RSTR_USART2RST_Pos         (17U)                               \n#define RCC_APB1RSTR_USART2RST_Msk         (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk          \n#define RCC_APB1RSTR_USART3RST_Pos         (18U)                               \n#define RCC_APB1RSTR_USART3RST_Msk         (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk          \n#define RCC_APB1RSTR_UART4RST_Pos          (19U)                               \n#define RCC_APB1RSTR_UART4RST_Msk          (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk           \n#define RCC_APB1RSTR_UART5RST_Pos          (20U)                               \n#define RCC_APB1RSTR_UART5RST_Msk          (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk           \n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)                               \n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1U << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk            \n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)                               \n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1U << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk            \n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)                               \n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1U << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk            \n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)                               \n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1U << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk            \n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)                               \n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1U << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk            \n#define RCC_APB1RSTR_PWRRST_Pos            (28U)                               \n#define RCC_APB1RSTR_PWRRST_Msk            (0x1U << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk             \n#define RCC_APB1RSTR_DACRST_Pos            (29U)                               \n#define RCC_APB1RSTR_DACRST_Msk            (0x1U << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk             \n#define RCC_APB1RSTR_UART7RST_Pos          (30U)                               \n#define RCC_APB1RSTR_UART7RST_Msk          (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */\n#define RCC_APB1RSTR_UART7RST              RCC_APB1RSTR_UART7RST_Msk           \n#define RCC_APB1RSTR_UART8RST_Pos          (31U)                               \n#define RCC_APB1RSTR_UART8RST_Msk          (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */\n#define RCC_APB1RSTR_UART8RST              RCC_APB1RSTR_UART8RST_Msk           \n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)                                \n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1U << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk            \n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)                                \n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1U << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk            \n#define RCC_APB2RSTR_USART1RST_Pos         (4U)                                \n#define RCC_APB2RSTR_USART1RST_Msk         (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk          \n#define RCC_APB2RSTR_USART6RST_Pos         (5U)                                \n#define RCC_APB2RSTR_USART6RST_Msk         (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk          \n#define RCC_APB2RSTR_ADCRST_Pos            (8U)                                \n#define RCC_APB2RSTR_ADCRST_Msk            (0x1U << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk             \n#define RCC_APB2RSTR_SDIORST_Pos           (11U)                               \n#define RCC_APB2RSTR_SDIORST_Msk           (0x1U << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk            \n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)                               \n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1U << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk            \n#define RCC_APB2RSTR_SPI4RST_Pos           (13U)                               \n#define RCC_APB2RSTR_SPI4RST_Msk           (0x1U << RCC_APB2RSTR_SPI4RST_Pos)  /*!< 0x00002000 */\n#define RCC_APB2RSTR_SPI4RST               RCC_APB2RSTR_SPI4RST_Msk            \n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)                               \n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk          \n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)                               \n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1U << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk            \n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)                               \n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk           \n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)                               \n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk           \n#define RCC_APB2RSTR_SPI5RST_Pos           (20U)                               \n#define RCC_APB2RSTR_SPI5RST_Msk           (0x1U << RCC_APB2RSTR_SPI5RST_Pos)  /*!< 0x00100000 */\n#define RCC_APB2RSTR_SPI5RST               RCC_APB2RSTR_SPI5RST_Msk            \n#define RCC_APB2RSTR_SPI6RST_Pos           (21U)                               \n#define RCC_APB2RSTR_SPI6RST_Msk           (0x1U << RCC_APB2RSTR_SPI6RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB2RSTR_SPI6RST               RCC_APB2RSTR_SPI6RST_Msk            \n#define RCC_APB2RSTR_SAI1RST_Pos           (22U)                               \n#define RCC_APB2RSTR_SAI1RST_Msk           (0x1U << RCC_APB2RSTR_SAI1RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB2RSTR_SAI1RST               RCC_APB2RSTR_SAI1RST_Msk            \n#define RCC_APB2RSTR_LTDCRST_Pos           (26U)                               \n#define RCC_APB2RSTR_LTDCRST_Msk           (0x1U << RCC_APB2RSTR_LTDCRST_Pos)  /*!< 0x04000000 */\n#define RCC_APB2RSTR_LTDCRST               RCC_APB2RSTR_LTDCRST_Msk            \n\n/* Old SPI1RST bit definition, maintained for legacy purpose */\n#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)                                \n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1U << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk             \n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)                                \n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1U << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk             \n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)                                \n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1U << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk             \n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)                                \n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1U << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk             \n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)                                \n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1U << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk             \n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)                                \n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1U << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk             \n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)                                \n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1U << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk             \n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)                                \n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1U << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk             \n#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)                                \n#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1U << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */\n#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk             \n#define RCC_AHB1ENR_GPIOJEN_Pos            (9U)                                \n#define RCC_AHB1ENR_GPIOJEN_Msk            (0x1U << RCC_AHB1ENR_GPIOJEN_Pos)   /*!< 0x00000200 */\n#define RCC_AHB1ENR_GPIOJEN                RCC_AHB1ENR_GPIOJEN_Msk             \n#define RCC_AHB1ENR_GPIOKEN_Pos            (10U)                               \n#define RCC_AHB1ENR_GPIOKEN_Msk            (0x1U << RCC_AHB1ENR_GPIOKEN_Pos)   /*!< 0x00000400 */\n#define RCC_AHB1ENR_GPIOKEN                RCC_AHB1ENR_GPIOKEN_Msk             \n#define RCC_AHB1ENR_CRCEN_Pos              (12U)                               \n#define RCC_AHB1ENR_CRCEN_Msk              (0x1U << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk               \n#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)                               \n#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk           \n#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)                               \n#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */\n#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk        \n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)                               \n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1U << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk              \n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)                               \n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1U << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk              \n#define RCC_AHB1ENR_DMA2DEN_Pos            (23U)                               \n#define RCC_AHB1ENR_DMA2DEN_Msk            (0x1U << RCC_AHB1ENR_DMA2DEN_Pos)   /*!< 0x00800000 */\n#define RCC_AHB1ENR_DMA2DEN                RCC_AHB1ENR_DMA2DEN_Msk             \n#define RCC_AHB1ENR_ETHMACEN_Pos           (25U)                               \n#define RCC_AHB1ENR_ETHMACEN_Msk           (0x1U << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */\n#define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk            \n#define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)                               \n#define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */\n#define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk          \n#define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)                               \n#define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */\n#define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk          \n#define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)                               \n#define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk         \n#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)                               \n#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1U << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */\n#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk             \n#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)                               \n#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk         \n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_DCMIEN_Pos             (0U)                                \n#define RCC_AHB2ENR_DCMIEN_Msk             (0x1U << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk              \n#define RCC_AHB2ENR_RNGEN_Pos              (6U)                                \n#define RCC_AHB2ENR_RNGEN_Msk              (0x1U << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk               \n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)                                \n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1U << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk             \n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FMCEN_Pos              (0U)                                \n#define RCC_AHB3ENR_FMCEN_Msk              (0x1U << RCC_AHB3ENR_FMCEN_Pos)     /*!< 0x00000001 */\n#define RCC_AHB3ENR_FMCEN                  RCC_AHB3ENR_FMCEN_Msk               \n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)                                \n#define RCC_APB1ENR_TIM2EN_Msk             (0x1U << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk              \n#define RCC_APB1ENR_TIM3EN_Pos             (1U)                                \n#define RCC_APB1ENR_TIM3EN_Msk             (0x1U << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk              \n#define RCC_APB1ENR_TIM4EN_Pos             (2U)                                \n#define RCC_APB1ENR_TIM4EN_Msk             (0x1U << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk              \n#define RCC_APB1ENR_TIM5EN_Pos             (3U)                                \n#define RCC_APB1ENR_TIM5EN_Msk             (0x1U << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk              \n#define RCC_APB1ENR_TIM6EN_Pos             (4U)                                \n#define RCC_APB1ENR_TIM6EN_Msk             (0x1U << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk              \n#define RCC_APB1ENR_TIM7EN_Pos             (5U)                                \n#define RCC_APB1ENR_TIM7EN_Msk             (0x1U << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk              \n#define RCC_APB1ENR_TIM12EN_Pos            (6U)                                \n#define RCC_APB1ENR_TIM12EN_Msk            (0x1U << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk             \n#define RCC_APB1ENR_TIM13EN_Pos            (7U)                                \n#define RCC_APB1ENR_TIM13EN_Msk            (0x1U << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk             \n#define RCC_APB1ENR_TIM14EN_Pos            (8U)                                \n#define RCC_APB1ENR_TIM14EN_Msk            (0x1U << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk             \n#define RCC_APB1ENR_WWDGEN_Pos             (11U)                               \n#define RCC_APB1ENR_WWDGEN_Msk             (0x1U << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk              \n#define RCC_APB1ENR_SPI2EN_Pos             (14U)                               \n#define RCC_APB1ENR_SPI2EN_Msk             (0x1U << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk              \n#define RCC_APB1ENR_SPI3EN_Pos             (15U)                               \n#define RCC_APB1ENR_SPI3EN_Msk             (0x1U << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk              \n#define RCC_APB1ENR_USART2EN_Pos           (17U)                               \n#define RCC_APB1ENR_USART2EN_Msk           (0x1U << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk            \n#define RCC_APB1ENR_USART3EN_Pos           (18U)                               \n#define RCC_APB1ENR_USART3EN_Msk           (0x1U << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk            \n#define RCC_APB1ENR_UART4EN_Pos            (19U)                               \n#define RCC_APB1ENR_UART4EN_Msk            (0x1U << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk             \n#define RCC_APB1ENR_UART5EN_Pos            (20U)                               \n#define RCC_APB1ENR_UART5EN_Msk            (0x1U << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk             \n#define RCC_APB1ENR_I2C1EN_Pos             (21U)                               \n#define RCC_APB1ENR_I2C1EN_Msk             (0x1U << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk              \n#define RCC_APB1ENR_I2C2EN_Pos             (22U)                               \n#define RCC_APB1ENR_I2C2EN_Msk             (0x1U << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk              \n#define RCC_APB1ENR_I2C3EN_Pos             (23U)                               \n#define RCC_APB1ENR_I2C3EN_Msk             (0x1U << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk              \n#define RCC_APB1ENR_CAN1EN_Pos             (25U)                               \n#define RCC_APB1ENR_CAN1EN_Msk             (0x1U << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk              \n#define RCC_APB1ENR_CAN2EN_Pos             (26U)                               \n#define RCC_APB1ENR_CAN2EN_Msk             (0x1U << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk              \n#define RCC_APB1ENR_PWREN_Pos              (28U)                               \n#define RCC_APB1ENR_PWREN_Msk              (0x1U << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk               \n#define RCC_APB1ENR_DACEN_Pos              (29U)                               \n#define RCC_APB1ENR_DACEN_Msk              (0x1U << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk               \n#define RCC_APB1ENR_UART7EN_Pos            (30U)                               \n#define RCC_APB1ENR_UART7EN_Msk            (0x1U << RCC_APB1ENR_UART7EN_Pos)   /*!< 0x40000000 */\n#define RCC_APB1ENR_UART7EN                RCC_APB1ENR_UART7EN_Msk             \n#define RCC_APB1ENR_UART8EN_Pos            (31U)                               \n#define RCC_APB1ENR_UART8EN_Msk            (0x1U << RCC_APB1ENR_UART8EN_Pos)   /*!< 0x80000000 */\n#define RCC_APB1ENR_UART8EN                RCC_APB1ENR_UART8EN_Msk             \n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)                                \n#define RCC_APB2ENR_TIM1EN_Msk             (0x1U << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk              \n#define RCC_APB2ENR_TIM8EN_Pos             (1U)                                \n#define RCC_APB2ENR_TIM8EN_Msk             (0x1U << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk              \n#define RCC_APB2ENR_USART1EN_Pos           (4U)                                \n#define RCC_APB2ENR_USART1EN_Msk           (0x1U << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk            \n#define RCC_APB2ENR_USART6EN_Pos           (5U)                                \n#define RCC_APB2ENR_USART6EN_Msk           (0x1U << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk            \n#define RCC_APB2ENR_ADC1EN_Pos             (8U)                                \n#define RCC_APB2ENR_ADC1EN_Msk             (0x1U << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk              \n#define RCC_APB2ENR_ADC2EN_Pos             (9U)                                \n#define RCC_APB2ENR_ADC2EN_Msk             (0x1U << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */\n#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk              \n#define RCC_APB2ENR_ADC3EN_Pos             (10U)                               \n#define RCC_APB2ENR_ADC3EN_Msk             (0x1U << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */\n#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk              \n#define RCC_APB2ENR_SDIOEN_Pos             (11U)                               \n#define RCC_APB2ENR_SDIOEN_Msk             (0x1U << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk              \n#define RCC_APB2ENR_SPI1EN_Pos             (12U)                               \n#define RCC_APB2ENR_SPI1EN_Msk             (0x1U << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk              \n#define RCC_APB2ENR_SPI4EN_Pos             (13U)                               \n#define RCC_APB2ENR_SPI4EN_Msk             (0x1U << RCC_APB2ENR_SPI4EN_Pos)    /*!< 0x00002000 */\n#define RCC_APB2ENR_SPI4EN                 RCC_APB2ENR_SPI4EN_Msk              \n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)                               \n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk            \n#define RCC_APB2ENR_TIM9EN_Pos             (16U)                               \n#define RCC_APB2ENR_TIM9EN_Msk             (0x1U << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk              \n#define RCC_APB2ENR_TIM10EN_Pos            (17U)                               \n#define RCC_APB2ENR_TIM10EN_Msk            (0x1U << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk             \n#define RCC_APB2ENR_TIM11EN_Pos            (18U)                               \n#define RCC_APB2ENR_TIM11EN_Msk            (0x1U << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk             \n#define RCC_APB2ENR_SPI5EN_Pos             (20U)                               \n#define RCC_APB2ENR_SPI5EN_Msk             (0x1U << RCC_APB2ENR_SPI5EN_Pos)    /*!< 0x00100000 */\n#define RCC_APB2ENR_SPI5EN                 RCC_APB2ENR_SPI5EN_Msk              \n#define RCC_APB2ENR_SPI6EN_Pos             (21U)                               \n#define RCC_APB2ENR_SPI6EN_Msk             (0x1U << RCC_APB2ENR_SPI6EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB2ENR_SPI6EN                 RCC_APB2ENR_SPI6EN_Msk              \n#define RCC_APB2ENR_SAI1EN_Pos             (22U)                               \n#define RCC_APB2ENR_SAI1EN_Msk             (0x1U << RCC_APB2ENR_SAI1EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB2ENR_SAI1EN                 RCC_APB2ENR_SAI1EN_Msk              \n#define RCC_APB2ENR_LTDCEN_Pos             (26U)                               \n#define RCC_APB2ENR_LTDCEN_Msk             (0x1U << RCC_APB2ENR_LTDCEN_Pos)    /*!< 0x04000000 */\n#define RCC_APB2ENR_LTDCEN                 RCC_APB2ENR_LTDCEN_Msk              \n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)                                \n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk         \n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)                                \n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)                                \n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk         \n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)                                \n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)                                \n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk         \n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)                                \n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)                                \n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)                                \n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)                                \n#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk         \n#define RCC_AHB1LPENR_GPIOJLPEN_Pos        (9U)                                \n#define RCC_AHB1LPENR_GPIOJLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */\n#define RCC_AHB1LPENR_GPIOJLPEN            RCC_AHB1LPENR_GPIOJLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOKLPEN_Pos        (10U)                               \n#define RCC_AHB1LPENR_GPIOKLPEN_Msk        (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */\n#define RCC_AHB1LPENR_GPIOKLPEN            RCC_AHB1LPENR_GPIOKLPEN_Msk         \n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)                               \n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk           \n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)                               \n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk         \n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)                               \n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk         \n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)                               \n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk         \n#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)                               \n#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk       \n#define RCC_AHB1LPENR_SRAM3LPEN_Pos        (19U)                               \n#define RCC_AHB1LPENR_SRAM3LPEN_Msk        (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */\n#define RCC_AHB1LPENR_SRAM3LPEN            RCC_AHB1LPENR_SRAM3LPEN_Msk         \n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)                               \n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk          \n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)                               \n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk          \n#define RCC_AHB1LPENR_DMA2DLPEN_Pos        (23U)                               \n#define RCC_AHB1LPENR_DMA2DLPEN_Msk        (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */\n#define RCC_AHB1LPENR_DMA2DLPEN            RCC_AHB1LPENR_DMA2DLPEN_Msk         \n\n#define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)                               \n#define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */\n#define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk        \n#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)                               \n#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */\n#define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk      \n#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)                               \n#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */\n#define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk      \n#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)                               \n#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */\n#define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk     \n#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)                               \n#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\n#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk         \n#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)                               \n#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk     \n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)                                \n#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk          \n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)                                \n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk           \n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)                                \n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk         \n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FMCLPEN_Pos          (0U)                                \n#define RCC_AHB3LPENR_FMCLPEN_Msk          (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FMCLPEN              RCC_AHB3LPENR_FMCLPEN_Msk           \n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)                                \n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk          \n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)                                \n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk          \n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)                                \n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk          \n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)                                \n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk          \n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)                                \n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk          \n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)                                \n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk          \n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)                                \n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk         \n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)                                \n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk         \n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)                                \n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk         \n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)                               \n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk          \n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)                               \n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk          \n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)                               \n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk          \n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)                               \n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk        \n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)                               \n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk        \n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)                               \n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk         \n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)                               \n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk         \n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)                               \n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk          \n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)                               \n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk          \n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)                               \n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk          \n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)                               \n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk          \n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)                               \n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk          \n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)                               \n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk           \n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)                               \n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk           \n#define RCC_APB1LPENR_UART7LPEN_Pos        (30U)                               \n#define RCC_APB1LPENR_UART7LPEN_Msk        (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */\n#define RCC_APB1LPENR_UART7LPEN            RCC_APB1LPENR_UART7LPEN_Msk         \n#define RCC_APB1LPENR_UART8LPEN_Pos        (31U)                               \n#define RCC_APB1LPENR_UART8LPEN_Msk        (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */\n#define RCC_APB1LPENR_UART8LPEN            RCC_APB1LPENR_UART8LPEN_Msk         \n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)                                \n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk          \n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)                                \n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk          \n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)                                \n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk        \n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)                                \n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk        \n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)                                \n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk          \n#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)                                \n#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk          \n#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)                               \n#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk          \n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)                               \n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk          \n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)                               \n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk          \n#define RCC_APB2LPENR_SPI4LPEN_Pos         (13U)                               \n#define RCC_APB2LPENR_SPI4LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2LPENR_SPI4LPEN             RCC_APB2LPENR_SPI4LPEN_Msk          \n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)                               \n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk        \n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)                               \n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk          \n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)                               \n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk         \n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)                               \n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk         \n#define RCC_APB2LPENR_SPI5LPEN_Pos         (20U)                               \n#define RCC_APB2LPENR_SPI5LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB2LPENR_SPI5LPEN             RCC_APB2LPENR_SPI5LPEN_Msk          \n#define RCC_APB2LPENR_SPI6LPEN_Pos         (21U)                               \n#define RCC_APB2LPENR_SPI6LPEN_Msk         (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB2LPENR_SPI6LPEN             RCC_APB2LPENR_SPI6LPEN_Msk          \n#define RCC_APB2LPENR_SAI1LPEN_Pos         (22U)                               \n#define RCC_APB2LPENR_SAI1LPEN_Msk         (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB2LPENR_SAI1LPEN             RCC_APB2LPENR_SAI1LPEN_Msk          \n#define RCC_APB2LPENR_LTDCLPEN_Pos         (26U)                               \n#define RCC_APB2LPENR_LTDCLPEN_Msk         (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB2LPENR_LTDCLPEN             RCC_APB2LPENR_LTDCLPEN_Msk          \n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)                                \n#define RCC_BDCR_LSEON_Msk                 (0x1U << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk                  \n#define RCC_BDCR_LSERDY_Pos                (1U)                                \n#define RCC_BDCR_LSERDY_Msk                (0x1U << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk                 \n#define RCC_BDCR_LSEBYP_Pos                (2U)                                \n#define RCC_BDCR_LSEBYP_Msk                (0x1U << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk                 \n\n#define RCC_BDCR_RTCSEL_Pos                (8U)                                \n#define RCC_BDCR_RTCSEL_Msk                (0x3U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk                 \n#define RCC_BDCR_RTCSEL_0                  (0x1U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2U << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)                               \n#define RCC_BDCR_RTCEN_Msk                 (0x1U << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk                  \n#define RCC_BDCR_BDRST_Pos                 (16U)                               \n#define RCC_BDCR_BDRST_Msk                 (0x1U << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk                  \n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)                                \n#define RCC_CSR_LSION_Msk                  (0x1U << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk                   \n#define RCC_CSR_LSIRDY_Pos                 (1U)                                \n#define RCC_CSR_LSIRDY_Msk                 (0x1U << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk                  \n#define RCC_CSR_RMVF_Pos                   (24U)                               \n#define RCC_CSR_RMVF_Msk                   (0x1U << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk                    \n#define RCC_CSR_BORRSTF_Pos                (25U)                               \n#define RCC_CSR_BORRSTF_Msk                (0x1U << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk                 \n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1U << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)                               \n#define RCC_CSR_PORRSTF_Msk                (0x1U << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk                 \n#define RCC_CSR_SFTRSTF_Pos                (28U)                               \n#define RCC_CSR_SFTRSTF_Msk                (0x1U << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk                 \n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1U << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)                               \n#define RCC_CSR_WWDGRSTF_Msk               (0x1U << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk                \n#define RCC_CSR_LPWRRSTF_Pos               (31U)                               \n#define RCC_CSR_LPWRRSTF_Msk               (0x1U << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)                                \n#define RCC_SSCGR_MODPER_Msk               (0x1FFFU << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk                \n#define RCC_SSCGR_INCSTEP_Pos              (13U)                               \n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFU << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk               \n#define RCC_SSCGR_SPREADSEL_Pos            (30U)                               \n#define RCC_SSCGR_SPREADSEL_Msk            (0x1U << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk             \n#define RCC_SSCGR_SSCGEN_Pos               (31U)                               \n#define RCC_SSCGR_SSCGEN_Msk               (0x1U << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk                \n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)                                \n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk          \n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SQ_Pos         (24U)                               \n#define RCC_PLLI2SCFGR_PLLI2SQ_Msk         (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ             RCC_PLLI2SCFGR_PLLI2SQ_Msk          \n#define RCC_PLLI2SCFGR_PLLI2SQ_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLI2SCFGR_PLLI2SQ_3           (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)                               \n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk          \n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_PLLSAICFGR register  ************/\n#define RCC_PLLSAICFGR_PLLSAIN_Pos         (6U)                                \n#define RCC_PLLSAICFGR_PLLSAIN_Msk         (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLSAICFGR_PLLSAIN             RCC_PLLSAICFGR_PLLSAIN_Msk          \n#define RCC_PLLSAICFGR_PLLSAIN_0           (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */\n#define RCC_PLLSAICFGR_PLLSAIN_1           (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */\n#define RCC_PLLSAICFGR_PLLSAIN_2           (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */\n#define RCC_PLLSAICFGR_PLLSAIN_3           (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */\n#define RCC_PLLSAICFGR_PLLSAIN_4           (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */\n#define RCC_PLLSAICFGR_PLLSAIN_5           (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */\n#define RCC_PLLSAICFGR_PLLSAIN_6           (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */\n#define RCC_PLLSAICFGR_PLLSAIN_7           (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */\n#define RCC_PLLSAICFGR_PLLSAIN_8           (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */\n\n\n#define RCC_PLLSAICFGR_PLLSAIQ_Pos         (24U)                               \n#define RCC_PLLSAICFGR_PLLSAIQ_Msk         (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ             RCC_PLLSAICFGR_PLLSAIQ_Msk          \n#define RCC_PLLSAICFGR_PLLSAIQ_0           (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_1           (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_2           (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */\n#define RCC_PLLSAICFGR_PLLSAIQ_3           (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */\n\n#define RCC_PLLSAICFGR_PLLSAIR_Pos         (28U)                               \n#define RCC_PLLSAICFGR_PLLSAIR_Msk         (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */\n#define RCC_PLLSAICFGR_PLLSAIR             RCC_PLLSAICFGR_PLLSAIR_Msk          \n#define RCC_PLLSAICFGR_PLLSAIR_0           (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */\n#define RCC_PLLSAICFGR_PLLSAIR_1           (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */\n#define RCC_PLLSAICFGR_PLLSAIR_2           (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_DCKCFGR register  ***************/\n#define RCC_DCKCFGR_PLLI2SDIVQ_Pos        (0U)                                \n#define RCC_DCKCFGR_PLLI2SDIVQ_Msk        (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */\n#define RCC_DCKCFGR_PLLI2SDIVQ            RCC_DCKCFGR_PLLI2SDIVQ_Msk         \n#define RCC_DCKCFGR_PLLI2SDIVQ_0          (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_1          (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_2          (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_3          (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */\n#define RCC_DCKCFGR_PLLI2SDIVQ_4          (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */\n                   \n#define RCC_DCKCFGR_PLLSAIDIVQ_Pos        (8U)                                \n#define RCC_DCKCFGR_PLLSAIDIVQ_Msk        (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */\n#define RCC_DCKCFGR_PLLSAIDIVQ            RCC_DCKCFGR_PLLSAIDIVQ_Msk         \n#define RCC_DCKCFGR_PLLSAIDIVQ_0          (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_1          (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_2          (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_3          (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */\n#define RCC_DCKCFGR_PLLSAIDIVQ_4          (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */\n#define RCC_DCKCFGR_PLLSAIDIVR_Pos        (16U)                               \n#define RCC_DCKCFGR_PLLSAIDIVR_Msk        (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */\n#define RCC_DCKCFGR_PLLSAIDIVR            RCC_DCKCFGR_PLLSAIDIVR_Msk         \n#define RCC_DCKCFGR_PLLSAIDIVR_0          (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */\n#define RCC_DCKCFGR_PLLSAIDIVR_1          (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */\n\n#define RCC_DCKCFGR_SAI1ASRC_Pos           (20U)                               \n#define RCC_DCKCFGR_SAI1ASRC_Msk           (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00300000 */\n#define RCC_DCKCFGR_SAI1ASRC               RCC_DCKCFGR_SAI1ASRC_Msk            \n#define RCC_DCKCFGR_SAI1ASRC_0             (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00100000 */\n#define RCC_DCKCFGR_SAI1ASRC_1             (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos)  /*!< 0x00200000 */\n#define RCC_DCKCFGR_SAI1BSRC_Pos           (22U)                               \n#define RCC_DCKCFGR_SAI1BSRC_Msk           (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00C00000 */\n#define RCC_DCKCFGR_SAI1BSRC               RCC_DCKCFGR_SAI1BSRC_Msk            \n#define RCC_DCKCFGR_SAI1BSRC_0             (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00400000 */\n#define RCC_DCKCFGR_SAI1BSRC_1             (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos)  /*!< 0x00800000 */\n#define RCC_DCKCFGR_TIMPRE_Pos             (24U)                               \n#define RCC_DCKCFGR_TIMPRE_Msk             (0x1U << RCC_DCKCFGR_TIMPRE_Pos)    /*!< 0x01000000 */\n#define RCC_DCKCFGR_TIMPRE                 RCC_DCKCFGR_TIMPRE_Msk              \n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)                                               \n#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   \n#define RNG_CR_IE_Pos       (3U)                                               \n#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk                                      \n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)                                               \n#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    \n#define RNG_SR_CECS_Pos     (1U)                                               \n#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    \n#define RNG_SR_SECS_Pos     (2U)                                               \n#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    \n#define RNG_SR_CEIS_Pos     (5U)                                               \n#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    \n#define RNG_SR_SEIS_Pos     (6U)                                               \n#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    \n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)\n */\n#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */\n#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)                                    \n#define RTC_TR_PM_Msk                 (0x1U << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk                            \n#define RTC_TR_HT_Pos                 (20U)                                    \n#define RTC_TR_HT_Msk                 (0x3U << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk                            \n#define RTC_TR_HT_0                   (0x1U << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2U << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)                                    \n#define RTC_TR_HU_Msk                 (0xFU << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk                            \n#define RTC_TR_HU_0                   (0x1U << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2U << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4U << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8U << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)                                    \n#define RTC_TR_MNT_Msk                (0x7U << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk                           \n#define RTC_TR_MNT_0                  (0x1U << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2U << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4U << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)                                     \n#define RTC_TR_MNU_Msk                (0xFU << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk                           \n#define RTC_TR_MNU_0                  (0x1U << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2U << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4U << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8U << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)                                     \n#define RTC_TR_ST_Msk                 (0x7U << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk                            \n#define RTC_TR_ST_0                   (0x1U << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2U << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4U << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)                                     \n#define RTC_TR_SU_Msk                 (0xFU << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk                            \n#define RTC_TR_SU_0                   (0x1U << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2U << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4U << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8U << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)                                    \n#define RTC_DR_YT_Msk                 (0xFU << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk                            \n#define RTC_DR_YT_0                   (0x1U << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2U << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4U << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8U << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)                                    \n#define RTC_DR_YU_Msk                 (0xFU << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk                            \n#define RTC_DR_YU_0                   (0x1U << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2U << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4U << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8U << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)                                    \n#define RTC_DR_WDU_Msk                (0x7U << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk                           \n#define RTC_DR_WDU_0                  (0x1U << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2U << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4U << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)                                    \n#define RTC_DR_MT_Msk                 (0x1U << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk                            \n#define RTC_DR_MU_Pos                 (8U)                                     \n#define RTC_DR_MU_Msk                 (0xFU << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk                            \n#define RTC_DR_MU_0                   (0x1U << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2U << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4U << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8U << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)                                     \n#define RTC_DR_DT_Msk                 (0x3U << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk                            \n#define RTC_DR_DT_0                   (0x1U << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2U << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)                                     \n#define RTC_DR_DU_Msk                 (0xFU << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk                            \n#define RTC_DR_DU_0                   (0x1U << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2U << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4U << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8U << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)                                    \n#define RTC_CR_COE_Msk                (0x1U << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk                           \n#define RTC_CR_OSEL_Pos               (21U)                                    \n#define RTC_CR_OSEL_Msk               (0x3U << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk                          \n#define RTC_CR_OSEL_0                 (0x1U << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2U << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)                                    \n#define RTC_CR_POL_Msk                (0x1U << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk                           \n#define RTC_CR_COSEL_Pos              (19U)                                    \n#define RTC_CR_COSEL_Msk              (0x1U << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk                         \n#define RTC_CR_BKP_Pos                 (18U)                                   \n#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          \n#define RTC_CR_SUB1H_Pos              (17U)                                    \n#define RTC_CR_SUB1H_Msk              (0x1U << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk                         \n#define RTC_CR_ADD1H_Pos              (16U)                                    \n#define RTC_CR_ADD1H_Msk              (0x1U << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk                         \n#define RTC_CR_TSIE_Pos               (15U)                                    \n#define RTC_CR_TSIE_Msk               (0x1U << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk                          \n#define RTC_CR_WUTIE_Pos              (14U)                                    \n#define RTC_CR_WUTIE_Msk              (0x1U << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk                         \n#define RTC_CR_ALRBIE_Pos             (13U)                                    \n#define RTC_CR_ALRBIE_Msk             (0x1U << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk                        \n#define RTC_CR_ALRAIE_Pos             (12U)                                    \n#define RTC_CR_ALRAIE_Msk             (0x1U << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk                        \n#define RTC_CR_TSE_Pos                (11U)                                    \n#define RTC_CR_TSE_Msk                (0x1U << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk                           \n#define RTC_CR_WUTE_Pos               (10U)                                    \n#define RTC_CR_WUTE_Msk               (0x1U << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk                          \n#define RTC_CR_ALRBE_Pos              (9U)                                     \n#define RTC_CR_ALRBE_Msk              (0x1U << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk                         \n#define RTC_CR_ALRAE_Pos              (8U)                                     \n#define RTC_CR_ALRAE_Msk              (0x1U << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk                         \n#define RTC_CR_DCE_Pos                (7U)                                     \n#define RTC_CR_DCE_Msk                (0x1U << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk                           \n#define RTC_CR_FMT_Pos                (6U)                                     \n#define RTC_CR_FMT_Msk                (0x1U << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk                           \n#define RTC_CR_BYPSHAD_Pos            (5U)                                     \n#define RTC_CR_BYPSHAD_Msk            (0x1U << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk                       \n#define RTC_CR_REFCKON_Pos            (4U)                                     \n#define RTC_CR_REFCKON_Msk            (0x1U << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk                       \n#define RTC_CR_TSEDGE_Pos             (3U)                                     \n#define RTC_CR_TSEDGE_Msk             (0x1U << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk                        \n#define RTC_CR_WUCKSEL_Pos            (0U)                                     \n#define RTC_CR_WUCKSEL_Msk            (0x7U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk                       \n#define RTC_CR_WUCKSEL_0              (0x1U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4U << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)                                    \n#define RTC_ISR_RECALPF_Msk           (0x1U << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk                      \n#define RTC_ISR_TAMP1F_Pos            (13U)                                    \n#define RTC_ISR_TAMP1F_Msk            (0x1U << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk                       \n#define RTC_ISR_TAMP2F_Pos            (14U)                                    \n#define RTC_ISR_TAMP2F_Msk            (0x1U << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk                       \n#define RTC_ISR_TSOVF_Pos             (12U)                                    \n#define RTC_ISR_TSOVF_Msk             (0x1U << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk                        \n#define RTC_ISR_TSF_Pos               (11U)                                    \n#define RTC_ISR_TSF_Msk               (0x1U << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk                          \n#define RTC_ISR_WUTF_Pos              (10U)                                    \n#define RTC_ISR_WUTF_Msk              (0x1U << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk                         \n#define RTC_ISR_ALRBF_Pos             (9U)                                     \n#define RTC_ISR_ALRBF_Msk             (0x1U << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk                        \n#define RTC_ISR_ALRAF_Pos             (8U)                                     \n#define RTC_ISR_ALRAF_Msk             (0x1U << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk                        \n#define RTC_ISR_INIT_Pos              (7U)                                     \n#define RTC_ISR_INIT_Msk              (0x1U << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk                         \n#define RTC_ISR_INITF_Pos             (6U)                                     \n#define RTC_ISR_INITF_Msk             (0x1U << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk                        \n#define RTC_ISR_RSF_Pos               (5U)                                     \n#define RTC_ISR_RSF_Msk               (0x1U << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk                          \n#define RTC_ISR_INITS_Pos             (4U)                                     \n#define RTC_ISR_INITS_Msk             (0x1U << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk                        \n#define RTC_ISR_SHPF_Pos              (3U)                                     \n#define RTC_ISR_SHPF_Msk              (0x1U << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk                         \n#define RTC_ISR_WUTWF_Pos             (2U)                                     \n#define RTC_ISR_WUTWF_Msk             (0x1U << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk                        \n#define RTC_ISR_ALRBWF_Pos            (1U)                                     \n#define RTC_ISR_ALRBWF_Msk            (0x1U << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk                       \n#define RTC_ISR_ALRAWF_Pos            (0U)                                     \n#define RTC_ISR_ALRAWF_Msk            (0x1U << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk                       \n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)                                    \n#define RTC_PRER_PREDIV_A_Msk         (0x7FU << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk                    \n#define RTC_PRER_PREDIV_S_Pos         (0U)                                     \n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFU << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk                    \n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)                                     \n#define RTC_WUTR_WUT_Msk              (0xFFFFU << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk                         \n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)                                     \n#define RTC_CALIBR_DCS_Msk            (0x1U << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk                       \n#define RTC_CALIBR_DC_Pos             (0U)                                     \n#define RTC_CALIBR_DC_Msk             (0x1FU << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk                        \n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)                                    \n#define RTC_ALRMAR_MSK4_Msk           (0x1U << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk                      \n#define RTC_ALRMAR_WDSEL_Pos          (30U)                                    \n#define RTC_ALRMAR_WDSEL_Msk          (0x1U << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk                     \n#define RTC_ALRMAR_DT_Pos             (28U)                                    \n#define RTC_ALRMAR_DT_Msk             (0x3U << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk                        \n#define RTC_ALRMAR_DT_0               (0x1U << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2U << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)                                    \n#define RTC_ALRMAR_DU_Msk             (0xFU << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk                        \n#define RTC_ALRMAR_DU_0               (0x1U << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2U << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4U << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8U << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)                                    \n#define RTC_ALRMAR_MSK3_Msk           (0x1U << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk                      \n#define RTC_ALRMAR_PM_Pos             (22U)                                    \n#define RTC_ALRMAR_PM_Msk             (0x1U << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk                        \n#define RTC_ALRMAR_HT_Pos             (20U)                                    \n#define RTC_ALRMAR_HT_Msk             (0x3U << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk                        \n#define RTC_ALRMAR_HT_0               (0x1U << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2U << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)                                    \n#define RTC_ALRMAR_HU_Msk             (0xFU << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk                        \n#define RTC_ALRMAR_HU_0               (0x1U << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2U << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4U << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8U << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)                                    \n#define RTC_ALRMAR_MSK2_Msk           (0x1U << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk                      \n#define RTC_ALRMAR_MNT_Pos            (12U)                                    \n#define RTC_ALRMAR_MNT_Msk            (0x7U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk                       \n#define RTC_ALRMAR_MNT_0              (0x1U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4U << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)                                     \n#define RTC_ALRMAR_MNU_Msk            (0xFU << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk                       \n#define RTC_ALRMAR_MNU_0              (0x1U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8U << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)                                     \n#define RTC_ALRMAR_MSK1_Msk           (0x1U << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk                      \n#define RTC_ALRMAR_ST_Pos             (4U)                                     \n#define RTC_ALRMAR_ST_Msk             (0x7U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk                        \n#define RTC_ALRMAR_ST_0               (0x1U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4U << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)                                     \n#define RTC_ALRMAR_SU_Msk             (0xFU << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk                        \n#define RTC_ALRMAR_SU_0               (0x1U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8U << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)                                    \n#define RTC_ALRMBR_MSK4_Msk           (0x1U << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk                      \n#define RTC_ALRMBR_WDSEL_Pos          (30U)                                    \n#define RTC_ALRMBR_WDSEL_Msk          (0x1U << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk                     \n#define RTC_ALRMBR_DT_Pos             (28U)                                    \n#define RTC_ALRMBR_DT_Msk             (0x3U << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk                        \n#define RTC_ALRMBR_DT_0               (0x1U << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2U << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)                                    \n#define RTC_ALRMBR_DU_Msk             (0xFU << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk                        \n#define RTC_ALRMBR_DU_0               (0x1U << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2U << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4U << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8U << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)                                    \n#define RTC_ALRMBR_MSK3_Msk           (0x1U << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk                      \n#define RTC_ALRMBR_PM_Pos             (22U)                                    \n#define RTC_ALRMBR_PM_Msk             (0x1U << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk                        \n#define RTC_ALRMBR_HT_Pos             (20U)                                    \n#define RTC_ALRMBR_HT_Msk             (0x3U << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk                        \n#define RTC_ALRMBR_HT_0               (0x1U << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2U << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)                                    \n#define RTC_ALRMBR_HU_Msk             (0xFU << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk                        \n#define RTC_ALRMBR_HU_0               (0x1U << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2U << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4U << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8U << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)                                    \n#define RTC_ALRMBR_MSK2_Msk           (0x1U << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk                      \n#define RTC_ALRMBR_MNT_Pos            (12U)                                    \n#define RTC_ALRMBR_MNT_Msk            (0x7U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk                       \n#define RTC_ALRMBR_MNT_0              (0x1U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4U << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)                                     \n#define RTC_ALRMBR_MNU_Msk            (0xFU << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk                       \n#define RTC_ALRMBR_MNU_0              (0x1U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8U << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)                                     \n#define RTC_ALRMBR_MSK1_Msk           (0x1U << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk                      \n#define RTC_ALRMBR_ST_Pos             (4U)                                     \n#define RTC_ALRMBR_ST_Msk             (0x7U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk                        \n#define RTC_ALRMBR_ST_0               (0x1U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4U << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)                                     \n#define RTC_ALRMBR_SU_Msk             (0xFU << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk                        \n#define RTC_ALRMBR_SU_0               (0x1U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8U << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)                                     \n#define RTC_WPR_KEY_Msk               (0xFFU << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk                          \n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)                                     \n#define RTC_SSR_SS_Msk                (0xFFFFU << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk                           \n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)                                     \n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk                     \n#define RTC_SHIFTR_ADD1S_Pos          (31U)                                    \n#define RTC_SHIFTR_ADD1S_Msk          (0x1U << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk                     \n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)                                    \n#define RTC_TSTR_PM_Msk               (0x1U << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk                          \n#define RTC_TSTR_HT_Pos               (20U)                                    \n#define RTC_TSTR_HT_Msk               (0x3U << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk                          \n#define RTC_TSTR_HT_0                 (0x1U << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2U << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)                                    \n#define RTC_TSTR_HU_Msk               (0xFU << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk                          \n#define RTC_TSTR_HU_0                 (0x1U << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2U << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4U << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8U << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)                                    \n#define RTC_TSTR_MNT_Msk              (0x7U << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk                         \n#define RTC_TSTR_MNT_0                (0x1U << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2U << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4U << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)                                     \n#define RTC_TSTR_MNU_Msk              (0xFU << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk                         \n#define RTC_TSTR_MNU_0                (0x1U << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2U << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4U << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8U << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)                                     \n#define RTC_TSTR_ST_Msk               (0x7U << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk                          \n#define RTC_TSTR_ST_0                 (0x1U << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2U << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4U << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)                                     \n#define RTC_TSTR_SU_Msk               (0xFU << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk                          \n#define RTC_TSTR_SU_0                 (0x1U << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2U << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4U << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8U << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)                                    \n#define RTC_TSDR_WDU_Msk              (0x7U << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk                         \n#define RTC_TSDR_WDU_0                (0x1U << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2U << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4U << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)                                    \n#define RTC_TSDR_MT_Msk               (0x1U << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk                          \n#define RTC_TSDR_MU_Pos               (8U)                                     \n#define RTC_TSDR_MU_Msk               (0xFU << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk                          \n#define RTC_TSDR_MU_0                 (0x1U << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2U << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4U << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8U << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)                                     \n#define RTC_TSDR_DT_Msk               (0x3U << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk                          \n#define RTC_TSDR_DT_0                 (0x1U << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2U << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)                                     \n#define RTC_TSDR_DU_Msk               (0xFU << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk                          \n#define RTC_TSDR_DU_0                 (0x1U << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2U << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4U << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8U << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)                                     \n#define RTC_TSSSR_SS_Msk              (0xFFFFU << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk                         \n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)                                    \n#define RTC_CALR_CALP_Msk             (0x1U << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk                        \n#define RTC_CALR_CALW8_Pos            (14U)                                    \n#define RTC_CALR_CALW8_Msk            (0x1U << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk                       \n#define RTC_CALR_CALW16_Pos           (13U)                                    \n#define RTC_CALR_CALW16_Msk           (0x1U << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk                      \n#define RTC_CALR_CALM_Pos             (0U)                                     \n#define RTC_CALR_CALM_Msk             (0x1FFU << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk                        \n#define RTC_CALR_CALM_0               (0x001U << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002U << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004U << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008U << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010U << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020U << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040U << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080U << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100U << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)                                    \n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk               \n#define RTC_TAFCR_TSINSEL_Pos         (17U)                                    \n#define RTC_TAFCR_TSINSEL_Msk         (0x1U << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk                    \n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)                                    \n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1U << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk                  \n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)                                    \n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk                  \n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)                                    \n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk                   \n#define RTC_TAFCR_TAMPPRCH_0          (0x1U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2U << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)                                    \n#define RTC_TAFCR_TAMPFLT_Msk         (0x3U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk                    \n#define RTC_TAFCR_TAMPFLT_0           (0x1U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2U << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)                                     \n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk                   \n#define RTC_TAFCR_TAMPFREQ_0          (0x1U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4U << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)                                     \n#define RTC_TAFCR_TAMPTS_Msk          (0x1U << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk                     \n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)                                     \n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1U << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk                   \n#define RTC_TAFCR_TAMP2E_Pos          (3U)                                     \n#define RTC_TAFCR_TAMP2E_Msk          (0x1U << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk                     \n#define RTC_TAFCR_TAMPIE_Pos          (2U)                                     \n#define RTC_TAFCR_TAMPIE_Msk          (0x1U << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk                     \n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)                                     \n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1U << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk                   \n#define RTC_TAFCR_TAMP1E_Pos          (0U)                                     \n#define RTC_TAFCR_TAMP1E_Msk          (0x1U << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk                     \n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)                                    \n#define RTC_ALRMASSR_MASKSS_Msk       (0xFU << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk                  \n#define RTC_ALRMASSR_MASKSS_0         (0x1U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8U << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)                                     \n#define RTC_ALRMASSR_SS_Msk           (0x7FFFU << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk                      \n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)                                    \n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFU << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk                  \n#define RTC_ALRMBSSR_MASKSS_0         (0x1U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8U << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)                                     \n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFU << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk                      \n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)                                     \n#define RTC_BKP0R_Msk                 (0xFFFFFFFFU << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk                            \n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)                                     \n#define RTC_BKP1R_Msk                 (0xFFFFFFFFU << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk                            \n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)                                     \n#define RTC_BKP2R_Msk                 (0xFFFFFFFFU << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk                            \n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)                                     \n#define RTC_BKP3R_Msk                 (0xFFFFFFFFU << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk                            \n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)                                     \n#define RTC_BKP4R_Msk                 (0xFFFFFFFFU << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk                            \n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)                                     \n#define RTC_BKP5R_Msk                 (0xFFFFFFFFU << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk                            \n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)                                     \n#define RTC_BKP6R_Msk                 (0xFFFFFFFFU << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk                            \n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)                                     \n#define RTC_BKP7R_Msk                 (0xFFFFFFFFU << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk                            \n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)                                     \n#define RTC_BKP8R_Msk                 (0xFFFFFFFFU << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk                            \n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)                                     \n#define RTC_BKP9R_Msk                 (0xFFFFFFFFU << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk                            \n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)                                     \n#define RTC_BKP10R_Msk                (0xFFFFFFFFU << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk                           \n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)                                     \n#define RTC_BKP11R_Msk                (0xFFFFFFFFU << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk                           \n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)                                     \n#define RTC_BKP12R_Msk                (0xFFFFFFFFU << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk                           \n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)                                     \n#define RTC_BKP13R_Msk                (0xFFFFFFFFU << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk                           \n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)                                     \n#define RTC_BKP14R_Msk                (0xFFFFFFFFU << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk                           \n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)                                     \n#define RTC_BKP15R_Msk                (0xFFFFFFFFU << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk                           \n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)                                     \n#define RTC_BKP16R_Msk                (0xFFFFFFFFU << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk                           \n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)                                     \n#define RTC_BKP17R_Msk                (0xFFFFFFFFU << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk                           \n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)                                     \n#define RTC_BKP18R_Msk                (0xFFFFFFFFU << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk                           \n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)                                     \n#define RTC_BKP19R_Msk                (0xFFFFFFFFU << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk                           \n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n    \n/******************************************************************************/\n/*                                                                            */\n/*                          Serial Audio Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for SAI_GCR register  *******************/\n#define SAI_GCR_SYNCIN_Pos         (0U)                                        \n#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\n#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\n#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\n\n#define SAI_GCR_SYNCOUT_Pos        (4U)                                        \n#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\n#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\n#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\n\n/*******************  Bit definition for SAI_xCR1 register  *******************/\n#define SAI_xCR1_MODE_Pos          (0U)                                        \n#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\n#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\n#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\n\n#define SAI_xCR1_PRTCFG_Pos        (2U)                                        \n#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\n#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\n#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\n\n#define SAI_xCR1_DS_Pos            (5U)                                        \n#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\n#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\n#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\n#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\n\n#define SAI_xCR1_LSBFIRST_Pos      (8U)                                        \n#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\n#define SAI_xCR1_CKSTR_Pos         (9U)                                        \n#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\n\n#define SAI_xCR1_SYNCEN_Pos        (10U)                                       \n#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\n#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\n#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\n\n#define SAI_xCR1_MONO_Pos          (12U)                                       \n#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\n#define SAI_xCR1_OUTDRIV_Pos       (13U)                                       \n#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\n#define SAI_xCR1_SAIEN_Pos         (16U)                                       \n#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\n#define SAI_xCR1_DMAEN_Pos         (17U)                                       \n#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\n#define SAI_xCR1_NODIV_Pos         (19U)                                       \n#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\n\n#define SAI_xCR1_MCKDIV_Pos        (20U)                                       \n#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\n#define SAI_xCR1_MCKDIV_0          (0x1U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00100000 */\n#define SAI_xCR1_MCKDIV_1          (0x2U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00200000 */\n#define SAI_xCR1_MCKDIV_2          (0x4U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00400000 */\n#define SAI_xCR1_MCKDIV_3          (0x8U << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00800000 */\n\n/*******************  Bit definition for SAI_xCR2 register  *******************/\n#define SAI_xCR2_FTH_Pos           (0U)                                        \n#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\n#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\n#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\n#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\n\n#define SAI_xCR2_FFLUSH_Pos        (3U)                                        \n#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\n#define SAI_xCR2_TRIS_Pos          (4U)                                        \n#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\n#define SAI_xCR2_MUTE_Pos          (5U)                                        \n#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\n#define SAI_xCR2_MUTEVAL_Pos       (6U)                                        \n#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\n\n#define SAI_xCR2_MUTECNT_Pos       (7U)                                        \n#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\n#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\n#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\n#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\n#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\n#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\n#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\n\n#define SAI_xCR2_CPL_Pos           (13U)                                       \n#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */\n\n#define SAI_xCR2_COMP_Pos          (14U)                                       \n#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\n#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\n#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for SAI_xFRCR register  *******************/\n#define SAI_xFRCR_FRL_Pos          (0U)                                        \n#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[1:0](Frame length)  */\n#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\n#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\n#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\n#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\n#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\n#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\n#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\n#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\n\n#define SAI_xFRCR_FSALL_Pos        (8U)                                        \n#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[1:0] (Frame synchronization active level length)  */\n#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\n#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\n#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\n#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\n#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\n#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\n#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\n\n#define SAI_xFRCR_FSDEF_Pos        (16U)                                       \n#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */\n#define SAI_xFRCR_FSPOL_Pos        (17U)                                       \n#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\n#define SAI_xFRCR_FSOFF_Pos        (18U)                                       \n#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\n/* Legacy defines */\n#define  SAI_xFRCR_FSPO                   SAI_xFRCR_FSPOL\n\n/******************  Bit definition for SAI_xSLOTR register  *******************/\n#define SAI_xSLOTR_FBOFF_Pos       (0U)                                        \n#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\n#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\n#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\n#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\n#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\n#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\n\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)                                        \n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\n#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\n#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\n\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)                                        \n#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\n#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\n#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\n#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\n#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\n\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)                                       \n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\n\n/*******************  Bit definition for SAI_xIMR register  *******************/\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)                                        \n#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)                                        \n#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)                                        \n#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\n#define SAI_xIMR_FREQIE_Pos        (3U)                                        \n#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\n#define SAI_xIMR_CNRDYIE_Pos       (4U)                                        \n#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\n#define SAI_xIMR_AFSDETIE_Pos      (5U)                                        \n#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\n#define SAI_xIMR_LFSDETIE_Pos      (6U)                                        \n#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\n\n/********************  Bit definition for SAI_xSR register  *******************/\n#define SAI_xSR_OVRUDR_Pos         (0U)                                        \n#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\n#define SAI_xSR_MUTEDET_Pos        (1U)                                        \n#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\n#define SAI_xSR_WCKCFG_Pos         (2U)                                        \n#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\n#define SAI_xSR_FREQ_Pos           (3U)                                        \n#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\n#define SAI_xSR_CNRDY_Pos          (4U)                                        \n#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\n#define SAI_xSR_AFSDET_Pos         (5U)                                        \n#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\n#define SAI_xSR_LFSDET_Pos         (6U)                                        \n#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\n\n#define SAI_xSR_FLVL_Pos           (16U)                                       \n#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\n#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\n#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\n#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\n\n/******************  Bit definition for SAI_xCLRFR register  ******************/\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)                                        \n#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)                                        \n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)                                        \n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\n#define SAI_xCLRFR_CFREQ_Pos       (3U)                                        \n#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)                                        \n#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)                                        \n#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)                                        \n#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\n\n/******************  Bit definition for SAI_xDR register  ******************/\n#define SAI_xDR_DATA_Pos           (0U)                                        \n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk                            \n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)                                    \n#define SDIO_POWER_PWRCTRL_Msk         (0x3U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2U << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)                                    \n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFU << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)                                    \n#define SDIO_CLKCR_CLKEN_Msk           (0x1U << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)                                    \n#define SDIO_CLKCR_PWRSAV_Msk          (0x1U << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)                                   \n#define SDIO_CLKCR_BYPASS_Msk          (0x1U << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)                                   \n#define SDIO_CLKCR_WIDBUS_Msk          (0x3U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2U << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)                                   \n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1U << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)                                   \n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1U << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)                                    \n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)                                    \n#define SDIO_CMD_CMDINDEX_Msk          (0x3FU << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)                                    \n#define SDIO_CMD_WAITRESP_Msk          (0x3U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2U << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)                                    \n#define SDIO_CMD_WAITINT_Msk           (0x1U << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)                                    \n#define SDIO_CMD_WAITPEND_Msk          (0x1U << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)                                   \n#define SDIO_CMD_CPSMEN_Msk            (0x1U << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)                                   \n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1U << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n#define SDIO_CMD_ENCMDCOMPL_Pos        (12U)                                   \n#define SDIO_CMD_ENCMDCOMPL_Msk        (0x1U << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */\n#define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */\n#define SDIO_CMD_NIEN_Pos              (13U)                                   \n#define SDIO_CMD_NIEN_Msk              (0x1U << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */\n#define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */\n#define SDIO_CMD_CEATACMD_Pos          (14U)                                   \n#define SDIO_CMD_CEATACMD_Msk          (0x1U << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */\n#define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)                                    \n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FU << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)                                    \n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)                                    \n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)                                    \n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)                                    \n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)                                    \n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)                                    \n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)                                    \n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)                                    \n#define SDIO_DCTRL_DTEN_Msk            (0x1U << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)                                    \n#define SDIO_DCTRL_DTDIR_Msk           (0x1U << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)                                    \n#define SDIO_DCTRL_DTMODE_Msk          (0x1U << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)                                    \n#define SDIO_DCTRL_DMAEN_Msk           (0x1U << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)                                    \n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)                                    \n#define SDIO_DCTRL_RWSTART_Msk         (0x1U << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)                                    \n#define SDIO_DCTRL_RWSTOP_Msk          (0x1U << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)                                   \n#define SDIO_DCTRL_RWMOD_Msk           (0x1U << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)                                   \n#define SDIO_DCTRL_SDIOEN_Msk          (0x1U << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)                                    \n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)                                    \n#define SDIO_STA_CCRCFAIL_Msk          (0x1U << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)                                    \n#define SDIO_STA_DCRCFAIL_Msk          (0x1U << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)                                    \n#define SDIO_STA_CTIMEOUT_Msk          (0x1U << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)                                    \n#define SDIO_STA_DTIMEOUT_Msk          (0x1U << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)                                    \n#define SDIO_STA_TXUNDERR_Msk          (0x1U << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)                                    \n#define SDIO_STA_RXOVERR_Msk           (0x1U << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)                                    \n#define SDIO_STA_CMDREND_Msk           (0x1U << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)                                    \n#define SDIO_STA_CMDSENT_Msk           (0x1U << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)                                    \n#define SDIO_STA_DATAEND_Msk           (0x1U << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_STBITERR_Pos          (9U)                                    \n#define SDIO_STA_STBITERR_Msk          (0x1U << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */\n#define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */\n#define SDIO_STA_DBCKEND_Pos           (10U)                                   \n#define SDIO_STA_DBCKEND_Msk           (0x1U << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)                                   \n#define SDIO_STA_CMDACT_Msk            (0x1U << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)                                   \n#define SDIO_STA_TXACT_Msk             (0x1U << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)                                   \n#define SDIO_STA_RXACT_Msk             (0x1U << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)                                   \n#define SDIO_STA_TXFIFOHE_Msk          (0x1U << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)                                   \n#define SDIO_STA_RXFIFOHF_Msk          (0x1U << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)                                   \n#define SDIO_STA_TXFIFOF_Msk           (0x1U << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)                                   \n#define SDIO_STA_RXFIFOF_Msk           (0x1U << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)                                   \n#define SDIO_STA_TXFIFOE_Msk           (0x1U << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)                                   \n#define SDIO_STA_RXFIFOE_Msk           (0x1U << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)                                   \n#define SDIO_STA_TXDAVL_Msk            (0x1U << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)                                   \n#define SDIO_STA_RXDAVL_Msk            (0x1U << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)                                   \n#define SDIO_STA_SDIOIT_Msk            (0x1U << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n#define SDIO_STA_CEATAEND_Pos          (23U)                                   \n#define SDIO_STA_CEATAEND_Msk          (0x1U << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */\n#define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)                                    \n#define SDIO_ICR_CCRCFAILC_Msk         (0x1U << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)                                    \n#define SDIO_ICR_DCRCFAILC_Msk         (0x1U << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)                                    \n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1U << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)                                    \n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1U << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)                                    \n#define SDIO_ICR_TXUNDERRC_Msk         (0x1U << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)                                    \n#define SDIO_ICR_RXOVERRC_Msk          (0x1U << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)                                    \n#define SDIO_ICR_CMDRENDC_Msk          (0x1U << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)                                    \n#define SDIO_ICR_CMDSENTC_Msk          (0x1U << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)                                    \n#define SDIO_ICR_DATAENDC_Msk          (0x1U << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_STBITERRC_Pos         (9U)                                    \n#define SDIO_ICR_STBITERRC_Msk         (0x1U << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */\n#define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)                                   \n#define SDIO_ICR_DBCKENDC_Msk          (0x1U << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)                                   \n#define SDIO_ICR_SDIOITC_Msk           (0x1U << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n#define SDIO_ICR_CEATAENDC_Pos         (23U)                                   \n#define SDIO_ICR_CEATAENDC_Msk         (0x1U << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */\n#define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)                                    \n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1U << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)                                    \n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1U << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)                                    \n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1U << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)                                    \n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1U << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)                                    \n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1U << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)                                    \n#define SDIO_MASK_RXOVERRIE_Msk        (0x1U << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)                                    \n#define SDIO_MASK_CMDRENDIE_Msk        (0x1U << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)                                    \n#define SDIO_MASK_CMDSENTIE_Msk        (0x1U << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)                                    \n#define SDIO_MASK_DATAENDIE_Msk        (0x1U << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_STBITERRIE_Pos       (9U)                                    \n#define SDIO_MASK_STBITERRIE_Msk       (0x1U << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */\n#define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)                                   \n#define SDIO_MASK_DBCKENDIE_Msk        (0x1U << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)                                   \n#define SDIO_MASK_CMDACTIE_Msk         (0x1U << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)                                   \n#define SDIO_MASK_TXACTIE_Msk          (0x1U << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)                                   \n#define SDIO_MASK_RXACTIE_Msk          (0x1U << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)                                   \n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1U << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)                                   \n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1U << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)                                   \n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1U << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)                                   \n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1U << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)                                   \n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1U << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)                                   \n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1U << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)                                   \n#define SDIO_MASK_TXDAVLIE_Msk         (0x1U << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)                                   \n#define SDIO_MASK_RXDAVLIE_Msk         (0x1U << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)                                   \n#define SDIO_MASK_SDIOITIE_Msk         (0x1U << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n#define SDIO_MASK_CEATAENDIE_Pos       (23U)                                   \n#define SDIO_MASK_CEATAENDIE_Msk       (0x1U << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */\n#define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)                                    \n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)                                    \n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)                                       \n#define SPI_CR1_CPHA_Msk            (0x1U << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)                                       \n#define SPI_CR1_CPOL_Msk            (0x1U << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)                                       \n#define SPI_CR1_MSTR_Msk            (0x1U << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)                                       \n#define SPI_CR1_BR_Msk              (0x7U << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1U << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2U << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4U << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)                                       \n#define SPI_CR1_SPE_Msk             (0x1U << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)                                       \n#define SPI_CR1_LSBFIRST_Msk        (0x1U << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)                                       \n#define SPI_CR1_SSI_Msk             (0x1U << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)                                       \n#define SPI_CR1_SSM_Msk             (0x1U << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)                                      \n#define SPI_CR1_RXONLY_Msk          (0x1U << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)                                      \n#define SPI_CR1_DFF_Msk             (0x1U << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)                                      \n#define SPI_CR1_CRCNEXT_Msk         (0x1U << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)                                      \n#define SPI_CR1_CRCEN_Msk           (0x1U << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)                                      \n#define SPI_CR1_BIDIOE_Msk          (0x1U << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)                                      \n#define SPI_CR1_BIDIMODE_Msk        (0x1U << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)                                       \n#define SPI_CR2_RXDMAEN_Msk         (0x1U << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)                                       \n#define SPI_CR2_TXDMAEN_Msk         (0x1U << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)                                       \n#define SPI_CR2_SSOE_Msk            (0x1U << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)                                       \n#define SPI_CR2_FRF_Msk             (0x1U << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)                                       \n#define SPI_CR2_ERRIE_Msk           (0x1U << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)                                       \n#define SPI_CR2_RXNEIE_Msk          (0x1U << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)                                       \n#define SPI_CR2_TXEIE_Msk           (0x1U << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)                                       \n#define SPI_SR_RXNE_Msk             (0x1U << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)                                       \n#define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)                                       \n#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)                                       \n#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)                                       \n#define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)                                       \n#define SPI_SR_MODF_Msk             (0x1U << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)                                       \n#define SPI_SR_OVR_Msk              (0x1U << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)                                       \n#define SPI_SR_BSY_Msk              (0x1U << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)                                       \n#define SPI_SR_FRE_Msk              (0x1U << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)                                       \n#define SPI_DR_DR_Msk               (0xFFFFU << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       \n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       \n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       \n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       \n#define SPI_I2SCFGR_CHLEN_Msk       (0x1U << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       \n#define SPI_I2SCFGR_DATLEN_Msk      (0x3U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2U << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       \n#define SPI_I2SCFGR_CKPOL_Msk       (0x1U << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       \n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2U << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       \n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       \n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2U << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      \n#define SPI_I2SCFGR_I2SE_Msk        (0x1U << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      \n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1U << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       \n#define SPI_I2SPR_I2SDIV_Msk        (0xFFU << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)                                       \n#define SPI_I2SPR_ODD_Msk           (0x1U << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)                                       \n#define SPI_I2SPR_MCKOE_Msk         (0x1U << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)                              \n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n#define SYSCFG_MEMRMP_MEM_MODE_2             (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */\n#define SYSCFG_MEMRMP_UFB_MODE_Pos           (8U)                              \n#define SYSCFG_MEMRMP_UFB_MODE_Msk           (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */\n#define SYSCFG_MEMRMP_UFB_MODE               SYSCFG_MEMRMP_UFB_MODE_Msk        /*!< User Flash Bank mode    */\n#define SYSCFG_MEMRMP_SWP_FMC_Pos            (10U)                             \n#define SYSCFG_MEMRMP_SWP_FMC_Msk            (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */\n#define SYSCFG_MEMRMP_SWP_FMC                SYSCFG_MEMRMP_SWP_FMC_Msk         /*!< FMC memory mapping swap */\n#define SYSCFG_MEMRMP_SWP_FMC_0              (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */\n/* Legacy Defines */\n#define SYSCFG_SWP_FMC                  SYSCFG_MEMRMP_SWP_FMC\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_ADCxDC2_Pos               (16U)                             \n#define SYSCFG_PMC_ADCxDC2_Msk               (0x7U << SYSCFG_PMC_ADCxDC2_Pos)  /*!< 0x00070000 */\n#define SYSCFG_PMC_ADCxDC2                   SYSCFG_PMC_ADCxDC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC1DC2_Pos               (16U)                             \n#define SYSCFG_PMC_ADC1DC2_Msk               (0x1U << SYSCFG_PMC_ADC1DC2_Pos)  /*!< 0x00010000 */\n#define SYSCFG_PMC_ADC1DC2                   SYSCFG_PMC_ADC1DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC2DC2_Pos               (17U)                             \n#define SYSCFG_PMC_ADC2DC2_Msk               (0x1U << SYSCFG_PMC_ADC2DC2_Pos)  /*!< 0x00020000 */\n#define SYSCFG_PMC_ADC2DC2                   SYSCFG_PMC_ADC2DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_ADC3DC2_Pos               (18U)                             \n#define SYSCFG_PMC_ADC3DC2_Msk               (0x1U << SYSCFG_PMC_ADC3DC2_Pos)  /*!< 0x00040000 */\n#define SYSCFG_PMC_ADC3DC2                   SYSCFG_PMC_ADC3DC2_Msk            /*!< Refer to AN4073 on how to use this bit  */\n#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)                             \n#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */\n#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */\n/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */\n#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL    \n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)                              \n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)                              \n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)                              \n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)                             \n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration  \n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PJ              0x0009U                           /*!<PJ[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PK              0x000AU                           /*!<PK[0] pin */\n\n/**\n  * @brief   EXTI1 configuration  \n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PJ              0x0090U                           /*!<PJ[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PK              0x00A0U                           /*!<PK[1] pin */\n\n/**\n  * @brief   EXTI2 configuration  \n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PJ              0x0900U                           /*!<PJ[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PK              0x0A00U                           /*!<PK[2] pin */\n\n/**\n  * @brief   EXTI3 configuration  \n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PJ              0x9000U                           /*!<PJ[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PK              0xA000U                           /*!<PK[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)                              \n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)                              \n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)                              \n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)                             \n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration  \n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PJ              0x0009U                           /*!<PJ[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PK              0x000AU                           /*!<PK[4] pin */\n\n/**\n  * @brief   EXTI5 configuration  \n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PJ              0x0090U                           /*!<PJ[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PK              0x00A0U                           /*!<PK[5] pin */\n\n/**\n  * @brief   EXTI6 configuration  \n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PJ              0x0900U                           /*!<PJ[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PK              0x0A00U                           /*!<PK[6] pin */\n\n/**\n  * @brief   EXTI7 configuration  \n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PJ              0x9000U                           /*!<PJ[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PK              0xA000U                           /*!<PK[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)                              \n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)                              \n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)                              \n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)                             \n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration  \n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PJ              0x0009U                           /*!<PJ[8] pin */\n\n/**\n  * @brief   EXTI9 configuration  \n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PJ              0x0090U                           /*!<PJ[9] pin */\n\n/**\n  * @brief   EXTI10 configuration  \n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PJ             0x0900U                           /*!<PJ[10] pin */\n\n/**\n  * @brief   EXTI11 configuration  \n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PJ             0x9000U                           /*!<PJ[11] pin */\n\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)                              \n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)                              \n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)                              \n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)                             \n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration  \n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PI             0x0008U                           /*!<PI[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PJ             0x0009U                           /*!<PJ[12] pin */\n\n/**\n  * @brief   EXTI13 configuration  \n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PI             0x0008U                           /*!<PI[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PJ             0x0009U                           /*!<PJ[13] pin */\n\n/**\n  * @brief   EXTI14 configuration  \n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PI             0x0800U                           /*!<PI[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PJ             0x0900U                           /*!<PJ[14] pin */\n\n/**\n  * @brief   EXTI15 configuration  \n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PI             0x8000U                           /*!<PI[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PJ             0x9000U                           /*!<PJ[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)                              \n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)                              \n#define SYSCFG_CMPCR_READY_Msk               (0x1U << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)                                         \n#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)                                         \n#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)                                         \n#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)                                         \n#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)                                         \n#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)                                         \n#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)                                         \n#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)                                         \n#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)                                         \n#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)                                         \n#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)                                         \n#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)                                         \n#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)                                         \n#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)                                         \n#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)                                         \n#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)                                        \n#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)                                        \n#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)                                        \n#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)                                        \n#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)                                        \n#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)                                         \n#define TIM_SMCR_SMS_Msk          (0x7U << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1U << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2U << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4U << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)                                         \n#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)                                         \n#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)                                         \n#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)                                        \n#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)                                        \n#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)                                        \n#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)                                         \n#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)                                         \n#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)                                         \n#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)                                         \n#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)                                         \n#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)                                         \n#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)                                         \n#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)                                         \n#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)                                         \n#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)                                         \n#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)                                        \n#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)                                        \n#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)                                        \n#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)                                        \n#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)                                        \n#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)                                         \n#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)                                         \n#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)                                         \n#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)                                         \n#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)                                         \n#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)                                         \n#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)                                         \n#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)                                         \n#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)                                         \n#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)                                        \n#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)                                        \n#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)                                        \n#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)                                         \n#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)                                         \n#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)                                         \n#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)                                         \n#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)                                         \n#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)                                         \n#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)                                         \n#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)                                         \n#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)                                         \n#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)                                         \n#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)                                         \n#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)                                         \n#define TIM_CCMR1_OC1M_Msk        (0x7U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4U << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)                                         \n#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)                                         \n#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)                                        \n#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)                                        \n#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)                                        \n#define TIM_CCMR1_OC2M_Msk        (0x7U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4U << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)                                        \n#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         \n#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)                                         \n#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        \n#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)                                        \n#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)                                         \n#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)                                         \n#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)                                         \n#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)                                         \n#define TIM_CCMR2_OC3M_Msk        (0x7U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4U << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)                                         \n#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)                                         \n#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)                                        \n#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)                                        \n#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)                                        \n#define TIM_CCMR2_OC4M_Msk        (0x7U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4U << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)                                        \n#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         \n#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)                                         \n#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        \n#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)                                        \n#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)                                         \n#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)                                         \n#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)                                         \n#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)                                         \n#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)                                         \n#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)                                         \n#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)                                         \n#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)                                         \n#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)                                         \n#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)                                         \n#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)                                        \n#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)                                        \n#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)                                        \n#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)                                        \n#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)                                        \n#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)                                             \n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)                                         \n#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)                                         \n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)                                         \n#define TIM_RCR_REP_Msk           (0xFFU << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)                                         \n#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)                                         \n#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)                                         \n#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)                                         \n#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)                                         \n#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)                                         \n#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)                                        \n#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)                                        \n#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)                                        \n#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)                                        \n#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)                                        \n#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)                                        \n#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)                                         \n#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)                                         \n#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)                                         \n#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)                                          \n#define TIM_OR_TI1_RMP_Msk        (0x3U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2U << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)                                         \n#define TIM_OR_TI4_RMP_Msk        (0x3U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2U << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)                                        \n#define TIM_OR_ITR1_RMP_Msk       (0x3U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2U << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)                                     \n#define USART_SR_PE_Msk               (0x1U << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)                                     \n#define USART_SR_FE_Msk               (0x1U << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)                                     \n#define USART_SR_NE_Msk               (0x1U << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)                                     \n#define USART_SR_ORE_Msk              (0x1U << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)                                     \n#define USART_SR_IDLE_Msk             (0x1U << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)                                     \n#define USART_SR_RXNE_Msk             (0x1U << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)                                     \n#define USART_SR_TC_Msk               (0x1U << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)                                     \n#define USART_SR_TXE_Msk              (0x1U << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)                                     \n#define USART_SR_LBD_Msk              (0x1U << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)                                     \n#define USART_SR_CTS_Msk              (0x1U << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)                                     \n#define USART_DR_DR_Msk               (0x1FFU << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)                                     \n#define USART_BRR_DIV_Fraction_Msk    (0xFU << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)                                     \n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFU << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)                                     \n#define USART_CR1_SBK_Msk             (0x1U << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)                                     \n#define USART_CR1_RWU_Msk             (0x1U << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)                                     \n#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)                                     \n#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)                                     \n#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)                                     \n#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)                                     \n#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)                                     \n#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */\n#define USART_CR1_PEIE_Pos            (8U)                                     \n#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)                                     \n#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)                                    \n#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)                                    \n#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)                                    \n#define USART_CR1_M_Msk               (0x1U << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)                                    \n#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)                                    \n#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)                                     \n#define USART_CR2_ADD_Msk             (0xFU << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)                                     \n#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)                                     \n#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)                                     \n#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)                                     \n#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)                                    \n#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)                                    \n#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)                                    \n#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)                                    \n#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)                                     \n#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)                                     \n#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)                                     \n#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)                                     \n#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)                                     \n#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)                                     \n#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)                                     \n#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)                                     \n#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)                                     \n#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)                                     \n#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)                                    \n#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)                                    \n#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)                                     \n#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01U << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02U << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04U << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08U << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10U << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20U << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40U << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80U << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)                                     \n#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)                                           \n#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)                                           \n#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)                                           \n#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)                                           \n#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)                                           \n#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)                                           \n#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      \n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  \n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     \n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  \n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)                      \n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk   \n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      \n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    \n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      \n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk \n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)                      \n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk  \n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)                      \n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk  \n#define DBGMCU_CR_TRACE_MODE_0                       (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     \n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     \n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     \n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     \n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk \n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)                     \n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk \n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)                     \n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk \n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)                     \n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)                     \n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk \n/* Old IWDGSTOP bit definition, maintained for legacy purpose */\n#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)                      \n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk \n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)                      \n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk \n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)                     \n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk \n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)                     \n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk \n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)                     \n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk \n\n/******************************************************************************/\n/*                                                                            */\n/*                Ethernet MAC Registers bits definitions                     */\n/*                                                                            */\n/******************************************************************************/\n/* Bit definition for Ethernet MAC Control Register register */\n#define ETH_MACCR_WD_Pos                              (23U)                    \n#define ETH_MACCR_WD_Msk                              (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */\n#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */\n#define ETH_MACCR_JD_Pos                              (22U)                    \n#define ETH_MACCR_JD_Msk                              (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */\n#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */\n#define ETH_MACCR_IFG_Pos                             (17U)                    \n#define ETH_MACCR_IFG_Msk                             (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */\n#define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */\n#define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */\n#define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */\n#define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */\n#define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */\n#define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */\n#define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */\n#define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */\n#define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */\n#define ETH_MACCR_CSD_Pos                             (16U)                    \n#define ETH_MACCR_CSD_Msk                             (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */\n#define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */\n#define ETH_MACCR_FES_Pos                             (14U)                    \n#define ETH_MACCR_FES_Msk                             (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */\n#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */\n#define ETH_MACCR_ROD_Pos                             (13U)                    \n#define ETH_MACCR_ROD_Msk                             (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */\n#define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */\n#define ETH_MACCR_LM_Pos                              (12U)                    \n#define ETH_MACCR_LM_Msk                              (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */\n#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */\n#define ETH_MACCR_DM_Pos                              (11U)                    \n#define ETH_MACCR_DM_Msk                              (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */\n#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */\n#define ETH_MACCR_IPCO_Pos                            (10U)                    \n#define ETH_MACCR_IPCO_Msk                            (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */\n#define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */\n#define ETH_MACCR_RD_Pos                              (9U)                     \n#define ETH_MACCR_RD_Msk                              (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */\n#define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */\n#define ETH_MACCR_APCS_Pos                            (7U)                     \n#define ETH_MACCR_APCS_Msk                            (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */\n#define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */\n#define ETH_MACCR_BL_Pos                              (5U)                     \n#define ETH_MACCR_BL_Msk                              (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */\n#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling\n                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */\n#define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */\n#define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */\n#define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */\n#define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */ \n#define ETH_MACCR_DC_Pos                              (4U)                     \n#define ETH_MACCR_DC_Msk                              (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */\n#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */\n#define ETH_MACCR_TE_Pos                              (3U)                     \n#define ETH_MACCR_TE_Msk                              (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */\n#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */\n#define ETH_MACCR_RE_Pos                              (2U)                     \n#define ETH_MACCR_RE_Msk                              (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */\n#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */\n\n/* Bit definition for Ethernet MAC Frame Filter Register */\n#define ETH_MACFFR_RA_Pos                             (31U)                    \n#define ETH_MACFFR_RA_Msk                             (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */\n#define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */\n#define ETH_MACFFR_HPF_Pos                            (10U)                    \n#define ETH_MACFFR_HPF_Msk                            (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */\n#define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */\n#define ETH_MACFFR_SAF_Pos                            (9U)                     \n#define ETH_MACFFR_SAF_Msk                            (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */\n#define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */\n#define ETH_MACFFR_SAIF_Pos                           (8U)                     \n#define ETH_MACFFR_SAIF_Msk                           (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */\n#define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */ \n#define ETH_MACFFR_PCF_Pos                            (6U)                     \n#define ETH_MACFFR_PCF_Msk                            (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */\n#define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */\n#define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)                     \n#define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */\n#define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */\n#define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)                     \n#define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */\n#define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)                     \n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */\n#define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ \n#define ETH_MACFFR_BFD_Pos                            (5U)                     \n#define ETH_MACFFR_BFD_Msk                            (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */\n#define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */ \n#define ETH_MACFFR_PAM_Pos                            (4U)                     \n#define ETH_MACFFR_PAM_Msk                            (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */\n#define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */\n#define ETH_MACFFR_DAIF_Pos                           (3U)                     \n#define ETH_MACFFR_DAIF_Msk                           (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */\n#define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */\n#define ETH_MACFFR_HM_Pos                             (2U)                     \n#define ETH_MACFFR_HM_Msk                             (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */\n#define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */ \n#define ETH_MACFFR_HU_Pos                             (1U)                     \n#define ETH_MACFFR_HU_Msk                             (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */\n#define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */\n#define ETH_MACFFR_PM_Pos                             (0U)                     \n#define ETH_MACFFR_PM_Msk                             (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */\n#define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */\n\n/* Bit definition for Ethernet MAC Hash Table High Register */\n#define ETH_MACHTHR_HTH_Pos                           (0U)                     \n#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */\n\n/* Bit definition for Ethernet MAC Hash Table Low Register */\n#define ETH_MACHTLR_HTL_Pos                           (0U)                     \n#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */\n\n/* Bit definition for Ethernet MAC MII Address Register */\n#define ETH_MACMIIAR_PA_Pos                           (11U)                    \n#define ETH_MACMIIAR_PA_Msk                           (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */\n#define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */\n#define ETH_MACMIIAR_MR_Pos                           (6U)                     \n#define ETH_MACMIIAR_MR_Msk                           (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */\n#define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */\n#define ETH_MACMIIAR_CR_Pos                           (2U)                     \n#define ETH_MACMIIAR_CR_Msk                           (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */\n#define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */\n#define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */\n#define ETH_MACMIIAR_CR_Div62_Pos                     (2U)                     \n#define ETH_MACMIIAR_CR_Div62_Msk                     (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */\n#define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */\n#define ETH_MACMIIAR_CR_Div16_Pos                     (3U)                     \n#define ETH_MACMIIAR_CR_Div16_Msk                     (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */\n#define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */\n#define ETH_MACMIIAR_CR_Div26_Pos                     (2U)                     \n#define ETH_MACMIIAR_CR_Div26_Msk                     (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */\n#define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */\n#define ETH_MACMIIAR_CR_Div102_Pos                    (4U)                     \n#define ETH_MACMIIAR_CR_Div102_Msk                    (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */\n#define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */\n#define ETH_MACMIIAR_MW_Pos                           (1U)                     \n#define ETH_MACMIIAR_MW_Msk                           (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */\n#define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */\n#define ETH_MACMIIAR_MB_Pos                           (0U)                     \n#define ETH_MACMIIAR_MB_Msk                           (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */\n#define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */\n\n/* Bit definition for Ethernet MAC MII Data Register */\n#define ETH_MACMIIDR_MD_Pos                           (0U)                     \n#define ETH_MACMIIDR_MD_Msk                           (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */\n#define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */\n\n/* Bit definition for Ethernet MAC Flow Control Register */\n#define ETH_MACFCR_PT_Pos                             (16U)                    \n#define ETH_MACFCR_PT_Msk                             (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */\n#define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */\n#define ETH_MACFCR_ZQPD_Pos                           (7U)                     \n#define ETH_MACFCR_ZQPD_Msk                           (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */\n#define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */\n#define ETH_MACFCR_PLT_Pos                            (4U)                     \n#define ETH_MACFCR_PLT_Msk                            (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */\n#define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */\n#define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */\n#define ETH_MACFCR_PLT_Minus28_Pos                    (4U)                     \n#define ETH_MACFCR_PLT_Minus28_Msk                    (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */\n#define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */\n#define ETH_MACFCR_PLT_Minus144_Pos                   (5U)                     \n#define ETH_MACFCR_PLT_Minus144_Msk                   (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */\n#define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */\n#define ETH_MACFCR_PLT_Minus256_Pos                   (4U)                     \n#define ETH_MACFCR_PLT_Minus256_Msk                   (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */\n#define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */\n#define ETH_MACFCR_UPFD_Pos                           (3U)                     \n#define ETH_MACFCR_UPFD_Msk                           (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */\n#define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */\n#define ETH_MACFCR_RFCE_Pos                           (2U)                     \n#define ETH_MACFCR_RFCE_Msk                           (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */\n#define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */\n#define ETH_MACFCR_TFCE_Pos                           (1U)                     \n#define ETH_MACFCR_TFCE_Msk                           (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */\n#define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */\n#define ETH_MACFCR_FCBBPA_Pos                         (0U)                     \n#define ETH_MACFCR_FCBBPA_Msk                         (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */\n#define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */\n\n/* Bit definition for Ethernet MAC VLAN Tag Register */\n#define ETH_MACVLANTR_VLANTC_Pos                      (16U)                    \n#define ETH_MACVLANTR_VLANTC_Msk                      (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */\n#define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */\n#define ETH_MACVLANTR_VLANTI_Pos                      (0U)                     \n#define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */\n#define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */\n\n/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \n#define ETH_MACRWUFFR_D_Pos                           (0U)                     \n#define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */\n/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\n   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\n/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\n   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\n   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\n   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\n   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \n                              RSVD - Filter1 Command - RSVD - Filter0 Command\n   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\n   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\n   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\n\n/* Bit definition for Ethernet MAC PMT Control and Status Register */ \n#define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)                    \n#define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */\n#define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */\n#define ETH_MACPMTCSR_GU_Pos                          (9U)                     \n#define ETH_MACPMTCSR_GU_Msk                          (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */\n#define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */\n#define ETH_MACPMTCSR_WFR_Pos                         (6U)                     \n#define ETH_MACPMTCSR_WFR_Msk                         (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */\n#define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */\n#define ETH_MACPMTCSR_MPR_Pos                         (5U)                     \n#define ETH_MACPMTCSR_MPR_Msk                         (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */\n#define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */\n#define ETH_MACPMTCSR_WFE_Pos                         (2U)                     \n#define ETH_MACPMTCSR_WFE_Msk                         (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */\n#define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */\n#define ETH_MACPMTCSR_MPE_Pos                         (1U)                     \n#define ETH_MACPMTCSR_MPE_Msk                         (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */\n#define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */\n#define ETH_MACPMTCSR_PD_Pos                          (0U)                     \n#define ETH_MACPMTCSR_PD_Msk                          (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */\n#define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */\n\n/* Bit definition for Ethernet MAC debug Register */\n#define ETH_MACDBGR_TFF_Pos                           (25U)                    \n#define ETH_MACDBGR_TFF_Msk                           (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */\n#define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */\n#define ETH_MACDBGR_TFNE_Pos                          (24U)                    \n#define ETH_MACDBGR_TFNE_Msk                          (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */\n#define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */\n#define ETH_MACDBGR_TFWA_Pos                          (22U)                    \n#define ETH_MACDBGR_TFWA_Msk                          (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */\n#define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */\n#define ETH_MACDBGR_TFRS_Pos                          (20U)                    \n#define ETH_MACDBGR_TFRS_Msk                          (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */\n#define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */\n#define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)                    \n#define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */\n#define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */\n#define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)                    \n#define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */\n#define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */\n#define ETH_MACDBGR_TFRS_READ_Pos                     (20U)                    \n#define ETH_MACDBGR_TFRS_READ_Msk                     (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */\n#define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */\n#define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */\n#define ETH_MACDBGR_MTP_Pos                           (19U)                    \n#define ETH_MACDBGR_MTP_Msk                           (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */\n#define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */\n#define ETH_MACDBGR_MTFCS_Pos                         (17U)                    \n#define ETH_MACDBGR_MTFCS_Msk                         (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */\n#define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */\n#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)                    \n#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */\n#define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)                    \n#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */\n#define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */\n#define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)                    \n#define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */\n#define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */\n#define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */\n#define ETH_MACDBGR_MMTEA_Pos                         (16U)                    \n#define ETH_MACDBGR_MMTEA_Msk                         (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */\n#define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */\n#define ETH_MACDBGR_RFFL_Pos                          (8U)                     \n#define ETH_MACDBGR_RFFL_Msk                          (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */\n#define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */\n#define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)                     \n#define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */\n#define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */\n#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)                     \n#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */\n#define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */\n#define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)                     \n#define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */\n#define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */\n#define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */\n#define ETH_MACDBGR_RFRCS_Pos                         (5U)                     \n#define ETH_MACDBGR_RFRCS_Msk                         (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */\n#define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */\n#define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)                     \n#define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */\n#define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */\n#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)                     \n#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */\n#define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */\n#define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)                     \n#define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */\n#define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */\n#define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */\n#define ETH_MACDBGR_RFWRA_Pos                         (4U)                     \n#define ETH_MACDBGR_RFWRA_Msk                         (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */\n#define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */\n#define ETH_MACDBGR_MSFRWCS_Pos                       (1U)                     \n#define ETH_MACDBGR_MSFRWCS_Msk                       (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */\n#define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */\n#define ETH_MACDBGR_MSFRWCS_1                         (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */\n#define ETH_MACDBGR_MSFRWCS_0                         (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */\n#define ETH_MACDBGR_MMRPEA_Pos                        (0U)                     \n#define ETH_MACDBGR_MMRPEA_Msk                        (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */\n#define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */\n\n/* Bit definition for Ethernet MAC Status Register */\n#define ETH_MACSR_TSTS_Pos                            (9U)                     \n#define ETH_MACSR_TSTS_Msk                            (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */\n#define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */\n#define ETH_MACSR_MMCTS_Pos                           (6U)                     \n#define ETH_MACSR_MMCTS_Msk                           (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */\n#define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */\n#define ETH_MACSR_MMMCRS_Pos                          (5U)                     \n#define ETH_MACSR_MMMCRS_Msk                          (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */\n#define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */\n#define ETH_MACSR_MMCS_Pos                            (4U)                     \n#define ETH_MACSR_MMCS_Msk                            (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */\n#define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */\n#define ETH_MACSR_PMTS_Pos                            (3U)                     \n#define ETH_MACSR_PMTS_Msk                            (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */\n#define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */\n\n/* Bit definition for Ethernet MAC Interrupt Mask Register */\n#define ETH_MACIMR_TSTIM_Pos                          (9U)                     \n#define ETH_MACIMR_TSTIM_Msk                          (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */\n#define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */\n#define ETH_MACIMR_PMTIM_Pos                          (3U)                     \n#define ETH_MACIMR_PMTIM_Msk                          (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */\n#define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */\n\n/* Bit definition for Ethernet MAC Address0 High Register */\n#define ETH_MACA0HR_MACA0H_Pos                        (0U)                     \n#define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */\n\n/* Bit definition for Ethernet MAC Address0 Low Register */\n#define ETH_MACA0LR_MACA0L_Pos                        (0U)                     \n#define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */\n\n/* Bit definition for Ethernet MAC Address1 High Register */\n#define ETH_MACA1HR_AE_Pos                            (31U)                    \n#define ETH_MACA1HR_AE_Msk                            (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */\n#define ETH_MACA1HR_SA_Pos                            (30U)                    \n#define ETH_MACA1HR_SA_Msk                            (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */\n#define ETH_MACA1HR_MBC_Pos                           (24U)                    \n#define ETH_MACA1HR_MBC_Msk                           (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\n#define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */\n#define ETH_MACA1HR_MACA1H_Pos                        (0U)                     \n#define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */\n\n/* Bit definition for Ethernet MAC Address1 Low Register */\n#define ETH_MACA1LR_MACA1L_Pos                        (0U)                     \n#define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */\n\n/* Bit definition for Ethernet MAC Address2 High Register */\n#define ETH_MACA2HR_AE_Pos                            (31U)                    \n#define ETH_MACA2HR_AE_Msk                            (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */\n#define ETH_MACA2HR_SA_Pos                            (30U)                    \n#define ETH_MACA2HR_SA_Msk                            (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */\n#define ETH_MACA2HR_MBC_Pos                           (24U)                    \n#define ETH_MACA2HR_MBC_Msk                           (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */\n#define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */\n#define ETH_MACA2HR_MACA2H_Pos                        (0U)                     \n#define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */\n\n/* Bit definition for Ethernet MAC Address2 Low Register */\n#define ETH_MACA2LR_MACA2L_Pos                        (0U)                     \n#define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */\n\n/* Bit definition for Ethernet MAC Address3 High Register */\n#define ETH_MACA3HR_AE_Pos                            (31U)                    \n#define ETH_MACA3HR_AE_Msk                            (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */\n#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */\n#define ETH_MACA3HR_SA_Pos                            (30U)                    \n#define ETH_MACA3HR_SA_Msk                            (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */\n#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */\n#define ETH_MACA3HR_MBC_Pos                           (24U)                    \n#define ETH_MACA3HR_MBC_Msk                           (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */\n#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */\n#define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */\n#define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */\n#define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */\n#define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */\n#define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */\n#define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */\n#define ETH_MACA3HR_MACA3H_Pos                        (0U)                     \n#define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */\n#define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */\n\n/* Bit definition for Ethernet MAC Address3 Low Register */\n#define ETH_MACA3LR_MACA3L_Pos                        (0U)                     \n#define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */\n\n/******************************************************************************/\n/*                Ethernet MMC Registers bits definition                      */\n/******************************************************************************/\n\n/* Bit definition for Ethernet MMC Contol Register */\n#define ETH_MMCCR_MCFHP_Pos                           (5U)                     \n#define ETH_MMCCR_MCFHP_Msk                           (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */\n#define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */\n#define ETH_MMCCR_MCP_Pos                             (4U)                     \n#define ETH_MMCCR_MCP_Msk                             (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */\n#define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */\n#define ETH_MMCCR_MCF_Pos                             (3U)                     \n#define ETH_MMCCR_MCF_Msk                             (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */\n#define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */\n#define ETH_MMCCR_ROR_Pos                             (2U)                     \n#define ETH_MMCCR_ROR_Msk                             (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */\n#define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */\n#define ETH_MMCCR_CSR_Pos                             (1U)                     \n#define ETH_MMCCR_CSR_Msk                             (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */\n#define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */\n#define ETH_MMCCR_CR_Pos                              (0U)                     \n#define ETH_MMCCR_CR_Msk                              (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */\n#define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */\n\n/* Bit definition for Ethernet MMC Receive Interrupt Register */\n#define ETH_MMCRIR_RGUFS_Pos                          (17U)                    \n#define ETH_MMCRIR_RGUFS_Msk                          (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */\n#define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */\n#define ETH_MMCRIR_RFAES_Pos                          (6U)                     \n#define ETH_MMCRIR_RFAES_Msk                          (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */\n#define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */\n#define ETH_MMCRIR_RFCES_Pos                          (5U)                     \n#define ETH_MMCRIR_RFCES_Msk                          (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */\n#define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmit Interrupt Register */\n#define ETH_MMCTIR_TGFS_Pos                           (21U)                    \n#define ETH_MMCTIR_TGFS_Msk                           (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */\n#define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */\n#define ETH_MMCTIR_TGFMSCS_Pos                        (15U)                    \n#define ETH_MMCTIR_TGFMSCS_Msk                        (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */\n#define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */\n#define ETH_MMCTIR_TGFSCS_Pos                         (14U)                    \n#define ETH_MMCTIR_TGFSCS_Msk                         (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */\n#define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\n#define ETH_MMCRIMR_RGUFM_Pos                         (17U)                    \n#define ETH_MMCRIMR_RGUFM_Msk                         (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */\n#define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\n#define ETH_MMCRIMR_RFAEM_Pos                         (6U)                     \n#define ETH_MMCRIMR_RFAEM_Msk                         (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */\n#define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\n#define ETH_MMCRIMR_RFCEM_Pos                         (5U)                     \n#define ETH_MMCRIMR_RFCEM_Msk                         (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */\n#define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\n#define ETH_MMCTIMR_TGFM_Pos                          (21U)                    \n#define ETH_MMCTIMR_TGFM_Msk                          (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */\n#define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\n#define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)                    \n#define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */\n#define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\n#define ETH_MMCTIMR_TGFSCM_Pos                        (14U)                    \n#define ETH_MMCTIMR_TGFSCM_Msk                        (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */\n#define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\n#define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)                     \n#define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\n#define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)                     \n#define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\n\n/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\n#define ETH_MMCTGFCR_TGFC_Pos                         (0U)                     \n#define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */\n\n/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\n#define ETH_MMCRFCECR_RFCEC_Pos                       (0U)                     \n#define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */\n\n/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\n#define ETH_MMCRFAECR_RFAEC_Pos                       (0U)                     \n#define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */\n\n/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\n#define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)                     \n#define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */\n#define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */\n\n/******************************************************************************/\n/*               Ethernet PTP Registers bits definition                       */\n/******************************************************************************/\n\n/* Bit definition for Ethernet PTP Time Stamp Contol Register */\n#define ETH_PTPTSCR_TSCNT_Pos                         (16U)                    \n#define ETH_PTPTSCR_TSCNT_Msk                         (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */\n#define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */\n#define ETH_PTPTSSR_TSSMRME_Pos                       (15U)                    \n#define ETH_PTPTSSR_TSSMRME_Msk                       (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */\n#define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */\n#define ETH_PTPTSSR_TSSEME_Pos                        (14U)                    \n#define ETH_PTPTSSR_TSSEME_Msk                        (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */\n#define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */\n#define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)                    \n#define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */\n#define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */\n#define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)                    \n#define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */\n#define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */\n#define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)                    \n#define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */\n#define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */\n#define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)                    \n#define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */\n#define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */\n#define ETH_PTPTSSR_TSSSR_Pos                         (9U)                     \n#define ETH_PTPTSSR_TSSSR_Msk                         (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */\n#define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */\n#define ETH_PTPTSSR_TSSARFE_Pos                       (8U)                     \n#define ETH_PTPTSSR_TSSARFE_Msk                       (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */\n#define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */\n\n#define ETH_PTPTSCR_TSARU_Pos                         (5U)                     \n#define ETH_PTPTSCR_TSARU_Msk                         (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */\n#define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */\n#define ETH_PTPTSCR_TSITE_Pos                         (4U)                     \n#define ETH_PTPTSCR_TSITE_Msk                         (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */\n#define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */\n#define ETH_PTPTSCR_TSSTU_Pos                         (3U)                     \n#define ETH_PTPTSCR_TSSTU_Msk                         (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */\n#define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */\n#define ETH_PTPTSCR_TSSTI_Pos                         (2U)                     \n#define ETH_PTPTSCR_TSSTI_Msk                         (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */\n#define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */\n#define ETH_PTPTSCR_TSFCU_Pos                         (1U)                     \n#define ETH_PTPTSCR_TSFCU_Msk                         (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */\n#define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */\n#define ETH_PTPTSCR_TSE_Pos                           (0U)                     \n#define ETH_PTPTSCR_TSE_Msk                           (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */\n#define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */\n\n/* Bit definition for Ethernet PTP Sub-Second Increment Register */\n#define ETH_PTPSSIR_STSSI_Pos                         (0U)                     \n#define ETH_PTPSSIR_STSSI_Msk                         (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */\n#define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */\n\n/* Bit definition for Ethernet PTP Time Stamp High Register */\n#define ETH_PTPTSHR_STS_Pos                           (0U)                     \n#define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */\n\n/* Bit definition for Ethernet PTP Time Stamp Low Register */\n#define ETH_PTPTSLR_STPNS_Pos                         (31U)                    \n#define ETH_PTPTSLR_STPNS_Msk                         (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */\n#define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */\n#define ETH_PTPTSLR_STSS_Pos                          (0U)                     \n#define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */\n#define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp High Update Register */\n#define ETH_PTPTSHUR_TSUS_Pos                         (0U)                     \n#define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\n#define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)                    \n#define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */\n#define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */\n#define ETH_PTPTSLUR_TSUSS_Pos                        (0U)                     \n#define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */\n#define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */\n\n/* Bit definition for Ethernet PTP Time Stamp Addend Register */\n#define ETH_PTPTSAR_TSA_Pos                           (0U)                     \n#define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */\n\n/* Bit definition for Ethernet PTP Target Time High Register */\n#define ETH_PTPTTHR_TTSH_Pos                          (0U)                     \n#define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */\n\n/* Bit definition for Ethernet PTP Target Time Low Register */\n#define ETH_PTPTTLR_TTSL_Pos                          (0U)                     \n#define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */\n\n/* Bit definition for Ethernet PTP Time Stamp Status Register */\n#define ETH_PTPTSSR_TSTTR_Pos                         (5U)                     \n#define ETH_PTPTSSR_TSTTR_Msk                         (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */\n#define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */\n#define ETH_PTPTSSR_TSSO_Pos                          (4U)                     \n#define ETH_PTPTSSR_TSSO_Msk                          (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */\n#define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */\n\n/******************************************************************************/\n/*                 Ethernet DMA Registers bits definition                     */\n/******************************************************************************/\n\n/* Bit definition for Ethernet DMA Bus Mode Register */\n#define ETH_DMABMR_AAB_Pos                            (25U)                    \n#define ETH_DMABMR_AAB_Msk                            (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */\n#define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */\n#define ETH_DMABMR_FPM_Pos                            (24U)                    \n#define ETH_DMABMR_FPM_Msk                            (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */\n#define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */\n#define ETH_DMABMR_USP_Pos                            (23U)                    \n#define ETH_DMABMR_USP_Msk                            (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */\n#define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */\n#define ETH_DMABMR_RDP_Pos                            (17U)                    \n#define ETH_DMABMR_RDP_Msk                            (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */\n#define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */\n#define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\n#define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\n#define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\n#define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\n#define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\n#define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                \n#define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\n#define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\n#define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\n#define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\n#define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\n#define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  \n#define ETH_DMABMR_FB_Pos                             (16U)                    \n#define ETH_DMABMR_FB_Msk                             (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */\n#define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */\n#define ETH_DMABMR_RTPR_Pos                           (14U)                    \n#define ETH_DMABMR_RTPR_Msk                           (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */\n#define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */\n#define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */  \n#define ETH_DMABMR_PBL_Pos                            (8U)                     \n#define ETH_DMABMR_PBL_Msk                            (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */\n#define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */\n#define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\n#define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\n#define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\n#define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\n#define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\n#define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                \n#define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\n#define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\n#define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\n#define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\n#define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\n#define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\n#define ETH_DMABMR_EDE_Pos                            (7U)                     \n#define ETH_DMABMR_EDE_Msk                            (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */\n#define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */\n#define ETH_DMABMR_DSL_Pos                            (2U)                     \n#define ETH_DMABMR_DSL_Msk                            (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */\n#define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */\n#define ETH_DMABMR_DA_Pos                             (1U)                     \n#define ETH_DMABMR_DA_Msk                             (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */\n#define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */\n#define ETH_DMABMR_SR_Pos                             (0U)                     \n#define ETH_DMABMR_SR_Msk                             (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */\n#define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */\n\n/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\n#define ETH_DMATPDR_TPD_Pos                           (0U)                     \n#define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */\n\n/* Bit definition for Ethernet DMA Receive Poll Demand Register */\n#define ETH_DMARPDR_RPD_Pos                           (0U)                     \n#define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */\n\n/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\n#define ETH_DMARDLAR_SRL_Pos                          (0U)                     \n#define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */\n\n/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\n#define ETH_DMATDLAR_STL_Pos                          (0U)                     \n#define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */\n\n/* Bit definition for Ethernet DMA Status Register */\n#define ETH_DMASR_TSTS_Pos                            (29U)                    \n#define ETH_DMASR_TSTS_Msk                            (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */\n#define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */\n#define ETH_DMASR_PMTS_Pos                            (28U)                    \n#define ETH_DMASR_PMTS_Msk                            (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */\n#define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */\n#define ETH_DMASR_MMCS_Pos                            (27U)                    \n#define ETH_DMASR_MMCS_Msk                            (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */\n#define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */\n#define ETH_DMASR_EBS_Pos                             (23U)                    \n#define ETH_DMASR_EBS_Msk                             (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */\n#define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */\n  /* combination with EBS[2:0] for GetFlagStatus function */\n#define ETH_DMASR_EBS_DescAccess_Pos                  (25U)                    \n#define ETH_DMASR_EBS_DescAccess_Msk                  (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */\n#define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */\n#define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)                    \n#define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */\n#define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */\n#define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)                    \n#define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */\n#define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */\n#define ETH_DMASR_TPS_Pos                             (20U)                    \n#define ETH_DMASR_TPS_Msk                             (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */\n#define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */\n#define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */\n#define ETH_DMASR_TPS_Fetching_Pos                    (20U)                    \n#define ETH_DMASR_TPS_Fetching_Msk                    (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */\n#define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */\n#define ETH_DMASR_TPS_Waiting_Pos                     (21U)                    \n#define ETH_DMASR_TPS_Waiting_Msk                     (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */\n#define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */\n#define ETH_DMASR_TPS_Reading_Pos                     (20U)                    \n#define ETH_DMASR_TPS_Reading_Msk                     (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */\n#define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */\n#define ETH_DMASR_TPS_Suspended_Pos                   (21U)                    \n#define ETH_DMASR_TPS_Suspended_Msk                   (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */\n#define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */\n#define ETH_DMASR_TPS_Closing_Pos                     (20U)                    \n#define ETH_DMASR_TPS_Closing_Msk                     (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */\n#define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */\n#define ETH_DMASR_RPS_Pos                             (17U)                    \n#define ETH_DMASR_RPS_Msk                             (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */\n#define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */\n#define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */\n#define ETH_DMASR_RPS_Fetching_Pos                    (17U)                    \n#define ETH_DMASR_RPS_Fetching_Msk                    (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */\n#define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */\n#define ETH_DMASR_RPS_Waiting_Pos                     (17U)                    \n#define ETH_DMASR_RPS_Waiting_Msk                     (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */\n#define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */\n#define ETH_DMASR_RPS_Suspended_Pos                   (19U)                    \n#define ETH_DMASR_RPS_Suspended_Msk                   (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */\n#define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */\n#define ETH_DMASR_RPS_Closing_Pos                     (17U)                    \n#define ETH_DMASR_RPS_Closing_Msk                     (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */\n#define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */\n#define ETH_DMASR_RPS_Queuing_Pos                     (17U)                    \n#define ETH_DMASR_RPS_Queuing_Msk                     (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */\n#define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */\n#define ETH_DMASR_NIS_Pos                             (16U)                    \n#define ETH_DMASR_NIS_Msk                             (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */\n#define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */\n#define ETH_DMASR_AIS_Pos                             (15U)                    \n#define ETH_DMASR_AIS_Msk                             (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */\n#define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */\n#define ETH_DMASR_ERS_Pos                             (14U)                    \n#define ETH_DMASR_ERS_Msk                             (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */\n#define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */\n#define ETH_DMASR_FBES_Pos                            (13U)                    \n#define ETH_DMASR_FBES_Msk                            (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */\n#define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */\n#define ETH_DMASR_ETS_Pos                             (10U)                    \n#define ETH_DMASR_ETS_Msk                             (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */\n#define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */\n#define ETH_DMASR_RWTS_Pos                            (9U)                     \n#define ETH_DMASR_RWTS_Msk                            (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */\n#define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */\n#define ETH_DMASR_RPSS_Pos                            (8U)                     \n#define ETH_DMASR_RPSS_Msk                            (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */\n#define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */\n#define ETH_DMASR_RBUS_Pos                            (7U)                     \n#define ETH_DMASR_RBUS_Msk                            (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */\n#define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */\n#define ETH_DMASR_RS_Pos                              (6U)                     \n#define ETH_DMASR_RS_Msk                              (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */\n#define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */\n#define ETH_DMASR_TUS_Pos                             (5U)                     \n#define ETH_DMASR_TUS_Msk                             (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */\n#define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */\n#define ETH_DMASR_ROS_Pos                             (4U)                     \n#define ETH_DMASR_ROS_Msk                             (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */\n#define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */\n#define ETH_DMASR_TJTS_Pos                            (3U)                     \n#define ETH_DMASR_TJTS_Msk                            (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */\n#define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */\n#define ETH_DMASR_TBUS_Pos                            (2U)                     \n#define ETH_DMASR_TBUS_Msk                            (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */\n#define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */\n#define ETH_DMASR_TPSS_Pos                            (1U)                     \n#define ETH_DMASR_TPSS_Msk                            (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */\n#define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */\n#define ETH_DMASR_TS_Pos                              (0U)                     \n#define ETH_DMASR_TS_Msk                              (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */\n#define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */\n\n/* Bit definition for Ethernet DMA Operation Mode Register */\n#define ETH_DMAOMR_DTCEFD_Pos                         (26U)                    \n#define ETH_DMAOMR_DTCEFD_Msk                         (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */\n#define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */\n#define ETH_DMAOMR_RSF_Pos                            (25U)                    \n#define ETH_DMAOMR_RSF_Msk                            (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */\n#define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */\n#define ETH_DMAOMR_DFRF_Pos                           (24U)                    \n#define ETH_DMAOMR_DFRF_Msk                           (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */\n#define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */\n#define ETH_DMAOMR_TSF_Pos                            (21U)                    \n#define ETH_DMAOMR_TSF_Msk                            (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */\n#define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */\n#define ETH_DMAOMR_FTF_Pos                            (20U)                    \n#define ETH_DMAOMR_FTF_Msk                            (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */\n#define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */\n#define ETH_DMAOMR_TTC_Pos                            (14U)                    \n#define ETH_DMAOMR_TTC_Msk                            (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */\n#define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */\n#define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */\n#define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */\n#define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */\n#define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */\n#define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */\n#define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */\n#define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */\n#define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */\n#define ETH_DMAOMR_ST_Pos                             (13U)                    \n#define ETH_DMAOMR_ST_Msk                             (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */\n#define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */\n#define ETH_DMAOMR_FEF_Pos                            (7U)                     \n#define ETH_DMAOMR_FEF_Msk                            (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */\n#define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */\n#define ETH_DMAOMR_FUGF_Pos                           (6U)                     \n#define ETH_DMAOMR_FUGF_Msk                           (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */\n#define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */\n#define ETH_DMAOMR_RTC_Pos                            (3U)                     \n#define ETH_DMAOMR_RTC_Msk                            (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */\n#define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */\n#define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */\n#define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */\n#define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */\n#define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */\n#define ETH_DMAOMR_OSF_Pos                            (2U)                     \n#define ETH_DMAOMR_OSF_Msk                            (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */\n#define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */\n#define ETH_DMAOMR_SR_Pos                             (1U)                     \n#define ETH_DMAOMR_SR_Msk                             (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */\n#define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */\n\n/* Bit definition for Ethernet DMA Interrupt Enable Register */\n#define ETH_DMAIER_NISE_Pos                           (16U)                    \n#define ETH_DMAIER_NISE_Msk                           (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */\n#define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */\n#define ETH_DMAIER_AISE_Pos                           (15U)                    \n#define ETH_DMAIER_AISE_Msk                           (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */\n#define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */\n#define ETH_DMAIER_ERIE_Pos                           (14U)                    \n#define ETH_DMAIER_ERIE_Msk                           (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */\n#define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */\n#define ETH_DMAIER_FBEIE_Pos                          (13U)                    \n#define ETH_DMAIER_FBEIE_Msk                          (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */\n#define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */\n#define ETH_DMAIER_ETIE_Pos                           (10U)                    \n#define ETH_DMAIER_ETIE_Msk                           (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */\n#define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */\n#define ETH_DMAIER_RWTIE_Pos                          (9U)                     \n#define ETH_DMAIER_RWTIE_Msk                          (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */\n#define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */\n#define ETH_DMAIER_RPSIE_Pos                          (8U)                     \n#define ETH_DMAIER_RPSIE_Msk                          (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */\n#define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */\n#define ETH_DMAIER_RBUIE_Pos                          (7U)                     \n#define ETH_DMAIER_RBUIE_Msk                          (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */\n#define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */\n#define ETH_DMAIER_RIE_Pos                            (6U)                     \n#define ETH_DMAIER_RIE_Msk                            (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */\n#define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */\n#define ETH_DMAIER_TUIE_Pos                           (5U)                     \n#define ETH_DMAIER_TUIE_Msk                           (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */\n#define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */\n#define ETH_DMAIER_ROIE_Pos                           (4U)                     \n#define ETH_DMAIER_ROIE_Msk                           (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */\n#define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */\n#define ETH_DMAIER_TJTIE_Pos                          (3U)                     \n#define ETH_DMAIER_TJTIE_Msk                          (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */\n#define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */\n#define ETH_DMAIER_TBUIE_Pos                          (2U)                     \n#define ETH_DMAIER_TBUIE_Msk                          (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */\n#define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */\n#define ETH_DMAIER_TPSIE_Pos                          (1U)                     \n#define ETH_DMAIER_TPSIE_Msk                          (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */\n#define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */\n#define ETH_DMAIER_TIE_Pos                            (0U)                     \n#define ETH_DMAIER_TIE_Msk                            (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */\n#define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */\n\n/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\n#define ETH_DMAMFBOCR_OFOC_Pos                        (28U)                    \n#define ETH_DMAMFBOCR_OFOC_Msk                        (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */\n#define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */\n#define ETH_DMAMFBOCR_MFA_Pos                         (17U)                    \n#define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */\n#define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */\n#define ETH_DMAMFBOCR_OMFC_Pos                        (16U)                    \n#define ETH_DMAMFBOCR_OMFC_Msk                        (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */\n#define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */\n#define ETH_DMAMFBOCR_MFC_Pos                         (0U)                     \n#define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */\n#define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */\n\n/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\n#define ETH_DMACHTDR_HTDAP_Pos                        (0U)                     \n#define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\n#define ETH_DMACHRDR_HRDAP_Pos                        (0U)                     \n#define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\n#define ETH_DMACHTBAR_HTBAP_Pos                       (0U)                     \n#define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */\n\n/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\n#define ETH_DMACHRBAR_HRBAP_Pos                       (0U)                     \n#define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */\n#define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          \n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          \n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)                          \n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)                          \n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)                         \n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)                         \n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)                         \n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)                         \n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)                         \n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)                         \n#define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          \n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          \n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          \n#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          \n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)                          \n#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         \n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         \n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          \n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          \n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          \n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          \n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          \n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          \n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         \n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         \n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         \n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          \n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          \n#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          \n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          \n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          \n#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          \n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          \n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          \n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         \n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         \n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          \n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          \n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         \n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          \n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          \n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)                          \n#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          \n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          \n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          \n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          \n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          \n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          \n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          \n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          \n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          \n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          \n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         \n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         \n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         \n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         \n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         \n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         \n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         \n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         \n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         \n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         \n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         \n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         \n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         \n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         \n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          \n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          \n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          \n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          \n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          \n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          \n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         \n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         \n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          \n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          \n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          \n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          \n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          \n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          \n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          \n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          \n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          \n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         \n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         \n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          \n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          \n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          \n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          \n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          \n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          \n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          \n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          \n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          \n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          \n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          \n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          \n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          \n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          \n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          \n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          \n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         \n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         \n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         \n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         \n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         \n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         \n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         \n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         \n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         \n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         \n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         \n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         \n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         \n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         \n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         \n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         \n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         \n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         \n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          \n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          \n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          \n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          \n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          \n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          \n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          \n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         \n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         \n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         \n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         \n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         \n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         \n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         \n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         \n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         \n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         \n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         \n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         \n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         \n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         \n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         \n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         \n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         \n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         \n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         \n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          \n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         \n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          \n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          \n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          \n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         \n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         \n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          \n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         \n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          \n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          \n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)                          \n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)                         \n#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)                          \n#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)                         \n#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          \n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          \n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         \n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         \n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          \n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          \n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          \n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         \n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         \n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         \n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          \n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          \n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         \n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         \n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)                         \n#define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/ \n#define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)                         \n#define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)                         \n#define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)                         \n#define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */\n#define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)                         \n#define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/ \n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          \n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         \n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          \n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          \n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          \n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          \n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          \n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          \n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          \n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          \n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          \n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         \n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          \n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          \n#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)                          \n#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          \n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)                          \n#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          \n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)                          \n#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          \n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)                          \n#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         \n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         \n#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         \n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         \n#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          \n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          \n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          \n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          \n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          \n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          \n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          \n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          \n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         \n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         \n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         \n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          \n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         \n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          \n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         \n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         \n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         \n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         \n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         \n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         \n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         \n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         \n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         \n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         \n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         \n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         \n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          \n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         \n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         \n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         \n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         \n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         \n#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         \n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         \n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         \n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         \n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          \n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          \n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         \n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         \n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         \n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          \n#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)                          \n#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          \n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)                          \n#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)                          \n#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)                          \n#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)                          \n#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          \n#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          \n#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          \n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         \n#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          \n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          \n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          \n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          \n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          \n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          \n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          \n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          \n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         \n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         \n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         \n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          \n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          \n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          \n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          \n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          \n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          \n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          \n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          \n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          \n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          \n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         \n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          \n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         \n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         \n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          \n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         \n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         \n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         \n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          \n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          \n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          \n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          \n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         \n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          \n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         \n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         \n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         \n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         \n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         \n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         \n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         \n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         \n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         \n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         \n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         \n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          \n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          \n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          \n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          \n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          \n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         \n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          \n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         \n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         \n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          \n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          \n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          \n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/* Legacy define */\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_CHNUM_Pos                        (0U)                          \n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)                          \n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)                         \n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)                         \n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)                          \n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)                         \n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n/******************************* DCMI Instances *******************************/\n#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)\n\n/******************************* DMA2D Instances *******************************/\n#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH) || \\\n                                        ((INSTANCE) == GPIOI) || \\\n                                        ((INSTANCE) == GPIOJ) || \\\n                                        ((INSTANCE) == GPIOK))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n/****************************** LTDC Instances ********************************/\n#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/******************************* SAI Instances ********************************/\n#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \\\n                                     ((PERIPH) == SAI1_Block_B))\n/* Legacy define */\n\n#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)  || \\\n                                       ((INSTANCE) == SPI2)  || \\\n                                       ((INSTANCE) == SPI3)  || \\\n                                       ((INSTANCE) == SPI4)  || \\\n                                       ((INSTANCE) == SPI5)  || \\\n                                       ((INSTANCE) == SPI6))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12)) \n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM7)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9) || \\\n                                                      ((INSTANCE) == TIM12))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == UART4)  || \\\n                                               ((INSTANCE) == UART5)  || \\\n                                               ((INSTANCE) == USART6) || \\\n                                               ((INSTANCE) == UART7)  || \\\n                                               ((INSTANCE) == UART8))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6) || \\\n                                    ((INSTANCE) == UART7)  || \\\n                                    ((INSTANCE) == UART8))                                     \n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x24003000U\n#define RCC_PLLSAICFGR_RST_VALUE           0x24003000U\n\n#define RCC_MAX_FREQUENCY           180000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2    168000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE3    120000000U         /*!< Maximum frequency for system clock at power scale3, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */\n#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */\n#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */\n#define FLASH_SCALE2_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 2  */\n\n#define FLASH_SCALE3_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 3  */\n#define FLASH_SCALE3_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 3  */\n#define FLASH_SCALE3_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 3  */\n\n#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */\n/******************************************************************************/\n/*  For a painless codes migration between the STM32F4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32F4 Family                              */\n/******************************************************************************/\n/* Aliases for __IRQn */\n#define FSMC_IRQn              FMC_IRQn\n\n/* Aliases for __IRQHandler */\n#define FSMC_IRQHandler        FMC_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F429xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.\n  *            \n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The STM32F4xx device used in the target application\n  *              - To use or not the peripherals drivers in application code(i.e. \n  *                code will be based on direct access to peripherals registers \n  *                rather than drivers API), this option is controlled by \n  *                \"#define USE_HAL_DRIVER\"\n  *  \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx\n  * @{\n  */\n    \n#ifndef __STM32F4xx_H\n#define __STM32F4xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n   \n/** @addtogroup Library_configuration_section\n  * @{\n  */\n  \n/**\n  * @brief STM32 Family\n  */\n#if !defined  (STM32F4)\n#define STM32F4\n#endif /* STM32F4 */\n\n/* Uncomment the line below according to the target STM32 device used in your\n   application \n  */\n#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \\\n    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \\\n    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \\\n    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \\\n    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \\\n    !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)\n  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */\n  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */\n  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */\n  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */\n  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */\n  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */\n  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, \n                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */\n  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, \n                                   STM32F439NI, STM32F439IG and STM32F439II Devices */\n  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */\n  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */\n  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */\n  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */\n  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */\n  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */\n  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, \n                                   and STM32F446ZE Devices */\n  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, \n                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */\n  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG \n                                   and STM32F479NG Devices */\n  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */\n  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */\n  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */\n  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */\n  /* #define STM32F413xx */   /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,\n                                   STM32F413RG, STM32F413VG and STM32F413ZG Devices */\n  /* #define STM32F423xx */   /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */\n#endif\n   \n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will \n   be based on direct access to peripherals registers \n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS version number V2.6.2\n  */\n#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */\n#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */\n#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */\n#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\n#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\\\n                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\\\n                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\\\n                                         |(__STM32F4xx_CMSIS_VERSION))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32F405xx)\n  #include \"stm32f405xx.h\"\n#elif defined(STM32F415xx)\n  #include \"stm32f415xx.h\"\n#elif defined(STM32F407xx)\n  #include \"stm32f407xx.h\"\n#elif defined(STM32F417xx)\n  #include \"stm32f417xx.h\"\n#elif defined(STM32F427xx)\n  #include \"stm32f427xx.h\"\n#elif defined(STM32F437xx)\n  #include \"stm32f437xx.h\"\n#elif defined(STM32F429xx)\n  #include \"stm32f429xx.h\"\n#elif defined(STM32F439xx)\n  #include \"stm32f439xx.h\"\n#elif defined(STM32F401xC)\n  #include \"stm32f401xc.h\"\n#elif defined(STM32F401xE)\n  #include \"stm32f401xe.h\"\n#elif defined(STM32F410Tx)\n  #include \"stm32f410tx.h\"\n#elif defined(STM32F410Cx)\n  #include \"stm32f410cx.h\"\n#elif defined(STM32F410Rx)\n  #include \"stm32f410rx.h\"\n#elif defined(STM32F411xE)\n  #include \"stm32f411xe.h\"\n#elif defined(STM32F446xx)\n  #include \"stm32f446xx.h\"\n#elif defined(STM32F469xx)\n  #include \"stm32f469xx.h\"\n#elif defined(STM32F479xx)\n  #include \"stm32f479xx.h\"\n#elif defined(STM32F412Cx)\n  #include \"stm32f412cx.h\"\n#elif defined(STM32F412Zx)\n  #include \"stm32f412zx.h\"\n#elif defined(STM32F412Rx)\n  #include \"stm32f412rx.h\"\n#elif defined(STM32F412Vx)\n  #include \"stm32f412vx.h\"\n#elif defined(STM32F413xx)\n  #include \"stm32f413xx.h\"\n#elif defined(STM32F423xx)\n  #include \"stm32f423xx.h\"\n#else\n #error \"Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */ \ntypedef enum \n{\n  RESET = 0U, \n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum \n{\n  DISABLE = 0U, \n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum \n{\n  ERROR = 0U, \n  SUCCESS = !ERROR\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macro\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) \n\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32f4xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F4xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n  \n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f4xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       \n  ******************************************************************************  \n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************  \n  */ \n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx_system\n  * @{\n  */  \n  \n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32F4XX_H\n#define __SYSTEM_STM32F4XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/** @addtogroup STM32F4xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32F4xx_System_Exported_types\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\n\nextern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\nextern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Functions\n  * @{\n  */\n  \nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32F4XX_H */\n\n/**\n  * @}\n  */\n  \n/**\n  * @}\n  */  \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l496xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32L496xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - Peripheral's registers declarations and bits definition\n  *           - Macros to access peripherals registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32l496xx\n  * @{\n  */\n\n#ifndef __STM32L496xx_H\n#define __STM32L496xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals\n   */\n#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */\n#define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32L4XX Interrupt Number Definition, according to the selected device\n *        in @ref Library_configuration_section\n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */\n  HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */\n  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */\n  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */\n  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */\n  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */\n  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */\n  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */\n  ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */\n  TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */\n  TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */\n  TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */\n  TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */\n  TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\n  ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */\n  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\n  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */\n  DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */\n  DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */\n  DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */\n  DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */\n  DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */\n  DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */\n  DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */\n  COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */\n  LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */\n  LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */\n  DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */\n  LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */\n  QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */\n  SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */\n  SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */\n  TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */\n  LCD_IRQn                    = 78,     /*!< LCD global interrupt                                              */\n  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */\n  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\n  CRS_IRQn                    = 82,     /*!< CRS global interrupt                                              */\n  I2C4_EV_IRQn                = 83,     /*!< I2C4 Event interrupt                                              */\n  I2C4_ER_IRQn                = 84,     /*!< I2C4 Error interrupt                                              */\n  DCMI_IRQn                   = 85,     /*!< DCMI global interrupt                                             */\n  CAN2_TX_IRQn                = 86,     /*!< CAN2 TX interrupt                                                 */\n  CAN2_RX0_IRQn               = 87,     /*!< CAN2 RX0 interrupt                                                */\n  CAN2_RX1_IRQn               = 88,     /*!< CAN2 RX1 interrupt                                                */\n  CAN2_SCE_IRQn               = 89,     /*!< CAN2 SCE interrupt                                                */\n  DMA2D_IRQn                  = 90      /*!< DMA2D global interrupt                                            */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32l4xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */\n\n/**\n  * @brief Analog to Digital Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */\n  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */\n  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */\n  __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */\n  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */\n  __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */\n  __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */\n       uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */\n  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */\n  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */\n  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */\n       uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */\n  __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */\n  __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */\n  __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */\n  __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */\n  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */\n       uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */\n       uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */\n  __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */\n       uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */\n  __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */\n  __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */\n  __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */\n  __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */\n       uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */\n  __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */\n  __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */\n  __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */\n  __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */\n       uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */\n  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */\n  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */\n       uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */\n       uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */\n  __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */\n  __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */\n\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */\n  uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */\n  __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */\n} ADC_Common_TypeDef;\n\n/**\n  * @brief DCMI\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DCMI control register,                         Address offset: 0x00 */\n  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\n  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\n  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\n  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\n  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\n  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\n  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\n  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\n  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\n  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\n} DCMI_TypeDef;\n\n/**\n  * @brief Controller Area Network TxMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FIFOMailBox\n  */\n\ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/**\n  * @brief Controller Area Network FilterRegister\n  */\n\ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/**\n  * @brief Controller Area Network\n  */\n\ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */\n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n\n/**\n  * @brief Comparator\n  */\n\ntypedef struct\n{\n  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */\n} COMP_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */\n} COMP_Common_TypeDef;\n\n/**\n  * @brief CRC calculation unit\n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */\n  __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */\n  uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */\n  uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */\n  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */\n  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */\n  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */\n  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */\n} CRC_TypeDef;\n\n/**\n  * @brief Clock Recovery System\n  */\ntypedef struct\n{\n__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */\n__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */\n__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */\n__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */\n} CRS_TypeDef;\n\n/**\n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */\n  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */\n  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */\n  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */\n  __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */\n  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */\n  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */\n} DAC_TypeDef;\n\n/**\n  * @brief DFSDM module registers\n  */\ntypedef struct\n{\n  __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */\n  __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */\n  __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */\n  __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */\n  __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */\n  __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */\n  __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */\n  __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */\n  __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */\n  __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */\n  __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */\n  __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */\n  __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */\n  __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */\n  __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */\n} DFSDM_Filter_TypeDef;\n\n/**\n  * @brief DFSDM channel configuration registers\n  */\ntypedef struct\n{\n  __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */\n  __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */\n  __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and\n                                  short circuit detector register,                  Address offset: 0x08 */\n  __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */\n  __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */\n} DFSDM_Channel_TypeDef;\n\n/**\n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */\n  __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */\n  __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */\n  __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */\n  __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */\n} DBGMCU_TypeDef;\n\n\n/**\n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */\n  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */\n  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */\n  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */\n  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */\n} DMA_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSELR;       /*!< DMA channel selection register              */\n} DMA_Request_TypeDef;\n\n/* Legacy define */\n#define DMA_request_TypeDef  DMA_Request_TypeDef\n\n\n/**\n  * @brief DMA2D Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\n  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\n  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\n  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\n  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\n  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\n  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\n  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\n  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\n  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\n  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\n  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\n  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\n  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\n  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\n  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\n  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\n  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\n  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\n  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\n  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\n  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\n  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\n} DMA2D_TypeDef;\n\n/**\n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */\n  __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */\n  __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */\n  __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */\n  __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */\n  __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */\n  uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */\n  uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */\n  __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */\n  __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */\n  __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */\n  __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */\n  __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */\n  __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */\n} EXTI_TypeDef;\n\n\n/**\n  * @brief Firewall\n  */\n\ntypedef struct\n{\n  __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */\n  __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */\n  __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */\n  __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */\n  __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */\n  __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */\n  uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */\n  uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */\n  __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */\n} FIREWALL_TypeDef;\n\n\n/**\n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */\n  __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */\n  __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */\n  __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */\n  __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */\n  __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */\n  __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */\n  __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */\n  __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */\n  __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */\n  __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */\n  __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */\n  __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */\n       uint32_t RESERVED2[4];     /*!< Reserved2,                           Address offset: 0x34-0x40 */\n  __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */\n  __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */\n  __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */\n  __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */\n} FLASH_TypeDef;\n\n\n/**\n  * @brief Flexible Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\n} FMC_Bank1_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FMC_Bank1E_TypeDef;\n\n/**\n  * @brief Flexible Memory Controller Bank3\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */\n  __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */\n  __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */\n  __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\n  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */\n  __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */\n} FMC_Bank3_TypeDef;\n\n/**\n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */\n  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */\n\n} GPIO_TypeDef;\n\n\n/**\n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */\n  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */\n  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */\n  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */\n  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */\n  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */\n  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */\n  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */\n  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */\n  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */\n} I2C_TypeDef;\n\n/**\n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */\n  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */\n} IWDG_TypeDef;\n\n/**\n  * @brief LCD\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< LCD control register,              Address offset: 0x00 */\n  __IO uint32_t FCR;         /*!< LCD frame control register,        Address offset: 0x04 */\n  __IO uint32_t SR;          /*!< LCD status register,               Address offset: 0x08 */\n  __IO uint32_t CLR;         /*!< LCD clear register,                Address offset: 0x0C */\n  uint32_t RESERVED;         /*!< Reserved,                          Address offset: 0x10 */\n  __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */\n} LCD_TypeDef;\n\n/**\n  * @brief LPTIMER\n  */\ntypedef struct\n{\n  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */\n  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */\n  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */\n  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */\n  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */\n  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */\n  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */\n  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */\n  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */\n} LPTIM_TypeDef;\n\n/**\n  * @brief Operational Amplifier (OPAMP)\n  */\n\ntypedef struct\n{\n  __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */\n  __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */\n  __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */\n} OPAMP_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */\n} OPAMP_Common_TypeDef;\n\n/**\n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */\n  __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */\n  __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */\n  __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */\n  __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */\n  __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */\n  __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */\n  uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */\n  __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */\n  __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */\n  __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */\n  __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */\n  __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */\n  __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */\n  __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */\n  __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */\n  __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */\n  __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */\n  __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */\n  __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */\n  __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */\n  __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */\n  __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */\n  __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */\n  __IO uint32_t PUCRI; /*!< Pull_up control register of portI,   Address offset: 0x60 */\n  __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */\n} PWR_TypeDef;\n\n\n/**\n  * @brief QUAD Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */\n  __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */\n  __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */\n  __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */\n  __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */\n  __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */\n  __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */\n  __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */\n  __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */\n  __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */\n  __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */\n  __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */\n  __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n\n/**\n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */\n  __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */\n  __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */\n  __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */\n  __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */\n  __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */\n  __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */\n  __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */\n  __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */\n  uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */\n  __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */\n  __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */\n  __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */\n  uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */\n  __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */\n  __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */\n  __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */\n  uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */\n  __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */\n  __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */\n  __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */\n  uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */\n  __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */\n  __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */\n  __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */\n  uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */\n  __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */\n  __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */\n  __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */\n  uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */\n  __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */\n  __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */\n  __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */\n  uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */\n  __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */\n  uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */\n  __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */\n  __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */\n  __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */\n  __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */\n} RCC_TypeDef;\n\n/**\n  * @brief Real-Time Clock\n  */\ntypedef struct\n{\n  __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */\n  __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */\n  __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */\n  __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */\n  __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */\n  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */\n       uint32_t reserved;    /*!< Reserved  */\n  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */\n  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */\n  __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */\n  __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */\n  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */\n  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */\n  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */\n  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */\n  __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */\n  __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */\n  __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */\n  __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */\n  __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */\n  __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */\n  __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */\n  __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */\n  __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */\n  __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */\n  __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */\n  __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */\n  __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */\n  __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */\n  __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */\n  __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */\n  __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */\n  __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */\n  __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */\n  __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */\n  __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */\n  __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */\n  __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */\n  __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */\n  __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */\n  __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */\n  __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */\n  __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */\n  __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */\n  __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */\n  __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */\n  __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */\n  __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */\n  __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */\n  __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */\n} RTC_TypeDef;\n\n/**\n  * @brief Serial Audio Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */\n  __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */\n  __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */\n  __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */\n  __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\n  __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */\n  __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */\n  __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n\n/**\n  * @brief Secure digital input/output Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */\n  __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */\n  __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */\n  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */\n  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */\n  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */\n  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */\n  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */\n  __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */\n  __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */\n} SDMMC_TypeDef;\n\n\n/**\n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */\n  __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */\n  __IO uint32_t DR;          /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */\n  __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */\n  __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */\n  uint32_t  RESERVED1;       /*!< Reserved,                                            Address offset: 0x1C */\n  uint32_t  RESERVED2;       /*!< Reserved,                                            Address offset: 0x20 */\n} SPI_TypeDef;\n\n\n/**\n  * @brief Single Wire Protocol Master Interface SPWMI\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */\n  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */\n    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */\n  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */\n  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */\n  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */\n  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */\n  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */\n  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */\n  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */\n} SWPMI_TypeDef;\n\n\n/**\n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */\n  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */\n  __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */\n  __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */\n  __IO uint32_t SWPR2;       /*!< SYSCFG SRAM2 write protection register 2,          Address offset: 0x28      */\n} SYSCFG_TypeDef;\n\n\n/**\n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */\n  __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */\n  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */\n  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */\n  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */\n  __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */\n  __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */\n} TIM_TypeDef;\n\n\n/**\n  * @brief Touch Sensing Controller (TSC)\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */\n  __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */\n  __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */\n  __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */\n  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */\n  uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */\n  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */\n  uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */\n  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */\n  uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */\n  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */\n  uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */\n  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */\n  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */\n} TSC_TypeDef;\n\n/**\n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */\n  __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */\n  __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */\n  __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */\n  uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */\n  __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */\n  __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */\n  uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */\n  __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */\n  __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */\n  __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */\n  uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */\n  __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */\n  uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */\n} USART_TypeDef;\n\n/**\n  * @brief VREFBUF\n  */\n\ntypedef struct\n{\n  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */\n  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */\n} VREFBUF_TypeDef;\n\n/**\n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @brief RNG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n  * @brief USB_OTG_Core_register\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/\n  __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/\n  __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/\n  __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/\n  __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/\n  __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/\n  __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/\n  __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/\n  __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/\n  __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                      024h*/\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/\n  __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/\n  uint32_t Reserved30[2];             /* Reserved                                        030h*/\n  __IO uint32_t GCCFG;                /* General Purpose IO Register                     038h*/\n  __IO uint32_t CID;                  /* User ID Register                                03Ch*/\n  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                 040h*/\n  __IO uint32_t GHWCFG1;              /* User HW config1                                 044h*/\n  __IO uint32_t GHWCFG2;              /* User HW config2                                 048h*/\n  __IO uint32_t GHWCFG3;              /* User HW config3                                 04Ch*/\n  uint32_t  Reserved6;                /* Reserved                                        050h*/\n  __IO uint32_t GLPMCFG;              /* LPM Register                                    054h*/\n  __IO uint32_t GPWRDN;               /* Power Down Register                             058h*/\n  __IO uint32_t GDFIFOCFG;            /* DFIFO Software Config Register                  05Ch*/\n   __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/\n    uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/\n  __IO uint32_t HPTXFSIZ;             /* Host Periodic Tx FIFO Size Reg                  100h*/\n  __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */\n} USB_OTG_GlobalTypeDef;\n\n/**\n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DCFG;        /* dev Configuration Register   800h*/\n  __IO uint32_t DCTL;        /* dev Control Register         804h*/\n  __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/\n  uint32_t Reserved0C;       /* Reserved                     80Ch*/\n  __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/\n  __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/\n  __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/\n  __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/\n  uint32_t  Reserved20;      /* Reserved                     820h*/\n  uint32_t Reserved9;        /* Reserved                     824h*/\n  __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/\n  __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/\n  __IO uint32_t DTHRCTL;     /* dev thr                      830h*/\n  __IO uint32_t DIEPEMPMSK;  /* dev empty msk             834h*/\n  __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/\n  __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/\n  uint32_t Reserved40;       /* dedicated EP mask           840h*/\n  __IO uint32_t DINEP1MSK;   /* dedicated EP mask           844h*/\n  uint32_t  Reserved44[15];  /* Reserved                 844-87Ch*/\n  __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk            884h*/\n} USB_OTG_DeviceTypeDef;\n\n/**\n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct\n{\n  __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/\n  uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/\n  __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/\n  uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/\n  __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/\n  __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/\n  __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/\n  uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/\n} USB_OTG_INEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/\n  uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/\n  __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/\n  uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/\n  __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/\n  __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/\n  uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/\n} USB_OTG_OUTEndpointTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct\n{\n  __IO uint32_t HCFG;        /* Host Configuration Register    400h*/\n  __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/\n  __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/\n  uint32_t Reserved40C;      /* Reserved                       40Ch*/\n  __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/\n  __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/\n  __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/\n} USB_OTG_HostTypeDef;\n\n/**\n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;\n  __IO uint32_t HCSPLT;\n  __IO uint32_t HCINT;\n  __IO uint32_t HCINTMSK;\n  __IO uint32_t HCTSIZ;\n  __IO uint32_t HCDMA;\n  uint32_t Reserved[2];\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */\n#define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 256 KB) base address */\n#define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */\n#define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */\n#define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address */\n#define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */\n\n#define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC  control registers base address */\n#define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */\n#define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */\n#define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n#define SRAM1_SIZE_MAX        ((uint32_t)0x00040000U) /*!< maximum SRAM1 size (up to 256 KBytes) */\n#define SRAM2_SIZE            ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE        PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)\n\n#define FMC_BANK1             FMC_BASE\n#define FMC_BANK1_1           FMC_BANK1\n#define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U)\n#define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U)\n#define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U)\n#define FMC_BANK3             (FMC_BASE  + 0x20000000U)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)\n#define LCD_BASE              (APB1PERIPH_BASE + 0x2400U)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)\n#define CRS_BASE              (APB1PERIPH_BASE + 0x6000U)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)\n#define I2C4_BASE             (APB1PERIPH_BASE + 0x8400U)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)\n#define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)\n#define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)\n#define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)\n#define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810U)\n#define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)\n#define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)\n#define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)\n#define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)\n\n\n/*!< APB2 peripherals */\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)\n#define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)\n#define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)\n#define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)\n#define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)\n#define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400U)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)\n#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)\n#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)\n#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800U)\n#define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)\n#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)\n#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)\n#define SAI2_BASE             (APB2PERIPH_BASE + 0x5800U)\n#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)\n#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)\n#define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)\n#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00)\n#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20)\n#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40)\n#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60)\n#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80)\n#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0)\n#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0)\n#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0)\n#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100)\n#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180)\n#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200)\n#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280)\n\n/*!< AHB1 peripherals */\n#define DMA1_BASE             (AHB1PERIPH_BASE)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)\n#define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)\n#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)\n\n\n#define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)\n#define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)\n#define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)\n#define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)\n#define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)\n#define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)\n#define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)\n#define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)\n\n\n#define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)\n#define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)\n#define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)\n#define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)\n#define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)\n#define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)\n#define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)\n#define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)\n\n\n/*!< AHB2 peripherals */\n#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)\n#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)\n#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)\n#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)\n#define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)\n#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400U)\n#define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800U)\n#define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)\n#define GPIOI_BASE            (AHB2PERIPH_BASE + 0x2000U)\n\n#define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000U)\n\n#define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)\n#define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100U)\n#define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200U)\n#define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300U)\n\n#define DCMI_BASE             (AHB2PERIPH_BASE + 0x08050000U)\n\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)\n\n\n/*!< FMC Banks registers base  address */\n#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)\n#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)\n#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)\n\n/* Debug MCU registers base address */\n#define DBGMCU_BASE           ((uint32_t)0xE0042000U)\n\n/*!< USB registers base address */\n#define USB_OTG_FS_PERIPH_BASE               ((uint32_t)0x50000000U)\n\n#define USB_OTG_GLOBAL_BASE                  ((uint32_t)0x00000000U)\n#define USB_OTG_DEVICE_BASE                  ((uint32_t)0x00000800U)\n#define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t)0x00000900U)\n#define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t)0x00000B00U)\n#define USB_OTG_EP_REG_SIZE                  ((uint32_t)0x00000020U)\n#define USB_OTG_HOST_BASE                    ((uint32_t)0x00000400U)\n#define USB_OTG_HOST_PORT_BASE               ((uint32_t)0x00000440U)\n#define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t)0x00000500U)\n#define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t)0x00000020U)\n#define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)\n#define USB_OTG_FIFO_BASE                    ((uint32_t)0x00001000U)\n#define USB_OTG_FIFO_SIZE                    ((uint32_t)0x00001000U)\n\n\n#define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */\n#define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */\n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define LCD                 ((LCD_TypeDef *) LCD_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define CRS                 ((CRS_TypeDef *) CRS_BASE)\n#define CAN                 ((CAN_TypeDef *) CAN1_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define I2C4                ((I2C_TypeDef *) I2C4_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC1_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC1_BASE)\n#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)\n#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)\n#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)\n#define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)\n#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)\n#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)\n#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)\n#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)\n\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)\n#define COMP1               ((COMP_TypeDef *) COMP1_BASE)\n#define COMP2               ((COMP_TypeDef *) COMP2_BASE)\n#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)\n#define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define TIM15               ((TIM_TypeDef *) TIM15_BASE)\n#define TIM16               ((TIM_TypeDef *) TIM16_BASE)\n#define TIM17               ((TIM_TypeDef *) TIM17_BASE)\n#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define SAI2                ((SAI_TypeDef *) SAI2_BASE)\n#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\n#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\n#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)\n#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)\n#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)\n#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)\n#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)\n#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)\n#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)\n#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)\n#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)\n#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)\n#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)\n#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)\n/* Aliases to keep compatibility after DFSDM renaming */\n#define DFSDM_Channel0      DFSDM1_Channel0\n#define DFSDM_Channel1      DFSDM1_Channel1\n#define DFSDM_Channel2      DFSDM1_Channel2\n#define DFSDM_Channel3      DFSDM1_Channel3\n#define DFSDM_Channel4      DFSDM1_Channel4\n#define DFSDM_Channel5      DFSDM1_Channel5\n#define DFSDM_Channel6      DFSDM1_Channel6\n#define DFSDM_Channel7      DFSDM1_Channel7\n#define DFSDM_Filter0       DFSDM1_Filter0\n#define DFSDM_Filter1       DFSDM1_Filter1\n#define DFSDM_Filter2       DFSDM1_Filter2\n#define DFSDM_Filter3       DFSDM1_Filter3\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define TSC                 ((TSC_TypeDef *) TSC_BASE)\n\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\n#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\n#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n\n\n#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\n#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\n#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\n#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\n#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\n#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\n#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\n#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)\n\n\n#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\n#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\n#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\n#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\n#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\n#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)\n#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)\n#define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)\n\n\n#define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\n#define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\n#define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\n\n#define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)\n\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n/** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n\n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\n\n/********************  Bit definition for ADC_ISR register  *******************/\n#define ADC_ISR_ADRDY_Pos              (0U)\n#define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */\n#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */\n#define ADC_ISR_EOSMP_Pos              (1U)\n#define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */\n#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */\n#define ADC_ISR_EOC_Pos                (2U)\n#define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */\n#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */\n#define ADC_ISR_EOS_Pos                (3U)\n#define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */\n#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */\n#define ADC_ISR_OVR_Pos                (4U)\n#define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */\n#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */\n#define ADC_ISR_JEOC_Pos               (5U)\n#define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */\n#define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */\n#define ADC_ISR_JEOS_Pos               (6U)\n#define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */\n#define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */\n#define ADC_ISR_AWD1_Pos               (7U)\n#define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */\n#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */\n#define ADC_ISR_AWD2_Pos               (8U)\n#define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */\n#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */\n#define ADC_ISR_AWD3_Pos               (9U)\n#define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */\n#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */\n#define ADC_ISR_JQOVF_Pos              (10U)\n#define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */\n#define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */\n\n/********************  Bit definition for ADC_IER register  *******************/\n#define ADC_IER_ADRDYIE_Pos            (0U)\n#define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */\n#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */\n#define ADC_IER_EOSMPIE_Pos            (1U)\n#define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */\n#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */\n#define ADC_IER_EOCIE_Pos              (2U)\n#define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */\n#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */\n#define ADC_IER_EOSIE_Pos              (3U)\n#define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */\n#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */\n#define ADC_IER_OVRIE_Pos              (4U)\n#define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */\n#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */\n#define ADC_IER_JEOCIE_Pos             (5U)\n#define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */\n#define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */\n#define ADC_IER_JEOSIE_Pos             (6U)\n#define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */\n#define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */\n#define ADC_IER_AWD1IE_Pos             (7U)\n#define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */\n#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */\n#define ADC_IER_AWD2IE_Pos             (8U)\n#define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */\n#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */\n#define ADC_IER_AWD3IE_Pos             (9U)\n#define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */\n#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */\n#define ADC_IER_JQOVFIE_Pos            (10U)\n#define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */\n#define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */\n\n/* Legacy defines */\n#define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)\n#define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)\n#define ADC_IER_EOC             (ADC_IER_EOCIE)\n#define ADC_IER_EOS             (ADC_IER_EOSIE)\n#define ADC_IER_OVR             (ADC_IER_OVRIE)\n#define ADC_IER_JEOC            (ADC_IER_JEOCIE)\n#define ADC_IER_JEOS            (ADC_IER_JEOSIE)\n#define ADC_IER_AWD1            (ADC_IER_AWD1IE)\n#define ADC_IER_AWD2            (ADC_IER_AWD2IE)\n#define ADC_IER_AWD3            (ADC_IER_AWD3IE)\n#define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)\n\n/********************  Bit definition for ADC_CR register  ********************/\n#define ADC_CR_ADEN_Pos                (0U)\n#define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */\n#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */\n#define ADC_CR_ADDIS_Pos               (1U)\n#define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */\n#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */\n#define ADC_CR_ADSTART_Pos             (2U)\n#define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */\n#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */\n#define ADC_CR_JADSTART_Pos            (3U)\n#define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */\n#define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */\n#define ADC_CR_ADSTP_Pos               (4U)\n#define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */\n#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */\n#define ADC_CR_JADSTP_Pos              (5U)\n#define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */\n#define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */\n#define ADC_CR_ADVREGEN_Pos            (28U)\n#define ADC_CR_ADVREGEN_Msk            (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */\n#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */\n#define ADC_CR_DEEPPWD_Pos             (29U)\n#define ADC_CR_DEEPPWD_Msk             (0x1U << ADC_CR_DEEPPWD_Pos)            /*!< 0x20000000 */\n#define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */\n#define ADC_CR_ADCALDIF_Pos            (30U)\n#define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */\n#define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */\n#define ADC_CR_ADCAL_Pos               (31U)\n#define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */\n#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */\n\n/********************  Bit definition for ADC_CFGR register  ******************/\n#define ADC_CFGR_DMAEN_Pos             (0U)\n#define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */\n#define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */\n#define ADC_CFGR_DMACFG_Pos            (1U)\n#define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */\n#define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */\n\n#define ADC_CFGR_DFSDMCFG_Pos          (2U)\n#define ADC_CFGR_DFSDMCFG_Msk          (0x1U << ADC_CFGR_DFSDMCFG_Pos)         /*!< 0x00000004 */\n#define ADC_CFGR_DFSDMCFG              ADC_CFGR_DFSDMCFG_Msk                   /*!< ADC DFSDM mode configuration */\n\n#define ADC_CFGR_RES_Pos               (3U)\n#define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */\n#define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */\n#define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */\n#define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */\n\n#define ADC_CFGR_ALIGN_Pos             (5U)\n#define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */\n#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */\n\n#define ADC_CFGR_EXTSEL_Pos            (6U)\n#define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */\n#define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */\n#define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */\n#define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */\n#define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */\n#define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */\n\n#define ADC_CFGR_EXTEN_Pos             (10U)\n#define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */\n#define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */\n#define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */\n#define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */\n\n#define ADC_CFGR_OVRMOD_Pos            (12U)\n#define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */\n#define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */\n#define ADC_CFGR_CONT_Pos              (13U)\n#define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */\n#define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */\n#define ADC_CFGR_AUTDLY_Pos            (14U)\n#define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */\n#define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */\n\n#define ADC_CFGR_DISCEN_Pos            (16U)\n#define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */\n#define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */\n\n#define ADC_CFGR_DISCNUM_Pos           (17U)\n#define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */\n#define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */\n#define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */\n#define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */\n#define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */\n\n#define ADC_CFGR_JDISCEN_Pos           (20U)\n#define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */\n#define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */\n#define ADC_CFGR_JQM_Pos               (21U)\n#define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */\n#define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */\n#define ADC_CFGR_AWD1SGL_Pos           (22U)\n#define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */\n#define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\n#define ADC_CFGR_AWD1EN_Pos            (23U)\n#define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */\n#define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */\n#define ADC_CFGR_JAWD1EN_Pos           (24U)\n#define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */\n#define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */\n#define ADC_CFGR_JAUTO_Pos             (25U)\n#define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */\n#define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */\n\n#define ADC_CFGR_AWD1CH_Pos            (26U)\n#define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */\n#define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */\n#define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */\n#define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */\n#define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */\n#define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */\n#define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */\n\n#define ADC_CFGR_JQDIS_Pos             (31U)\n#define ADC_CFGR_JQDIS_Msk             (0x1U << ADC_CFGR_JQDIS_Pos)            /*!< 0x80000000 */\n#define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */\n\n/********************  Bit definition for ADC_CFGR2 register  *****************/\n#define ADC_CFGR2_ROVSE_Pos            (0U)\n#define ADC_CFGR2_ROVSE_Msk            (0x1U << ADC_CFGR2_ROVSE_Pos)           /*!< 0x00000001 */\n#define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */\n#define ADC_CFGR2_JOVSE_Pos            (1U)\n#define ADC_CFGR2_JOVSE_Msk            (0x1U << ADC_CFGR2_JOVSE_Pos)           /*!< 0x00000002 */\n#define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */\n\n#define ADC_CFGR2_OVSR_Pos             (2U)\n#define ADC_CFGR2_OVSR_Msk             (0x7U << ADC_CFGR2_OVSR_Pos)            /*!< 0x0000001C */\n#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */\n#define ADC_CFGR2_OVSR_0               (0x1U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000004 */\n#define ADC_CFGR2_OVSR_1               (0x2U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000008 */\n#define ADC_CFGR2_OVSR_2               (0x4U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000010 */\n\n#define ADC_CFGR2_OVSS_Pos             (5U)\n#define ADC_CFGR2_OVSS_Msk             (0xFU << ADC_CFGR2_OVSS_Pos)            /*!< 0x000001E0 */\n#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */\n#define ADC_CFGR2_OVSS_0               (0x1U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000020 */\n#define ADC_CFGR2_OVSS_1               (0x2U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000040 */\n#define ADC_CFGR2_OVSS_2               (0x4U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000080 */\n#define ADC_CFGR2_OVSS_3               (0x8U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000100 */\n\n#define ADC_CFGR2_TROVS_Pos            (9U)\n#define ADC_CFGR2_TROVS_Msk            (0x1U << ADC_CFGR2_TROVS_Pos)           /*!< 0x00000200 */\n#define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */\n#define ADC_CFGR2_ROVSM_Pos            (10U)\n#define ADC_CFGR2_ROVSM_Msk            (0x1U << ADC_CFGR2_ROVSM_Pos)           /*!< 0x00000400 */\n#define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */\n\n/********************  Bit definition for ADC_SMPR1 register  *****************/\n#define ADC_SMPR1_SMP0_Pos             (0U)\n#define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */\n#define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */\n#define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */\n#define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */\n#define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */\n\n#define ADC_SMPR1_SMP1_Pos             (3U)\n#define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */\n#define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */\n#define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */\n#define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */\n#define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */\n\n#define ADC_SMPR1_SMP2_Pos             (6U)\n#define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */\n#define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */\n#define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */\n#define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */\n\n#define ADC_SMPR1_SMP3_Pos             (9U)\n#define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */\n#define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */\n#define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */\n#define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */\n\n#define ADC_SMPR1_SMP4_Pos             (12U)\n#define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */\n#define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */\n#define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */\n#define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */\n#define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */\n\n#define ADC_SMPR1_SMP5_Pos             (15U)\n#define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */\n#define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */\n#define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */\n#define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */\n#define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */\n\n#define ADC_SMPR1_SMP6_Pos             (18U)\n#define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */\n#define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */\n#define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */\n#define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */\n\n#define ADC_SMPR1_SMP7_Pos             (21U)\n#define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */\n#define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */\n#define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */\n#define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */\n\n#define ADC_SMPR1_SMP8_Pos             (24U)\n#define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */\n#define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */\n#define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */\n#define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */\n#define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */\n\n#define ADC_SMPR1_SMP9_Pos             (27U)\n#define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */\n#define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */\n#define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */\n#define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */\n#define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */\n\n#define ADC_SMPR1_SMPPLUS_Pos          (31U)\n#define ADC_SMPR1_SMPPLUS_Msk          (0x1U << ADC_SMPR1_SMPPLUS_Pos)         /*!< 0x80000000 */\n#define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */\n\n/********************  Bit definition for ADC_SMPR2 register  *****************/\n#define ADC_SMPR2_SMP10_Pos            (0U)\n#define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */\n#define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */\n#define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */\n#define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */\n#define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */\n\n#define ADC_SMPR2_SMP11_Pos            (3U)\n#define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */\n#define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */\n#define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */\n#define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */\n#define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */\n\n#define ADC_SMPR2_SMP12_Pos            (6U)\n#define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */\n#define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */\n#define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */\n#define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */\n\n#define ADC_SMPR2_SMP13_Pos            (9U)\n#define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */\n#define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */\n#define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */\n#define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */\n\n#define ADC_SMPR2_SMP14_Pos            (12U)\n#define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */\n#define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */\n#define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */\n#define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */\n#define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */\n\n#define ADC_SMPR2_SMP15_Pos            (15U)\n#define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */\n#define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */\n#define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */\n#define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */\n#define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */\n\n#define ADC_SMPR2_SMP16_Pos            (18U)\n#define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */\n#define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */\n#define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */\n#define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */\n\n#define ADC_SMPR2_SMP17_Pos            (21U)\n#define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */\n#define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */\n#define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */\n#define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */\n\n#define ADC_SMPR2_SMP18_Pos            (24U)\n#define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */\n#define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */\n#define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */\n#define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */\n#define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */\n\n/********************  Bit definition for ADC_TR1 register  *******************/\n#define ADC_TR1_LT1_Pos                (0U)\n#define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */\n#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */\n#define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */\n#define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */\n#define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */\n#define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */\n#define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */\n#define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */\n#define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */\n#define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */\n#define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */\n#define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */\n#define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */\n#define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */\n\n#define ADC_TR1_HT1_Pos                (16U)\n#define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */\n#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */\n#define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */\n#define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */\n#define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */\n#define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */\n#define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */\n#define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */\n#define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */\n#define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */\n#define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */\n#define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */\n#define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */\n#define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */\n\n/********************  Bit definition for ADC_TR2 register  *******************/\n#define ADC_TR2_LT2_Pos                (0U)\n#define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */\n#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */\n#define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */\n#define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */\n#define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */\n#define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */\n#define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */\n#define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */\n#define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */\n#define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */\n\n#define ADC_TR2_HT2_Pos                (16U)\n#define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */\n#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */\n#define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */\n#define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */\n#define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */\n#define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */\n#define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */\n#define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */\n#define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */\n#define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */\n\n/********************  Bit definition for ADC_TR3 register  *******************/\n#define ADC_TR3_LT3_Pos                (0U)\n#define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */\n#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */\n#define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */\n#define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */\n#define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */\n#define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */\n#define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */\n#define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */\n#define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */\n#define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */\n\n#define ADC_TR3_HT3_Pos                (16U)\n#define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */\n#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */\n#define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */\n#define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */\n#define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */\n#define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */\n#define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */\n#define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */\n#define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */\n#define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */\n\n/********************  Bit definition for ADC_SQR1 register  ******************/\n#define ADC_SQR1_L_Pos                 (0U)\n#define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */\n#define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */\n#define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */\n#define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */\n#define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */\n#define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */\n\n#define ADC_SQR1_SQ1_Pos               (6U)\n#define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */\n#define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */\n#define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */\n#define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */\n#define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */\n#define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */\n#define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */\n\n#define ADC_SQR1_SQ2_Pos               (12U)\n#define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */\n#define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */\n#define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */\n#define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */\n#define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */\n#define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */\n#define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */\n\n#define ADC_SQR1_SQ3_Pos               (18U)\n#define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */\n#define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */\n#define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */\n#define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */\n#define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */\n#define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */\n#define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */\n\n#define ADC_SQR1_SQ4_Pos               (24U)\n#define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */\n#define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */\n#define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */\n#define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */\n#define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */\n#define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */\n#define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */\n\n/********************  Bit definition for ADC_SQR2 register  ******************/\n#define ADC_SQR2_SQ5_Pos               (0U)\n#define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */\n#define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */\n#define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */\n#define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */\n#define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */\n#define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */\n#define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */\n\n#define ADC_SQR2_SQ6_Pos               (6U)\n#define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */\n#define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */\n#define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */\n#define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */\n#define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */\n#define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */\n#define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */\n\n#define ADC_SQR2_SQ7_Pos               (12U)\n#define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */\n#define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */\n#define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */\n#define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */\n#define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */\n#define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */\n#define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */\n\n#define ADC_SQR2_SQ8_Pos               (18U)\n#define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */\n#define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */\n#define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */\n#define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */\n#define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */\n#define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */\n#define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */\n\n#define ADC_SQR2_SQ9_Pos               (24U)\n#define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */\n#define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */\n#define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */\n#define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */\n#define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */\n#define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */\n#define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */\n\n/********************  Bit definition for ADC_SQR3 register  ******************/\n#define ADC_SQR3_SQ10_Pos              (0U)\n#define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */\n#define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */\n#define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */\n#define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */\n#define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */\n#define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */\n#define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */\n\n#define ADC_SQR3_SQ11_Pos              (6U)\n#define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */\n#define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */\n#define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */\n#define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */\n#define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */\n#define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */\n#define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */\n\n#define ADC_SQR3_SQ12_Pos              (12U)\n#define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */\n#define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */\n#define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */\n#define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */\n#define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */\n#define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */\n#define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */\n\n#define ADC_SQR3_SQ13_Pos              (18U)\n#define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */\n#define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */\n#define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */\n#define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */\n#define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */\n#define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */\n#define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */\n\n#define ADC_SQR3_SQ14_Pos              (24U)\n#define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */\n#define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */\n#define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */\n#define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */\n#define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */\n#define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */\n#define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */\n\n/********************  Bit definition for ADC_SQR4 register  ******************/\n#define ADC_SQR4_SQ15_Pos              (0U)\n#define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */\n#define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */\n#define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */\n#define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */\n#define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */\n#define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */\n#define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */\n\n#define ADC_SQR4_SQ16_Pos              (6U)\n#define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */\n#define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */\n#define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */\n#define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */\n#define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */\n#define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */\n#define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_RDATA_Pos               (0U)\n#define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */\n#define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */\n#define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */\n#define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */\n#define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */\n#define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */\n#define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */\n#define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */\n#define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */\n#define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */\n#define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */\n#define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */\n#define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */\n#define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */\n#define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */\n#define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */\n#define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */\n#define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */\n\n/********************  Bit definition for ADC_JSQR register  ******************/\n#define ADC_JSQR_JL_Pos                (0U)\n#define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */\n#define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */\n#define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */\n#define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */\n\n#define ADC_JSQR_JEXTSEL_Pos           (2U)\n#define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */\n#define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */\n#define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */\n#define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */\n#define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */\n#define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */\n\n#define ADC_JSQR_JEXTEN_Pos            (6U)\n#define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */\n#define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */\n#define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */\n#define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */\n\n#define ADC_JSQR_JSQ1_Pos              (8U)\n#define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */\n#define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */\n#define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */\n#define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */\n#define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */\n#define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */\n#define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */\n\n#define ADC_JSQR_JSQ2_Pos              (14U)\n#define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */\n#define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */\n#define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */\n#define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */\n#define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */\n#define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */\n#define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */\n\n#define ADC_JSQR_JSQ3_Pos              (20U)\n#define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */\n#define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */\n#define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */\n#define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */\n#define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */\n#define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */\n#define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */\n\n#define ADC_JSQR_JSQ4_Pos              (26U)\n#define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */\n#define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */\n#define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */\n#define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */\n#define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */\n#define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */\n#define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */\n\n/********************  Bit definition for ADC_OFR1 register  ******************/\n#define ADC_OFR1_OFFSET1_Pos           (0U)\n#define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */\n#define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */\n#define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */\n#define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */\n#define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */\n#define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */\n#define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */\n#define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */\n#define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */\n#define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */\n#define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */\n#define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */\n#define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */\n#define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */\n\n#define ADC_OFR1_OFFSET1_CH_Pos        (26U)\n#define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */\n#define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */\n#define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */\n#define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */\n#define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */\n#define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */\n#define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */\n\n#define ADC_OFR1_OFFSET1_EN_Pos        (31U)\n#define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */\n#define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */\n\n/********************  Bit definition for ADC_OFR2 register  ******************/\n#define ADC_OFR2_OFFSET2_Pos           (0U)\n#define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */\n#define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */\n#define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */\n#define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */\n#define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */\n#define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */\n#define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */\n#define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */\n#define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */\n#define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */\n#define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */\n#define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */\n#define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */\n#define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */\n\n#define ADC_OFR2_OFFSET2_CH_Pos        (26U)\n#define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */\n#define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */\n#define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */\n#define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */\n#define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */\n#define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */\n#define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */\n\n#define ADC_OFR2_OFFSET2_EN_Pos        (31U)\n#define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */\n#define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */\n\n/********************  Bit definition for ADC_OFR3 register  ******************/\n#define ADC_OFR3_OFFSET3_Pos           (0U)\n#define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */\n#define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */\n#define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */\n#define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */\n#define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */\n#define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */\n#define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */\n#define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */\n#define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */\n#define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */\n#define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */\n#define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */\n#define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */\n#define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */\n\n#define ADC_OFR3_OFFSET3_CH_Pos        (26U)\n#define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */\n#define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */\n#define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */\n#define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */\n#define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */\n#define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */\n#define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */\n\n#define ADC_OFR3_OFFSET3_EN_Pos        (31U)\n#define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */\n#define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */\n\n/********************  Bit definition for ADC_OFR4 register  ******************/\n#define ADC_OFR4_OFFSET4_Pos           (0U)\n#define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */\n#define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */\n#define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */\n#define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */\n#define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */\n#define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */\n#define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */\n#define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */\n#define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */\n#define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */\n#define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */\n#define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */\n#define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */\n#define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */\n\n#define ADC_OFR4_OFFSET4_CH_Pos        (26U)\n#define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */\n#define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */\n#define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */\n#define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */\n#define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */\n#define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */\n#define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */\n\n#define ADC_OFR4_OFFSET4_EN_Pos        (31U)\n#define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */\n#define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */\n\n/********************  Bit definition for ADC_JDR1 register  ******************/\n#define ADC_JDR1_JDATA_Pos             (0U)\n#define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */\n#define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */\n#define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */\n#define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */\n#define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */\n#define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */\n#define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */\n#define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */\n#define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */\n#define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */\n#define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */\n#define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */\n#define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */\n#define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */\n#define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */\n#define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */\n#define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */\n\n/********************  Bit definition for ADC_JDR2 register  ******************/\n#define ADC_JDR2_JDATA_Pos             (0U)\n#define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */\n#define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */\n#define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */\n#define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */\n#define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */\n#define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */\n#define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */\n#define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */\n#define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */\n#define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */\n#define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */\n#define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */\n#define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */\n#define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */\n#define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */\n#define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */\n#define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */\n\n/********************  Bit definition for ADC_JDR3 register  ******************/\n#define ADC_JDR3_JDATA_Pos             (0U)\n#define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */\n#define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */\n#define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */\n#define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */\n#define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */\n#define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */\n#define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */\n#define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */\n#define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */\n#define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */\n#define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */\n#define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */\n#define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */\n#define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */\n#define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */\n#define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */\n#define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */\n\n/********************  Bit definition for ADC_JDR4 register  ******************/\n#define ADC_JDR4_JDATA_Pos             (0U)\n#define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */\n#define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */\n#define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */\n#define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */\n#define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */\n#define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */\n#define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */\n#define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */\n#define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */\n#define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */\n#define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */\n#define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */\n#define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */\n#define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */\n#define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */\n#define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */\n#define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */\n\n/********************  Bit definition for ADC_AWD2CR register  ****************/\n#define ADC_AWD2CR_AWD2CH_Pos          (0U)\n#define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */\n#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */\n#define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */\n#define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */\n#define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */\n#define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */\n#define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */\n#define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */\n#define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */\n#define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */\n#define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */\n#define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */\n#define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */\n#define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */\n#define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */\n#define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */\n#define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */\n#define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */\n#define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */\n#define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */\n#define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */\n\n/********************  Bit definition for ADC_AWD3CR register  ****************/\n#define ADC_AWD3CR_AWD3CH_Pos          (0U)\n#define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */\n#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */\n#define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */\n#define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */\n#define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */\n#define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */\n#define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */\n#define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */\n#define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */\n#define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */\n#define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */\n#define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */\n#define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */\n#define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */\n#define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */\n#define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */\n#define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */\n#define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */\n#define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */\n#define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */\n#define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */\n\n/********************  Bit definition for ADC_DIFSEL register  ****************/\n#define ADC_DIFSEL_DIFSEL_Pos          (0U)\n#define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */\n#define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */\n#define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */\n#define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */\n#define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */\n#define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */\n#define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */\n#define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */\n#define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */\n#define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */\n#define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */\n#define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */\n#define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */\n#define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */\n#define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */\n#define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */\n#define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */\n#define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */\n#define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */\n#define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */\n#define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */\n\n/********************  Bit definition for ADC_CALFACT register  ***************/\n#define ADC_CALFACT_CALFACT_S_Pos      (0U)\n#define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */\n#define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */\n#define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */\n#define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */\n#define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */\n#define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */\n#define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */\n#define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */\n#define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */\n\n#define ADC_CALFACT_CALFACT_D_Pos      (16U)\n#define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */\n#define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */\n#define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */\n#define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */\n#define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */\n#define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */\n#define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */\n#define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */\n#define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */\n\n/*************************  ADC Common registers  *****************************/\n/********************  Bit definition for ADC_CSR register  *******************/\n#define ADC_CSR_ADRDY_MST_Pos          (0U)\n#define ADC_CSR_ADRDY_MST_Msk          (0x1U << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */\n#define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */\n#define ADC_CSR_EOSMP_MST_Pos          (1U)\n#define ADC_CSR_EOSMP_MST_Msk          (0x1U << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */\n#define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */\n#define ADC_CSR_EOC_MST_Pos            (2U)\n#define ADC_CSR_EOC_MST_Msk            (0x1U << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */\n#define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */\n#define ADC_CSR_EOS_MST_Pos            (3U)\n#define ADC_CSR_EOS_MST_Msk            (0x1U << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */\n#define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */\n#define ADC_CSR_OVR_MST_Pos            (4U)\n#define ADC_CSR_OVR_MST_Msk            (0x1U << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */\n#define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */\n#define ADC_CSR_JEOC_MST_Pos           (5U)\n#define ADC_CSR_JEOC_MST_Msk           (0x1U << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */\n#define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */\n#define ADC_CSR_JEOS_MST_Pos           (6U)\n#define ADC_CSR_JEOS_MST_Msk           (0x1U << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */\n#define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */\n#define ADC_CSR_AWD1_MST_Pos           (7U)\n#define ADC_CSR_AWD1_MST_Msk           (0x1U << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */\n#define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */\n#define ADC_CSR_AWD2_MST_Pos           (8U)\n#define ADC_CSR_AWD2_MST_Msk           (0x1U << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */\n#define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */\n#define ADC_CSR_AWD3_MST_Pos           (9U)\n#define ADC_CSR_AWD3_MST_Msk           (0x1U << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */\n#define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */\n#define ADC_CSR_JQOVF_MST_Pos          (10U)\n#define ADC_CSR_JQOVF_MST_Msk          (0x1U << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */\n#define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */\n\n#define ADC_CSR_ADRDY_SLV_Pos          (16U)\n#define ADC_CSR_ADRDY_SLV_Msk          (0x1U << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */\n#define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */\n#define ADC_CSR_EOSMP_SLV_Pos          (17U)\n#define ADC_CSR_EOSMP_SLV_Msk          (0x1U << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */\n#define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */\n#define ADC_CSR_EOC_SLV_Pos            (18U)\n#define ADC_CSR_EOC_SLV_Msk            (0x1U << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */\n#define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */\n#define ADC_CSR_EOS_SLV_Pos            (19U)\n#define ADC_CSR_EOS_SLV_Msk            (0x1U << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */\n#define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */\n#define ADC_CSR_OVR_SLV_Pos            (20U)\n#define ADC_CSR_OVR_SLV_Msk            (0x1U << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */\n#define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */\n#define ADC_CSR_JEOC_SLV_Pos           (21U)\n#define ADC_CSR_JEOC_SLV_Msk           (0x1U << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */\n#define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */\n#define ADC_CSR_JEOS_SLV_Pos           (22U)\n#define ADC_CSR_JEOS_SLV_Msk           (0x1U << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */\n#define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */\n#define ADC_CSR_AWD1_SLV_Pos           (23U)\n#define ADC_CSR_AWD1_SLV_Msk           (0x1U << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */\n#define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */\n#define ADC_CSR_AWD2_SLV_Pos           (24U)\n#define ADC_CSR_AWD2_SLV_Msk           (0x1U << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */\n#define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */\n#define ADC_CSR_AWD3_SLV_Pos           (25U)\n#define ADC_CSR_AWD3_SLV_Msk           (0x1U << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */\n#define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */\n#define ADC_CSR_JQOVF_SLV_Pos          (26U)\n#define ADC_CSR_JQOVF_SLV_Msk          (0x1U << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */\n#define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */\n\n/********************  Bit definition for ADC_CCR register  *******************/\n#define ADC_CCR_DUAL_Pos               (0U)\n#define ADC_CCR_DUAL_Msk               (0x1FU << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */\n#define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */\n#define ADC_CCR_DUAL_0                 (0x01U << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */\n#define ADC_CCR_DUAL_1                 (0x02U << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */\n#define ADC_CCR_DUAL_2                 (0x04U << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */\n#define ADC_CCR_DUAL_3                 (0x08U << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */\n#define ADC_CCR_DUAL_4                 (0x10U << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */\n\n#define ADC_CCR_DELAY_Pos              (8U)\n#define ADC_CCR_DELAY_Msk              (0xFU << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */\n#define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */\n#define ADC_CCR_DELAY_0                (0x1U << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1                (0x2U << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2                (0x4U << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3                (0x8U << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */\n\n#define ADC_CCR_DMACFG_Pos             (13U)\n#define ADC_CCR_DMACFG_Msk             (0x1U << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */\n#define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */\n\n#define ADC_CCR_MDMA_Pos               (14U)\n#define ADC_CCR_MDMA_Msk               (0x3U << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */\n#define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */\n#define ADC_CCR_MDMA_0                 (0x1U << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */\n#define ADC_CCR_MDMA_1                 (0x2U << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */\n\n#define ADC_CCR_CKMODE_Pos             (16U)\n#define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */\n#define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */\n#define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */\n#define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */\n\n#define ADC_CCR_PRESC_Pos              (18U)\n#define ADC_CCR_PRESC_Msk              (0xFU << ADC_CCR_PRESC_Pos)             /*!< 0x003C0000 */\n#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */\n#define ADC_CCR_PRESC_0                (0x1U << ADC_CCR_PRESC_Pos)             /*!< 0x00040000 */\n#define ADC_CCR_PRESC_1                (0x2U << ADC_CCR_PRESC_Pos)             /*!< 0x00080000 */\n#define ADC_CCR_PRESC_2                (0x4U << ADC_CCR_PRESC_Pos)             /*!< 0x00100000 */\n#define ADC_CCR_PRESC_3                (0x8U << ADC_CCR_PRESC_Pos)             /*!< 0x00200000 */\n\n#define ADC_CCR_VREFEN_Pos             (22U)\n#define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */\n#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */\n#define ADC_CCR_TSEN_Pos               (23U)\n#define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */\n#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */\n#define ADC_CCR_VBATEN_Pos             (24U)\n#define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */\n#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */\n\n/********************  Bit definition for ADC_CDR register  *******************/\n#define ADC_CDR_RDATA_MST_Pos          (0U)\n#define ADC_CDR_RDATA_MST_Msk          (0xFFFFU << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */\n#define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */\n#define ADC_CDR_RDATA_MST_0            (0x0001U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */\n#define ADC_CDR_RDATA_MST_1            (0x0002U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */\n#define ADC_CDR_RDATA_MST_2            (0x0004U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */\n#define ADC_CDR_RDATA_MST_3            (0x0008U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */\n#define ADC_CDR_RDATA_MST_4            (0x0010U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */\n#define ADC_CDR_RDATA_MST_5            (0x0020U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */\n#define ADC_CDR_RDATA_MST_6            (0x0040U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */\n#define ADC_CDR_RDATA_MST_7            (0x0080U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */\n#define ADC_CDR_RDATA_MST_8            (0x0100U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */\n#define ADC_CDR_RDATA_MST_9            (0x0200U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */\n#define ADC_CDR_RDATA_MST_10           (0x0400U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */\n#define ADC_CDR_RDATA_MST_11           (0x0800U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */\n#define ADC_CDR_RDATA_MST_12           (0x1000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */\n#define ADC_CDR_RDATA_MST_13           (0x2000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */\n#define ADC_CDR_RDATA_MST_14           (0x4000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */\n#define ADC_CDR_RDATA_MST_15           (0x8000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */\n\n#define ADC_CDR_RDATA_SLV_Pos          (16U)\n#define ADC_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */\n#define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */\n#define ADC_CDR_RDATA_SLV_0            (0x0001U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */\n#define ADC_CDR_RDATA_SLV_1            (0x0002U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */\n#define ADC_CDR_RDATA_SLV_2            (0x0004U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */\n#define ADC_CDR_RDATA_SLV_3            (0x0008U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */\n#define ADC_CDR_RDATA_SLV_4            (0x0010U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */\n#define ADC_CDR_RDATA_SLV_5            (0x0020U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */\n#define ADC_CDR_RDATA_SLV_6            (0x0040U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */\n#define ADC_CDR_RDATA_SLV_7            (0x0080U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */\n#define ADC_CDR_RDATA_SLV_8            (0x0100U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */\n#define ADC_CDR_RDATA_SLV_9            (0x0200U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */\n#define ADC_CDR_RDATA_SLV_10           (0x0400U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */\n#define ADC_CDR_RDATA_SLV_11           (0x0800U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */\n#define ADC_CDR_RDATA_SLV_12           (0x1000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */\n#define ADC_CDR_RDATA_SLV_13           (0x2000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */\n#define ADC_CDR_RDATA_SLV_14           (0x4000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */\n#define ADC_CDR_RDATA_SLV_15           (0x8000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)\n#define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)\n#define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)\n#define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)\n#define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)\n#define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)\n#define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)\n#define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)\n#define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)\n#define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)\n#define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)\n#define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)\n#define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)\n#define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)\n#define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)\n#define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)\n#define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)\n#define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)\n#define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)\n#define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)\n#define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)\n#define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)\n#define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)\n#define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)\n#define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)\n#define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)\n#define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)\n#define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)\n#define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)\n#define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)\n#define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)\n#define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)\n#define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)\n#define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)\n#define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)\n#define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)\n#define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)\n#define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)\n#define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)\n#define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)\n#define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)\n#define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)\n#define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)\n#define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)\n#define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)\n#define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)\n#define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)\n#define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)\n#define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)\n#define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)\n#define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)\n#define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)\n#define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)\n#define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)\n#define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)\n#define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)\n#define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)\n#define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)\n#define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)\n#define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)\n#define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)\n#define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)\n#define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)\n#define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)\n#define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)\n#define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)\n#define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)\n#define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)\n#define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)\n#define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)\n#define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)\n#define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)\n#define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)\n#define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)\n#define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)\n#define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)\n#define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)\n#define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)\n#define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)\n#define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)\n#define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)\n#define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)\n#define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)\n#define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)\n#define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)\n#define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)\n#define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)\n#define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)\n#define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)\n#define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)\n#define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)\n#define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)\n#define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)\n#define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)\n#define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)\n#define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)\n#define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)\n#define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)\n#define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)\n#define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)\n#define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)\n#define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)\n#define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)\n#define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)\n#define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)\n#define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)\n#define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)\n#define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)\n#define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)\n#define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)\n#define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)\n#define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)\n#define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)\n#define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/\n#define CAN_TDT2R_DLC_Pos      (0U)\n#define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)\n#define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)\n#define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)\n#define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)\n#define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)\n#define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)\n#define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)\n#define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)\n#define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)\n#define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)\n#define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)\n#define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)\n#define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)\n#define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)\n#define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)\n#define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)\n#define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)\n#define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)\n#define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)\n#define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)\n#define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)\n#define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)\n#define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)\n#define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)\n#define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)\n#define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)\n#define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)\n#define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)\n#define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)\n#define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)\n#define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)\n#define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)\n#define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)\n#define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)\n#define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)\n#define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)\n#define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)\n#define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)\n#define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)\n#define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)\n#define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)\n#define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)\n#define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank  */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)\n#define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)\n#define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)\n#define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)\n#define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)\n#define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)\n#define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)\n#define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)\n#define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)\n#define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)\n#define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)\n#define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)\n#define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)\n#define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)\n#define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)\n#define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)\n#define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)\n#define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)\n#define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)\n#define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)\n#define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)\n#define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)\n#define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)\n#define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)\n#define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)\n#define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)\n#define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)\n#define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)\n#define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)\n#define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)\n#define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)\n#define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)\n#define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)\n#define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)\n#define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)\n#define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)\n#define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)\n#define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)\n#define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)\n#define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)\n#define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)\n#define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)\n#define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)\n#define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)\n#define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)\n#define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)\n#define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)\n#define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */\n#define CAN_FA1R_FACT1_Pos     (1U)\n#define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */\n#define CAN_FA1R_FACT2_Pos     (2U)\n#define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */\n#define CAN_FA1R_FACT3_Pos     (3U)\n#define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */\n#define CAN_FA1R_FACT4_Pos     (4U)\n#define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */\n#define CAN_FA1R_FACT5_Pos     (5U)\n#define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */\n#define CAN_FA1R_FACT6_Pos     (6U)\n#define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */\n#define CAN_FA1R_FACT7_Pos     (7U)\n#define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */\n#define CAN_FA1R_FACT8_Pos     (8U)\n#define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */\n#define CAN_FA1R_FACT9_Pos     (9U)\n#define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */\n#define CAN_FA1R_FACT10_Pos    (10U)\n#define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */\n#define CAN_FA1R_FACT11_Pos    (11U)\n#define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */\n#define CAN_FA1R_FACT12_Pos    (12U)\n#define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */\n#define CAN_FA1R_FACT13_Pos    (13U)\n#define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)\n#define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)\n#define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)\n#define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)\n#define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)\n#define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)\n#define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)\n#define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)\n#define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)\n#define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)\n#define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)\n#define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)\n#define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)\n#define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)\n#define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)\n#define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)\n#define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)\n#define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)\n#define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)\n#define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)\n#define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)\n#define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)\n#define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)\n#define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)\n#define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)\n#define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)\n#define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)\n#define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)\n#define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)\n#define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)\n#define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)\n#define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)\n#define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)\n#define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)\n#define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)\n#define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)\n#define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)\n#define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)\n#define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)\n#define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)\n#define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)\n#define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)\n#define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)\n#define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)\n#define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)\n#define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)\n#define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)\n#define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)\n#define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)\n#define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)\n#define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)\n#define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)\n#define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)\n#define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)\n#define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)\n#define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)\n#define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)\n#define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)\n#define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)\n#define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)\n#define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)\n#define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)\n#define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)\n#define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)\n#define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)\n#define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)\n#define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)\n#define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)\n#define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)\n#define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)\n#define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)\n#define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)\n#define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)\n#define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)\n#define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)\n#define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)\n#define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)\n#define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)\n#define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)\n#define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)\n#define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)\n#define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)\n#define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)\n#define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)\n#define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)\n#define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)\n#define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)\n#define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)\n#define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)\n#define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)\n#define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)\n#define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)\n#define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)\n#define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)\n#define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)\n#define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)\n#define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)\n#define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)\n#define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)\n#define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)\n#define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)\n#define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)\n#define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)\n#define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)\n#define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)\n#define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)\n#define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)\n#define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)\n#define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)\n#define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)\n#define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)\n#define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)\n#define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)\n#define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)\n#define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)\n#define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)\n#define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)\n#define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)\n#define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)\n#define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)\n#define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)\n#define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)\n#define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)\n#define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)\n#define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)\n#define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)\n#define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)\n#define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)\n#define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)\n#define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)\n#define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)\n#define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)\n#define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)\n#define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)\n#define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)\n#define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)\n#define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)\n#define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)\n#define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)\n#define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)\n#define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)\n#define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)\n#define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)\n#define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)\n#define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)\n#define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)\n#define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)\n#define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)\n#define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)\n#define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)\n#define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)\n#define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)\n#define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)\n#define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)\n#define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)\n#define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)\n#define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)\n#define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)\n#define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)\n#define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)\n#define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)\n#define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)\n#define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)\n#define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)\n#define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)\n#define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)\n#define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)\n#define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)\n#define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)\n#define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)\n#define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)\n#define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)\n#define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)\n#define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)\n#define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)\n#define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)\n#define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)\n#define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)\n#define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)\n#define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)\n#define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)\n#define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)\n#define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)\n#define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)\n#define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)\n#define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)\n#define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)\n#define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)\n#define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)\n#define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)\n#define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)\n#define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)\n#define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)\n#define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)\n#define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)\n#define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)\n#define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)\n#define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)\n#define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)\n#define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)\n#define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)\n#define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)\n#define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)\n#define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)\n#define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)\n#define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)\n#define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)\n#define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)\n#define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)\n#define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)\n#define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)\n#define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)\n#define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)\n#define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)\n#define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)\n#define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)\n#define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)\n#define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)\n#define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)\n#define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)\n#define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)\n#define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)\n#define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)\n#define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)\n#define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)\n#define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)\n#define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)\n#define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)\n#define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)\n#define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)\n#define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)\n#define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)\n#define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)\n#define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)\n#define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)\n#define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)\n#define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)\n#define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)\n#define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)\n#define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)\n#define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)\n#define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)\n#define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)\n#define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)\n#define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)\n#define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)\n#define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)\n#define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)\n#define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)\n#define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)\n#define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)\n#define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)\n#define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)\n#define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)\n#define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)\n#define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)\n#define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)\n#define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)\n#define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)\n#define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)\n#define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)\n#define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)\n#define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)\n#define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)\n#define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)\n#define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)\n#define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)\n#define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)\n#define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)\n#define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)\n#define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)\n#define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)\n#define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)\n#define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)\n#define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)\n#define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)\n#define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)\n#define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)\n#define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)\n#define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)\n#define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)\n#define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)\n#define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)\n#define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)\n#define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)\n#define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)\n#define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)\n#define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)\n#define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)\n#define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)\n#define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)\n#define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)\n#define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)\n#define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)\n#define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)\n#define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)\n#define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)\n#define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)\n#define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)\n#define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)\n#define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)\n#define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)\n#define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)\n#define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)\n#define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)\n#define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)\n#define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)\n#define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)\n#define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)\n#define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)\n#define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)\n#define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)\n#define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)\n#define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)\n#define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)\n#define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)\n#define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)\n#define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)\n#define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)\n#define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)\n#define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)\n#define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)\n#define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)\n#define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)\n#define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)\n#define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)\n#define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)\n#define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)\n#define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)\n#define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)\n#define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)\n#define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)\n#define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)\n#define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)\n#define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)\n#define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)\n#define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)\n#define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)\n#define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)\n#define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)\n#define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)\n#define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)\n#define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)\n#define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)\n#define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)\n#define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)\n#define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)\n#define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)\n#define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)\n#define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)\n#define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)\n#define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)\n#define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)\n#define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)\n#define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)\n#define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)\n#define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)\n#define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)\n#define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)\n#define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)\n#define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)\n#define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)\n#define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)\n#define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)\n#define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)\n#define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)\n#define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)\n#define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)\n#define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)\n#define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)\n#define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)\n#define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)\n#define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)\n#define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)\n#define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)\n#define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)\n#define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)\n#define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)\n#define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)\n#define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)\n#define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)\n#define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)\n#define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)\n#define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)\n#define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)\n#define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)\n#define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)\n#define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)\n#define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)\n#define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)\n#define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)\n#define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)\n#define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)\n#define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)\n#define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)\n#define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)\n#define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)\n#define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)\n#define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)\n#define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)\n#define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)\n#define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)\n#define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)\n#define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)\n#define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)\n#define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)\n#define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)\n#define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)\n#define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)\n#define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)\n#define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)\n#define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)\n#define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)\n#define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)\n#define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)\n#define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)\n#define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)\n#define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)\n#define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)\n#define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)\n#define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)\n#define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)\n#define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)\n#define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)\n#define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)\n#define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)\n#define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)\n#define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)\n#define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)\n#define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)\n#define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)\n#define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)\n#define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)\n#define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)\n#define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)\n#define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)\n#define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)\n#define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)\n#define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)\n#define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)\n#define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)\n#define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)\n#define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)\n#define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)\n#define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)\n#define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)\n#define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)\n#define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)\n#define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)\n#define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)\n#define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)\n#define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)\n#define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)\n#define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)\n#define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)\n#define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)\n#define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)\n#define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)\n#define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)\n#define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)\n#define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)\n#define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)\n#define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)\n#define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)\n#define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)\n#define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)\n#define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)\n#define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)\n#define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)\n#define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)\n#define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)\n#define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)\n#define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)\n#define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)\n#define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)\n#define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)\n#define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)\n#define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)\n#define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)\n#define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)\n#define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)\n#define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)\n#define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)\n#define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)\n#define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)\n#define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)\n#define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)\n#define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)\n#define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)\n#define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)\n#define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)\n#define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)\n#define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)\n#define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)\n#define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)\n#define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)\n#define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)\n#define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)\n#define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)\n#define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)\n#define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)\n#define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)\n#define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)\n#define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)\n#define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)\n#define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)\n#define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)\n#define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)\n#define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)\n#define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)\n#define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)\n#define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)\n#define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)\n#define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)\n#define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)\n#define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)\n#define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)\n#define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)\n#define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)\n#define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)\n#define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)\n#define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)\n#define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)\n#define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)\n#define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)\n#define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)\n#define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)\n#define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)\n#define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)\n#define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)\n#define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)\n#define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)\n#define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)\n#define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)\n#define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)\n#define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)\n#define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)\n#define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)\n#define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)\n#define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)\n#define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)\n#define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)\n#define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)\n#define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)\n#define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)\n#define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)\n#define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)\n#define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)\n#define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)\n#define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)\n#define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)\n#define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)\n#define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)\n#define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)\n#define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)\n#define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)\n#define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)\n#define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)\n#define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)\n#define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)\n#define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)\n#define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)\n#define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)\n#define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)\n#define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)\n#define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)\n#define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)\n#define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)\n#define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)\n#define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)\n#define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)\n#define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)\n#define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)\n#define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)\n#define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)\n#define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)\n#define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)\n#define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)\n#define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)\n#define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)\n#define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)\n#define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)\n#define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)\n#define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)\n#define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)\n#define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)\n#define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)\n#define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)\n#define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)\n#define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)\n#define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)\n#define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)\n#define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)\n#define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)\n#define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)\n#define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)\n#define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)\n#define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)\n#define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)\n#define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)\n#define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)\n#define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)\n#define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)\n#define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)\n#define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)\n#define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)\n#define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)\n#define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)\n#define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)\n#define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)\n#define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)\n#define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)\n#define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)\n#define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)\n#define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)\n#define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)\n#define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)\n#define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)\n#define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)\n#define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)\n#define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)\n#define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)\n#define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)\n#define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)\n#define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)\n#define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)\n#define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)\n#define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)\n#define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)\n#define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)\n#define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)\n#define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)\n#define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)\n#define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)\n#define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)\n#define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)\n#define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)\n#define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)\n#define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)\n#define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)\n#define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)\n#define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)\n#define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)\n#define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)\n#define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)\n#define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)\n#define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)\n#define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)\n#define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)\n#define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)\n#define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)\n#define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)\n#define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)\n#define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)\n#define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)\n#define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)\n#define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)\n#define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)\n#define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)\n#define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)\n#define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)\n#define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)\n#define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)\n#define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)\n#define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)\n#define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)\n#define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)\n#define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)\n#define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)\n#define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)\n#define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)\n#define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)\n#define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)\n#define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)\n#define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)\n#define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)\n#define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)\n#define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)\n#define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)\n#define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)\n#define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)\n#define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)\n#define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)\n#define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)\n#define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)\n#define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)\n#define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)\n#define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)\n#define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)\n#define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)\n#define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)\n#define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)\n#define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)\n#define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)\n#define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)\n#define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)\n#define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)\n#define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)\n#define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)\n#define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)\n#define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)\n#define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)\n#define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)\n#define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)\n#define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)\n#define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)\n#define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)\n#define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)\n#define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)\n#define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)\n#define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)\n#define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)\n#define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)\n#define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)\n#define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)\n#define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)\n#define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)\n#define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)\n#define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)\n#define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)\n#define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)\n#define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)\n#define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)\n#define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)\n#define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)\n#define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)\n#define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)\n#define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)\n#define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)\n#define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)\n#define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)\n#define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)\n#define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)\n#define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)\n#define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)\n#define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)\n#define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)\n#define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)\n#define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)\n#define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)\n#define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)\n#define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)\n#define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)\n#define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)\n#define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)\n#define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)\n#define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)\n#define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)\n#define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)\n#define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)\n#define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)\n#define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)\n#define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)\n#define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)\n#define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)\n#define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)\n#define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)\n#define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)\n#define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)\n#define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)\n#define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)\n#define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)\n#define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)\n#define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)\n#define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)\n#define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)\n#define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)\n#define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)\n#define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)\n#define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)\n#define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)\n#define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)\n#define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)\n#define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)\n#define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)\n#define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)\n#define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)\n#define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)\n#define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)\n#define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)\n#define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)\n#define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)\n#define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)\n#define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)\n#define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)\n#define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)\n#define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)\n#define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)\n#define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)\n#define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)\n#define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)\n#define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)\n#define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)\n#define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)\n#define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)\n#define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)\n#define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)\n#define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)\n#define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)\n#define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)\n#define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)\n#define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)\n#define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)\n#define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)\n#define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)\n#define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)\n#define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)\n#define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)\n#define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)\n#define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)\n#define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)\n#define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)\n#define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)\n#define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)\n#define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)\n#define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)\n#define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)\n#define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)\n#define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)\n#define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)\n#define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)\n#define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)\n#define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)\n#define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)\n#define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)\n#define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)\n#define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)\n#define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)\n#define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)\n#define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)\n#define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)\n#define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)\n#define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)\n#define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)\n#define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)\n#define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)\n#define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)\n#define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)\n#define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)\n#define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)\n#define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)\n#define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)\n#define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)\n#define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)\n#define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)\n#define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)\n#define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)\n#define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)\n#define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)\n#define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)\n#define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)\n#define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)\n#define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)\n#define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)\n#define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)\n#define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)\n#define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)\n#define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)\n#define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)\n#define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)\n#define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)\n#define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)\n#define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)\n#define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)\n#define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)\n#define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)\n#define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)\n#define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)\n#define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)\n#define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)\n#define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)\n#define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)\n#define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)\n#define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)\n#define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)\n#define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)\n#define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)\n#define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)\n#define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)\n#define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)\n#define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)\n#define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)\n#define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)\n#define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)\n#define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)\n#define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)\n#define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)\n#define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)\n#define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)\n#define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)\n#define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)\n#define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)\n#define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)\n#define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)\n#define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)\n#define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)\n#define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos            (0U)\n#define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */\n#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos          (0U)\n#define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */\n#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos         (0U)\n#define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */\n#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */\n#define CRC_CR_POLYSIZE_Pos      (3U)\n#define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */\n#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */\n#define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */\n#define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */\n#define CRC_CR_REV_IN_Pos        (5U)\n#define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */\n#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */\n#define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */\n#define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */\n#define CRC_CR_REV_OUT_Pos       (7U)\n#define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */\n#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */\n\n/*******************  Bit definition for CRC_INIT register  *******************/\n#define CRC_INIT_INIT_Pos        (0U)\n#define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */\n#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */\n\n/*******************  Bit definition for CRC_POL register  ********************/\n#define CRC_POL_POL_Pos          (0U)\n#define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */\n#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRS Clock Recovery System                         */\n/******************************************************************************/\n\n/*******************  Bit definition for CRS_CR register  *********************/\n#define CRS_CR_SYNCOKIE_Pos       (0U)\n#define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */\n#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */\n#define CRS_CR_SYNCWARNIE_Pos     (1U)\n#define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */\n#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */\n#define CRS_CR_ERRIE_Pos          (2U)\n#define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */\n#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */\n#define CRS_CR_ESYNCIE_Pos        (3U)\n#define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */\n#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */\n#define CRS_CR_CEN_Pos            (5U)\n#define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */\n#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */\n#define CRS_CR_AUTOTRIMEN_Pos     (6U)\n#define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */\n#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */\n#define CRS_CR_SWSYNC_Pos         (7U)\n#define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */\n#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */\n#define CRS_CR_TRIM_Pos           (8U)\n#define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */\n#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */\n\n/*******************  Bit definition for CRS_CFGR register  *********************/\n#define CRS_CFGR_RELOAD_Pos       (0U)\n#define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */\n#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */\n#define CRS_CFGR_FELIM_Pos        (16U)\n#define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */\n#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */\n\n#define CRS_CFGR_SYNCDIV_Pos      (24U)\n#define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */\n#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */\n#define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */\n#define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */\n#define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */\n\n#define CRS_CFGR_SYNCSRC_Pos      (28U)\n#define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */\n#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */\n#define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */\n#define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */\n\n#define CRS_CFGR_SYNCPOL_Pos      (31U)\n#define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */\n#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */\n\n/*******************  Bit definition for CRS_ISR register  *********************/\n#define CRS_ISR_SYNCOKF_Pos       (0U)\n#define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */\n#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */\n#define CRS_ISR_SYNCWARNF_Pos     (1U)\n#define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */\n#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */\n#define CRS_ISR_ERRF_Pos          (2U)\n#define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */\n#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */\n#define CRS_ISR_ESYNCF_Pos        (3U)\n#define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */\n#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */\n#define CRS_ISR_SYNCERR_Pos       (8U)\n#define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */\n#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */\n#define CRS_ISR_SYNCMISS_Pos      (9U)\n#define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */\n#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */\n#define CRS_ISR_TRIMOVF_Pos       (10U)\n#define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */\n#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */\n#define CRS_ISR_FEDIR_Pos         (15U)\n#define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */\n#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */\n#define CRS_ISR_FECAP_Pos         (16U)\n#define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */\n#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */\n\n/*******************  Bit definition for CRS_ICR register  *********************/\n#define CRS_ICR_SYNCOKC_Pos       (0U)\n#define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */\n#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */\n#define CRS_ICR_SYNCWARNC_Pos     (1U)\n#define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */\n#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */\n#define CRS_ICR_ERRC_Pos          (2U)\n#define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */\n#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */\n#define CRS_ICR_ESYNCC_Pos        (3U)\n#define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */\n#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */\n\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)\n#define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_TEN1_Pos             (2U)\n#define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)\n#define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)\n#define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)\n#define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)\n#define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)\n#define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/\n#define DAC_CR_CEN1_Pos             (14U)\n#define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */\n#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/\n\n#define DAC_CR_EN2_Pos              (16U)\n#define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_TEN2_Pos             (18U)\n#define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)\n#define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)\n#define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)\n#define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)\n#define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)\n#define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/\n#define DAC_CR_CEN2_Pos             (30U)\n#define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */\n#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)\n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)\n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)\n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)\n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)\n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)\n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)\n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)\n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)\n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)\n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)\n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)\n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)\n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)\n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)\n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)\n#define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_CAL_FLAG1_Pos        (14U)\n#define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */\n#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */\n#define DAC_SR_BWST1_Pos            (15U)\n#define DAC_SR_BWST1_Msk            (0x1U << DAC_SR_BWST1_Pos)                 /*!< 0x00008000 */\n#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */\n\n#define DAC_SR_DMAUDR2_Pos          (29U)\n#define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n#define DAC_SR_CAL_FLAG2_Pos        (30U)\n#define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */\n#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */\n#define DAC_SR_BWST2_Pos            (31U)\n#define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */\n#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */\n\n/*******************  Bit definition for DAC_CCR register  ********************/\n#define DAC_CCR_OTRIM1_Pos          (0U)\n#define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */\n#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */\n#define DAC_CCR_OTRIM2_Pos          (16U)\n#define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */\n#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */\n\n/*******************  Bit definition for DAC_MCR register  *******************/\n#define DAC_MCR_MODE1_Pos           (0U)\n#define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */\n#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */\n#define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */\n#define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */\n#define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */\n\n#define DAC_MCR_MODE2_Pos           (16U)\n#define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */\n#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */\n#define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */\n#define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */\n#define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */\n\n/******************  Bit definition for DAC_SHSR1 register  ******************/\n#define DAC_SHSR1_TSAMPLE1_Pos      (0U)\n#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */\n#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */\n\n/******************  Bit definition for DAC_SHSR2 register  ******************/\n#define DAC_SHSR2_TSAMPLE2_Pos      (0U)\n#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos)         /*!< 0x000003FF */\n#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */\n\n/******************  Bit definition for DAC_SHHR register  ******************/\n#define DAC_SHHR_THOLD1_Pos         (0U)\n#define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */\n#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */\n#define DAC_SHHR_THOLD2_Pos         (16U)\n#define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */\n#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */\n\n/******************  Bit definition for DAC_SHRR register  ******************/\n#define DAC_SHRR_TREFRESH1_Pos      (0U)\n#define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */\n#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */\n#define DAC_SHRR_TREFRESH2_Pos      (16U)\n#define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */\n#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    DCMI                                    */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DCMI_CR register  ******************/\n#define DCMI_CR_CAPTURE_Pos           (0U)\n#define DCMI_CR_CAPTURE_Msk           (0x1U << DCMI_CR_CAPTURE_Pos)            /*!< 0x00000001 */\n#define DCMI_CR_CAPTURE               DCMI_CR_CAPTURE_Msk                      /*!< DCMI Capture enable */\n#define DCMI_CR_CM_Pos                (1U)\n#define DCMI_CR_CM_Msk                (0x1U << DCMI_CR_CM_Pos)                 /*!< 0x00000002 */\n#define DCMI_CR_CM                    DCMI_CR_CM_Msk                           /*!< DCMI Capture mode */\n#define DCMI_CR_CROP_Pos              (2U)\n#define DCMI_CR_CROP_Msk              (0x1U << DCMI_CR_CROP_Pos)               /*!< 0x00000004 */\n#define DCMI_CR_CROP                  DCMI_CR_CROP_Msk                         /*!< DCMI Crop feature */\n#define DCMI_CR_JPEG_Pos              (3U)\n#define DCMI_CR_JPEG_Msk              (0x1U << DCMI_CR_JPEG_Pos)               /*!< 0x00000008 */\n#define DCMI_CR_JPEG                  DCMI_CR_JPEG_Msk                         /*!< DCMI JPEG format */\n#define DCMI_CR_ESS_Pos               (4U)\n#define DCMI_CR_ESS_Msk               (0x1U << DCMI_CR_ESS_Pos)                /*!< 0x00000010 */\n#define DCMI_CR_ESS                   DCMI_CR_ESS_Msk                          /*!< DCMI Embedded synchronization select */\n#define DCMI_CR_PCKPOL_Pos            (5U)\n#define DCMI_CR_PCKPOL_Msk            (0x1U << DCMI_CR_PCKPOL_Pos)             /*!< 0x00000020 */\n#define DCMI_CR_PCKPOL                DCMI_CR_PCKPOL_Msk                       /*!< DCMI Pixel clock polarity */\n#define DCMI_CR_HSPOL_Pos             (6U)\n#define DCMI_CR_HSPOL_Msk             (0x1U << DCMI_CR_HSPOL_Pos)              /*!< 0x00000040 */\n#define DCMI_CR_HSPOL                 DCMI_CR_HSPOL_Msk                        /*!< DCMI Horizontal synchronization polarity */\n#define DCMI_CR_VSPOL_Pos             (7U)\n#define DCMI_CR_VSPOL_Msk             (0x1U << DCMI_CR_VSPOL_Pos)              /*!< 0x00000080 */\n#define DCMI_CR_VSPOL                 DCMI_CR_VSPOL_Msk                        /*!< DCMI Vertical synchronization polarity */\n#define DCMI_CR_FCRC_Pos              (8U)\n#define DCMI_CR_FCRC_Msk              (0x3U << DCMI_CR_FCRC_Pos)               /*!< 0x00000300 */\n#define DCMI_CR_FCRC                  DCMI_CR_FCRC_Msk                         /*!< DCMI Frame capture rate control FCRC[1:0] */\n#define DCMI_CR_FCRC_0                (0x1U << DCMI_CR_FCRC_Pos)               /*!< 0x00000100 */\n#define DCMI_CR_FCRC_1                (0x2U << DCMI_CR_FCRC_Pos)               /*!< 0x00000200 */\n#define DCMI_CR_EDM_Pos               (10U)\n#define DCMI_CR_EDM_Msk               (0x3U << DCMI_CR_EDM_Pos)                /*!< 0x00000C00 */\n#define DCMI_CR_EDM                   DCMI_CR_EDM_Msk                          /*!< DCMI Extended data mode EDM[1:0] */\n#define DCMI_CR_EDM_0                 (0x1U << DCMI_CR_EDM_Pos)                /*!< 0x00000400 */\n#define DCMI_CR_EDM_1                 (0x2U << DCMI_CR_EDM_Pos)                /*!< 0x00000800 */\n#define DCMI_CR_ENABLE_Pos            (14U)\n#define DCMI_CR_ENABLE_Msk            (0x1U << DCMI_CR_ENABLE_Pos)             /*!< 0x00004000 */\n#define DCMI_CR_ENABLE                DCMI_CR_ENABLE_Msk                       /*!< DCMI DCMI enable */\n#define DCMI_CR_BSM_Pos               (16U)\n#define DCMI_CR_BSM_Msk               (0x3U << DCMI_CR_BSM_Pos)                /*!< 0x00030000 */\n#define DCMI_CR_BSM                   DCMI_CR_BSM_Msk                          /*!< DCMI Byte Select mode BSM[1:0] */\n#define DCMI_CR_BSM_0                 (0x1U << DCMI_CR_BSM_Pos)                /*!< 0x00010000 */\n#define DCMI_CR_BSM_1                 (0x2U << DCMI_CR_BSM_Pos)                /*!< 0x00020000 */\n#define DCMI_CR_OEBS_Pos              (18U)\n#define DCMI_CR_OEBS_Msk              (0x1U << DCMI_CR_OEBS_Pos)               /*!< 0x00040000 */\n#define DCMI_CR_OEBS                  DCMI_CR_OEBS_Msk                         /*!< DCMI Odd/Even Byte Select (Byte Select Start) */\n#define DCMI_CR_LSM_Pos               (19U)\n#define DCMI_CR_LSM_Msk               (0x1U << DCMI_CR_LSM_Pos)                /*!< 0x00080000 */\n#define DCMI_CR_LSM                   DCMI_CR_LSM_Msk                          /*!< DCMI Line Select mode */\n#define DCMI_CR_OELS_Pos              (20U)\n#define DCMI_CR_OELS_Msk              (0x1U << DCMI_CR_OELS_Pos)               /*!< 0x00100000 */\n#define DCMI_CR_OELS                  DCMI_CR_OELS_Msk                         /*!< DCMI Odd/Even Line Select (Line Select Start) */\n\n/********************  Bits definition for DCMI_SR register  ******************/\n#define DCMI_SR_HSYNC_Pos             (0U)\n#define DCMI_SR_HSYNC_Msk             (0x1U << DCMI_SR_HSYNC_Pos)              /*!< 0x00000001 */\n#define DCMI_SR_HSYNC                 DCMI_SR_HSYNC_Msk\n#define DCMI_SR_VSYNC_Pos             (1U)\n#define DCMI_SR_VSYNC_Msk             (0x1U << DCMI_SR_VSYNC_Pos)              /*!< 0x00000002 */\n#define DCMI_SR_VSYNC                 DCMI_SR_VSYNC_Msk\n#define DCMI_SR_FNE_Pos               (2U)\n#define DCMI_SR_FNE_Msk               (0x1U << DCMI_SR_FNE_Pos)                /*!< 0x00000004 */\n#define DCMI_SR_FNE                   DCMI_SR_FNE_Msk                          /*!< DCMI FIFO not empty */\n\n/********************  Bits definition for DCMI_RISR register  ****************/\n#define DCMI_RIS_FRAME_RIS_Pos        (0U)\n#define DCMI_RIS_FRAME_RIS_Msk        (0x1U << DCMI_RIS_FRAME_RIS_Pos)         /*!< 0x00000001 */\n#define DCMI_RIS_FRAME_RIS            DCMI_RIS_FRAME_RIS_Msk                   /*!< DCMI Capture complete raw interrupt status */\n#define DCMI_RIS_OVR_RIS_Pos          (1U)\n#define DCMI_RIS_OVR_RIS_Msk          (0x1U << DCMI_RIS_OVR_RIS_Pos)           /*!< 0x00000002 */\n#define DCMI_RIS_OVR_RIS              DCMI_RIS_OVR_RIS_Msk                     /*!< DCMI Overrun raw interrupt status */\n#define DCMI_RIS_ERR_RIS_Pos          (2U)\n#define DCMI_RIS_ERR_RIS_Msk          (0x1U << DCMI_RIS_ERR_RIS_Pos)           /*!< 0x00000004 */\n#define DCMI_RIS_ERR_RIS              DCMI_RIS_ERR_RIS_Msk                     /*!< DCMI Synchronization error raw interrupt status */\n#define DCMI_RIS_VSYNC_RIS_Pos        (3U)\n#define DCMI_RIS_VSYNC_RIS_Msk        (0x1U << DCMI_RIS_VSYNC_RIS_Pos)         /*!< 0x00000008 */\n#define DCMI_RIS_VSYNC_RIS            DCMI_RIS_VSYNC_RIS_Msk                   /*!< DCMI VSYNC raw interrupt status */\n#define DCMI_RIS_LINE_RIS_Pos         (4U)\n#define DCMI_RIS_LINE_RIS_Msk         (0x1U << DCMI_RIS_LINE_RIS_Pos)          /*!< 0x00000010 */\n#define DCMI_RIS_LINE_RIS             DCMI_RIS_LINE_RIS_Msk                    /*!< DCMI Line raw interrupt status */\n\n/********************  Bits definition for DCMI_IER register  *****************/\n#define DCMI_IER_FRAME_IE_Pos         (0U)\n#define DCMI_IER_FRAME_IE_Msk         (0x1U << DCMI_IER_FRAME_IE_Pos)          /*!< 0x00000001 */\n#define DCMI_IER_FRAME_IE             DCMI_IER_FRAME_IE_Msk                    /*!< DCMI Capture complete interrupt enable */\n#define DCMI_IER_OVR_IE_Pos           (1U)\n#define DCMI_IER_OVR_IE_Msk           (0x1U << DCMI_IER_OVR_IE_Pos)            /*!< 0x00000002 */\n#define DCMI_IER_OVR_IE               DCMI_IER_OVR_IE_Msk                      /*!< DCMI Overrun interrupt enable */\n#define DCMI_IER_ERR_IE_Pos           (2U)\n#define DCMI_IER_ERR_IE_Msk           (0x1U << DCMI_IER_ERR_IE_Pos)            /*!< 0x00000004 */\n#define DCMI_IER_ERR_IE               DCMI_IER_ERR_IE_Msk                      /*!< DCMI Synchronization error interrupt enable */\n#define DCMI_IER_VSYNC_IE_Pos         (3U)\n#define DCMI_IER_VSYNC_IE_Msk         (0x1U << DCMI_IER_VSYNC_IE_Pos)          /*!< 0x00000008 */\n#define DCMI_IER_VSYNC_IE             DCMI_IER_VSYNC_IE_Msk                    /*!< DCMI VSYNC interrupt enable */\n#define DCMI_IER_LINE_IE_Pos          (4U)\n#define DCMI_IER_LINE_IE_Msk          (0x1U << DCMI_IER_LINE_IE_Pos)           /*!< 0x00000010 */\n#define DCMI_IER_LINE_IE              DCMI_IER_LINE_IE_Msk                     /*!< DCMI Line interrupt enable */\n#define DCMI_IER_INT_IE_Pos           (0U)\n#define DCMI_IER_INT_IE_Msk           (0x1FU << DCMI_IER_INT_IE_Pos)           /*!< 0x0000001F */\n#define DCMI_IER_INT_IE               DCMI_IER_INT_IE_Msk\n\n/********************  Bits definition for DCMI_MIS register  *****************/\n#define DCMI_MIS_FRAME_MIS_Pos        (0U)\n#define DCMI_MIS_FRAME_MIS_Msk        (0x1U << DCMI_MIS_FRAME_MIS_Pos)         /*!< 0x00000001 */\n#define DCMI_MIS_FRAME_MIS            DCMI_MIS_FRAME_MIS_Msk                   /*!< DCMI Capture complete masked interrupt status */\n#define DCMI_MIS_OVR_MIS_Pos          (1U)\n#define DCMI_MIS_OVR_MIS_Msk          (0x1U << DCMI_MIS_OVR_MIS_Pos)           /*!< 0x00000002 */\n#define DCMI_MIS_OVR_MIS              DCMI_MIS_OVR_MIS_Msk                     /*!< DCMI Overrun masked interrupt status */\n#define DCMI_MIS_ERR_MIS_Pos          (2U)\n#define DCMI_MIS_ERR_MIS_Msk          (0x1U << DCMI_MIS_ERR_MIS_Pos)           /*!< 0x00000004 */\n#define DCMI_MIS_ERR_MIS              DCMI_MIS_ERR_MIS_Msk                     /*!< DCMI Synchronization error masked interrupt status */\n#define DCMI_MIS_VSYNC_MIS_Pos        (3U)\n#define DCMI_MIS_VSYNC_MIS_Msk        (0x1U << DCMI_MIS_VSYNC_MIS_Pos)         /*!< 0x00000008 */\n#define DCMI_MIS_VSYNC_MIS            DCMI_MIS_VSYNC_MIS_Msk                   /*!< DCMI VSYNC masked interrupt status */\n#define DCMI_MIS_LINE_MIS_Pos         (4U)\n#define DCMI_MIS_LINE_MIS_Msk         (0x1U << DCMI_MIS_LINE_MIS_Pos)          /*!< 0x00000010 */\n#define DCMI_MIS_LINE_MIS             DCMI_MIS_LINE_MIS_Msk                    /*!< DCMI Line masked interrupt status */\n\n/********************  Bits definition for DCMI_ICR register  *****************/\n#define DCMI_ICR_FRAME_ISC_Pos        (0U)\n#define DCMI_ICR_FRAME_ISC_Msk        (0x1U << DCMI_ICR_FRAME_ISC_Pos)         /*!< 0x00000001 */\n#define DCMI_ICR_FRAME_ISC            DCMI_ICR_FRAME_ISC_Msk                   /*!< DCMI Capture complete interrupt status clear */\n#define DCMI_ICR_OVR_ISC_Pos          (1U)\n#define DCMI_ICR_OVR_ISC_Msk          (0x1U << DCMI_ICR_OVR_ISC_Pos)           /*!< 0x00000002 */\n#define DCMI_ICR_OVR_ISC              DCMI_ICR_OVR_ISC_Msk                     /*!< DCMI Overrun interrupt status clear */\n#define DCMI_ICR_ERR_ISC_Pos          (2U)\n#define DCMI_ICR_ERR_ISC_Msk          (0x1U << DCMI_ICR_ERR_ISC_Pos)           /*!< 0x00000004 */\n#define DCMI_ICR_ERR_ISC              DCMI_ICR_ERR_ISC_Msk                     /*!< DCMI Synchronization error interrupt status clear */\n#define DCMI_ICR_VSYNC_ISC_Pos        (3U)\n#define DCMI_ICR_VSYNC_ISC_Msk        (0x1U << DCMI_ICR_VSYNC_ISC_Pos)         /*!< 0x00000008 */\n#define DCMI_ICR_VSYNC_ISC            DCMI_ICR_VSYNC_ISC_Msk                   /*!< DCMI Vertical synch interrupt status clear */\n#define DCMI_ICR_LINE_ISC_Pos         (4U)\n#define DCMI_ICR_LINE_ISC_Msk         (0x1U << DCMI_ICR_LINE_ISC_Pos)          /*!< 0x00000010 */\n#define DCMI_ICR_LINE_ISC             DCMI_ICR_LINE_ISC_Msk                    /*!< DCMI line interrupt status clear */\n\n/********************  Bits definition for DCMI_ESCR register  ****************/\n#define DCMI_ESCR_FSC_Pos             (0U)\n#define DCMI_ESCR_FSC_Msk             (0xFFU << DCMI_ESCR_FSC_Pos)             /*!< 0x000000FF */\n#define DCMI_ESCR_FSC                 DCMI_ESCR_FSC_Msk                        /*!< DCMI Frame start delimiter code FSC[7:0] */\n#define DCMI_ESCR_FSC_0               (0x01U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000001 */\n#define DCMI_ESCR_FSC_1               (0x02U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000002 */\n#define DCMI_ESCR_FSC_2               (0x04U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000004 */\n#define DCMI_ESCR_FSC_3               (0x08U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000008 */\n#define DCMI_ESCR_FSC_4               (0x10U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000010 */\n#define DCMI_ESCR_FSC_5               (0x20U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000020 */\n#define DCMI_ESCR_FSC_6               (0x40U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000040 */\n#define DCMI_ESCR_FSC_7               (0x80U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000080 */\n#define DCMI_ESCR_LSC_Pos             (8U)\n#define DCMI_ESCR_LSC_Msk             (0xFFU << DCMI_ESCR_LSC_Pos)             /*!< 0x0000FF00 */\n#define DCMI_ESCR_LSC                 DCMI_ESCR_LSC_Msk                        /*!< DCMI Line start delimiter code LSC[7:0] */\n#define DCMI_ESCR_LSC_0               (0x01U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000100 */\n#define DCMI_ESCR_LSC_1               (0x02U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000200 */\n#define DCMI_ESCR_LSC_2               (0x04U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000400 */\n#define DCMI_ESCR_LSC_3               (0x08U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000800 */\n#define DCMI_ESCR_LSC_4               (0x10U << DCMI_ESCR_LSC_Pos)             /*!< 0x00001000 */\n#define DCMI_ESCR_LSC_5               (0x20U << DCMI_ESCR_LSC_Pos)             /*!< 0x00002000 */\n#define DCMI_ESCR_LSC_6               (0x40U << DCMI_ESCR_LSC_Pos)             /*!< 0x00004000 */\n#define DCMI_ESCR_LSC_7               (0x80U << DCMI_ESCR_LSC_Pos)             /*!< 0x00008000 */\n#define DCMI_ESCR_LEC_Pos             (16U)\n#define DCMI_ESCR_LEC_Msk             (0xFFU << DCMI_ESCR_LEC_Pos)             /*!< 0x00FF0000 */\n#define DCMI_ESCR_LEC                 DCMI_ESCR_LEC_Msk                        /*!< DCMI Line end delimiter code LEC[7:0] */\n#define DCMI_ESCR_LEC_0               (0x01U << DCMI_ESCR_LEC_Pos)             /*!< 0x00010000 */\n#define DCMI_ESCR_LEC_1               (0x02U << DCMI_ESCR_LEC_Pos)             /*!< 0x00020000 */\n#define DCMI_ESCR_LEC_2               (0x04U << DCMI_ESCR_LEC_Pos)             /*!< 0x00040000 */\n#define DCMI_ESCR_LEC_3               (0x08U << DCMI_ESCR_LEC_Pos)             /*!< 0x00080000 */\n#define DCMI_ESCR_LEC_4               (0x10U << DCMI_ESCR_LEC_Pos)             /*!< 0x00100000 */\n#define DCMI_ESCR_LEC_5               (0x20U << DCMI_ESCR_LEC_Pos)             /*!< 0x00200000 */\n#define DCMI_ESCR_LEC_6               (0x40U << DCMI_ESCR_LEC_Pos)             /*!< 0x00400000 */\n#define DCMI_ESCR_LEC_7               (0x80U << DCMI_ESCR_LEC_Pos)             /*!< 0x00800000 */\n#define DCMI_ESCR_FEC_Pos             (24U)\n#define DCMI_ESCR_FEC_Msk             (0xFFU << DCMI_ESCR_FEC_Pos)             /*!< 0xFF000000 */\n#define DCMI_ESCR_FEC                 DCMI_ESCR_FEC_Msk                        /*!< DCMI Frame end delimiter code FEC[7:0] */\n#define DCMI_ESCR_FEC_0               (0x01U << DCMI_ESCR_FEC_Pos)             /*!< 0x01000000 */\n#define DCMI_ESCR_FEC_1               (0x02U << DCMI_ESCR_FEC_Pos)             /*!< 0x02000000 */\n#define DCMI_ESCR_FEC_2               (0x04U << DCMI_ESCR_FEC_Pos)             /*!< 0x04000000 */\n#define DCMI_ESCR_FEC_3               (0x08U << DCMI_ESCR_FEC_Pos)             /*!< 0x08000000 */\n#define DCMI_ESCR_FEC_4               (0x10U << DCMI_ESCR_FEC_Pos)             /*!< 0x10000000 */\n#define DCMI_ESCR_FEC_5               (0x20U << DCMI_ESCR_FEC_Pos)             /*!< 0x20000000 */\n#define DCMI_ESCR_FEC_6               (0x40U << DCMI_ESCR_FEC_Pos)             /*!< 0x40000000 */\n#define DCMI_ESCR_FEC_7               (0x80U << DCMI_ESCR_FEC_Pos)             /*!< 0x80000000 */\n\n/********************  Bits definition for DCMI_ESUR register  ****************/\n#define DCMI_ESUR_FSU_Pos             (0U)\n#define DCMI_ESUR_FSU_Msk             (0xFFU << DCMI_ESUR_FSU_Pos)             /*!< 0x000000FF */\n#define DCMI_ESUR_FSU                 DCMI_ESUR_FSU_Msk                        /*!< DCMI Frame start delimiter unmask FSU[7:0] */\n#define DCMI_ESUR_FSU_0               (0x01U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000001 */\n#define DCMI_ESUR_FSU_1               (0x02U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000002 */\n#define DCMI_ESUR_FSU_2               (0x04U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000004 */\n#define DCMI_ESUR_FSU_3               (0x08U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000008 */\n#define DCMI_ESUR_FSU_4               (0x10U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000010 */\n#define DCMI_ESUR_FSU_5               (0x20U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000020 */\n#define DCMI_ESUR_FSU_6               (0x40U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000040 */\n#define DCMI_ESUR_FSU_7               (0x80U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000080 */\n#define DCMI_ESUR_LSU_Pos             (8U)\n#define DCMI_ESUR_LSU_Msk             (0xFFU << DCMI_ESUR_LSU_Pos)             /*!< 0x0000FF00 */\n#define DCMI_ESUR_LSU                 DCMI_ESUR_LSU_Msk                        /*!< DCMI Line start delimiter unmask LSU[7:0] */\n#define DCMI_ESUR_LSU_0               (0x01U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000100 */\n#define DCMI_ESUR_LSU_1               (0x02U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000200 */\n#define DCMI_ESUR_LSU_2               (0x04U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000400 */\n#define DCMI_ESUR_LSU_3               (0x08U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000800 */\n#define DCMI_ESUR_LSU_4               (0x10U << DCMI_ESUR_LSU_Pos)             /*!< 0x00001000 */\n#define DCMI_ESUR_LSU_5               (0x20U << DCMI_ESUR_LSU_Pos)             /*!< 0x00002000 */\n#define DCMI_ESUR_LSU_6               (0x40U << DCMI_ESUR_LSU_Pos)             /*!< 0x00004000 */\n#define DCMI_ESUR_LSU_7               (0x80U << DCMI_ESUR_LSU_Pos)             /*!< 0x00008000 */\n#define DCMI_ESUR_LEU_Pos             (16U)\n#define DCMI_ESUR_LEU_Msk             (0xFFU << DCMI_ESUR_LEU_Pos)             /*!< 0x00FF0000 */\n#define DCMI_ESUR_LEU                 DCMI_ESUR_LEU_Msk                        /*!< DCMI Line end delimiter unmask LEU[7:0] */\n#define DCMI_ESUR_LEU_0               (0x01U << DCMI_ESUR_LEU_Pos)             /*!< 0x00010000 */\n#define DCMI_ESUR_LEU_1               (0x02U << DCMI_ESUR_LEU_Pos)             /*!< 0x00020000 */\n#define DCMI_ESUR_LEU_2               (0x04U << DCMI_ESUR_LEU_Pos)             /*!< 0x00040000 */\n#define DCMI_ESUR_LEU_3               (0x08U << DCMI_ESUR_LEU_Pos)             /*!< 0x00080000 */\n#define DCMI_ESUR_LEU_4               (0x10U << DCMI_ESUR_LEU_Pos)             /*!< 0x00100000 */\n#define DCMI_ESUR_LEU_5               (0x20U << DCMI_ESUR_LEU_Pos)             /*!< 0x00200000 */\n#define DCMI_ESUR_LEU_6               (0x40U << DCMI_ESUR_LEU_Pos)             /*!< 0x00400000 */\n#define DCMI_ESUR_LEU_7               (0x80U << DCMI_ESUR_LEU_Pos)             /*!< 0x00800000 */\n#define DCMI_ESUR_FEU_Pos             (24U)\n#define DCMI_ESUR_FEU_Msk             (0xFFU << DCMI_ESUR_FEU_Pos)             /*!< 0xFF000000 */\n#define DCMI_ESUR_FEU                 DCMI_ESUR_FEU_Msk                        /*!< DCMI Frame end delimiter unmask FEU[7:0] */\n#define DCMI_ESUR_FEU_0               (0x01U << DCMI_ESUR_FEU_Pos)             /*!< 0x01000000 */\n#define DCMI_ESUR_FEU_1               (0x02U << DCMI_ESUR_FEU_Pos)             /*!< 0x02000000 */\n#define DCMI_ESUR_FEU_2               (0x04U << DCMI_ESUR_FEU_Pos)             /*!< 0x04000000 */\n#define DCMI_ESUR_FEU_3               (0x08U << DCMI_ESUR_FEU_Pos)             /*!< 0x08000000 */\n#define DCMI_ESUR_FEU_4               (0x10U << DCMI_ESUR_FEU_Pos)             /*!< 0x10000000 */\n#define DCMI_ESUR_FEU_5               (0x20U << DCMI_ESUR_FEU_Pos)             /*!< 0x20000000 */\n#define DCMI_ESUR_FEU_6               (0x40U << DCMI_ESUR_FEU_Pos)             /*!< 0x40000000 */\n#define DCMI_ESUR_FEU_7               (0x80U << DCMI_ESUR_FEU_Pos)             /*!< 0x80000000 */\n\n/********************  Bits definition for DCMI_CWSTRT register  **************/\n#define DCMI_CWSTRT_HOFFCNT_Pos       (0U)\n#define DCMI_CWSTRT_HOFFCNT_Msk       (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00003FFF */\n#define DCMI_CWSTRT_HOFFCNT           DCMI_CWSTRT_HOFFCNT_Msk                  /*!< DCMI Horizontal offset count HOFFCNT[13:0] */\n#define DCMI_CWSTRT_HOFFCNT_0         (0x0001U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000001 */\n#define DCMI_CWSTRT_HOFFCNT_1         (0x0002U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000002 */\n#define DCMI_CWSTRT_HOFFCNT_2         (0x0004U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000004 */\n#define DCMI_CWSTRT_HOFFCNT_3         (0x0008U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000008 */\n#define DCMI_CWSTRT_HOFFCNT_4         (0x0010U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000010 */\n#define DCMI_CWSTRT_HOFFCNT_5         (0x0020U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000020 */\n#define DCMI_CWSTRT_HOFFCNT_6         (0x0040U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000040 */\n#define DCMI_CWSTRT_HOFFCNT_7         (0x0080U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000080 */\n#define DCMI_CWSTRT_HOFFCNT_8         (0x0100U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000100 */\n#define DCMI_CWSTRT_HOFFCNT_9         (0x0200U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000200 */\n#define DCMI_CWSTRT_HOFFCNT_10        (0x0400U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000400 */\n#define DCMI_CWSTRT_HOFFCNT_11        (0x0800U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000800 */\n#define DCMI_CWSTRT_HOFFCNT_12        (0x1000U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00001000 */\n#define DCMI_CWSTRT_HOFFCNT_13        (0x2000U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00002000 */\n#define DCMI_CWSTRT_VST_Pos           (16U)\n#define DCMI_CWSTRT_VST_Msk           (0x1FFFU << DCMI_CWSTRT_VST_Pos)         /*!< 0x1FFF0000 */\n#define DCMI_CWSTRT_VST               DCMI_CWSTRT_VST_Msk                      /*!< DCMI Vertical start line count VST[12:0] */\n#define DCMI_CWSTRT_VST_0             (0x0001U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00010000 */\n#define DCMI_CWSTRT_VST_1             (0x0002U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00020000 */\n#define DCMI_CWSTRT_VST_2             (0x0004U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00040000 */\n#define DCMI_CWSTRT_VST_3             (0x0008U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00080000 */\n#define DCMI_CWSTRT_VST_4             (0x0010U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00100000 */\n#define DCMI_CWSTRT_VST_5             (0x0020U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00200000 */\n#define DCMI_CWSTRT_VST_6             (0x0040U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00400000 */\n#define DCMI_CWSTRT_VST_7             (0x0080U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00800000 */\n#define DCMI_CWSTRT_VST_8             (0x0100U << DCMI_CWSTRT_VST_Pos)         /*!< 0x01000000 */\n#define DCMI_CWSTRT_VST_9             (0x0200U << DCMI_CWSTRT_VST_Pos)         /*!< 0x02000000 */\n#define DCMI_CWSTRT_VST_10            (0x0400U << DCMI_CWSTRT_VST_Pos)         /*!< 0x04000000 */\n#define DCMI_CWSTRT_VST_11            (0x0800U << DCMI_CWSTRT_VST_Pos)         /*!< 0x08000000 */\n#define DCMI_CWSTRT_VST_12            (0x1000U << DCMI_CWSTRT_VST_Pos)         /*!< 0x10000000 */\n\n/********************  Bits definition for DCMI_CWSIZE register  **************/\n#define DCMI_CWSIZE_CAPCNT_Pos        (0U)\n#define DCMI_CWSIZE_CAPCNT_Msk        (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00003FFF */\n#define DCMI_CWSIZE_CAPCNT            DCMI_CWSIZE_CAPCNT_Msk                   /*!< DCMI Capture count CAPCNT[13:0] */\n#define DCMI_CWSIZE_CAPCNT_0          (0x0001U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000001 */\n#define DCMI_CWSIZE_CAPCNT_1          (0x0002U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000002 */\n#define DCMI_CWSIZE_CAPCNT_2          (0x0004U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000004 */\n#define DCMI_CWSIZE_CAPCNT_3          (0x0008U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000008 */\n#define DCMI_CWSIZE_CAPCNT_4          (0x0010U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000010 */\n#define DCMI_CWSIZE_CAPCNT_5          (0x0020U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000020 */\n#define DCMI_CWSIZE_CAPCNT_6          (0x0040U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000040 */\n#define DCMI_CWSIZE_CAPCNT_7          (0x0080U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000080 */\n#define DCMI_CWSIZE_CAPCNT_8          (0x0100U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000100 */\n#define DCMI_CWSIZE_CAPCNT_9          (0x0200U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000200 */\n#define DCMI_CWSIZE_CAPCNT_10         (0x0400U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000400 */\n#define DCMI_CWSIZE_CAPCNT_11         (0x0800U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000800 */\n#define DCMI_CWSIZE_CAPCNT_12         (0x1000U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00001000 */\n#define DCMI_CWSIZE_CAPCNT_13         (0x2000U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00002000 */\n#define DCMI_CWSIZE_VLINE_Pos         (16U)\n#define DCMI_CWSIZE_VLINE_Msk         (0x3FFFU << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x3FFF0000 */\n#define DCMI_CWSIZE_VLINE             DCMI_CWSIZE_VLINE_Msk                    /*!< DCMI Vertical line count VLINE[13:0] */\n#define DCMI_CWSIZE_VLINE_0           (0x0001U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00010000 */\n#define DCMI_CWSIZE_VLINE_1           (0x0002U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00020000 */\n#define DCMI_CWSIZE_VLINE_2           (0x0004U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00040000 */\n#define DCMI_CWSIZE_VLINE_3           (0x0008U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00080000 */\n#define DCMI_CWSIZE_VLINE_4           (0x0010U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00100000 */\n#define DCMI_CWSIZE_VLINE_5           (0x0020U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00200000 */\n#define DCMI_CWSIZE_VLINE_6           (0x0040U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00400000 */\n#define DCMI_CWSIZE_VLINE_7           (0x0080U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00800000 */\n#define DCMI_CWSIZE_VLINE_8           (0x0100U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x01000000 */\n#define DCMI_CWSIZE_VLINE_9           (0x0200U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x02000000 */\n#define DCMI_CWSIZE_VLINE_10          (0x0400U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x04000000 */\n#define DCMI_CWSIZE_VLINE_11          (0x0800U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x08000000 */\n#define DCMI_CWSIZE_VLINE_12          (0x1000U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x10000000 */\n#define DCMI_CWSIZE_VLINE_13          (0x2000U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x20000000 */\n\n/********************  Bits definition for DCMI_DR register  **************/\n#define DCMI_DR_BYTE0_Pos             (0U)\n#define DCMI_DR_BYTE0_Msk             (0xFFU << DCMI_DR_BYTE0_Pos)             /*!< 0x000000FF */\n#define DCMI_DR_BYTE0                 DCMI_DR_BYTE0_Msk                        /*!< DCMI Data byte 0 Byte0[7:0] */\n#define DCMI_DR_BYTE0_0               (0x01U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000001 */\n#define DCMI_DR_BYTE0_1               (0x02U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000002 */\n#define DCMI_DR_BYTE0_2               (0x04U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000004 */\n#define DCMI_DR_BYTE0_3               (0x08U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000008 */\n#define DCMI_DR_BYTE0_4               (0x10U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000010 */\n#define DCMI_DR_BYTE0_5               (0x20U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000020 */\n#define DCMI_DR_BYTE0_6               (0x40U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000040 */\n#define DCMI_DR_BYTE0_7               (0x80U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000080 */\n#define DCMI_DR_BYTE1_Pos             (8U)\n#define DCMI_DR_BYTE1_Msk             (0xFFU << DCMI_DR_BYTE1_Pos)             /*!< 0x0000FF00 */\n#define DCMI_DR_BYTE1                 DCMI_DR_BYTE1_Msk                        /*!< DCMI Data byte 1 Byte1[7:0] */\n#define DCMI_DR_BYTE1_0               (0x01U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000100 */\n#define DCMI_DR_BYTE1_1               (0x02U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000200 */\n#define DCMI_DR_BYTE1_2               (0x04U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000400 */\n#define DCMI_DR_BYTE1_3               (0x08U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000800 */\n#define DCMI_DR_BYTE1_4               (0x10U << DCMI_DR_BYTE1_Pos)             /*!< 0x00001000 */\n#define DCMI_DR_BYTE1_5               (0x20U << DCMI_DR_BYTE1_Pos)             /*!< 0x00002000 */\n#define DCMI_DR_BYTE1_6               (0x40U << DCMI_DR_BYTE1_Pos)             /*!< 0x00004000 */\n#define DCMI_DR_BYTE1_7               (0x80U << DCMI_DR_BYTE1_Pos)             /*!< 0x00008000 */\n#define DCMI_DR_BYTE2_Pos             (16U)\n#define DCMI_DR_BYTE2_Msk             (0xFFU << DCMI_DR_BYTE2_Pos)             /*!< 0x00FF0000 */\n#define DCMI_DR_BYTE2                 DCMI_DR_BYTE2_Msk                        /*!< DCMI Data byte 2 Byte2[7:0] */\n#define DCMI_DR_BYTE2_0               (0x01U << DCMI_DR_BYTE2_Pos)             /*!< 0x00010000 */\n#define DCMI_DR_BYTE2_1               (0x02U << DCMI_DR_BYTE2_Pos)             /*!< 0x00020000 */\n#define DCMI_DR_BYTE2_2               (0x04U << DCMI_DR_BYTE2_Pos)             /*!< 0x00040000 */\n#define DCMI_DR_BYTE2_3               (0x08U << DCMI_DR_BYTE2_Pos)             /*!< 0x00080000 */\n#define DCMI_DR_BYTE2_4               (0x10U << DCMI_DR_BYTE2_Pos)             /*!< 0x00100000 */\n#define DCMI_DR_BYTE2_5               (0x20U << DCMI_DR_BYTE2_Pos)             /*!< 0x00200000 */\n#define DCMI_DR_BYTE2_6               (0x40U << DCMI_DR_BYTE2_Pos)             /*!< 0x00400000 */\n#define DCMI_DR_BYTE2_7               (0x80U << DCMI_DR_BYTE2_Pos)             /*!< 0x00800000 */\n#define DCMI_DR_BYTE3_Pos             (24U)\n#define DCMI_DR_BYTE3_Msk             (0xFFU << DCMI_DR_BYTE3_Pos)             /*!< 0xFF000000 */\n#define DCMI_DR_BYTE3                 DCMI_DR_BYTE3_Msk                        /*!< DCMI Data byte 3 Byte3[7:0] */\n#define DCMI_DR_BYTE3_0               (0x01U << DCMI_DR_BYTE3_Pos)             /*!< 0x01000000 */\n#define DCMI_DR_BYTE3_1               (0x02U << DCMI_DR_BYTE3_Pos)             /*!< 0x02000000 */\n#define DCMI_DR_BYTE3_2               (0x04U << DCMI_DR_BYTE3_Pos)             /*!< 0x04000000 */\n#define DCMI_DR_BYTE3_3               (0x08U << DCMI_DR_BYTE3_Pos)             /*!< 0x08000000 */\n#define DCMI_DR_BYTE3_4               (0x10U << DCMI_DR_BYTE3_Pos)             /*!< 0x10000000 */\n#define DCMI_DR_BYTE3_5               (0x20U << DCMI_DR_BYTE3_Pos)             /*!< 0x20000000 */\n#define DCMI_DR_BYTE3_6               (0x40U << DCMI_DR_BYTE3_Pos)             /*!< 0x40000000 */\n#define DCMI_DR_BYTE3_7               (0x80U << DCMI_DR_BYTE3_Pos)             /*!< 0x80000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                 Digital Filter for Sigma Delta Modulators                  */\n/*                                                                            */\n/******************************************************************************/\n\n/****************   DFSDM channel configuration registers  ********************/\n\n/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/\n#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)\n#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */\n#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */\n#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)\n#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */\n#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */\n#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)\n#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */\n#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */\n#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)\n#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */\n#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */\n#define DFSDM_CHCFGR1_DATPACK_1         (0x2U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */\n#define DFSDM_CHCFGR1_DATPACK_0         (0x1U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */\n#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)\n#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */\n#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */\n#define DFSDM_CHCFGR1_DATMPX_1          (0x2U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */\n#define DFSDM_CHCFGR1_DATMPX_0          (0x1U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */\n#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)\n#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */\n#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */\n#define DFSDM_CHCFGR1_CHEN_Pos          (7U)\n#define DFSDM_CHCFGR1_CHEN_Msk          (0x1U << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */\n#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */\n#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)\n#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1U << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */\n#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */\n#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)\n#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1U << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)\n#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */\n#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */\n#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */\n#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */\n#define DFSDM_CHCFGR1_SITP_Pos          (0U)\n#define DFSDM_CHCFGR1_SITP_Msk          (0x3U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */\n#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */\n#define DFSDM_CHCFGR1_SITP_1            (0x2U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */\n#define DFSDM_CHCFGR1_SITP_0            (0x1U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */\n\n/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/\n#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)\n#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */\n#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)\n#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */\n#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */\n\n/****************  Bit definition for DFSDM_CHAWSCDR register *****************/\n#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)\n#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */\n#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */\n#define DFSDM_CHAWSCDR_AWFORD_1         (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */\n#define DFSDM_CHAWSCDR_AWFORD_0         (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */\n#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)\n#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */\n#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */\n#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)\n#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */\n#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */\n#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)\n#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */\n#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */\n\n/****************  Bit definition for DFSDM_CHWDATR register *******************/\n#define DFSDM_CHWDATR_WDATA_Pos         (0U)\n#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */\n#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */\n\n/****************  Bit definition for DFSDM_CHDATINR register *****************/\n#define DFSDM_CHDATINR_INDAT0_Pos       (0U)\n#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */\n#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */\n#define DFSDM_CHDATINR_INDAT1_Pos       (16U)\n#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */\n#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */\n\n/************************   DFSDM module registers  ****************************/\n\n/*****************  Bit definition for DFSDM_FLTCR1 register *******************/\n#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)\n#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1U << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */\n#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */\n#define DFSDM_FLTCR1_FAST_Pos           (29U)\n#define DFSDM_FLTCR1_FAST_Msk           (0x1U << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */\n#define DFSDM_FLTCR1_RCH_Pos            (24U)\n#define DFSDM_FLTCR1_RCH_Msk            (0x7U << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */\n#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */\n#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)\n#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1U << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */\n#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */\n#define DFSDM_FLTCR1_RSYNC_Pos          (19U)\n#define DFSDM_FLTCR1_RSYNC_Msk          (0x1U << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */\n#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */\n#define DFSDM_FLTCR1_RCONT_Pos          (18U)\n#define DFSDM_FLTCR1_RCONT_Msk          (0x1U << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */\n#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */\n#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)\n#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1U << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */\n#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */\n#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)\n#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */\n#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */\n#define DFSDM_FLTCR1_JEXTEN_1           (0x2U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */\n#define DFSDM_FLTCR1_JEXTEN_0           (0x1U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */\n#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)\n#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */\n#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */\n#define DFSDM_FLTCR1_JEXTSEL_2          (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */\n#define DFSDM_FLTCR1_JEXTSEL_1          (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */\n#define DFSDM_FLTCR1_JEXTSEL_0          (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */\n#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)\n#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1U << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */\n#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */\n#define DFSDM_FLTCR1_JSCAN_Pos          (4U)\n#define DFSDM_FLTCR1_JSCAN_Msk          (0x1U << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */\n#define DFSDM_FLTCR1_JSYNC_Pos          (3U)\n#define DFSDM_FLTCR1_JSYNC_Msk          (0x1U << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */\n#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)\n#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1U << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */\n#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */\n#define DFSDM_FLTCR1_DFEN_Pos           (0U)\n#define DFSDM_FLTCR1_DFEN_Msk           (0x1U << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */\n#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */\n\n/*****************  Bit definition for DFSDM_FLTCR2 register *******************/\n#define DFSDM_FLTCR2_AWDCH_Pos          (16U)\n#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFU << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */\n#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */\n#define DFSDM_FLTCR2_EXCH_Pos           (8U)\n#define DFSDM_FLTCR2_EXCH_Msk           (0xFFU << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */\n#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */\n#define DFSDM_FLTCR2_CKABIE_Pos         (6U)\n#define DFSDM_FLTCR2_CKABIE_Msk         (0x1U << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */\n#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */\n#define DFSDM_FLTCR2_SCDIE_Pos          (5U)\n#define DFSDM_FLTCR2_SCDIE_Msk          (0x1U << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */\n#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */\n#define DFSDM_FLTCR2_AWDIE_Pos          (4U)\n#define DFSDM_FLTCR2_AWDIE_Msk          (0x1U << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */\n#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */\n#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)\n#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1U << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */\n#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */\n#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)\n#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1U << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */\n#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */\n#define DFSDM_FLTCR2_REOCIE_Pos         (1U)\n#define DFSDM_FLTCR2_REOCIE_Msk         (0x1U << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */\n#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */\n#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)\n#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1U << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */\n#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */\n\n/*****************  Bit definition for DFSDM_FLTISR register *******************/\n#define DFSDM_FLTISR_SCDF_Pos           (24U)\n#define DFSDM_FLTISR_SCDF_Msk           (0xFFU << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */\n#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */\n#define DFSDM_FLTISR_CKABF_Pos          (16U)\n#define DFSDM_FLTISR_CKABF_Msk          (0xFFU << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */\n#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */\n#define DFSDM_FLTISR_RCIP_Pos           (14U)\n#define DFSDM_FLTISR_RCIP_Msk           (0x1U << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */\n#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */\n#define DFSDM_FLTISR_JCIP_Pos           (13U)\n#define DFSDM_FLTISR_JCIP_Msk           (0x1U << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */\n#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */\n#define DFSDM_FLTISR_AWDF_Pos           (4U)\n#define DFSDM_FLTISR_AWDF_Msk           (0x1U << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */\n#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */\n#define DFSDM_FLTISR_ROVRF_Pos          (3U)\n#define DFSDM_FLTISR_ROVRF_Msk          (0x1U << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */\n#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */\n#define DFSDM_FLTISR_JOVRF_Pos          (2U)\n#define DFSDM_FLTISR_JOVRF_Msk          (0x1U << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */\n#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */\n#define DFSDM_FLTISR_REOCF_Pos          (1U)\n#define DFSDM_FLTISR_REOCF_Msk          (0x1U << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */\n#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */\n#define DFSDM_FLTISR_JEOCF_Pos          (0U)\n#define DFSDM_FLTISR_JEOCF_Msk          (0x1U << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */\n#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */\n\n/*****************  Bit definition for DFSDM_FLTICR register *******************/\n#define DFSDM_FLTICR_CLRSCSDF_Pos       (24U)\n#define DFSDM_FLTICR_CLRSCSDF_Msk       (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos)   /*!< 0xFF000000 */\n#define DFSDM_FLTICR_CLRSCSDF           DFSDM_FLTICR_CLRSCSDF_Msk              /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */\n#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)\n#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */\n#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */\n#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)\n#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1U << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */\n#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */\n#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)\n#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */\n#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */\n\n/****************  Bit definition for DFSDM_FLTJCHGR register ******************/\n#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)\n#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */\n#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */\n\n/*****************  Bit definition for DFSDM_FLTFCR register *******************/\n#define DFSDM_FLTFCR_FORD_Pos           (29U)\n#define DFSDM_FLTFCR_FORD_Msk           (0x7U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */\n#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */\n#define DFSDM_FLTFCR_FORD_2             (0x4U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */\n#define DFSDM_FLTFCR_FORD_1             (0x2U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */\n#define DFSDM_FLTFCR_FORD_0             (0x1U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */\n#define DFSDM_FLTFCR_FOSR_Pos           (16U)\n#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFU << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */\n#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */\n#define DFSDM_FLTFCR_IOSR_Pos           (0U)\n#define DFSDM_FLTFCR_IOSR_Msk           (0xFFU << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */\n#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */\n\n/***************  Bit definition for DFSDM_FLTJDATAR register *****************/\n#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)\n#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */\n#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)\n#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTRDATAR register *****************/\n#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)\n#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */\n#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)\n#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1U << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */\n#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */\n#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)\n#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */\n#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */\n\n/***************  Bit definition for DFSDM_FLTAWHTR register ******************/\n#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)\n#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */\n#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)\n#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWLTR register ******************/\n#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)\n#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */\n#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)\n#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */\n#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */\n\n/***************  Bit definition for DFSDM_FLTAWSR register *******************/\n#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)\n#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */\n#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */\n#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)\n#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */\n#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */\n\n/***************  Bit definition for DFSDM_FLTAWCFR register ******************/\n#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)\n#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */\n#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */\n#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)\n#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */\n#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */\n\n/***************  Bit definition for DFSDM_FLTEXMAX register ******************/\n#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)\n#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */\n#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)\n#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */\n\n/***************  Bit definition for DFSDM_FLTEXMIN register ******************/\n#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)\n#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */\n#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */\n#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)\n#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */\n#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */\n\n/***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/\n#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)\n#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */\n#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           DMA Controller (DMA)                             */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for DMA_ISR register  ********************/\n#define DMA_ISR_GIF1_Pos       (0U)\n#define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */\n#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */\n#define DMA_ISR_TCIF1_Pos      (1U)\n#define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */\n#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */\n#define DMA_ISR_HTIF1_Pos      (2U)\n#define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */\n#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */\n#define DMA_ISR_TEIF1_Pos      (3U)\n#define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */\n#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */\n#define DMA_ISR_GIF2_Pos       (4U)\n#define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */\n#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */\n#define DMA_ISR_TCIF2_Pos      (5U)\n#define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */\n#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */\n#define DMA_ISR_HTIF2_Pos      (6U)\n#define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */\n#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */\n#define DMA_ISR_TEIF2_Pos      (7U)\n#define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */\n#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */\n#define DMA_ISR_GIF3_Pos       (8U)\n#define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */\n#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */\n#define DMA_ISR_TCIF3_Pos      (9U)\n#define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */\n#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */\n#define DMA_ISR_HTIF3_Pos      (10U)\n#define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */\n#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */\n#define DMA_ISR_TEIF3_Pos      (11U)\n#define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */\n#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */\n#define DMA_ISR_GIF4_Pos       (12U)\n#define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */\n#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */\n#define DMA_ISR_TCIF4_Pos      (13U)\n#define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */\n#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */\n#define DMA_ISR_HTIF4_Pos      (14U)\n#define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */\n#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */\n#define DMA_ISR_TEIF4_Pos      (15U)\n#define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */\n#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */\n#define DMA_ISR_GIF5_Pos       (16U)\n#define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */\n#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */\n#define DMA_ISR_TCIF5_Pos      (17U)\n#define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */\n#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */\n#define DMA_ISR_HTIF5_Pos      (18U)\n#define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */\n#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */\n#define DMA_ISR_TEIF5_Pos      (19U)\n#define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */\n#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */\n#define DMA_ISR_GIF6_Pos       (20U)\n#define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */\n#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */\n#define DMA_ISR_TCIF6_Pos      (21U)\n#define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */\n#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */\n#define DMA_ISR_HTIF6_Pos      (22U)\n#define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */\n#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */\n#define DMA_ISR_TEIF6_Pos      (23U)\n#define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */\n#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */\n#define DMA_ISR_GIF7_Pos       (24U)\n#define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */\n#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */\n#define DMA_ISR_TCIF7_Pos      (25U)\n#define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */\n#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */\n#define DMA_ISR_HTIF7_Pos      (26U)\n#define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */\n#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */\n#define DMA_ISR_TEIF7_Pos      (27U)\n#define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */\n#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */\n\n/*******************  Bit definition for DMA_IFCR register  *******************/\n#define DMA_IFCR_CGIF1_Pos     (0U)\n#define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */\n#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */\n#define DMA_IFCR_CTCIF1_Pos    (1U)\n#define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */\n#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */\n#define DMA_IFCR_CHTIF1_Pos    (2U)\n#define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */\n#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */\n#define DMA_IFCR_CTEIF1_Pos    (3U)\n#define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */\n#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */\n#define DMA_IFCR_CGIF2_Pos     (4U)\n#define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */\n#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */\n#define DMA_IFCR_CTCIF2_Pos    (5U)\n#define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */\n#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */\n#define DMA_IFCR_CHTIF2_Pos    (6U)\n#define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */\n#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */\n#define DMA_IFCR_CTEIF2_Pos    (7U)\n#define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */\n#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */\n#define DMA_IFCR_CGIF3_Pos     (8U)\n#define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */\n#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */\n#define DMA_IFCR_CTCIF3_Pos    (9U)\n#define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */\n#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */\n#define DMA_IFCR_CHTIF3_Pos    (10U)\n#define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */\n#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */\n#define DMA_IFCR_CTEIF3_Pos    (11U)\n#define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */\n#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */\n#define DMA_IFCR_CGIF4_Pos     (12U)\n#define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */\n#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */\n#define DMA_IFCR_CTCIF4_Pos    (13U)\n#define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */\n#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */\n#define DMA_IFCR_CHTIF4_Pos    (14U)\n#define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */\n#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */\n#define DMA_IFCR_CTEIF4_Pos    (15U)\n#define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */\n#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */\n#define DMA_IFCR_CGIF5_Pos     (16U)\n#define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */\n#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */\n#define DMA_IFCR_CTCIF5_Pos    (17U)\n#define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */\n#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */\n#define DMA_IFCR_CHTIF5_Pos    (18U)\n#define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */\n#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */\n#define DMA_IFCR_CTEIF5_Pos    (19U)\n#define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */\n#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */\n#define DMA_IFCR_CGIF6_Pos     (20U)\n#define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */\n#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */\n#define DMA_IFCR_CTCIF6_Pos    (21U)\n#define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */\n#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */\n#define DMA_IFCR_CHTIF6_Pos    (22U)\n#define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */\n#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */\n#define DMA_IFCR_CTEIF6_Pos    (23U)\n#define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */\n#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */\n#define DMA_IFCR_CGIF7_Pos     (24U)\n#define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */\n#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */\n#define DMA_IFCR_CTCIF7_Pos    (25U)\n#define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */\n#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */\n#define DMA_IFCR_CHTIF7_Pos    (26U)\n#define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */\n#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */\n#define DMA_IFCR_CTEIF7_Pos    (27U)\n#define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */\n#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */\n\n/*******************  Bit definition for DMA_CCR register  ********************/\n#define DMA_CCR_EN_Pos         (0U)\n#define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */\n#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */\n#define DMA_CCR_TCIE_Pos       (1U)\n#define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */\n#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */\n#define DMA_CCR_HTIE_Pos       (2U)\n#define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */\n#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */\n#define DMA_CCR_TEIE_Pos       (3U)\n#define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */\n#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */\n#define DMA_CCR_DIR_Pos        (4U)\n#define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */\n#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */\n#define DMA_CCR_CIRC_Pos       (5U)\n#define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */\n#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */\n#define DMA_CCR_PINC_Pos       (6U)\n#define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */\n#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */\n#define DMA_CCR_MINC_Pos       (7U)\n#define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */\n#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */\n\n#define DMA_CCR_PSIZE_Pos      (8U)\n#define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */\n#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */\n#define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */\n#define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */\n\n#define DMA_CCR_MSIZE_Pos      (10U)\n#define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */\n#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */\n#define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */\n#define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */\n\n#define DMA_CCR_PL_Pos         (12U)\n#define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */\n#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/\n#define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */\n#define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */\n\n#define DMA_CCR_MEM2MEM_Pos    (14U)\n#define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */\n#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */\n\n/******************  Bit definition for DMA_CNDTR register  *******************/\n#define DMA_CNDTR_NDT_Pos      (0U)\n#define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */\n#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */\n\n/******************  Bit definition for DMA_CPAR register  ********************/\n#define DMA_CPAR_PA_Pos        (0U)\n#define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */\n#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */\n\n/******************  Bit definition for DMA_CMAR register  ********************/\n#define DMA_CMAR_MA_Pos        (0U)\n#define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */\n#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */\n\n\n/*******************  Bit definition for DMA_CSELR register  *******************/\n#define DMA_CSELR_C1S_Pos      (0U)\n#define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */\n#define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */\n#define DMA_CSELR_C2S_Pos      (4U)\n#define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */\n#define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */\n#define DMA_CSELR_C3S_Pos      (8U)\n#define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */\n#define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */\n#define DMA_CSELR_C4S_Pos      (12U)\n#define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */\n#define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */\n#define DMA_CSELR_C5S_Pos      (16U)\n#define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */\n#define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */\n#define DMA_CSELR_C6S_Pos      (20U)\n#define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */\n#define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */\n#define DMA_CSELR_C7S_Pos      (24U)\n#define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */\n#define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         AHB Master DMA2D Controller (DMA2D)                */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for DMA2D_CR register  ******************/\n\n#define DMA2D_CR_START_Pos         (0U)\n#define DMA2D_CR_START_Msk         (0x1U << DMA2D_CR_START_Pos)                /*!< 0x00000001 */\n#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */\n#define DMA2D_CR_SUSP_Pos          (1U)\n#define DMA2D_CR_SUSP_Msk          (0x1U << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */\n#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */\n#define DMA2D_CR_ABORT_Pos         (2U)\n#define DMA2D_CR_ABORT_Msk         (0x1U << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */\n#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */\n#define DMA2D_CR_TEIE_Pos          (8U)\n#define DMA2D_CR_TEIE_Msk          (0x1U << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */\n#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */\n#define DMA2D_CR_TCIE_Pos          (9U)\n#define DMA2D_CR_TCIE_Msk          (0x1U << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */\n#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */\n#define DMA2D_CR_TWIE_Pos          (10U)\n#define DMA2D_CR_TWIE_Msk          (0x1U << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */\n#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */\n#define DMA2D_CR_CAEIE_Pos         (11U)\n#define DMA2D_CR_CAEIE_Msk         (0x1U << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */\n#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */\n#define DMA2D_CR_CTCIE_Pos         (12U)\n#define DMA2D_CR_CTCIE_Msk         (0x1U << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */\n#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */\n#define DMA2D_CR_CEIE_Pos          (13U)\n#define DMA2D_CR_CEIE_Msk          (0x1U << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */\n#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */\n#define DMA2D_CR_MODE_Pos          (16U)\n#define DMA2D_CR_MODE_Msk          (0x3U << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */\n#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */\n#define DMA2D_CR_MODE_0            (0x1U << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */\n#define DMA2D_CR_MODE_1            (0x2U << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */\n\n/********************  Bit definition for DMA2D_ISR register  *****************/\n\n#define DMA2D_ISR_TEIF_Pos         (0U)\n#define DMA2D_ISR_TEIF_Msk         (0x1U << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */\n#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */\n#define DMA2D_ISR_TCIF_Pos         (1U)\n#define DMA2D_ISR_TCIF_Msk         (0x1U << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */\n#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */\n#define DMA2D_ISR_TWIF_Pos         (2U)\n#define DMA2D_ISR_TWIF_Msk         (0x1U << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */\n#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */\n#define DMA2D_ISR_CAEIF_Pos        (3U)\n#define DMA2D_ISR_CAEIF_Msk        (0x1U << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */\n#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */\n#define DMA2D_ISR_CTCIF_Pos        (4U)\n#define DMA2D_ISR_CTCIF_Msk        (0x1U << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */\n#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_ISR_CEIF_Pos         (5U)\n#define DMA2D_ISR_CEIF_Msk         (0x1U << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */\n#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */\n\n/********************  Bit definition for DMA2D_IFCR register  ****************/\n\n#define DMA2D_IFCR_CTEIF_Pos       (0U)\n#define DMA2D_IFCR_CTEIF_Msk       (0x1U << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */\n#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */\n#define DMA2D_IFCR_CTCIF_Pos       (1U)\n#define DMA2D_IFCR_CTCIF_Msk       (0x1U << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */\n#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */\n#define DMA2D_IFCR_CTWIF_Pos       (2U)\n#define DMA2D_IFCR_CTWIF_Msk       (0x1U << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */\n#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */\n#define DMA2D_IFCR_CAECIF_Pos      (3U)\n#define DMA2D_IFCR_CAECIF_Msk      (0x1U << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */\n#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */\n#define DMA2D_IFCR_CCTCIF_Pos      (4U)\n#define DMA2D_IFCR_CCTCIF_Msk      (0x1U << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */\n#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */\n#define DMA2D_IFCR_CCEIF_Pos       (5U)\n#define DMA2D_IFCR_CCEIF_Msk       (0x1U << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */\n#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */\n\n/********************  Bit definition for DMA2D_FGMAR register  ***************/\n\n#define DMA2D_FGMAR_MA_Pos         (0U)\n#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */\n#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_FGOR register  ****************/\n\n#define DMA2D_FGOR_LO_Pos          (0U)\n#define DMA2D_FGOR_LO_Msk          (0x3FFFU << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */\n#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_BGMAR register  ***************/\n\n#define DMA2D_BGMAR_MA_Pos         (0U)\n#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */\n#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_BGOR register  ****************/\n\n#define DMA2D_BGOR_LO_Pos          (0U)\n#define DMA2D_BGOR_LO_Msk          (0x3FFFU << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */\n#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_FGPFCCR register  *************/\n\n#define DMA2D_FGPFCCR_CM_Pos       (0U)\n#define DMA2D_FGPFCCR_CM_Msk       (0xFU << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */\n#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\n#define DMA2D_FGPFCCR_CM_0         (0x1U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_FGPFCCR_CM_1         (0x2U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_FGPFCCR_CM_2         (0x4U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_FGPFCCR_CM_3         (0x8U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */\n#define DMA2D_FGPFCCR_CCM_Pos      (4U)\n#define DMA2D_FGPFCCR_CCM_Msk      (0x1U << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */\n#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\n#define DMA2D_FGPFCCR_START_Pos    (5U)\n#define DMA2D_FGPFCCR_START_Msk    (0x1U << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */\n#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */\n#define DMA2D_FGPFCCR_CS_Pos       (8U)\n#define DMA2D_FGPFCCR_CS_Msk       (0xFFU << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */\n#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */\n#define DMA2D_FGPFCCR_AM_Pos       (16U)\n#define DMA2D_FGPFCCR_AM_Msk       (0x3U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */\n#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\n#define DMA2D_FGPFCCR_AM_0         (0x1U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */\n#define DMA2D_FGPFCCR_AM_1         (0x2U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */\n#define DMA2D_FGPFCCR_AI_Pos       (20U)\n#define DMA2D_FGPFCCR_AI_Msk       (0x1U << DMA2D_FGPFCCR_AI_Pos)              /*!< 0x00100000 */\n#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */\n#define DMA2D_FGPFCCR_RBS_Pos      (21U)\n#define DMA2D_FGPFCCR_RBS_Msk      (0x1U << DMA2D_FGPFCCR_RBS_Pos)             /*!< 0x00200000 */\n#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */\n#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)\n#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */\n#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */\n\n/********************  Bit definition for DMA2D_FGCOLR register  **************/\n\n#define DMA2D_FGCOLR_BLUE_Pos      (0U)\n#define DMA2D_FGCOLR_BLUE_Msk      (0xFFU << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */\n#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */\n#define DMA2D_FGCOLR_GREEN_Pos     (8U)\n#define DMA2D_FGCOLR_GREEN_Msk     (0xFFU << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */\n#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */\n#define DMA2D_FGCOLR_RED_Pos       (16U)\n#define DMA2D_FGCOLR_RED_Msk       (0xFFU << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */\n#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */\n\n/********************  Bit definition for DMA2D_BGPFCCR register  *************/\n\n#define DMA2D_BGPFCCR_CM_Pos       (0U)\n#define DMA2D_BGPFCCR_CM_Msk       (0xFU << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */\n#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */\n#define DMA2D_BGPFCCR_CM_0         (0x1U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */\n#define DMA2D_BGPFCCR_CM_1         (0x2U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */\n#define DMA2D_BGPFCCR_CM_2         (0x4U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */\n#define DMA2D_BGPFCCR_CM_3         (0x8U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */\n#define DMA2D_BGPFCCR_CCM_Pos      (4U)\n#define DMA2D_BGPFCCR_CCM_Msk      (0x1U << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */\n#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */\n#define DMA2D_BGPFCCR_START_Pos    (5U)\n#define DMA2D_BGPFCCR_START_Msk    (0x1U << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */\n#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */\n#define DMA2D_BGPFCCR_CS_Pos       (8U)\n#define DMA2D_BGPFCCR_CS_Msk       (0xFFU << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */\n#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */\n#define DMA2D_BGPFCCR_AM_Pos       (16U)\n#define DMA2D_BGPFCCR_AM_Msk       (0x3U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */\n#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */\n#define DMA2D_BGPFCCR_AM_0         (0x1U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */\n#define DMA2D_BGPFCCR_AM_1         (0x2U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */\n#define DMA2D_BGPFCCR_AI_Pos       (20U)\n#define DMA2D_BGPFCCR_AI_Msk       (0x1U << DMA2D_BGPFCCR_AI_Pos)              /*!< 0x00100000 */\n#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */\n#define DMA2D_BGPFCCR_RBS_Pos      (21U)\n#define DMA2D_BGPFCCR_RBS_Msk      (0x1U << DMA2D_BGPFCCR_RBS_Pos)             /*!< 0x00200000 */\n#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */\n#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)\n#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */\n#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */\n\n/********************  Bit definition for DMA2D_BGCOLR register  **************/\n\n#define DMA2D_BGCOLR_BLUE_Pos      (0U)\n#define DMA2D_BGCOLR_BLUE_Msk      (0xFFU << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */\n#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */\n#define DMA2D_BGCOLR_GREEN_Pos     (8U)\n#define DMA2D_BGCOLR_GREEN_Msk     (0xFFU << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */\n#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */\n#define DMA2D_BGCOLR_RED_Pos       (16U)\n#define DMA2D_BGCOLR_RED_Msk       (0xFFU << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */\n#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */\n\n/********************  Bit definition for DMA2D_FGCMAR register  **************/\n\n#define DMA2D_FGCMAR_MA_Pos        (0U)\n#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */\n#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_BGCMAR register  **************/\n\n#define DMA2D_BGCMAR_MA_Pos        (0U)\n#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */\n#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_OPFCCR register  **************/\n\n#define DMA2D_OPFCCR_CM_Pos        (0U)\n#define DMA2D_OPFCCR_CM_Msk        (0x7U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */\n#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */\n#define DMA2D_OPFCCR_CM_0          (0x1U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */\n#define DMA2D_OPFCCR_CM_1          (0x2U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */\n#define DMA2D_OPFCCR_CM_2          (0x4U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */\n#define DMA2D_OPFCCR_AI_Pos        (20U)\n#define DMA2D_OPFCCR_AI_Msk        (0x1U << DMA2D_OPFCCR_AI_Pos)               /*!< 0x00100000 */\n#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */\n#define DMA2D_OPFCCR_RBS_Pos       (21U)\n#define DMA2D_OPFCCR_RBS_Msk       (0x1U << DMA2D_OPFCCR_RBS_Pos)              /*!< 0x00200000 */\n#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */\n\n/********************  Bit definition for DMA2D_OCOLR register  ***************/\n\n/*!<Mode_ARGB8888/RGB888 */\n\n#define DMA2D_OCOLR_BLUE_1         (0x000000FFU)                               /*!< Blue Value */\n#define DMA2D_OCOLR_GREEN_1        (0x0000FF00U)                               /*!< Green Value  */\n#define DMA2D_OCOLR_RED_1          (0x00FF0000U)                               /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_1        (0xFF000000U)                               /*!< Alpha Channel Value */\n\n/*!<Mode_RGB565 */\n#define DMA2D_OCOLR_BLUE_2         (0x0000001FU)                               /*!< Blue Value */\n#define DMA2D_OCOLR_GREEN_2        (0x000007E0U)                               /*!< Green Value  */\n#define DMA2D_OCOLR_RED_2          (0x0000F800U)                               /*!< Red Value */\n\n/*!<Mode_ARGB1555 */\n#define DMA2D_OCOLR_BLUE_3         (0x0000001FU)                               /*!< Blue Value */\n#define DMA2D_OCOLR_GREEN_3        (0x000003E0U)                               /*!< Green Value  */\n#define DMA2D_OCOLR_RED_3          (0x00007C00U)                               /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_3        (0x00008000U)                               /*!< Alpha Channel Value */\n\n/*!<Mode_ARGB4444 */\n#define DMA2D_OCOLR_BLUE_4         (0x0000000FU)                               /*!< Blue Value */\n#define DMA2D_OCOLR_GREEN_4        (0x000000F0U)                               /*!< Green Value  */\n#define DMA2D_OCOLR_RED_4          (0x00000F00U)                               /*!< Red Value */\n#define DMA2D_OCOLR_ALPHA_4        (0x0000F000U)                               /*!< Alpha Channel Value */\n\n/********************  Bit definition for DMA2D_OMAR register  ****************/\n\n#define DMA2D_OMAR_MA_Pos          (0U)\n#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */\n#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */\n\n/********************  Bit definition for DMA2D_OOR register  *****************/\n\n#define DMA2D_OOR_LO_Pos           (0U)\n#define DMA2D_OOR_LO_Msk           (0x3FFFU << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */\n#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */\n\n/********************  Bit definition for DMA2D_NLR register  *****************/\n\n#define DMA2D_NLR_NL_Pos           (0U)\n#define DMA2D_NLR_NL_Msk           (0xFFFFU << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */\n#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */\n#define DMA2D_NLR_PL_Pos           (16U)\n#define DMA2D_NLR_PL_Msk           (0x3FFFU << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */\n#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */\n\n/********************  Bit definition for DMA2D_LWR register  *****************/\n\n#define DMA2D_LWR_LW_Pos           (0U)\n#define DMA2D_LWR_LW_Msk           (0xFFFFU << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */\n#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */\n\n/********************  Bit definition for DMA2D_AMTCR register  ***************/\n\n#define DMA2D_AMTCR_EN_Pos         (0U)\n#define DMA2D_AMTCR_EN_Msk         (0x1U << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */\n#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */\n#define DMA2D_AMTCR_DT_Pos         (8U)\n#define DMA2D_AMTCR_DT_Msk         (0xFFU << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */\n#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */\n\n\n/********************  Bit definition for DMA2D_FGCLUT register  **************/\n\n/********************  Bit definition for DMA2D_BGCLUT register  **************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR1 register  ******************/\n#define EXTI_IMR1_IM0_Pos        (0U)\n#define EXTI_IMR1_IM0_Msk        (0x1U << EXTI_IMR1_IM0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR1_IM1_Pos        (1U)\n#define EXTI_IMR1_IM1_Msk        (0x1U << EXTI_IMR1_IM1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR1_IM2_Pos        (2U)\n#define EXTI_IMR1_IM2_Msk        (0x1U << EXTI_IMR1_IM2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR1_IM3_Pos        (3U)\n#define EXTI_IMR1_IM3_Msk        (0x1U << EXTI_IMR1_IM3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR1_IM4_Pos        (4U)\n#define EXTI_IMR1_IM4_Msk        (0x1U << EXTI_IMR1_IM4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR1_IM5_Pos        (5U)\n#define EXTI_IMR1_IM5_Msk        (0x1U << EXTI_IMR1_IM5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR1_IM6_Pos        (6U)\n#define EXTI_IMR1_IM6_Msk        (0x1U << EXTI_IMR1_IM6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR1_IM7_Pos        (7U)\n#define EXTI_IMR1_IM7_Msk        (0x1U << EXTI_IMR1_IM7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR1_IM8_Pos        (8U)\n#define EXTI_IMR1_IM8_Msk        (0x1U << EXTI_IMR1_IM8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR1_IM9_Pos        (9U)\n#define EXTI_IMR1_IM9_Msk        (0x1U << EXTI_IMR1_IM9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR1_IM10_Pos       (10U)\n#define EXTI_IMR1_IM10_Msk       (0x1U << EXTI_IMR1_IM10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR1_IM11_Pos       (11U)\n#define EXTI_IMR1_IM11_Msk       (0x1U << EXTI_IMR1_IM11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR1_IM12_Pos       (12U)\n#define EXTI_IMR1_IM12_Msk       (0x1U << EXTI_IMR1_IM12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR1_IM13_Pos       (13U)\n#define EXTI_IMR1_IM13_Msk       (0x1U << EXTI_IMR1_IM13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR1_IM14_Pos       (14U)\n#define EXTI_IMR1_IM14_Msk       (0x1U << EXTI_IMR1_IM14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR1_IM15_Pos       (15U)\n#define EXTI_IMR1_IM15_Msk       (0x1U << EXTI_IMR1_IM15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR1_IM16_Pos       (16U)\n#define EXTI_IMR1_IM16_Msk       (0x1U << EXTI_IMR1_IM16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR1_IM17_Pos       (17U)\n#define EXTI_IMR1_IM17_Msk       (0x1U << EXTI_IMR1_IM17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR1_IM18_Pos       (18U)\n#define EXTI_IMR1_IM18_Msk       (0x1U << EXTI_IMR1_IM18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR1_IM19_Pos       (19U)\n#define EXTI_IMR1_IM19_Msk       (0x1U << EXTI_IMR1_IM19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR1_IM20_Pos       (20U)\n#define EXTI_IMR1_IM20_Msk       (0x1U << EXTI_IMR1_IM20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR1_IM21_Pos       (21U)\n#define EXTI_IMR1_IM21_Msk       (0x1U << EXTI_IMR1_IM21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR1_IM22_Pos       (22U)\n#define EXTI_IMR1_IM22_Msk       (0x1U << EXTI_IMR1_IM22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */\n#define EXTI_IMR1_IM23_Pos       (23U)\n#define EXTI_IMR1_IM23_Msk       (0x1U << EXTI_IMR1_IM23_Pos)                  /*!< 0x00800000 */\n#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */\n#define EXTI_IMR1_IM24_Pos       (24U)\n#define EXTI_IMR1_IM24_Msk       (0x1U << EXTI_IMR1_IM24_Pos)                  /*!< 0x01000000 */\n#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */\n#define EXTI_IMR1_IM25_Pos       (25U)\n#define EXTI_IMR1_IM25_Msk       (0x1U << EXTI_IMR1_IM25_Pos)                  /*!< 0x02000000 */\n#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */\n#define EXTI_IMR1_IM26_Pos       (26U)\n#define EXTI_IMR1_IM26_Msk       (0x1U << EXTI_IMR1_IM26_Pos)                  /*!< 0x04000000 */\n#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */\n#define EXTI_IMR1_IM27_Pos       (27U)\n#define EXTI_IMR1_IM27_Msk       (0x1U << EXTI_IMR1_IM27_Pos)                  /*!< 0x08000000 */\n#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */\n#define EXTI_IMR1_IM28_Pos       (28U)\n#define EXTI_IMR1_IM28_Msk       (0x1U << EXTI_IMR1_IM28_Pos)                  /*!< 0x10000000 */\n#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */\n#define EXTI_IMR1_IM29_Pos       (29U)\n#define EXTI_IMR1_IM29_Msk       (0x1U << EXTI_IMR1_IM29_Pos)                  /*!< 0x20000000 */\n#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */\n#define EXTI_IMR1_IM30_Pos       (30U)\n#define EXTI_IMR1_IM30_Msk       (0x1U << EXTI_IMR1_IM30_Pos)                  /*!< 0x40000000 */\n#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */\n#define EXTI_IMR1_IM31_Pos       (31U)\n#define EXTI_IMR1_IM31_Msk       (0x1U << EXTI_IMR1_IM31_Pos)                  /*!< 0x80000000 */\n#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */\n#define EXTI_IMR1_IM_Pos         (0U)\n#define EXTI_IMR1_IM_Msk         (0xFFFFFFFFU << EXTI_IMR1_IM_Pos)             /*!< 0xFFFFFFFF */\n#define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR1 register  ******************/\n#define EXTI_EMR1_EM0_Pos        (0U)\n#define EXTI_EMR1_EM0_Msk        (0x1U << EXTI_EMR1_EM0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR1_EM1_Pos        (1U)\n#define EXTI_EMR1_EM1_Msk        (0x1U << EXTI_EMR1_EM1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR1_EM2_Pos        (2U)\n#define EXTI_EMR1_EM2_Msk        (0x1U << EXTI_EMR1_EM2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR1_EM3_Pos        (3U)\n#define EXTI_EMR1_EM3_Msk        (0x1U << EXTI_EMR1_EM3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR1_EM4_Pos        (4U)\n#define EXTI_EMR1_EM4_Msk        (0x1U << EXTI_EMR1_EM4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR1_EM5_Pos        (5U)\n#define EXTI_EMR1_EM5_Msk        (0x1U << EXTI_EMR1_EM5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR1_EM6_Pos        (6U)\n#define EXTI_EMR1_EM6_Msk        (0x1U << EXTI_EMR1_EM6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR1_EM7_Pos        (7U)\n#define EXTI_EMR1_EM7_Msk        (0x1U << EXTI_EMR1_EM7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR1_EM8_Pos        (8U)\n#define EXTI_EMR1_EM8_Msk        (0x1U << EXTI_EMR1_EM8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR1_EM9_Pos        (9U)\n#define EXTI_EMR1_EM9_Msk        (0x1U << EXTI_EMR1_EM9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR1_EM10_Pos       (10U)\n#define EXTI_EMR1_EM10_Msk       (0x1U << EXTI_EMR1_EM10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR1_EM11_Pos       (11U)\n#define EXTI_EMR1_EM11_Msk       (0x1U << EXTI_EMR1_EM11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR1_EM12_Pos       (12U)\n#define EXTI_EMR1_EM12_Msk       (0x1U << EXTI_EMR1_EM12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR1_EM13_Pos       (13U)\n#define EXTI_EMR1_EM13_Msk       (0x1U << EXTI_EMR1_EM13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR1_EM14_Pos       (14U)\n#define EXTI_EMR1_EM14_Msk       (0x1U << EXTI_EMR1_EM14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR1_EM15_Pos       (15U)\n#define EXTI_EMR1_EM15_Msk       (0x1U << EXTI_EMR1_EM15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR1_EM16_Pos       (16U)\n#define EXTI_EMR1_EM16_Msk       (0x1U << EXTI_EMR1_EM16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR1_EM17_Pos       (17U)\n#define EXTI_EMR1_EM17_Msk       (0x1U << EXTI_EMR1_EM17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR1_EM18_Pos       (18U)\n#define EXTI_EMR1_EM18_Msk       (0x1U << EXTI_EMR1_EM18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR1_EM19_Pos       (19U)\n#define EXTI_EMR1_EM19_Msk       (0x1U << EXTI_EMR1_EM19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR1_EM20_Pos       (20U)\n#define EXTI_EMR1_EM20_Msk       (0x1U << EXTI_EMR1_EM20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR1_EM21_Pos       (21U)\n#define EXTI_EMR1_EM21_Msk       (0x1U << EXTI_EMR1_EM21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR1_EM22_Pos       (22U)\n#define EXTI_EMR1_EM22_Msk       (0x1U << EXTI_EMR1_EM22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */\n#define EXTI_EMR1_EM23_Pos       (23U)\n#define EXTI_EMR1_EM23_Msk       (0x1U << EXTI_EMR1_EM23_Pos)                  /*!< 0x00800000 */\n#define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */\n#define EXTI_EMR1_EM24_Pos       (24U)\n#define EXTI_EMR1_EM24_Msk       (0x1U << EXTI_EMR1_EM24_Pos)                  /*!< 0x01000000 */\n#define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */\n#define EXTI_EMR1_EM25_Pos       (25U)\n#define EXTI_EMR1_EM25_Msk       (0x1U << EXTI_EMR1_EM25_Pos)                  /*!< 0x02000000 */\n#define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */\n#define EXTI_EMR1_EM26_Pos       (26U)\n#define EXTI_EMR1_EM26_Msk       (0x1U << EXTI_EMR1_EM26_Pos)                  /*!< 0x04000000 */\n#define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */\n#define EXTI_EMR1_EM27_Pos       (27U)\n#define EXTI_EMR1_EM27_Msk       (0x1U << EXTI_EMR1_EM27_Pos)                  /*!< 0x08000000 */\n#define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */\n#define EXTI_EMR1_EM28_Pos       (28U)\n#define EXTI_EMR1_EM28_Msk       (0x1U << EXTI_EMR1_EM28_Pos)                  /*!< 0x10000000 */\n#define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */\n#define EXTI_EMR1_EM29_Pos       (29U)\n#define EXTI_EMR1_EM29_Msk       (0x1U << EXTI_EMR1_EM29_Pos)                  /*!< 0x20000000 */\n#define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */\n#define EXTI_EMR1_EM30_Pos       (30U)\n#define EXTI_EMR1_EM30_Msk       (0x1U << EXTI_EMR1_EM30_Pos)                  /*!< 0x40000000 */\n#define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */\n#define EXTI_EMR1_EM31_Pos       (31U)\n#define EXTI_EMR1_EM31_Msk       (0x1U << EXTI_EMR1_EM31_Pos)                  /*!< 0x80000000 */\n#define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */\n\n/******************  Bit definition for EXTI_RTSR1 register  ******************/\n#define EXTI_RTSR1_RT0_Pos       (0U)\n#define EXTI_RTSR1_RT0_Msk       (0x1U << EXTI_RTSR1_RT0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR1_RT1_Pos       (1U)\n#define EXTI_RTSR1_RT1_Msk       (0x1U << EXTI_RTSR1_RT1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR1_RT2_Pos       (2U)\n#define EXTI_RTSR1_RT2_Msk       (0x1U << EXTI_RTSR1_RT2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR1_RT3_Pos       (3U)\n#define EXTI_RTSR1_RT3_Msk       (0x1U << EXTI_RTSR1_RT3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR1_RT4_Pos       (4U)\n#define EXTI_RTSR1_RT4_Msk       (0x1U << EXTI_RTSR1_RT4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR1_RT5_Pos       (5U)\n#define EXTI_RTSR1_RT5_Msk       (0x1U << EXTI_RTSR1_RT5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR1_RT6_Pos       (6U)\n#define EXTI_RTSR1_RT6_Msk       (0x1U << EXTI_RTSR1_RT6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR1_RT7_Pos       (7U)\n#define EXTI_RTSR1_RT7_Msk       (0x1U << EXTI_RTSR1_RT7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR1_RT8_Pos       (8U)\n#define EXTI_RTSR1_RT8_Msk       (0x1U << EXTI_RTSR1_RT8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR1_RT9_Pos       (9U)\n#define EXTI_RTSR1_RT9_Msk       (0x1U << EXTI_RTSR1_RT9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR1_RT10_Pos      (10U)\n#define EXTI_RTSR1_RT10_Msk      (0x1U << EXTI_RTSR1_RT10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR1_RT11_Pos      (11U)\n#define EXTI_RTSR1_RT11_Msk      (0x1U << EXTI_RTSR1_RT11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR1_RT12_Pos      (12U)\n#define EXTI_RTSR1_RT12_Msk      (0x1U << EXTI_RTSR1_RT12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR1_RT13_Pos      (13U)\n#define EXTI_RTSR1_RT13_Msk      (0x1U << EXTI_RTSR1_RT13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR1_RT14_Pos      (14U)\n#define EXTI_RTSR1_RT14_Msk      (0x1U << EXTI_RTSR1_RT14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR1_RT15_Pos      (15U)\n#define EXTI_RTSR1_RT15_Msk      (0x1U << EXTI_RTSR1_RT15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR1_RT16_Pos      (16U)\n#define EXTI_RTSR1_RT16_Msk      (0x1U << EXTI_RTSR1_RT16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR1_RT18_Pos      (18U)\n#define EXTI_RTSR1_RT18_Msk      (0x1U << EXTI_RTSR1_RT18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR1_RT19_Pos      (19U)\n#define EXTI_RTSR1_RT19_Msk      (0x1U << EXTI_RTSR1_RT19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR1_RT20_Pos      (20U)\n#define EXTI_RTSR1_RT20_Msk      (0x1U << EXTI_RTSR1_RT20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR1_RT21_Pos      (21U)\n#define EXTI_RTSR1_RT21_Msk      (0x1U << EXTI_RTSR1_RT21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR1_RT22_Pos      (22U)\n#define EXTI_RTSR1_RT22_Msk      (0x1U << EXTI_RTSR1_RT22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR1 register  ******************/\n#define EXTI_FTSR1_FT0_Pos       (0U)\n#define EXTI_FTSR1_FT0_Msk       (0x1U << EXTI_FTSR1_FT0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR1_FT1_Pos       (1U)\n#define EXTI_FTSR1_FT1_Msk       (0x1U << EXTI_FTSR1_FT1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR1_FT2_Pos       (2U)\n#define EXTI_FTSR1_FT2_Msk       (0x1U << EXTI_FTSR1_FT2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR1_FT3_Pos       (3U)\n#define EXTI_FTSR1_FT3_Msk       (0x1U << EXTI_FTSR1_FT3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR1_FT4_Pos       (4U)\n#define EXTI_FTSR1_FT4_Msk       (0x1U << EXTI_FTSR1_FT4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR1_FT5_Pos       (5U)\n#define EXTI_FTSR1_FT5_Msk       (0x1U << EXTI_FTSR1_FT5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR1_FT6_Pos       (6U)\n#define EXTI_FTSR1_FT6_Msk       (0x1U << EXTI_FTSR1_FT6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR1_FT7_Pos       (7U)\n#define EXTI_FTSR1_FT7_Msk       (0x1U << EXTI_FTSR1_FT7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR1_FT8_Pos       (8U)\n#define EXTI_FTSR1_FT8_Msk       (0x1U << EXTI_FTSR1_FT8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR1_FT9_Pos       (9U)\n#define EXTI_FTSR1_FT9_Msk       (0x1U << EXTI_FTSR1_FT9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR1_FT10_Pos      (10U)\n#define EXTI_FTSR1_FT10_Msk      (0x1U << EXTI_FTSR1_FT10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR1_FT11_Pos      (11U)\n#define EXTI_FTSR1_FT11_Msk      (0x1U << EXTI_FTSR1_FT11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR1_FT12_Pos      (12U)\n#define EXTI_FTSR1_FT12_Msk      (0x1U << EXTI_FTSR1_FT12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR1_FT13_Pos      (13U)\n#define EXTI_FTSR1_FT13_Msk      (0x1U << EXTI_FTSR1_FT13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR1_FT14_Pos      (14U)\n#define EXTI_FTSR1_FT14_Msk      (0x1U << EXTI_FTSR1_FT14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR1_FT15_Pos      (15U)\n#define EXTI_FTSR1_FT15_Msk      (0x1U << EXTI_FTSR1_FT15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR1_FT16_Pos      (16U)\n#define EXTI_FTSR1_FT16_Msk      (0x1U << EXTI_FTSR1_FT16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR1_FT18_Pos      (18U)\n#define EXTI_FTSR1_FT18_Msk      (0x1U << EXTI_FTSR1_FT18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR1_FT19_Pos      (19U)\n#define EXTI_FTSR1_FT19_Msk      (0x1U << EXTI_FTSR1_FT19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR1_FT20_Pos      (20U)\n#define EXTI_FTSR1_FT20_Msk      (0x1U << EXTI_FTSR1_FT20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR1_FT21_Pos      (21U)\n#define EXTI_FTSR1_FT21_Msk      (0x1U << EXTI_FTSR1_FT21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR1_FT22_Pos      (22U)\n#define EXTI_FTSR1_FT22_Msk      (0x1U << EXTI_FTSR1_FT22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER1 register  *****************/\n#define EXTI_SWIER1_SWI0_Pos     (0U)\n#define EXTI_SWIER1_SWI0_Msk     (0x1U << EXTI_SWIER1_SWI0_Pos)                /*!< 0x00000001 */\n#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER1_SWI1_Pos     (1U)\n#define EXTI_SWIER1_SWI1_Msk     (0x1U << EXTI_SWIER1_SWI1_Pos)                /*!< 0x00000002 */\n#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER1_SWI2_Pos     (2U)\n#define EXTI_SWIER1_SWI2_Msk     (0x1U << EXTI_SWIER1_SWI2_Pos)                /*!< 0x00000004 */\n#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER1_SWI3_Pos     (3U)\n#define EXTI_SWIER1_SWI3_Msk     (0x1U << EXTI_SWIER1_SWI3_Pos)                /*!< 0x00000008 */\n#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER1_SWI4_Pos     (4U)\n#define EXTI_SWIER1_SWI4_Msk     (0x1U << EXTI_SWIER1_SWI4_Pos)                /*!< 0x00000010 */\n#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER1_SWI5_Pos     (5U)\n#define EXTI_SWIER1_SWI5_Msk     (0x1U << EXTI_SWIER1_SWI5_Pos)                /*!< 0x00000020 */\n#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER1_SWI6_Pos     (6U)\n#define EXTI_SWIER1_SWI6_Msk     (0x1U << EXTI_SWIER1_SWI6_Pos)                /*!< 0x00000040 */\n#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER1_SWI7_Pos     (7U)\n#define EXTI_SWIER1_SWI7_Msk     (0x1U << EXTI_SWIER1_SWI7_Pos)                /*!< 0x00000080 */\n#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER1_SWI8_Pos     (8U)\n#define EXTI_SWIER1_SWI8_Msk     (0x1U << EXTI_SWIER1_SWI8_Pos)                /*!< 0x00000100 */\n#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER1_SWI9_Pos     (9U)\n#define EXTI_SWIER1_SWI9_Msk     (0x1U << EXTI_SWIER1_SWI9_Pos)                /*!< 0x00000200 */\n#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER1_SWI10_Pos    (10U)\n#define EXTI_SWIER1_SWI10_Msk    (0x1U << EXTI_SWIER1_SWI10_Pos)               /*!< 0x00000400 */\n#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER1_SWI11_Pos    (11U)\n#define EXTI_SWIER1_SWI11_Msk    (0x1U << EXTI_SWIER1_SWI11_Pos)               /*!< 0x00000800 */\n#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER1_SWI12_Pos    (12U)\n#define EXTI_SWIER1_SWI12_Msk    (0x1U << EXTI_SWIER1_SWI12_Pos)               /*!< 0x00001000 */\n#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER1_SWI13_Pos    (13U)\n#define EXTI_SWIER1_SWI13_Msk    (0x1U << EXTI_SWIER1_SWI13_Pos)               /*!< 0x00002000 */\n#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER1_SWI14_Pos    (14U)\n#define EXTI_SWIER1_SWI14_Msk    (0x1U << EXTI_SWIER1_SWI14_Pos)               /*!< 0x00004000 */\n#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER1_SWI15_Pos    (15U)\n#define EXTI_SWIER1_SWI15_Msk    (0x1U << EXTI_SWIER1_SWI15_Pos)               /*!< 0x00008000 */\n#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER1_SWI16_Pos    (16U)\n#define EXTI_SWIER1_SWI16_Msk    (0x1U << EXTI_SWIER1_SWI16_Pos)               /*!< 0x00010000 */\n#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER1_SWI18_Pos    (18U)\n#define EXTI_SWIER1_SWI18_Msk    (0x1U << EXTI_SWIER1_SWI18_Pos)               /*!< 0x00040000 */\n#define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER1_SWI19_Pos    (19U)\n#define EXTI_SWIER1_SWI19_Msk    (0x1U << EXTI_SWIER1_SWI19_Pos)               /*!< 0x00080000 */\n#define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER1_SWI20_Pos    (20U)\n#define EXTI_SWIER1_SWI20_Msk    (0x1U << EXTI_SWIER1_SWI20_Pos)               /*!< 0x00100000 */\n#define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER1_SWI21_Pos    (21U)\n#define EXTI_SWIER1_SWI21_Msk    (0x1U << EXTI_SWIER1_SWI21_Pos)               /*!< 0x00200000 */\n#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER1_SWI22_Pos    (22U)\n#define EXTI_SWIER1_SWI22_Msk    (0x1U << EXTI_SWIER1_SWI22_Pos)               /*!< 0x00400000 */\n#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR1 register  *******************/\n#define EXTI_PR1_PIF0_Pos        (0U)\n#define EXTI_PR1_PIF0_Msk        (0x1U << EXTI_PR1_PIF0_Pos)                   /*!< 0x00000001 */\n#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */\n#define EXTI_PR1_PIF1_Pos        (1U)\n#define EXTI_PR1_PIF1_Msk        (0x1U << EXTI_PR1_PIF1_Pos)                   /*!< 0x00000002 */\n#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */\n#define EXTI_PR1_PIF2_Pos        (2U)\n#define EXTI_PR1_PIF2_Msk        (0x1U << EXTI_PR1_PIF2_Pos)                   /*!< 0x00000004 */\n#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */\n#define EXTI_PR1_PIF3_Pos        (3U)\n#define EXTI_PR1_PIF3_Msk        (0x1U << EXTI_PR1_PIF3_Pos)                   /*!< 0x00000008 */\n#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */\n#define EXTI_PR1_PIF4_Pos        (4U)\n#define EXTI_PR1_PIF4_Msk        (0x1U << EXTI_PR1_PIF4_Pos)                   /*!< 0x00000010 */\n#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */\n#define EXTI_PR1_PIF5_Pos        (5U)\n#define EXTI_PR1_PIF5_Msk        (0x1U << EXTI_PR1_PIF5_Pos)                   /*!< 0x00000020 */\n#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */\n#define EXTI_PR1_PIF6_Pos        (6U)\n#define EXTI_PR1_PIF6_Msk        (0x1U << EXTI_PR1_PIF6_Pos)                   /*!< 0x00000040 */\n#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */\n#define EXTI_PR1_PIF7_Pos        (7U)\n#define EXTI_PR1_PIF7_Msk        (0x1U << EXTI_PR1_PIF7_Pos)                   /*!< 0x00000080 */\n#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */\n#define EXTI_PR1_PIF8_Pos        (8U)\n#define EXTI_PR1_PIF8_Msk        (0x1U << EXTI_PR1_PIF8_Pos)                   /*!< 0x00000100 */\n#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */\n#define EXTI_PR1_PIF9_Pos        (9U)\n#define EXTI_PR1_PIF9_Msk        (0x1U << EXTI_PR1_PIF9_Pos)                   /*!< 0x00000200 */\n#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */\n#define EXTI_PR1_PIF10_Pos       (10U)\n#define EXTI_PR1_PIF10_Msk       (0x1U << EXTI_PR1_PIF10_Pos)                  /*!< 0x00000400 */\n#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */\n#define EXTI_PR1_PIF11_Pos       (11U)\n#define EXTI_PR1_PIF11_Msk       (0x1U << EXTI_PR1_PIF11_Pos)                  /*!< 0x00000800 */\n#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */\n#define EXTI_PR1_PIF12_Pos       (12U)\n#define EXTI_PR1_PIF12_Msk       (0x1U << EXTI_PR1_PIF12_Pos)                  /*!< 0x00001000 */\n#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */\n#define EXTI_PR1_PIF13_Pos       (13U)\n#define EXTI_PR1_PIF13_Msk       (0x1U << EXTI_PR1_PIF13_Pos)                  /*!< 0x00002000 */\n#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */\n#define EXTI_PR1_PIF14_Pos       (14U)\n#define EXTI_PR1_PIF14_Msk       (0x1U << EXTI_PR1_PIF14_Pos)                  /*!< 0x00004000 */\n#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */\n#define EXTI_PR1_PIF15_Pos       (15U)\n#define EXTI_PR1_PIF15_Msk       (0x1U << EXTI_PR1_PIF15_Pos)                  /*!< 0x00008000 */\n#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */\n#define EXTI_PR1_PIF16_Pos       (16U)\n#define EXTI_PR1_PIF16_Msk       (0x1U << EXTI_PR1_PIF16_Pos)                  /*!< 0x00010000 */\n#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */\n#define EXTI_PR1_PIF18_Pos       (18U)\n#define EXTI_PR1_PIF18_Msk       (0x1U << EXTI_PR1_PIF18_Pos)                  /*!< 0x00040000 */\n#define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */\n#define EXTI_PR1_PIF19_Pos       (19U)\n#define EXTI_PR1_PIF19_Msk       (0x1U << EXTI_PR1_PIF19_Pos)                  /*!< 0x00080000 */\n#define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */\n#define EXTI_PR1_PIF20_Pos       (20U)\n#define EXTI_PR1_PIF20_Msk       (0x1U << EXTI_PR1_PIF20_Pos)                  /*!< 0x00100000 */\n#define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */\n#define EXTI_PR1_PIF21_Pos       (21U)\n#define EXTI_PR1_PIF21_Msk       (0x1U << EXTI_PR1_PIF21_Pos)                  /*!< 0x00200000 */\n#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */\n#define EXTI_PR1_PIF22_Pos       (22U)\n#define EXTI_PR1_PIF22_Msk       (0x1U << EXTI_PR1_PIF22_Pos)                  /*!< 0x00400000 */\n#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */\n\n/*******************  Bit definition for EXTI_IMR2 register  ******************/\n#define EXTI_IMR2_IM32_Pos       (0U)\n#define EXTI_IMR2_IM32_Msk       (0x1U << EXTI_IMR2_IM32_Pos)                  /*!< 0x00000001 */\n#define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */\n#define EXTI_IMR2_IM33_Pos       (1U)\n#define EXTI_IMR2_IM33_Msk       (0x1U << EXTI_IMR2_IM33_Pos)                  /*!< 0x00000002 */\n#define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */\n#define EXTI_IMR2_IM34_Pos       (2U)\n#define EXTI_IMR2_IM34_Msk       (0x1U << EXTI_IMR2_IM34_Pos)                  /*!< 0x00000004 */\n#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */\n#define EXTI_IMR2_IM35_Pos       (3U)\n#define EXTI_IMR2_IM35_Msk       (0x1U << EXTI_IMR2_IM35_Pos)                  /*!< 0x00000008 */\n#define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */\n#define EXTI_IMR2_IM36_Pos       (4U)\n#define EXTI_IMR2_IM36_Msk       (0x1U << EXTI_IMR2_IM36_Pos)                  /*!< 0x00000010 */\n#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */\n#define EXTI_IMR2_IM37_Pos       (5U)\n#define EXTI_IMR2_IM37_Msk       (0x1U << EXTI_IMR2_IM37_Pos)                  /*!< 0x00000020 */\n#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */\n#define EXTI_IMR2_IM38_Pos       (6U)\n#define EXTI_IMR2_IM38_Msk       (0x1U << EXTI_IMR2_IM38_Pos)                  /*!< 0x00000040 */\n#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */\n#define EXTI_IMR2_IM39_Pos       (7U)\n#define EXTI_IMR2_IM39_Msk       (0x1U << EXTI_IMR2_IM39_Pos)                  /*!< 0x00000080 */\n#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */\n#define EXTI_IMR2_IM40_Pos       (8U)\n#define EXTI_IMR2_IM40_Msk       (0x1U << EXTI_IMR2_IM40_Pos)                  /*!< 0x00000100 */\n#define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */\n#define EXTI_IMR2_IM_Pos         (0U)\n#define EXTI_IMR2_IM_Msk         (0x1FFU << EXTI_IMR2_IM_Pos)                  /*!< 0x000001FF */\n#define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */\n\n/*******************  Bit definition for EXTI_EMR2 register  ******************/\n#define EXTI_EMR2_EM32_Pos       (0U)\n#define EXTI_EMR2_EM32_Msk       (0x1U << EXTI_EMR2_EM32_Pos)                  /*!< 0x00000001 */\n#define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */\n#define EXTI_EMR2_EM33_Pos       (1U)\n#define EXTI_EMR2_EM33_Msk       (0x1U << EXTI_EMR2_EM33_Pos)                  /*!< 0x00000002 */\n#define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */\n#define EXTI_EMR2_EM34_Pos       (2U)\n#define EXTI_EMR2_EM34_Msk       (0x1U << EXTI_EMR2_EM34_Pos)                  /*!< 0x00000004 */\n#define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */\n#define EXTI_EMR2_EM35_Pos       (3U)\n#define EXTI_EMR2_EM35_Msk       (0x1U << EXTI_EMR2_EM35_Pos)                  /*!< 0x00000008 */\n#define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */\n#define EXTI_EMR2_EM36_Pos       (4U)\n#define EXTI_EMR2_EM36_Msk       (0x1U << EXTI_EMR2_EM36_Pos)                  /*!< 0x00000010 */\n#define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */\n#define EXTI_EMR2_EM37_Pos       (5U)\n#define EXTI_EMR2_EM37_Msk       (0x1U << EXTI_EMR2_EM37_Pos)                  /*!< 0x00000020 */\n#define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */\n#define EXTI_EMR2_EM38_Pos       (6U)\n#define EXTI_EMR2_EM38_Msk       (0x1U << EXTI_EMR2_EM38_Pos)                  /*!< 0x00000040 */\n#define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */\n#define EXTI_EMR2_EM39_Pos       (7U)\n#define EXTI_EMR2_EM39_Msk       (0x1U << EXTI_EMR2_EM39_Pos)                  /*!< 0x00000080 */\n#define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */\n#define EXTI_EMR2_EM40_Pos       (8U)\n#define EXTI_EMR2_EM40_Msk       (0x1U << EXTI_EMR2_EM40_Pos)                  /*!< 0x00000100 */\n#define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< Event Mask on line 40 */\n#define EXTI_EMR2_EM_Pos         (0U)\n#define EXTI_EMR2_EM_Msk         (0x1FFU << EXTI_EMR2_EM_Pos)                  /*!< 0x000001FF */\n#define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */\n\n/******************  Bit definition for EXTI_RTSR2 register  ******************/\n#define EXTI_RTSR2_RT35_Pos      (3U)\n#define EXTI_RTSR2_RT35_Msk      (0x1U << EXTI_RTSR2_RT35_Pos)                 /*!< 0x00000008 */\n#define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */\n#define EXTI_RTSR2_RT36_Pos      (4U)\n#define EXTI_RTSR2_RT36_Msk      (0x1U << EXTI_RTSR2_RT36_Pos)                 /*!< 0x00000010 */\n#define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */\n#define EXTI_RTSR2_RT37_Pos      (5U)\n#define EXTI_RTSR2_RT37_Msk      (0x1U << EXTI_RTSR2_RT37_Pos)                 /*!< 0x00000020 */\n#define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */\n#define EXTI_RTSR2_RT38_Pos      (6U)\n#define EXTI_RTSR2_RT38_Msk      (0x1U << EXTI_RTSR2_RT38_Pos)                 /*!< 0x00000040 */\n#define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */\n\n/******************  Bit definition for EXTI_FTSR2 register  ******************/\n#define EXTI_FTSR2_FT35_Pos      (3U)\n#define EXTI_FTSR2_FT35_Msk      (0x1U << EXTI_FTSR2_FT35_Pos)                 /*!< 0x00000008 */\n#define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */\n#define EXTI_FTSR2_FT36_Pos      (4U)\n#define EXTI_FTSR2_FT36_Msk      (0x1U << EXTI_FTSR2_FT36_Pos)                 /*!< 0x00000010 */\n#define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */\n#define EXTI_FTSR2_FT37_Pos      (5U)\n#define EXTI_FTSR2_FT37_Msk      (0x1U << EXTI_FTSR2_FT37_Pos)                 /*!< 0x00000020 */\n#define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */\n#define EXTI_FTSR2_FT38_Pos      (6U)\n#define EXTI_FTSR2_FT38_Msk      (0x1U << EXTI_FTSR2_FT38_Pos)                 /*!< 0x00000040 */\n#define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */\n\n/******************  Bit definition for EXTI_SWIER2 register  *****************/\n#define EXTI_SWIER2_SWI35_Pos    (3U)\n#define EXTI_SWIER2_SWI35_Msk    (0x1U << EXTI_SWIER2_SWI35_Pos)               /*!< 0x00000008 */\n#define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */\n#define EXTI_SWIER2_SWI36_Pos    (4U)\n#define EXTI_SWIER2_SWI36_Msk    (0x1U << EXTI_SWIER2_SWI36_Pos)               /*!< 0x00000010 */\n#define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */\n#define EXTI_SWIER2_SWI37_Pos    (5U)\n#define EXTI_SWIER2_SWI37_Msk    (0x1U << EXTI_SWIER2_SWI37_Pos)               /*!< 0x00000020 */\n#define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */\n#define EXTI_SWIER2_SWI38_Pos    (6U)\n#define EXTI_SWIER2_SWI38_Msk    (0x1U << EXTI_SWIER2_SWI38_Pos)               /*!< 0x00000040 */\n#define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */\n\n/*******************  Bit definition for EXTI_PR2 register  *******************/\n#define EXTI_PR2_PIF35_Pos       (3U)\n#define EXTI_PR2_PIF35_Msk       (0x1U << EXTI_PR2_PIF35_Pos)                  /*!< 0x00000008 */\n#define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */\n#define EXTI_PR2_PIF36_Pos       (4U)\n#define EXTI_PR2_PIF36_Msk       (0x1U << EXTI_PR2_PIF36_Pos)                  /*!< 0x00000010 */\n#define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */\n#define EXTI_PR2_PIF37_Pos       (5U)\n#define EXTI_PR2_PIF37_Msk       (0x1U << EXTI_PR2_PIF37_Pos)                  /*!< 0x00000020 */\n#define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */\n#define EXTI_PR2_PIF38_Pos       (6U)\n#define EXTI_PR2_PIF38_Msk       (0x1U << EXTI_PR2_PIF38_Pos)                  /*!< 0x00000040 */\n#define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos             (0U)\n#define FLASH_ACR_LATENCY_Msk             (0x7U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000007 */\n#define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS             (0x00000000U)\n#define FLASH_ACR_LATENCY_1WS             (0x00000001U)\n#define FLASH_ACR_LATENCY_2WS             (0x00000002U)\n#define FLASH_ACR_LATENCY_3WS             (0x00000003U)\n#define FLASH_ACR_LATENCY_4WS             (0x00000004U)\n#define FLASH_ACR_PRFTEN_Pos              (8U)\n#define FLASH_ACR_PRFTEN_Msk              (0x1U << FLASH_ACR_PRFTEN_Pos)       /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk\n#define FLASH_ACR_ICEN_Pos                (9U)\n#define FLASH_ACR_ICEN_Msk                (0x1U << FLASH_ACR_ICEN_Pos)         /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk\n#define FLASH_ACR_DCEN_Pos                (10U)\n#define FLASH_ACR_DCEN_Msk                (0x1U << FLASH_ACR_DCEN_Pos)         /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk\n#define FLASH_ACR_ICRST_Pos               (11U)\n#define FLASH_ACR_ICRST_Msk               (0x1U << FLASH_ACR_ICRST_Pos)        /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk\n#define FLASH_ACR_DCRST_Pos               (12U)\n#define FLASH_ACR_DCRST_Msk               (0x1U << FLASH_ACR_DCRST_Pos)        /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk\n#define FLASH_ACR_RUN_PD_Pos              (13U)\n#define FLASH_ACR_RUN_PD_Msk              (0x1U << FLASH_ACR_RUN_PD_Pos)       /*!< 0x00002000 */\n#define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */\n#define FLASH_ACR_SLEEP_PD_Pos            (14U)\n#define FLASH_ACR_SLEEP_PD_Msk            (0x1U << FLASH_ACR_SLEEP_PD_Pos)     /*!< 0x00004000 */\n#define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */\n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos                  (0U)\n#define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000001 */\n#define FLASH_SR_EOP                      FLASH_SR_EOP_Msk\n#define FLASH_SR_OPERR_Pos                (1U)\n#define FLASH_SR_OPERR_Msk                (0x1U << FLASH_SR_OPERR_Pos)         /*!< 0x00000002 */\n#define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk\n#define FLASH_SR_PROGERR_Pos              (3U)\n#define FLASH_SR_PROGERR_Msk              (0x1U << FLASH_SR_PROGERR_Pos)       /*!< 0x00000008 */\n#define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk\n#define FLASH_SR_WRPERR_Pos               (4U)\n#define FLASH_SR_WRPERR_Msk               (0x1U << FLASH_SR_WRPERR_Pos)        /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk\n#define FLASH_SR_PGAERR_Pos               (5U)\n#define FLASH_SR_PGAERR_Msk               (0x1U << FLASH_SR_PGAERR_Pos)        /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk\n#define FLASH_SR_SIZERR_Pos               (6U)\n#define FLASH_SR_SIZERR_Msk               (0x1U << FLASH_SR_SIZERR_Pos)        /*!< 0x00000040 */\n#define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk\n#define FLASH_SR_PGSERR_Pos               (7U)\n#define FLASH_SR_PGSERR_Msk               (0x1U << FLASH_SR_PGSERR_Pos)        /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk\n#define FLASH_SR_MISERR_Pos               (8U)\n#define FLASH_SR_MISERR_Msk               (0x1U << FLASH_SR_MISERR_Pos)        /*!< 0x00000100 */\n#define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk\n#define FLASH_SR_FASTERR_Pos              (9U)\n#define FLASH_SR_FASTERR_Msk              (0x1U << FLASH_SR_FASTERR_Pos)       /*!< 0x00000200 */\n#define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk\n#define FLASH_SR_RDERR_Pos                (14U)\n#define FLASH_SR_RDERR_Msk                (0x1U << FLASH_SR_RDERR_Pos)         /*!< 0x00004000 */\n#define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk\n#define FLASH_SR_OPTVERR_Pos              (15U)\n#define FLASH_SR_OPTVERR_Msk              (0x1U << FLASH_SR_OPTVERR_Pos)       /*!< 0x00008000 */\n#define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk\n#define FLASH_SR_BSY_Pos                  (16U)\n#define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00010000 */\n#define FLASH_SR_BSY                      FLASH_SR_BSY_Msk\n#define FLASH_SR_PEMPTY_Pos               (17U)\n#define FLASH_SR_PEMPTY_Msk               (0x1U << FLASH_SR_PEMPTY_Pos)        /*!< 0x00020000 */\n#define FLASH_SR_PEMPTY                   FLASH_SR_PEMPTY_Msk\n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                   (0U)\n#define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */\n#define FLASH_CR_PG                       FLASH_CR_PG_Msk\n#define FLASH_CR_PER_Pos                  (1U)\n#define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */\n#define FLASH_CR_PER                      FLASH_CR_PER_Msk\n#define FLASH_CR_MER1_Pos                 (2U)\n#define FLASH_CR_MER1_Msk                 (0x1U << FLASH_CR_MER1_Pos)          /*!< 0x00000004 */\n#define FLASH_CR_MER1                     FLASH_CR_MER1_Msk\n#define FLASH_CR_PNB_Pos                  (3U)\n#define FLASH_CR_PNB_Msk                  (0xFFU << FLASH_CR_PNB_Pos)          /*!< 0x000007F8 */\n#define FLASH_CR_PNB                      FLASH_CR_PNB_Msk\n#define FLASH_CR_BKER_Pos                 (11U)\n#define FLASH_CR_BKER_Msk                 (0x1U << FLASH_CR_BKER_Pos)          /*!< 0x00000800 */\n#define FLASH_CR_BKER                     FLASH_CR_BKER_Msk\n#define FLASH_CR_MER2_Pos                 (15U)\n#define FLASH_CR_MER2_Msk                 (0x1U << FLASH_CR_MER2_Pos)          /*!< 0x00008000 */\n#define FLASH_CR_MER2                     FLASH_CR_MER2_Msk\n#define FLASH_CR_STRT_Pos                 (16U)\n#define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00010000 */\n#define FLASH_CR_STRT                     FLASH_CR_STRT_Msk\n#define FLASH_CR_OPTSTRT_Pos              (17U)\n#define FLASH_CR_OPTSTRT_Msk              (0x1U << FLASH_CR_OPTSTRT_Pos)       /*!< 0x00020000 */\n#define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk\n#define FLASH_CR_FSTPG_Pos                (18U)\n#define FLASH_CR_FSTPG_Msk                (0x1U << FLASH_CR_FSTPG_Pos)         /*!< 0x00040000 */\n#define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk\n#define FLASH_CR_EOPIE_Pos                (24U)\n#define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk\n#define FLASH_CR_ERRIE_Pos                (25U)\n#define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x02000000 */\n#define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk\n#define FLASH_CR_RDERRIE_Pos              (26U)\n#define FLASH_CR_RDERRIE_Msk              (0x1U << FLASH_CR_RDERRIE_Pos)       /*!< 0x04000000 */\n#define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk\n#define FLASH_CR_OBL_LAUNCH_Pos           (27U)\n#define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */\n#define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk\n#define FLASH_CR_OPTLOCK_Pos              (30U)\n#define FLASH_CR_OPTLOCK_Msk              (0x1U << FLASH_CR_OPTLOCK_Pos)       /*!< 0x40000000 */\n#define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk\n#define FLASH_CR_LOCK_Pos                 (31U)\n#define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x80000000 */\n#define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk\n\n/*******************  Bits definition for FLASH_ECCR register  ***************/\n#define FLASH_ECCR_ADDR_ECC_Pos           (0U)\n#define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */\n#define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk\n#define FLASH_ECCR_BK_ECC_Pos             (19U)\n#define FLASH_ECCR_BK_ECC_Msk             (0x1U << FLASH_ECCR_BK_ECC_Pos)      /*!< 0x00080000 */\n#define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk\n#define FLASH_ECCR_SYSF_ECC_Pos           (20U)\n#define FLASH_ECCR_SYSF_ECC_Msk           (0x1U << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */\n#define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk\n#define FLASH_ECCR_ECCIE_Pos              (24U)\n#define FLASH_ECCR_ECCIE_Msk              (0x1U << FLASH_ECCR_ECCIE_Pos)       /*!< 0x01000000 */\n#define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk\n#define FLASH_ECCR_ECCC_Pos               (30U)\n#define FLASH_ECCR_ECCC_Msk               (0x1U << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */\n#define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk\n#define FLASH_ECCR_ECCD_Pos               (31U)\n#define FLASH_ECCR_ECCD_Msk               (0x1U << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */\n#define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk\n\n/*******************  Bits definition for FLASH_OPTR register  ***************/\n#define FLASH_OPTR_RDP_Pos                (0U)\n#define FLASH_OPTR_RDP_Msk                (0xFFU << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */\n#define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk\n#define FLASH_OPTR_BOR_LEV_Pos            (8U)\n#define FLASH_OPTR_BOR_LEV_Msk            (0x7U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000700 */\n#define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk\n#define FLASH_OPTR_BOR_LEV_0              (0x0U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000000 */\n#define FLASH_OPTR_BOR_LEV_1              (0x1U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000100 */\n#define FLASH_OPTR_BOR_LEV_2              (0x2U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000200 */\n#define FLASH_OPTR_BOR_LEV_3              (0x3U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000300 */\n#define FLASH_OPTR_BOR_LEV_4              (0x4U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000400 */\n#define FLASH_OPTR_nRST_STOP_Pos          (12U)\n#define FLASH_OPTR_nRST_STOP_Msk          (0x1U << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00001000 */\n#define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk\n#define FLASH_OPTR_nRST_STDBY_Pos         (13U)\n#define FLASH_OPTR_nRST_STDBY_Msk         (0x1U << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00002000 */\n#define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk\n#define FLASH_OPTR_nRST_SHDW_Pos          (14U)\n#define FLASH_OPTR_nRST_SHDW_Msk          (0x1U << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00004000 */\n#define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk\n#define FLASH_OPTR_IWDG_SW_Pos            (16U)\n#define FLASH_OPTR_IWDG_SW_Msk            (0x1U << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */\n#define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk\n#define FLASH_OPTR_IWDG_STOP_Pos          (17U)\n#define FLASH_OPTR_IWDG_STOP_Msk          (0x1U << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */\n#define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk\n#define FLASH_OPTR_IWDG_STDBY_Pos         (18U)\n#define FLASH_OPTR_IWDG_STDBY_Msk         (0x1U << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */\n#define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk\n#define FLASH_OPTR_WWDG_SW_Pos            (19U)\n#define FLASH_OPTR_WWDG_SW_Msk            (0x1U << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */\n#define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk\n#define FLASH_OPTR_BFB2_Pos               (20U)\n#define FLASH_OPTR_BFB2_Msk               (0x1U << FLASH_OPTR_BFB2_Pos)        /*!< 0x00100000 */\n#define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk\n#define FLASH_OPTR_DUALBANK_Pos           (21U)\n#define FLASH_OPTR_DUALBANK_Msk           (0x1U << FLASH_OPTR_DUALBANK_Pos)    /*!< 0x00200000 */\n#define FLASH_OPTR_DUALBANK               FLASH_OPTR_DUALBANK_Msk\n#define FLASH_OPTR_nBOOT1_Pos             (23U)\n#define FLASH_OPTR_nBOOT1_Msk             (0x1U << FLASH_OPTR_nBOOT1_Pos)      /*!< 0x00800000 */\n#define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk\n#define FLASH_OPTR_SRAM2_PE_Pos           (24U)\n#define FLASH_OPTR_SRAM2_PE_Msk           (0x1U << FLASH_OPTR_SRAM2_PE_Pos)    /*!< 0x01000000 */\n#define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk\n#define FLASH_OPTR_SRAM2_RST_Pos          (25U)\n#define FLASH_OPTR_SRAM2_RST_Msk          (0x1U << FLASH_OPTR_SRAM2_RST_Pos)   /*!< 0x02000000 */\n#define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk\n#define FLASH_OPTR_nSWBOOT0_Pos           (26U)\n#define FLASH_OPTR_nSWBOOT0_Msk           (0x1U << FLASH_OPTR_nSWBOOT0_Pos)    /*!< 0x04000000 */\n#define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk\n#define FLASH_OPTR_nBOOT0_Pos             (27U)\n#define FLASH_OPTR_nBOOT0_Msk             (0x1U << FLASH_OPTR_nBOOT0_Pos)      /*!< 0x08000000 */\n#define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk\n\n/******************  Bits definition for FLASH_PCROP1SR register  **********/\n#define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)\n#define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */\n#define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk\n\n/******************  Bits definition for FLASH_PCROP1ER register  ***********/\n#define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)\n#define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */\n#define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk\n#define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)\n#define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */\n#define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk\n\n/******************  Bits definition for FLASH_WRP1AR register  ***************/\n#define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)\n#define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */\n#define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk\n#define FLASH_WRP1AR_WRP1A_END_Pos        (16U)\n#define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */\n#define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk\n\n/******************  Bits definition for FLASH_WRPB1R register  ***************/\n#define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)\n#define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */\n#define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk\n#define FLASH_WRP1BR_WRP1B_END_Pos        (16U)\n#define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */\n#define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk\n\n/******************  Bits definition for FLASH_PCROP2SR register  **********/\n#define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)\n#define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */\n#define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk\n\n/******************  Bits definition for FLASH_PCROP2ER register  ***********/\n#define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)\n#define FLASH_PCROP2ER_PCROP2_END_Msk     (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */\n#define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk\n\n/******************  Bits definition for FLASH_WRP2AR register  ***************/\n#define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)\n#define FLASH_WRP2AR_WRP2A_STRT_Msk       (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */\n#define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk\n#define FLASH_WRP2AR_WRP2A_END_Pos        (16U)\n#define FLASH_WRP2AR_WRP2A_END_Msk        (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */\n#define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk\n\n/******************  Bits definition for FLASH_WRP2BR register  ***************/\n#define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)\n#define FLASH_WRP2BR_WRP2B_STRT_Msk       (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */\n#define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk\n#define FLASH_WRP2BR_WRP2B_END_Pos        (16U)\n#define FLASH_WRP2BR_WRP2B_END_Msk        (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */\n#define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Flexible Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FMC_BCR1 register  *******************/\n#define FMC_BCR1_CCLKEN_Pos        (20U)\n#define FMC_BCR1_CCLKEN_Msk        (0x1U << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */\n#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */\n#define FMC_BCR1_WFDIS_Pos         (21U)\n#define FMC_BCR1_WFDIS_Msk         (0x1U << FMC_BCR1_WFDIS_Pos)                /*!< 0x00200000 */\n#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */\n\n/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/\n#define FMC_BCRx_MBKEN_Pos         (0U)\n#define FMC_BCRx_MBKEN_Msk         (0x1U << FMC_BCRx_MBKEN_Pos)                /*!< 0x00000001 */\n#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */\n#define FMC_BCRx_MUXEN_Pos         (1U)\n#define FMC_BCRx_MUXEN_Msk         (0x1U << FMC_BCRx_MUXEN_Pos)                /*!< 0x00000002 */\n#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */\n\n#define FMC_BCRx_MTYP_Pos          (2U)\n#define FMC_BCRx_MTYP_Msk          (0x3U << FMC_BCRx_MTYP_Pos)                 /*!< 0x0000000C */\n#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */\n#define FMC_BCRx_MTYP_0            (0x1U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */\n#define FMC_BCRx_MTYP_1            (0x2U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */\n\n#define FMC_BCRx_MWID_Pos          (4U)\n#define FMC_BCRx_MWID_Msk          (0x3U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000030 */\n#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */\n#define FMC_BCRx_MWID_0            (0x1U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */\n#define FMC_BCRx_MWID_1            (0x2U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */\n\n#define FMC_BCRx_FACCEN_Pos        (6U)\n#define FMC_BCRx_FACCEN_Msk        (0x1U << FMC_BCRx_FACCEN_Pos)               /*!< 0x00000040 */\n#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */\n#define FMC_BCRx_BURSTEN_Pos       (8U)\n#define FMC_BCRx_BURSTEN_Msk       (0x1U << FMC_BCRx_BURSTEN_Pos)              /*!< 0x00000100 */\n#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */\n#define FMC_BCRx_WAITPOL_Pos       (9U)\n#define FMC_BCRx_WAITPOL_Msk       (0x1U << FMC_BCRx_WAITPOL_Pos)              /*!< 0x00000200 */\n#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */\n#define FMC_BCRx_WAITCFG_Pos       (11U)\n#define FMC_BCRx_WAITCFG_Msk       (0x1U << FMC_BCRx_WAITCFG_Pos)              /*!< 0x00000800 */\n#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */\n#define FMC_BCRx_WREN_Pos          (12U)\n#define FMC_BCRx_WREN_Msk          (0x1U << FMC_BCRx_WREN_Pos)                 /*!< 0x00001000 */\n#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */\n#define FMC_BCRx_WAITEN_Pos        (13U)\n#define FMC_BCRx_WAITEN_Msk        (0x1U << FMC_BCRx_WAITEN_Pos)               /*!< 0x00002000 */\n#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */\n#define FMC_BCRx_EXTMOD_Pos        (14U)\n#define FMC_BCRx_EXTMOD_Msk        (0x1U << FMC_BCRx_EXTMOD_Pos)               /*!< 0x00004000 */\n#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */\n#define FMC_BCRx_ASYNCWAIT_Pos     (15U)\n#define FMC_BCRx_ASYNCWAIT_Msk     (0x1U << FMC_BCRx_ASYNCWAIT_Pos)            /*!< 0x00008000 */\n#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */\n\n#define FMC_BCRx_CPSIZE_Pos        (16U)\n#define FMC_BCRx_CPSIZE_Msk        (0x7U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00070000 */\n#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */\n#define FMC_BCRx_CPSIZE_0          (0x1U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */\n#define FMC_BCRx_CPSIZE_1          (0x2U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */\n#define FMC_BCRx_CPSIZE_2          (0x4U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */\n\n#define FMC_BCRx_CBURSTRW_Pos      (19U)\n#define FMC_BCRx_CBURSTRW_Msk      (0x1U << FMC_BCRx_CBURSTRW_Pos)             /*!< 0x00080000 */\n#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */\n\n/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/\n#define FMC_BTRx_ADDSET_Pos        (0U)\n#define FMC_BTRx_ADDSET_Msk        (0xFU << FMC_BTRx_ADDSET_Pos)               /*!< 0x0000000F */\n#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BTRx_ADDSET_0          (0x1U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */\n#define FMC_BTRx_ADDSET_1          (0x2U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */\n#define FMC_BTRx_ADDSET_2          (0x4U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */\n#define FMC_BTRx_ADDSET_3          (0x8U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */\n\n#define FMC_BTRx_ADDHLD_Pos        (4U)\n#define FMC_BTRx_ADDHLD_Msk        (0xFU << FMC_BTRx_ADDHLD_Pos)               /*!< 0x000000F0 */\n#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\n#define FMC_BTRx_ADDHLD_0          (0x1U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */\n#define FMC_BTRx_ADDHLD_1          (0x2U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */\n#define FMC_BTRx_ADDHLD_2          (0x4U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */\n#define FMC_BTRx_ADDHLD_3          (0x8U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */\n\n#define FMC_BTRx_DATAST_Pos        (8U)\n#define FMC_BTRx_DATAST_Msk        (0xFFU << FMC_BTRx_DATAST_Pos)              /*!< 0x0000FF00 */\n#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BTRx_DATAST_0          (0x01U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */\n#define FMC_BTRx_DATAST_1          (0x02U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */\n#define FMC_BTRx_DATAST_2          (0x04U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */\n#define FMC_BTRx_DATAST_3          (0x08U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */\n#define FMC_BTRx_DATAST_4          (0x10U << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */\n#define FMC_BTRx_DATAST_5          (0x20U << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */\n#define FMC_BTRx_DATAST_6          (0x40U << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */\n#define FMC_BTRx_DATAST_7          (0x80U << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */\n\n#define FMC_BTRx_BUSTURN_Pos       (16U)\n#define FMC_BTRx_BUSTURN_Msk       (0xFU << FMC_BTRx_BUSTURN_Pos)              /*!< 0x000F0000 */\n#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BTRx_BUSTURN_0         (0x1U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */\n#define FMC_BTRx_BUSTURN_1         (0x2U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */\n#define FMC_BTRx_BUSTURN_2         (0x4U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */\n#define FMC_BTRx_BUSTURN_3         (0x8U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */\n\n#define FMC_BTRx_CLKDIV_Pos        (20U)\n#define FMC_BTRx_CLKDIV_Msk        (0xFU << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00F00000 */\n#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FMC_BTRx_CLKDIV_0          (0x1U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */\n#define FMC_BTRx_CLKDIV_1          (0x2U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */\n#define FMC_BTRx_CLKDIV_2          (0x4U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */\n#define FMC_BTRx_CLKDIV_3          (0x8U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */\n\n#define FMC_BTRx_DATLAT_Pos        (24U)\n#define FMC_BTRx_DATLAT_Msk        (0xFU << FMC_BTRx_DATLAT_Pos)               /*!< 0x0F000000 */\n#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */\n#define FMC_BTRx_DATLAT_0          (0x1U << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */\n#define FMC_BTRx_DATLAT_1          (0x2U << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */\n#define FMC_BTRx_DATLAT_2          (0x4U << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */\n#define FMC_BTRx_DATLAT_3          (0x8U << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */\n\n#define FMC_BTRx_ACCMOD_Pos        (28U)\n#define FMC_BTRx_ACCMOD_Msk        (0x3U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x30000000 */\n#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BTRx_ACCMOD_0          (0x1U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */\n#define FMC_BTRx_ACCMOD_1          (0x2U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/\n#define FMC_BWTRx_ADDSET_Pos       (0U)\n#define FMC_BWTRx_ADDSET_Msk       (0xFU << FMC_BWTRx_ADDSET_Pos)              /*!< 0x0000000F */\n#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FMC_BWTRx_ADDSET_0         (0x1U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */\n#define FMC_BWTRx_ADDSET_1         (0x2U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */\n#define FMC_BWTRx_ADDSET_2         (0x4U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */\n#define FMC_BWTRx_ADDSET_3         (0x8U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */\n\n#define FMC_BWTRx_ADDHLD_Pos       (4U)\n#define FMC_BWTRx_ADDHLD_Msk       (0xFU << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x000000F0 */\n#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FMC_BWTRx_ADDHLD_0         (0x1U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */\n#define FMC_BWTRx_ADDHLD_1         (0x2U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */\n#define FMC_BWTRx_ADDHLD_2         (0x4U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */\n#define FMC_BWTRx_ADDHLD_3         (0x8U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */\n\n#define FMC_BWTRx_DATAST_Pos       (8U)\n#define FMC_BWTRx_DATAST_Msk       (0xFFU << FMC_BWTRx_DATAST_Pos)             /*!< 0x0000FF00 */\n#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FMC_BWTRx_DATAST_0         (0x01U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */\n#define FMC_BWTRx_DATAST_1         (0x02U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */\n#define FMC_BWTRx_DATAST_2         (0x04U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */\n#define FMC_BWTRx_DATAST_3         (0x08U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */\n#define FMC_BWTRx_DATAST_4         (0x10U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */\n#define FMC_BWTRx_DATAST_5         (0x20U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */\n#define FMC_BWTRx_DATAST_6         (0x40U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */\n#define FMC_BWTRx_DATAST_7         (0x80U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */\n\n#define FMC_BWTRx_BUSTURN_Pos      (16U)\n#define FMC_BWTRx_BUSTURN_Msk      (0xFU << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x000F0000 */\n#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FMC_BWTRx_BUSTURN_0        (0x1U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */\n#define FMC_BWTRx_BUSTURN_1        (0x2U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */\n#define FMC_BWTRx_BUSTURN_2        (0x4U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */\n#define FMC_BWTRx_BUSTURN_3        (0x8U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */\n\n#define FMC_BWTRx_ACCMOD_Pos       (28U)\n#define FMC_BWTRx_ACCMOD_Msk       (0x3U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x30000000 */\n#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */\n#define FMC_BWTRx_ACCMOD_0         (0x1U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */\n#define FMC_BWTRx_ACCMOD_1         (0x2U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */\n\n/******************  Bit definition for FMC_PCR register  ********************/\n#define FMC_PCR_PWAITEN_Pos        (1U)\n#define FMC_PCR_PWAITEN_Msk        (0x1U << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */\n#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */\n#define FMC_PCR_PBKEN_Pos          (2U)\n#define FMC_PCR_PBKEN_Msk          (0x1U << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */\n#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */\n#define FMC_PCR_PTYP_Pos           (3U)\n#define FMC_PCR_PTYP_Msk           (0x1U << FMC_PCR_PTYP_Pos)                  /*!< 0x00000008 */\n#define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */\n\n#define FMC_PCR_PWID_Pos           (4U)\n#define FMC_PCR_PWID_Msk           (0x3U << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */\n#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FMC_PCR_PWID_0             (0x1U << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */\n#define FMC_PCR_PWID_1             (0x2U << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */\n\n#define FMC_PCR_ECCEN_Pos          (6U)\n#define FMC_PCR_ECCEN_Msk          (0x1U << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */\n#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */\n\n#define FMC_PCR_TCLR_Pos           (9U)\n#define FMC_PCR_TCLR_Msk           (0xFU << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */\n#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */\n#define FMC_PCR_TCLR_0             (0x1U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */\n#define FMC_PCR_TCLR_1             (0x2U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */\n#define FMC_PCR_TCLR_2             (0x4U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */\n#define FMC_PCR_TCLR_3             (0x8U << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */\n\n#define FMC_PCR_TAR_Pos            (13U)\n#define FMC_PCR_TAR_Msk            (0xFU << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */\n#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */\n#define FMC_PCR_TAR_0              (0x1U << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */\n#define FMC_PCR_TAR_1              (0x2U << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */\n#define FMC_PCR_TAR_2              (0x4U << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */\n#define FMC_PCR_TAR_3              (0x8U << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */\n\n#define FMC_PCR_ECCPS_Pos          (17U)\n#define FMC_PCR_ECCPS_Msk          (0x7U << FMC_PCR_ECCPS_Pos)                 /*!< 0x000E0000 */\n#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */\n#define FMC_PCR_ECCPS_0            (0x1U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */\n#define FMC_PCR_ECCPS_1            (0x2U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */\n#define FMC_PCR_ECCPS_2            (0x4U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */\n\n/*******************  Bit definition for FMC_SR register  ********************/\n#define FMC_SR_IRS_Pos             (0U)\n#define FMC_SR_IRS_Msk             (0x1U << FMC_SR_IRS_Pos)                    /*!< 0x00000001 */\n#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */\n#define FMC_SR_ILS_Pos             (1U)\n#define FMC_SR_ILS_Msk             (0x1U << FMC_SR_ILS_Pos)                    /*!< 0x00000002 */\n#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */\n#define FMC_SR_IFS_Pos             (2U)\n#define FMC_SR_IFS_Msk             (0x1U << FMC_SR_IFS_Pos)                    /*!< 0x00000004 */\n#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */\n#define FMC_SR_IREN_Pos            (3U)\n#define FMC_SR_IREN_Msk            (0x1U << FMC_SR_IREN_Pos)                   /*!< 0x00000008 */\n#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */\n#define FMC_SR_ILEN_Pos            (4U)\n#define FMC_SR_ILEN_Msk            (0x1U << FMC_SR_ILEN_Pos)                   /*!< 0x00000010 */\n#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */\n#define FMC_SR_IFEN_Pos            (5U)\n#define FMC_SR_IFEN_Msk            (0x1U << FMC_SR_IFEN_Pos)                   /*!< 0x00000020 */\n#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */\n#define FMC_SR_FEMPT_Pos           (6U)\n#define FMC_SR_FEMPT_Msk           (0x1U << FMC_SR_FEMPT_Pos)                  /*!< 0x00000040 */\n#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */\n\n/******************  Bit definition for FMC_PMEM register  ******************/\n#define FMC_PMEM_MEMSET_Pos        (0U)\n#define FMC_PMEM_MEMSET_Msk        (0xFFU << FMC_PMEM_MEMSET_Pos)              /*!< 0x000000FF */\n#define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */\n#define FMC_PMEM_MEMSET_0          (0x01U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000001 */\n#define FMC_PMEM_MEMSET_1          (0x02U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000002 */\n#define FMC_PMEM_MEMSET_2          (0x04U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000004 */\n#define FMC_PMEM_MEMSET_3          (0x08U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000008 */\n#define FMC_PMEM_MEMSET_4          (0x10U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000010 */\n#define FMC_PMEM_MEMSET_5          (0x20U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000020 */\n#define FMC_PMEM_MEMSET_6          (0x40U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000040 */\n#define FMC_PMEM_MEMSET_7          (0x80U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000080 */\n\n#define FMC_PMEM_MEMWAIT_Pos       (8U)\n#define FMC_PMEM_MEMWAIT_Msk       (0xFFU << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x0000FF00 */\n#define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */\n#define FMC_PMEM_MEMWAIT_0         (0x01U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000100 */\n#define FMC_PMEM_MEMWAIT_1         (0x02U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000200 */\n#define FMC_PMEM_MEMWAIT_2         (0x04U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000400 */\n#define FMC_PMEM_MEMWAIT_3         (0x08U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000800 */\n#define FMC_PMEM_MEMWAIT_4         (0x10U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00001000 */\n#define FMC_PMEM_MEMWAIT_5         (0x20U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00002000 */\n#define FMC_PMEM_MEMWAIT_6         (0x40U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00004000 */\n#define FMC_PMEM_MEMWAIT_7         (0x80U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00008000 */\n\n#define FMC_PMEM_MEMHOLD_Pos       (16U)\n#define FMC_PMEM_MEMHOLD_Msk       (0xFFU << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00FF0000 */\n#define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */\n#define FMC_PMEM_MEMHOLD_0         (0x01U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00010000 */\n#define FMC_PMEM_MEMHOLD_1         (0x02U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00020000 */\n#define FMC_PMEM_MEMHOLD_2         (0x04U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00040000 */\n#define FMC_PMEM_MEMHOLD_3         (0x08U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00080000 */\n#define FMC_PMEM_MEMHOLD_4         (0x10U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00100000 */\n#define FMC_PMEM_MEMHOLD_5         (0x20U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00200000 */\n#define FMC_PMEM_MEMHOLD_6         (0x40U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00400000 */\n#define FMC_PMEM_MEMHOLD_7         (0x80U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00800000 */\n\n#define FMC_PMEM_MEMHIZ_Pos        (24U)\n#define FMC_PMEM_MEMHIZ_Msk        (0xFFU << FMC_PMEM_MEMHIZ_Pos)              /*!< 0xFF000000 */\n#define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */\n#define FMC_PMEM_MEMHIZ_0          (0x01U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x01000000 */\n#define FMC_PMEM_MEMHIZ_1          (0x02U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x02000000 */\n#define FMC_PMEM_MEMHIZ_2          (0x04U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x04000000 */\n#define FMC_PMEM_MEMHIZ_3          (0x08U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x08000000 */\n#define FMC_PMEM_MEMHIZ_4          (0x10U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x10000000 */\n#define FMC_PMEM_MEMHIZ_5          (0x20U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x20000000 */\n#define FMC_PMEM_MEMHIZ_6          (0x40U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x40000000 */\n#define FMC_PMEM_MEMHIZ_7          (0x80U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_PATT register  *******************/\n#define FMC_PATT_ATTSET_Pos        (0U)\n#define FMC_PATT_ATTSET_Msk        (0xFFU << FMC_PATT_ATTSET_Pos)              /*!< 0x000000FF */\n#define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */\n#define FMC_PATT_ATTSET_0          (0x01U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000001 */\n#define FMC_PATT_ATTSET_1          (0x02U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000002 */\n#define FMC_PATT_ATTSET_2          (0x04U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000004 */\n#define FMC_PATT_ATTSET_3          (0x08U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000008 */\n#define FMC_PATT_ATTSET_4          (0x10U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000010 */\n#define FMC_PATT_ATTSET_5          (0x20U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000020 */\n#define FMC_PATT_ATTSET_6          (0x40U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000040 */\n#define FMC_PATT_ATTSET_7          (0x80U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000080 */\n\n#define FMC_PATT_ATTWAIT_Pos       (8U)\n#define FMC_PATT_ATTWAIT_Msk       (0xFFU << FMC_PATT_ATTWAIT_Pos)             /*!< 0x0000FF00 */\n#define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */\n#define FMC_PATT_ATTWAIT_0         (0x01U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000100 */\n#define FMC_PATT_ATTWAIT_1         (0x02U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000200 */\n#define FMC_PATT_ATTWAIT_2         (0x04U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000400 */\n#define FMC_PATT_ATTWAIT_3         (0x08U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000800 */\n#define FMC_PATT_ATTWAIT_4         (0x10U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00001000 */\n#define FMC_PATT_ATTWAIT_5         (0x20U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00002000 */\n#define FMC_PATT_ATTWAIT_6         (0x40U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00004000 */\n#define FMC_PATT_ATTWAIT_7         (0x80U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00008000 */\n\n#define FMC_PATT_ATTHOLD_Pos       (16U)\n#define FMC_PATT_ATTHOLD_Msk       (0xFFU << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00FF0000 */\n#define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */\n#define FMC_PATT_ATTHOLD_0         (0x01U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00010000 */\n#define FMC_PATT_ATTHOLD_1         (0x02U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00020000 */\n#define FMC_PATT_ATTHOLD_2         (0x04U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00040000 */\n#define FMC_PATT_ATTHOLD_3         (0x08U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00080000 */\n#define FMC_PATT_ATTHOLD_4         (0x10U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00100000 */\n#define FMC_PATT_ATTHOLD_5         (0x20U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00200000 */\n#define FMC_PATT_ATTHOLD_6         (0x40U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00400000 */\n#define FMC_PATT_ATTHOLD_7         (0x80U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00800000 */\n\n#define FMC_PATT_ATTHIZ_Pos        (24U)\n#define FMC_PATT_ATTHIZ_Msk        (0xFFU << FMC_PATT_ATTHIZ_Pos)              /*!< 0xFF000000 */\n#define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */\n#define FMC_PATT_ATTHIZ_0          (0x01U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x01000000 */\n#define FMC_PATT_ATTHIZ_1          (0x02U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x02000000 */\n#define FMC_PATT_ATTHIZ_2          (0x04U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x04000000 */\n#define FMC_PATT_ATTHIZ_3          (0x08U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x08000000 */\n#define FMC_PATT_ATTHIZ_4          (0x10U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x10000000 */\n#define FMC_PATT_ATTHIZ_5          (0x20U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x20000000 */\n#define FMC_PATT_ATTHIZ_6          (0x40U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x40000000 */\n#define FMC_PATT_ATTHIZ_7          (0x80U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x80000000 */\n\n/******************  Bit definition for FMC_ECCR register  *******************/\n#define FMC_ECCR_ECC_Pos           (0U)\n#define FMC_ECCR_ECC_Msk           (0xFFFFFFFFU << FMC_ECCR_ECC_Pos)           /*!< 0xFFFFFFFF */\n#define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */\n\n/******************************************************************************/\n/*                                                                            */\n/*                       General Purpose IOs (GPIO)                           */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODE0_Pos           (0U)\n#define GPIO_MODER_MODE0_Msk           (0x3U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */\n#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk\n#define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */\n#define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */\n#define GPIO_MODER_MODE1_Pos           (2U)\n#define GPIO_MODER_MODE1_Msk           (0x3U << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */\n#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk\n#define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */\n#define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */\n#define GPIO_MODER_MODE2_Pos           (4U)\n#define GPIO_MODER_MODE2_Msk           (0x3U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */\n#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk\n#define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */\n#define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */\n#define GPIO_MODER_MODE3_Pos           (6U)\n#define GPIO_MODER_MODE3_Msk           (0x3U << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */\n#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk\n#define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */\n#define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */\n#define GPIO_MODER_MODE4_Pos           (8U)\n#define GPIO_MODER_MODE4_Msk           (0x3U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */\n#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk\n#define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */\n#define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */\n#define GPIO_MODER_MODE5_Pos           (10U)\n#define GPIO_MODER_MODE5_Msk           (0x3U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */\n#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk\n#define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */\n#define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */\n#define GPIO_MODER_MODE6_Pos           (12U)\n#define GPIO_MODER_MODE6_Msk           (0x3U << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */\n#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk\n#define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */\n#define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */\n#define GPIO_MODER_MODE7_Pos           (14U)\n#define GPIO_MODER_MODE7_Msk           (0x3U << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */\n#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk\n#define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */\n#define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */\n#define GPIO_MODER_MODE8_Pos           (16U)\n#define GPIO_MODER_MODE8_Msk           (0x3U << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */\n#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk\n#define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */\n#define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */\n#define GPIO_MODER_MODE9_Pos           (18U)\n#define GPIO_MODER_MODE9_Msk           (0x3U << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */\n#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk\n#define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */\n#define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */\n#define GPIO_MODER_MODE10_Pos          (20U)\n#define GPIO_MODER_MODE10_Msk          (0x3U << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */\n#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk\n#define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */\n#define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */\n#define GPIO_MODER_MODE11_Pos          (22U)\n#define GPIO_MODER_MODE11_Msk          (0x3U << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */\n#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk\n#define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */\n#define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */\n#define GPIO_MODER_MODE12_Pos          (24U)\n#define GPIO_MODER_MODE12_Msk          (0x3U << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */\n#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk\n#define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */\n#define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */\n#define GPIO_MODER_MODE13_Pos          (26U)\n#define GPIO_MODER_MODE13_Msk          (0x3U << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */\n#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk\n#define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */\n#define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */\n#define GPIO_MODER_MODE14_Pos          (28U)\n#define GPIO_MODER_MODE14_Msk          (0x3U << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */\n#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk\n#define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */\n#define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */\n#define GPIO_MODER_MODE15_Pos          (30U)\n#define GPIO_MODER_MODE15_Msk          (0x3U << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */\n#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk\n#define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */\n#define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODER0                   GPIO_MODER_MODE0\n#define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0\n#define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1\n#define GPIO_MODER_MODER1                   GPIO_MODER_MODE1\n#define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0\n#define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1\n#define GPIO_MODER_MODER2                   GPIO_MODER_MODE2\n#define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0\n#define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1\n#define GPIO_MODER_MODER3                   GPIO_MODER_MODE3\n#define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0\n#define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1\n#define GPIO_MODER_MODER4                   GPIO_MODER_MODE4\n#define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0\n#define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1\n#define GPIO_MODER_MODER5                   GPIO_MODER_MODE5\n#define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0\n#define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1\n#define GPIO_MODER_MODER6                   GPIO_MODER_MODE6\n#define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0\n#define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1\n#define GPIO_MODER_MODER7                   GPIO_MODER_MODE7\n#define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0\n#define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1\n#define GPIO_MODER_MODER8                   GPIO_MODER_MODE8\n#define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0\n#define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1\n#define GPIO_MODER_MODER9                   GPIO_MODER_MODE9\n#define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0\n#define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1\n#define GPIO_MODER_MODER10                  GPIO_MODER_MODE10\n#define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0\n#define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1\n#define GPIO_MODER_MODER11                  GPIO_MODER_MODE11\n#define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0\n#define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1\n#define GPIO_MODER_MODER12                  GPIO_MODER_MODE12\n#define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0\n#define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1\n#define GPIO_MODER_MODER13                  GPIO_MODER_MODE13\n#define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0\n#define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1\n#define GPIO_MODER_MODER14                  GPIO_MODER_MODE14\n#define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0\n#define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1\n#define GPIO_MODER_MODER15                  GPIO_MODER_MODE15\n#define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0\n#define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos            (0U)\n#define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk\n#define GPIO_OTYPER_OT1_Pos            (1U)\n#define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk\n#define GPIO_OTYPER_OT2_Pos            (2U)\n#define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk\n#define GPIO_OTYPER_OT3_Pos            (3U)\n#define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk\n#define GPIO_OTYPER_OT4_Pos            (4U)\n#define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk\n#define GPIO_OTYPER_OT5_Pos            (5U)\n#define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk\n#define GPIO_OTYPER_OT6_Pos            (6U)\n#define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk\n#define GPIO_OTYPER_OT7_Pos            (7U)\n#define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk\n#define GPIO_OTYPER_OT8_Pos            (8U)\n#define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk\n#define GPIO_OTYPER_OT9_Pos            (9U)\n#define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk\n#define GPIO_OTYPER_OT10_Pos           (10U)\n#define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk\n#define GPIO_OTYPER_OT11_Pos           (11U)\n#define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk\n#define GPIO_OTYPER_OT12_Pos           (12U)\n#define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk\n#define GPIO_OTYPER_OT13_Pos           (13U)\n#define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk\n#define GPIO_OTYPER_OT14_Pos           (14U)\n#define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk\n#define GPIO_OTYPER_OT15_Pos           (15U)\n#define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk\n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)\n#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk\n#define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)\n#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk\n#define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)\n#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk\n#define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)\n#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk\n#define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)\n#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk\n#define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)\n#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk\n#define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)\n#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk\n#define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)\n#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk\n#define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)\n#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk\n#define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)\n#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk\n#define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)\n#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk\n#define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)\n#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk\n#define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)\n#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk\n#define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)\n#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk\n#define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)\n#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk\n#define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)\n#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk\n#define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos           (0U)\n#define GPIO_PUPDR_PUPD0_Msk           (0x3U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk\n#define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos           (2U)\n#define GPIO_PUPDR_PUPD1_Msk           (0x3U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk\n#define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos           (4U)\n#define GPIO_PUPDR_PUPD2_Msk           (0x3U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk\n#define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos           (6U)\n#define GPIO_PUPDR_PUPD3_Msk           (0x3U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk\n#define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos           (8U)\n#define GPIO_PUPDR_PUPD4_Msk           (0x3U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk\n#define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos           (10U)\n#define GPIO_PUPDR_PUPD5_Msk           (0x3U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk\n#define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos           (12U)\n#define GPIO_PUPDR_PUPD6_Msk           (0x3U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk\n#define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos           (14U)\n#define GPIO_PUPDR_PUPD7_Msk           (0x3U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk\n#define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos           (16U)\n#define GPIO_PUPDR_PUPD8_Msk           (0x3U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk\n#define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos           (18U)\n#define GPIO_PUPDR_PUPD9_Msk           (0x3U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk\n#define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos          (20U)\n#define GPIO_PUPDR_PUPD10_Msk          (0x3U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk\n#define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos          (22U)\n#define GPIO_PUPDR_PUPD11_Msk          (0x3U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk\n#define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos          (24U)\n#define GPIO_PUPDR_PUPD12_Msk          (0x3U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk\n#define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos          (26U)\n#define GPIO_PUPDR_PUPD13_Msk          (0x3U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk\n#define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos          (28U)\n#define GPIO_PUPDR_PUPD14_Msk          (0x3U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk\n#define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos          (30U)\n#define GPIO_PUPDR_PUPD15_Msk          (0x3U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk\n#define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos               (0U)\n#define GPIO_IDR_ID0_Msk               (0x1U << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */\n#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk\n#define GPIO_IDR_ID1_Pos               (1U)\n#define GPIO_IDR_ID1_Msk               (0x1U << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */\n#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk\n#define GPIO_IDR_ID2_Pos               (2U)\n#define GPIO_IDR_ID2_Msk               (0x1U << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */\n#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk\n#define GPIO_IDR_ID3_Pos               (3U)\n#define GPIO_IDR_ID3_Msk               (0x1U << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */\n#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk\n#define GPIO_IDR_ID4_Pos               (4U)\n#define GPIO_IDR_ID4_Msk               (0x1U << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */\n#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk\n#define GPIO_IDR_ID5_Pos               (5U)\n#define GPIO_IDR_ID5_Msk               (0x1U << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */\n#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk\n#define GPIO_IDR_ID6_Pos               (6U)\n#define GPIO_IDR_ID6_Msk               (0x1U << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */\n#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk\n#define GPIO_IDR_ID7_Pos               (7U)\n#define GPIO_IDR_ID7_Msk               (0x1U << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */\n#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk\n#define GPIO_IDR_ID8_Pos               (8U)\n#define GPIO_IDR_ID8_Msk               (0x1U << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */\n#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk\n#define GPIO_IDR_ID9_Pos               (9U)\n#define GPIO_IDR_ID9_Msk               (0x1U << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */\n#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk\n#define GPIO_IDR_ID10_Pos              (10U)\n#define GPIO_IDR_ID10_Msk              (0x1U << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */\n#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk\n#define GPIO_IDR_ID11_Pos              (11U)\n#define GPIO_IDR_ID11_Msk              (0x1U << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */\n#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk\n#define GPIO_IDR_ID12_Pos              (12U)\n#define GPIO_IDR_ID12_Msk              (0x1U << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */\n#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk\n#define GPIO_IDR_ID13_Pos              (13U)\n#define GPIO_IDR_ID13_Msk              (0x1U << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */\n#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk\n#define GPIO_IDR_ID14_Pos              (14U)\n#define GPIO_IDR_ID14_Msk              (0x1U << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */\n#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk\n#define GPIO_IDR_ID15_Pos              (15U)\n#define GPIO_IDR_ID15_Msk              (0x1U << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */\n#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk\n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                      GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                      GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                      GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                      GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                      GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                      GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                      GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                      GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                      GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                      GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                     GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                     GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                     GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                     GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                     GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                     GPIO_IDR_ID15\n\n/* Old GPIO_IDR register bits definition, maintained for legacy purpose */\n#define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0\n#define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1\n#define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2\n#define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3\n#define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4\n#define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5\n#define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6\n#define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7\n#define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8\n#define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9\n#define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10\n#define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11\n#define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12\n#define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13\n#define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14\n#define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos               (0U)\n#define GPIO_ODR_OD0_Msk               (0x1U << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */\n#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk\n#define GPIO_ODR_OD1_Pos               (1U)\n#define GPIO_ODR_OD1_Msk               (0x1U << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */\n#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk\n#define GPIO_ODR_OD2_Pos               (2U)\n#define GPIO_ODR_OD2_Msk               (0x1U << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */\n#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk\n#define GPIO_ODR_OD3_Pos               (3U)\n#define GPIO_ODR_OD3_Msk               (0x1U << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */\n#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk\n#define GPIO_ODR_OD4_Pos               (4U)\n#define GPIO_ODR_OD4_Msk               (0x1U << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */\n#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk\n#define GPIO_ODR_OD5_Pos               (5U)\n#define GPIO_ODR_OD5_Msk               (0x1U << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */\n#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk\n#define GPIO_ODR_OD6_Pos               (6U)\n#define GPIO_ODR_OD6_Msk               (0x1U << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */\n#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk\n#define GPIO_ODR_OD7_Pos               (7U)\n#define GPIO_ODR_OD7_Msk               (0x1U << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */\n#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk\n#define GPIO_ODR_OD8_Pos               (8U)\n#define GPIO_ODR_OD8_Msk               (0x1U << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */\n#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk\n#define GPIO_ODR_OD9_Pos               (9U)\n#define GPIO_ODR_OD9_Msk               (0x1U << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */\n#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk\n#define GPIO_ODR_OD10_Pos              (10U)\n#define GPIO_ODR_OD10_Msk              (0x1U << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */\n#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk\n#define GPIO_ODR_OD11_Pos              (11U)\n#define GPIO_ODR_OD11_Msk              (0x1U << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */\n#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk\n#define GPIO_ODR_OD12_Pos              (12U)\n#define GPIO_ODR_OD12_Msk              (0x1U << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */\n#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk\n#define GPIO_ODR_OD13_Pos              (13U)\n#define GPIO_ODR_OD13_Msk              (0x1U << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */\n#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk\n#define GPIO_ODR_OD14_Pos              (14U)\n#define GPIO_ODR_OD14_Msk              (0x1U << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */\n#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk\n#define GPIO_ODR_OD15_Pos              (15U)\n#define GPIO_ODR_OD15_Msk              (0x1U << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */\n#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk\n\n/* Legacy defines */\n#define GPIO_ODR_ODR_0                      GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                      GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                      GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                      GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                      GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                      GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                      GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                      GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                      GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                      GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                     GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                     GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                     GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                     GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                     GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                     GPIO_ODR_OD15\n\n/* Old GPIO_ODR register bits definition, maintained for legacy purpose */\n#define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0\n#define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1\n#define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2\n#define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3\n#define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4\n#define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5\n#define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6\n#define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7\n#define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8\n#define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9\n#define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10\n#define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11\n#define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12\n#define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13\n#define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14\n#define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos              (0U)\n#define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk\n#define GPIO_BSRR_BS1_Pos              (1U)\n#define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk\n#define GPIO_BSRR_BS2_Pos              (2U)\n#define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk\n#define GPIO_BSRR_BS3_Pos              (3U)\n#define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk\n#define GPIO_BSRR_BS4_Pos              (4U)\n#define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk\n#define GPIO_BSRR_BS5_Pos              (5U)\n#define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk\n#define GPIO_BSRR_BS6_Pos              (6U)\n#define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk\n#define GPIO_BSRR_BS7_Pos              (7U)\n#define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk\n#define GPIO_BSRR_BS8_Pos              (8U)\n#define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk\n#define GPIO_BSRR_BS9_Pos              (9U)\n#define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk\n#define GPIO_BSRR_BS10_Pos             (10U)\n#define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk\n#define GPIO_BSRR_BS11_Pos             (11U)\n#define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk\n#define GPIO_BSRR_BS12_Pos             (12U)\n#define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk\n#define GPIO_BSRR_BS13_Pos             (13U)\n#define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk\n#define GPIO_BSRR_BS14_Pos             (14U)\n#define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk\n#define GPIO_BSRR_BS15_Pos             (15U)\n#define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk\n#define GPIO_BSRR_BR0_Pos              (16U)\n#define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk\n#define GPIO_BSRR_BR1_Pos              (17U)\n#define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk\n#define GPIO_BSRR_BR2_Pos              (18U)\n#define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk\n#define GPIO_BSRR_BR3_Pos              (19U)\n#define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk\n#define GPIO_BSRR_BR4_Pos              (20U)\n#define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk\n#define GPIO_BSRR_BR5_Pos              (21U)\n#define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk\n#define GPIO_BSRR_BR6_Pos              (22U)\n#define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk\n#define GPIO_BSRR_BR7_Pos              (23U)\n#define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk\n#define GPIO_BSRR_BR8_Pos              (24U)\n#define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk\n#define GPIO_BSRR_BR9_Pos              (25U)\n#define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk\n#define GPIO_BSRR_BR10_Pos             (26U)\n#define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk\n#define GPIO_BSRR_BR11_Pos             (27U)\n#define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk\n#define GPIO_BSRR_BR12_Pos             (28U)\n#define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk\n#define GPIO_BSRR_BR13_Pos             (29U)\n#define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk\n#define GPIO_BSRR_BR14_Pos             (30U)\n#define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk\n#define GPIO_BSRR_BR15_Pos             (31U)\n#define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15\n\n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos             (0U)\n#define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk\n#define GPIO_LCKR_LCK1_Pos             (1U)\n#define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk\n#define GPIO_LCKR_LCK2_Pos             (2U)\n#define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk\n#define GPIO_LCKR_LCK3_Pos             (3U)\n#define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk\n#define GPIO_LCKR_LCK4_Pos             (4U)\n#define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk\n#define GPIO_LCKR_LCK5_Pos             (5U)\n#define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk\n#define GPIO_LCKR_LCK6_Pos             (6U)\n#define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk\n#define GPIO_LCKR_LCK7_Pos             (7U)\n#define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk\n#define GPIO_LCKR_LCK8_Pos             (8U)\n#define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk\n#define GPIO_LCKR_LCK9_Pos             (9U)\n#define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk\n#define GPIO_LCKR_LCK10_Pos            (10U)\n#define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk\n#define GPIO_LCKR_LCK11_Pos            (11U)\n#define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk\n#define GPIO_LCKR_LCK12_Pos            (12U)\n#define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk\n#define GPIO_LCKR_LCK13_Pos            (13U)\n#define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk\n#define GPIO_LCKR_LCK14_Pos            (14U)\n#define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk\n#define GPIO_LCKR_LCK15_Pos            (15U)\n#define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk\n#define GPIO_LCKR_LCKK_Pos             (16U)\n#define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk\n\n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos           (0U)\n#define GPIO_AFRL_AFSEL0_Msk           (0xFU << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk\n#define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos           (4U)\n#define GPIO_AFRL_AFSEL1_Msk           (0xFU << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk\n#define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos           (8U)\n#define GPIO_AFRL_AFSEL2_Msk           (0xFU << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk\n#define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos           (12U)\n#define GPIO_AFRL_AFSEL3_Msk           (0xFU << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk\n#define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos           (16U)\n#define GPIO_AFRL_AFSEL4_Msk           (0xFU << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk\n#define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos           (20U)\n#define GPIO_AFRL_AFSEL5_Msk           (0xFU << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk\n#define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos           (24U)\n#define GPIO_AFRL_AFSEL6_Msk           (0xFU << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk\n#define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos           (28U)\n#define GPIO_AFRL_AFSEL7_Msk           (0xFU << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk\n#define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos           (0U)\n#define GPIO_AFRH_AFSEL8_Msk           (0xFU << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk\n#define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos           (4U)\n#define GPIO_AFRH_AFSEL9_Msk           (0xFU << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk\n#define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos          (8U)\n#define GPIO_AFRH_AFSEL10_Msk          (0xFU << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk\n#define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos          (12U)\n#define GPIO_AFRH_AFSEL11_Msk          (0xFU << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk\n#define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos          (16U)\n#define GPIO_AFRH_AFSEL12_Msk          (0xFU << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk\n#define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos          (20U)\n#define GPIO_AFRH_AFSEL13_Msk          (0xFU << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk\n#define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos          (24U)\n#define GPIO_AFRH_AFSEL14_Msk          (0xFU << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk\n#define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos          (28U)\n#define GPIO_AFRH_AFSEL15_Msk          (0xFU << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk\n#define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15\n\n/******************  Bits definition for GPIO_BRR register  ******************/\n#define GPIO_BRR_BR0_Pos               (0U)\n#define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */\n#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk\n#define GPIO_BRR_BR1_Pos               (1U)\n#define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */\n#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk\n#define GPIO_BRR_BR2_Pos               (2U)\n#define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */\n#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk\n#define GPIO_BRR_BR3_Pos               (3U)\n#define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */\n#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk\n#define GPIO_BRR_BR4_Pos               (4U)\n#define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */\n#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk\n#define GPIO_BRR_BR5_Pos               (5U)\n#define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */\n#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk\n#define GPIO_BRR_BR6_Pos               (6U)\n#define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */\n#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk\n#define GPIO_BRR_BR7_Pos               (7U)\n#define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */\n#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk\n#define GPIO_BRR_BR8_Pos               (8U)\n#define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */\n#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk\n#define GPIO_BRR_BR9_Pos               (9U)\n#define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */\n#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk\n#define GPIO_BRR_BR10_Pos              (10U)\n#define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */\n#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk\n#define GPIO_BRR_BR11_Pos              (11U)\n#define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */\n#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk\n#define GPIO_BRR_BR12_Pos              (12U)\n#define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */\n#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk\n#define GPIO_BRR_BR13_Pos              (13U)\n#define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */\n#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk\n#define GPIO_BRR_BR14_Pos              (14U)\n#define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */\n#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk\n#define GPIO_BRR_BR15_Pos              (15U)\n#define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */\n#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk\n\n/* Legacy defines */\n#define GPIO_BRR_BR_0                       GPIO_BRR_BR0\n#define GPIO_BRR_BR_1                       GPIO_BRR_BR1\n#define GPIO_BRR_BR_2                       GPIO_BRR_BR2\n#define GPIO_BRR_BR_3                       GPIO_BRR_BR3\n#define GPIO_BRR_BR_4                       GPIO_BRR_BR4\n#define GPIO_BRR_BR_5                       GPIO_BRR_BR5\n#define GPIO_BRR_BR_6                       GPIO_BRR_BR6\n#define GPIO_BRR_BR_7                       GPIO_BRR_BR7\n#define GPIO_BRR_BR_8                       GPIO_BRR_BR8\n#define GPIO_BRR_BR_9                       GPIO_BRR_BR9\n#define GPIO_BRR_BR_10                      GPIO_BRR_BR10\n#define GPIO_BRR_BR_11                      GPIO_BRR_BR11\n#define GPIO_BRR_BR_12                      GPIO_BRR_BR12\n#define GPIO_BRR_BR_13                      GPIO_BRR_BR13\n#define GPIO_BRR_BR_14                      GPIO_BRR_BR14\n#define GPIO_BRR_BR_15                      GPIO_BRR_BR15\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface (I2C)              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  *******************/\n#define I2C_CR1_PE_Pos               (0U)\n#define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */\n#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */\n#define I2C_CR1_TXIE_Pos             (1U)\n#define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */\n#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */\n#define I2C_CR1_RXIE_Pos             (2U)\n#define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */\n#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */\n#define I2C_CR1_ADDRIE_Pos           (3U)\n#define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */\n#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */\n#define I2C_CR1_NACKIE_Pos           (4U)\n#define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */\n#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */\n#define I2C_CR1_STOPIE_Pos           (5U)\n#define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */\n#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */\n#define I2C_CR1_TCIE_Pos             (6U)\n#define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */\n#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */\n#define I2C_CR1_ERRIE_Pos            (7U)\n#define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */\n#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */\n#define I2C_CR1_DNF_Pos              (8U)\n#define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */\n#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */\n#define I2C_CR1_ANFOFF_Pos           (12U)\n#define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */\n#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */\n#define I2C_CR1_SWRST_Pos            (13U)\n#define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */\n#define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */\n#define I2C_CR1_TXDMAEN_Pos          (14U)\n#define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */\n#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */\n#define I2C_CR1_RXDMAEN_Pos          (15U)\n#define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */\n#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */\n#define I2C_CR1_SBC_Pos              (16U)\n#define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */\n#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */\n#define I2C_CR1_NOSTRETCH_Pos        (17U)\n#define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */\n#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */\n#define I2C_CR1_WUPEN_Pos            (18U)\n#define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */\n#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */\n#define I2C_CR1_GCEN_Pos             (19U)\n#define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */\n#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */\n#define I2C_CR1_SMBHEN_Pos           (20U)\n#define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */\n#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */\n#define I2C_CR1_SMBDEN_Pos           (21U)\n#define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */\n#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */\n#define I2C_CR1_ALERTEN_Pos          (22U)\n#define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */\n#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */\n#define I2C_CR1_PECEN_Pos            (23U)\n#define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */\n#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */\n\n/******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_SADD_Pos             (0U)\n#define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */\n#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */\n#define I2C_CR2_RD_WRN_Pos           (10U)\n#define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */\n#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */\n#define I2C_CR2_ADD10_Pos            (11U)\n#define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */\n#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */\n#define I2C_CR2_HEAD10R_Pos          (12U)\n#define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */\n#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */\n#define I2C_CR2_START_Pos            (13U)\n#define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */\n#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */\n#define I2C_CR2_STOP_Pos             (14U)\n#define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */\n#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */\n#define I2C_CR2_NACK_Pos             (15U)\n#define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */\n#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */\n#define I2C_CR2_NBYTES_Pos           (16U)\n#define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */\n#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */\n#define I2C_CR2_RELOAD_Pos           (24U)\n#define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */\n#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */\n#define I2C_CR2_AUTOEND_Pos          (25U)\n#define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */\n#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */\n#define I2C_CR2_PECBYTE_Pos          (26U)\n#define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */\n#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */\n\n/*******************  Bit definition for I2C_OAR1 register  ******************/\n#define I2C_OAR1_OA1_Pos             (0U)\n#define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */\n#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */\n#define I2C_OAR1_OA1MODE_Pos         (10U)\n#define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */\n#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */\n#define I2C_OAR1_OA1EN_Pos           (15U)\n#define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */\n#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */\n\n/*******************  Bit definition for I2C_OAR2 register  ******************/\n#define I2C_OAR2_OA2_Pos             (1U)\n#define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */\n#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */\n#define I2C_OAR2_OA2MSK_Pos          (8U)\n#define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */\n#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */\n#define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */\n#define I2C_OAR2_OA2MASK01_Pos       (8U)\n#define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */\n#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */\n#define I2C_OAR2_OA2MASK02_Pos       (9U)\n#define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */\n#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\n#define I2C_OAR2_OA2MASK03_Pos       (8U)\n#define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */\n#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\n#define I2C_OAR2_OA2MASK04_Pos       (10U)\n#define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */\n#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\n#define I2C_OAR2_OA2MASK05_Pos       (8U)\n#define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */\n#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\n#define I2C_OAR2_OA2MASK06_Pos       (9U)\n#define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */\n#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */\n#define I2C_OAR2_OA2MASK07_Pos       (8U)\n#define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */\n#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */\n#define I2C_OAR2_OA2EN_Pos           (15U)\n#define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */\n#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */\n\n/*******************  Bit definition for I2C_TIMINGR register *******************/\n#define I2C_TIMINGR_SCLL_Pos         (0U)\n#define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */\n#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */\n#define I2C_TIMINGR_SCLH_Pos         (8U)\n#define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */\n#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */\n#define I2C_TIMINGR_SDADEL_Pos       (16U)\n#define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */\n#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */\n#define I2C_TIMINGR_SCLDEL_Pos       (20U)\n#define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */\n#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */\n#define I2C_TIMINGR_PRESC_Pos        (28U)\n#define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */\n#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */\n\n/******************* Bit definition for I2C_TIMEOUTR register *******************/\n#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)\n#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */\n#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */\n#define I2C_TIMEOUTR_TIDLE_Pos       (12U)\n#define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */\n#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */\n#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)\n#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */\n#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */\n#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)\n#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */\n#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */\n#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)\n#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */\n#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */\n\n/******************  Bit definition for I2C_ISR register  *********************/\n#define I2C_ISR_TXE_Pos              (0U)\n#define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */\n#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */\n#define I2C_ISR_TXIS_Pos             (1U)\n#define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */\n#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */\n#define I2C_ISR_RXNE_Pos             (2U)\n#define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */\n#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */\n#define I2C_ISR_ADDR_Pos             (3U)\n#define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */\n#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */\n#define I2C_ISR_NACKF_Pos            (4U)\n#define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */\n#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */\n#define I2C_ISR_STOPF_Pos            (5U)\n#define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */\n#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */\n#define I2C_ISR_TC_Pos               (6U)\n#define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */\n#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */\n#define I2C_ISR_TCR_Pos              (7U)\n#define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */\n#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */\n#define I2C_ISR_BERR_Pos             (8U)\n#define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */\n#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */\n#define I2C_ISR_ARLO_Pos             (9U)\n#define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */\n#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */\n#define I2C_ISR_OVR_Pos              (10U)\n#define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */\n#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */\n#define I2C_ISR_PECERR_Pos           (11U)\n#define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */\n#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */\n#define I2C_ISR_TIMEOUT_Pos          (12U)\n#define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */\n#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */\n#define I2C_ISR_ALERT_Pos            (13U)\n#define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */\n#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */\n#define I2C_ISR_BUSY_Pos             (15U)\n#define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */\n#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */\n#define I2C_ISR_DIR_Pos              (16U)\n#define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */\n#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */\n#define I2C_ISR_ADDCODE_Pos          (17U)\n#define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */\n#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */\n\n/******************  Bit definition for I2C_ICR register  *********************/\n#define I2C_ICR_ADDRCF_Pos           (3U)\n#define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */\n#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */\n#define I2C_ICR_NACKCF_Pos           (4U)\n#define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */\n#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */\n#define I2C_ICR_STOPCF_Pos           (5U)\n#define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */\n#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */\n#define I2C_ICR_BERRCF_Pos           (8U)\n#define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */\n#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */\n#define I2C_ICR_ARLOCF_Pos           (9U)\n#define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */\n#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */\n#define I2C_ICR_OVRCF_Pos            (10U)\n#define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */\n#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */\n#define I2C_ICR_PECCF_Pos            (11U)\n#define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */\n#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */\n#define I2C_ICR_TIMOUTCF_Pos         (12U)\n#define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */\n#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */\n#define I2C_ICR_ALERTCF_Pos          (13U)\n#define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */\n#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */\n\n/******************  Bit definition for I2C_PECR register  *********************/\n#define I2C_PECR_PEC_Pos             (0U)\n#define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */\n#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */\n\n/******************  Bit definition for I2C_RXDR register  *********************/\n#define I2C_RXDR_RXDATA_Pos          (0U)\n#define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */\n#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */\n\n/******************  Bit definition for I2C_TXDR register  *********************/\n#define I2C_TXDR_TXDATA_Pos          (0U)\n#define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */\n#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos      (0U)\n#define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */\n#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos       (0U)\n#define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */\n#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */\n#define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */\n#define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos      (0U)\n#define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */\n#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos      (0U)\n#define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */\n#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */\n#define IWDG_SR_RVU_Pos      (1U)\n#define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */\n#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */\n#define IWDG_SR_WVU_Pos      (2U)\n#define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */\n#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */\n\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_WINR_WIN_Pos    (0U)\n#define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */\n#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                     Firewall                               */\n/*                                                                            */\n/******************************************************************************/\n\n/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */\n#define FW_CSSA_ADD_Pos      (8U)\n#define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */\n#define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */\n#define FW_CSL_LENG_Pos      (8U)\n#define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */\n#define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */\n#define FW_NVDSSA_ADD_Pos    (8U)\n#define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */\n#define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */\n#define FW_NVDSL_LENG_Pos    (8U)\n#define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */\n#define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */\n#define FW_VDSSA_ADD_Pos     (6U)\n#define FW_VDSSA_ADD_Msk     (0xFFFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0003FFC0 */\n#define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */\n#define FW_VDSL_LENG_Pos     (6U)\n#define FW_VDSL_LENG_Msk     (0xFFFU << FW_VDSL_LENG_Pos)                      /*!< 0x0003FFC0 */\n#define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */\n\n/**************************Bit definition for CR register *********************/\n#define FW_CR_FPA_Pos        (0U)\n#define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */\n#define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/\n#define FW_CR_VDS_Pos        (1U)\n#define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */\n#define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/\n#define FW_CR_VDE_Pos        (2U)\n#define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */\n#define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for PWR_CR1 register  ********************/\n\n#define PWR_CR1_LPR_Pos              (14U)\n#define PWR_CR1_LPR_Msk              (0x1U << PWR_CR1_LPR_Pos)                 /*!< 0x00004000 */\n#define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */\n#define PWR_CR1_VOS_Pos              (9U)\n#define PWR_CR1_VOS_Msk              (0x3U << PWR_CR1_VOS_Pos)                 /*!< 0x00000600 */\n#define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\n#define PWR_CR1_VOS_0                (0x1U << PWR_CR1_VOS_Pos)                 /*!< 0x00000200 */\n#define PWR_CR1_VOS_1                (0x2U << PWR_CR1_VOS_Pos)                 /*!< 0x00000400 */\n#define PWR_CR1_DBP_Pos              (8U)\n#define PWR_CR1_DBP_Msk              (0x1U << PWR_CR1_DBP_Pos)                 /*!< 0x00000100 */\n#define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */\n#define PWR_CR1_LPMS_Pos             (0U)\n#define PWR_CR1_LPMS_Msk             (0x7U << PWR_CR1_LPMS_Pos)                /*!< 0x00000007 */\n#define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */\n#define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */\n#define PWR_CR1_LPMS_STOP1_Pos       (0U)\n#define PWR_CR1_LPMS_STOP1_Msk       (0x1U << PWR_CR1_LPMS_STOP1_Pos)          /*!< 0x00000001 */\n#define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */\n#define PWR_CR1_LPMS_STOP2_Pos       (1U)\n#define PWR_CR1_LPMS_STOP2_Msk       (0x1U << PWR_CR1_LPMS_STOP2_Pos)          /*!< 0x00000002 */\n#define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */\n#define PWR_CR1_LPMS_STANDBY_Pos     (0U)\n#define PWR_CR1_LPMS_STANDBY_Msk     (0x3U << PWR_CR1_LPMS_STANDBY_Pos)        /*!< 0x00000003 */\n#define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */\n#define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)\n#define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos)       /*!< 0x00000004 */\n#define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */\n\n\n/********************  Bit definition for PWR_CR2 register  ********************/\n#define PWR_CR2_USV_Pos              (10U)\n#define PWR_CR2_USV_Msk              (0x1U << PWR_CR2_USV_Pos)                 /*!< 0x00000400 */\n#define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */\n#define PWR_CR2_IOSV_Pos             (9U)\n#define PWR_CR2_IOSV_Msk             (0x1U << PWR_CR2_IOSV_Pos)                /*!< 0x00000200 */\n#define PWR_CR2_IOSV                 PWR_CR2_IOSV_Msk                          /*!< VDD IO2 independent I/Os Supply Valid */\n/*!< PVME  Peripheral Voltage Monitor Enable */\n#define PWR_CR2_PVME_Pos             (4U)\n#define PWR_CR2_PVME_Msk             (0xFU << PWR_CR2_PVME_Pos)                /*!< 0x000000F0 */\n#define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */\n#define PWR_CR2_PVME4_Pos            (7U)\n#define PWR_CR2_PVME4_Msk            (0x1U << PWR_CR2_PVME4_Pos)               /*!< 0x00000080 */\n#define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */\n#define PWR_CR2_PVME3_Pos            (6U)\n#define PWR_CR2_PVME3_Msk            (0x1U << PWR_CR2_PVME3_Pos)               /*!< 0x00000040 */\n#define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */\n#define PWR_CR2_PVME2_Pos            (5U)\n#define PWR_CR2_PVME2_Msk            (0x1U << PWR_CR2_PVME2_Pos)               /*!< 0x00000020 */\n#define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */\n#define PWR_CR2_PVME1_Pos            (4U)\n#define PWR_CR2_PVME1_Msk            (0x1U << PWR_CR2_PVME1_Pos)               /*!< 0x00000010 */\n#define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */\n/*!< PVD level configuration */\n#define PWR_CR2_PLS_Pos              (1U)\n#define PWR_CR2_PLS_Msk              (0x7U << PWR_CR2_PLS_Pos)                 /*!< 0x0000000E */\n#define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */\n#define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */\n#define PWR_CR2_PLS_LEV1_Pos         (1U)\n#define PWR_CR2_PLS_LEV1_Msk         (0x1U << PWR_CR2_PLS_LEV1_Pos)            /*!< 0x00000002 */\n#define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */\n#define PWR_CR2_PLS_LEV2_Pos         (2U)\n#define PWR_CR2_PLS_LEV2_Msk         (0x1U << PWR_CR2_PLS_LEV2_Pos)            /*!< 0x00000004 */\n#define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */\n#define PWR_CR2_PLS_LEV3_Pos         (1U)\n#define PWR_CR2_PLS_LEV3_Msk         (0x3U << PWR_CR2_PLS_LEV3_Pos)            /*!< 0x00000006 */\n#define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */\n#define PWR_CR2_PLS_LEV4_Pos         (3U)\n#define PWR_CR2_PLS_LEV4_Msk         (0x1U << PWR_CR2_PLS_LEV4_Pos)            /*!< 0x00000008 */\n#define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */\n#define PWR_CR2_PLS_LEV5_Pos         (1U)\n#define PWR_CR2_PLS_LEV5_Msk         (0x5U << PWR_CR2_PLS_LEV5_Pos)            /*!< 0x0000000A */\n#define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */\n#define PWR_CR2_PLS_LEV6_Pos         (2U)\n#define PWR_CR2_PLS_LEV6_Msk         (0x3U << PWR_CR2_PLS_LEV6_Pos)            /*!< 0x0000000C */\n#define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */\n#define PWR_CR2_PLS_LEV7_Pos         (1U)\n#define PWR_CR2_PLS_LEV7_Msk         (0x7U << PWR_CR2_PLS_LEV7_Pos)            /*!< 0x0000000E */\n#define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */\n#define PWR_CR2_PVDE_Pos             (0U)\n#define PWR_CR2_PVDE_Msk             (0x1U << PWR_CR2_PVDE_Pos)                /*!< 0x00000001 */\n#define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */\n\n/********************  Bit definition for PWR_CR3 register  ********************/\n#define PWR_CR3_EIWUL_Pos            (15U)\n#define PWR_CR3_EIWUL_Msk            (0x1U << PWR_CR3_EIWUL_Pos)               /*!< 0x00008000 */\n#define PWR_CR3_EIWUL                PWR_CR3_EIWUL_Msk                         /*!< Enable Internal Wake-up line */\n#define PWR_CR3_APC_Pos              (10U)\n#define PWR_CR3_APC_Msk              (0x1U << PWR_CR3_APC_Pos)                 /*!< 0x00000400 */\n#define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */\n#define PWR_CR3_RRS_Pos              (8U)\n#define PWR_CR3_RRS_Msk              (0x1U << PWR_CR3_RRS_Pos)                 /*!< 0x00000100 */\n#define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */\n#define PWR_CR3_EWUP5_Pos            (4U)\n#define PWR_CR3_EWUP5_Msk            (0x1U << PWR_CR3_EWUP5_Pos)               /*!< 0x00000010 */\n#define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */\n#define PWR_CR3_EWUP4_Pos            (3U)\n#define PWR_CR3_EWUP4_Msk            (0x1U << PWR_CR3_EWUP4_Pos)               /*!< 0x00000008 */\n#define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */\n#define PWR_CR3_EWUP3_Pos            (2U)\n#define PWR_CR3_EWUP3_Msk            (0x1U << PWR_CR3_EWUP3_Pos)               /*!< 0x00000004 */\n#define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */\n#define PWR_CR3_EWUP2_Pos            (1U)\n#define PWR_CR3_EWUP2_Msk            (0x1U << PWR_CR3_EWUP2_Pos)               /*!< 0x00000002 */\n#define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */\n#define PWR_CR3_EWUP1_Pos            (0U)\n#define PWR_CR3_EWUP1_Msk            (0x1U << PWR_CR3_EWUP1_Pos)               /*!< 0x00000001 */\n#define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */\n#define PWR_CR3_EWUP_Pos             (0U)\n#define PWR_CR3_EWUP_Msk             (0x1FU << PWR_CR3_EWUP_Pos)               /*!< 0x0000001F */\n#define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */\n\n/* Legacy defines */\n#define PWR_CR3_EIWF_Pos             PWR_CR3_EIWUL_Pos\n#define PWR_CR3_EIWF_Msk             PWR_CR3_EIWUL_Msk\n#define PWR_CR3_EIWF                 PWR_CR3_EIWUL\n\n\n/********************  Bit definition for PWR_CR4 register  ********************/\n#define PWR_CR4_VBRS_Pos             (9U)\n#define PWR_CR4_VBRS_Msk             (0x1U << PWR_CR4_VBRS_Pos)                /*!< 0x00000200 */\n#define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */\n#define PWR_CR4_VBE_Pos              (8U)\n#define PWR_CR4_VBE_Msk              (0x1U << PWR_CR4_VBE_Pos)                 /*!< 0x00000100 */\n#define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */\n#define PWR_CR4_WP5_Pos              (4U)\n#define PWR_CR4_WP5_Msk              (0x1U << PWR_CR4_WP5_Pos)                 /*!< 0x00000010 */\n#define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */\n#define PWR_CR4_WP4_Pos              (3U)\n#define PWR_CR4_WP4_Msk              (0x1U << PWR_CR4_WP4_Pos)                 /*!< 0x00000008 */\n#define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */\n#define PWR_CR4_WP3_Pos              (2U)\n#define PWR_CR4_WP3_Msk              (0x1U << PWR_CR4_WP3_Pos)                 /*!< 0x00000004 */\n#define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */\n#define PWR_CR4_WP2_Pos              (1U)\n#define PWR_CR4_WP2_Msk              (0x1U << PWR_CR4_WP2_Pos)                 /*!< 0x00000002 */\n#define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */\n#define PWR_CR4_WP1_Pos              (0U)\n#define PWR_CR4_WP1_Msk              (0x1U << PWR_CR4_WP1_Pos)                 /*!< 0x00000001 */\n#define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */\n\n/********************  Bit definition for PWR_SR1 register  ********************/\n#define PWR_SR1_WUFI_Pos             (15U)\n#define PWR_SR1_WUFI_Msk             (0x1U << PWR_SR1_WUFI_Pos)                /*!< 0x00008000 */\n#define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */\n#define PWR_SR1_SBF_Pos              (8U)\n#define PWR_SR1_SBF_Msk              (0x1U << PWR_SR1_SBF_Pos)                 /*!< 0x00000100 */\n#define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */\n#define PWR_SR1_WUF_Pos              (0U)\n#define PWR_SR1_WUF_Msk              (0x1FU << PWR_SR1_WUF_Pos)                /*!< 0x0000001F */\n#define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */\n#define PWR_SR1_WUF5_Pos             (4U)\n#define PWR_SR1_WUF5_Msk             (0x1U << PWR_SR1_WUF5_Pos)                /*!< 0x00000010 */\n#define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */\n#define PWR_SR1_WUF4_Pos             (3U)\n#define PWR_SR1_WUF4_Msk             (0x1U << PWR_SR1_WUF4_Pos)                /*!< 0x00000008 */\n#define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */\n#define PWR_SR1_WUF3_Pos             (2U)\n#define PWR_SR1_WUF3_Msk             (0x1U << PWR_SR1_WUF3_Pos)                /*!< 0x00000004 */\n#define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */\n#define PWR_SR1_WUF2_Pos             (1U)\n#define PWR_SR1_WUF2_Msk             (0x1U << PWR_SR1_WUF2_Pos)                /*!< 0x00000002 */\n#define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */\n#define PWR_SR1_WUF1_Pos             (0U)\n#define PWR_SR1_WUF1_Msk             (0x1U << PWR_SR1_WUF1_Pos)                /*!< 0x00000001 */\n#define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */\n\n/********************  Bit definition for PWR_SR2 register  ********************/\n#define PWR_SR2_PVMO4_Pos            (15U)\n#define PWR_SR2_PVMO4_Msk            (0x1U << PWR_SR2_PVMO4_Pos)               /*!< 0x00008000 */\n#define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */\n#define PWR_SR2_PVMO3_Pos            (14U)\n#define PWR_SR2_PVMO3_Msk            (0x1U << PWR_SR2_PVMO3_Pos)               /*!< 0x00004000 */\n#define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */\n#define PWR_SR2_PVMO2_Pos            (13U)\n#define PWR_SR2_PVMO2_Msk            (0x1U << PWR_SR2_PVMO2_Pos)               /*!< 0x00002000 */\n#define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */\n#define PWR_SR2_PVMO1_Pos            (12U)\n#define PWR_SR2_PVMO1_Msk            (0x1U << PWR_SR2_PVMO1_Pos)               /*!< 0x00001000 */\n#define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */\n#define PWR_SR2_PVDO_Pos             (11U)\n#define PWR_SR2_PVDO_Msk             (0x1U << PWR_SR2_PVDO_Pos)                /*!< 0x00000800 */\n#define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */\n#define PWR_SR2_VOSF_Pos             (10U)\n#define PWR_SR2_VOSF_Msk             (0x1U << PWR_SR2_VOSF_Pos)                /*!< 0x00000400 */\n#define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */\n#define PWR_SR2_REGLPF_Pos           (9U)\n#define PWR_SR2_REGLPF_Msk           (0x1U << PWR_SR2_REGLPF_Pos)              /*!< 0x00000200 */\n#define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */\n#define PWR_SR2_REGLPS_Pos           (8U)\n#define PWR_SR2_REGLPS_Msk           (0x1U << PWR_SR2_REGLPS_Pos)              /*!< 0x00000100 */\n#define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */\n\n/********************  Bit definition for PWR_SCR register  ********************/\n#define PWR_SCR_CSBF_Pos             (8U)\n#define PWR_SCR_CSBF_Msk             (0x1U << PWR_SCR_CSBF_Pos)                /*!< 0x00000100 */\n#define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */\n#define PWR_SCR_CWUF_Pos             (0U)\n#define PWR_SCR_CWUF_Msk             (0x1FU << PWR_SCR_CWUF_Pos)               /*!< 0x0000001F */\n#define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */\n#define PWR_SCR_CWUF5_Pos            (4U)\n#define PWR_SCR_CWUF5_Msk            (0x1U << PWR_SCR_CWUF5_Pos)               /*!< 0x00000010 */\n#define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */\n#define PWR_SCR_CWUF4_Pos            (3U)\n#define PWR_SCR_CWUF4_Msk            (0x1U << PWR_SCR_CWUF4_Pos)               /*!< 0x00000008 */\n#define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */\n#define PWR_SCR_CWUF3_Pos            (2U)\n#define PWR_SCR_CWUF3_Msk            (0x1U << PWR_SCR_CWUF3_Pos)               /*!< 0x00000004 */\n#define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */\n#define PWR_SCR_CWUF2_Pos            (1U)\n#define PWR_SCR_CWUF2_Msk            (0x1U << PWR_SCR_CWUF2_Pos)               /*!< 0x00000002 */\n#define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */\n#define PWR_SCR_CWUF1_Pos            (0U)\n#define PWR_SCR_CWUF1_Msk            (0x1U << PWR_SCR_CWUF1_Pos)               /*!< 0x00000001 */\n#define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */\n\n/********************  Bit definition for PWR_PUCRA register  ********************/\n#define PWR_PUCRA_PA15_Pos           (15U)\n#define PWR_PUCRA_PA15_Msk           (0x1U << PWR_PUCRA_PA15_Pos)              /*!< 0x00008000 */\n#define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */\n#define PWR_PUCRA_PA13_Pos           (13U)\n#define PWR_PUCRA_PA13_Msk           (0x1U << PWR_PUCRA_PA13_Pos)              /*!< 0x00002000 */\n#define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */\n#define PWR_PUCRA_PA12_Pos           (12U)\n#define PWR_PUCRA_PA12_Msk           (0x1U << PWR_PUCRA_PA12_Pos)              /*!< 0x00001000 */\n#define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */\n#define PWR_PUCRA_PA11_Pos           (11U)\n#define PWR_PUCRA_PA11_Msk           (0x1U << PWR_PUCRA_PA11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */\n#define PWR_PUCRA_PA10_Pos           (10U)\n#define PWR_PUCRA_PA10_Msk           (0x1U << PWR_PUCRA_PA10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */\n#define PWR_PUCRA_PA9_Pos            (9U)\n#define PWR_PUCRA_PA9_Msk            (0x1U << PWR_PUCRA_PA9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */\n#define PWR_PUCRA_PA8_Pos            (8U)\n#define PWR_PUCRA_PA8_Msk            (0x1U << PWR_PUCRA_PA8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */\n#define PWR_PUCRA_PA7_Pos            (7U)\n#define PWR_PUCRA_PA7_Msk            (0x1U << PWR_PUCRA_PA7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */\n#define PWR_PUCRA_PA6_Pos            (6U)\n#define PWR_PUCRA_PA6_Msk            (0x1U << PWR_PUCRA_PA6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */\n#define PWR_PUCRA_PA5_Pos            (5U)\n#define PWR_PUCRA_PA5_Msk            (0x1U << PWR_PUCRA_PA5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */\n#define PWR_PUCRA_PA4_Pos            (4U)\n#define PWR_PUCRA_PA4_Msk            (0x1U << PWR_PUCRA_PA4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */\n#define PWR_PUCRA_PA3_Pos            (3U)\n#define PWR_PUCRA_PA3_Msk            (0x1U << PWR_PUCRA_PA3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */\n#define PWR_PUCRA_PA2_Pos            (2U)\n#define PWR_PUCRA_PA2_Msk            (0x1U << PWR_PUCRA_PA2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */\n#define PWR_PUCRA_PA1_Pos            (1U)\n#define PWR_PUCRA_PA1_Msk            (0x1U << PWR_PUCRA_PA1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */\n#define PWR_PUCRA_PA0_Pos            (0U)\n#define PWR_PUCRA_PA0_Msk            (0x1U << PWR_PUCRA_PA0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRA register  ********************/\n#define PWR_PDCRA_PA14_Pos           (14U)\n#define PWR_PDCRA_PA14_Msk           (0x1U << PWR_PDCRA_PA14_Pos)              /*!< 0x00004000 */\n#define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */\n#define PWR_PDCRA_PA12_Pos           (12U)\n#define PWR_PDCRA_PA12_Msk           (0x1U << PWR_PDCRA_PA12_Pos)              /*!< 0x00001000 */\n#define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */\n#define PWR_PDCRA_PA11_Pos           (11U)\n#define PWR_PDCRA_PA11_Msk           (0x1U << PWR_PDCRA_PA11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */\n#define PWR_PDCRA_PA10_Pos           (10U)\n#define PWR_PDCRA_PA10_Msk           (0x1U << PWR_PDCRA_PA10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */\n#define PWR_PDCRA_PA9_Pos            (9U)\n#define PWR_PDCRA_PA9_Msk            (0x1U << PWR_PDCRA_PA9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */\n#define PWR_PDCRA_PA8_Pos            (8U)\n#define PWR_PDCRA_PA8_Msk            (0x1U << PWR_PDCRA_PA8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */\n#define PWR_PDCRA_PA7_Pos            (7U)\n#define PWR_PDCRA_PA7_Msk            (0x1U << PWR_PDCRA_PA7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */\n#define PWR_PDCRA_PA6_Pos            (6U)\n#define PWR_PDCRA_PA6_Msk            (0x1U << PWR_PDCRA_PA6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */\n#define PWR_PDCRA_PA5_Pos            (5U)\n#define PWR_PDCRA_PA5_Msk            (0x1U << PWR_PDCRA_PA5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */\n#define PWR_PDCRA_PA4_Pos            (4U)\n#define PWR_PDCRA_PA4_Msk            (0x1U << PWR_PDCRA_PA4_Pos)               /*!< 0x00000010 */\n#define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */\n#define PWR_PDCRA_PA3_Pos            (3U)\n#define PWR_PDCRA_PA3_Msk            (0x1U << PWR_PDCRA_PA3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */\n#define PWR_PDCRA_PA2_Pos            (2U)\n#define PWR_PDCRA_PA2_Msk            (0x1U << PWR_PDCRA_PA2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */\n#define PWR_PDCRA_PA1_Pos            (1U)\n#define PWR_PDCRA_PA1_Msk            (0x1U << PWR_PDCRA_PA1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */\n#define PWR_PDCRA_PA0_Pos            (0U)\n#define PWR_PDCRA_PA0_Msk            (0x1U << PWR_PDCRA_PA0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */\n\n/********************  Bit definition for PWR_PUCRB register  ********************/\n#define PWR_PUCRB_PB15_Pos           (15U)\n#define PWR_PUCRB_PB15_Msk           (0x1U << PWR_PUCRB_PB15_Pos)              /*!< 0x00008000 */\n#define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */\n#define PWR_PUCRB_PB14_Pos           (14U)\n#define PWR_PUCRB_PB14_Msk           (0x1U << PWR_PUCRB_PB14_Pos)              /*!< 0x00004000 */\n#define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */\n#define PWR_PUCRB_PB13_Pos           (13U)\n#define PWR_PUCRB_PB13_Msk           (0x1U << PWR_PUCRB_PB13_Pos)              /*!< 0x00002000 */\n#define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */\n#define PWR_PUCRB_PB12_Pos           (12U)\n#define PWR_PUCRB_PB12_Msk           (0x1U << PWR_PUCRB_PB12_Pos)              /*!< 0x00001000 */\n#define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */\n#define PWR_PUCRB_PB11_Pos           (11U)\n#define PWR_PUCRB_PB11_Msk           (0x1U << PWR_PUCRB_PB11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */\n#define PWR_PUCRB_PB10_Pos           (10U)\n#define PWR_PUCRB_PB10_Msk           (0x1U << PWR_PUCRB_PB10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */\n#define PWR_PUCRB_PB9_Pos            (9U)\n#define PWR_PUCRB_PB9_Msk            (0x1U << PWR_PUCRB_PB9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */\n#define PWR_PUCRB_PB8_Pos            (8U)\n#define PWR_PUCRB_PB8_Msk            (0x1U << PWR_PUCRB_PB8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */\n#define PWR_PUCRB_PB7_Pos            (7U)\n#define PWR_PUCRB_PB7_Msk            (0x1U << PWR_PUCRB_PB7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */\n#define PWR_PUCRB_PB6_Pos            (6U)\n#define PWR_PUCRB_PB6_Msk            (0x1U << PWR_PUCRB_PB6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */\n#define PWR_PUCRB_PB5_Pos            (5U)\n#define PWR_PUCRB_PB5_Msk            (0x1U << PWR_PUCRB_PB5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */\n#define PWR_PUCRB_PB4_Pos            (4U)\n#define PWR_PUCRB_PB4_Msk            (0x1U << PWR_PUCRB_PB4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */\n#define PWR_PUCRB_PB3_Pos            (3U)\n#define PWR_PUCRB_PB3_Msk            (0x1U << PWR_PUCRB_PB3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */\n#define PWR_PUCRB_PB2_Pos            (2U)\n#define PWR_PUCRB_PB2_Msk            (0x1U << PWR_PUCRB_PB2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */\n#define PWR_PUCRB_PB1_Pos            (1U)\n#define PWR_PUCRB_PB1_Msk            (0x1U << PWR_PUCRB_PB1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */\n#define PWR_PUCRB_PB0_Pos            (0U)\n#define PWR_PUCRB_PB0_Msk            (0x1U << PWR_PUCRB_PB0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRB register  ********************/\n#define PWR_PDCRB_PB15_Pos           (15U)\n#define PWR_PDCRB_PB15_Msk           (0x1U << PWR_PDCRB_PB15_Pos)              /*!< 0x00008000 */\n#define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */\n#define PWR_PDCRB_PB14_Pos           (14U)\n#define PWR_PDCRB_PB14_Msk           (0x1U << PWR_PDCRB_PB14_Pos)              /*!< 0x00004000 */\n#define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */\n#define PWR_PDCRB_PB13_Pos           (13U)\n#define PWR_PDCRB_PB13_Msk           (0x1U << PWR_PDCRB_PB13_Pos)              /*!< 0x00002000 */\n#define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */\n#define PWR_PDCRB_PB12_Pos           (12U)\n#define PWR_PDCRB_PB12_Msk           (0x1U << PWR_PDCRB_PB12_Pos)              /*!< 0x00001000 */\n#define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */\n#define PWR_PDCRB_PB11_Pos           (11U)\n#define PWR_PDCRB_PB11_Msk           (0x1U << PWR_PDCRB_PB11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */\n#define PWR_PDCRB_PB10_Pos           (10U)\n#define PWR_PDCRB_PB10_Msk           (0x1U << PWR_PDCRB_PB10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */\n#define PWR_PDCRB_PB9_Pos            (9U)\n#define PWR_PDCRB_PB9_Msk            (0x1U << PWR_PDCRB_PB9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */\n#define PWR_PDCRB_PB8_Pos            (8U)\n#define PWR_PDCRB_PB8_Msk            (0x1U << PWR_PDCRB_PB8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */\n#define PWR_PDCRB_PB7_Pos            (7U)\n#define PWR_PDCRB_PB7_Msk            (0x1U << PWR_PDCRB_PB7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */\n#define PWR_PDCRB_PB6_Pos            (6U)\n#define PWR_PDCRB_PB6_Msk            (0x1U << PWR_PDCRB_PB6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */\n#define PWR_PDCRB_PB5_Pos            (5U)\n#define PWR_PDCRB_PB5_Msk            (0x1U << PWR_PDCRB_PB5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */\n#define PWR_PDCRB_PB3_Pos            (3U)\n#define PWR_PDCRB_PB3_Msk            (0x1U << PWR_PDCRB_PB3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */\n#define PWR_PDCRB_PB2_Pos            (2U)\n#define PWR_PDCRB_PB2_Msk            (0x1U << PWR_PDCRB_PB2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */\n#define PWR_PDCRB_PB1_Pos            (1U)\n#define PWR_PDCRB_PB1_Msk            (0x1U << PWR_PDCRB_PB1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */\n#define PWR_PDCRB_PB0_Pos            (0U)\n#define PWR_PDCRB_PB0_Msk            (0x1U << PWR_PDCRB_PB0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */\n\n/********************  Bit definition for PWR_PUCRC register  ********************/\n#define PWR_PUCRC_PC15_Pos           (15U)\n#define PWR_PUCRC_PC15_Msk           (0x1U << PWR_PUCRC_PC15_Pos)              /*!< 0x00008000 */\n#define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */\n#define PWR_PUCRC_PC14_Pos           (14U)\n#define PWR_PUCRC_PC14_Msk           (0x1U << PWR_PUCRC_PC14_Pos)              /*!< 0x00004000 */\n#define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */\n#define PWR_PUCRC_PC13_Pos           (13U)\n#define PWR_PUCRC_PC13_Msk           (0x1U << PWR_PUCRC_PC13_Pos)              /*!< 0x00002000 */\n#define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */\n#define PWR_PUCRC_PC12_Pos           (12U)\n#define PWR_PUCRC_PC12_Msk           (0x1U << PWR_PUCRC_PC12_Pos)              /*!< 0x00001000 */\n#define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */\n#define PWR_PUCRC_PC11_Pos           (11U)\n#define PWR_PUCRC_PC11_Msk           (0x1U << PWR_PUCRC_PC11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */\n#define PWR_PUCRC_PC10_Pos           (10U)\n#define PWR_PUCRC_PC10_Msk           (0x1U << PWR_PUCRC_PC10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */\n#define PWR_PUCRC_PC9_Pos            (9U)\n#define PWR_PUCRC_PC9_Msk            (0x1U << PWR_PUCRC_PC9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */\n#define PWR_PUCRC_PC8_Pos            (8U)\n#define PWR_PUCRC_PC8_Msk            (0x1U << PWR_PUCRC_PC8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */\n#define PWR_PUCRC_PC7_Pos            (7U)\n#define PWR_PUCRC_PC7_Msk            (0x1U << PWR_PUCRC_PC7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */\n#define PWR_PUCRC_PC6_Pos            (6U)\n#define PWR_PUCRC_PC6_Msk            (0x1U << PWR_PUCRC_PC6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */\n#define PWR_PUCRC_PC5_Pos            (5U)\n#define PWR_PUCRC_PC5_Msk            (0x1U << PWR_PUCRC_PC5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */\n#define PWR_PUCRC_PC4_Pos            (4U)\n#define PWR_PUCRC_PC4_Msk            (0x1U << PWR_PUCRC_PC4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */\n#define PWR_PUCRC_PC3_Pos            (3U)\n#define PWR_PUCRC_PC3_Msk            (0x1U << PWR_PUCRC_PC3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */\n#define PWR_PUCRC_PC2_Pos            (2U)\n#define PWR_PUCRC_PC2_Msk            (0x1U << PWR_PUCRC_PC2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */\n#define PWR_PUCRC_PC1_Pos            (1U)\n#define PWR_PUCRC_PC1_Msk            (0x1U << PWR_PUCRC_PC1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */\n#define PWR_PUCRC_PC0_Pos            (0U)\n#define PWR_PUCRC_PC0_Msk            (0x1U << PWR_PUCRC_PC0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRC register  ********************/\n#define PWR_PDCRC_PC15_Pos           (15U)\n#define PWR_PDCRC_PC15_Msk           (0x1U << PWR_PDCRC_PC15_Pos)              /*!< 0x00008000 */\n#define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */\n#define PWR_PDCRC_PC14_Pos           (14U)\n#define PWR_PDCRC_PC14_Msk           (0x1U << PWR_PDCRC_PC14_Pos)              /*!< 0x00004000 */\n#define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */\n#define PWR_PDCRC_PC13_Pos           (13U)\n#define PWR_PDCRC_PC13_Msk           (0x1U << PWR_PDCRC_PC13_Pos)              /*!< 0x00002000 */\n#define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */\n#define PWR_PDCRC_PC12_Pos           (12U)\n#define PWR_PDCRC_PC12_Msk           (0x1U << PWR_PDCRC_PC12_Pos)              /*!< 0x00001000 */\n#define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */\n#define PWR_PDCRC_PC11_Pos           (11U)\n#define PWR_PDCRC_PC11_Msk           (0x1U << PWR_PDCRC_PC11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */\n#define PWR_PDCRC_PC10_Pos           (10U)\n#define PWR_PDCRC_PC10_Msk           (0x1U << PWR_PDCRC_PC10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */\n#define PWR_PDCRC_PC9_Pos            (9U)\n#define PWR_PDCRC_PC9_Msk            (0x1U << PWR_PDCRC_PC9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */\n#define PWR_PDCRC_PC8_Pos            (8U)\n#define PWR_PDCRC_PC8_Msk            (0x1U << PWR_PDCRC_PC8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */\n#define PWR_PDCRC_PC7_Pos            (7U)\n#define PWR_PDCRC_PC7_Msk            (0x1U << PWR_PDCRC_PC7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */\n#define PWR_PDCRC_PC6_Pos            (6U)\n#define PWR_PDCRC_PC6_Msk            (0x1U << PWR_PDCRC_PC6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */\n#define PWR_PDCRC_PC5_Pos            (5U)\n#define PWR_PDCRC_PC5_Msk            (0x1U << PWR_PDCRC_PC5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */\n#define PWR_PDCRC_PC4_Pos            (4U)\n#define PWR_PDCRC_PC4_Msk            (0x1U << PWR_PDCRC_PC4_Pos)               /*!< 0x00000010 */\n#define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */\n#define PWR_PDCRC_PC3_Pos            (3U)\n#define PWR_PDCRC_PC3_Msk            (0x1U << PWR_PDCRC_PC3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */\n#define PWR_PDCRC_PC2_Pos            (2U)\n#define PWR_PDCRC_PC2_Msk            (0x1U << PWR_PDCRC_PC2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */\n#define PWR_PDCRC_PC1_Pos            (1U)\n#define PWR_PDCRC_PC1_Msk            (0x1U << PWR_PDCRC_PC1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */\n#define PWR_PDCRC_PC0_Pos            (0U)\n#define PWR_PDCRC_PC0_Msk            (0x1U << PWR_PDCRC_PC0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */\n\n/********************  Bit definition for PWR_PUCRD register  ********************/\n#define PWR_PUCRD_PD15_Pos           (15U)\n#define PWR_PUCRD_PD15_Msk           (0x1U << PWR_PUCRD_PD15_Pos)              /*!< 0x00008000 */\n#define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */\n#define PWR_PUCRD_PD14_Pos           (14U)\n#define PWR_PUCRD_PD14_Msk           (0x1U << PWR_PUCRD_PD14_Pos)              /*!< 0x00004000 */\n#define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */\n#define PWR_PUCRD_PD13_Pos           (13U)\n#define PWR_PUCRD_PD13_Msk           (0x1U << PWR_PUCRD_PD13_Pos)              /*!< 0x00002000 */\n#define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */\n#define PWR_PUCRD_PD12_Pos           (12U)\n#define PWR_PUCRD_PD12_Msk           (0x1U << PWR_PUCRD_PD12_Pos)              /*!< 0x00001000 */\n#define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */\n#define PWR_PUCRD_PD11_Pos           (11U)\n#define PWR_PUCRD_PD11_Msk           (0x1U << PWR_PUCRD_PD11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */\n#define PWR_PUCRD_PD10_Pos           (10U)\n#define PWR_PUCRD_PD10_Msk           (0x1U << PWR_PUCRD_PD10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */\n#define PWR_PUCRD_PD9_Pos            (9U)\n#define PWR_PUCRD_PD9_Msk            (0x1U << PWR_PUCRD_PD9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */\n#define PWR_PUCRD_PD8_Pos            (8U)\n#define PWR_PUCRD_PD8_Msk            (0x1U << PWR_PUCRD_PD8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */\n#define PWR_PUCRD_PD7_Pos            (7U)\n#define PWR_PUCRD_PD7_Msk            (0x1U << PWR_PUCRD_PD7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */\n#define PWR_PUCRD_PD6_Pos            (6U)\n#define PWR_PUCRD_PD6_Msk            (0x1U << PWR_PUCRD_PD6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */\n#define PWR_PUCRD_PD5_Pos            (5U)\n#define PWR_PUCRD_PD5_Msk            (0x1U << PWR_PUCRD_PD5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */\n#define PWR_PUCRD_PD4_Pos            (4U)\n#define PWR_PUCRD_PD4_Msk            (0x1U << PWR_PUCRD_PD4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */\n#define PWR_PUCRD_PD3_Pos            (3U)\n#define PWR_PUCRD_PD3_Msk            (0x1U << PWR_PUCRD_PD3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */\n#define PWR_PUCRD_PD2_Pos            (2U)\n#define PWR_PUCRD_PD2_Msk            (0x1U << PWR_PUCRD_PD2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */\n#define PWR_PUCRD_PD1_Pos            (1U)\n#define PWR_PUCRD_PD1_Msk            (0x1U << PWR_PUCRD_PD1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */\n#define PWR_PUCRD_PD0_Pos            (0U)\n#define PWR_PUCRD_PD0_Msk            (0x1U << PWR_PUCRD_PD0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRD register  ********************/\n#define PWR_PDCRD_PD15_Pos           (15U)\n#define PWR_PDCRD_PD15_Msk           (0x1U << PWR_PDCRD_PD15_Pos)              /*!< 0x00008000 */\n#define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */\n#define PWR_PDCRD_PD14_Pos           (14U)\n#define PWR_PDCRD_PD14_Msk           (0x1U << PWR_PDCRD_PD14_Pos)              /*!< 0x00004000 */\n#define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */\n#define PWR_PDCRD_PD13_Pos           (13U)\n#define PWR_PDCRD_PD13_Msk           (0x1U << PWR_PDCRD_PD13_Pos)              /*!< 0x00002000 */\n#define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */\n#define PWR_PDCRD_PD12_Pos           (12U)\n#define PWR_PDCRD_PD12_Msk           (0x1U << PWR_PDCRD_PD12_Pos)              /*!< 0x00001000 */\n#define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */\n#define PWR_PDCRD_PD11_Pos           (11U)\n#define PWR_PDCRD_PD11_Msk           (0x1U << PWR_PDCRD_PD11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */\n#define PWR_PDCRD_PD10_Pos           (10U)\n#define PWR_PDCRD_PD10_Msk           (0x1U << PWR_PDCRD_PD10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */\n#define PWR_PDCRD_PD9_Pos            (9U)\n#define PWR_PDCRD_PD9_Msk            (0x1U << PWR_PDCRD_PD9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */\n#define PWR_PDCRD_PD8_Pos            (8U)\n#define PWR_PDCRD_PD8_Msk            (0x1U << PWR_PDCRD_PD8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */\n#define PWR_PDCRD_PD7_Pos            (7U)\n#define PWR_PDCRD_PD7_Msk            (0x1U << PWR_PDCRD_PD7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */\n#define PWR_PDCRD_PD6_Pos            (6U)\n#define PWR_PDCRD_PD6_Msk            (0x1U << PWR_PDCRD_PD6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */\n#define PWR_PDCRD_PD5_Pos            (5U)\n#define PWR_PDCRD_PD5_Msk            (0x1U << PWR_PDCRD_PD5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */\n#define PWR_PDCRD_PD4_Pos            (4U)\n#define PWR_PDCRD_PD4_Msk            (0x1U << PWR_PDCRD_PD4_Pos)               /*!< 0x00000010 */\n#define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */\n#define PWR_PDCRD_PD3_Pos            (3U)\n#define PWR_PDCRD_PD3_Msk            (0x1U << PWR_PDCRD_PD3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */\n#define PWR_PDCRD_PD2_Pos            (2U)\n#define PWR_PDCRD_PD2_Msk            (0x1U << PWR_PDCRD_PD2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */\n#define PWR_PDCRD_PD1_Pos            (1U)\n#define PWR_PDCRD_PD1_Msk            (0x1U << PWR_PDCRD_PD1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */\n#define PWR_PDCRD_PD0_Pos            (0U)\n#define PWR_PDCRD_PD0_Msk            (0x1U << PWR_PDCRD_PD0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */\n\n/********************  Bit definition for PWR_PUCRE register  ********************/\n#define PWR_PUCRE_PE15_Pos           (15U)\n#define PWR_PUCRE_PE15_Msk           (0x1U << PWR_PUCRE_PE15_Pos)              /*!< 0x00008000 */\n#define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */\n#define PWR_PUCRE_PE14_Pos           (14U)\n#define PWR_PUCRE_PE14_Msk           (0x1U << PWR_PUCRE_PE14_Pos)              /*!< 0x00004000 */\n#define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */\n#define PWR_PUCRE_PE13_Pos           (13U)\n#define PWR_PUCRE_PE13_Msk           (0x1U << PWR_PUCRE_PE13_Pos)              /*!< 0x00002000 */\n#define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */\n#define PWR_PUCRE_PE12_Pos           (12U)\n#define PWR_PUCRE_PE12_Msk           (0x1U << PWR_PUCRE_PE12_Pos)              /*!< 0x00001000 */\n#define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */\n#define PWR_PUCRE_PE11_Pos           (11U)\n#define PWR_PUCRE_PE11_Msk           (0x1U << PWR_PUCRE_PE11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */\n#define PWR_PUCRE_PE10_Pos           (10U)\n#define PWR_PUCRE_PE10_Msk           (0x1U << PWR_PUCRE_PE10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */\n#define PWR_PUCRE_PE9_Pos            (9U)\n#define PWR_PUCRE_PE9_Msk            (0x1U << PWR_PUCRE_PE9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */\n#define PWR_PUCRE_PE8_Pos            (8U)\n#define PWR_PUCRE_PE8_Msk            (0x1U << PWR_PUCRE_PE8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */\n#define PWR_PUCRE_PE7_Pos            (7U)\n#define PWR_PUCRE_PE7_Msk            (0x1U << PWR_PUCRE_PE7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */\n#define PWR_PUCRE_PE6_Pos            (6U)\n#define PWR_PUCRE_PE6_Msk            (0x1U << PWR_PUCRE_PE6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */\n#define PWR_PUCRE_PE5_Pos            (5U)\n#define PWR_PUCRE_PE5_Msk            (0x1U << PWR_PUCRE_PE5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */\n#define PWR_PUCRE_PE4_Pos            (4U)\n#define PWR_PUCRE_PE4_Msk            (0x1U << PWR_PUCRE_PE4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */\n#define PWR_PUCRE_PE3_Pos            (3U)\n#define PWR_PUCRE_PE3_Msk            (0x1U << PWR_PUCRE_PE3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */\n#define PWR_PUCRE_PE2_Pos            (2U)\n#define PWR_PUCRE_PE2_Msk            (0x1U << PWR_PUCRE_PE2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */\n#define PWR_PUCRE_PE1_Pos            (1U)\n#define PWR_PUCRE_PE1_Msk            (0x1U << PWR_PUCRE_PE1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */\n#define PWR_PUCRE_PE0_Pos            (0U)\n#define PWR_PUCRE_PE0_Msk            (0x1U << PWR_PUCRE_PE0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRE register  ********************/\n#define PWR_PDCRE_PE15_Pos           (15U)\n#define PWR_PDCRE_PE15_Msk           (0x1U << PWR_PDCRE_PE15_Pos)              /*!< 0x00008000 */\n#define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */\n#define PWR_PDCRE_PE14_Pos           (14U)\n#define PWR_PDCRE_PE14_Msk           (0x1U << PWR_PDCRE_PE14_Pos)              /*!< 0x00004000 */\n#define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */\n#define PWR_PDCRE_PE13_Pos           (13U)\n#define PWR_PDCRE_PE13_Msk           (0x1U << PWR_PDCRE_PE13_Pos)              /*!< 0x00002000 */\n#define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */\n#define PWR_PDCRE_PE12_Pos           (12U)\n#define PWR_PDCRE_PE12_Msk           (0x1U << PWR_PDCRE_PE12_Pos)              /*!< 0x00001000 */\n#define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */\n#define PWR_PDCRE_PE11_Pos           (11U)\n#define PWR_PDCRE_PE11_Msk           (0x1U << PWR_PDCRE_PE11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */\n#define PWR_PDCRE_PE10_Pos           (10U)\n#define PWR_PDCRE_PE10_Msk           (0x1U << PWR_PDCRE_PE10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */\n#define PWR_PDCRE_PE9_Pos            (9U)\n#define PWR_PDCRE_PE9_Msk            (0x1U << PWR_PDCRE_PE9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */\n#define PWR_PDCRE_PE8_Pos            (8U)\n#define PWR_PDCRE_PE8_Msk            (0x1U << PWR_PDCRE_PE8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */\n#define PWR_PDCRE_PE7_Pos            (7U)\n#define PWR_PDCRE_PE7_Msk            (0x1U << PWR_PDCRE_PE7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */\n#define PWR_PDCRE_PE6_Pos            (6U)\n#define PWR_PDCRE_PE6_Msk            (0x1U << PWR_PDCRE_PE6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */\n#define PWR_PDCRE_PE5_Pos            (5U)\n#define PWR_PDCRE_PE5_Msk            (0x1U << PWR_PDCRE_PE5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */\n#define PWR_PDCRE_PE4_Pos            (4U)\n#define PWR_PDCRE_PE4_Msk            (0x1U << PWR_PDCRE_PE4_Pos)               /*!< 0x00000010 */\n#define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */\n#define PWR_PDCRE_PE3_Pos            (3U)\n#define PWR_PDCRE_PE3_Msk            (0x1U << PWR_PDCRE_PE3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */\n#define PWR_PDCRE_PE2_Pos            (2U)\n#define PWR_PDCRE_PE2_Msk            (0x1U << PWR_PDCRE_PE2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */\n#define PWR_PDCRE_PE1_Pos            (1U)\n#define PWR_PDCRE_PE1_Msk            (0x1U << PWR_PDCRE_PE1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */\n#define PWR_PDCRE_PE0_Pos            (0U)\n#define PWR_PDCRE_PE0_Msk            (0x1U << PWR_PDCRE_PE0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */\n\n/********************  Bit definition for PWR_PUCRF register  ********************/\n#define PWR_PUCRF_PF15_Pos           (15U)\n#define PWR_PUCRF_PF15_Msk           (0x1U << PWR_PUCRF_PF15_Pos)              /*!< 0x00008000 */\n#define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */\n#define PWR_PUCRF_PF14_Pos           (14U)\n#define PWR_PUCRF_PF14_Msk           (0x1U << PWR_PUCRF_PF14_Pos)              /*!< 0x00004000 */\n#define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */\n#define PWR_PUCRF_PF13_Pos           (13U)\n#define PWR_PUCRF_PF13_Msk           (0x1U << PWR_PUCRF_PF13_Pos)              /*!< 0x00002000 */\n#define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */\n#define PWR_PUCRF_PF12_Pos           (12U)\n#define PWR_PUCRF_PF12_Msk           (0x1U << PWR_PUCRF_PF12_Pos)              /*!< 0x00001000 */\n#define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */\n#define PWR_PUCRF_PF11_Pos           (11U)\n#define PWR_PUCRF_PF11_Msk           (0x1U << PWR_PUCRF_PF11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */\n#define PWR_PUCRF_PF10_Pos           (10U)\n#define PWR_PUCRF_PF10_Msk           (0x1U << PWR_PUCRF_PF10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */\n#define PWR_PUCRF_PF9_Pos            (9U)\n#define PWR_PUCRF_PF9_Msk            (0x1U << PWR_PUCRF_PF9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */\n#define PWR_PUCRF_PF8_Pos            (8U)\n#define PWR_PUCRF_PF8_Msk            (0x1U << PWR_PUCRF_PF8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */\n#define PWR_PUCRF_PF7_Pos            (7U)\n#define PWR_PUCRF_PF7_Msk            (0x1U << PWR_PUCRF_PF7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */\n#define PWR_PUCRF_PF6_Pos            (6U)\n#define PWR_PUCRF_PF6_Msk            (0x1U << PWR_PUCRF_PF6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */\n#define PWR_PUCRF_PF5_Pos            (5U)\n#define PWR_PUCRF_PF5_Msk            (0x1U << PWR_PUCRF_PF5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */\n#define PWR_PUCRF_PF4_Pos            (4U)\n#define PWR_PUCRF_PF4_Msk            (0x1U << PWR_PUCRF_PF4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */\n#define PWR_PUCRF_PF3_Pos            (3U)\n#define PWR_PUCRF_PF3_Msk            (0x1U << PWR_PUCRF_PF3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */\n#define PWR_PUCRF_PF2_Pos            (2U)\n#define PWR_PUCRF_PF2_Msk            (0x1U << PWR_PUCRF_PF2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */\n#define PWR_PUCRF_PF1_Pos            (1U)\n#define PWR_PUCRF_PF1_Msk            (0x1U << PWR_PUCRF_PF1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */\n#define PWR_PUCRF_PF0_Pos            (0U)\n#define PWR_PUCRF_PF0_Msk            (0x1U << PWR_PUCRF_PF0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRF register  ********************/\n#define PWR_PDCRF_PF15_Pos           (15U)\n#define PWR_PDCRF_PF15_Msk           (0x1U << PWR_PDCRF_PF15_Pos)              /*!< 0x00008000 */\n#define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */\n#define PWR_PDCRF_PF14_Pos           (14U)\n#define PWR_PDCRF_PF14_Msk           (0x1U << PWR_PDCRF_PF14_Pos)              /*!< 0x00004000 */\n#define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */\n#define PWR_PDCRF_PF13_Pos           (13U)\n#define PWR_PDCRF_PF13_Msk           (0x1U << PWR_PDCRF_PF13_Pos)              /*!< 0x00002000 */\n#define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */\n#define PWR_PDCRF_PF12_Pos           (12U)\n#define PWR_PDCRF_PF12_Msk           (0x1U << PWR_PDCRF_PF12_Pos)              /*!< 0x00001000 */\n#define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */\n#define PWR_PDCRF_PF11_Pos           (11U)\n#define PWR_PDCRF_PF11_Msk           (0x1U << PWR_PDCRF_PF11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */\n#define PWR_PDCRF_PF10_Pos           (10U)\n#define PWR_PDCRF_PF10_Msk           (0x1U << PWR_PDCRF_PF10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */\n#define PWR_PDCRF_PF9_Pos            (9U)\n#define PWR_PDCRF_PF9_Msk            (0x1U << PWR_PDCRF_PF9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */\n#define PWR_PDCRF_PF8_Pos            (8U)\n#define PWR_PDCRF_PF8_Msk            (0x1U << PWR_PDCRF_PF8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */\n#define PWR_PDCRF_PF7_Pos            (7U)\n#define PWR_PDCRF_PF7_Msk            (0x1U << PWR_PDCRF_PF7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */\n#define PWR_PDCRF_PF6_Pos            (6U)\n#define PWR_PDCRF_PF6_Msk            (0x1U << PWR_PDCRF_PF6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */\n#define PWR_PDCRF_PF5_Pos            (5U)\n#define PWR_PDCRF_PF5_Msk            (0x1U << PWR_PDCRF_PF5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */\n#define PWR_PDCRF_PF4_Pos            (4U)\n#define PWR_PDCRF_PF4_Msk            (0x1U << PWR_PDCRF_PF4_Pos)               /*!< 0x00000010 */\n#define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */\n#define PWR_PDCRF_PF3_Pos            (3U)\n#define PWR_PDCRF_PF3_Msk            (0x1U << PWR_PDCRF_PF3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */\n#define PWR_PDCRF_PF2_Pos            (2U)\n#define PWR_PDCRF_PF2_Msk            (0x1U << PWR_PDCRF_PF2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */\n#define PWR_PDCRF_PF1_Pos            (1U)\n#define PWR_PDCRF_PF1_Msk            (0x1U << PWR_PDCRF_PF1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */\n#define PWR_PDCRF_PF0_Pos            (0U)\n#define PWR_PDCRF_PF0_Msk            (0x1U << PWR_PDCRF_PF0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */\n\n/********************  Bit definition for PWR_PUCRG register  ********************/\n#define PWR_PUCRG_PG15_Pos           (15U)\n#define PWR_PUCRG_PG15_Msk           (0x1U << PWR_PUCRG_PG15_Pos)              /*!< 0x00008000 */\n#define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */\n#define PWR_PUCRG_PG14_Pos           (14U)\n#define PWR_PUCRG_PG14_Msk           (0x1U << PWR_PUCRG_PG14_Pos)              /*!< 0x00004000 */\n#define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */\n#define PWR_PUCRG_PG13_Pos           (13U)\n#define PWR_PUCRG_PG13_Msk           (0x1U << PWR_PUCRG_PG13_Pos)              /*!< 0x00002000 */\n#define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */\n#define PWR_PUCRG_PG12_Pos           (12U)\n#define PWR_PUCRG_PG12_Msk           (0x1U << PWR_PUCRG_PG12_Pos)              /*!< 0x00001000 */\n#define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */\n#define PWR_PUCRG_PG11_Pos           (11U)\n#define PWR_PUCRG_PG11_Msk           (0x1U << PWR_PUCRG_PG11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */\n#define PWR_PUCRG_PG10_Pos           (10U)\n#define PWR_PUCRG_PG10_Msk           (0x1U << PWR_PUCRG_PG10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */\n#define PWR_PUCRG_PG9_Pos            (9U)\n#define PWR_PUCRG_PG9_Msk            (0x1U << PWR_PUCRG_PG9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */\n#define PWR_PUCRG_PG8_Pos            (8U)\n#define PWR_PUCRG_PG8_Msk            (0x1U << PWR_PUCRG_PG8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */\n#define PWR_PUCRG_PG7_Pos            (7U)\n#define PWR_PUCRG_PG7_Msk            (0x1U << PWR_PUCRG_PG7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */\n#define PWR_PUCRG_PG6_Pos            (6U)\n#define PWR_PUCRG_PG6_Msk            (0x1U << PWR_PUCRG_PG6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */\n#define PWR_PUCRG_PG5_Pos            (5U)\n#define PWR_PUCRG_PG5_Msk            (0x1U << PWR_PUCRG_PG5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */\n#define PWR_PUCRG_PG4_Pos            (4U)\n#define PWR_PUCRG_PG4_Msk            (0x1U << PWR_PUCRG_PG4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */\n#define PWR_PUCRG_PG3_Pos            (3U)\n#define PWR_PUCRG_PG3_Msk            (0x1U << PWR_PUCRG_PG3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */\n#define PWR_PUCRG_PG2_Pos            (2U)\n#define PWR_PUCRG_PG2_Msk            (0x1U << PWR_PUCRG_PG2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */\n#define PWR_PUCRG_PG1_Pos            (1U)\n#define PWR_PUCRG_PG1_Msk            (0x1U << PWR_PUCRG_PG1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */\n#define PWR_PUCRG_PG0_Pos            (0U)\n#define PWR_PUCRG_PG0_Msk            (0x1U << PWR_PUCRG_PG0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRG register  ********************/\n#define PWR_PDCRG_PG15_Pos           (15U)\n#define PWR_PDCRG_PG15_Msk           (0x1U << PWR_PDCRG_PG15_Pos)              /*!< 0x00008000 */\n#define PWR_PDCRG_PG15               PWR_PDCRG_PG15_Msk                        /*!< Port PG15 Pull-Down set */\n#define PWR_PDCRG_PG14_Pos           (14U)\n#define PWR_PDCRG_PG14_Msk           (0x1U << PWR_PDCRG_PG14_Pos)              /*!< 0x00004000 */\n#define PWR_PDCRG_PG14               PWR_PDCRG_PG14_Msk                        /*!< Port PG14 Pull-Down set */\n#define PWR_PDCRG_PG13_Pos           (13U)\n#define PWR_PDCRG_PG13_Msk           (0x1U << PWR_PDCRG_PG13_Pos)              /*!< 0x00002000 */\n#define PWR_PDCRG_PG13               PWR_PDCRG_PG13_Msk                        /*!< Port PG13 Pull-Down set */\n#define PWR_PDCRG_PG12_Pos           (12U)\n#define PWR_PDCRG_PG12_Msk           (0x1U << PWR_PDCRG_PG12_Pos)              /*!< 0x00001000 */\n#define PWR_PDCRG_PG12               PWR_PDCRG_PG12_Msk                        /*!< Port PG12 Pull-Down set */\n#define PWR_PDCRG_PG11_Pos           (11U)\n#define PWR_PDCRG_PG11_Msk           (0x1U << PWR_PDCRG_PG11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRG_PG11               PWR_PDCRG_PG11_Msk                        /*!< Port PG11 Pull-Down set */\n#define PWR_PDCRG_PG10_Pos           (10U)\n#define PWR_PDCRG_PG10_Msk           (0x1U << PWR_PDCRG_PG10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */\n#define PWR_PDCRG_PG9_Pos            (9U)\n#define PWR_PDCRG_PG9_Msk            (0x1U << PWR_PDCRG_PG9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */\n#define PWR_PDCRG_PG8_Pos            (8U)\n#define PWR_PDCRG_PG8_Msk            (0x1U << PWR_PDCRG_PG8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */\n#define PWR_PDCRG_PG7_Pos            (7U)\n#define PWR_PDCRG_PG7_Msk            (0x1U << PWR_PDCRG_PG7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */\n#define PWR_PDCRG_PG6_Pos            (6U)\n#define PWR_PDCRG_PG6_Msk            (0x1U << PWR_PDCRG_PG6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */\n#define PWR_PDCRG_PG5_Pos            (5U)\n#define PWR_PDCRG_PG5_Msk            (0x1U << PWR_PDCRG_PG5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */\n#define PWR_PDCRG_PG4_Pos            (4U)\n#define PWR_PDCRG_PG4_Msk            (0x1U << PWR_PDCRG_PG4_Pos)               /*!< 0x00000010 */\n#define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */\n#define PWR_PDCRG_PG3_Pos            (3U)\n#define PWR_PDCRG_PG3_Msk            (0x1U << PWR_PDCRG_PG3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */\n#define PWR_PDCRG_PG2_Pos            (2U)\n#define PWR_PDCRG_PG2_Msk            (0x1U << PWR_PDCRG_PG2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */\n#define PWR_PDCRG_PG1_Pos            (1U)\n#define PWR_PDCRG_PG1_Msk            (0x1U << PWR_PDCRG_PG1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */\n#define PWR_PDCRG_PG0_Pos            (0U)\n#define PWR_PDCRG_PG0_Msk            (0x1U << PWR_PDCRG_PG0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */\n\n/********************  Bit definition for PWR_PUCRH register  ********************/\n#define PWR_PUCRH_PH15_Pos           (15U)\n#define PWR_PUCRH_PH15_Msk           (0x1U << PWR_PUCRH_PH15_Pos)              /*!< 0x00008000 */\n#define PWR_PUCRH_PH15               PWR_PUCRH_PH15_Msk                        /*!< Port PH15 Pull-Up set  */\n#define PWR_PUCRH_PH14_Pos           (14U)\n#define PWR_PUCRH_PH14_Msk           (0x1U << PWR_PUCRH_PH14_Pos)              /*!< 0x00004000 */\n#define PWR_PUCRH_PH14               PWR_PUCRH_PH14_Msk                        /*!< Port PH14 Pull-Up set  */\n#define PWR_PUCRH_PH13_Pos           (13U)\n#define PWR_PUCRH_PH13_Msk           (0x1U << PWR_PUCRH_PH13_Pos)              /*!< 0x00002000 */\n#define PWR_PUCRH_PH13               PWR_PUCRH_PH13_Msk                        /*!< Port PH13 Pull-Up set  */\n#define PWR_PUCRH_PH12_Pos           (12U)\n#define PWR_PUCRH_PH12_Msk           (0x1U << PWR_PUCRH_PH12_Pos)              /*!< 0x00001000 */\n#define PWR_PUCRH_PH12               PWR_PUCRH_PH12_Msk                        /*!< Port PH12 Pull-Up set  */\n#define PWR_PUCRH_PH11_Pos           (11U)\n#define PWR_PUCRH_PH11_Msk           (0x1U << PWR_PUCRH_PH11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRH_PH11               PWR_PUCRH_PH11_Msk                        /*!< Port PH11 Pull-Up set  */\n#define PWR_PUCRH_PH10_Pos           (10U)\n#define PWR_PUCRH_PH10_Msk           (0x1U << PWR_PUCRH_PH10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRH_PH10               PWR_PUCRH_PH10_Msk                        /*!< Port PH10 Pull-Up set  */\n#define PWR_PUCRH_PH9_Pos            (9U)\n#define PWR_PUCRH_PH9_Msk            (0x1U << PWR_PUCRH_PH9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRH_PH9                PWR_PUCRH_PH9_Msk                         /*!< Port PH9 Pull-Up set  */\n#define PWR_PUCRH_PH8_Pos            (8U)\n#define PWR_PUCRH_PH8_Msk            (0x1U << PWR_PUCRH_PH8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRH_PH8                PWR_PUCRH_PH8_Msk                         /*!< Port PH8 Pull-Up set  */\n#define PWR_PUCRH_PH7_Pos            (7U)\n#define PWR_PUCRH_PH7_Msk            (0x1U << PWR_PUCRH_PH7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRH_PH7                PWR_PUCRH_PH7_Msk                         /*!< Port PH7 Pull-Up set  */\n#define PWR_PUCRH_PH6_Pos            (6U)\n#define PWR_PUCRH_PH6_Msk            (0x1U << PWR_PUCRH_PH6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRH_PH6                PWR_PUCRH_PH6_Msk                         /*!< Port PH6 Pull-Up set  */\n#define PWR_PUCRH_PH5_Pos            (5U)\n#define PWR_PUCRH_PH5_Msk            (0x1U << PWR_PUCRH_PH5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRH_PH5                PWR_PUCRH_PH5_Msk                         /*!< Port PH5 Pull-Up set  */\n#define PWR_PUCRH_PH4_Pos            (4U)\n#define PWR_PUCRH_PH4_Msk            (0x1U << PWR_PUCRH_PH4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRH_PH4                PWR_PUCRH_PH4_Msk                         /*!< Port PH4 Pull-Up set  */\n#define PWR_PUCRH_PH3_Pos            (3U)\n#define PWR_PUCRH_PH3_Msk            (0x1U << PWR_PUCRH_PH3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRH_PH3                PWR_PUCRH_PH3_Msk                         /*!< Port PH3 Pull-Up set  */\n#define PWR_PUCRH_PH2_Pos            (2U)\n#define PWR_PUCRH_PH2_Msk            (0x1U << PWR_PUCRH_PH2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRH_PH2                PWR_PUCRH_PH2_Msk                         /*!< Port PH2 Pull-Up set  */\n#define PWR_PUCRH_PH1_Pos            (1U)\n#define PWR_PUCRH_PH1_Msk            (0x1U << PWR_PUCRH_PH1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */\n#define PWR_PUCRH_PH0_Pos            (0U)\n#define PWR_PUCRH_PH0_Msk            (0x1U << PWR_PUCRH_PH0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRH register  ********************/\n#define PWR_PDCRH_PH15_Pos           (15U)\n#define PWR_PDCRH_PH15_Msk           (0x1U << PWR_PDCRH_PH15_Pos)              /*!< 0x00008000 */\n#define PWR_PDCRH_PH15               PWR_PDCRH_PH15_Msk                        /*!< Port PH15 Pull-Down set  */\n#define PWR_PDCRH_PH14_Pos           (14U)\n#define PWR_PDCRH_PH14_Msk           (0x1U << PWR_PDCRH_PH14_Pos)              /*!< 0x00004000 */\n#define PWR_PDCRH_PH14               PWR_PDCRH_PH14_Msk                        /*!< Port PH14 Pull-Down set  */\n#define PWR_PDCRH_PH13_Pos           (13U)\n#define PWR_PDCRH_PH13_Msk           (0x1U << PWR_PDCRH_PH13_Pos)              /*!< 0x00002000 */\n#define PWR_PDCRH_PH13               PWR_PDCRH_PH13_Msk                        /*!< Port PH13 Pull-Down set  */\n#define PWR_PDCRH_PH12_Pos           (12U)\n#define PWR_PDCRH_PH12_Msk           (0x1U << PWR_PDCRH_PH12_Pos)              /*!< 0x00001000 */\n#define PWR_PDCRH_PH12               PWR_PDCRH_PH12_Msk                        /*!< Port PH12 Pull-Down set  */\n#define PWR_PDCRH_PH11_Pos           (11U)\n#define PWR_PDCRH_PH11_Msk           (0x1U << PWR_PDCRH_PH11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRH_PH11               PWR_PDCRH_PH11_Msk                        /*!< Port PH11 Pull-Down set  */\n#define PWR_PDCRH_PH10_Pos           (10U)\n#define PWR_PDCRH_PH10_Msk           (0x1U << PWR_PDCRH_PH10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRH_PH10               PWR_PDCRH_PH10_Msk                        /*!< Port PH10 Pull-Down set  */\n#define PWR_PDCRH_PH9_Pos            (9U)\n#define PWR_PDCRH_PH9_Msk            (0x1U << PWR_PDCRH_PH9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRH_PH9                PWR_PDCRH_PH9_Msk                         /*!< Port PH9 Pull-Down set  */\n#define PWR_PDCRH_PH8_Pos            (8U)\n#define PWR_PDCRH_PH8_Msk            (0x1U << PWR_PDCRH_PH8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRH_PH8                PWR_PDCRH_PH8_Msk                         /*!< Port PH8 Pull-Down set  */\n#define PWR_PDCRH_PH7_Pos            (7U)\n#define PWR_PDCRH_PH7_Msk            (0x1U << PWR_PDCRH_PH7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRH_PH7                PWR_PDCRH_PH7_Msk                         /*!< Port PH7 Pull-Down set  */\n#define PWR_PDCRH_PH6_Pos            (6U)\n#define PWR_PDCRH_PH6_Msk            (0x1U << PWR_PDCRH_PH6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRH_PH6                PWR_PDCRH_PH6_Msk                         /*!< Port PH6 Pull-Down set  */\n#define PWR_PDCRH_PH5_Pos            (5U)\n#define PWR_PDCRH_PH5_Msk            (0x1U << PWR_PDCRH_PH5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRH_PH5                PWR_PDCRH_PH5_Msk                         /*!< Port PH5 Pull-Down set  */\n#define PWR_PDCRH_PH4_Pos            (4U)\n#define PWR_PDCRH_PH4_Msk            (0x1U << PWR_PDCRH_PH4_Pos)               /*!< 0x00000010 */\n#define PWR_PDCRH_PH4                PWR_PDCRH_PH4_Msk                         /*!< Port PH4 Pull-Down set  */\n#define PWR_PDCRH_PH3_Pos            (3U)\n#define PWR_PDCRH_PH3_Msk            (0x1U << PWR_PDCRH_PH3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRH_PH3                PWR_PDCRH_PH3_Msk                         /*!< Port PH3 Pull-Down set  */\n#define PWR_PDCRH_PH2_Pos            (2U)\n#define PWR_PDCRH_PH2_Msk            (0x1U << PWR_PDCRH_PH2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRH_PH2                PWR_PDCRH_PH2_Msk                         /*!< Port PH1 Pull-Down set  */\n#define PWR_PDCRH_PH1_Pos            (1U)\n#define PWR_PDCRH_PH1_Msk            (0x1U << PWR_PDCRH_PH1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */\n#define PWR_PDCRH_PH0_Pos            (0U)\n#define PWR_PDCRH_PH0_Msk            (0x1U << PWR_PDCRH_PH0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */\n\n/********************  Bit definition for PWR_PUCRI register  ********************/\n#define PWR_PUCRI_PI11_Pos           (11U)\n#define PWR_PUCRI_PI11_Msk           (0x1U << PWR_PUCRI_PI11_Pos)              /*!< 0x00000800 */\n#define PWR_PUCRI_PI11               PWR_PUCRI_PI11_Msk                        /*!< Port PI11 Pull-Up set */\n#define PWR_PUCRI_PI10_Pos           (10U)\n#define PWR_PUCRI_PI10_Msk           (0x1U << PWR_PUCRI_PI10_Pos)              /*!< 0x00000400 */\n#define PWR_PUCRI_PI10               PWR_PUCRI_PI10_Msk                        /*!< Port PI10 Pull-Up set */\n#define PWR_PUCRI_PI9_Pos            (9U)\n#define PWR_PUCRI_PI9_Msk            (0x1U << PWR_PUCRI_PI9_Pos)               /*!< 0x00000200 */\n#define PWR_PUCRI_PI9                PWR_PUCRI_PI9_Msk                         /*!< Port PI9 Pull-Up set  */\n#define PWR_PUCRI_PI8_Pos            (8U)\n#define PWR_PUCRI_PI8_Msk            (0x1U << PWR_PUCRI_PI8_Pos)               /*!< 0x00000100 */\n#define PWR_PUCRI_PI8                PWR_PUCRI_PI8_Msk                         /*!< Port PI8 Pull-Up set  */\n#define PWR_PUCRI_PI7_Pos            (7U)\n#define PWR_PUCRI_PI7_Msk            (0x1U << PWR_PUCRI_PI7_Pos)               /*!< 0x00000080 */\n#define PWR_PUCRI_PI7                PWR_PUCRI_PI7_Msk                         /*!< Port PI7 Pull-Up set  */\n#define PWR_PUCRI_PI6_Pos            (6U)\n#define PWR_PUCRI_PI6_Msk            (0x1U << PWR_PUCRI_PI6_Pos)               /*!< 0x00000040 */\n#define PWR_PUCRI_PI6                PWR_PUCRI_PI6_Msk                         /*!< Port PI6 Pull-Up set  */\n#define PWR_PUCRI_PI5_Pos            (5U)\n#define PWR_PUCRI_PI5_Msk            (0x1U << PWR_PUCRI_PI5_Pos)               /*!< 0x00000020 */\n#define PWR_PUCRI_PI5                PWR_PUCRI_PI5_Msk                         /*!< Port PI5 Pull-Up set  */\n#define PWR_PUCRI_PI4_Pos            (4U)\n#define PWR_PUCRI_PI4_Msk            (0x1U << PWR_PUCRI_PI4_Pos)               /*!< 0x00000010 */\n#define PWR_PUCRI_PI4                PWR_PUCRI_PI4_Msk                         /*!< Port PI4 Pull-Up set  */\n#define PWR_PUCRI_PI3_Pos            (3U)\n#define PWR_PUCRI_PI3_Msk            (0x1U << PWR_PUCRI_PI3_Pos)               /*!< 0x00000008 */\n#define PWR_PUCRI_PI3                PWR_PUCRI_PI3_Msk                         /*!< Port PI3 Pull-Up set  */\n#define PWR_PUCRI_PI2_Pos            (2U)\n#define PWR_PUCRI_PI2_Msk            (0x1U << PWR_PUCRI_PI2_Pos)               /*!< 0x00000004 */\n#define PWR_PUCRI_PI2                PWR_PUCRI_PI2_Msk                         /*!< Port PI2 Pull-Up set  */\n#define PWR_PUCRI_PI1_Pos            (1U)\n#define PWR_PUCRI_PI1_Msk            (0x1U << PWR_PUCRI_PI1_Pos)               /*!< 0x00000002 */\n#define PWR_PUCRI_PI1                PWR_PUCRI_PI1_Msk                         /*!< Port PI1 Pull-Up set  */\n#define PWR_PUCRI_PI0_Pos            (0U)\n#define PWR_PUCRI_PI0_Msk            (0x1U << PWR_PUCRI_PI0_Pos)               /*!< 0x00000001 */\n#define PWR_PUCRI_PI0                PWR_PUCRI_PI0_Msk                         /*!< Port PI0 Pull-Up set  */\n\n/********************  Bit definition for PWR_PDCRI register  ********************/\n#define PWR_PDCRI_PI11_Pos           (11U)\n#define PWR_PDCRI_PI11_Msk           (0x1U << PWR_PDCRI_PI11_Pos)              /*!< 0x00000800 */\n#define PWR_PDCRI_PI11               PWR_PDCRI_PI11_Msk                        /*!< Port PI11 Pull-Down set */\n#define PWR_PDCRI_PI10_Pos           (10U)\n#define PWR_PDCRI_PI10_Msk           (0x1U << PWR_PDCRI_PI10_Pos)              /*!< 0x00000400 */\n#define PWR_PDCRI_PI10               PWR_PDCRI_PI10_Msk                        /*!< Port PI10 Pull-Down set */\n#define PWR_PDCRI_PI9_Pos            (9U)\n#define PWR_PDCRI_PI9_Msk            (0x1U << PWR_PDCRI_PI9_Pos)               /*!< 0x00000200 */\n#define PWR_PDCRI_PI9                PWR_PDCRI_PI9_Msk                         /*!< Port PI9 Pull-Down set  */\n#define PWR_PDCRI_PI8_Pos            (8U)\n#define PWR_PDCRI_PI8_Msk            (0x1U << PWR_PDCRI_PI8_Pos)               /*!< 0x00000100 */\n#define PWR_PDCRI_PI8                PWR_PDCRI_PI8_Msk                         /*!< Port PI8 Pull-Down set  */\n#define PWR_PDCRI_PI7_Pos            (7U)\n#define PWR_PDCRI_PI7_Msk            (0x1U << PWR_PDCRI_PI7_Pos)               /*!< 0x00000080 */\n#define PWR_PDCRI_PI7                PWR_PDCRI_PI7_Msk                         /*!< Port PI7 Pull-Down set  */\n#define PWR_PDCRI_PI6_Pos            (6U)\n#define PWR_PDCRI_PI6_Msk            (0x1U << PWR_PDCRI_PI6_Pos)               /*!< 0x00000040 */\n#define PWR_PDCRI_PI6                PWR_PDCRI_PI6_Msk                         /*!< Port PI6 Pull-Down set  */\n#define PWR_PDCRI_PI5_Pos            (5U)\n#define PWR_PDCRI_PI5_Msk            (0x1U << PWR_PDCRI_PI5_Pos)               /*!< 0x00000020 */\n#define PWR_PDCRI_PI5                PWR_PDCRI_PI5_Msk                         /*!< Port PI5 Pull-Down set  */\n#define PWR_PDCRI_PI4_Pos            (4U)\n#define PWR_PDCRI_PI4_Msk            (0x1U << PWR_PDCRI_PI4_Pos)               /*!< 0x00000010 */\n#define PWR_PDCRI_PI4                PWR_PDCRI_PI4_Msk                         /*!< Port PI4 Pull-Down set  */\n#define PWR_PDCRI_PI3_Pos            (3U)\n#define PWR_PDCRI_PI3_Msk            (0x1U << PWR_PDCRI_PI3_Pos)               /*!< 0x00000008 */\n#define PWR_PDCRI_PI3                PWR_PDCRI_PI3_Msk                         /*!< Port PI3 Pull-Down set  */\n#define PWR_PDCRI_PI2_Pos            (2U)\n#define PWR_PDCRI_PI2_Msk            (0x1U << PWR_PDCRI_PI2_Pos)               /*!< 0x00000004 */\n#define PWR_PDCRI_PI2                PWR_PDCRI_PI2_Msk                         /*!< Port PI2 Pull-Down set  */\n#define PWR_PDCRI_PI1_Pos            (1U)\n#define PWR_PDCRI_PI1_Msk            (0x1U << PWR_PDCRI_PI1_Pos)               /*!< 0x00000002 */\n#define PWR_PDCRI_PI1                PWR_PDCRI_PI1_Msk                         /*!< Port PI1 Pull-Down set  */\n#define PWR_PDCRI_PI0_Pos            (0U)\n#define PWR_PDCRI_PI0_Msk            (0x1U << PWR_PDCRI_PI0_Pos)               /*!< 0x00000001 */\n#define PWR_PDCRI_PI0                PWR_PDCRI_PI0_Msk                         /*!< Port PI0 Pull-Down set  */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/*\n* @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)\n*/\n#define RCC_PLLSAI1_SUPPORT\n#define RCC_PLLP_SUPPORT\n#define RCC_HSI48_SUPPORT\n#define RCC_PLLP_DIV_2_31_SUPPORT\n#define RCC_PLLSAI1P_DIV_2_31_SUPPORT\n#define RCC_PLLSAI2_SUPPORT\n#define RCC_PLLSAI2P_DIV_2_31_SUPPORT\n\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_MSION_Pos                     (0U)\n#define RCC_CR_MSION_Msk                     (0x1U << RCC_CR_MSION_Pos)        /*!< 0x00000001 */\n#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */\n#define RCC_CR_MSIRDY_Pos                    (1U)\n#define RCC_CR_MSIRDY_Msk                    (0x1U << RCC_CR_MSIRDY_Pos)       /*!< 0x00000002 */\n#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */\n#define RCC_CR_MSIPLLEN_Pos                  (2U)\n#define RCC_CR_MSIPLLEN_Msk                  (0x1U << RCC_CR_MSIPLLEN_Pos)     /*!< 0x00000004 */\n#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */\n#define RCC_CR_MSIRGSEL_Pos                  (3U)\n#define RCC_CR_MSIRGSEL_Msk                  (0x1U << RCC_CR_MSIRGSEL_Pos)     /*!< 0x00000008 */\n#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */\n\n/*!< MSIRANGE configuration : 12 frequency ranges available */\n#define RCC_CR_MSIRANGE_Pos                  (4U)\n#define RCC_CR_MSIRANGE_Msk                  (0xFU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000F0 */\n#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */\n#define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */\n#define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */\n#define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */\n#define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */\n#define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */\n#define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */\n#define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */\n#define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */\n#define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */\n#define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */\n#define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */\n#define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */\n\n#define RCC_CR_HSION_Pos                     (8U)\n#define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */\n#define RCC_CR_HSIKERON_Pos                  (9U)\n#define RCC_CR_HSIKERON_Msk                  (0x1U << RCC_CR_HSIKERON_Pos)     /*!< 0x00000200 */\n#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */\n#define RCC_CR_HSIRDY_Pos                    (10U)\n#define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000400 */\n#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */\n#define RCC_CR_HSIASFS_Pos                   (11U)\n#define RCC_CR_HSIASFS_Msk                   (0x1U << RCC_CR_HSIASFS_Pos)      /*!< 0x00000800 */\n#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */\n\n#define RCC_CR_HSEON_Pos                     (16U)\n#define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */\n#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */\n#define RCC_CR_HSERDY_Pos                    (17U)\n#define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */\n#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */\n#define RCC_CR_HSEBYP_Pos                    (18U)\n#define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */\n#define RCC_CR_CSSON_Pos                     (19U)\n#define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */\n#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */\n\n#define RCC_CR_PLLON_Pos                     (24U)\n#define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */\n#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */\n#define RCC_CR_PLLRDY_Pos                    (25U)\n#define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */\n#define RCC_CR_PLLSAI1ON_Pos                 (26U)\n#define RCC_CR_PLLSAI1ON_Msk                 (0x1U << RCC_CR_PLLSAI1ON_Pos)    /*!< 0x04000000 */\n#define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */\n#define RCC_CR_PLLSAI1RDY_Pos                (27U)\n#define RCC_CR_PLLSAI1RDY_Msk                (0x1U << RCC_CR_PLLSAI1RDY_Pos)   /*!< 0x08000000 */\n#define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */\n#define RCC_CR_PLLSAI2ON_Pos                 (28U)\n#define RCC_CR_PLLSAI2ON_Msk                 (0x1U << RCC_CR_PLLSAI2ON_Pos)    /*!< 0x10000000 */\n#define RCC_CR_PLLSAI2ON                     RCC_CR_PLLSAI2ON_Msk              /*!< SAI2 PLL enable */\n#define RCC_CR_PLLSAI2RDY_Pos                (29U)\n#define RCC_CR_PLLSAI2RDY_Msk                (0x1U << RCC_CR_PLLSAI2RDY_Pos)   /*!< 0x20000000 */\n#define RCC_CR_PLLSAI2RDY                    RCC_CR_PLLSAI2RDY_Msk             /*!< SAI2 PLL ready */\n\n/********************  Bit definition for RCC_ICSCR register  ***************/\n/*!< MSICAL configuration */\n#define RCC_ICSCR_MSICAL_Pos                 (0U)\n#define RCC_ICSCR_MSICAL_Msk                 (0xFFU << RCC_ICSCR_MSICAL_Pos)   /*!< 0x000000FF */\n#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */\n#define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */\n#define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */\n#define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */\n#define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */\n#define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */\n#define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */\n#define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */\n#define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */\n\n/*!< MSITRIM configuration */\n#define RCC_ICSCR_MSITRIM_Pos                (8U)\n#define RCC_ICSCR_MSITRIM_Msk                (0xFFU << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x0000FF00 */\n#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */\n#define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */\n#define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */\n#define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */\n#define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */\n#define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */\n#define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */\n#define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */\n#define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */\n\n/*!< HSICAL configuration */\n#define RCC_ICSCR_HSICAL_Pos                 (16U)\n#define RCC_ICSCR_HSICAL_Msk                 (0xFFU << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00FF0000 */\n#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */\n#define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */\n#define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */\n#define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */\n#define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */\n#define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */\n#define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */\n#define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */\n#define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */\n\n/*!< HSITRIM configuration */\n#define RCC_ICSCR_HSITRIM_Pos                (24U)\n#define RCC_ICSCR_HSITRIM_Msk                (0x7FU << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x7F000000 */\n#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */\n#define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */\n#define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */\n#define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */\n#define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */\n#define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */\n#define RCC_ICSCR_HSITRIM_5                  (0x20U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x20000000 */\n#define RCC_ICSCR_HSITRIM_6                  (0x40U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x40000000 */\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                      (0U)\n#define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */\n#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI oscillator selection as system clock */\n#define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */\n#define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */\n#define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                     (2U)\n#define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */\n#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */\n#define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */\n#define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */\n#define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                    (4U)\n#define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */\n#define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */\n#define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */\n#define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */\n#define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */\n#define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */\n#define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                   (8U)\n#define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */\n#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */\n#define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */\n#define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */\n\n#define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */\n#define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */\n#define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */\n#define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */\n#define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                   (11U)\n#define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */\n#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */\n#define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */\n#define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */\n\n#define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */\n#define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */\n#define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */\n#define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */\n#define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */\n\n#define RCC_CFGR_STOPWUCK_Pos                (15U)\n#define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */\n#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */\n\n/*!< MCOSEL configuration */\n#define RCC_CFGR_MCOSEL_Pos                  (24U)\n#define RCC_CFGR_MCOSEL_Msk                  (0xFU << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */\n#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */\n#define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */\n#define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */\n#define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */\n#define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */\n\n#define RCC_CFGR_MCOPRE_Pos                  (28U)\n#define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */\n#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */\n#define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */\n#define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */\n#define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */\n\n#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */\n#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */\n#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */\n#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */\n#define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */\n\n/* Legacy aliases */\n#define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE\n#define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1\n#define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2\n#define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4\n#define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8\n#define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16\n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLSRC_Pos               (0U)\n#define RCC_PLLCFGR_PLLSRC_Msk               (0x3U << RCC_PLLCFGR_PLLSRC_Pos)  /*!< 0x00000003 */\n#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk\n\n#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)\n#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */\n#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)\n#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */\n#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)\n#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */\n#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */\n\n#define RCC_PLLCFGR_PLLM_Pos                 (4U)\n#define RCC_PLLCFGR_PLLM_Msk                 (0x7U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000070 */\n#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk\n#define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000020 */\n#define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000040 */\n\n#define RCC_PLLCFGR_PLLN_Pos                 (8U)\n#define RCC_PLLCFGR_PLLN_Msk                 (0x7FU << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00007F00 */\n#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk\n#define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLPEN_Pos               (16U)\n#define RCC_PLLCFGR_PLLPEN_Msk               (0x1U << RCC_PLLCFGR_PLLPEN_Pos)  /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk\n#define RCC_PLLCFGR_PLLP_Pos                 (17U)\n#define RCC_PLLCFGR_PLLP_Msk                 (0x1U << RCC_PLLCFGR_PLLP_Pos)    /*!< 0x00020000 */\n#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk\n#define RCC_PLLCFGR_PLLQEN_Pos               (20U)\n#define RCC_PLLCFGR_PLLQEN_Msk               (0x1U << RCC_PLLCFGR_PLLQEN_Pos)  /*!< 0x00100000 */\n#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk\n\n#define RCC_PLLCFGR_PLLQ_Pos                 (21U)\n#define RCC_PLLCFGR_PLLQ_Msk                 (0x3U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00600000 */\n#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk\n#define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00200000 */\n#define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00400000 */\n\n#define RCC_PLLCFGR_PLLREN_Pos               (24U)\n#define RCC_PLLCFGR_PLLREN_Msk               (0x1U << RCC_PLLCFGR_PLLREN_Pos)  /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk\n#define RCC_PLLCFGR_PLLR_Pos                 (25U)\n#define RCC_PLLCFGR_PLLR_Msk                 (0x3U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x06000000 */\n#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk\n#define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x04000000 */\n\n#define RCC_PLLCFGR_PLLPDIV_Pos              (27U)\n#define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */\n#define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk\n#define RCC_PLLCFGR_PLLPDIV_0                (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */\n#define RCC_PLLCFGR_PLLPDIV_1                (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */\n#define RCC_PLLCFGR_PLLPDIV_2                (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */\n#define RCC_PLLCFGR_PLLPDIV_3                (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */\n#define RCC_PLLCFGR_PLLPDIV_4                (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_PLLSAI1CFGR register  ************/\n#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)\n#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */\n#define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk\n#define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */\n#define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */\n#define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */\n#define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */\n#define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)\n#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk\n#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)\n#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk\n\n#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)\n#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk\n#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)\n#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk\n#define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */\n\n#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)\n#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk\n#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)\n#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk\n#define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */\n\n#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos      (27U)\n#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk      (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1PDIV          RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk\n#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0        (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1        (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2        (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3        (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */\n#define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4        (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_PLLSAI2CFGR register  ************/\n#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos         (8U)\n#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk         (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */\n#define RCC_PLLSAI2CFGR_PLLSAI2N             RCC_PLLSAI2CFGR_PLLSAI2N_Msk\n#define RCC_PLLSAI2CFGR_PLLSAI2N_0           (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */\n#define RCC_PLLSAI2CFGR_PLLSAI2N_1           (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */\n#define RCC_PLLSAI2CFGR_PLLSAI2N_2           (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */\n#define RCC_PLLSAI2CFGR_PLLSAI2N_3           (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */\n#define RCC_PLLSAI2CFGR_PLLSAI2N_4           (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2N_5           (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2N_6           (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos       (16U)\n#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2PEN           RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk\n#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos         (17U)\n#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk         (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2P             RCC_PLLSAI2CFGR_PLLSAI2P_Msk\n\n#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos       (24U)\n#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2REN           RCC_PLLSAI2CFGR_PLLSAI2REN_Msk\n#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos         (25U)\n#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk         (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2R             RCC_PLLSAI2CFGR_PLLSAI2R_Msk\n#define RCC_PLLSAI2CFGR_PLLSAI2R_0           (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2R_1           (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */\n\n#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos      (27U)\n#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk      (0x1FU << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0xF8000000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2PDIV          RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk\n#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_0        (0x01U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x08000000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_1        (0x02U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x10000000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_2        (0x04U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x20000000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_3        (0x08U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x40000000 */\n#define RCC_PLLSAI2CFGR_PLLSAI2PDIV_4        (0x10U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIER register  ******************/\n#define RCC_CIER_LSIRDYIE_Pos                (0U)\n#define RCC_CIER_LSIRDYIE_Msk                (0x1U << RCC_CIER_LSIRDYIE_Pos)   /*!< 0x00000001 */\n#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk\n#define RCC_CIER_LSERDYIE_Pos                (1U)\n#define RCC_CIER_LSERDYIE_Msk                (0x1U << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */\n#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk\n#define RCC_CIER_MSIRDYIE_Pos                (2U)\n#define RCC_CIER_MSIRDYIE_Msk                (0x1U << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */\n#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk\n#define RCC_CIER_HSIRDYIE_Pos                (3U)\n#define RCC_CIER_HSIRDYIE_Msk                (0x1U << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */\n#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk\n#define RCC_CIER_HSERDYIE_Pos                (4U)\n#define RCC_CIER_HSERDYIE_Msk                (0x1U << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */\n#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk\n#define RCC_CIER_PLLRDYIE_Pos                (5U)\n#define RCC_CIER_PLLRDYIE_Msk                (0x1U << RCC_CIER_PLLRDYIE_Pos)   /*!< 0x00000020 */\n#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk\n#define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)\n#define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */\n#define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk\n#define RCC_CIER_PLLSAI2RDYIE_Pos            (7U)\n#define RCC_CIER_PLLSAI2RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */\n#define RCC_CIER_PLLSAI2RDYIE                RCC_CIER_PLLSAI2RDYIE_Msk\n#define RCC_CIER_LSECSSIE_Pos                (9U)\n#define RCC_CIER_LSECSSIE_Msk                (0x1U << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */\n#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk\n#define RCC_CIER_HSI48RDYIE_Pos              (10U)\n#define RCC_CIER_HSI48RDYIE_Msk              (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */\n#define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk\n\n/********************  Bit definition for RCC_CIFR register  ******************/\n#define RCC_CIFR_LSIRDYF_Pos                 (0U)\n#define RCC_CIFR_LSIRDYF_Msk                 (0x1U << RCC_CIFR_LSIRDYF_Pos)    /*!< 0x00000001 */\n#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk\n#define RCC_CIFR_LSERDYF_Pos                 (1U)\n#define RCC_CIFR_LSERDYF_Msk                 (0x1U << RCC_CIFR_LSERDYF_Pos)    /*!< 0x00000002 */\n#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk\n#define RCC_CIFR_MSIRDYF_Pos                 (2U)\n#define RCC_CIFR_MSIRDYF_Msk                 (0x1U << RCC_CIFR_MSIRDYF_Pos)    /*!< 0x00000004 */\n#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk\n#define RCC_CIFR_HSIRDYF_Pos                 (3U)\n#define RCC_CIFR_HSIRDYF_Msk                 (0x1U << RCC_CIFR_HSIRDYF_Pos)    /*!< 0x00000008 */\n#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk\n#define RCC_CIFR_HSERDYF_Pos                 (4U)\n#define RCC_CIFR_HSERDYF_Msk                 (0x1U << RCC_CIFR_HSERDYF_Pos)    /*!< 0x00000010 */\n#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk\n#define RCC_CIFR_PLLRDYF_Pos                 (5U)\n#define RCC_CIFR_PLLRDYF_Msk                 (0x1U << RCC_CIFR_PLLRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk\n#define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)\n#define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */\n#define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk\n#define RCC_CIFR_PLLSAI2RDYF_Pos             (7U)\n#define RCC_CIFR_PLLSAI2RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */\n#define RCC_CIFR_PLLSAI2RDYF                 RCC_CIFR_PLLSAI2RDYF_Msk\n#define RCC_CIFR_CSSF_Pos                    (8U)\n#define RCC_CIFR_CSSF_Msk                    (0x1U << RCC_CIFR_CSSF_Pos)       /*!< 0x00000100 */\n#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk\n#define RCC_CIFR_LSECSSF_Pos                 (9U)\n#define RCC_CIFR_LSECSSF_Msk                 (0x1U << RCC_CIFR_LSECSSF_Pos)    /*!< 0x00000200 */\n#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk\n#define RCC_CIFR_HSI48RDYF_Pos               (10U)\n#define RCC_CIFR_HSI48RDYF_Msk               (0x1U << RCC_CIFR_HSI48RDYF_Pos)  /*!< 0x00000400 */\n#define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk\n\n/********************  Bit definition for RCC_CICR register  ******************/\n#define RCC_CICR_LSIRDYC_Pos                 (0U)\n#define RCC_CICR_LSIRDYC_Msk                 (0x1U << RCC_CICR_LSIRDYC_Pos)    /*!< 0x00000001 */\n#define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk\n#define RCC_CICR_LSERDYC_Pos                 (1U)\n#define RCC_CICR_LSERDYC_Msk                 (0x1U << RCC_CICR_LSERDYC_Pos)    /*!< 0x00000002 */\n#define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk\n#define RCC_CICR_MSIRDYC_Pos                 (2U)\n#define RCC_CICR_MSIRDYC_Msk                 (0x1U << RCC_CICR_MSIRDYC_Pos)    /*!< 0x00000004 */\n#define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk\n#define RCC_CICR_HSIRDYC_Pos                 (3U)\n#define RCC_CICR_HSIRDYC_Msk                 (0x1U << RCC_CICR_HSIRDYC_Pos)    /*!< 0x00000008 */\n#define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk\n#define RCC_CICR_HSERDYC_Pos                 (4U)\n#define RCC_CICR_HSERDYC_Msk                 (0x1U << RCC_CICR_HSERDYC_Pos)    /*!< 0x00000010 */\n#define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk\n#define RCC_CICR_PLLRDYC_Pos                 (5U)\n#define RCC_CICR_PLLRDYC_Msk                 (0x1U << RCC_CICR_PLLRDYC_Pos)    /*!< 0x00000020 */\n#define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk\n#define RCC_CICR_PLLSAI1RDYC_Pos             (6U)\n#define RCC_CICR_PLLSAI1RDYC_Msk             (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */\n#define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk\n#define RCC_CICR_PLLSAI2RDYC_Pos             (7U)\n#define RCC_CICR_PLLSAI2RDYC_Msk             (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */\n#define RCC_CICR_PLLSAI2RDYC                 RCC_CICR_PLLSAI2RDYC_Msk\n#define RCC_CICR_CSSC_Pos                    (8U)\n#define RCC_CICR_CSSC_Msk                    (0x1U << RCC_CICR_CSSC_Pos)       /*!< 0x00000100 */\n#define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk\n#define RCC_CICR_LSECSSC_Pos                 (9U)\n#define RCC_CICR_LSECSSC_Msk                 (0x1U << RCC_CICR_LSECSSC_Pos)    /*!< 0x00000200 */\n#define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk\n#define RCC_CICR_HSI48RDYC_Pos               (10U)\n#define RCC_CICR_HSI48RDYC_Msk               (0x1U << RCC_CICR_HSI48RDYC_Pos)  /*!< 0x00000400 */\n#define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk\n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)\n#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk\n#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)\n#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk\n#define RCC_AHB1RSTR_FLASHRST_Pos            (8U)\n#define RCC_AHB1RSTR_FLASHRST_Msk            (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */\n#define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk\n#define RCC_AHB1RSTR_CRCRST_Pos              (12U)\n#define RCC_AHB1RSTR_CRCRST_Msk              (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk\n#define RCC_AHB1RSTR_TSCRST_Pos              (16U)\n#define RCC_AHB1RSTR_TSCRST_Msk              (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */\n#define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk\n#define RCC_AHB1RSTR_DMA2DRST_Pos            (17U)\n#define RCC_AHB1RSTR_DMA2DRST_Msk            (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00020000 */\n#define RCC_AHB1RSTR_DMA2DRST                RCC_AHB1RSTR_DMA2DRST_Msk\n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_GPIOARST_Pos            (0U)\n#define RCC_AHB2RSTR_GPIOARST_Msk            (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk\n#define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)\n#define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk\n#define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)\n#define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk\n#define RCC_AHB2RSTR_GPIODRST_Pos            (3U)\n#define RCC_AHB2RSTR_GPIODRST_Msk            (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk\n#define RCC_AHB2RSTR_GPIOERST_Pos            (4U)\n#define RCC_AHB2RSTR_GPIOERST_Msk            (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk\n#define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)\n#define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk\n#define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)\n#define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk\n#define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)\n#define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk\n#define RCC_AHB2RSTR_GPIOIRST_Pos            (8U)\n#define RCC_AHB2RSTR_GPIOIRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\n#define RCC_AHB2RSTR_GPIOIRST                RCC_AHB2RSTR_GPIOIRST_Msk\n#define RCC_AHB2RSTR_OTGFSRST_Pos            (12U)\n#define RCC_AHB2RSTR_OTGFSRST_Msk            (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */\n#define RCC_AHB2RSTR_OTGFSRST                RCC_AHB2RSTR_OTGFSRST_Msk\n#define RCC_AHB2RSTR_ADCRST_Pos              (13U)\n#define RCC_AHB2RSTR_ADCRST_Msk              (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */\n#define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk\n#define RCC_AHB2RSTR_DCMIRST_Pos             (14U)\n#define RCC_AHB2RSTR_DCMIRST_Msk             (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00004000 */\n#define RCC_AHB2RSTR_DCMIRST                 RCC_AHB2RSTR_DCMIRST_Msk\n#define RCC_AHB2RSTR_RNGRST_Pos              (18U)\n#define RCC_AHB2RSTR_RNGRST_Msk              (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */\n#define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk\n\n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FMCRST_Pos              (0U)\n#define RCC_AHB3RSTR_FMCRST_Msk              (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk\n#define RCC_AHB3RSTR_QSPIRST_Pos             (8U)\n#define RCC_AHB3RSTR_QSPIRST_Msk             (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */\n#define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk\n\n/********************  Bit definition for RCC_APB1RSTR1 register  **************/\n#define RCC_APB1RSTR1_TIM2RST_Pos            (0U)\n#define RCC_APB1RSTR1_TIM2RST_Msk            (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */\n#define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk\n#define RCC_APB1RSTR1_TIM3RST_Pos            (1U)\n#define RCC_APB1RSTR1_TIM3RST_Msk            (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */\n#define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk\n#define RCC_APB1RSTR1_TIM4RST_Pos            (2U)\n#define RCC_APB1RSTR1_TIM4RST_Msk            (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */\n#define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk\n#define RCC_APB1RSTR1_TIM5RST_Pos            (3U)\n#define RCC_APB1RSTR1_TIM5RST_Msk            (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */\n#define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk\n#define RCC_APB1RSTR1_TIM6RST_Pos            (4U)\n#define RCC_APB1RSTR1_TIM6RST_Msk            (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */\n#define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk\n#define RCC_APB1RSTR1_TIM7RST_Pos            (5U)\n#define RCC_APB1RSTR1_TIM7RST_Msk            (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */\n#define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk\n#define RCC_APB1RSTR1_LCDRST_Pos             (9U)\n#define RCC_APB1RSTR1_LCDRST_Msk             (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */\n#define RCC_APB1RSTR1_LCDRST                 RCC_APB1RSTR1_LCDRST_Msk\n#define RCC_APB1RSTR1_SPI2RST_Pos            (14U)\n#define RCC_APB1RSTR1_SPI2RST_Msk            (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */\n#define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk\n#define RCC_APB1RSTR1_SPI3RST_Pos            (15U)\n#define RCC_APB1RSTR1_SPI3RST_Msk            (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */\n#define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk\n#define RCC_APB1RSTR1_USART2RST_Pos          (17U)\n#define RCC_APB1RSTR1_USART2RST_Msk          (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk\n#define RCC_APB1RSTR1_USART3RST_Pos          (18U)\n#define RCC_APB1RSTR1_USART3RST_Msk          (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk\n#define RCC_APB1RSTR1_UART4RST_Pos           (19U)\n#define RCC_APB1RSTR1_UART4RST_Msk           (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk\n#define RCC_APB1RSTR1_UART5RST_Pos           (20U)\n#define RCC_APB1RSTR1_UART5RST_Msk           (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk\n#define RCC_APB1RSTR1_I2C1RST_Pos            (21U)\n#define RCC_APB1RSTR1_I2C1RST_Msk            (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */\n#define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk\n#define RCC_APB1RSTR1_I2C2RST_Pos            (22U)\n#define RCC_APB1RSTR1_I2C2RST_Msk            (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */\n#define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk\n#define RCC_APB1RSTR1_I2C3RST_Pos            (23U)\n#define RCC_APB1RSTR1_I2C3RST_Msk            (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */\n#define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk\n#define RCC_APB1RSTR1_CRSRST_Pos             (24U)\n#define RCC_APB1RSTR1_CRSRST_Msk             (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */\n#define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk\n#define RCC_APB1RSTR1_CAN1RST_Pos            (25U)\n#define RCC_APB1RSTR1_CAN1RST_Msk            (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */\n#define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk\n#define RCC_APB1RSTR1_CAN2RST_Pos            (26U)\n#define RCC_APB1RSTR1_CAN2RST_Msk            (0x1U << RCC_APB1RSTR1_CAN2RST_Pos) /*!< 0x04000000 */\n#define RCC_APB1RSTR1_CAN2RST                RCC_APB1RSTR1_CAN2RST_Msk\n#define RCC_APB1RSTR1_PWRRST_Pos             (28U)\n#define RCC_APB1RSTR1_PWRRST_Msk             (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */\n#define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk\n#define RCC_APB1RSTR1_DAC1RST_Pos            (29U)\n#define RCC_APB1RSTR1_DAC1RST_Msk            (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */\n#define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk\n#define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)\n#define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */\n#define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk\n#define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)\n#define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */\n#define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk\n\n/********************  Bit definition for RCC_APB1RSTR2 register  **************/\n#define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)\n#define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */\n#define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk\n#define RCC_APB1RSTR2_I2C4RST_Pos            (1U)\n#define RCC_APB1RSTR2_I2C4RST_Msk            (0x1U << RCC_APB1RSTR2_I2C4RST_Pos) /*!< 0x00000002 */\n#define RCC_APB1RSTR2_I2C4RST                RCC_APB1RSTR2_I2C4RST_Msk\n#define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)\n#define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */\n#define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk\n#define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)\n#define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */\n#define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk\n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)\n#define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */\n#define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk\n#define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)\n#define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */\n#define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk\n#define RCC_APB2RSTR_TIM1RST_Pos             (11U)\n#define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */\n#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk\n#define RCC_APB2RSTR_SPI1RST_Pos             (12U)\n#define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk\n#define RCC_APB2RSTR_TIM8RST_Pos             (13U)\n#define RCC_APB2RSTR_TIM8RST_Msk             (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */\n#define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk\n#define RCC_APB2RSTR_USART1RST_Pos           (14U)\n#define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk\n#define RCC_APB2RSTR_TIM15RST_Pos            (16U)\n#define RCC_APB2RSTR_TIM15RST_Msk            (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk\n#define RCC_APB2RSTR_TIM16RST_Pos            (17U)\n#define RCC_APB2RSTR_TIM16RST_Msk            (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk\n#define RCC_APB2RSTR_TIM17RST_Pos            (18U)\n#define RCC_APB2RSTR_TIM17RST_Msk            (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk\n#define RCC_APB2RSTR_SAI1RST_Pos             (21U)\n#define RCC_APB2RSTR_SAI1RST_Msk             (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */\n#define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk\n#define RCC_APB2RSTR_SAI2RST_Pos             (22U)\n#define RCC_APB2RSTR_SAI2RST_Msk             (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */\n#define RCC_APB2RSTR_SAI2RST                 RCC_APB2RSTR_SAI2RST_Msk\n#define RCC_APB2RSTR_DFSDM1RST_Pos           (24U)\n#define RCC_APB2RSTR_DFSDM1RST_Msk           (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */\n#define RCC_APB2RSTR_DFSDM1RST               RCC_APB2RSTR_DFSDM1RST_Msk\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_DMA1EN_Pos               (0U)\n#define RCC_AHB1ENR_DMA1EN_Msk               (0x1U << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */\n#define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk\n#define RCC_AHB1ENR_DMA2EN_Pos               (1U)\n#define RCC_AHB1ENR_DMA2EN_Msk               (0x1U << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */\n#define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk\n#define RCC_AHB1ENR_FLASHEN_Pos              (8U)\n#define RCC_AHB1ENR_FLASHEN_Msk              (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk\n#define RCC_AHB1ENR_CRCEN_Pos                (12U)\n#define RCC_AHB1ENR_CRCEN_Msk                (0x1U << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk\n#define RCC_AHB1ENR_TSCEN_Pos                (16U)\n#define RCC_AHB1ENR_TSCEN_Msk                (0x1U << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */\n#define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk\n#define RCC_AHB1ENR_DMA2DEN_Pos              (17U)\n#define RCC_AHB1ENR_DMA2DEN_Msk              (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1ENR_DMA2DEN                  RCC_AHB1ENR_DMA2DEN_Msk\n\n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n#define RCC_AHB2ENR_GPIOAEN_Pos              (0U)\n#define RCC_AHB2ENR_GPIOAEN_Msk              (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk\n#define RCC_AHB2ENR_GPIOBEN_Pos              (1U)\n#define RCC_AHB2ENR_GPIOBEN_Msk              (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk\n#define RCC_AHB2ENR_GPIOCEN_Pos              (2U)\n#define RCC_AHB2ENR_GPIOCEN_Msk              (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk\n#define RCC_AHB2ENR_GPIODEN_Pos              (3U)\n#define RCC_AHB2ENR_GPIODEN_Msk              (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk\n#define RCC_AHB2ENR_GPIOEEN_Pos              (4U)\n#define RCC_AHB2ENR_GPIOEEN_Msk              (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk\n#define RCC_AHB2ENR_GPIOFEN_Pos              (5U)\n#define RCC_AHB2ENR_GPIOFEN_Msk              (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk\n#define RCC_AHB2ENR_GPIOGEN_Pos              (6U)\n#define RCC_AHB2ENR_GPIOGEN_Msk              (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk\n#define RCC_AHB2ENR_GPIOHEN_Pos              (7U)\n#define RCC_AHB2ENR_GPIOHEN_Msk              (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk\n#define RCC_AHB2ENR_GPIOIEN_Pos              (8U)\n#define RCC_AHB2ENR_GPIOIEN_Msk              (0x1U << RCC_AHB2ENR_GPIOIEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB2ENR_GPIOIEN                  RCC_AHB2ENR_GPIOIEN_Msk\n#define RCC_AHB2ENR_OTGFSEN_Pos              (12U)\n#define RCC_AHB2ENR_OTGFSEN_Msk              (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB2ENR_OTGFSEN                  RCC_AHB2ENR_OTGFSEN_Msk\n#define RCC_AHB2ENR_ADCEN_Pos                (13U)\n#define RCC_AHB2ENR_ADCEN_Msk                (0x1U << RCC_AHB2ENR_ADCEN_Pos)   /*!< 0x00002000 */\n#define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk\n#define RCC_AHB2ENR_DCMIEN_Pos               (14U)\n#define RCC_AHB2ENR_DCMIEN_Msk               (0x1U << RCC_AHB2ENR_DCMIEN_Pos)  /*!< 0x00004000 */\n#define RCC_AHB2ENR_DCMIEN                   RCC_AHB2ENR_DCMIEN_Msk\n#define RCC_AHB2ENR_RNGEN_Pos                (18U)\n#define RCC_AHB2ENR_RNGEN_Msk                (0x1U << RCC_AHB2ENR_RNGEN_Pos)   /*!< 0x00040000 */\n#define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk\n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n#define RCC_AHB3ENR_FMCEN_Pos                (0U)\n#define RCC_AHB3ENR_FMCEN_Msk                (0x1U << RCC_AHB3ENR_FMCEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk\n#define RCC_AHB3ENR_QSPIEN_Pos               (8U)\n#define RCC_AHB3ENR_QSPIEN_Msk               (0x1U << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */\n#define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk\n\n/********************  Bit definition for RCC_APB1ENR1 register  ***************/\n#define RCC_APB1ENR1_TIM2EN_Pos              (0U)\n#define RCC_APB1ENR1_TIM2EN_Msk              (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */\n#define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk\n#define RCC_APB1ENR1_TIM3EN_Pos              (1U)\n#define RCC_APB1ENR1_TIM3EN_Msk              (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */\n#define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk\n#define RCC_APB1ENR1_TIM4EN_Pos              (2U)\n#define RCC_APB1ENR1_TIM4EN_Msk              (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */\n#define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk\n#define RCC_APB1ENR1_TIM5EN_Pos              (3U)\n#define RCC_APB1ENR1_TIM5EN_Msk              (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */\n#define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk\n#define RCC_APB1ENR1_TIM6EN_Pos              (4U)\n#define RCC_APB1ENR1_TIM6EN_Msk              (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */\n#define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk\n#define RCC_APB1ENR1_TIM7EN_Pos              (5U)\n#define RCC_APB1ENR1_TIM7EN_Msk              (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */\n#define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk\n#define RCC_APB1ENR1_LCDEN_Pos               (9U)\n#define RCC_APB1ENR1_LCDEN_Msk               (0x1U << RCC_APB1ENR1_LCDEN_Pos)  /*!< 0x00000200 */\n#define RCC_APB1ENR1_LCDEN                   RCC_APB1ENR1_LCDEN_Msk\n#define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)\n#define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */\n#define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk\n#define RCC_APB1ENR1_WWDGEN_Pos              (11U)\n#define RCC_APB1ENR1_WWDGEN_Msk              (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk\n#define RCC_APB1ENR1_SPI2EN_Pos              (14U)\n#define RCC_APB1ENR1_SPI2EN_Msk              (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */\n#define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk\n#define RCC_APB1ENR1_SPI3EN_Pos              (15U)\n#define RCC_APB1ENR1_SPI3EN_Msk              (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */\n#define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk\n#define RCC_APB1ENR1_USART2EN_Pos            (17U)\n#define RCC_APB1ENR1_USART2EN_Msk            (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */\n#define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk\n#define RCC_APB1ENR1_USART3EN_Pos            (18U)\n#define RCC_APB1ENR1_USART3EN_Msk            (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */\n#define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk\n#define RCC_APB1ENR1_UART4EN_Pos             (19U)\n#define RCC_APB1ENR1_UART4EN_Msk             (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */\n#define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk\n#define RCC_APB1ENR1_UART5EN_Pos             (20U)\n#define RCC_APB1ENR1_UART5EN_Msk             (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */\n#define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk\n#define RCC_APB1ENR1_I2C1EN_Pos              (21U)\n#define RCC_APB1ENR1_I2C1EN_Msk              (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */\n#define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk\n#define RCC_APB1ENR1_I2C2EN_Pos              (22U)\n#define RCC_APB1ENR1_I2C2EN_Msk              (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */\n#define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk\n#define RCC_APB1ENR1_I2C3EN_Pos              (23U)\n#define RCC_APB1ENR1_I2C3EN_Msk              (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */\n#define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk\n#define RCC_APB1ENR1_CRSEN_Pos               (24U)\n#define RCC_APB1ENR1_CRSEN_Msk               (0x1U << RCC_APB1ENR1_CRSEN_Pos)  /*!< 0x01000000 */\n#define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk\n#define RCC_APB1ENR1_CAN1EN_Pos              (25U)\n#define RCC_APB1ENR1_CAN1EN_Msk              (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */\n#define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk\n#define RCC_APB1ENR1_CAN2EN_Pos              (26U)\n#define RCC_APB1ENR1_CAN2EN_Msk              (0x1U << RCC_APB1ENR1_CAN2EN_Pos) /*!< 0x04000000 */\n#define RCC_APB1ENR1_CAN2EN                  RCC_APB1ENR1_CAN2EN_Msk\n#define RCC_APB1ENR1_PWREN_Pos               (28U)\n#define RCC_APB1ENR1_PWREN_Msk               (0x1U << RCC_APB1ENR1_PWREN_Pos)  /*!< 0x10000000 */\n#define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk\n#define RCC_APB1ENR1_DAC1EN_Pos              (29U)\n#define RCC_APB1ENR1_DAC1EN_Msk              (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */\n#define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk\n#define RCC_APB1ENR1_OPAMPEN_Pos             (30U)\n#define RCC_APB1ENR1_OPAMPEN_Msk             (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */\n#define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk\n#define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)\n#define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */\n#define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk\n\n/********************  Bit definition for RCC_APB1RSTR2 register  **************/\n#define RCC_APB1ENR2_LPUART1EN_Pos           (0U)\n#define RCC_APB1ENR2_LPUART1EN_Msk           (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */\n#define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk\n#define RCC_APB1ENR2_I2C4EN_Pos              (1U)\n#define RCC_APB1ENR2_I2C4EN_Msk              (0x1U << RCC_APB1ENR2_I2C4EN_Pos) /*!< 0x00000002 */\n#define RCC_APB1ENR2_I2C4EN                  RCC_APB1ENR2_I2C4EN_Msk\n#define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)\n#define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */\n#define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk\n#define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)\n#define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */\n#define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk\n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_SYSCFGEN_Pos             (0U)\n#define RCC_APB2ENR_SYSCFGEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk\n#define RCC_APB2ENR_FWEN_Pos                 (7U)\n#define RCC_APB2ENR_FWEN_Msk                 (0x1U << RCC_APB2ENR_FWEN_Pos)    /*!< 0x00000080 */\n#define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk\n#define RCC_APB2ENR_SDMMC1EN_Pos             (10U)\n#define RCC_APB2ENR_SDMMC1EN_Msk             (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */\n#define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk\n#define RCC_APB2ENR_TIM1EN_Pos               (11U)\n#define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */\n#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk\n#define RCC_APB2ENR_SPI1EN_Pos               (12U)\n#define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk\n#define RCC_APB2ENR_TIM8EN_Pos               (13U)\n#define RCC_APB2ENR_TIM8EN_Msk               (0x1U << RCC_APB2ENR_TIM8EN_Pos)  /*!< 0x00002000 */\n#define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk\n#define RCC_APB2ENR_USART1EN_Pos             (14U)\n#define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */\n#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk\n#define RCC_APB2ENR_TIM15EN_Pos              (16U)\n#define RCC_APB2ENR_TIM15EN_Msk              (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk\n#define RCC_APB2ENR_TIM16EN_Pos              (17U)\n#define RCC_APB2ENR_TIM16EN_Msk              (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk\n#define RCC_APB2ENR_TIM17EN_Pos              (18U)\n#define RCC_APB2ENR_TIM17EN_Msk              (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk\n#define RCC_APB2ENR_SAI1EN_Pos               (21U)\n#define RCC_APB2ENR_SAI1EN_Msk               (0x1U << RCC_APB2ENR_SAI1EN_Pos)  /*!< 0x00200000 */\n#define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk\n#define RCC_APB2ENR_SAI2EN_Pos               (22U)\n#define RCC_APB2ENR_SAI2EN_Msk               (0x1U << RCC_APB2ENR_SAI2EN_Pos)  /*!< 0x00400000 */\n#define RCC_APB2ENR_SAI2EN                   RCC_APB2ENR_SAI2EN_Msk\n#define RCC_APB2ENR_DFSDM1EN_Pos             (24U)\n#define RCC_APB2ENR_DFSDM1EN_Msk             (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */\n#define RCC_APB2ENR_DFSDM1EN                 RCC_APB2ENR_DFSDM1EN_Msk\n\n/********************  Bit definition for RCC_AHB1SMENR register  ***************/\n#define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)\n#define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk\n#define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)\n#define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk\n#define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)\n#define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk\n#define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)\n#define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */\n#define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk\n#define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)\n#define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk\n#define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)\n#define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk\n#define RCC_AHB1SMENR_DMA2DSMEN_Pos          (17U)\n#define RCC_AHB1SMENR_DMA2DSMEN_Msk          (0x1U << RCC_AHB1SMENR_DMA2DSMEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1SMENR_DMA2DSMEN              RCC_AHB1SMENR_DMA2DSMEN_Msk\n\n/********************  Bit definition for RCC_AHB2SMENR register  *************/\n#define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)\n#define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk\n#define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)\n#define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk\n#define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)\n#define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk\n#define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)\n#define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk\n#define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)\n#define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk\n#define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)\n#define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk\n#define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)\n#define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk\n#define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)\n#define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk\n#define RCC_AHB2SMENR_GPIOISMEN_Pos          (8U)\n#define RCC_AHB2SMENR_GPIOISMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOISMEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB2SMENR_GPIOISMEN              RCC_AHB2SMENR_GPIOISMEN_Msk\n#define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)\n#define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */\n#define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk\n#define RCC_AHB2SMENR_OTGFSSMEN_Pos          (12U)\n#define RCC_AHB2SMENR_OTGFSSMEN_Msk          (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB2SMENR_OTGFSSMEN              RCC_AHB2SMENR_OTGFSSMEN_Msk\n#define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)\n#define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */\n#define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk\n#define RCC_AHB2SMENR_DCMISMEN_Pos           (14U)\n#define RCC_AHB2SMENR_DCMISMEN_Msk           (0x1U << RCC_AHB2SMENR_DCMISMEN_Pos) /*!< 0x00004000 */\n#define RCC_AHB2SMENR_DCMISMEN               RCC_AHB2SMENR_DCMISMEN_Msk\n#define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)\n#define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk\n\n/********************  Bit definition for RCC_AHB3SMENR register  *************/\n#define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)\n#define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk\n#define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)\n#define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk\n\n/********************  Bit definition for RCC_APB1SMENR1 register  *************/\n#define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)\n#define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk\n#define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)\n#define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk\n#define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)\n#define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk\n#define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)\n#define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk\n#define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)\n#define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk\n#define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)\n#define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk\n#define RCC_APB1SMENR1_LCDSMEN_Pos           (9U)\n#define RCC_APB1SMENR1_LCDSMEN_Msk           (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */\n#define RCC_APB1SMENR1_LCDSMEN               RCC_APB1SMENR1_LCDSMEN_Msk\n#define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)\n#define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */\n#define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk\n#define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)\n#define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk\n#define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)\n#define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk\n#define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)\n#define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk\n#define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)\n#define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk\n#define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)\n#define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk\n#define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)\n#define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk\n#define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)\n#define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk\n#define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)\n#define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk\n#define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)\n#define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk\n#define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)\n#define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk\n#define RCC_APB1SMENR1_CRSSMEN_Pos           (24U)\n#define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */\n#define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk\n#define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)\n#define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk\n#define RCC_APB1SMENR1_CAN2SMEN_Pos          (26U)\n#define RCC_APB1SMENR1_CAN2SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN2SMEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1SMENR1_CAN2SMEN              RCC_APB1SMENR1_CAN2SMEN_Msk\n#define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)\n#define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk\n#define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)\n#define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk\n#define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)\n#define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */\n#define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk\n#define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)\n#define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */\n#define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk\n\n/********************  Bit definition for RCC_APB1SMENR2 register  *************/\n#define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)\n#define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk\n#define RCC_APB1SMENR2_I2C4SMEN_Pos          (1U)\n#define RCC_APB1SMENR2_I2C4SMEN_Msk          (0x1U << RCC_APB1SMENR2_I2C4SMEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1SMENR2_I2C4SMEN              RCC_APB1SMENR2_I2C4SMEN_Msk\n#define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)\n#define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk\n#define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)\n#define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk\n\n/********************  Bit definition for RCC_APB2SMENR register  *************/\n#define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)\n#define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk\n#define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)\n#define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */\n#define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk\n#define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)\n#define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk\n#define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)\n#define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk\n#define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)\n#define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */\n#define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk\n#define RCC_APB2SMENR_USART1SMEN_Pos         (14U)\n#define RCC_APB2SMENR_USART1SMEN_Msk         (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk\n#define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)\n#define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk\n#define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)\n#define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk\n#define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)\n#define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk\n#define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)\n#define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */\n#define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk\n#define RCC_APB2SMENR_SAI2SMEN_Pos           (22U)\n#define RCC_APB2SMENR_SAI2SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */\n#define RCC_APB2SMENR_SAI2SMEN               RCC_APB2SMENR_SAI2SMEN_Msk\n#define RCC_APB2SMENR_DFSDM1SMEN_Pos         (24U)\n#define RCC_APB2SMENR_DFSDM1SMEN_Msk         (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */\n#define RCC_APB2SMENR_DFSDM1SMEN             RCC_APB2SMENR_DFSDM1SMEN_Msk\n\n/********************  Bit definition for RCC_CCIPR register  ******************/\n#define RCC_CCIPR_USART1SEL_Pos              (0U)\n#define RCC_CCIPR_USART1SEL_Msk              (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */\n#define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk\n#define RCC_CCIPR_USART1SEL_0                (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */\n#define RCC_CCIPR_USART1SEL_1                (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */\n\n#define RCC_CCIPR_USART2SEL_Pos              (2U)\n#define RCC_CCIPR_USART2SEL_Msk              (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */\n#define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk\n#define RCC_CCIPR_USART2SEL_0                (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */\n#define RCC_CCIPR_USART2SEL_1                (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */\n\n#define RCC_CCIPR_USART3SEL_Pos              (4U)\n#define RCC_CCIPR_USART3SEL_Msk              (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */\n#define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk\n#define RCC_CCIPR_USART3SEL_0                (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */\n#define RCC_CCIPR_USART3SEL_1                (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */\n\n#define RCC_CCIPR_UART4SEL_Pos               (6U)\n#define RCC_CCIPR_UART4SEL_Msk               (0x3U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x000000C0 */\n#define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk\n#define RCC_CCIPR_UART4SEL_0                 (0x1U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000040 */\n#define RCC_CCIPR_UART4SEL_1                 (0x2U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000080 */\n\n#define RCC_CCIPR_UART5SEL_Pos               (8U)\n#define RCC_CCIPR_UART5SEL_Msk               (0x3U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000300 */\n#define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk\n#define RCC_CCIPR_UART5SEL_0                 (0x1U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000100 */\n#define RCC_CCIPR_UART5SEL_1                 (0x2U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000200 */\n\n#define RCC_CCIPR_LPUART1SEL_Pos             (10U)\n#define RCC_CCIPR_LPUART1SEL_Msk             (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */\n#define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk\n#define RCC_CCIPR_LPUART1SEL_0               (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */\n#define RCC_CCIPR_LPUART1SEL_1               (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */\n\n#define RCC_CCIPR_I2C1SEL_Pos                (12U)\n#define RCC_CCIPR_I2C1SEL_Msk                (0x3U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */\n#define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk\n#define RCC_CCIPR_I2C1SEL_0                  (0x1U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */\n#define RCC_CCIPR_I2C1SEL_1                  (0x2U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */\n\n#define RCC_CCIPR_I2C2SEL_Pos                (14U)\n#define RCC_CCIPR_I2C2SEL_Msk                (0x3U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */\n#define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk\n#define RCC_CCIPR_I2C2SEL_0                  (0x1U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */\n#define RCC_CCIPR_I2C2SEL_1                  (0x2U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */\n\n#define RCC_CCIPR_I2C3SEL_Pos                (16U)\n#define RCC_CCIPR_I2C3SEL_Msk                (0x3U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */\n#define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk\n#define RCC_CCIPR_I2C3SEL_0                  (0x1U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */\n#define RCC_CCIPR_I2C3SEL_1                  (0x2U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */\n\n#define RCC_CCIPR_LPTIM1SEL_Pos              (18U)\n#define RCC_CCIPR_LPTIM1SEL_Msk              (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */\n#define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk\n#define RCC_CCIPR_LPTIM1SEL_0                (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */\n#define RCC_CCIPR_LPTIM1SEL_1                (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */\n\n#define RCC_CCIPR_LPTIM2SEL_Pos              (20U)\n#define RCC_CCIPR_LPTIM2SEL_Msk              (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */\n#define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk\n#define RCC_CCIPR_LPTIM2SEL_0                (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */\n#define RCC_CCIPR_LPTIM2SEL_1                (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */\n\n#define RCC_CCIPR_SAI1SEL_Pos                (22U)\n#define RCC_CCIPR_SAI1SEL_Msk                (0x3U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00C00000 */\n#define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk\n#define RCC_CCIPR_SAI1SEL_0                  (0x1U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00400000 */\n#define RCC_CCIPR_SAI1SEL_1                  (0x2U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00800000 */\n\n#define RCC_CCIPR_SAI2SEL_Pos                (24U)\n#define RCC_CCIPR_SAI2SEL_Msk                (0x3U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x03000000 */\n#define RCC_CCIPR_SAI2SEL                    RCC_CCIPR_SAI2SEL_Msk\n#define RCC_CCIPR_SAI2SEL_0                  (0x1U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x01000000 */\n#define RCC_CCIPR_SAI2SEL_1                  (0x2U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x02000000 */\n\n#define RCC_CCIPR_CLK48SEL_Pos               (26U)\n#define RCC_CCIPR_CLK48SEL_Msk               (0x3U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */\n#define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk\n#define RCC_CCIPR_CLK48SEL_0                 (0x1U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x04000000 */\n#define RCC_CCIPR_CLK48SEL_1                 (0x2U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x08000000 */\n\n#define RCC_CCIPR_ADCSEL_Pos                 (28U)\n#define RCC_CCIPR_ADCSEL_Msk                 (0x3U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */\n#define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk\n#define RCC_CCIPR_ADCSEL_0                   (0x1U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */\n#define RCC_CCIPR_ADCSEL_1                   (0x2U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */\n\n#define RCC_CCIPR_SWPMI1SEL_Pos              (30U)\n#define RCC_CCIPR_SWPMI1SEL_Msk              (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */\n#define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk\n\n#define RCC_CCIPR_DFSDM1SEL_Pos              (31U)\n#define RCC_CCIPR_DFSDM1SEL_Msk              (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */\n#define RCC_CCIPR_DFSDM1SEL                  RCC_CCIPR_DFSDM1SEL_Msk\n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                   (0U)\n#define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk\n#define RCC_BDCR_LSERDY_Pos                  (1U)\n#define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk\n#define RCC_BDCR_LSEBYP_Pos                  (2U)\n#define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk\n\n#define RCC_BDCR_LSEDRV_Pos                  (3U)\n#define RCC_BDCR_LSEDRV_Msk                  (0x3U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */\n#define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk\n#define RCC_BDCR_LSEDRV_0                    (0x1U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */\n#define RCC_BDCR_LSEDRV_1                    (0x2U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */\n\n#define RCC_BDCR_LSECSSON_Pos                (5U)\n#define RCC_BDCR_LSECSSON_Msk                (0x1U << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */\n#define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk\n#define RCC_BDCR_LSECSSD_Pos                 (6U)\n#define RCC_BDCR_LSECSSD_Msk                 (0x1U << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */\n#define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk\n\n#define RCC_BDCR_RTCSEL_Pos                  (8U)\n#define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk\n#define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                   (15U)\n#define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk\n#define RCC_BDCR_BDRST_Pos                   (16U)\n#define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk\n#define RCC_BDCR_LSCOEN_Pos                  (24U)\n#define RCC_BDCR_LSCOEN_Msk                  (0x1U << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */\n#define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk\n#define RCC_BDCR_LSCOSEL_Pos                 (25U)\n#define RCC_BDCR_LSCOSEL_Msk                 (0x1U << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */\n#define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk\n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                    (0U)\n#define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */\n#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk\n#define RCC_CSR_LSIRDY_Pos                   (1U)\n#define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk\n\n#define RCC_CSR_MSISRANGE_Pos                (8U)\n#define RCC_CSR_MSISRANGE_Msk                (0xFU << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000F00 */\n#define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk\n#define RCC_CSR_MSISRANGE_1                  (0x4U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000400 */\n#define RCC_CSR_MSISRANGE_2                  (0x5U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000500 */\n#define RCC_CSR_MSISRANGE_4                  (0x6U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000600 */\n#define RCC_CSR_MSISRANGE_8                  (0x7U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000700 */\n\n#define RCC_CSR_RMVF_Pos                     (23U)\n#define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */\n#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk\n#define RCC_CSR_FWRSTF_Pos                   (24U)\n#define RCC_CSR_FWRSTF_Msk                   (0x1U << RCC_CSR_FWRSTF_Pos)      /*!< 0x01000000 */\n#define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk\n#define RCC_CSR_OBLRSTF_Pos                  (25U)\n#define RCC_CSR_OBLRSTF_Msk                  (0x1U << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */\n#define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk\n#define RCC_CSR_PINRSTF_Pos                  (26U)\n#define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_BORRSTF_Pos                  (27U)\n#define RCC_CSR_BORRSTF_Msk                  (0x1U << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */\n#define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk\n#define RCC_CSR_SFTRSTF_Pos                  (28U)\n#define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk\n#define RCC_CSR_IWDGRSTF_Pos                 (29U)\n#define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos                 (30U)\n#define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk\n#define RCC_CSR_LPWRRSTF_Pos                 (31U)\n#define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk\n\n/********************  Bit definition for RCC_CRRCR register  *****************/\n#define RCC_CRRCR_HSI48ON_Pos                (0U)\n#define RCC_CRRCR_HSI48ON_Msk                (0x1U << RCC_CRRCR_HSI48ON_Pos)   /*!< 0x00000001 */\n#define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk\n#define RCC_CRRCR_HSI48RDY_Pos               (1U)\n#define RCC_CRRCR_HSI48RDY_Msk               (0x1U << RCC_CRRCR_HSI48RDY_Pos)  /*!< 0x00000002 */\n#define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk\n\n/*!< HSI48CAL configuration */\n#define RCC_CRRCR_HSI48CAL_Pos               (7U)\n#define RCC_CRRCR_HSI48CAL_Msk               (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */\n#define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */\n#define RCC_CRRCR_HSI48CAL_0                 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */\n#define RCC_CRRCR_HSI48CAL_1                 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */\n#define RCC_CRRCR_HSI48CAL_2                 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */\n#define RCC_CRRCR_HSI48CAL_3                 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */\n#define RCC_CRRCR_HSI48CAL_4                 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */\n#define RCC_CRRCR_HSI48CAL_5                 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */\n#define RCC_CRRCR_HSI48CAL_6                 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */\n#define RCC_CRRCR_HSI48CAL_7                 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */\n#define RCC_CRRCR_HSI48CAL_8                 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */\n\n/********************  Bit definition for RCC_CCIPR2 register  ******************/\n#define RCC_CCIPR2_I2C4SEL_Pos               (0U)\n#define RCC_CCIPR2_I2C4SEL_Msk               (0x3U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000003 */\n#define RCC_CCIPR2_I2C4SEL                   RCC_CCIPR2_I2C4SEL_Msk\n#define RCC_CCIPR2_I2C4SEL_0                 (0x1U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000001 */\n#define RCC_CCIPR2_I2C4SEL_1                 (0x2U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000002 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)\n#define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk\n#define RNG_CR_IE_Pos       (3U)\n#define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk\n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)\n#define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk\n#define RNG_SR_CECS_Pos     (1U)\n#define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk\n#define RNG_SR_SECS_Pos     (2U)\n#define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk\n#define RNG_SR_CEIS_Pos     (5U)\n#define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk\n#define RNG_SR_SEIS_Pos     (6U)\n#define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/*\n* @brief Specific device feature definitions\n*/\n#define RTC_TAMPER1_SUPPORT\n#define RTC_TAMPER2_SUPPORT\n#define RTC_TAMPER3_SUPPORT\n#define RTC_WAKEUP_SUPPORT\n#define RTC_BACKUP_SUPPORT\n\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                  (22U)\n#define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */\n#define RTC_TR_PM                      RTC_TR_PM_Msk\n#define RTC_TR_HT_Pos                  (20U)\n#define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */\n#define RTC_TR_HT                      RTC_TR_HT_Msk\n#define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */\n#define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                  (16U)\n#define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */\n#define RTC_TR_HU                      RTC_TR_HU_Msk\n#define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */\n#define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */\n#define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */\n#define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                 (12U)\n#define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */\n#define RTC_TR_MNT                     RTC_TR_MNT_Msk\n#define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */\n#define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */\n#define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                 (8U)\n#define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */\n#define RTC_TR_MNU                     RTC_TR_MNU_Msk\n#define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */\n#define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */\n#define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */\n#define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                  (4U)\n#define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */\n#define RTC_TR_ST                      RTC_TR_ST_Msk\n#define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */\n#define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */\n#define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                  (0U)\n#define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */\n#define RTC_TR_SU                      RTC_TR_SU_Msk\n#define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */\n#define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */\n#define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */\n#define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                  (20U)\n#define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */\n#define RTC_DR_YT                      RTC_DR_YT_Msk\n#define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */\n#define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */\n#define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */\n#define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                  (16U)\n#define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */\n#define RTC_DR_YU                      RTC_DR_YU_Msk\n#define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */\n#define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */\n#define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */\n#define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                 (13U)\n#define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */\n#define RTC_DR_WDU                     RTC_DR_WDU_Msk\n#define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */\n#define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */\n#define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                  (12U)\n#define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */\n#define RTC_DR_MT                      RTC_DR_MT_Msk\n#define RTC_DR_MU_Pos                  (8U)\n#define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */\n#define RTC_DR_MU                      RTC_DR_MU_Msk\n#define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */\n#define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */\n#define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */\n#define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                  (4U)\n#define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */\n#define RTC_DR_DT                      RTC_DR_DT_Msk\n#define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */\n#define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                  (0U)\n#define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */\n#define RTC_DR_DU                      RTC_DR_DU_Msk\n#define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */\n#define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */\n#define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */\n#define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_ITSE_Pos                (24U)\n#define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */\n#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk\n#define RTC_CR_COE_Pos                 (23U)\n#define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */\n#define RTC_CR_COE                     RTC_CR_COE_Msk\n#define RTC_CR_OSEL_Pos                (21U)\n#define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */\n#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk\n#define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                 (20U)\n#define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */\n#define RTC_CR_POL                     RTC_CR_POL_Msk\n#define RTC_CR_COSEL_Pos               (19U)\n#define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */\n#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk\n#define RTC_CR_BKP_Pos                 (18U)\n#define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk\n#define RTC_CR_SUB1H_Pos               (17U)\n#define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */\n#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk\n#define RTC_CR_ADD1H_Pos               (16U)\n#define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */\n#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk\n#define RTC_CR_TSIE_Pos                (15U)\n#define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */\n#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk\n#define RTC_CR_WUTIE_Pos               (14U)\n#define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */\n#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk\n#define RTC_CR_ALRBIE_Pos              (13U)\n#define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk\n#define RTC_CR_ALRAIE_Pos              (12U)\n#define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk\n#define RTC_CR_TSE_Pos                 (11U)\n#define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */\n#define RTC_CR_TSE                     RTC_CR_TSE_Msk\n#define RTC_CR_WUTE_Pos                (10U)\n#define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */\n#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk\n#define RTC_CR_ALRBE_Pos               (9U)\n#define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */\n#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk\n#define RTC_CR_ALRAE_Pos               (8U)\n#define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */\n#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk\n#define RTC_CR_FMT_Pos                 (6U)\n#define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */\n#define RTC_CR_FMT                     RTC_CR_FMT_Msk\n#define RTC_CR_BYPSHAD_Pos             (5U)\n#define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk\n#define RTC_CR_REFCKON_Pos             (4U)\n#define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */\n#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk\n#define RTC_CR_TSEDGE_Pos              (3U)\n#define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk\n#define RTC_CR_WUCKSEL_Pos             (0U)\n#define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk\n#define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos\n#define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_ITSF_Pos               (17U)\n#define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */\n#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk\n#define RTC_ISR_RECALPF_Pos            (16U)\n#define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */\n#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk\n#define RTC_ISR_TAMP3F_Pos             (15U)\n#define RTC_ISR_TAMP3F_Msk             (0x1U << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */\n#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk\n#define RTC_ISR_TAMP2F_Pos             (14U)\n#define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk\n#define RTC_ISR_TAMP1F_Pos             (13U)\n#define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk\n#define RTC_ISR_TSOVF_Pos              (12U)\n#define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk\n#define RTC_ISR_TSF_Pos                (11U)\n#define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */\n#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk\n#define RTC_ISR_WUTF_Pos               (10U)\n#define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */\n#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk\n#define RTC_ISR_ALRBF_Pos              (9U)\n#define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk\n#define RTC_ISR_ALRAF_Pos              (8U)\n#define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk\n#define RTC_ISR_INIT_Pos               (7U)\n#define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */\n#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk\n#define RTC_ISR_INITF_Pos              (6U)\n#define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */\n#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk\n#define RTC_ISR_RSF_Pos                (5U)\n#define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */\n#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk\n#define RTC_ISR_INITS_Pos              (4U)\n#define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */\n#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk\n#define RTC_ISR_SHPF_Pos               (3U)\n#define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */\n#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk\n#define RTC_ISR_WUTWF_Pos              (2U)\n#define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk\n#define RTC_ISR_ALRBWF_Pos             (1U)\n#define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk\n#define RTC_ISR_ALRAWF_Pos             (0U)\n#define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk\n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos          (16U)\n#define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk\n#define RTC_PRER_PREDIV_S_Pos          (0U)\n#define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk\n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos               (0U)\n#define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk\n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos            (31U)\n#define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk\n#define RTC_ALRMAR_WDSEL_Pos           (30U)\n#define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk\n#define RTC_ALRMAR_DT_Pos              (28U)\n#define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk\n#define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos              (24U)\n#define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk\n#define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos            (23U)\n#define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk\n#define RTC_ALRMAR_PM_Pos              (22U)\n#define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk\n#define RTC_ALRMAR_HT_Pos              (20U)\n#define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk\n#define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos              (16U)\n#define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk\n#define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos            (15U)\n#define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk\n#define RTC_ALRMAR_MNT_Pos             (12U)\n#define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk\n#define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos             (8U)\n#define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk\n#define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos            (7U)\n#define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk\n#define RTC_ALRMAR_ST_Pos              (4U)\n#define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk\n#define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos              (0U)\n#define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk\n#define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos            (31U)\n#define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk\n#define RTC_ALRMBR_WDSEL_Pos           (30U)\n#define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk\n#define RTC_ALRMBR_DT_Pos              (28U)\n#define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk\n#define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos              (24U)\n#define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk\n#define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos            (23U)\n#define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk\n#define RTC_ALRMBR_PM_Pos              (22U)\n#define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk\n#define RTC_ALRMBR_HT_Pos              (20U)\n#define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk\n#define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos              (16U)\n#define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk\n#define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos            (15U)\n#define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk\n#define RTC_ALRMBR_MNT_Pos             (12U)\n#define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk\n#define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos             (8U)\n#define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk\n#define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos            (7U)\n#define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk\n#define RTC_ALRMBR_ST_Pos              (4U)\n#define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk\n#define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos              (0U)\n#define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk\n#define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos                (0U)\n#define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */\n#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk\n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                 (0U)\n#define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */\n#define RTC_SSR_SS                     RTC_SSR_SS_Msk\n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos           (0U)\n#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk\n#define RTC_SHIFTR_ADD1S_Pos           (31U)\n#define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk\n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos                (22U)\n#define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */\n#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk\n#define RTC_TSTR_HT_Pos                (20U)\n#define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */\n#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk\n#define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos                (16U)\n#define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */\n#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk\n#define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos               (12U)\n#define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */\n#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk\n#define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos               (8U)\n#define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk\n#define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos                (4U)\n#define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */\n#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk\n#define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos                (0U)\n#define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */\n#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk\n#define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos               (13U)\n#define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk\n#define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos                (12U)\n#define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */\n#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk\n#define RTC_TSDR_MU_Pos                (8U)\n#define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk\n#define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos                (4U)\n#define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */\n#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk\n#define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos                (0U)\n#define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */\n#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk\n#define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos               (0U)\n#define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk\n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos              (15U)\n#define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */\n#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk\n#define RTC_CALR_CALW8_Pos             (14U)\n#define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */\n#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk\n#define RTC_CALR_CALW16_Pos            (13U)\n#define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */\n#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk\n#define RTC_CALR_CALM_Pos              (0U)\n#define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */\n#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk\n#define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */\n#define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */\n#define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */\n#define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */\n#define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */\n#define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */\n#define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */\n#define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */\n#define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAMPCR register  ***************/\n#define RTC_TAMPCR_TAMP3MF_Pos         (24U)\n#define RTC_TAMPCR_TAMP3MF_Msk         (0x1U << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */\n#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk\n#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)\n#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */\n#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk\n#define RTC_TAMPCR_TAMP3IE_Pos         (22U)\n#define RTC_TAMPCR_TAMP3IE_Msk         (0x1U << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */\n#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk\n#define RTC_TAMPCR_TAMP2MF_Pos         (21U)\n#define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */\n#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk\n#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)\n#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */\n#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk\n#define RTC_TAMPCR_TAMP2IE_Pos         (19U)\n#define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */\n#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk\n#define RTC_TAMPCR_TAMP1MF_Pos         (18U)\n#define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */\n#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk\n#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)\n#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */\n#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk\n#define RTC_TAMPCR_TAMP1IE_Pos         (16U)\n#define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */\n#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk\n#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)\n#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */\n#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk\n#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)\n#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */\n#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk\n#define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */\n#define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */\n#define RTC_TAMPCR_TAMPFLT_Pos         (11U)\n#define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */\n#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk\n#define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */\n#define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */\n#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)\n#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */\n#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk\n#define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */\n#define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */\n#define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */\n#define RTC_TAMPCR_TAMPTS_Pos          (7U)\n#define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */\n#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk\n#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)\n#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1U << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */\n#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk\n#define RTC_TAMPCR_TAMP3E_Pos          (5U)\n#define RTC_TAMPCR_TAMP3E_Msk          (0x1U << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */\n#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk\n#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)\n#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */\n#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk\n#define RTC_TAMPCR_TAMP2E_Pos          (3U)\n#define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */\n#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk\n#define RTC_TAMPCR_TAMPIE_Pos          (2U)\n#define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */\n#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk\n#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)\n#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */\n#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk\n#define RTC_TAMPCR_TAMP1E_Pos          (0U)\n#define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */\n#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos        (24U)\n#define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk\n#define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos            (0U)\n#define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk\n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos        (24U)\n#define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk\n#define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos            (0U)\n#define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk\n\n/********************  Bits definition for RTC_0R register  *******************/\n#define RTC_OR_OUT_RMP_Pos             (1U)\n#define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */\n#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk\n#define RTC_OR_ALARMOUTTYPE_Pos        (0U)\n#define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */\n#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk\n\n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                  (0U)\n#define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                      RTC_BKP0R_Msk\n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                  (0U)\n#define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                      RTC_BKP1R_Msk\n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                  (0U)\n#define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                      RTC_BKP2R_Msk\n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                  (0U)\n#define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                      RTC_BKP3R_Msk\n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                  (0U)\n#define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                      RTC_BKP4R_Msk\n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                  (0U)\n#define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                      RTC_BKP5R_Msk\n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                  (0U)\n#define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                      RTC_BKP6R_Msk\n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                  (0U)\n#define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                      RTC_BKP7R_Msk\n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                  (0U)\n#define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                      RTC_BKP8R_Msk\n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                  (0U)\n#define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                      RTC_BKP9R_Msk\n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                 (0U)\n#define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                     RTC_BKP10R_Msk\n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                 (0U)\n#define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                     RTC_BKP11R_Msk\n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                 (0U)\n#define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                     RTC_BKP12R_Msk\n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                 (0U)\n#define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                     RTC_BKP13R_Msk\n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                 (0U)\n#define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                     RTC_BKP14R_Msk\n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                 (0U)\n#define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                     RTC_BKP15R_Msk\n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                 (0U)\n#define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                     RTC_BKP16R_Msk\n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                 (0U)\n#define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                     RTC_BKP17R_Msk\n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                 (0U)\n#define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                     RTC_BKP18R_Msk\n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                 (0U)\n#define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                     RTC_BKP19R_Msk\n\n/********************  Bits definition for RTC_BKP20R register  ***************/\n#define RTC_BKP20R_Pos                 (0U)\n#define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP20R                     RTC_BKP20R_Msk\n\n/********************  Bits definition for RTC_BKP21R register  ***************/\n#define RTC_BKP21R_Pos                 (0U)\n#define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP21R                     RTC_BKP21R_Msk\n\n/********************  Bits definition for RTC_BKP22R register  ***************/\n#define RTC_BKP22R_Pos                 (0U)\n#define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP22R                     RTC_BKP22R_Msk\n\n/********************  Bits definition for RTC_BKP23R register  ***************/\n#define RTC_BKP23R_Pos                 (0U)\n#define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP23R                     RTC_BKP23R_Msk\n\n/********************  Bits definition for RTC_BKP24R register  ***************/\n#define RTC_BKP24R_Pos                 (0U)\n#define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP24R                     RTC_BKP24R_Msk\n\n/********************  Bits definition for RTC_BKP25R register  ***************/\n#define RTC_BKP25R_Pos                 (0U)\n#define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP25R                     RTC_BKP25R_Msk\n\n/********************  Bits definition for RTC_BKP26R register  ***************/\n#define RTC_BKP26R_Pos                 (0U)\n#define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP26R                     RTC_BKP26R_Msk\n\n/********************  Bits definition for RTC_BKP27R register  ***************/\n#define RTC_BKP27R_Pos                 (0U)\n#define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP27R                     RTC_BKP27R_Msk\n\n/********************  Bits definition for RTC_BKP28R register  ***************/\n#define RTC_BKP28R_Pos                 (0U)\n#define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP28R                     RTC_BKP28R_Msk\n\n/********************  Bits definition for RTC_BKP29R register  ***************/\n#define RTC_BKP29R_Pos                 (0U)\n#define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP29R                     RTC_BKP29R_Msk\n\n/********************  Bits definition for RTC_BKP30R register  ***************/\n#define RTC_BKP30R_Pos                 (0U)\n#define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP30R                     RTC_BKP30R_Msk\n\n/********************  Bits definition for RTC_BKP31R register  ***************/\n#define RTC_BKP31R_Pos                 (0U)\n#define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */\n#define RTC_BKP31R                     RTC_BKP31R_Msk\n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       32U\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Serial Audio Interface                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for SAI_GCR register  *******************/\n#define SAI_GCR_SYNCIN_Pos         (0U)\n#define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */\n#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\n#define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */\n#define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */\n\n#define SAI_GCR_SYNCOUT_Pos        (4U)\n#define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */\n#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\n#define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */\n#define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */\n\n/*******************  Bit definition for SAI_xCR1 register  *******************/\n#define SAI_xCR1_MODE_Pos          (0U)\n#define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */\n#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */\n#define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */\n#define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */\n\n#define SAI_xCR1_PRTCFG_Pos        (2U)\n#define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */\n#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\n#define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */\n#define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */\n\n#define SAI_xCR1_DS_Pos            (5U)\n#define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */\n#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */\n#define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */\n#define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */\n#define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */\n\n#define SAI_xCR1_LSBFIRST_Pos      (8U)\n#define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */\n#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */\n#define SAI_xCR1_CKSTR_Pos         (9U)\n#define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */\n#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */\n\n#define SAI_xCR1_SYNCEN_Pos        (10U)\n#define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */\n#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */\n#define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */\n#define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */\n\n#define SAI_xCR1_MONO_Pos          (12U)\n#define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */\n#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */\n#define SAI_xCR1_OUTDRIV_Pos       (13U)\n#define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */\n#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */\n#define SAI_xCR1_SAIEN_Pos         (16U)\n#define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */\n#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */\n#define SAI_xCR1_DMAEN_Pos         (17U)\n#define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */\n#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */\n#define SAI_xCR1_NODIV_Pos         (19U)\n#define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */\n#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */\n\n#define SAI_xCR1_MCKDIV_Pos        (20U)\n#define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */\n#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */\n#define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */\n#define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */\n#define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */\n#define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */\n\n/*******************  Bit definition for SAI_xCR2 register  *******************/\n#define SAI_xCR2_FTH_Pos           (0U)\n#define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */\n#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */\n#define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */\n#define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */\n#define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */\n\n#define SAI_xCR2_FFLUSH_Pos        (3U)\n#define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */\n#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */\n#define SAI_xCR2_TRIS_Pos          (4U)\n#define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */\n#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */\n#define SAI_xCR2_MUTE_Pos          (5U)\n#define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */\n#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */\n#define SAI_xCR2_MUTEVAL_Pos       (6U)\n#define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */\n#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */\n\n\n#define SAI_xCR2_MUTECNT_Pos       (7U)\n#define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */\n#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */\n#define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */\n#define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */\n#define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */\n#define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */\n#define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */\n#define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */\n\n#define SAI_xCR2_CPL_Pos           (13U)\n#define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */\n#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */\n#define SAI_xCR2_COMP_Pos          (14U)\n#define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */\n#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */\n#define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */\n#define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */\n\n\n/******************  Bit definition for SAI_xFRCR register  *******************/\n#define SAI_xFRCR_FRL_Pos          (0U)\n#define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */\n#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */\n#define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */\n#define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */\n#define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */\n#define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */\n#define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */\n#define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */\n#define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */\n#define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */\n\n#define SAI_xFRCR_FSALL_Pos        (8U)\n#define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */\n#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */\n#define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */\n#define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */\n#define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */\n#define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */\n#define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */\n#define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */\n#define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */\n\n#define SAI_xFRCR_FSDEF_Pos        (16U)\n#define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */\n#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */\n#define SAI_xFRCR_FSPOL_Pos        (17U)\n#define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */\n#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */\n#define SAI_xFRCR_FSOFF_Pos        (18U)\n#define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */\n#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */\n\n/******************  Bit definition for SAI_xSLOTR register  *******************/\n#define SAI_xSLOTR_FBOFF_Pos       (0U)\n#define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */\n#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */\n#define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */\n#define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */\n#define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */\n#define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */\n#define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */\n\n#define SAI_xSLOTR_SLOTSZ_Pos      (6U)\n#define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */\n#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */\n#define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */\n#define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */\n\n#define SAI_xSLOTR_NBSLOT_Pos      (8U)\n#define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */\n#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\n#define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */\n#define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */\n#define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */\n#define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */\n\n#define SAI_xSLOTR_SLOTEN_Pos      (16U)\n#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */\n#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */\n\n/*******************  Bit definition for SAI_xIMR register  *******************/\n#define SAI_xIMR_OVRUDRIE_Pos      (0U)\n#define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */\n#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */\n#define SAI_xIMR_MUTEDETIE_Pos     (1U)\n#define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */\n#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */\n#define SAI_xIMR_WCKCFGIE_Pos      (2U)\n#define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */\n#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */\n#define SAI_xIMR_FREQIE_Pos        (3U)\n#define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */\n#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */\n#define SAI_xIMR_CNRDYIE_Pos       (4U)\n#define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */\n#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */\n#define SAI_xIMR_AFSDETIE_Pos      (5U)\n#define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */\n#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */\n#define SAI_xIMR_LFSDETIE_Pos      (6U)\n#define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */\n#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */\n\n/********************  Bit definition for SAI_xSR register  *******************/\n#define SAI_xSR_OVRUDR_Pos         (0U)\n#define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */\n#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */\n#define SAI_xSR_MUTEDET_Pos        (1U)\n#define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */\n#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */\n#define SAI_xSR_WCKCFG_Pos         (2U)\n#define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */\n#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */\n#define SAI_xSR_FREQ_Pos           (3U)\n#define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */\n#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */\n#define SAI_xSR_CNRDY_Pos          (4U)\n#define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */\n#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */\n#define SAI_xSR_AFSDET_Pos         (5U)\n#define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */\n#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */\n#define SAI_xSR_LFSDET_Pos         (6U)\n#define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */\n#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */\n\n#define SAI_xSR_FLVL_Pos           (16U)\n#define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */\n#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */\n#define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */\n#define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */\n#define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */\n\n/******************  Bit definition for SAI_xCLRFR register  ******************/\n#define SAI_xCLRFR_COVRUDR_Pos     (0U)\n#define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */\n#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */\n#define SAI_xCLRFR_CMUTEDET_Pos    (1U)\n#define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */\n#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */\n#define SAI_xCLRFR_CWCKCFG_Pos     (2U)\n#define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */\n#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */\n#define SAI_xCLRFR_CFREQ_Pos       (3U)\n#define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */\n#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */\n#define SAI_xCLRFR_CCNRDY_Pos      (4U)\n#define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */\n#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */\n#define SAI_xCLRFR_CAFSDET_Pos     (5U)\n#define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */\n#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */\n#define SAI_xCLRFR_CLFSDET_Pos     (6U)\n#define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */\n#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */\n\n/******************  Bit definition for SAI_xDR register  ******************/\n#define SAI_xDR_DATA_Pos           (0U)\n#define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */\n#define SAI_xDR_DATA               SAI_xDR_DATA_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                          LCD Controller (LCD)                              */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for LCD_CR register  *********************/\n#define LCD_CR_LCDEN_Pos            (0U)\n#define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */\n#define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */\n#define LCD_CR_VSEL_Pos             (1U)\n#define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */\n#define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */\n\n#define LCD_CR_DUTY_Pos             (2U)\n#define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */\n#define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */\n#define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */\n#define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */\n#define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */\n\n#define LCD_CR_BIAS_Pos             (5U)\n#define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */\n#define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */\n#define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */\n#define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */\n\n#define LCD_CR_MUX_SEG_Pos          (7U)\n#define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */\n#define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */\n#define LCD_CR_BUFEN_Pos            (8U)\n#define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */\n#define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable */\n\n/*******************  Bit definition for LCD_FCR register  ********************/\n#define LCD_FCR_HD_Pos              (0U)\n#define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */\n#define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */\n#define LCD_FCR_SOFIE_Pos           (1U)\n#define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */\n#define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */\n#define LCD_FCR_UDDIE_Pos           (3U)\n#define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */\n#define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */\n\n#define LCD_FCR_PON_Pos             (4U)\n#define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */\n#define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Pulse ON Duration) */\n#define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */\n#define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */\n#define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */\n\n#define LCD_FCR_DEAD_Pos            (7U)\n#define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */\n#define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */\n#define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */\n#define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */\n#define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */\n\n#define LCD_FCR_CC_Pos              (10U)\n#define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */\n#define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */\n#define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */\n#define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */\n#define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */\n\n#define LCD_FCR_BLINKF_Pos          (13U)\n#define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */\n#define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */\n#define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */\n#define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */\n#define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */\n\n#define LCD_FCR_BLINK_Pos           (16U)\n#define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */\n#define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */\n#define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */\n#define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */\n\n#define LCD_FCR_DIV_Pos             (18U)\n#define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */\n#define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */\n#define LCD_FCR_PS_Pos              (22U)\n#define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */\n#define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */\n\n/*******************  Bit definition for LCD_SR register  *********************/\n#define LCD_SR_ENS_Pos              (0U)\n#define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */\n#define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */\n#define LCD_SR_SOF_Pos              (1U)\n#define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */\n#define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */\n#define LCD_SR_UDR_Pos              (2U)\n#define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */\n#define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */\n#define LCD_SR_UDD_Pos              (3U)\n#define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */\n#define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */\n#define LCD_SR_RDY_Pos              (4U)\n#define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */\n#define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */\n#define LCD_SR_FCRSR_Pos            (5U)\n#define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */\n#define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */\n\n/*******************  Bit definition for LCD_CLR register  ********************/\n#define LCD_CLR_SOFC_Pos            (1U)\n#define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */\n#define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */\n#define LCD_CLR_UDDC_Pos            (3U)\n#define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */\n#define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */\n\n/*******************  Bit definition for LCD_RAM register  ********************/\n#define LCD_RAM_SEGMENT_DATA_Pos    (0U)\n#define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */\n#define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */\n\n/******************************************************************************/\n/*                                                                            */\n/*                           SDMMC Interface                                  */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDMMC_POWER register  ******************/\n#define SDMMC_POWER_PWRCTRL_Pos         (0U)\n#define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */\n#define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */\n#define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */\n\n/******************  Bit definition for SDMMC_CLKCR register  ******************/\n#define SDMMC_CLKCR_CLKDIV_Pos          (0U)\n#define SDMMC_CLKCR_CLKDIV_Msk          (0xFFU << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */\n#define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */\n#define SDMMC_CLKCR_CLKEN_Pos           (8U)\n#define SDMMC_CLKCR_CLKEN_Msk           (0x1U << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */\n#define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */\n#define SDMMC_CLKCR_PWRSAV_Pos          (9U)\n#define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */\n#define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */\n#define SDMMC_CLKCR_BYPASS_Pos          (10U)\n#define SDMMC_CLKCR_BYPASS_Msk          (0x1U << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */\n#define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */\n\n#define SDMMC_CLKCR_WIDBUS_Pos          (11U)\n#define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */\n#define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00000800 */\n#define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001000 */\n\n#define SDMMC_CLKCR_NEGEDGE_Pos         (13U)\n#define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */\n#define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */\n#define SDMMC_CLKCR_HWFC_EN_Pos         (14U)\n#define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */\n#define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDMMC_ARG register  *******************/\n#define SDMMC_ARG_CMDARG_Pos            (0U)\n#define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */\n#define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */\n\n/*******************  Bit definition for SDMMC_CMD register  *******************/\n#define SDMMC_CMD_CMDINDEX_Pos          (0U)\n#define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */\n#define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */\n\n#define SDMMC_CMD_WAITRESP_Pos          (6U)\n#define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */\n#define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000040 */\n#define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000080 */\n\n#define SDMMC_CMD_WAITINT_Pos           (8U)\n#define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */\n#define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */\n#define SDMMC_CMD_WAITPEND_Pos          (9U)\n#define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */\n#define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDMMC_CMD_CPSMEN_Pos            (10U)\n#define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */\n#define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)\n#define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */\n#define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */\n\n/*****************  Bit definition for SDMMC_RESPCMD register  *****************/\n#define SDMMC_RESPCMD_RESPCMD_Pos       (0U)\n#define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */\n#define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */\n\n/******************  Bit definition for SDMMC_RESP1 register  ******************/\n#define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)\n#define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */\n\n/******************  Bit definition for SDMMC_RESP2 register  ******************/\n#define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)\n#define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */\n\n/******************  Bit definition for SDMMC_RESP3 register  ******************/\n#define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)\n#define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */\n\n/******************  Bit definition for SDMMC_RESP4 register  ******************/\n#define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)\n#define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */\n\n/******************  Bit definition for SDMMC_DTIMER register  *****************/\n#define SDMMC_DTIMER_DATATIME_Pos       (0U)\n#define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */\n\n/******************  Bit definition for SDMMC_DLEN register  *******************/\n#define SDMMC_DLEN_DATALENGTH_Pos       (0U)\n#define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */\n\n/******************  Bit definition for SDMMC_DCTRL register  ******************/\n#define SDMMC_DCTRL_DTEN_Pos            (0U)\n#define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */\n#define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */\n#define SDMMC_DCTRL_DTDIR_Pos           (1U)\n#define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */\n#define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */\n#define SDMMC_DCTRL_DTMODE_Pos          (2U)\n#define SDMMC_DCTRL_DTMODE_Msk          (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */\n#define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */\n#define SDMMC_DCTRL_DMAEN_Pos           (3U)\n#define SDMMC_DCTRL_DMAEN_Msk           (0x1U << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */\n#define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */\n\n#define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)\n#define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */\n#define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */\n#define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */\n#define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */\n#define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */\n\n#define SDMMC_DCTRL_RWSTART_Pos         (8U)\n#define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */\n#define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */\n#define SDMMC_DCTRL_RWSTOP_Pos          (9U)\n#define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */\n#define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */\n#define SDMMC_DCTRL_RWMOD_Pos           (10U)\n#define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */\n#define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */\n#define SDMMC_DCTRL_SDIOEN_Pos          (11U)\n#define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */\n#define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDMMC_DCOUNT register  *****************/\n#define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)\n#define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */\n\n/******************  Bit definition for SDMMC_STA register  ********************/\n#define SDMMC_STA_CCRCFAIL_Pos          (0U)\n#define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */\n#define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */\n#define SDMMC_STA_DCRCFAIL_Pos          (1U)\n#define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */\n#define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */\n#define SDMMC_STA_CTIMEOUT_Pos          (2U)\n#define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */\n#define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */\n#define SDMMC_STA_DTIMEOUT_Pos          (3U)\n#define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */\n#define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */\n#define SDMMC_STA_TXUNDERR_Pos          (4U)\n#define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */\n#define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */\n#define SDMMC_STA_RXOVERR_Pos           (5U)\n#define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */\n#define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */\n#define SDMMC_STA_CMDREND_Pos           (6U)\n#define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */\n#define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */\n#define SDMMC_STA_CMDSENT_Pos           (7U)\n#define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */\n#define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */\n#define SDMMC_STA_DATAEND_Pos           (8U)\n#define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */\n#define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDMMC_STA_STBITERR_Pos          (9U)\n#define SDMMC_STA_STBITERR_Msk          (0x1U << SDMMC_STA_STBITERR_Pos)       /*!< 0x00000200 */\n#define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */\n#define SDMMC_STA_DBCKEND_Pos           (10U)\n#define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */\n#define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */\n#define SDMMC_STA_CMDACT_Pos            (11U)\n#define SDMMC_STA_CMDACT_Msk            (0x1U << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */\n#define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */\n#define SDMMC_STA_TXACT_Pos             (12U)\n#define SDMMC_STA_TXACT_Msk             (0x1U << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */\n#define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */\n#define SDMMC_STA_RXACT_Pos             (13U)\n#define SDMMC_STA_RXACT_Msk             (0x1U << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */\n#define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */\n#define SDMMC_STA_TXFIFOHE_Pos          (14U)\n#define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */\n#define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDMMC_STA_RXFIFOHF_Pos          (15U)\n#define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */\n#define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDMMC_STA_TXFIFOF_Pos           (16U)\n#define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */\n#define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */\n#define SDMMC_STA_RXFIFOF_Pos           (17U)\n#define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */\n#define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */\n#define SDMMC_STA_TXFIFOE_Pos           (18U)\n#define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */\n#define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */\n#define SDMMC_STA_RXFIFOE_Pos           (19U)\n#define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */\n#define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */\n#define SDMMC_STA_TXDAVL_Pos            (20U)\n#define SDMMC_STA_TXDAVL_Msk            (0x1U << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */\n#define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */\n#define SDMMC_STA_RXDAVL_Pos            (21U)\n#define SDMMC_STA_RXDAVL_Msk            (0x1U << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */\n#define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */\n#define SDMMC_STA_SDIOIT_Pos            (22U)\n#define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */\n#define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */\n\n/*******************  Bit definition for SDMMC_ICR register  *******************/\n#define SDMMC_ICR_CCRCFAILC_Pos         (0U)\n#define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */\n#define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */\n#define SDMMC_ICR_DCRCFAILC_Pos         (1U)\n#define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */\n#define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */\n#define SDMMC_ICR_CTIMEOUTC_Pos         (2U)\n#define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */\n#define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */\n#define SDMMC_ICR_DTIMEOUTC_Pos         (3U)\n#define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */\n#define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */\n#define SDMMC_ICR_TXUNDERRC_Pos         (4U)\n#define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */\n#define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */\n#define SDMMC_ICR_RXOVERRC_Pos          (5U)\n#define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */\n#define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */\n#define SDMMC_ICR_CMDRENDC_Pos          (6U)\n#define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */\n#define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */\n#define SDMMC_ICR_CMDSENTC_Pos          (7U)\n#define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */\n#define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */\n#define SDMMC_ICR_DATAENDC_Pos          (8U)\n#define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */\n#define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */\n#define SDMMC_ICR_STBITERRC_Pos         (9U)\n#define SDMMC_ICR_STBITERRC_Msk         (0x1U << SDMMC_ICR_STBITERRC_Pos)      /*!< 0x00000200 */\n#define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */\n#define SDMMC_ICR_DBCKENDC_Pos          (10U)\n#define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */\n#define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */\n#define SDMMC_ICR_SDIOITC_Pos           (22U)\n#define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */\n#define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */\n\n/******************  Bit definition for SDMMC_MASK register  *******************/\n#define SDMMC_MASK_CCRCFAILIE_Pos       (0U)\n#define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */\n#define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */\n#define SDMMC_MASK_DCRCFAILIE_Pos       (1U)\n#define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */\n#define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */\n#define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)\n#define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */\n#define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */\n#define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)\n#define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */\n#define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */\n#define SDMMC_MASK_TXUNDERRIE_Pos       (4U)\n#define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */\n#define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDMMC_MASK_RXOVERRIE_Pos        (5U)\n#define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */\n#define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDMMC_MASK_CMDRENDIE_Pos        (6U)\n#define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */\n#define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */\n#define SDMMC_MASK_CMDSENTIE_Pos        (7U)\n#define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */\n#define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */\n#define SDMMC_MASK_DATAENDIE_Pos        (8U)\n#define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */\n#define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */\n#define SDMMC_MASK_DBCKENDIE_Pos        (10U)\n#define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */\n#define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */\n#define SDMMC_MASK_CMDACTIE_Pos         (11U)\n#define SDMMC_MASK_CMDACTIE_Msk         (0x1U << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */\n#define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */\n#define SDMMC_MASK_TXACTIE_Pos          (12U)\n#define SDMMC_MASK_TXACTIE_Msk          (0x1U << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */\n#define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */\n#define SDMMC_MASK_RXACTIE_Pos          (13U)\n#define SDMMC_MASK_RXACTIE_Msk          (0x1U << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */\n#define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */\n#define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)\n#define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */\n#define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)\n#define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */\n#define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDMMC_MASK_TXFIFOFIE_Pos        (16U)\n#define SDMMC_MASK_TXFIFOFIE_Msk        (0x1U << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */\n#define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */\n#define SDMMC_MASK_RXFIFOFIE_Pos        (17U)\n#define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */\n#define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */\n#define SDMMC_MASK_TXFIFOEIE_Pos        (18U)\n#define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */\n#define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */\n#define SDMMC_MASK_RXFIFOEIE_Pos        (19U)\n#define SDMMC_MASK_RXFIFOEIE_Msk        (0x1U << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */\n#define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */\n#define SDMMC_MASK_TXDAVLIE_Pos         (20U)\n#define SDMMC_MASK_TXDAVLIE_Msk         (0x1U << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */\n#define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */\n#define SDMMC_MASK_RXDAVLIE_Pos         (21U)\n#define SDMMC_MASK_RXDAVLIE_Msk         (0x1U << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */\n#define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */\n#define SDMMC_MASK_SDIOITIE_Pos         (22U)\n#define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */\n#define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */\n\n/*****************  Bit definition for SDMMC_FIFOCNT register  *****************/\n#define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)\n#define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDMMC_FIFO register  *******************/\n#define SDMMC_FIFO_FIFODATA_Pos         (0U)\n#define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface (SPI)                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos         (0U)\n#define SPI_CR1_CPHA_Msk         (0x1U << SPI_CR1_CPHA_Pos)                    /*!< 0x00000001 */\n#define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos         (1U)\n#define SPI_CR1_CPOL_Msk         (0x1U << SPI_CR1_CPOL_Pos)                    /*!< 0x00000002 */\n#define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos         (2U)\n#define SPI_CR1_MSTR_Msk         (0x1U << SPI_CR1_MSTR_Pos)                    /*!< 0x00000004 */\n#define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos           (3U)\n#define SPI_CR1_BR_Msk           (0x7U << SPI_CR1_BR_Pos)                      /*!< 0x00000038 */\n#define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0             (0x1U << SPI_CR1_BR_Pos)                      /*!< 0x00000008 */\n#define SPI_CR1_BR_1             (0x2U << SPI_CR1_BR_Pos)                      /*!< 0x00000010 */\n#define SPI_CR1_BR_2             (0x4U << SPI_CR1_BR_Pos)                      /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos          (6U)\n#define SPI_CR1_SPE_Msk          (0x1U << SPI_CR1_SPE_Pos)                     /*!< 0x00000040 */\n#define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos     (7U)\n#define SPI_CR1_LSBFIRST_Msk     (0x1U << SPI_CR1_LSBFIRST_Pos)                /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos          (8U)\n#define SPI_CR1_SSI_Msk          (0x1U << SPI_CR1_SSI_Pos)                     /*!< 0x00000100 */\n#define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos          (9U)\n#define SPI_CR1_SSM_Msk          (0x1U << SPI_CR1_SSM_Pos)                     /*!< 0x00000200 */\n#define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos       (10U)\n#define SPI_CR1_RXONLY_Msk       (0x1U << SPI_CR1_RXONLY_Pos)                  /*!< 0x00000400 */\n#define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */\n#define SPI_CR1_CRCL_Pos         (11U)\n#define SPI_CR1_CRCL_Msk         (0x1U << SPI_CR1_CRCL_Pos)                    /*!< 0x00000800 */\n#define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */\n#define SPI_CR1_CRCNEXT_Pos      (12U)\n#define SPI_CR1_CRCNEXT_Msk      (0x1U << SPI_CR1_CRCNEXT_Pos)                 /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos        (13U)\n#define SPI_CR1_CRCEN_Msk        (0x1U << SPI_CR1_CRCEN_Pos)                   /*!< 0x00002000 */\n#define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos       (14U)\n#define SPI_CR1_BIDIOE_Msk       (0x1U << SPI_CR1_BIDIOE_Pos)                  /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos     (15U)\n#define SPI_CR1_BIDIMODE_Msk     (0x1U << SPI_CR1_BIDIMODE_Pos)                /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos      (0U)\n#define SPI_CR2_RXDMAEN_Msk      (0x1U << SPI_CR2_RXDMAEN_Pos)                 /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */\n#define SPI_CR2_TXDMAEN_Pos      (1U)\n#define SPI_CR2_TXDMAEN_Msk      (0x1U << SPI_CR2_TXDMAEN_Pos)                 /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */\n#define SPI_CR2_SSOE_Pos         (2U)\n#define SPI_CR2_SSOE_Msk         (0x1U << SPI_CR2_SSOE_Pos)                    /*!< 0x00000004 */\n#define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */\n#define SPI_CR2_NSSP_Pos         (3U)\n#define SPI_CR2_NSSP_Msk         (0x1U << SPI_CR2_NSSP_Pos)                    /*!< 0x00000008 */\n#define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */\n#define SPI_CR2_FRF_Pos          (4U)\n#define SPI_CR2_FRF_Msk          (0x1U << SPI_CR2_FRF_Pos)                     /*!< 0x00000010 */\n#define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */\n#define SPI_CR2_ERRIE_Pos        (5U)\n#define SPI_CR2_ERRIE_Msk        (0x1U << SPI_CR2_ERRIE_Pos)                   /*!< 0x00000020 */\n#define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */\n#define SPI_CR2_RXNEIE_Pos       (6U)\n#define SPI_CR2_RXNEIE_Msk       (0x1U << SPI_CR2_RXNEIE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos        (7U)\n#define SPI_CR2_TXEIE_Msk        (0x1U << SPI_CR2_TXEIE_Pos)                   /*!< 0x00000080 */\n#define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */\n#define SPI_CR2_DS_Pos           (8U)\n#define SPI_CR2_DS_Msk           (0xFU << SPI_CR2_DS_Pos)                      /*!< 0x00000F00 */\n#define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */\n#define SPI_CR2_DS_0             (0x1U << SPI_CR2_DS_Pos)                      /*!< 0x00000100 */\n#define SPI_CR2_DS_1             (0x2U << SPI_CR2_DS_Pos)                      /*!< 0x00000200 */\n#define SPI_CR2_DS_2             (0x4U << SPI_CR2_DS_Pos)                      /*!< 0x00000400 */\n#define SPI_CR2_DS_3             (0x8U << SPI_CR2_DS_Pos)                      /*!< 0x00000800 */\n#define SPI_CR2_FRXTH_Pos        (12U)\n#define SPI_CR2_FRXTH_Msk        (0x1U << SPI_CR2_FRXTH_Pos)                   /*!< 0x00001000 */\n#define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */\n#define SPI_CR2_LDMARX_Pos       (13U)\n#define SPI_CR2_LDMARX_Msk       (0x1U << SPI_CR2_LDMARX_Pos)                  /*!< 0x00002000 */\n#define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */\n#define SPI_CR2_LDMATX_Pos       (14U)\n#define SPI_CR2_LDMATX_Msk       (0x1U << SPI_CR2_LDMATX_Pos)                  /*!< 0x00004000 */\n#define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos          (0U)\n#define SPI_SR_RXNE_Msk          (0x1U << SPI_SR_RXNE_Pos)                     /*!< 0x00000001 */\n#define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos           (1U)\n#define SPI_SR_TXE_Msk           (0x1U << SPI_SR_TXE_Pos)                      /*!< 0x00000002 */\n#define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */\n#define SPI_SR_CHSIDE_Pos        (2U)\n#define SPI_SR_CHSIDE_Msk        (0x1U << SPI_SR_CHSIDE_Pos)                   /*!< 0x00000004 */\n#define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */\n#define SPI_SR_UDR_Pos           (3U)\n#define SPI_SR_UDR_Msk           (0x1U << SPI_SR_UDR_Pos)                      /*!< 0x00000008 */\n#define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */\n#define SPI_SR_CRCERR_Pos        (4U)\n#define SPI_SR_CRCERR_Msk        (0x1U << SPI_SR_CRCERR_Pos)                   /*!< 0x00000010 */\n#define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */\n#define SPI_SR_MODF_Pos          (5U)\n#define SPI_SR_MODF_Msk          (0x1U << SPI_SR_MODF_Pos)                     /*!< 0x00000020 */\n#define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */\n#define SPI_SR_OVR_Pos           (6U)\n#define SPI_SR_OVR_Msk           (0x1U << SPI_SR_OVR_Pos)                      /*!< 0x00000040 */\n#define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */\n#define SPI_SR_BSY_Pos           (7U)\n#define SPI_SR_BSY_Msk           (0x1U << SPI_SR_BSY_Pos)                      /*!< 0x00000080 */\n#define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */\n#define SPI_SR_FRE_Pos           (8U)\n#define SPI_SR_FRE_Msk           (0x1U << SPI_SR_FRE_Pos)                      /*!< 0x00000100 */\n#define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */\n#define SPI_SR_FRLVL_Pos         (9U)\n#define SPI_SR_FRLVL_Msk         (0x3U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000600 */\n#define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */\n#define SPI_SR_FRLVL_0           (0x1U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000200 */\n#define SPI_SR_FRLVL_1           (0x2U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000400 */\n#define SPI_SR_FTLVL_Pos         (11U)\n#define SPI_SR_FTLVL_Msk         (0x3U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001800 */\n#define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */\n#define SPI_SR_FTLVL_0           (0x1U << SPI_SR_FTLVL_Pos)                    /*!< 0x00000800 */\n#define SPI_SR_FTLVL_1           (0x2U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001000 */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos            (0U)\n#define SPI_DR_DR_Msk            (0xFFFFU << SPI_DR_DR_Pos)                    /*!< 0x0000FFFF */\n#define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos    (0U)\n#define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)            /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos     (0U)\n#define SPI_RXCRCR_RXCRC_Msk     (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)             /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos     (0U)\n#define SPI_TXCRCR_TXCRC_Msk     (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)             /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    QUADSPI                                 */\n/*                                                                            */\n/******************************************************************************/\n/*****************  Bit definition for QUADSPI_CR register  *******************/\n#define QUADSPI_CR_EN_Pos              (0U)\n#define QUADSPI_CR_EN_Msk              (0x1U << QUADSPI_CR_EN_Pos)             /*!< 0x00000001 */\n#define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */\n#define QUADSPI_CR_ABORT_Pos           (1U)\n#define QUADSPI_CR_ABORT_Msk           (0x1U << QUADSPI_CR_ABORT_Pos)          /*!< 0x00000002 */\n#define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */\n#define QUADSPI_CR_DMAEN_Pos           (2U)\n#define QUADSPI_CR_DMAEN_Msk           (0x1U << QUADSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */\n#define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */\n#define QUADSPI_CR_TCEN_Pos            (3U)\n#define QUADSPI_CR_TCEN_Msk            (0x1U << QUADSPI_CR_TCEN_Pos)           /*!< 0x00000008 */\n#define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */\n#define QUADSPI_CR_SSHIFT_Pos          (4U)\n#define QUADSPI_CR_SSHIFT_Msk          (0x1U << QUADSPI_CR_SSHIFT_Pos)         /*!< 0x00000010 */\n#define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */\n#define QUADSPI_CR_DFM_Pos             (6U)\n#define QUADSPI_CR_DFM_Msk             (0x1U << QUADSPI_CR_DFM_Pos)            /*!< 0x00000040 */\n#define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */\n#define QUADSPI_CR_FSEL_Pos            (7U)\n#define QUADSPI_CR_FSEL_Msk            (0x1U << QUADSPI_CR_FSEL_Pos)           /*!< 0x00000080 */\n#define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */\n#define QUADSPI_CR_FTHRES_Pos          (8U)\n#define QUADSPI_CR_FTHRES_Msk          (0xFU << QUADSPI_CR_FTHRES_Pos)         /*!< 0x00000F00 */\n#define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */\n#define QUADSPI_CR_TEIE_Pos            (16U)\n#define QUADSPI_CR_TEIE_Msk            (0x1U << QUADSPI_CR_TEIE_Pos)           /*!< 0x00010000 */\n#define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */\n#define QUADSPI_CR_TCIE_Pos            (17U)\n#define QUADSPI_CR_TCIE_Msk            (0x1U << QUADSPI_CR_TCIE_Pos)           /*!< 0x00020000 */\n#define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */\n#define QUADSPI_CR_FTIE_Pos            (18U)\n#define QUADSPI_CR_FTIE_Msk            (0x1U << QUADSPI_CR_FTIE_Pos)           /*!< 0x00040000 */\n#define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */\n#define QUADSPI_CR_SMIE_Pos            (19U)\n#define QUADSPI_CR_SMIE_Msk            (0x1U << QUADSPI_CR_SMIE_Pos)           /*!< 0x00080000 */\n#define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */\n#define QUADSPI_CR_TOIE_Pos            (20U)\n#define QUADSPI_CR_TOIE_Msk            (0x1U << QUADSPI_CR_TOIE_Pos)           /*!< 0x00100000 */\n#define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */\n#define QUADSPI_CR_APMS_Pos            (22U)\n#define QUADSPI_CR_APMS_Msk            (0x1U << QUADSPI_CR_APMS_Pos)           /*!< 0x00400000 */\n#define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */\n#define QUADSPI_CR_PMM_Pos             (23U)\n#define QUADSPI_CR_PMM_Msk             (0x1U << QUADSPI_CR_PMM_Pos)            /*!< 0x00800000 */\n#define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */\n#define QUADSPI_CR_PRESCALER_Pos       (24U)\n#define QUADSPI_CR_PRESCALER_Msk       (0xFFU << QUADSPI_CR_PRESCALER_Pos)     /*!< 0xFF000000 */\n#define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */\n\n/*****************  Bit definition for QUADSPI_DCR register  ******************/\n#define QUADSPI_DCR_CKMODE_Pos         (0U)\n#define QUADSPI_DCR_CKMODE_Msk         (0x1U << QUADSPI_DCR_CKMODE_Pos)        /*!< 0x00000001 */\n#define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */\n#define QUADSPI_DCR_CSHT_Pos           (8U)\n#define QUADSPI_DCR_CSHT_Msk           (0x7U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000700 */\n#define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */\n#define QUADSPI_DCR_CSHT_0             (0x1U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000100 */\n#define QUADSPI_DCR_CSHT_1             (0x2U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000200 */\n#define QUADSPI_DCR_CSHT_2             (0x4U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000400 */\n#define QUADSPI_DCR_FSIZE_Pos          (16U)\n#define QUADSPI_DCR_FSIZE_Msk          (0x1FU << QUADSPI_DCR_FSIZE_Pos)        /*!< 0x001F0000 */\n#define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */\n\n/******************  Bit definition for QUADSPI_SR register  *******************/\n#define QUADSPI_SR_TEF_Pos             (0U)\n#define QUADSPI_SR_TEF_Msk             (0x1U << QUADSPI_SR_TEF_Pos)            /*!< 0x00000001 */\n#define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */\n#define QUADSPI_SR_TCF_Pos             (1U)\n#define QUADSPI_SR_TCF_Msk             (0x1U << QUADSPI_SR_TCF_Pos)            /*!< 0x00000002 */\n#define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */\n#define QUADSPI_SR_FTF_Pos             (2U)\n#define QUADSPI_SR_FTF_Msk             (0x1U << QUADSPI_SR_FTF_Pos)            /*!< 0x00000004 */\n#define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */\n#define QUADSPI_SR_SMF_Pos             (3U)\n#define QUADSPI_SR_SMF_Msk             (0x1U << QUADSPI_SR_SMF_Pos)            /*!< 0x00000008 */\n#define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */\n#define QUADSPI_SR_TOF_Pos             (4U)\n#define QUADSPI_SR_TOF_Msk             (0x1U << QUADSPI_SR_TOF_Pos)            /*!< 0x00000010 */\n#define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */\n#define QUADSPI_SR_BUSY_Pos            (5U)\n#define QUADSPI_SR_BUSY_Msk            (0x1U << QUADSPI_SR_BUSY_Pos)           /*!< 0x00000020 */\n#define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */\n#define QUADSPI_SR_FLEVEL_Pos          (8U)\n#define QUADSPI_SR_FLEVEL_Msk          (0x1FU << QUADSPI_SR_FLEVEL_Pos)        /*!< 0x00001F00 */\n#define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */\n\n/******************  Bit definition for QUADSPI_FCR register  ******************/\n#define QUADSPI_FCR_CTEF_Pos           (0U)\n#define QUADSPI_FCR_CTEF_Msk           (0x1U << QUADSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */\n#define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */\n#define QUADSPI_FCR_CTCF_Pos           (1U)\n#define QUADSPI_FCR_CTCF_Msk           (0x1U << QUADSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */\n#define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */\n#define QUADSPI_FCR_CSMF_Pos           (3U)\n#define QUADSPI_FCR_CSMF_Msk           (0x1U << QUADSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */\n#define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */\n#define QUADSPI_FCR_CTOF_Pos           (4U)\n#define QUADSPI_FCR_CTOF_Msk           (0x1U << QUADSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */\n#define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */\n\n/******************  Bit definition for QUADSPI_DLR register  ******************/\n#define QUADSPI_DLR_DL_Pos             (0U)\n#define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */\n#define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */\n\n/******************  Bit definition for QUADSPI_CCR register  ******************/\n#define QUADSPI_CCR_INSTRUCTION_Pos    (0U)\n#define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)  /*!< 0x000000FF */\n#define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */\n#define QUADSPI_CCR_IMODE_Pos          (8U)\n#define QUADSPI_CCR_IMODE_Msk          (0x3U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000300 */\n#define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */\n#define QUADSPI_CCR_IMODE_0            (0x1U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000100 */\n#define QUADSPI_CCR_IMODE_1            (0x2U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000200 */\n#define QUADSPI_CCR_ADMODE_Pos         (10U)\n#define QUADSPI_CCR_ADMODE_Msk         (0x3U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000C00 */\n#define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */\n#define QUADSPI_CCR_ADMODE_0           (0x1U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */\n#define QUADSPI_CCR_ADMODE_1           (0x2U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000800 */\n#define QUADSPI_CCR_ADSIZE_Pos         (12U)\n#define QUADSPI_CCR_ADSIZE_Msk         (0x3U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */\n#define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */\n#define QUADSPI_CCR_ADSIZE_0           (0x1U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */\n#define QUADSPI_CCR_ADSIZE_1           (0x2U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */\n#define QUADSPI_CCR_ABMODE_Pos         (14U)\n#define QUADSPI_CCR_ABMODE_Msk         (0x3U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x0000C000 */\n#define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */\n#define QUADSPI_CCR_ABMODE_0           (0x1U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00004000 */\n#define QUADSPI_CCR_ABMODE_1           (0x2U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00008000 */\n#define QUADSPI_CCR_ABSIZE_Pos         (16U)\n#define QUADSPI_CCR_ABSIZE_Msk         (0x3U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00030000 */\n#define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */\n#define QUADSPI_CCR_ABSIZE_0           (0x1U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00010000 */\n#define QUADSPI_CCR_ABSIZE_1           (0x2U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00020000 */\n#define QUADSPI_CCR_DCYC_Pos           (18U)\n#define QUADSPI_CCR_DCYC_Msk           (0x1FU << QUADSPI_CCR_DCYC_Pos)         /*!< 0x007C0000 */\n#define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */\n#define QUADSPI_CCR_DMODE_Pos          (24U)\n#define QUADSPI_CCR_DMODE_Msk          (0x3U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x03000000 */\n#define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */\n#define QUADSPI_CCR_DMODE_0            (0x1U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */\n#define QUADSPI_CCR_DMODE_1            (0x2U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */\n#define QUADSPI_CCR_FMODE_Pos          (26U)\n#define QUADSPI_CCR_FMODE_Msk          (0x3U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x0C000000 */\n#define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */\n#define QUADSPI_CCR_FMODE_0            (0x1U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x04000000 */\n#define QUADSPI_CCR_FMODE_1            (0x2U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x08000000 */\n#define QUADSPI_CCR_SIOO_Pos           (28U)\n#define QUADSPI_CCR_SIOO_Msk           (0x1U << QUADSPI_CCR_SIOO_Pos)          /*!< 0x10000000 */\n#define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */\n#define QUADSPI_CCR_DHHC_Pos           (30U)\n#define QUADSPI_CCR_DHHC_Msk           (0x1U << QUADSPI_CCR_DHHC_Pos)          /*!< 0x40000000 */\n#define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */\n#define QUADSPI_CCR_DDRM_Pos           (31U)\n#define QUADSPI_CCR_DDRM_Msk           (0x1U << QUADSPI_CCR_DDRM_Pos)          /*!< 0x80000000 */\n#define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */\n\n/******************  Bit definition for QUADSPI_AR register  *******************/\n#define QUADSPI_AR_ADDRESS_Pos         (0U)\n#define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */\n\n/******************  Bit definition for QUADSPI_ABR register  ******************/\n#define QUADSPI_ABR_ALTERNATE_Pos      (0U)\n#define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */\n\n/******************  Bit definition for QUADSPI_DR register  *******************/\n#define QUADSPI_DR_DATA_Pos            (0U)\n#define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */\n#define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */\n\n/******************  Bit definition for QUADSPI_PSMKR register  ****************/\n#define QUADSPI_PSMKR_MASK_Pos         (0U)\n#define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */\n\n/******************  Bit definition for QUADSPI_PSMAR register  ****************/\n#define QUADSPI_PSMAR_MATCH_Pos        (0U)\n#define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\n#define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */\n\n/******************  Bit definition for QUADSPI_PIR register  *****************/\n#define QUADSPI_PIR_INTERVAL_Pos       (0U)\n#define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */\n#define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */\n\n/******************  Bit definition for QUADSPI_LPTR register  *****************/\n#define QUADSPI_LPTR_TIMEOUT_Pos       (0U)\n#define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */\n#define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)\n#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000007 */\n#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */\n#define SYSCFG_MEMRMP_MEM_MODE_2        (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000004 */\n\n#define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)\n#define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos)    /*!< 0x00000100 */\n#define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< Flash Bank mode selection */\n\n/******************  Bit definition for SYSCFG_CFGR1 register  ******************/\n#define SYSCFG_CFGR1_FWDIS_Pos          (0U)\n#define SYSCFG_CFGR1_FWDIS_Msk          (0x1U << SYSCFG_CFGR1_FWDIS_Pos)       /*!< 0x00000001 */\n#define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/\n#define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)\n#define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */\n#define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */\n#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)\n#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */\n#define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */\n#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)\n#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */\n#define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */\n#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)\n#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */\n#define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */\n#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)\n#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */\n#define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */\n#define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)\n#define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos)    /*!< 0x00100000 */\n#define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */\n#define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)\n#define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos)    /*!< 0x00200000 */\n#define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */\n#define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)\n#define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos)    /*!< 0x00400000 */\n#define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */\n#define SYSCFG_CFGR1_I2C4_FMP_Pos       (23U)\n#define SYSCFG_CFGR1_I2C4_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C4_FMP_Pos)    /*!< 0x00800000 */\n#define SYSCFG_CFGR1_I2C4_FMP           SYSCFG_CFGR1_I2C4_FMP_Msk              /*!< I2C4 Fast mode plus */\n#define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */\n#define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */\n#define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */\n#define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */\n#define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */\n#define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */\n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)\n#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFU << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)\n#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFU << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)\n#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFU << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)\n#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFU << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */\n\n/**\n  * @brief   EXTI0 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI             (0x00000008U)                      /*!<PI[0] pin */\n\n/**\n  * @brief   EXTI1 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI             (0x00000080U)                      /*!<PI[1] pin */\n\n/**\n  * @brief   EXTI2 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH             (0x00000700U)                      /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI             (0x00000800U)                      /*!<PI[2] pin */\n\n/**\n  * @brief   EXTI3 configuration\n  */\n#define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH             (0x00007000U)                      /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI             (0x00008000U)                      /*!<PI[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)\n#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFU << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)\n#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFU << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)\n#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFU << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)\n#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFU << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */\n/**\n  * @brief   EXTI4 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH             (0x00000007U)                      /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI             (0x00000008U)                      /*!<PI[4] pin */\n\n/**\n  * @brief   EXTI5 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH             (0x00000070U)                      /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI             (0x00000080U)                      /*!<PI[5] pin */\n\n/**\n  * @brief   EXTI6 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH             (0x00000700U)                      /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI             (0x00000800U)                      /*!<PI[6] pin */\n\n/**\n  * @brief   EXTI7 configuration\n  */\n#define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH             (0x00007000U)                      /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI             (0x00008000U)                      /*!<PI[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)\n#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFU << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)\n#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFU << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)\n#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFU << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)\n#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFU << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH             (0x00000007U)                      /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI             (0x00000008U)                      /*!<PI[8] pin */\n\n/**\n  * @brief   EXTI9 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH             (0x00000070U)                      /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI             (0x00000080U)                      /*!<PI[9] pin */\n\n/**\n  * @brief   EXTI10 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600U)                      /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH            (0x00000700U)                      /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI            (0x00000800U)                      /*!<PI[10] pin */\n\n/**\n  * @brief   EXTI11 configuration\n  */\n#define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000U)                      /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH            (0x00007000U)                      /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI            (0x00008000U)                      /*!<PI[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)\n#define SYSCFG_EXTICR4_EXTI12_Msk       (0x7U << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x00000007 */\n#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)\n#define SYSCFG_EXTICR4_EXTI13_Msk       (0x7U << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x00000070 */\n#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)\n#define SYSCFG_EXTICR4_EXTI14_Msk       (0x7U << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000700 */\n#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)\n#define SYSCFG_EXTICR4_EXTI15_Msk       (0x7U << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x00007000 */\n#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006U)                      /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH            (0x00000007U)                      /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060U)                      /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH            (0x00000070U)                      /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600U)                      /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH            (0x00000700U)                      /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration\n  */\n#define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000U)                      /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH            (0x00007000U)                      /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_SCSR register  ****************/\n#define SYSCFG_SCSR_SRAM2ER_Pos         (0U)\n#define SYSCFG_SCSR_SRAM2ER_Msk         (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)      /*!< 0x00000001 */\n#define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */\n#define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)\n#define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos)     /*!< 0x00000002 */\n#define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */\n\n/******************  Bit definition for SYSCFG_CFGR2 register  ****************/\n#define SYSCFG_CFGR2_CLL_Pos            (0U)\n#define SYSCFG_CFGR2_CLL_Msk            (0x1U << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */\n#define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */\n#define SYSCFG_CFGR2_SPL_Pos            (1U)\n#define SYSCFG_CFGR2_SPL_Msk            (0x1U << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */\n#define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/\n#define SYSCFG_CFGR2_PVDL_Pos           (2U)\n#define SYSCFG_CFGR2_PVDL_Msk           (0x1U << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */\n#define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */\n#define SYSCFG_CFGR2_ECCL_Pos           (3U)\n#define SYSCFG_CFGR2_ECCL_Msk           (0x1U << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */\n#define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/\n#define SYSCFG_CFGR2_SPF_Pos            (8U)\n#define SYSCFG_CFGR2_SPF_Msk            (0x1U << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */\n#define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */\n\n/******************  Bit definition for SYSCFG_SWPR register  ****************/\n#define SYSCFG_SWPR_PAGE0_Pos           (0U)\n#define SYSCFG_SWPR_PAGE0_Msk           (0x1U << SYSCFG_SWPR_PAGE0_Pos)        /*!< 0x00000001 */\n#define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */\n#define SYSCFG_SWPR_PAGE1_Pos           (1U)\n#define SYSCFG_SWPR_PAGE1_Msk           (0x1U << SYSCFG_SWPR_PAGE1_Pos)        /*!< 0x00000002 */\n#define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */\n#define SYSCFG_SWPR_PAGE2_Pos           (2U)\n#define SYSCFG_SWPR_PAGE2_Msk           (0x1U << SYSCFG_SWPR_PAGE2_Pos)        /*!< 0x00000004 */\n#define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */\n#define SYSCFG_SWPR_PAGE3_Pos           (3U)\n#define SYSCFG_SWPR_PAGE3_Msk           (0x1U << SYSCFG_SWPR_PAGE3_Pos)        /*!< 0x00000008 */\n#define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */\n#define SYSCFG_SWPR_PAGE4_Pos           (4U)\n#define SYSCFG_SWPR_PAGE4_Msk           (0x1U << SYSCFG_SWPR_PAGE4_Pos)        /*!< 0x00000010 */\n#define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */\n#define SYSCFG_SWPR_PAGE5_Pos           (5U)\n#define SYSCFG_SWPR_PAGE5_Msk           (0x1U << SYSCFG_SWPR_PAGE5_Pos)        /*!< 0x00000020 */\n#define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */\n#define SYSCFG_SWPR_PAGE6_Pos           (6U)\n#define SYSCFG_SWPR_PAGE6_Msk           (0x1U << SYSCFG_SWPR_PAGE6_Pos)        /*!< 0x00000040 */\n#define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */\n#define SYSCFG_SWPR_PAGE7_Pos           (7U)\n#define SYSCFG_SWPR_PAGE7_Msk           (0x1U << SYSCFG_SWPR_PAGE7_Pos)        /*!< 0x00000080 */\n#define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */\n#define SYSCFG_SWPR_PAGE8_Pos           (8U)\n#define SYSCFG_SWPR_PAGE8_Msk           (0x1U << SYSCFG_SWPR_PAGE8_Pos)        /*!< 0x00000100 */\n#define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */\n#define SYSCFG_SWPR_PAGE9_Pos           (9U)\n#define SYSCFG_SWPR_PAGE9_Msk           (0x1U << SYSCFG_SWPR_PAGE9_Pos)        /*!< 0x00000200 */\n#define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */\n#define SYSCFG_SWPR_PAGE10_Pos          (10U)\n#define SYSCFG_SWPR_PAGE10_Msk          (0x1U << SYSCFG_SWPR_PAGE10_Pos)       /*!< 0x00000400 */\n#define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/\n#define SYSCFG_SWPR_PAGE11_Pos          (11U)\n#define SYSCFG_SWPR_PAGE11_Msk          (0x1U << SYSCFG_SWPR_PAGE11_Pos)       /*!< 0x00000800 */\n#define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/\n#define SYSCFG_SWPR_PAGE12_Pos          (12U)\n#define SYSCFG_SWPR_PAGE12_Msk          (0x1U << SYSCFG_SWPR_PAGE12_Pos)       /*!< 0x00001000 */\n#define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/\n#define SYSCFG_SWPR_PAGE13_Pos          (13U)\n#define SYSCFG_SWPR_PAGE13_Msk          (0x1U << SYSCFG_SWPR_PAGE13_Pos)       /*!< 0x00002000 */\n#define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/\n#define SYSCFG_SWPR_PAGE14_Pos          (14U)\n#define SYSCFG_SWPR_PAGE14_Msk          (0x1U << SYSCFG_SWPR_PAGE14_Pos)       /*!< 0x00004000 */\n#define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/\n#define SYSCFG_SWPR_PAGE15_Pos          (15U)\n#define SYSCFG_SWPR_PAGE15_Msk          (0x1U << SYSCFG_SWPR_PAGE15_Pos)       /*!< 0x00008000 */\n#define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/\n#define SYSCFG_SWPR_PAGE16_Pos          (16U)\n#define SYSCFG_SWPR_PAGE16_Msk          (0x1U << SYSCFG_SWPR_PAGE16_Pos)       /*!< 0x00010000 */\n#define SYSCFG_SWPR_PAGE16              SYSCFG_SWPR_PAGE16_Msk                 /*!< SRAM2 Write protection page 16*/\n#define SYSCFG_SWPR_PAGE17_Pos          (17U)\n#define SYSCFG_SWPR_PAGE17_Msk          (0x1U << SYSCFG_SWPR_PAGE17_Pos)       /*!< 0x00020000 */\n#define SYSCFG_SWPR_PAGE17              SYSCFG_SWPR_PAGE17_Msk                 /*!< SRAM2 Write protection page 17*/\n#define SYSCFG_SWPR_PAGE18_Pos          (18U)\n#define SYSCFG_SWPR_PAGE18_Msk          (0x1U << SYSCFG_SWPR_PAGE18_Pos)       /*!< 0x00040000 */\n#define SYSCFG_SWPR_PAGE18              SYSCFG_SWPR_PAGE18_Msk                 /*!< SRAM2 Write protection page 18*/\n#define SYSCFG_SWPR_PAGE19_Pos          (19U)\n#define SYSCFG_SWPR_PAGE19_Msk          (0x1U << SYSCFG_SWPR_PAGE19_Pos)       /*!< 0x00080000 */\n#define SYSCFG_SWPR_PAGE19              SYSCFG_SWPR_PAGE19_Msk                 /*!< SRAM2 Write protection page 19*/\n#define SYSCFG_SWPR_PAGE20_Pos          (20U)\n#define SYSCFG_SWPR_PAGE20_Msk          (0x1U << SYSCFG_SWPR_PAGE20_Pos)       /*!< 0x00100000 */\n#define SYSCFG_SWPR_PAGE20              SYSCFG_SWPR_PAGE20_Msk                 /*!< SRAM2 Write protection page 20*/\n#define SYSCFG_SWPR_PAGE21_Pos          (21U)\n#define SYSCFG_SWPR_PAGE21_Msk          (0x1U << SYSCFG_SWPR_PAGE21_Pos)       /*!< 0x00200000 */\n#define SYSCFG_SWPR_PAGE21              SYSCFG_SWPR_PAGE21_Msk                 /*!< SRAM2 Write protection page 21*/\n#define SYSCFG_SWPR_PAGE22_Pos          (22U)\n#define SYSCFG_SWPR_PAGE22_Msk          (0x1U << SYSCFG_SWPR_PAGE22_Pos)       /*!< 0x00400000 */\n#define SYSCFG_SWPR_PAGE22              SYSCFG_SWPR_PAGE22_Msk                 /*!< SRAM2 Write protection page 22*/\n#define SYSCFG_SWPR_PAGE23_Pos          (23U)\n#define SYSCFG_SWPR_PAGE23_Msk          (0x1U << SYSCFG_SWPR_PAGE23_Pos)       /*!< 0x00800000 */\n#define SYSCFG_SWPR_PAGE23              SYSCFG_SWPR_PAGE23_Msk                 /*!< SRAM2 Write protection page 23*/\n#define SYSCFG_SWPR_PAGE24_Pos          (24U)\n#define SYSCFG_SWPR_PAGE24_Msk          (0x1U << SYSCFG_SWPR_PAGE24_Pos)       /*!< 0x01000000 */\n#define SYSCFG_SWPR_PAGE24              SYSCFG_SWPR_PAGE24_Msk                 /*!< SRAM2 Write protection page 24*/\n#define SYSCFG_SWPR_PAGE25_Pos          (25U)\n#define SYSCFG_SWPR_PAGE25_Msk          (0x1U << SYSCFG_SWPR_PAGE25_Pos)       /*!< 0x02000000 */\n#define SYSCFG_SWPR_PAGE25              SYSCFG_SWPR_PAGE25_Msk                 /*!< SRAM2 Write protection page 25*/\n#define SYSCFG_SWPR_PAGE26_Pos          (26U)\n#define SYSCFG_SWPR_PAGE26_Msk          (0x1U << SYSCFG_SWPR_PAGE26_Pos)       /*!< 0x04000000 */\n#define SYSCFG_SWPR_PAGE26              SYSCFG_SWPR_PAGE26_Msk                 /*!< SRAM2 Write protection page 26*/\n#define SYSCFG_SWPR_PAGE27_Pos          (27U)\n#define SYSCFG_SWPR_PAGE27_Msk          (0x1U << SYSCFG_SWPR_PAGE27_Pos)       /*!< 0x08000000 */\n#define SYSCFG_SWPR_PAGE27              SYSCFG_SWPR_PAGE27_Msk                 /*!< SRAM2 Write protection page 27*/\n#define SYSCFG_SWPR_PAGE28_Pos          (28U)\n#define SYSCFG_SWPR_PAGE28_Msk          (0x1U << SYSCFG_SWPR_PAGE28_Pos)       /*!< 0x10000000 */\n#define SYSCFG_SWPR_PAGE28              SYSCFG_SWPR_PAGE28_Msk                 /*!< SRAM2 Write protection page 28*/\n#define SYSCFG_SWPR_PAGE29_Pos          (29U)\n#define SYSCFG_SWPR_PAGE29_Msk          (0x1U << SYSCFG_SWPR_PAGE29_Pos)       /*!< 0x20000000 */\n#define SYSCFG_SWPR_PAGE29              SYSCFG_SWPR_PAGE29_Msk                 /*!< SRAM2 Write protection page 29*/\n#define SYSCFG_SWPR_PAGE30_Pos          (30U)\n#define SYSCFG_SWPR_PAGE30_Msk          (0x1U << SYSCFG_SWPR_PAGE30_Pos)       /*!< 0x40000000 */\n#define SYSCFG_SWPR_PAGE30              SYSCFG_SWPR_PAGE30_Msk                 /*!< SRAM2 Write protection page 30*/\n#define SYSCFG_SWPR_PAGE31_Pos          (31U)\n#define SYSCFG_SWPR_PAGE31_Msk          (0x1U << SYSCFG_SWPR_PAGE31_Pos)       /*!< 0x80000000 */\n#define SYSCFG_SWPR_PAGE31              SYSCFG_SWPR_PAGE31_Msk                 /*!< SRAM2 Write protection page 31*/\n\n/******************  Bit definition for SYSCFG_SWPR2 register  ***************/\n#define SYSCFG_SWPR2_PAGE32_Pos         (0U)\n#define SYSCFG_SWPR2_PAGE32_Msk         (0x1U << SYSCFG_SWPR2_PAGE32_Pos)      /*!< 0x00000001 */\n#define SYSCFG_SWPR2_PAGE32             SYSCFG_SWPR2_PAGE32_Msk                /*!< SRAM2 Write protection page 32*/\n#define SYSCFG_SWPR2_PAGE33_Pos         (1U)\n#define SYSCFG_SWPR2_PAGE33_Msk         (0x1U << SYSCFG_SWPR2_PAGE33_Pos)      /*!< 0x00000002 */\n#define SYSCFG_SWPR2_PAGE33             SYSCFG_SWPR2_PAGE33_Msk                /*!< SRAM2 Write protection page 33*/\n#define SYSCFG_SWPR2_PAGE34_Pos         (2U)\n#define SYSCFG_SWPR2_PAGE34_Msk         (0x1U << SYSCFG_SWPR2_PAGE34_Pos)      /*!< 0x00000004 */\n#define SYSCFG_SWPR2_PAGE34             SYSCFG_SWPR2_PAGE34_Msk                /*!< SRAM2 Write protection page 34*/\n#define SYSCFG_SWPR2_PAGE35_Pos         (3U)\n#define SYSCFG_SWPR2_PAGE35_Msk         (0x1U << SYSCFG_SWPR2_PAGE35_Pos)      /*!< 0x00000008 */\n#define SYSCFG_SWPR2_PAGE35             SYSCFG_SWPR2_PAGE35_Msk                /*!< SRAM2 Write protection page 35*/\n#define SYSCFG_SWPR2_PAGE36_Pos         (4U)\n#define SYSCFG_SWPR2_PAGE36_Msk         (0x1U << SYSCFG_SWPR2_PAGE36_Pos)      /*!< 0x00000010 */\n#define SYSCFG_SWPR2_PAGE36             SYSCFG_SWPR2_PAGE36_Msk                /*!< SRAM2 Write protection page 36*/\n#define SYSCFG_SWPR2_PAGE37_Pos         (5U)\n#define SYSCFG_SWPR2_PAGE37_Msk         (0x1U << SYSCFG_SWPR2_PAGE37_Pos)      /*!< 0x00000020 */\n#define SYSCFG_SWPR2_PAGE37             SYSCFG_SWPR2_PAGE37_Msk                /*!< SRAM2 Write protection page 37*/\n#define SYSCFG_SWPR2_PAGE38_Pos         (6U)\n#define SYSCFG_SWPR2_PAGE38_Msk         (0x1U << SYSCFG_SWPR2_PAGE38_Pos)      /*!< 0x00000040 */\n#define SYSCFG_SWPR2_PAGE38             SYSCFG_SWPR2_PAGE38_Msk                /*!< SRAM2 Write protection page 38*/\n#define SYSCFG_SWPR2_PAGE39_Pos         (7U)\n#define SYSCFG_SWPR2_PAGE39_Msk         (0x1U << SYSCFG_SWPR2_PAGE39_Pos)      /*!< 0x00000080 */\n#define SYSCFG_SWPR2_PAGE39             SYSCFG_SWPR2_PAGE39_Msk                /*!< SRAM2 Write protection page 39*/\n#define SYSCFG_SWPR2_PAGE40_Pos         (8U)\n#define SYSCFG_SWPR2_PAGE40_Msk         (0x1U << SYSCFG_SWPR2_PAGE40_Pos)      /*!< 0x00000100 */\n#define SYSCFG_SWPR2_PAGE40             SYSCFG_SWPR2_PAGE40_Msk                /*!< SRAM2 Write protection page 40*/\n#define SYSCFG_SWPR2_PAGE41_Pos         (9U)\n#define SYSCFG_SWPR2_PAGE41_Msk         (0x1U << SYSCFG_SWPR2_PAGE41_Pos)      /*!< 0x00000200 */\n#define SYSCFG_SWPR2_PAGE41             SYSCFG_SWPR2_PAGE41_Msk                /*!< SRAM2 Write protection page 41*/\n#define SYSCFG_SWPR2_PAGE42_Pos         (10U)\n#define SYSCFG_SWPR2_PAGE42_Msk         (0x1U << SYSCFG_SWPR2_PAGE42_Pos)      /*!< 0x00000400 */\n#define SYSCFG_SWPR2_PAGE42             SYSCFG_SWPR2_PAGE42_Msk                /*!< SRAM2 Write protection page 42*/\n#define SYSCFG_SWPR2_PAGE43_Pos         (11U)\n#define SYSCFG_SWPR2_PAGE43_Msk         (0x1U << SYSCFG_SWPR2_PAGE43_Pos)      /*!< 0x00000800 */\n#define SYSCFG_SWPR2_PAGE43             SYSCFG_SWPR2_PAGE43_Msk                /*!< SRAM2 Write protection page 43*/\n#define SYSCFG_SWPR2_PAGE44_Pos         (12U)\n#define SYSCFG_SWPR2_PAGE44_Msk         (0x1U << SYSCFG_SWPR2_PAGE44_Pos)      /*!< 0x00001000 */\n#define SYSCFG_SWPR2_PAGE44             SYSCFG_SWPR2_PAGE44_Msk                /*!< SRAM2 Write protection page 44*/\n#define SYSCFG_SWPR2_PAGE45_Pos         (13U)\n#define SYSCFG_SWPR2_PAGE45_Msk         (0x1U << SYSCFG_SWPR2_PAGE45_Pos)      /*!< 0x00002000 */\n#define SYSCFG_SWPR2_PAGE45             SYSCFG_SWPR2_PAGE45_Msk                /*!< SRAM2 Write protection page 45*/\n#define SYSCFG_SWPR2_PAGE46_Pos         (14U)\n#define SYSCFG_SWPR2_PAGE46_Msk         (0x1U << SYSCFG_SWPR2_PAGE46_Pos)      /*!< 0x00004000 */\n#define SYSCFG_SWPR2_PAGE46             SYSCFG_SWPR2_PAGE46_Msk                /*!< SRAM2 Write protection page 46*/\n#define SYSCFG_SWPR2_PAGE47_Pos         (15U)\n#define SYSCFG_SWPR2_PAGE47_Msk         (0x1U << SYSCFG_SWPR2_PAGE47_Pos)      /*!< 0x00008000 */\n#define SYSCFG_SWPR2_PAGE47             SYSCFG_SWPR2_PAGE47_Msk                /*!< SRAM2 Write protection page 47*/\n#define SYSCFG_SWPR2_PAGE48_Pos         (16U)\n#define SYSCFG_SWPR2_PAGE48_Msk         (0x1U << SYSCFG_SWPR2_PAGE48_Pos)      /*!< 0x00010000 */\n#define SYSCFG_SWPR2_PAGE48             SYSCFG_SWPR2_PAGE48_Msk                /*!< SRAM2 Write protection page 48*/\n#define SYSCFG_SWPR2_PAGE49_Pos         (17U)\n#define SYSCFG_SWPR2_PAGE49_Msk         (0x1U << SYSCFG_SWPR2_PAGE49_Pos)      /*!< 0x00020000 */\n#define SYSCFG_SWPR2_PAGE49             SYSCFG_SWPR2_PAGE49_Msk                /*!< SRAM2 Write protection page 49*/\n#define SYSCFG_SWPR2_PAGE50_Pos         (18U)\n#define SYSCFG_SWPR2_PAGE50_Msk         (0x1U << SYSCFG_SWPR2_PAGE50_Pos)      /*!< 0x00040000 */\n#define SYSCFG_SWPR2_PAGE50             SYSCFG_SWPR2_PAGE50_Msk                /*!< SRAM2 Write protection page 50*/\n#define SYSCFG_SWPR2_PAGE51_Pos         (19U)\n#define SYSCFG_SWPR2_PAGE51_Msk         (0x1U << SYSCFG_SWPR2_PAGE51_Pos)      /*!< 0x00080000 */\n#define SYSCFG_SWPR2_PAGE51             SYSCFG_SWPR2_PAGE51_Msk                /*!< SRAM2 Write protection page 51*/\n#define SYSCFG_SWPR2_PAGE52_Pos         (20U)\n#define SYSCFG_SWPR2_PAGE52_Msk         (0x1U << SYSCFG_SWPR2_PAGE52_Pos)      /*!< 0x00100000 */\n#define SYSCFG_SWPR2_PAGE52             SYSCFG_SWPR2_PAGE52_Msk                /*!< SRAM2 Write protection page 52*/\n#define SYSCFG_SWPR2_PAGE53_Pos         (21U)\n#define SYSCFG_SWPR2_PAGE53_Msk         (0x1U << SYSCFG_SWPR2_PAGE53_Pos)      /*!< 0x00200000 */\n#define SYSCFG_SWPR2_PAGE53             SYSCFG_SWPR2_PAGE53_Msk                /*!< SRAM2 Write protection page 53*/\n#define SYSCFG_SWPR2_PAGE54_Pos         (22U)\n#define SYSCFG_SWPR2_PAGE54_Msk         (0x1U << SYSCFG_SWPR2_PAGE54_Pos)      /*!< 0x00400000 */\n#define SYSCFG_SWPR2_PAGE54             SYSCFG_SWPR2_PAGE54_Msk                /*!< SRAM2 Write protection page 54*/\n#define SYSCFG_SWPR2_PAGE55_Pos         (23U)\n#define SYSCFG_SWPR2_PAGE55_Msk         (0x1U << SYSCFG_SWPR2_PAGE55_Pos)      /*!< 0x00800000 */\n#define SYSCFG_SWPR2_PAGE55             SYSCFG_SWPR2_PAGE55_Msk                /*!< SRAM2 Write protection page 55*/\n#define SYSCFG_SWPR2_PAGE56_Pos         (24U)\n#define SYSCFG_SWPR2_PAGE56_Msk         (0x1U << SYSCFG_SWPR2_PAGE56_Pos)      /*!< 0x01000000 */\n#define SYSCFG_SWPR2_PAGE56             SYSCFG_SWPR2_PAGE56_Msk                /*!< SRAM2 Write protection page 56*/\n#define SYSCFG_SWPR2_PAGE57_Pos         (25U)\n#define SYSCFG_SWPR2_PAGE57_Msk         (0x1U << SYSCFG_SWPR2_PAGE57_Pos)      /*!< 0x02000000 */\n#define SYSCFG_SWPR2_PAGE57             SYSCFG_SWPR2_PAGE57_Msk                /*!< SRAM2 Write protection page 57*/\n#define SYSCFG_SWPR2_PAGE58_Pos         (26U)\n#define SYSCFG_SWPR2_PAGE58_Msk         (0x1U << SYSCFG_SWPR2_PAGE58_Pos)      /*!< 0x04000000 */\n#define SYSCFG_SWPR2_PAGE58             SYSCFG_SWPR2_PAGE58_Msk                /*!< SRAM2 Write protection page 58*/\n#define SYSCFG_SWPR2_PAGE59_Pos         (27U)\n#define SYSCFG_SWPR2_PAGE59_Msk         (0x1U << SYSCFG_SWPR2_PAGE59_Pos)      /*!< 0x08000000 */\n#define SYSCFG_SWPR2_PAGE59             SYSCFG_SWPR2_PAGE59_Msk                /*!< SRAM2 Write protection page 59*/\n#define SYSCFG_SWPR2_PAGE60_Pos         (28U)\n#define SYSCFG_SWPR2_PAGE60_Msk         (0x1U << SYSCFG_SWPR2_PAGE60_Pos)      /*!< 0x10000000 */\n#define SYSCFG_SWPR2_PAGE60             SYSCFG_SWPR2_PAGE60_Msk                /*!< SRAM2 Write protection page 60*/\n#define SYSCFG_SWPR2_PAGE61_Pos         (29U)\n#define SYSCFG_SWPR2_PAGE61_Msk         (0x1U << SYSCFG_SWPR2_PAGE61_Pos)      /*!< 0x20000000 */\n#define SYSCFG_SWPR2_PAGE61             SYSCFG_SWPR2_PAGE61_Msk                /*!< SRAM2 Write protection page 61*/\n#define SYSCFG_SWPR2_PAGE62_Pos         (30U)\n#define SYSCFG_SWPR2_PAGE62_Msk         (0x1U << SYSCFG_SWPR2_PAGE62_Pos)      /*!< 0x40000000 */\n#define SYSCFG_SWPR2_PAGE62             SYSCFG_SWPR2_PAGE62_Msk                /*!< SRAM2 Write protection page 62*/\n#define SYSCFG_SWPR2_PAGE63_Pos         (31U)\n#define SYSCFG_SWPR2_PAGE63_Msk         (0x1U << SYSCFG_SWPR2_PAGE63_Pos)      /*!< 0x80000000 */\n#define SYSCFG_SWPR2_PAGE63             SYSCFG_SWPR2_PAGE63_Msk                /*!< SRAM2 Write protection page 63*/\n\n/******************  Bit definition for SYSCFG_SKR register  ****************/\n#define SYSCFG_SKR_KEY_Pos              (0U)\n#define SYSCFG_SKR_KEY_Msk              (0xFFU << SYSCFG_SKR_KEY_Pos)          /*!< 0x000000FF */\n#define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */\n\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)\n#define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */\n#define TIM_CR1_UDIS_Pos          (1U)\n#define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */\n#define TIM_CR1_URS_Pos           (2U)\n#define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)\n#define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */\n#define TIM_CR1_DIR_Pos           (4U)\n#define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */\n\n#define TIM_CR1_CMS_Pos           (5U)\n#define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */\n#define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)\n#define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */\n\n#define TIM_CR1_CKD_Pos           (8U)\n#define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */\n#define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */\n\n#define TIM_CR1_UIFREMAP_Pos      (11U)\n#define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */\n#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)\n#define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */\n#define TIM_CR2_CCUS_Pos          (2U)\n#define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)\n#define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */\n\n#define TIM_CR2_MMS_Pos           (4U)\n#define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */\n#define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */\n#define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)\n#define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)\n#define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */\n#define TIM_CR2_OIS1N_Pos         (9U)\n#define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)\n#define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */\n#define TIM_CR2_OIS2N_Pos         (11U)\n#define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)\n#define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */\n#define TIM_CR2_OIS3N_Pos         (13U)\n#define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)\n#define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */\n#define TIM_CR2_OIS5_Pos          (16U)\n#define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */\n#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */\n#define TIM_CR2_OIS6_Pos          (18U)\n#define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */\n#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */\n\n#define TIM_CR2_MMS2_Pos          (20U)\n#define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */\n#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */\n#define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */\n#define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */\n#define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)\n#define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */\n#define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */\n#define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */\n#define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */\n#define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */\n\n#define TIM_SMCR_OCCS_Pos         (3U)\n#define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */\n#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */\n\n#define TIM_SMCR_TS_Pos           (4U)\n#define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */\n#define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */\n#define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */\n#define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)\n#define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */\n\n#define TIM_SMCR_ETF_Pos          (8U)\n#define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */\n#define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */\n#define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */\n#define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)\n#define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */\n#define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)\n#define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */\n#define TIM_SMCR_ETP_Pos          (15U)\n#define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)\n#define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)\n#define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */\n#define TIM_DIER_CC2IE_Pos        (2U)\n#define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */\n#define TIM_DIER_CC3IE_Pos        (3U)\n#define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */\n#define TIM_DIER_CC4IE_Pos        (4U)\n#define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */\n#define TIM_DIER_COMIE_Pos        (5U)\n#define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */\n#define TIM_DIER_TIE_Pos          (6U)\n#define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */\n#define TIM_DIER_BIE_Pos          (7U)\n#define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */\n#define TIM_DIER_UDE_Pos          (8U)\n#define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */\n#define TIM_DIER_CC1DE_Pos        (9U)\n#define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)\n#define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)\n#define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)\n#define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)\n#define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */\n#define TIM_DIER_TDE_Pos          (14U)\n#define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)\n#define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */\n#define TIM_SR_CC1IF_Pos          (1U)\n#define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */\n#define TIM_SR_CC2IF_Pos          (2U)\n#define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */\n#define TIM_SR_CC3IF_Pos          (3U)\n#define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */\n#define TIM_SR_CC4IF_Pos          (4U)\n#define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */\n#define TIM_SR_COMIF_Pos          (5U)\n#define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */\n#define TIM_SR_TIF_Pos            (6U)\n#define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */\n#define TIM_SR_BIF_Pos            (7U)\n#define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */\n#define TIM_SR_B2IF_Pos           (8U)\n#define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */\n#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */\n#define TIM_SR_CC1OF_Pos          (9U)\n#define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)\n#define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)\n#define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)\n#define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n#define TIM_SR_SBIF_Pos           (13U)\n#define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */\n#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */\n#define TIM_SR_CC5IF_Pos          (16U)\n#define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */\n#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */\n#define TIM_SR_CC6IF_Pos          (17U)\n#define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */\n#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */\n\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)\n#define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */\n#define TIM_EGR_CC1G_Pos          (1U)\n#define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */\n#define TIM_EGR_CC2G_Pos          (2U)\n#define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */\n#define TIM_EGR_CC3G_Pos          (3U)\n#define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */\n#define TIM_EGR_CC4G_Pos          (4U)\n#define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */\n#define TIM_EGR_COMG_Pos          (5U)\n#define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)\n#define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */\n#define TIM_EGR_BG_Pos            (7U)\n#define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */\n#define TIM_EGR_B2G_Pos           (8U)\n#define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */\n#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */\n\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)\n#define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */\n#define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)\n#define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */\n#define TIM_CCMR1_OC1PE_Pos       (3U)\n#define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)\n#define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\n#define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */\n#define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */\n#define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */\n#define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)\n#define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)\n#define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */\n#define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)\n#define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */\n#define TIM_CCMR1_OC2PE_Pos       (11U)\n#define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)\n#define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\n#define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */\n#define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */\n#define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */\n#define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)\n#define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n#define TIM_CCMR1_IC1PSC_Pos      (2U)\n#define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)\n#define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\n#define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */\n#define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */\n#define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */\n#define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)\n#define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\n#define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)\n#define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\n#define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */\n#define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */\n#define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */\n#define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)\n#define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\n#define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */\n#define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)\n#define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */\n#define TIM_CCMR2_OC3PE_Pos       (3U)\n#define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)\n#define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */\n#define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */\n#define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */\n#define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)\n#define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)\n#define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */\n#define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)\n#define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */\n#define TIM_CCMR2_OC4PE_Pos       (11U)\n#define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)\n#define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */\n#define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */\n#define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */\n#define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)\n#define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n#define TIM_CCMR2_IC3PSC_Pos      (2U)\n#define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)\n#define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */\n#define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */\n#define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */\n#define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)\n#define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)\n#define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */\n#define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */\n#define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */\n#define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */\n\n/******************  Bit definition for TIM_CCMR3 register  *******************/\n#define TIM_CCMR3_OC5FE_Pos       (2U)\n#define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */\n#define TIM_CCMR3_OC5PE_Pos       (3U)\n#define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */\n\n#define TIM_CCMR3_OC5M_Pos        (4U)\n#define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */\n#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */\n#define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */\n#define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */\n#define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */\n#define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */\n\n#define TIM_CCMR3_OC5CE_Pos       (7U)\n#define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */\n\n#define TIM_CCMR3_OC6FE_Pos       (10U)\n#define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */\n#define TIM_CCMR3_OC6PE_Pos       (11U)\n#define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */\n\n#define TIM_CCMR3_OC6M_Pos        (12U)\n#define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */\n#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */\n#define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */\n#define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */\n#define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */\n#define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */\n\n#define TIM_CCMR3_OC6CE_Pos       (15U)\n#define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)\n#define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */\n#define TIM_CCER_CC1P_Pos         (1U)\n#define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */\n#define TIM_CCER_CC1NE_Pos        (2U)\n#define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */\n#define TIM_CCER_CC1NP_Pos        (3U)\n#define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)\n#define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */\n#define TIM_CCER_CC2P_Pos         (5U)\n#define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */\n#define TIM_CCER_CC2NE_Pos        (6U)\n#define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */\n#define TIM_CCER_CC2NP_Pos        (7U)\n#define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)\n#define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */\n#define TIM_CCER_CC3P_Pos         (9U)\n#define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */\n#define TIM_CCER_CC3NE_Pos        (10U)\n#define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */\n#define TIM_CCER_CC3NP_Pos        (11U)\n#define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)\n#define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */\n#define TIM_CCER_CC4P_Pos         (13U)\n#define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */\n#define TIM_CCER_CC4NP_Pos        (15U)\n#define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n#define TIM_CCER_CC5E_Pos         (16U)\n#define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */\n#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */\n#define TIM_CCER_CC5P_Pos         (17U)\n#define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */\n#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */\n#define TIM_CCER_CC6E_Pos         (20U)\n#define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */\n#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */\n#define TIM_CCER_CC6P_Pos         (21U)\n#define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */\n#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)\n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */\n#define TIM_CNT_UIFCPY_Pos        (31U)\n#define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */\n#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)\n#define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)\n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)\n#define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)\n#define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)\n#define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)\n#define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)\n#define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */\n\n/*******************  Bit definition for TIM_CCR5 register  *******************/\n#define TIM_CCR5_CCR5_Pos         (0U)\n#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */\n#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */\n#define TIM_CCR5_GC5C1_Pos        (29U)\n#define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */\n#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */\n#define TIM_CCR5_GC5C2_Pos        (30U)\n#define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */\n#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */\n#define TIM_CCR5_GC5C3_Pos        (31U)\n#define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */\n#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */\n\n/*******************  Bit definition for TIM_CCR6 register  *******************/\n#define TIM_CCR6_CCR6_Pos         (0U)\n#define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)\n#define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */\n#define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */\n#define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */\n#define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */\n#define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */\n#define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */\n#define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */\n#define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)\n#define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */\n#define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)\n#define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)\n#define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */\n#define TIM_BDTR_BKE_Pos          (12U)\n#define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */\n#define TIM_BDTR_BKP_Pos          (13U)\n#define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */\n#define TIM_BDTR_AOE_Pos          (14U)\n#define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */\n#define TIM_BDTR_MOE_Pos          (15U)\n#define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */\n\n#define TIM_BDTR_BKF_Pos          (16U)\n#define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */\n#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */\n#define TIM_BDTR_BK2F_Pos         (20U)\n#define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */\n#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */\n\n#define TIM_BDTR_BK2E_Pos         (24U)\n#define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */\n#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */\n#define TIM_BDTR_BK2P_Pos         (25U)\n#define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */\n#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)\n#define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */\n#define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */\n#define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */\n#define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */\n#define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */\n\n#define TIM_DCR_DBL_Pos           (8U)\n#define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */\n#define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */\n#define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */\n#define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */\n#define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)\n#define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */\n\n/*******************  Bit definition for TIM1_OR1 register  *******************/\n#define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)\n#define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */\n#define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */\n#define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */\n#define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */\n\n#define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)\n#define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */\n#define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */\n#define TIM1_OR1_ETR_ADC3_RMP_0        (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */\n#define TIM1_OR1_ETR_ADC3_RMP_1        (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */\n\n#define TIM1_OR1_TI1_RMP_Pos           (4U)\n#define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */\n#define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */\n\n/*******************  Bit definition for TIM1_OR2 register  *******************/\n#define TIM1_OR2_BKINE_Pos             (0U)\n#define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */\n#define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */\n#define TIM1_OR2_BKCMP1E_Pos           (1U)\n#define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */\n#define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */\n#define TIM1_OR2_BKCMP2E_Pos           (2U)\n#define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */\n#define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */\n#define TIM1_OR2_BKDF1BK0E_Pos         (8U)\n#define TIM1_OR2_BKDF1BK0E_Msk         (0x1U << TIM1_OR2_BKDF1BK0E_Pos)        /*!< 0x00000100 */\n#define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */\n#define TIM1_OR2_BKINP_Pos             (9U)\n#define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */\n#define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */\n#define TIM1_OR2_BKCMP1P_Pos           (10U)\n#define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */\n#define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */\n#define TIM1_OR2_BKCMP2P_Pos           (11U)\n#define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */\n#define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */\n\n#define TIM1_OR2_ETRSEL_Pos            (14U)\n#define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */\n#define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */\n#define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */\n#define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */\n#define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */\n\n/*******************  Bit definition for TIM1_OR3 register  *******************/\n#define TIM1_OR3_BK2INE_Pos            (0U)\n#define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */\n#define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */\n#define TIM1_OR3_BK2CMP1E_Pos          (1U)\n#define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */\n#define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */\n#define TIM1_OR3_BK2CMP2E_Pos          (2U)\n#define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */\n#define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */\n#define TIM1_OR3_BK2DF1BK1E_Pos        (8U)\n#define TIM1_OR3_BK2DF1BK1E_Msk        (0x1U << TIM1_OR3_BK2DF1BK1E_Pos)       /*!< 0x00000100 */\n#define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */\n#define TIM1_OR3_BK2INP_Pos            (9U)\n#define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */\n#define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */\n#define TIM1_OR3_BK2CMP1P_Pos          (10U)\n#define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */\n#define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */\n#define TIM1_OR3_BK2CMP2P_Pos          (11U)\n#define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */\n#define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */\n\n/*******************  Bit definition for TIM8_OR1 register  *******************/\n#define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)\n#define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000003 */\n#define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */\n#define TIM8_OR1_ETR_ADC2_RMP_0        (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000001 */\n#define TIM8_OR1_ETR_ADC2_RMP_1        (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000002 */\n\n#define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)\n#define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */\n#define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */\n#define TIM8_OR1_ETR_ADC3_RMP_0        (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */\n#define TIM8_OR1_ETR_ADC3_RMP_1        (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */\n\n#define TIM8_OR1_TI1_RMP_Pos           (4U)\n#define TIM8_OR1_TI1_RMP_Msk           (0x1U << TIM8_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */\n#define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */\n\n/*******************  Bit definition for TIM8_OR2 register  *******************/\n#define TIM8_OR2_BKINE_Pos             (0U)\n#define TIM8_OR2_BKINE_Msk             (0x1U << TIM8_OR2_BKINE_Pos)            /*!< 0x00000001 */\n#define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */\n#define TIM8_OR2_BKCMP1E_Pos           (1U)\n#define TIM8_OR2_BKCMP1E_Msk           (0x1U << TIM8_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */\n#define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */\n#define TIM8_OR2_BKCMP2E_Pos           (2U)\n#define TIM8_OR2_BKCMP2E_Msk           (0x1U << TIM8_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */\n#define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */\n#define TIM8_OR2_BKDF1BK2E_Pos         (8U)\n#define TIM8_OR2_BKDF1BK2E_Msk         (0x1U << TIM8_OR2_BKDF1BK2E_Pos)        /*!< 0x00000100 */\n#define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */\n#define TIM8_OR2_BKINP_Pos             (9U)\n#define TIM8_OR2_BKINP_Msk             (0x1U << TIM8_OR2_BKINP_Pos)            /*!< 0x00000200 */\n#define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */\n#define TIM8_OR2_BKCMP1P_Pos           (10U)\n#define TIM8_OR2_BKCMP1P_Msk           (0x1U << TIM8_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */\n#define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */\n#define TIM8_OR2_BKCMP2P_Pos           (11U)\n#define TIM8_OR2_BKCMP2P_Msk           (0x1U << TIM8_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */\n#define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */\n\n#define TIM8_OR2_ETRSEL_Pos            (14U)\n#define TIM8_OR2_ETRSEL_Msk            (0x7U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */\n#define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */\n#define TIM8_OR2_ETRSEL_0              (0x1U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00004000 */\n#define TIM8_OR2_ETRSEL_1              (0x2U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00008000 */\n#define TIM8_OR2_ETRSEL_2              (0x4U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00010000 */\n\n/*******************  Bit definition for TIM8_OR3 register  *******************/\n#define TIM8_OR3_BK2INE_Pos            (0U)\n#define TIM8_OR3_BK2INE_Msk            (0x1U << TIM8_OR3_BK2INE_Pos)           /*!< 0x00000001 */\n#define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */\n#define TIM8_OR3_BK2CMP1E_Pos          (1U)\n#define TIM8_OR3_BK2CMP1E_Msk          (0x1U << TIM8_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */\n#define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */\n#define TIM8_OR3_BK2CMP2E_Pos          (2U)\n#define TIM8_OR3_BK2CMP2E_Msk          (0x1U << TIM8_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */\n#define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */\n#define TIM8_OR3_BK2DF1BK3E_Pos        (8U)\n#define TIM8_OR3_BK2DF1BK3E_Msk        (0x1U << TIM8_OR3_BK2DF1BK3E_Pos)       /*!< 0x00000100 */\n#define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */\n#define TIM8_OR3_BK2INP_Pos            (9U)\n#define TIM8_OR3_BK2INP_Msk            (0x1U << TIM8_OR3_BK2INP_Pos)           /*!< 0x00000200 */\n#define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */\n#define TIM8_OR3_BK2CMP1P_Pos          (10U)\n#define TIM8_OR3_BK2CMP1P_Msk          (0x1U << TIM8_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */\n#define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */\n#define TIM8_OR3_BK2CMP2P_Pos          (11U)\n#define TIM8_OR3_BK2CMP2P_Msk          (0x1U << TIM8_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */\n#define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */\n\n/*******************  Bit definition for TIM2_OR1 register  *******************/\n#define TIM2_OR1_ITR1_RMP_Pos     (0U)\n#define TIM2_OR1_ITR1_RMP_Msk     (0x1U << TIM2_OR1_ITR1_RMP_Pos)              /*!< 0x00000001 */\n#define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */\n#define TIM2_OR1_ETR1_RMP_Pos     (1U)\n#define TIM2_OR1_ETR1_RMP_Msk     (0x1U << TIM2_OR1_ETR1_RMP_Pos)              /*!< 0x00000002 */\n#define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */\n\n#define TIM2_OR1_TI4_RMP_Pos      (2U)\n#define TIM2_OR1_TI4_RMP_Msk      (0x3U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x0000000C */\n#define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */\n#define TIM2_OR1_TI4_RMP_0        (0x1U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000004 */\n#define TIM2_OR1_TI4_RMP_1        (0x2U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000008 */\n\n/*******************  Bit definition for TIM2_OR2 register  *******************/\n#define TIM2_OR2_ETRSEL_Pos       (14U)\n#define TIM2_OR2_ETRSEL_Msk       (0x7U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */\n#define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */\n#define TIM2_OR2_ETRSEL_0         (0x1U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00004000 */\n#define TIM2_OR2_ETRSEL_1         (0x2U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00008000 */\n#define TIM2_OR2_ETRSEL_2         (0x4U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00010000 */\n\n/*******************  Bit definition for TIM3_OR1 register  *******************/\n#define TIM3_OR1_TI1_RMP_Pos      (0U)\n#define TIM3_OR1_TI1_RMP_Msk      (0x3U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000003 */\n#define TIM3_OR1_TI1_RMP          TIM3_OR1_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */\n#define TIM3_OR1_TI1_RMP_0        (0x1U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000001 */\n#define TIM3_OR1_TI1_RMP_1        (0x2U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000002 */\n\n/*******************  Bit definition for TIM3_OR2 register  *******************/\n#define TIM3_OR2_ETRSEL_Pos       (14U)\n#define TIM3_OR2_ETRSEL_Msk       (0x7U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */\n#define TIM3_OR2_ETRSEL           TIM3_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */\n#define TIM3_OR2_ETRSEL_0         (0x1U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00004000 */\n#define TIM3_OR2_ETRSEL_1         (0x2U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00008000 */\n#define TIM3_OR2_ETRSEL_2         (0x4U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00010000 */\n\n/*******************  Bit definition for TIM15_OR1 register  ******************/\n#define TIM15_OR1_TI1_RMP_Pos           (0U)\n#define TIM15_OR1_TI1_RMP_Msk           (0x1U << TIM15_OR1_TI1_RMP_Pos)        /*!< 0x00000001 */\n#define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */\n\n#define TIM15_OR1_ENCODER_MODE_Pos      (1U)\n#define TIM15_OR1_ENCODER_MODE_Msk      (0x3U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000006 */\n#define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */\n#define TIM15_OR1_ENCODER_MODE_0        (0x1U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000002 */\n#define TIM15_OR1_ENCODER_MODE_1        (0x2U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000004 */\n\n/*******************  Bit definition for TIM15_OR2 register  ******************/\n#define TIM15_OR2_BKINE_Pos             (0U)\n#define TIM15_OR2_BKINE_Msk             (0x1U << TIM15_OR2_BKINE_Pos)          /*!< 0x00000001 */\n#define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */\n#define TIM15_OR2_BKCMP1E_Pos           (1U)\n#define TIM15_OR2_BKCMP1E_Msk           (0x1U << TIM15_OR2_BKCMP1E_Pos)        /*!< 0x00000002 */\n#define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */\n#define TIM15_OR2_BKCMP2E_Pos           (2U)\n#define TIM15_OR2_BKCMP2E_Msk           (0x1U << TIM15_OR2_BKCMP2E_Pos)        /*!< 0x00000004 */\n#define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */\n#define TIM15_OR2_BKDF1BK0E_Pos         (8U)\n#define TIM15_OR2_BKDF1BK0E_Msk         (0x1U << TIM15_OR2_BKDF1BK0E_Pos)      /*!< 0x00000100 */\n#define TIM15_OR2_BKDF1BK0E             TIM15_OR2_BKDF1BK0E_Msk                /*!<BRK DFSDM1_BREAK[0] enable */\n#define TIM15_OR2_BKINP_Pos             (9U)\n#define TIM15_OR2_BKINP_Msk             (0x1U << TIM15_OR2_BKINP_Pos)          /*!< 0x00000200 */\n#define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */\n#define TIM15_OR2_BKCMP1P_Pos           (10U)\n#define TIM15_OR2_BKCMP1P_Msk           (0x1U << TIM15_OR2_BKCMP1P_Pos)        /*!< 0x00000400 */\n#define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */\n#define TIM15_OR2_BKCMP2P_Pos           (11U)\n#define TIM15_OR2_BKCMP2P_Msk           (0x1U << TIM15_OR2_BKCMP2P_Pos)        /*!< 0x00000800 */\n#define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */\n\n/*******************  Bit definition for TIM16_OR1 register  ******************/\n#define TIM16_OR1_TI1_RMP_Pos      (0U)\n#define TIM16_OR1_TI1_RMP_Msk      (0x7U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000007 */\n#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */\n#define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */\n#define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */\n#define TIM16_OR1_TI1_RMP_2        (0x4U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000004 */\n\n/*******************  Bit definition for TIM16_OR2 register  ******************/\n#define TIM16_OR2_BKINE_Pos        (0U)\n#define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */\n#define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */\n#define TIM16_OR2_BKCMP1E_Pos      (1U)\n#define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */\n#define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */\n#define TIM16_OR2_BKCMP2E_Pos      (2U)\n#define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */\n#define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */\n#define TIM16_OR2_BKDF1BK1E_Pos    (8U)\n#define TIM16_OR2_BKDF1BK1E_Msk    (0x1U << TIM16_OR2_BKDF1BK1E_Pos)           /*!< 0x00000100 */\n#define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */\n#define TIM16_OR2_BKINP_Pos        (9U)\n#define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */\n#define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */\n#define TIM16_OR2_BKCMP1P_Pos      (10U)\n#define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */\n#define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */\n#define TIM16_OR2_BKCMP2P_Pos      (11U)\n#define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */\n#define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */\n\n/*******************  Bit definition for TIM17_OR1 register  ******************/\n#define TIM17_OR1_TI1_RMP_Pos      (0U)\n#define TIM17_OR1_TI1_RMP_Msk      (0x3U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */\n#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */\n#define TIM17_OR1_TI1_RMP_0        (0x1U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */\n#define TIM17_OR1_TI1_RMP_1        (0x2U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */\n\n/*******************  Bit definition for TIM17_OR2 register  ******************/\n#define TIM17_OR2_BKINE_Pos        (0U)\n#define TIM17_OR2_BKINE_Msk        (0x1U << TIM17_OR2_BKINE_Pos)               /*!< 0x00000001 */\n#define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */\n#define TIM17_OR2_BKCMP1E_Pos      (1U)\n#define TIM17_OR2_BKCMP1E_Msk      (0x1U << TIM17_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */\n#define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */\n#define TIM17_OR2_BKCMP2E_Pos      (2U)\n#define TIM17_OR2_BKCMP2E_Msk      (0x1U << TIM17_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */\n#define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */\n#define TIM17_OR2_BKDF1BK2E_Pos    (8U)\n#define TIM17_OR2_BKDF1BK2E_Msk    (0x1U << TIM17_OR2_BKDF1BK2E_Pos)           /*!< 0x00000100 */\n#define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */\n#define TIM17_OR2_BKINP_Pos        (9U)\n#define TIM17_OR2_BKINP_Msk        (0x1U << TIM17_OR2_BKINP_Pos)               /*!< 0x00000200 */\n#define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */\n#define TIM17_OR2_BKCMP1P_Pos      (10U)\n#define TIM17_OR2_BKCMP1P_Msk      (0x1U << TIM17_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */\n#define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */\n#define TIM17_OR2_BKCMP2P_Pos      (11U)\n#define TIM17_OR2_BKCMP2P_Msk      (0x1U << TIM17_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */\n#define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Low Power Timer (LPTTIM)                           */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for LPTIM_ISR register  *******************/\n#define LPTIM_ISR_CMPM_Pos          (0U)\n#define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */\n#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */\n#define LPTIM_ISR_ARRM_Pos          (1U)\n#define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */\n#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */\n#define LPTIM_ISR_EXTTRIG_Pos       (2U)\n#define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */\n#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */\n#define LPTIM_ISR_CMPOK_Pos         (3U)\n#define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */\n#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */\n#define LPTIM_ISR_ARROK_Pos         (4U)\n#define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */\n#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */\n#define LPTIM_ISR_UP_Pos            (5U)\n#define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */\n#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */\n#define LPTIM_ISR_DOWN_Pos          (6U)\n#define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */\n#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */\n\n/******************  Bit definition for LPTIM_ICR register  *******************/\n#define LPTIM_ICR_CMPMCF_Pos        (0U)\n#define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */\n#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */\n#define LPTIM_ICR_ARRMCF_Pos        (1U)\n#define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */\n#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */\n#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)\n#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */\n#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */\n#define LPTIM_ICR_CMPOKCF_Pos       (3U)\n#define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */\n#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */\n#define LPTIM_ICR_ARROKCF_Pos       (4U)\n#define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */\n#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */\n#define LPTIM_ICR_UPCF_Pos          (5U)\n#define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */\n#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */\n#define LPTIM_ICR_DOWNCF_Pos        (6U)\n#define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */\n#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */\n\n/******************  Bit definition for LPTIM_IER register ********************/\n#define LPTIM_IER_CMPMIE_Pos        (0U)\n#define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */\n#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */\n#define LPTIM_IER_ARRMIE_Pos        (1U)\n#define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */\n#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */\n#define LPTIM_IER_EXTTRIGIE_Pos     (2U)\n#define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */\n#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */\n#define LPTIM_IER_CMPOKIE_Pos       (3U)\n#define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */\n#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */\n#define LPTIM_IER_ARROKIE_Pos       (4U)\n#define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */\n#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */\n#define LPTIM_IER_UPIE_Pos          (5U)\n#define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */\n#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */\n#define LPTIM_IER_DOWNIE_Pos        (6U)\n#define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */\n#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */\n\n/******************  Bit definition for LPTIM_CFGR register *******************/\n#define LPTIM_CFGR_CKSEL_Pos        (0U)\n#define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */\n#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */\n\n#define LPTIM_CFGR_CKPOL_Pos        (1U)\n#define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */\n#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */\n#define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */\n#define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */\n\n#define LPTIM_CFGR_CKFLT_Pos        (3U)\n#define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */\n#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\n#define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */\n#define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */\n\n#define LPTIM_CFGR_TRGFLT_Pos       (6U)\n#define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */\n#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\n#define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */\n#define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */\n\n#define LPTIM_CFGR_PRESC_Pos        (9U)\n#define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */\n#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */\n#define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */\n#define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */\n#define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */\n\n#define LPTIM_CFGR_TRIGSEL_Pos      (13U)\n#define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */\n#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */\n#define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */\n#define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */\n#define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */\n\n#define LPTIM_CFGR_TRIGEN_Pos       (17U)\n#define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */\n#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\n#define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */\n#define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */\n\n#define LPTIM_CFGR_TIMOUT_Pos       (19U)\n#define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */\n#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */\n#define LPTIM_CFGR_WAVE_Pos         (20U)\n#define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */\n#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */\n#define LPTIM_CFGR_WAVPOL_Pos       (21U)\n#define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */\n#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */\n#define LPTIM_CFGR_PRELOAD_Pos      (22U)\n#define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */\n#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */\n#define LPTIM_CFGR_COUNTMODE_Pos    (23U)\n#define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */\n#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */\n#define LPTIM_CFGR_ENC_Pos          (24U)\n#define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */\n#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */\n\n/******************  Bit definition for LPTIM_CR register  ********************/\n#define LPTIM_CR_ENABLE_Pos         (0U)\n#define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */\n#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */\n#define LPTIM_CR_SNGSTRT_Pos        (1U)\n#define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */\n#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */\n#define LPTIM_CR_CNTSTRT_Pos        (2U)\n#define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */\n#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */\n\n/******************  Bit definition for LPTIM_CMP register  *******************/\n#define LPTIM_CMP_CMP_Pos           (0U)\n#define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */\n#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */\n\n/******************  Bit definition for LPTIM_ARR register  *******************/\n#define LPTIM_ARR_ARR_Pos           (0U)\n#define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */\n#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */\n\n/******************  Bit definition for LPTIM_CNT register  *******************/\n#define LPTIM_CNT_CNT_Pos           (0U)\n#define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */\n#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */\n\n/******************  Bit definition for LPTIM_OR register  ********************/\n#define LPTIM_OR_OR_Pos             (0U)\n#define LPTIM_OR_OR_Msk             (0x3U << LPTIM_OR_OR_Pos)                  /*!< 0x00000003 */\n#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */\n#define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */\n#define LPTIM_OR_OR_1               (0x2U << LPTIM_OR_OR_Pos)                  /*!< 0x00000002 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Analog Comparators (COMP)                             */\n/*                                                                            */\n/******************************************************************************/\n/**********************  Bit definition for COMP_CSR register  ****************/\n#define COMP_CSR_EN_Pos            (0U)\n#define COMP_CSR_EN_Msk            (0x1U << COMP_CSR_EN_Pos)                   /*!< 0x00000001 */\n#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */\n\n#define COMP_CSR_PWRMODE_Pos       (2U)\n#define COMP_CSR_PWRMODE_Msk       (0x3U << COMP_CSR_PWRMODE_Pos)              /*!< 0x0000000C */\n#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */\n#define COMP_CSR_PWRMODE_0         (0x1U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000004 */\n#define COMP_CSR_PWRMODE_1         (0x2U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000008 */\n\n#define COMP_CSR_INMSEL_Pos        (4U)\n#define COMP_CSR_INMSEL_Msk        (0x7U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000070 */\n#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */\n#define COMP_CSR_INMSEL_0          (0x1U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000010 */\n#define COMP_CSR_INMSEL_1          (0x2U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000020 */\n#define COMP_CSR_INMSEL_2          (0x4U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000040 */\n\n#define COMP_CSR_INPSEL_Pos        (7U)\n#define COMP_CSR_INPSEL_Msk        (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */\n#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */\n#define COMP_CSR_INPSEL_0          (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */\n\n#define COMP_CSR_WINMODE_Pos       (9U)\n#define COMP_CSR_WINMODE_Msk       (0x1U << COMP_CSR_WINMODE_Pos)              /*!< 0x00000200 */\n#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */\n\n#define COMP_CSR_POLARITY_Pos      (15U)\n#define COMP_CSR_POLARITY_Msk      (0x1U << COMP_CSR_POLARITY_Pos)             /*!< 0x00008000 */\n#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */\n\n#define COMP_CSR_HYST_Pos          (16U)\n#define COMP_CSR_HYST_Msk          (0x3U << COMP_CSR_HYST_Pos)                 /*!< 0x00030000 */\n#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */\n#define COMP_CSR_HYST_0            (0x1U << COMP_CSR_HYST_Pos)                 /*!< 0x00010000 */\n#define COMP_CSR_HYST_1            (0x2U << COMP_CSR_HYST_Pos)                 /*!< 0x00020000 */\n\n#define COMP_CSR_BLANKING_Pos      (18U)\n#define COMP_CSR_BLANKING_Msk      (0x7U << COMP_CSR_BLANKING_Pos)             /*!< 0x001C0000 */\n#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */\n#define COMP_CSR_BLANKING_0        (0x1U << COMP_CSR_BLANKING_Pos)             /*!< 0x00040000 */\n#define COMP_CSR_BLANKING_1        (0x2U << COMP_CSR_BLANKING_Pos)             /*!< 0x00080000 */\n#define COMP_CSR_BLANKING_2        (0x4U << COMP_CSR_BLANKING_Pos)             /*!< 0x00100000 */\n\n#define COMP_CSR_BRGEN_Pos         (22U)\n#define COMP_CSR_BRGEN_Msk         (0x1U << COMP_CSR_BRGEN_Pos)                /*!< 0x00400000 */\n#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */\n#define COMP_CSR_SCALEN_Pos        (23U)\n#define COMP_CSR_SCALEN_Msk        (0x1U << COMP_CSR_SCALEN_Pos)               /*!< 0x00800000 */\n#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */\n\n#define COMP_CSR_VALUE_Pos         (30U)\n#define COMP_CSR_VALUE_Msk         (0x1U << COMP_CSR_VALUE_Pos)                /*!< 0x40000000 */\n#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */\n\n#define COMP_CSR_LOCK_Pos          (31U)\n#define COMP_CSR_LOCK_Msk          (0x1U << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */\n#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Operational Amplifier (OPAMP)                      */\n/*                                                                            */\n/******************************************************************************/\n/*********************  Bit definition for OPAMPx_CSR register  ***************/\n#define OPAMP_CSR_OPAMPxEN_Pos           (0U)\n#define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */\n#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */\n#define OPAMP_CSR_OPALPM_Pos             (1U)\n#define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */\n#define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */\n\n#define OPAMP_CSR_OPAMODE_Pos            (2U)\n#define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */\n#define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */\n#define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */\n#define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */\n\n#define OPAMP_CSR_PGGAIN_Pos             (4U)\n#define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */\n#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */\n#define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */\n#define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */\n\n#define OPAMP_CSR_VMSEL_Pos              (8U)\n#define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */\n#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */\n#define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */\n#define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */\n\n#define OPAMP_CSR_VPSEL_Pos              (10U)\n#define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */\n#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */\n#define OPAMP_CSR_CALON_Pos              (12U)\n#define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */\n#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */\n#define OPAMP_CSR_CALSEL_Pos             (13U)\n#define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */\n#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */\n#define OPAMP_CSR_USERTRIM_Pos           (14U)\n#define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */\n#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */\n#define OPAMP_CSR_CALOUT_Pos             (15U)\n#define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */\n#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */\n\n/*********************  Bit definition for OPAMP1_CSR register  ***************/\n#define OPAMP1_CSR_OPAEN_Pos              (0U)\n#define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */\n#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */\n#define OPAMP1_CSR_OPALPM_Pos             (1U)\n#define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */\n#define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */\n\n#define OPAMP1_CSR_OPAMODE_Pos            (2U)\n#define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */\n#define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */\n#define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */\n#define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */\n\n#define OPAMP1_CSR_PGAGAIN_Pos            (4U)\n#define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */\n#define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */\n#define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */\n#define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */\n\n#define OPAMP1_CSR_VMSEL_Pos              (8U)\n#define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */\n#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */\n#define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */\n#define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */\n\n#define OPAMP1_CSR_VPSEL_Pos              (10U)\n#define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */\n#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\n#define OPAMP1_CSR_CALON_Pos              (12U)\n#define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */\n#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */\n#define OPAMP1_CSR_CALSEL_Pos             (13U)\n#define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */\n#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */\n#define OPAMP1_CSR_USERTRIM_Pos           (14U)\n#define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */\n#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */\n#define OPAMP1_CSR_CALOUT_Pos             (15U)\n#define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */\n#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */\n\n#define OPAMP1_CSR_OPARANGE_Pos           (31U)\n#define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */\n#define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */\n\n/*********************  Bit definition for OPAMP2_CSR register  ***************/\n#define OPAMP2_CSR_OPAEN_Pos              (0U)\n#define OPAMP2_CSR_OPAEN_Msk              (0x1U << OPAMP2_CSR_OPAEN_Pos)       /*!< 0x00000001 */\n#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */\n#define OPAMP2_CSR_OPALPM_Pos             (1U)\n#define OPAMP2_CSR_OPALPM_Msk             (0x1U << OPAMP2_CSR_OPALPM_Pos)      /*!< 0x00000002 */\n#define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */\n\n#define OPAMP2_CSR_OPAMODE_Pos            (2U)\n#define OPAMP2_CSR_OPAMODE_Msk            (0x3U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x0000000C */\n#define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */\n#define OPAMP2_CSR_OPAMODE_0              (0x1U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000004 */\n#define OPAMP2_CSR_OPAMODE_1              (0x2U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000008 */\n\n#define OPAMP2_CSR_PGAGAIN_Pos            (4U)\n#define OPAMP2_CSR_PGAGAIN_Msk            (0x3U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */\n#define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */\n#define OPAMP2_CSR_PGAGAIN_0              (0x1U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */\n#define OPAMP2_CSR_PGAGAIN_1              (0x2U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */\n\n#define OPAMP2_CSR_VMSEL_Pos              (8U)\n#define OPAMP2_CSR_VMSEL_Msk              (0x3U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000300 */\n#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */\n#define OPAMP2_CSR_VMSEL_0                (0x1U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000100 */\n#define OPAMP2_CSR_VMSEL_1                (0x2U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000200 */\n\n#define OPAMP2_CSR_VPSEL_Pos              (10U)\n#define OPAMP2_CSR_VPSEL_Msk              (0x1U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000400 */\n#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */\n#define OPAMP2_CSR_CALON_Pos              (12U)\n#define OPAMP2_CSR_CALON_Msk              (0x1U << OPAMP2_CSR_CALON_Pos)       /*!< 0x00001000 */\n#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */\n#define OPAMP2_CSR_CALSEL_Pos             (13U)\n#define OPAMP2_CSR_CALSEL_Msk             (0x1U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */\n#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */\n#define OPAMP2_CSR_USERTRIM_Pos           (14U)\n#define OPAMP2_CSR_USERTRIM_Msk           (0x1U << OPAMP2_CSR_USERTRIM_Pos)    /*!< 0x00004000 */\n#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */\n#define OPAMP2_CSR_CALOUT_Pos             (15U)\n#define OPAMP2_CSR_CALOUT_Msk             (0x1U << OPAMP2_CSR_CALOUT_Pos)      /*!< 0x00008000 */\n#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */\n\n/*******************  Bit definition for OPAMP_OTR register  ******************/\n#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)\n#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */\n#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */\n#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)\n#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */\n#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP1_OTR register  ******************/\n#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)\n#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\n#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)\n#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP2_OTR register  ******************/\n#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)\n#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */\n#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)\n#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP_LPOTR register  ****************/\n#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)\n#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */\n#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)\n#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP1_LPOTR register  ****************/\n#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)\n#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\n#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)\n#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\n\n/*******************  Bit definition for OPAMP2_LPOTR register  ****************/\n#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)\n#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */\n#define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */\n#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)\n#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */\n#define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          Touch Sensing Controller (TSC)                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TSC_CR register  *********************/\n#define TSC_CR_TSCE_Pos          (0U)\n#define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */\n#define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */\n#define TSC_CR_START_Pos         (1U)\n#define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */\n#define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */\n#define TSC_CR_AM_Pos            (2U)\n#define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */\n#define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */\n#define TSC_CR_SYNCPOL_Pos       (3U)\n#define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */\n#define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */\n#define TSC_CR_IODEF_Pos         (4U)\n#define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */\n#define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */\n\n#define TSC_CR_MCV_Pos           (5U)\n#define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */\n#define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */\n#define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */\n#define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */\n#define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */\n\n#define TSC_CR_PGPSC_Pos         (12U)\n#define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */\n#define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */\n#define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */\n#define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */\n#define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */\n\n#define TSC_CR_SSPSC_Pos         (15U)\n#define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */\n#define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */\n#define TSC_CR_SSE_Pos           (16U)\n#define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */\n#define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */\n\n#define TSC_CR_SSD_Pos           (17U)\n#define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */\n#define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */\n#define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */\n#define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */\n#define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */\n#define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */\n#define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */\n#define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */\n#define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */\n\n#define TSC_CR_CTPL_Pos          (24U)\n#define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */\n#define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */\n#define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */\n#define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */\n#define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */\n#define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */\n\n#define TSC_CR_CTPH_Pos          (28U)\n#define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */\n#define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */\n#define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */\n#define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */\n#define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */\n#define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */\n\n/*******************  Bit definition for TSC_IER register  ********************/\n#define TSC_IER_EOAIE_Pos        (0U)\n#define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */\n#define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */\n#define TSC_IER_MCEIE_Pos        (1U)\n#define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */\n#define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */\n\n/*******************  Bit definition for TSC_ICR register  ********************/\n#define TSC_ICR_EOAIC_Pos        (0U)\n#define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */\n#define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */\n#define TSC_ICR_MCEIC_Pos        (1U)\n#define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */\n#define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */\n\n/*******************  Bit definition for TSC_ISR register  ********************/\n#define TSC_ISR_EOAF_Pos         (0U)\n#define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */\n#define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */\n#define TSC_ISR_MCEF_Pos         (1U)\n#define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */\n#define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */\n\n/*******************  Bit definition for TSC_IOHCR register  ******************/\n#define TSC_IOHCR_G1_IO1_Pos     (0U)\n#define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */\n#define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G1_IO2_Pos     (1U)\n#define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */\n#define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G1_IO3_Pos     (2U)\n#define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */\n#define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G1_IO4_Pos     (3U)\n#define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */\n#define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G2_IO1_Pos     (4U)\n#define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */\n#define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G2_IO2_Pos     (5U)\n#define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */\n#define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G2_IO3_Pos     (6U)\n#define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */\n#define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G2_IO4_Pos     (7U)\n#define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */\n#define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G3_IO1_Pos     (8U)\n#define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */\n#define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G3_IO2_Pos     (9U)\n#define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */\n#define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G3_IO3_Pos     (10U)\n#define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */\n#define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G3_IO4_Pos     (11U)\n#define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */\n#define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G4_IO1_Pos     (12U)\n#define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */\n#define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G4_IO2_Pos     (13U)\n#define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */\n#define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G4_IO3_Pos     (14U)\n#define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */\n#define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G4_IO4_Pos     (15U)\n#define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */\n#define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G5_IO1_Pos     (16U)\n#define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */\n#define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G5_IO2_Pos     (17U)\n#define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */\n#define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G5_IO3_Pos     (18U)\n#define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */\n#define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G5_IO4_Pos     (19U)\n#define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */\n#define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G6_IO1_Pos     (20U)\n#define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */\n#define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G6_IO2_Pos     (21U)\n#define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */\n#define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G6_IO3_Pos     (22U)\n#define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */\n#define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G6_IO4_Pos     (23U)\n#define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */\n#define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G7_IO1_Pos     (24U)\n#define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */\n#define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G7_IO2_Pos     (25U)\n#define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */\n#define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G7_IO3_Pos     (26U)\n#define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */\n#define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G7_IO4_Pos     (27U)\n#define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */\n#define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G8_IO1_Pos     (28U)\n#define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */\n#define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G8_IO2_Pos     (29U)\n#define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */\n#define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G8_IO3_Pos     (30U)\n#define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */\n#define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */\n#define TSC_IOHCR_G8_IO4_Pos     (31U)\n#define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */\n#define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */\n\n/*******************  Bit definition for TSC_IOASCR register  *****************/\n#define TSC_IOASCR_G1_IO1_Pos    (0U)\n#define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */\n#define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */\n#define TSC_IOASCR_G1_IO2_Pos    (1U)\n#define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */\n#define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */\n#define TSC_IOASCR_G1_IO3_Pos    (2U)\n#define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */\n#define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */\n#define TSC_IOASCR_G1_IO4_Pos    (3U)\n#define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */\n#define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */\n#define TSC_IOASCR_G2_IO1_Pos    (4U)\n#define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */\n#define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */\n#define TSC_IOASCR_G2_IO2_Pos    (5U)\n#define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */\n#define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */\n#define TSC_IOASCR_G2_IO3_Pos    (6U)\n#define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */\n#define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */\n#define TSC_IOASCR_G2_IO4_Pos    (7U)\n#define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */\n#define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */\n#define TSC_IOASCR_G3_IO1_Pos    (8U)\n#define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */\n#define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */\n#define TSC_IOASCR_G3_IO2_Pos    (9U)\n#define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */\n#define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */\n#define TSC_IOASCR_G3_IO3_Pos    (10U)\n#define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */\n#define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */\n#define TSC_IOASCR_G3_IO4_Pos    (11U)\n#define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */\n#define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */\n#define TSC_IOASCR_G4_IO1_Pos    (12U)\n#define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */\n#define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */\n#define TSC_IOASCR_G4_IO2_Pos    (13U)\n#define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */\n#define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */\n#define TSC_IOASCR_G4_IO3_Pos    (14U)\n#define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */\n#define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */\n#define TSC_IOASCR_G4_IO4_Pos    (15U)\n#define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */\n#define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */\n#define TSC_IOASCR_G5_IO1_Pos    (16U)\n#define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */\n#define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */\n#define TSC_IOASCR_G5_IO2_Pos    (17U)\n#define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */\n#define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */\n#define TSC_IOASCR_G5_IO3_Pos    (18U)\n#define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */\n#define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */\n#define TSC_IOASCR_G5_IO4_Pos    (19U)\n#define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */\n#define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */\n#define TSC_IOASCR_G6_IO1_Pos    (20U)\n#define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */\n#define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */\n#define TSC_IOASCR_G6_IO2_Pos    (21U)\n#define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */\n#define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */\n#define TSC_IOASCR_G6_IO3_Pos    (22U)\n#define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */\n#define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */\n#define TSC_IOASCR_G6_IO4_Pos    (23U)\n#define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */\n#define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */\n#define TSC_IOASCR_G7_IO1_Pos    (24U)\n#define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */\n#define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */\n#define TSC_IOASCR_G7_IO2_Pos    (25U)\n#define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */\n#define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */\n#define TSC_IOASCR_G7_IO3_Pos    (26U)\n#define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */\n#define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */\n#define TSC_IOASCR_G7_IO4_Pos    (27U)\n#define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */\n#define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */\n#define TSC_IOASCR_G8_IO1_Pos    (28U)\n#define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */\n#define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */\n#define TSC_IOASCR_G8_IO2_Pos    (29U)\n#define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */\n#define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */\n#define TSC_IOASCR_G8_IO3_Pos    (30U)\n#define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */\n#define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */\n#define TSC_IOASCR_G8_IO4_Pos    (31U)\n#define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */\n#define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */\n\n/*******************  Bit definition for TSC_IOSCR register  ******************/\n#define TSC_IOSCR_G1_IO1_Pos     (0U)\n#define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */\n#define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */\n#define TSC_IOSCR_G1_IO2_Pos     (1U)\n#define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */\n#define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */\n#define TSC_IOSCR_G1_IO3_Pos     (2U)\n#define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */\n#define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */\n#define TSC_IOSCR_G1_IO4_Pos     (3U)\n#define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */\n#define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */\n#define TSC_IOSCR_G2_IO1_Pos     (4U)\n#define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */\n#define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */\n#define TSC_IOSCR_G2_IO2_Pos     (5U)\n#define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */\n#define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */\n#define TSC_IOSCR_G2_IO3_Pos     (6U)\n#define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */\n#define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */\n#define TSC_IOSCR_G2_IO4_Pos     (7U)\n#define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */\n#define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */\n#define TSC_IOSCR_G3_IO1_Pos     (8U)\n#define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */\n#define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */\n#define TSC_IOSCR_G3_IO2_Pos     (9U)\n#define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */\n#define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */\n#define TSC_IOSCR_G3_IO3_Pos     (10U)\n#define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */\n#define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */\n#define TSC_IOSCR_G3_IO4_Pos     (11U)\n#define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */\n#define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */\n#define TSC_IOSCR_G4_IO1_Pos     (12U)\n#define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */\n#define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */\n#define TSC_IOSCR_G4_IO2_Pos     (13U)\n#define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */\n#define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */\n#define TSC_IOSCR_G4_IO3_Pos     (14U)\n#define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */\n#define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */\n#define TSC_IOSCR_G4_IO4_Pos     (15U)\n#define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */\n#define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */\n#define TSC_IOSCR_G5_IO1_Pos     (16U)\n#define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */\n#define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */\n#define TSC_IOSCR_G5_IO2_Pos     (17U)\n#define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */\n#define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */\n#define TSC_IOSCR_G5_IO3_Pos     (18U)\n#define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */\n#define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */\n#define TSC_IOSCR_G5_IO4_Pos     (19U)\n#define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */\n#define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */\n#define TSC_IOSCR_G6_IO1_Pos     (20U)\n#define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */\n#define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */\n#define TSC_IOSCR_G6_IO2_Pos     (21U)\n#define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */\n#define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */\n#define TSC_IOSCR_G6_IO3_Pos     (22U)\n#define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */\n#define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */\n#define TSC_IOSCR_G6_IO4_Pos     (23U)\n#define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */\n#define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */\n#define TSC_IOSCR_G7_IO1_Pos     (24U)\n#define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */\n#define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */\n#define TSC_IOSCR_G7_IO2_Pos     (25U)\n#define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */\n#define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */\n#define TSC_IOSCR_G7_IO3_Pos     (26U)\n#define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */\n#define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */\n#define TSC_IOSCR_G7_IO4_Pos     (27U)\n#define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */\n#define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */\n#define TSC_IOSCR_G8_IO1_Pos     (28U)\n#define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */\n#define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */\n#define TSC_IOSCR_G8_IO2_Pos     (29U)\n#define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */\n#define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */\n#define TSC_IOSCR_G8_IO3_Pos     (30U)\n#define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */\n#define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */\n#define TSC_IOSCR_G8_IO4_Pos     (31U)\n#define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */\n#define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */\n\n/*******************  Bit definition for TSC_IOCCR register  ******************/\n#define TSC_IOCCR_G1_IO1_Pos     (0U)\n#define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */\n#define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */\n#define TSC_IOCCR_G1_IO2_Pos     (1U)\n#define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */\n#define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */\n#define TSC_IOCCR_G1_IO3_Pos     (2U)\n#define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */\n#define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */\n#define TSC_IOCCR_G1_IO4_Pos     (3U)\n#define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */\n#define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */\n#define TSC_IOCCR_G2_IO1_Pos     (4U)\n#define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */\n#define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */\n#define TSC_IOCCR_G2_IO2_Pos     (5U)\n#define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */\n#define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */\n#define TSC_IOCCR_G2_IO3_Pos     (6U)\n#define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */\n#define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */\n#define TSC_IOCCR_G2_IO4_Pos     (7U)\n#define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */\n#define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */\n#define TSC_IOCCR_G3_IO1_Pos     (8U)\n#define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */\n#define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */\n#define TSC_IOCCR_G3_IO2_Pos     (9U)\n#define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */\n#define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */\n#define TSC_IOCCR_G3_IO3_Pos     (10U)\n#define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */\n#define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */\n#define TSC_IOCCR_G3_IO4_Pos     (11U)\n#define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */\n#define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */\n#define TSC_IOCCR_G4_IO1_Pos     (12U)\n#define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */\n#define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */\n#define TSC_IOCCR_G4_IO2_Pos     (13U)\n#define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */\n#define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */\n#define TSC_IOCCR_G4_IO3_Pos     (14U)\n#define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */\n#define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */\n#define TSC_IOCCR_G4_IO4_Pos     (15U)\n#define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */\n#define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */\n#define TSC_IOCCR_G5_IO1_Pos     (16U)\n#define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */\n#define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */\n#define TSC_IOCCR_G5_IO2_Pos     (17U)\n#define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */\n#define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */\n#define TSC_IOCCR_G5_IO3_Pos     (18U)\n#define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */\n#define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */\n#define TSC_IOCCR_G5_IO4_Pos     (19U)\n#define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */\n#define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */\n#define TSC_IOCCR_G6_IO1_Pos     (20U)\n#define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */\n#define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */\n#define TSC_IOCCR_G6_IO2_Pos     (21U)\n#define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */\n#define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */\n#define TSC_IOCCR_G6_IO3_Pos     (22U)\n#define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */\n#define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */\n#define TSC_IOCCR_G6_IO4_Pos     (23U)\n#define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */\n#define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */\n#define TSC_IOCCR_G7_IO1_Pos     (24U)\n#define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */\n#define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */\n#define TSC_IOCCR_G7_IO2_Pos     (25U)\n#define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */\n#define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */\n#define TSC_IOCCR_G7_IO3_Pos     (26U)\n#define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */\n#define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */\n#define TSC_IOCCR_G7_IO4_Pos     (27U)\n#define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */\n#define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */\n#define TSC_IOCCR_G8_IO1_Pos     (28U)\n#define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */\n#define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */\n#define TSC_IOCCR_G8_IO2_Pos     (29U)\n#define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */\n#define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */\n#define TSC_IOCCR_G8_IO3_Pos     (30U)\n#define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */\n#define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */\n#define TSC_IOCCR_G8_IO4_Pos     (31U)\n#define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */\n#define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */\n\n/*******************  Bit definition for TSC_IOGCSR register  *****************/\n#define TSC_IOGCSR_G1E_Pos       (0U)\n#define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */\n#define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */\n#define TSC_IOGCSR_G2E_Pos       (1U)\n#define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */\n#define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */\n#define TSC_IOGCSR_G3E_Pos       (2U)\n#define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */\n#define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */\n#define TSC_IOGCSR_G4E_Pos       (3U)\n#define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */\n#define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */\n#define TSC_IOGCSR_G5E_Pos       (4U)\n#define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */\n#define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */\n#define TSC_IOGCSR_G6E_Pos       (5U)\n#define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */\n#define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */\n#define TSC_IOGCSR_G7E_Pos       (6U)\n#define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */\n#define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */\n#define TSC_IOGCSR_G8E_Pos       (7U)\n#define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */\n#define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */\n#define TSC_IOGCSR_G1S_Pos       (16U)\n#define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */\n#define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */\n#define TSC_IOGCSR_G2S_Pos       (17U)\n#define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */\n#define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */\n#define TSC_IOGCSR_G3S_Pos       (18U)\n#define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */\n#define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */\n#define TSC_IOGCSR_G4S_Pos       (19U)\n#define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */\n#define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */\n#define TSC_IOGCSR_G5S_Pos       (20U)\n#define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */\n#define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */\n#define TSC_IOGCSR_G6S_Pos       (21U)\n#define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */\n#define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */\n#define TSC_IOGCSR_G7S_Pos       (22U)\n#define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */\n#define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */\n#define TSC_IOGCSR_G8S_Pos       (23U)\n#define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */\n#define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */\n\n/*******************  Bit definition for TSC_IOGXCR register  *****************/\n#define TSC_IOGXCR_CNT_Pos       (0U)\n#define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */\n#define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */\n\n/******************************************************************************/\n/*                                                                            */\n/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */\n/*                                                                            */\n/******************************************************************************/\n\n/*\n* @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)\n*/\n#define USART_TCBGT_SUPPORT\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_UE_Pos              (0U)\n#define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */\n#define USART_CR1_UESM_Pos            (1U)\n#define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */\n#define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */\n#define USART_CR1_RE_Pos              (2U)\n#define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */\n#define USART_CR1_TE_Pos              (3U)\n#define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */\n#define USART_CR1_IDLEIE_Pos          (4U)\n#define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */\n#define USART_CR1_RXNEIE_Pos          (5U)\n#define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */\n#define USART_CR1_TCIE_Pos            (6U)\n#define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)\n#define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */\n#define USART_CR1_PEIE_Pos            (8U)\n#define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */\n#define USART_CR1_PS_Pos              (9U)\n#define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */\n#define USART_CR1_PCE_Pos             (10U)\n#define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */\n#define USART_CR1_WAKE_Pos            (11U)\n#define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */\n#define USART_CR1_M_Pos               (12U)\n#define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */\n#define USART_CR1_M0_Pos              (12U)\n#define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */\n#define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */\n#define USART_CR1_MME_Pos             (13U)\n#define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */\n#define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */\n#define USART_CR1_CMIE_Pos            (14U)\n#define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */\n#define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */\n#define USART_CR1_OVER8_Pos           (15U)\n#define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */\n#define USART_CR1_DEDT_Pos            (16U)\n#define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */\n#define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\n#define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */\n#define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */\n#define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */\n#define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */\n#define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */\n#define USART_CR1_DEAT_Pos            (21U)\n#define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */\n#define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\n#define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */\n#define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */\n#define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */\n#define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */\n#define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */\n#define USART_CR1_RTOIE_Pos           (26U)\n#define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */\n#define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */\n#define USART_CR1_EOBIE_Pos           (27U)\n#define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */\n#define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */\n#define USART_CR1_M1_Pos              (28U)\n#define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */\n#define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADDM7_Pos           (4U)\n#define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */\n#define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */\n#define USART_CR2_LBDL_Pos            (5U)\n#define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */\n#define USART_CR2_LBDIE_Pos           (6U)\n#define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)\n#define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */\n#define USART_CR2_CPHA_Pos            (9U)\n#define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */\n#define USART_CR2_CPOL_Pos            (10U)\n#define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */\n#define USART_CR2_CLKEN_Pos           (11U)\n#define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */\n#define USART_CR2_STOP_Pos            (12U)\n#define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */\n#define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */\n#define USART_CR2_LINEN_Pos           (14U)\n#define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */\n#define USART_CR2_SWAP_Pos            (15U)\n#define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */\n#define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */\n#define USART_CR2_RXINV_Pos           (16U)\n#define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */\n#define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */\n#define USART_CR2_TXINV_Pos           (17U)\n#define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */\n#define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */\n#define USART_CR2_DATAINV_Pos         (18U)\n#define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */\n#define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */\n#define USART_CR2_MSBFIRST_Pos        (19U)\n#define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */\n#define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */\n#define USART_CR2_ABREN_Pos           (20U)\n#define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */\n#define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/\n#define USART_CR2_ABRMODE_Pos         (21U)\n#define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */\n#define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\n#define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */\n#define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */\n#define USART_CR2_RTOEN_Pos           (23U)\n#define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */\n#define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */\n#define USART_CR2_ADD_Pos             (24U)\n#define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)\n#define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */\n#define USART_CR3_IREN_Pos            (1U)\n#define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */\n#define USART_CR3_IRLP_Pos            (2U)\n#define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */\n#define USART_CR3_HDSEL_Pos           (3U)\n#define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */\n#define USART_CR3_NACK_Pos            (4U)\n#define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */\n#define USART_CR3_SCEN_Pos            (5U)\n#define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */\n#define USART_CR3_DMAR_Pos            (6U)\n#define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */\n#define USART_CR3_DMAT_Pos            (7U)\n#define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */\n#define USART_CR3_RTSE_Pos            (8U)\n#define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */\n#define USART_CR3_CTSE_Pos            (9U)\n#define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */\n#define USART_CR3_CTSIE_Pos           (10U)\n#define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */\n#define USART_CR3_ONEBIT_Pos          (11U)\n#define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */\n#define USART_CR3_OVRDIS_Pos          (12U)\n#define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */\n#define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */\n#define USART_CR3_DDRE_Pos            (13U)\n#define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */\n#define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */\n#define USART_CR3_DEM_Pos             (14U)\n#define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */\n#define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */\n#define USART_CR3_DEP_Pos             (15U)\n#define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */\n#define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */\n#define USART_CR3_SCARCNT_Pos         (17U)\n#define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */\n#define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\n#define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */\n#define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */\n#define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */\n#define USART_CR3_WUS_Pos             (20U)\n#define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */\n#define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */\n#define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */\n#define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */\n#define USART_CR3_WUFIE_Pos           (22U)\n#define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */\n#define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */\n#define USART_CR3_TCBGTIE_Pos         (24U)\n#define USART_CR3_TCBGTIE_Msk         (0x1U << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */\n#define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_FRACTION_Pos    (0U)\n#define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */\n#define USART_BRR_DIV_MANTISSA_Pos    (4U)\n#define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)\n#define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_GT_Pos             (8U)\n#define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */\n\n/*******************  Bit definition for USART_RTOR register  *****************/\n#define USART_RTOR_RTO_Pos            (0U)\n#define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */\n#define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */\n#define USART_RTOR_BLEN_Pos           (24U)\n#define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */\n#define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */\n\n/*******************  Bit definition for USART_RQR register  ******************/\n#define USART_RQR_ABRRQ_Pos           (0U)\n#define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */\n#define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */\n#define USART_RQR_SBKRQ_Pos           (1U)\n#define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */\n#define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */\n#define USART_RQR_MMRQ_Pos            (2U)\n#define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */\n#define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */\n#define USART_RQR_RXFRQ_Pos           (3U)\n#define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */\n#define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */\n#define USART_RQR_TXFRQ_Pos           (4U)\n#define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */\n#define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */\n\n/*******************  Bit definition for USART_ISR register  ******************/\n#define USART_ISR_PE_Pos              (0U)\n#define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */\n#define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */\n#define USART_ISR_FE_Pos              (1U)\n#define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */\n#define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */\n#define USART_ISR_NE_Pos              (2U)\n#define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */\n#define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise Error detected Flag */\n#define USART_ISR_ORE_Pos             (3U)\n#define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */\n#define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */\n#define USART_ISR_IDLE_Pos            (4U)\n#define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */\n#define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */\n#define USART_ISR_RXNE_Pos            (5U)\n#define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */\n#define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */\n#define USART_ISR_TC_Pos              (6U)\n#define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */\n#define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */\n#define USART_ISR_TXE_Pos             (7U)\n#define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */\n#define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */\n#define USART_ISR_LBDF_Pos            (8U)\n#define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */\n#define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */\n#define USART_ISR_CTSIF_Pos           (9U)\n#define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */\n#define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */\n#define USART_ISR_CTS_Pos             (10U)\n#define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */\n#define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */\n#define USART_ISR_RTOF_Pos            (11U)\n#define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */\n#define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */\n#define USART_ISR_EOBF_Pos            (12U)\n#define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */\n#define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */\n#define USART_ISR_ABRE_Pos            (14U)\n#define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */\n#define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */\n#define USART_ISR_ABRF_Pos            (15U)\n#define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */\n#define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */\n#define USART_ISR_BUSY_Pos            (16U)\n#define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */\n#define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */\n#define USART_ISR_CMF_Pos             (17U)\n#define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */\n#define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */\n#define USART_ISR_SBKF_Pos            (18U)\n#define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */\n#define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */\n#define USART_ISR_RWU_Pos             (19U)\n#define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */\n#define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */\n#define USART_ISR_WUF_Pos             (20U)\n#define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */\n#define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */\n#define USART_ISR_TEACK_Pos           (21U)\n#define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */\n#define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */\n#define USART_ISR_REACK_Pos           (22U)\n#define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */\n#define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */\n#define USART_ISR_TCBGT_Pos           (25U)\n#define USART_ISR_TCBGT_Msk           (0x1U << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */\n#define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */\n\n/*******************  Bit definition for USART_ICR register  ******************/\n#define USART_ICR_PECF_Pos            (0U)\n#define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */\n#define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */\n#define USART_ICR_FECF_Pos            (1U)\n#define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */\n#define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */\n#define USART_ICR_NECF_Pos            (2U)\n#define USART_ICR_NECF_Msk            (0x1U << USART_ICR_NECF_Pos)             /*!< 0x00000004 */\n#define USART_ICR_NECF                USART_ICR_NECF_Msk                       /*!< Noise Error detected Clear Flag */\n#define USART_ICR_ORECF_Pos           (3U)\n#define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */\n#define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */\n#define USART_ICR_IDLECF_Pos          (4U)\n#define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */\n#define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */\n#define USART_ICR_TCCF_Pos            (6U)\n#define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */\n#define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */\n#define USART_ICR_TCBGTCF_Pos         (7U)\n#define USART_ICR_TCBGTCF_Msk         (0x1U << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */\n#define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */\n#define USART_ICR_LBDCF_Pos           (8U)\n#define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */\n#define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */\n#define USART_ICR_CTSCF_Pos           (9U)\n#define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */\n#define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */\n#define USART_ICR_RTOCF_Pos           (11U)\n#define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */\n#define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */\n#define USART_ICR_EOBCF_Pos           (12U)\n#define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */\n#define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */\n#define USART_ICR_CMCF_Pos            (17U)\n#define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */\n#define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */\n#define USART_ICR_WUCF_Pos            (20U)\n#define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */\n#define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */\n\n/* Legacy defines */\n#define USART_ICR_NCF_Pos             USART_ICR_NECF_Pos\n#define USART_ICR_NCF_Msk             USART_ICR_NECF_Msk\n#define USART_ICR_NCF                 USART_ICR_NECF\n\n/*******************  Bit definition for USART_RDR register  ******************/\n#define USART_RDR_RDR_Pos             (0U)\n#define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */\n#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */\n\n/*******************  Bit definition for USART_TDR register  ******************/\n#define USART_TDR_TDR_Pos             (0U)\n#define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */\n#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */\n\n/******************************************************************************/\n/*                                                                            */\n/*           Single Wire Protocol Master Interface (SWPMI)                    */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for SWPMI_CR register   ********************/\n#define SWPMI_CR_RXDMA_Pos       (0U)\n#define SWPMI_CR_RXDMA_Msk       (0x1U << SWPMI_CR_RXDMA_Pos)                  /*!< 0x00000001 */\n#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */\n#define SWPMI_CR_TXDMA_Pos       (1U)\n#define SWPMI_CR_TXDMA_Msk       (0x1U << SWPMI_CR_TXDMA_Pos)                  /*!< 0x00000002 */\n#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */\n#define SWPMI_CR_RXMODE_Pos      (2U)\n#define SWPMI_CR_RXMODE_Msk      (0x1U << SWPMI_CR_RXMODE_Pos)                 /*!< 0x00000004 */\n#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */\n#define SWPMI_CR_TXMODE_Pos      (3U)\n#define SWPMI_CR_TXMODE_Msk      (0x1U << SWPMI_CR_TXMODE_Pos)                 /*!< 0x00000008 */\n#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */\n#define SWPMI_CR_LPBK_Pos        (4U)\n#define SWPMI_CR_LPBK_Msk        (0x1U << SWPMI_CR_LPBK_Pos)                   /*!< 0x00000010 */\n#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */\n#define SWPMI_CR_SWPACT_Pos      (5U)\n#define SWPMI_CR_SWPACT_Msk      (0x1U << SWPMI_CR_SWPACT_Pos)                 /*!< 0x00000020 */\n#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */\n#define SWPMI_CR_DEACT_Pos       (10U)\n#define SWPMI_CR_DEACT_Msk       (0x1U << SWPMI_CR_DEACT_Pos)                  /*!< 0x00000400 */\n#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */\n\n/*******************  Bit definition for SWPMI_BRR register  ********************/\n#define SWPMI_BRR_BR_Pos         (0U)\n#define SWPMI_BRR_BR_Msk         (0x3FU << SWPMI_BRR_BR_Pos)                   /*!< 0x0000003F */\n#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */\n\n/*******************  Bit definition for SWPMI_ISR register  ********************/\n#define SWPMI_ISR_RXBFF_Pos      (0U)\n#define SWPMI_ISR_RXBFF_Msk      (0x1U << SWPMI_ISR_RXBFF_Pos)                 /*!< 0x00000001 */\n#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */\n#define SWPMI_ISR_TXBEF_Pos      (1U)\n#define SWPMI_ISR_TXBEF_Msk      (0x1U << SWPMI_ISR_TXBEF_Pos)                 /*!< 0x00000002 */\n#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */\n#define SWPMI_ISR_RXBERF_Pos     (2U)\n#define SWPMI_ISR_RXBERF_Msk     (0x1U << SWPMI_ISR_RXBERF_Pos)                /*!< 0x00000004 */\n#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */\n#define SWPMI_ISR_RXOVRF_Pos     (3U)\n#define SWPMI_ISR_RXOVRF_Msk     (0x1U << SWPMI_ISR_RXOVRF_Pos)                /*!< 0x00000008 */\n#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */\n#define SWPMI_ISR_TXUNRF_Pos     (4U)\n#define SWPMI_ISR_TXUNRF_Msk     (0x1U << SWPMI_ISR_TXUNRF_Pos)                /*!< 0x00000010 */\n#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */\n#define SWPMI_ISR_RXNE_Pos       (5U)\n#define SWPMI_ISR_RXNE_Msk       (0x1U << SWPMI_ISR_RXNE_Pos)                  /*!< 0x00000020 */\n#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */\n#define SWPMI_ISR_TXE_Pos        (6U)\n#define SWPMI_ISR_TXE_Msk        (0x1U << SWPMI_ISR_TXE_Pos)                   /*!< 0x00000040 */\n#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */\n#define SWPMI_ISR_TCF_Pos        (7U)\n#define SWPMI_ISR_TCF_Msk        (0x1U << SWPMI_ISR_TCF_Pos)                   /*!< 0x00000080 */\n#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */\n#define SWPMI_ISR_SRF_Pos        (8U)\n#define SWPMI_ISR_SRF_Msk        (0x1U << SWPMI_ISR_SRF_Pos)                   /*!< 0x00000100 */\n#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */\n#define SWPMI_ISR_SUSP_Pos       (9U)\n#define SWPMI_ISR_SUSP_Msk       (0x1U << SWPMI_ISR_SUSP_Pos)                  /*!< 0x00000200 */\n#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */\n#define SWPMI_ISR_DEACTF_Pos     (10U)\n#define SWPMI_ISR_DEACTF_Msk     (0x1U << SWPMI_ISR_DEACTF_Pos)                /*!< 0x00000400 */\n#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */\n\n/*******************  Bit definition for SWPMI_ICR register  ********************/\n#define SWPMI_ICR_CRXBFF_Pos     (0U)\n#define SWPMI_ICR_CRXBFF_Msk     (0x1U << SWPMI_ICR_CRXBFF_Pos)                /*!< 0x00000001 */\n#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */\n#define SWPMI_ICR_CTXBEF_Pos     (1U)\n#define SWPMI_ICR_CTXBEF_Msk     (0x1U << SWPMI_ICR_CTXBEF_Pos)                /*!< 0x00000002 */\n#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */\n#define SWPMI_ICR_CRXBERF_Pos    (2U)\n#define SWPMI_ICR_CRXBERF_Msk    (0x1U << SWPMI_ICR_CRXBERF_Pos)               /*!< 0x00000004 */\n#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */\n#define SWPMI_ICR_CRXOVRF_Pos    (3U)\n#define SWPMI_ICR_CRXOVRF_Msk    (0x1U << SWPMI_ICR_CRXOVRF_Pos)               /*!< 0x00000008 */\n#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */\n#define SWPMI_ICR_CTXUNRF_Pos    (4U)\n#define SWPMI_ICR_CTXUNRF_Msk    (0x1U << SWPMI_ICR_CTXUNRF_Pos)               /*!< 0x00000010 */\n#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */\n#define SWPMI_ICR_CTCF_Pos       (7U)\n#define SWPMI_ICR_CTCF_Msk       (0x1U << SWPMI_ICR_CTCF_Pos)                  /*!< 0x00000080 */\n#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */\n#define SWPMI_ICR_CSRF_Pos       (8U)\n#define SWPMI_ICR_CSRF_Msk       (0x1U << SWPMI_ICR_CSRF_Pos)                  /*!< 0x00000100 */\n#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */\n\n/*******************  Bit definition for SWPMI_IER register  ********************/\n#define SWPMI_IER_SRIE_Pos       (8U)\n#define SWPMI_IER_SRIE_Msk       (0x1U << SWPMI_IER_SRIE_Pos)                  /*!< 0x00000100 */\n#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */\n#define SWPMI_IER_TCIE_Pos       (7U)\n#define SWPMI_IER_TCIE_Msk       (0x1U << SWPMI_IER_TCIE_Pos)                  /*!< 0x00000080 */\n#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */\n#define SWPMI_IER_TIE_Pos        (6U)\n#define SWPMI_IER_TIE_Msk        (0x1U << SWPMI_IER_TIE_Pos)                   /*!< 0x00000040 */\n#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */\n#define SWPMI_IER_RIE_Pos        (5U)\n#define SWPMI_IER_RIE_Msk        (0x1U << SWPMI_IER_RIE_Pos)                   /*!< 0x00000020 */\n#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */\n#define SWPMI_IER_TXUNRIE_Pos    (4U)\n#define SWPMI_IER_TXUNRIE_Msk    (0x1U << SWPMI_IER_TXUNRIE_Pos)               /*!< 0x00000010 */\n#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */\n#define SWPMI_IER_RXOVRIE_Pos    (3U)\n#define SWPMI_IER_RXOVRIE_Msk    (0x1U << SWPMI_IER_RXOVRIE_Pos)               /*!< 0x00000008 */\n#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */\n#define SWPMI_IER_RXBERIE_Pos    (2U)\n#define SWPMI_IER_RXBERIE_Msk    (0x1U << SWPMI_IER_RXBERIE_Pos)               /*!< 0x00000004 */\n#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */\n#define SWPMI_IER_TXBEIE_Pos     (1U)\n#define SWPMI_IER_TXBEIE_Msk     (0x1U << SWPMI_IER_TXBEIE_Pos)                /*!< 0x00000002 */\n#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */\n#define SWPMI_IER_RXBFIE_Pos     (0U)\n#define SWPMI_IER_RXBFIE_Msk     (0x1U << SWPMI_IER_RXBFIE_Pos)                /*!< 0x00000001 */\n#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */\n\n/*******************  Bit definition for SWPMI_RFL register  ********************/\n#define SWPMI_RFL_RFL_Pos        (0U)\n#define SWPMI_RFL_RFL_Msk        (0x1FU << SWPMI_RFL_RFL_Pos)                  /*!< 0x0000001F */\n#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */\n#define SWPMI_RFL_RFL_0_1_Pos    (0U)\n#define SWPMI_RFL_RFL_0_1_Msk    (0x3U << SWPMI_RFL_RFL_0_1_Pos)               /*!< 0x00000003 */\n#define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */\n\n/*******************  Bit definition for SWPMI_TDR register  ********************/\n#define SWPMI_TDR_TD_Pos         (0U)\n#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */\n#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */\n\n/*******************  Bit definition for SWPMI_RDR register  ********************/\n#define SWPMI_RDR_RD_Pos         (0U)\n#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */\n#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */\n\n/*******************  Bit definition for SWPMI_OR register  ********************/\n#define SWPMI_OR_TBYP_Pos        (0U)\n#define SWPMI_OR_TBYP_Msk        (0x1U << SWPMI_OR_TBYP_Pos)                   /*!< 0x00000001 */\n#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */\n#define SWPMI_OR_CLASS_Pos       (1U)\n#define SWPMI_OR_CLASS_Msk       (0x1U << SWPMI_OR_CLASS_Pos)                  /*!< 0x00000002 */\n#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 VREFBUF                                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for VREFBUF_CSR register  ****************/\n#define VREFBUF_CSR_ENVR_Pos    (0U)\n#define VREFBUF_CSR_ENVR_Msk    (0x1U << VREFBUF_CSR_ENVR_Pos)                 /*!< 0x00000001 */\n#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */\n#define VREFBUF_CSR_HIZ_Pos     (1U)\n#define VREFBUF_CSR_HIZ_Msk     (0x1U << VREFBUF_CSR_HIZ_Pos)                  /*!< 0x00000002 */\n#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */\n#define VREFBUF_CSR_VRS_Pos     (2U)\n#define VREFBUF_CSR_VRS_Msk     (0x1U << VREFBUF_CSR_VRS_Pos)                  /*!< 0x00000004 */\n#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */\n#define VREFBUF_CSR_VRR_Pos     (3U)\n#define VREFBUF_CSR_VRR_Msk     (0x1U << VREFBUF_CSR_VRR_Pos)                  /*!< 0x00000008 */\n#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */\n\n/*******************  Bit definition for VREFBUF_CCR register  ******************/\n#define VREFBUF_CCR_TRIM_Pos    (0U)\n#define VREFBUF_CCR_TRIM_Msk    (0x3FU << VREFBUF_CCR_TRIM_Pos)                /*!< 0x0000003F */\n#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)\n#define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */\n#define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */\n#define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */\n#define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */\n#define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */\n#define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */\n#define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */\n\n#define WWDG_CR_WDGA_Pos        (7U)\n#define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)\n#define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */\n#define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */\n#define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */\n#define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */\n#define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */\n#define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */\n#define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */\n\n#define WWDG_CFR_WDGTB_Pos      (7U)\n#define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */\n#define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */\n\n#define WWDG_CFR_EWI_Pos        (9U)\n#define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)\n#define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 Debug MCU                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos               (0U)\n#define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk\n#define DBGMCU_IDCODE_REV_ID_Pos               (16U)\n#define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk\n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)\n#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk\n#define DBGMCU_CR_DBG_STOP_Pos                 (1U)\n#define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk\n#define DBGMCU_CR_DBG_STANDBY_Pos              (2U)\n#define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk\n#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)\n#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk\n\n#define DBGMCU_CR_TRACE_MODE_Pos               (6U)\n#define DBGMCU_CR_TRACE_MODE_Msk               (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk\n#define DBGMCU_CR_TRACE_MODE_0                 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/\n#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)\n#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)\n#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)\n#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)\n#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)\n#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)\n#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)\n#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)\n#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)\n#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)\n#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)\n#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)\n#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)\n#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_CAN2_STOP_Pos      (26U)\n#define DBGMCU_APB1FZR1_DBG_CAN2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1FZR1_DBG_CAN2_STOP          DBGMCU_APB1FZR1_DBG_CAN2_STOP_Msk\n#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)\n#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */\n#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk\n\n/********************  Bit definition for DBGMCU_APB1FZR2 register  **********/\n#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos      (1U)\n#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk      (0x1U << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1FZR2_DBG_I2C4_STOP          DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk\n#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)\n#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk\n\n/********************  Bit definition for DBGMCU_APB2FZ register  ************/\n#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)\n#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk\n#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)\n#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */\n#define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk\n#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)\n#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk\n#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)\n#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk\n#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)\n#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk\n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ********************/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)\n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)\n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)\n#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */\n#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)\n#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\n#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\n#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)\n#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)\n#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\n#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */\n#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)\n#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */\n#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)\n#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */\n#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)\n#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!<  B-session valid*/\n\n/********************  Bit definition for USB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)\n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)\n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)\n#define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)\n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n#define USB_OTG_DCFG_DAD_Pos                     (4U)\n#define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)\n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)\n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)\n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)\n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)\n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)\n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)\n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)\n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)\n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)\n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)\n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)\n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)\n#define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)\n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)\n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)\n#define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)\n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)\n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)\n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)\n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)\n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)\n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)\n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)\n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)\n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)\n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)\n#define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)\n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)\n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)\n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)\n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)\n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)\n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)\n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)\n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)\n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)\n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)\n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)\n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)\n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)\n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)\n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)\n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)\n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)\n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)\n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)\n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)\n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)\n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)\n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)\n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)\n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)\n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)\n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)\n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)\n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)\n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)\n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)\n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)\n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)\n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)\n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)\n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)\n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)\n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)\n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)\n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)\n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)\n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)\n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)\n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)\n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */\n\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)\n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)\n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)\n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)\n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)\n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)\n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)\n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)\n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)\n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)\n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)\n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)\n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)\n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)\n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)\n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)\n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)\n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)\n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)\n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)\n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */\n#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)\n#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)\n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)\n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)\n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)\n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)\n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)\n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)\n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)\n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)\n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)\n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)\n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)\n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)\n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)\n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)\n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)\n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)\n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)\n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)\n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)\n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)\n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)\n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)\n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)\n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)\n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */\n#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)\n#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\n#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)\n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)\n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)\n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)\n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)\n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)\n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)\n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)\n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)\n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)\n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)\n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)\n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)\n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition for OTG register  ********************/\n\n#define USB_OTG_CHNUM_Pos                        (0U)\n#define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)\n#define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n#define USB_OTG_DPID_Pos                         (15U)\n#define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n#define USB_OTG_PKTSTS_Pos                       (17U)\n#define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n#define USB_OTG_EPNUM_Pos                        (0U)\n#define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_FRMNUM_Pos                       (21U)\n#define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)\n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)\n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)\n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)\n#define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth */\n#define USB_OTG_TX0FSA_Pos                       (0U)\n#define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address */\n#define USB_OTG_TX0FD_Pos                        (16U)\n#define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)\n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ***************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)\n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)\n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)\n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)\n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)\n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)\n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)\n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)\n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_DCDET_Pos                  (0U)\n#define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\n#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */\n#define USB_OTG_GCCFG_PDET_Pos                   (1U)\n#define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */\n#define USB_OTG_GCCFG_SDET_Pos                   (2U)\n#define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */\n#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)\n#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\n#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)\n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)\n#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */\n#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)\n#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/\n#define USB_OTG_GCCFG_PDEN_Pos                   (19U)\n#define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/\n#define USB_OTG_GCCFG_SDEN_Pos                   (20U)\n#define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */\n#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)\n#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */\n\n/********************  Bit definition for USB_OTG_GPWRDN) register  ********************/\n#define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)\n#define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */\n#define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */\n\n/********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)\n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n\n/********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/\n#define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)\n#define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */\n#define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk   /* LPM mode specified for Mode of Operation */\n\n/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/\n#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)\n#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\n#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /* Enable best effort service latency */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)\n#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\n#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */\n#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)\n#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /* Send LPM transaction */\n#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)\n#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\n#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /* LPM retry count */\n#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)\n#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /* LPMCHIDX: */\n#define USB_OTG_GLPMCFG_L1ResumeOK_Pos           (16U)\n#define USB_OTG_GLPMCFG_L1ResumeOK_Msk           (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */\n#define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */\n#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)\n#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /* Port sleep status */\n#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)\n#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\n#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /* LPM response */\n#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)\n#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\n#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /* L1 deep sleep enable */\n#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)\n#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\n#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /* BESL threshold */\n#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)\n#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /* L1 shallow sleep enable */\n#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)\n#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\n#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /* bRemoteWake value received with last ACKed LPM Token */\n#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)\n#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\n#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /* BESL value received with last ACKed LPM Token  */\n#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)\n#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\n#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /* LPM Token acknowledge enable*/\n#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)\n#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\n#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /* LPM support enable  */\n\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)\n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)\n#define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)\n#define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)\n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)\n#define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)\n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)\n#define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)\n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)\n#define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)\n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)\n#define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)\n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)\n#define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */\n#define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)\n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)\n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)\n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)\n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)\n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)\n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)\n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)\n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)\n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)\n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)\n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)\n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)\n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)\n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)\n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)\n#define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)\n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)\n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)\n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)\n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)\n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)\n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)\n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)\n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)\n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)\n#define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)\n#define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)\n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)\n#define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)\n#define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)\n#define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)\n#define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)\n#define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)\n#define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)\n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)\n#define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)\n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)\n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)\n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)\n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)\n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)\n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)\n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition for USB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)\n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)\n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)\n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)\n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)\n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)\n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)\n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)\n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)\n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)\n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)\n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)\n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)\n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)\n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)\n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)\n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)\n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)\n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)\n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)\n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)\n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)\n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)\n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)\n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)\n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)\n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)\n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)\n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)\n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)\n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)\n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)\n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)\n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)\n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)\n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)\n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)\n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)\n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)\n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)\n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)\n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)\n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)\n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\n\n/******************************** CAN Instances ******************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n\n/******************************** COMP Instances ******************************/\n#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \\\n                                        ((INSTANCE) == COMP2))\n\n#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)\n\n/******************** COMP Instances with window mode capability **************/\n#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)\n\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n/****************************** DFSDM Instances *******************************/\n#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \\\n                                                ((INSTANCE) == DFSDM1_Filter1) || \\\n                                                ((INSTANCE) == DFSDM1_Filter2) || \\\n                                                ((INSTANCE) == DFSDM1_Filter3))\n\n#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel1) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel2) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel3) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel4) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel5) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel6) || \\\n                                                 ((INSTANCE) == DFSDM1_Channel7))\n\n/******************************* DCMI Instances *******************************/\n#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)\n\n/******************************* DMA2D Instances *******************************/\n#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \\\n                                       ((INSTANCE) == DMA1_Channel2) || \\\n                                       ((INSTANCE) == DMA1_Channel3) || \\\n                                       ((INSTANCE) == DMA1_Channel4) || \\\n                                       ((INSTANCE) == DMA1_Channel5) || \\\n                                       ((INSTANCE) == DMA1_Channel6) || \\\n                                       ((INSTANCE) == DMA1_Channel7) || \\\n                                       ((INSTANCE) == DMA2_Channel1) || \\\n                                       ((INSTANCE) == DMA2_Channel2) || \\\n                                       ((INSTANCE) == DMA2_Channel3) || \\\n                                       ((INSTANCE) == DMA2_Channel4) || \\\n                                       ((INSTANCE) == DMA2_Channel5) || \\\n                                       ((INSTANCE) == DMA2_Channel6) || \\\n                                       ((INSTANCE) == DMA2_Channel7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH) || \\\n                                        ((INSTANCE) == GPIOI))\n\n/******************************* GPIO AF Instances ****************************/\n/* On L4, all GPIO Bank support AF */\n#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)\n\n/**************************** GPIO Lock Instances *****************************/\n/* On L4, all GPIO Bank support the Lock mechanism */\n#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3) || \\\n                                       ((INSTANCE) == I2C4))\n\n/****************** I2C Instances : wakeup capability from stop modes *********/\n#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)\n\n/******************************* LCD Instances ********************************/\n#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)\n\n/******************************* HCD Instances *******************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)\n\n/****************************** OPAMP Instances *******************************/\n#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \\\n                                         ((INSTANCE) == OPAMP2))\n\n#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)\n\n/******************************* PCD Instances *******************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)\n\n/******************************* QSPI Instances *******************************/\n#define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/******************************** SAI Instances *******************************/\n#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \\\n                                       ((INSTANCE) == SAI1_Block_B) || \\\n                                       ((INSTANCE) == SAI2_Block_A) || \\\n                                       ((INSTANCE) == SAI2_Block_B))\n\n/****************************** SDMMC Instances *******************************/\n#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)\n\n/****************************** SMBUS Instances *******************************/\n#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                         ((INSTANCE) == I2C2) || \\\n                                         ((INSTANCE) == I2C3) || \\\n                                         ((INSTANCE) == I2C4))\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n/******************************** SWPMI Instances *****************************/\n#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)\n\n/****************** LPTIM Instances : All supported instances *****************/\n#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \\\n                                         ((INSTANCE) == LPTIM2))\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM6)   || \\\n                                         ((INSTANCE) == TIM7)   || \\\n                                         ((INSTANCE) == TIM8)   || \\\n                                         ((INSTANCE) == TIM15)  || \\\n                                         ((INSTANCE) == TIM16)  || \\\n                                         ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting 32 bits counter ****************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \\\n                                               ((INSTANCE) == TIM5))\n\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\\n                                            ((INSTANCE) == TIM8)    || \\\n                                            ((INSTANCE) == TIM15)   || \\\n                                            ((INSTANCE) == TIM16)   || \\\n                                            ((INSTANCE) == TIM17))\n\n/************** TIM Instances : supporting Break source selection *************/\n#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                               ((INSTANCE) == TIM8)   || \\\n                                               ((INSTANCE) == TIM15)  || \\\n                                               ((INSTANCE) == TIM16)  || \\\n                                               ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting 2 break inputs *****************/\n#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\\n                                            ((INSTANCE) == TIM8))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8)   || \\\n                                         ((INSTANCE) == TIM15)  || \\\n                                         ((INSTANCE) == TIM16)  || \\\n                                         ((INSTANCE) == TIM17))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8)   || \\\n                                         ((INSTANCE) == TIM15))\n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM2)   || \\\n                                         ((INSTANCE) == TIM3)   || \\\n                                         ((INSTANCE) == TIM4)   || \\\n                                         ((INSTANCE) == TIM5)   || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : at least 5 capture/compare channels *******/\n#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : at least 6 capture/compare channels *******/\n#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM8)   || \\\n                                            ((INSTANCE) == TIM15)  || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/\n#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM2)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM4)   || \\\n                                            ((INSTANCE) == TIM5)   || \\\n                                            ((INSTANCE) == TIM6)   || \\\n                                            ((INSTANCE) == TIM7)   || \\\n                                            ((INSTANCE) == TIM8)   || \\\n                                            ((INSTANCE) == TIM15)  || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n\n/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM2)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM4)   || \\\n                                            ((INSTANCE) == TIM5)   || \\\n                                            ((INSTANCE) == TIM8)   || \\\n                                            ((INSTANCE) == TIM15)  || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM2)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM4)   || \\\n                                            ((INSTANCE) == TIM5)   || \\\n                                            ((INSTANCE) == TIM8)   || \\\n                                            ((INSTANCE) == TIM15)  || \\\n                                            ((INSTANCE) == TIM16)  || \\\n                                            ((INSTANCE) == TIM17))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM2) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM3) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM4) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM5) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM8) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_5) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_6)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM15) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM16) &&                 \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n     ||                                        \\\n     (((INSTANCE) == TIM17) &&                 \\\n      (((CHANNEL) == TIM_CHANNEL_1))))\n\n/****************** TIM Instances : supporting complementary output(s) ********/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM15) &&                   \\\n     ((CHANNEL) == TIM_CHANNEL_1))              \\\n    ||                                          \\\n    (((INSTANCE) == TIM16) &&                   \\\n     ((CHANNEL) == TIM_CHANNEL_1))              \\\n    ||                                          \\\n    (((INSTANCE) == TIM17) &&                   \\\n     ((CHANNEL) == TIM_CHANNEL_1)))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \\\n                                                    ((INSTANCE) == TIM2)    || \\\n                                                    ((INSTANCE) == TIM3)    || \\\n                                                    ((INSTANCE) == TIM4)    || \\\n                                                    ((INSTANCE) == TIM5)    || \\\n                                                    ((INSTANCE) == TIM8)    || \\\n                                                    ((INSTANCE) == TIM15)   || \\\n                                                    ((INSTANCE) == TIM16)   || \\\n                                                    ((INSTANCE) == TIM17))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM15))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM15))\n\n/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM15))\n\n/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\n#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                                     ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                                     ((INSTANCE) == TIM8)   || \\\n                                                     ((INSTANCE) == TIM15)  || \\\n                                                     ((INSTANCE) == TIM16)  || \\\n                                                     ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\\n                                                      ((INSTANCE) == TIM2)  || \\\n                                                      ((INSTANCE) == TIM3)  || \\\n                                                      ((INSTANCE) == TIM4)  || \\\n                                                      ((INSTANCE) == TIM5)  || \\\n                                                      ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \\\n                                                         ((INSTANCE) == TIM2)   || \\\n                                                         ((INSTANCE) == TIM3)   || \\\n                                                         ((INSTANCE) == TIM4)   || \\\n                                                         ((INSTANCE) == TIM5)   || \\\n                                                         ((INSTANCE) == TIM8))\n\n/**************** TIM Instances : external trigger input available ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \\\n                                            ((INSTANCE) == TIM2)  || \\\n                                            ((INSTANCE) == TIM3)  || \\\n                                            ((INSTANCE) == TIM4)  || \\\n                                            ((INSTANCE) == TIM5)  || \\\n                                            ((INSTANCE) == TIM8))\n\n/************* TIM Instances : supporting ETR source selection ***************/\n#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\\n                                             ((INSTANCE) == TIM2)  || \\\n                                             ((INSTANCE) == TIM3)  || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                            ((INSTANCE) == TIM2)  || \\\n                                            ((INSTANCE) == TIM3)  || \\\n                                            ((INSTANCE) == TIM4)  || \\\n                                            ((INSTANCE) == TIM5)  || \\\n                                            ((INSTANCE) == TIM6)  || \\\n                                            ((INSTANCE) == TIM7)  || \\\n                                            ((INSTANCE) == TIM8)  || \\\n                                            ((INSTANCE) == TIM15))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\\n                                            ((INSTANCE) == TIM2)  || \\\n                                            ((INSTANCE) == TIM3)  || \\\n                                            ((INSTANCE) == TIM4)  || \\\n                                            ((INSTANCE) == TIM5)  || \\\n                                            ((INSTANCE) == TIM8)  || \\\n                                            ((INSTANCE) == TIM15))\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \\\n                                            ((INSTANCE) == TIM2)  || \\\n                                            ((INSTANCE) == TIM3)  || \\\n                                            ((INSTANCE) == TIM8)  || \\\n                                            ((INSTANCE) == TIM15) || \\\n                                            ((INSTANCE) == TIM16) || \\\n                                            ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \\\n                                                       ((INSTANCE) == TIM8)  || \\\n                                                       ((INSTANCE) == TIM15) || \\\n                                                       ((INSTANCE) == TIM16) || \\\n                                                       ((INSTANCE) == TIM17))\n\n/****************** TIM Instances : supporting synchronization ****************/\n#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)\n\n/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\n#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \\\n                                            ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \\\n                                            ((INSTANCE) == TIM2)   || \\\n                                            ((INSTANCE) == TIM3)   || \\\n                                            ((INSTANCE) == TIM4)   || \\\n                                            ((INSTANCE) == TIM5)   || \\\n                                            ((INSTANCE) == TIM8)   || \\\n                                            ((INSTANCE) == TIM15))\n\n/****************** TIM Instances : Advanced timer instances *******************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \\\n                                                  ((INSTANCE) == TIM8))\n\n/****************************** TSC Instances *********************************/\n#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3))\n\n/******************** UART Instances : Asynchronous mode **********************/\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5))\n\n/****************** UART Instances : Auto Baud Rate detection ****************/\n#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                                            ((INSTANCE) == USART2) || \\\n                                                            ((INSTANCE) == USART3) || \\\n                                                            ((INSTANCE) == UART4)  || \\\n                                                            ((INSTANCE) == UART5))\n\n/****************** UART Instances : Driver Enable *****************/\n#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \\\n                                                      ((INSTANCE) == USART2) || \\\n                                                      ((INSTANCE) == USART3) || \\\n                                                      ((INSTANCE) == UART4)  || \\\n                                                      ((INSTANCE) == UART5)  || \\\n                                                      ((INSTANCE) == LPUART1))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\\n                                                 ((INSTANCE) == USART2) || \\\n                                                 ((INSTANCE) == USART3) || \\\n                                                 ((INSTANCE) == UART4)  || \\\n                                                 ((INSTANCE) == UART5)  || \\\n                                                 ((INSTANCE) == LPUART1))\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == UART4)  || \\\n                                           ((INSTANCE) == UART5)  || \\\n                                           ((INSTANCE) == LPUART1))\n\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\\n                                          ((INSTANCE) == USART2) || \\\n                                          ((INSTANCE) == USART3) || \\\n                                          ((INSTANCE) == UART4)  || \\\n                                          ((INSTANCE) == UART5))\n\n/******************** UART Instances : Wake-up from Stop mode **********************/\n#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \\\n                                                      ((INSTANCE) == USART2) || \\\n                                                      ((INSTANCE) == USART3) || \\\n                                                      ((INSTANCE) == UART4)  || \\\n                                                      ((INSTANCE) == UART5)  || \\\n                                                      ((INSTANCE) == LPUART1))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5))\n\n/********************* USART Instances : Smard card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3))\n\n/******************** LPUART Instance *****************************************/\n#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/**\n  * @}\n  */\n\n\n/******************************************************************************/\n/*  For a painless codes migration between the STM32L4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32L4 Family                              */\n/******************************************************************************/\n\n/* Aliases for __IRQn */\n#define TIM6_IRQn                      TIM6_DAC_IRQn\n#define ADC1_IRQn                      ADC1_2_IRQn\n#define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn\n#define TIM8_IRQn                      TIM8_UP_IRQn\n#define HASH_RNG_IRQn                  RNG_IRQn\n#define HASH_CRS_IRQn                  CRS_IRQn\n#define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn\n#define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn\n#define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn\n#define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn\n\n/* Aliases for __IRQHandler */\n#define TIM6_IRQHandler                TIM6_DAC_IRQHandler\n#define ADC1_IRQHandler                ADC1_2_IRQHandler\n#define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler\n#define TIM8_IRQHandler                TIM8_UP_IRQHandler\n#define HASH_RNG_IRQHandler            RNG_IRQHandler\n#define HASH_CRS_IRQHandler            CRS_IRQHandler\n#define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler\n#define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler\n#define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler\n#define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32L496xx_H */\n\n/**\n  * @}\n  */\n\n  /**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.\n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The STM32L4xx device used in the target application\n  *              - To use or not the peripherals drivers in application code(i.e.\n  *                code will be based on direct access to peripherals registers\n  *                rather than drivers API), this option is controlled by\n  *                \"#define USE_HAL_DRIVER\"\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32l4xx\n  * @{\n  */\n\n#ifndef __STM32L4xx_H\n#define __STM32L4xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Library_configuration_section\n  * @{\n  */\n\n/**\n  * @brief STM32 Family\n  */\n#if !defined (STM32L4)\n#define STM32L4\n#endif /* STM32L4 */\n\n/* Uncomment the line below according to the target STM32L4 device used in your\n   application\n  */\n\n#if !defined (STM32L412xx) && !defined (STM32L422xx) && \\\n    !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \\\n    !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \\\n    !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \\\n    !defined (STM32L496xx) && !defined (STM32L4A6xx) && \\\n    !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx)\n  /* #define STM32L412xx */   /*!< STM32L412xx Devices */\n  /* #define STM32L422xx */   /*!< STM32L422xx Devices */\n  /* #define STM32L431xx */   /*!< STM32L431xx Devices */\n  /* #define STM32L432xx */   /*!< STM32L432xx Devices */\n  /* #define STM32L433xx */   /*!< STM32L433xx Devices */\n  /* #define STM32L442xx */   /*!< STM32L442xx Devices */\n  /* #define STM32L443xx */   /*!< STM32L443xx Devices */\n  /* #define STM32L451xx */   /*!< STM32L451xx Devices */\n  /* #define STM32L452xx */   /*!< STM32L452xx Devices */\n  /* #define STM32L462xx */   /*!< STM32L462xx Devices */\n  /* #define STM32L471xx */   /*!< STM32L471xx Devices */\n  /* #define STM32L475xx */   /*!< STM32L475xx Devices */\n  /* #define STM32L476xx */   /*!< STM32L476xx Devices */\n  /* #define STM32L485xx */   /*!< STM32L485xx Devices */\n  /* #define STM32L486xx */   /*!< STM32L486xx Devices */\n  /* #define STM32L496xx */   /*!< STM32L496xx Devices */\n  /* #define STM32L4A6xx */   /*!< STM32L4A6xx Devices */\n  /* #define STM32L4R5xx */   /*!< STM32L4R5xx Devices */\n  /* #define STM32L4R7xx */   /*!< STM32L4R7xx Devices */\n  /* #define STM32L4R9xx */   /*!< STM32L4R9xx Devices */\n  /* #define STM32L4S5xx */   /*!< STM32L4S5xx Devices */\n  /* #define STM32L4S7xx */   /*!< STM32L4S7xx Devices */\n  /* #define STM32L4S9xx */   /*!< STM32L4S9xx Devices */\n#endif\n\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will\n   be based on direct access to peripherals registers\n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS Device version number $VERSION$\n  */\n#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */\n#define __STM32L4_CMSIS_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */\n#define __STM32L4_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */\n#define __STM32L4_CMSIS_VERSION_RC     (0x01) /*!< [7:0]  release candidate */\n#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\\\n                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\\\n                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\\\n                                       |(__STM32L4_CMSIS_VERSION_RC))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32L412xx)\n  #include \"stm32l412xx.h\"\n#elif defined(STM32L422xx)\n  #include \"stm32l422xx.h\"\n#elif defined(STM32L431xx)\n  #include \"stm32l431xx.h\"\n#elif defined(STM32L432xx)\n  #include \"stm32l432xx.h\"\n#elif defined(STM32L433xx)\n  #include \"stm32l433xx.h\"\n#elif defined(STM32L442xx)\n  #include \"stm32l442xx.h\"\n#elif defined(STM32L443xx)\n  #include \"stm32l443xx.h\"\n#elif defined(STM32L451xx)\n  #include \"stm32l451xx.h\"\n#elif defined(STM32L452xx)\n  #include \"stm32l452xx.h\"\n#elif defined(STM32L462xx)\n  #include \"stm32l462xx.h\"\n#elif defined(STM32L471xx)\n  #include \"stm32l471xx.h\"\n#elif defined(STM32L475xx)\n  #include \"stm32l475xx.h\"\n#elif defined(STM32L476xx)\n  #include \"stm32l476xx.h\"\n#elif defined(STM32L485xx)\n  #include \"stm32l485xx.h\"\n#elif defined(STM32L486xx)\n  #include \"stm32l486xx.h\"\n#elif defined(STM32L496xx)\n  #include \"stm32l496xx.h\"\n#elif defined(STM32L4A6xx)\n  #include \"stm32l4a6xx.h\"\n#elif defined(STM32L4R5xx)\n  #include \"stm32l4r5xx.h\"\n#elif defined(STM32L4R7xx)\n  #include \"stm32l4r7xx.h\"\n#elif defined(STM32L4R9xx)\n  #include \"stm32l4r9xx.h\"\n#elif defined(STM32L4S5xx)\n  #include \"stm32l4s5xx.h\"\n#elif defined(STM32L4S7xx)\n  #include \"stm32l4s7xx.h\"\n#elif defined(STM32L4S9xx)\n  #include \"stm32l4s9xx.h\"\n#else\n #error \"Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */\ntypedef enum\n{\n  RESET = 0,\n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum\n{\n  DISABLE = 0,\n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  ERROR = 0,\n  SUCCESS = !ERROR\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))\n\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32l4xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32L4xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32l4xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32l4xx_system\n  * @{\n  */\n\n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32L4XX_H\n#define __SYSTEM_STM32L4XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/** @addtogroup STM32L4xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32L4xx_System_Exported_Variables\n  * @{\n  */\n  /* The SystemCoreClock variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nextern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */\n\nextern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\nextern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\nextern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Exported_Functions\n  * @{\n  */\n\nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32L4XX_H */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/arm_common_tables.h",
    "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\n*\n* $Date:        19. October 2015\n* $Revision: \tV.1.4.5 a\n*\n* Project: \t    CMSIS DSP Library\n* Title:\t    arm_common_tables.h\n*\n* Description:\tThis file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the\n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n#ifndef _ARM_COMMON_TABLES_H\n#define _ARM_COMMON_TABLES_H\n\n#include \"arm_math.h\"\n\nextern const uint16_t armBitRevTable[1024];\nextern const q15_t armRecipTableQ15[64];\nextern const q31_t armRecipTableQ31[64];\n/* extern const q31_t realCoefAQ31[1024]; */\n/* extern const q31_t realCoefBQ31[1024]; */\nextern const float32_t twiddleCoef_16[32];\nextern const float32_t twiddleCoef_32[64];\nextern const float32_t twiddleCoef_64[128];\nextern const float32_t twiddleCoef_128[256];\nextern const float32_t twiddleCoef_256[512];\nextern const float32_t twiddleCoef_512[1024];\nextern const float32_t twiddleCoef_1024[2048];\nextern const float32_t twiddleCoef_2048[4096];\nextern const float32_t twiddleCoef_4096[8192];\n#define twiddleCoef twiddleCoef_4096\nextern const q31_t twiddleCoef_16_q31[24];\nextern const q31_t twiddleCoef_32_q31[48];\nextern const q31_t twiddleCoef_64_q31[96];\nextern const q31_t twiddleCoef_128_q31[192];\nextern const q31_t twiddleCoef_256_q31[384];\nextern const q31_t twiddleCoef_512_q31[768];\nextern const q31_t twiddleCoef_1024_q31[1536];\nextern const q31_t twiddleCoef_2048_q31[3072];\nextern const q31_t twiddleCoef_4096_q31[6144];\nextern const q15_t twiddleCoef_16_q15[24];\nextern const q15_t twiddleCoef_32_q15[48];\nextern const q15_t twiddleCoef_64_q15[96];\nextern const q15_t twiddleCoef_128_q15[192];\nextern const q15_t twiddleCoef_256_q15[384];\nextern const q15_t twiddleCoef_512_q15[768];\nextern const q15_t twiddleCoef_1024_q15[1536];\nextern const q15_t twiddleCoef_2048_q15[3072];\nextern const q15_t twiddleCoef_4096_q15[6144];\nextern const float32_t twiddleCoef_rfft_32[32];\nextern const float32_t twiddleCoef_rfft_64[64];\nextern const float32_t twiddleCoef_rfft_128[128];\nextern const float32_t twiddleCoef_rfft_256[256];\nextern const float32_t twiddleCoef_rfft_512[512];\nextern const float32_t twiddleCoef_rfft_1024[1024];\nextern const float32_t twiddleCoef_rfft_2048[2048];\nextern const float32_t twiddleCoef_rfft_4096[4096];\n\n\n/* floating-point bit reversal tables */\n#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )\n#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )\n#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )\n#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )\n#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )\n#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )\n#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)\n#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)\n#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)\n\nextern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];\n\n/* fixed-point bit reversal tables */\n#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )\n#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )\n#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )\n#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )\n#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )\n#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )\n#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )\n#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\n#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\n\nextern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\n\n/* Tables for Fast Math Sine and Cosine */\nextern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\nextern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\nextern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\n\n#endif /*  ARM_COMMON_TABLES_H */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/arm_const_structs.h",
    "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2014 ARM Limited. All rights reserved.\n*\n* $Date:        19. March 2015\n* $Revision: \tV.1.4.5\n*\n* Project: \t    CMSIS DSP Library\n* Title:\t    arm_const_structs.h\n*\n* Description:\tThis file has constant structs that are initialized for\n*              user convenience.  For example, some can be given as\n*              arguments to the arm_cfft_f32() function.\n*\n* Target Processor: Cortex-M4/Cortex-M3\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the\n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n* -------------------------------------------------------------------- */\n\n#ifndef _ARM_CONST_STRUCTS_H\n#define _ARM_CONST_STRUCTS_H\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\n\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\n\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\n\n#endif\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/arm_math.h",
    "content": "/* ----------------------------------------------------------------------\n* Copyright (C) 2010-2015 ARM Limited. All rights reserved.\n*\n* $Date:        20. October 2015\n* $Revision:    V1.4.5 b\n*\n* Project:      CMSIS DSP Library\n* Title:        arm_math.h\n*\n* Description:  Public header file for CMSIS DSP Library\n*\n* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions\n* are met:\n*   - Redistributions of source code must retain the above copyright\n*     notice, this list of conditions and the following disclaimer.\n*   - Redistributions in binary form must reproduce the above copyright\n*     notice, this list of conditions and the following disclaimer in\n*     the documentation and/or other materials provided with the\n*     distribution.\n*   - Neither the name of ARM LIMITED nor the names of its contributors\n*     may be used to endorse or promote products derived from this\n*     software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n* POSSIBILITY OF SUCH DAMAGE.\n * -------------------------------------------------------------------- */\n\n/**\n   \\mainpage CMSIS DSP Software Library\n   *\n   * Introduction\n   * ------------\n   *\n   * This user manual describes the CMSIS DSP software library,\n   * a suite of common signal processing functions for use on Cortex-M processor based devices.\n   *\n   * The library is divided into a number of functions each covering a specific category:\n   * - Basic math functions\n   * - Fast math functions\n   * - Complex math functions\n   * - Filters\n   * - Matrix functions\n   * - Transforms\n   * - Motor control functions\n   * - Statistical functions\n   * - Support functions\n   * - Interpolation functions\n   *\n   * The library has separate functions for operating on 8-bit integers, 16-bit integers,\n   * 32-bit integer and 32-bit floating-point values.\n   *\n   * Using the Library\n   * ------------\n   *\n   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\n   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)\n   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)\n   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)\n   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)\n   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)\n   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)\n   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)\n   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)\n   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)\n   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)\n   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)\n   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)\n   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)\n   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)\n   *\n   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\n   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\n   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\n   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or\n   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\n   *\n   * Examples\n   * --------\n   *\n   * The library ships with a number of examples which demonstrate how to use the library functions.\n   *\n   * Toolchain Support\n   * ------------\n   *\n   * The library has been developed and tested with MDK-ARM version 5.14.0.0\n   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\n   *\n   * Building the Library\n   * ------------\n   *\n   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\\\DSP_Lib\\\\Source\\\\ARM</code> folder.\n   * - arm_cortexM_math.uvprojx\n   *\n   *\n   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.\n   *\n   * Pre-processor Macros\n   * ------------\n   *\n   * Each library project have differant pre-processor macros.\n   *\n   * - UNALIGNED_SUPPORT_DISABLE:\n   *\n   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\n   *\n   * - ARM_MATH_BIG_ENDIAN:\n   *\n   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\n   *\n   * - ARM_MATH_MATRIX_CHECK:\n   *\n   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\n   *\n   * - ARM_MATH_ROUNDING:\n   *\n   * Define macro ARM_MATH_ROUNDING for rounding on support functions\n   *\n   * - ARM_MATH_CMx:\n   *\n   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\n   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\n   * ARM_MATH_CM7 for building the library on cortex-M7.\n   *\n   * - __FPU_PRESENT:\n   *\n   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries\n   *\n   * <hr>\n   * CMSIS-DSP in ARM::CMSIS Pack\n   * -----------------------------\n   *\n   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\n   * |File/Folder                   |Content                                                                 |\n   * |------------------------------|------------------------------------------------------------------------|\n   * |\\b CMSIS\\\\Documentation\\\\DSP  | This documentation                                                     |\n   * |\\b CMSIS\\\\DSP_Lib             | Software license agreement (license.txt)                               |\n   * |\\b CMSIS\\\\DSP_Lib\\\\Examples   | Example projects demonstrating the usage of the library functions      |\n   * |\\b CMSIS\\\\DSP_Lib\\\\Source     | Source files for rebuilding the library                                |\n   *\n   * <hr>\n   * Revision History of CMSIS-DSP\n   * ------------\n   * Please refer to \\ref ChangeLog_pg.\n   *\n   * Copyright Notice\n   * ------------\n   *\n   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.\n   */\n\n\n/**\n * @defgroup groupMath Basic Math Functions\n */\n\n/**\n * @defgroup groupFastMath Fast Math Functions\n * This set of functions provides a fast approximation to sine, cosine, and square root.\n * As compared to most of the other functions in the CMSIS math library, the fast math functions\n * operate on individual values and not arrays.\n * There are separate functions for Q15, Q31, and floating-point data.\n *\n */\n\n/**\n * @defgroup groupCmplxMath Complex Math Functions\n * This set of functions operates on complex data vectors.\n * The data in the complex arrays is stored in an interleaved fashion\n * (real, imag, real, imag, ...).\n * In the API functions, the number of samples in a complex array refers\n * to the number of complex values; the array contains twice this number of\n * real values.\n */\n\n/**\n * @defgroup groupFilters Filtering Functions\n */\n\n/**\n * @defgroup groupMatrix Matrix Functions\n *\n * This set of functions provides basic matrix math operations.\n * The functions operate on matrix data structures.  For example,\n * the type\n * definition for the floating-point matrix structure is shown\n * below:\n * <pre>\n *     typedef struct\n *     {\n *       uint16_t numRows;     // number of rows of the matrix.\n *       uint16_t numCols;     // number of columns of the matrix.\n *       float32_t *pData;     // points to the data of the matrix.\n *     } arm_matrix_instance_f32;\n * </pre>\n * There are similar definitions for Q15 and Q31 data types.\n *\n * The structure specifies the size of the matrix and then points to\n * an array of data.  The array is of size <code>numRows X numCols</code>\n * and the values are arranged in row order.  That is, the\n * matrix element (i, j) is stored at:\n * <pre>\n *     pData[i*numCols + j]\n * </pre>\n *\n * \\par Init Functions\n * There is an associated initialization function for each type of matrix\n * data structure.\n * The initialization function sets the values of the internal structure fields.\n * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\n * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.\n *\n * \\par\n * Use of the initialization function is optional. However, if initialization function is used\n * then the instance structure cannot be placed into a const data section.\n * To place the instance structure in a const data\n * section, manually initialize the data structure.  For example:\n * <pre>\n * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\n * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\n * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\n * </pre>\n * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\n * specifies the number of columns, and <code>pData</code> points to the\n * data array.\n *\n * \\par Size Checking\n * By default all of the matrix functions perform size checking on the input and\n * output matrices.  For example, the matrix addition function verifies that the\n * two input matrices and the output matrix all have the same number of rows and\n * columns.  If the size check fails the functions return:\n * <pre>\n *     ARM_MATH_SIZE_MISMATCH\n * </pre>\n * Otherwise the functions return\n * <pre>\n *     ARM_MATH_SUCCESS\n * </pre>\n * There is some overhead associated with this matrix size checking.\n * The matrix size checking is enabled via the \\#define\n * <pre>\n *     ARM_MATH_MATRIX_CHECK\n * </pre>\n * within the library project settings.  By default this macro is defined\n * and size checking is enabled.  By changing the project settings and\n * undefining this macro size checking is eliminated and the functions\n * run a bit faster.  With size checking disabled the functions always\n * return <code>ARM_MATH_SUCCESS</code>.\n */\n\n/**\n * @defgroup groupTransforms Transform Functions\n */\n\n/**\n * @defgroup groupController Controller Functions\n */\n\n/**\n * @defgroup groupStats Statistics Functions\n */\n/**\n * @defgroup groupSupport Support Functions\n */\n\n/**\n * @defgroup groupInterpolation Interpolation Functions\n * These functions perform 1- and 2-dimensional interpolation of data.\n * Linear interpolation is used for 1-dimensional data and\n * bilinear interpolation is used for 2-dimensional data.\n */\n\n/**\n * @defgroup groupExamples Examples\n */\n#ifndef _ARM_MATH_H\n#define _ARM_MATH_H\n\n/* ignore some GCC warnings */\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n#endif\n\n#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */\n\n#if defined(ARM_MATH_CM7)\n  #include \"core_cm7.h\"\n#elif defined (ARM_MATH_CM4)\n  #include \"core_cm4.h\"\n#elif defined (ARM_MATH_CM3)\n  #include \"core_cm3.h\"\n#elif defined (ARM_MATH_CM0)\n  #include \"core_cm0.h\"\n  #define ARM_MATH_CM0_FAMILY\n#elif defined (ARM_MATH_CM0PLUS)\n  #include \"core_cm0plus.h\"\n  #define ARM_MATH_CM0_FAMILY\n#else\n  #error \"Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0\"\n#endif\n\n#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */\n#include \"string.h\"\n#include \"math.h\"\n#ifdef   __cplusplus\nextern \"C\"\n{\n#endif\n\n\n  /**\n   * @brief Macros required for reciprocal calculation in Normalized LMS\n   */\n\n#define DELTA_Q31          (0x100)\n#define DELTA_Q15          0x5\n#define INDEX_MASK         0x0000003F\n#ifndef PI\n#define PI                 3.14159265358979f\n#endif\n\n  /**\n   * @brief Macros required for SINE and COSINE Fast math approximations\n   */\n\n#define FAST_MATH_TABLE_SIZE  512\n#define FAST_MATH_Q31_SHIFT   (32 - 10)\n#define FAST_MATH_Q15_SHIFT   (16 - 10)\n#define CONTROLLER_Q31_SHIFT  (32 - 9)\n#define TABLE_SIZE  256\n#define TABLE_SPACING_Q31     0x400000\n#define TABLE_SPACING_Q15     0x80\n\n  /**\n   * @brief Macros required for SINE and COSINE Controller functions\n   */\n  /* 1.31(q31) Fixed value of 2/360 */\n  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\n#define INPUT_SPACING         0xB60B61\n\n  /**\n   * @brief Macro for Unaligned Support\n   */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n    #define ALIGN4\n#else\n  #if defined  (__GNUC__)\n    #define ALIGN4 __attribute__((aligned(4)))\n  #else\n    #define ALIGN4 __align(4)\n  #endif\n#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */\n\n  /**\n   * @brief Error status returned by some functions in the library.\n   */\n\n  typedef enum\n  {\n    ARM_MATH_SUCCESS = 0,                /**< No error */\n    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */\n    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */\n    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */\n    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */\n    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\n    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */\n  } arm_status;\n\n  /**\n   * @brief 8-bit fractional data type in 1.7 format.\n   */\n  typedef int8_t q7_t;\n\n  /**\n   * @brief 16-bit fractional data type in 1.15 format.\n   */\n  typedef int16_t q15_t;\n\n  /**\n   * @brief 32-bit fractional data type in 1.31 format.\n   */\n  typedef int32_t q31_t;\n\n  /**\n   * @brief 64-bit fractional data type in 1.63 format.\n   */\n  typedef int64_t q63_t;\n\n  /**\n   * @brief 32-bit floating-point type definition.\n   */\n  typedef float float32_t;\n\n  /**\n   * @brief 64-bit floating-point type definition.\n   */\n  typedef double float64_t;\n\n  /**\n   * @brief definition to read/write two 16 bit values.\n   */\n#if defined __CC_ARM\n  #define __SIMD32_TYPE int32_t __packed\n  #define CMSIS_UNUSED __attribute__((unused))\n\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #define __SIMD32_TYPE int32_t\n  #define CMSIS_UNUSED __attribute__((unused))\n\n#elif defined __GNUC__\n  #define __SIMD32_TYPE int32_t\n  #define CMSIS_UNUSED __attribute__((unused))\n\n#elif defined __ICCARM__\n  #define __SIMD32_TYPE int32_t __packed\n  #define CMSIS_UNUSED\n\n#elif defined __CSMC__\n  #define __SIMD32_TYPE int32_t\n  #define CMSIS_UNUSED\n\n#elif defined __TASKING__\n  #define __SIMD32_TYPE __unaligned int32_t\n  #define CMSIS_UNUSED\n\n#else\n  #error Unknown compiler\n#endif\n\n#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))\n#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))\n#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))\n#define __SIMD64(addr)        (*(int64_t **) & (addr))\n\n#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\n  /**\n   * @brief definition to pack two 16 bit values.\n   */\n#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \\\n                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )\n#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \\\n                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )\n\n#endif\n\n\n   /**\n   * @brief definition to pack four 8 bit values.\n   */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \\\n                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \\\n                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\\n                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )\n#else\n\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \\\n                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \\\n                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\\n                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )\n\n#endif\n\n\n  /**\n   * @brief Clips Q63 to Q31 values.\n   */\n  static __INLINE q31_t clip_q63_to_q31(\n  q63_t x)\n  {\n    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\n      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\n  }\n\n  /**\n   * @brief Clips Q63 to Q15 values.\n   */\n  static __INLINE q15_t clip_q63_to_q15(\n  q63_t x)\n  {\n    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\n      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\n  }\n\n  /**\n   * @brief Clips Q31 to Q7 values.\n   */\n  static __INLINE q7_t clip_q31_to_q7(\n  q31_t x)\n  {\n    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\n      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\n  }\n\n  /**\n   * @brief Clips Q31 to Q15 values.\n   */\n  static __INLINE q15_t clip_q31_to_q15(\n  q31_t x)\n  {\n    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\n      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\n  }\n\n  /**\n   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\n   */\n\n  static __INLINE q63_t mult32x64(\n  q63_t x,\n  q31_t y)\n  {\n    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\n            (((q63_t) (x >> 32) * y)));\n  }\n\n/*\n  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )\n  #define __CLZ __clz\n  #endif\n */\n/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */\n#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )\n  static __INLINE uint32_t __CLZ(\n  q31_t data);\n\n  static __INLINE uint32_t __CLZ(\n  q31_t data)\n  {\n    uint32_t count = 0;\n    uint32_t mask = 0x80000000;\n\n    while((data & mask) == 0)\n    {\n      count += 1u;\n      mask = mask >> 1u;\n    }\n\n    return (count);\n  }\n#endif\n\n  /**\n   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\n   */\n\n  static __INLINE uint32_t arm_recip_q31(\n  q31_t in,\n  q31_t * dst,\n  q31_t * pRecipTable)\n  {\n    q31_t out;\n    uint32_t tempVal;\n    uint32_t index, i;\n    uint32_t signBits;\n\n    if(in > 0)\n    {\n      signBits = ((uint32_t) (__CLZ( in) - 1));\n    }\n    else\n    {\n      signBits = ((uint32_t) (__CLZ(-in) - 1));\n    }\n\n    /* Convert input sample to 1.31 format */\n    in = (in << signBits);\n\n    /* calculation of index for initial approximated Val */\n    index = (uint32_t)(in >> 24);\n    index = (index & INDEX_MASK);\n\n    /* 1.31 with exp 1 */\n    out = pRecipTable[index];\n\n    /* calculation of reciprocal value */\n    /* running approximation for two iterations */\n    for (i = 0u; i < 2u; i++)\n    {\n      tempVal = (uint32_t) (((q63_t) in * out) >> 31);\n      tempVal = 0x7FFFFFFFu - tempVal;\n      /*      1.31 with exp 1 */\n      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\n      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\n    }\n\n    /* write output */\n    *dst = out;\n\n    /* return num of signbits of out = 1/in value */\n    return (signBits + 1u);\n  }\n\n\n  /**\n   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\n   */\n  static __INLINE uint32_t arm_recip_q15(\n  q15_t in,\n  q15_t * dst,\n  q15_t * pRecipTable)\n  {\n    q15_t out = 0;\n    uint32_t tempVal = 0;\n    uint32_t index = 0, i = 0;\n    uint32_t signBits = 0;\n\n    if(in > 0)\n    {\n      signBits = ((uint32_t)(__CLZ( in) - 17));\n    }\n    else\n    {\n      signBits = ((uint32_t)(__CLZ(-in) - 17));\n    }\n\n    /* Convert input sample to 1.15 format */\n    in = (in << signBits);\n\n    /* calculation of index for initial approximated Val */\n    index = (uint32_t)(in >>  8);\n    index = (index & INDEX_MASK);\n\n    /*      1.15 with exp 1  */\n    out = pRecipTable[index];\n\n    /* calculation of reciprocal value */\n    /* running approximation for two iterations */\n    for (i = 0u; i < 2u; i++)\n    {\n      tempVal = (uint32_t) (((q31_t) in * out) >> 15);\n      tempVal = 0x7FFFu - tempVal;\n      /*      1.15 with exp 1 */\n      out = (q15_t) (((q31_t) out * tempVal) >> 14);\n      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\n    }\n\n    /* write output */\n    *dst = out;\n\n    /* return num of signbits of out = 1/in value */\n    return (signBits + 1);\n  }\n\n\n  /*\n   * @brief C custom defined intrinisic function for only M0 processors\n   */\n#if defined(ARM_MATH_CM0_FAMILY)\n  static __INLINE q31_t __SSAT(\n  q31_t x,\n  uint32_t y)\n  {\n    int32_t posMax, negMin;\n    uint32_t i;\n\n    posMax = 1;\n    for (i = 0; i < (y - 1); i++)\n    {\n      posMax = posMax * 2;\n    }\n\n    if(x > 0)\n    {\n      posMax = (posMax - 1);\n\n      if(x > posMax)\n      {\n        x = posMax;\n      }\n    }\n    else\n    {\n      negMin = -posMax;\n\n      if(x < negMin)\n      {\n        x = negMin;\n      }\n    }\n    return (x);\n  }\n#endif /* end of ARM_MATH_CM0_FAMILY */\n\n\n  /*\n   * @brief C custom defined intrinsic function for M3 and M0 processors\n   */\n#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)\n\n  /*\n   * @brief C custom defined QADD8 for M3 and M0 processors\n   */\n  static __INLINE uint32_t __QADD8(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s, t, u;\n\n    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\n    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\n    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;\n    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;\n\n    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QSUB8 for M3 and M0 processors\n   */\n  static __INLINE uint32_t __QSUB8(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s, t, u;\n\n    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\n    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\n    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;\n    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;\n\n    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QADD16 for M3 and M0 processors\n   */\n  static __INLINE uint32_t __QADD16(\n  uint32_t x,\n  uint32_t y)\n  {\n/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */\n    q31_t r = 0, s = 0;\n\n    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\n    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SHADD16 for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SHADD16(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QSUB16 for M3 and M0 processors\n   */\n  static __INLINE uint32_t __QSUB16(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\n    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SHSUB16 for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SHSUB16(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QASX for M3 and M0 processors\n   */\n  static __INLINE uint32_t __QASX(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\n    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SHASX for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SHASX(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QSAX for M3 and M0 processors\n   */\n  static __INLINE uint32_t __QSAX(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\n    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SHSAX for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SHSAX(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SMUSDX for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SMUSDX(\n  uint32_t x,\n  uint32_t y)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));\n  }\n\n  /*\n   * @brief C custom defined SMUADX for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SMUADX(\n  uint32_t x,\n  uint32_t y)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));\n  }\n\n\n  /*\n   * @brief C custom defined QADD for M3 and M0 processors\n   */\n  static __INLINE int32_t __QADD(\n  int32_t x,\n  int32_t y)\n  {\n    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\n  }\n\n\n  /*\n   * @brief C custom defined QSUB for M3 and M0 processors\n   */\n  static __INLINE int32_t __QSUB(\n  int32_t x,\n  int32_t y)\n  {\n    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\n  }\n\n\n  /*\n   * @brief C custom defined SMLAD for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SMLAD(\n  uint32_t x,\n  uint32_t y,\n  uint32_t sum)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ( ((q31_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMLADX for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SMLADX(\n  uint32_t x,\n  uint32_t y,\n  uint32_t sum)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ( ((q31_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMLSDX for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SMLSDX(\n  uint32_t x,\n  uint32_t y,\n  uint32_t sum)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ( ((q31_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMLALD for M3 and M0 processors\n   */\n  static __INLINE uint64_t __SMLALD(\n  uint32_t x,\n  uint32_t y,\n  uint64_t sum)\n  {\n/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\n    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ( ((q63_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMLALDX for M3 and M0 processors\n   */\n  static __INLINE uint64_t __SMLALDX(\n  uint32_t x,\n  uint32_t y,\n  uint64_t sum)\n  {\n/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\n    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ( ((q63_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMUAD for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SMUAD(\n  uint32_t x,\n  uint32_t y)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMUSD for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SMUSD(\n  uint32_t x,\n  uint32_t y)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));\n  }\n\n\n  /*\n   * @brief C custom defined SXTB16 for M3 and M0 processors\n   */\n  static __INLINE uint32_t __SXTB16(\n  uint32_t x)\n  {\n    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\n                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));\n  }\n\n#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */\n\n\n  /**\n   * @brief Instance structure for the Q7 FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;        /**< number of filter coefficients in the filter. */\n    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\n  } arm_fir_instance_q7;\n\n  /**\n   * @brief Instance structure for the Q15 FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;         /**< number of filter coefficients in the filter. */\n    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\n  } arm_fir_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;         /**< number of filter coefficients in the filter. */\n    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */\n  } arm_fir_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;     /**< number of filter coefficients in the filter. */\n    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */\n  } arm_fir_instance_f32;\n\n\n  /**\n   * @brief Processing function for the Q7 FIR filter.\n   * @param[in]  S          points to an instance of the Q7 FIR filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_q7(\n  const arm_fir_instance_q7 * S,\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q7 FIR filter.\n   * @param[in,out] S          points to an instance of the Q7 FIR structure.\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of samples that are processed.\n   */\n  void arm_fir_init_q7(\n  arm_fir_instance_q7 * S,\n  uint16_t numTaps,\n  q7_t * pCoeffs,\n  q7_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 FIR filter.\n   * @param[in]  S          points to an instance of the Q15 FIR structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_q15(\n  const arm_fir_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q15 FIR filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_fast_q15(\n  const arm_fir_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 FIR filter.\n   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.\n   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of samples that are processed at a time.\n   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\n   * <code>numTaps</code> is not a supported value.\n   */\n  arm_status arm_fir_init_q15(\n  arm_fir_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 FIR filter.\n   * @param[in]  S          points to an instance of the Q31 FIR filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_q31(\n  const arm_fir_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q31 FIR structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_fast_q31(\n  const arm_fir_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 FIR filter.\n   * @param[in,out] S          points to an instance of the Q31 FIR structure.\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of samples that are processed at a time.\n   */\n  void arm_fir_init_q31(\n  arm_fir_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the floating-point FIR filter.\n   * @param[in]  S          points to an instance of the floating-point FIR structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_f32(\n  const arm_fir_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point FIR filter.\n   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of samples that are processed at a time.\n   */\n  void arm_fir_init_f32(\n  arm_fir_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 Biquad cascade filter.\n   */\n  typedef struct\n  {\n    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\n    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */\n    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */\n  } arm_biquad_casd_df1_inst_q15;\n\n  /**\n   * @brief Instance structure for the Q31 Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\n    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */\n    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */\n  } arm_biquad_casd_df1_inst_q31;\n\n  /**\n   * @brief Instance structure for the floating-point Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\n    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */\n  } arm_biquad_casd_df1_inst_f32;\n\n\n  /**\n   * @brief Processing function for the Q15 Biquad cascade filter.\n   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_q15(\n  const arm_biquad_casd_df1_inst_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format\n   */\n  void arm_biquad_cascade_df1_init_q15(\n  arm_biquad_casd_df1_inst_q15 * S,\n  uint8_t numStages,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  int8_t postShift);\n\n\n  /**\n   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_fast_q15(\n  const arm_biquad_casd_df1_inst_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 Biquad cascade filter\n   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_q31(\n  const arm_biquad_casd_df1_inst_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_fast_q31(\n  const arm_biquad_casd_df1_inst_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format\n   */\n  void arm_biquad_cascade_df1_init_q31(\n  arm_biquad_casd_df1_inst_q31 * S,\n  uint8_t numStages,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  int8_t postShift);\n\n\n  /**\n   * @brief Processing function for the floating-point Biquad cascade filter.\n   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_f32(\n  const arm_biquad_casd_df1_inst_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   */\n  void arm_biquad_cascade_df1_init_f32(\n  arm_biquad_casd_df1_inst_f32 * S,\n  uint8_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState);\n\n\n  /**\n   * @brief Instance structure for the floating-point matrix structure.\n   */\n  typedef struct\n  {\n    uint16_t numRows;     /**< number of rows of the matrix.     */\n    uint16_t numCols;     /**< number of columns of the matrix.  */\n    float32_t *pData;     /**< points to the data of the matrix. */\n  } arm_matrix_instance_f32;\n\n\n  /**\n   * @brief Instance structure for the floating-point matrix structure.\n   */\n  typedef struct\n  {\n    uint16_t numRows;     /**< number of rows of the matrix.     */\n    uint16_t numCols;     /**< number of columns of the matrix.  */\n    float64_t *pData;     /**< points to the data of the matrix. */\n  } arm_matrix_instance_f64;\n\n  /**\n   * @brief Instance structure for the Q15 matrix structure.\n   */\n  typedef struct\n  {\n    uint16_t numRows;     /**< number of rows of the matrix.     */\n    uint16_t numCols;     /**< number of columns of the matrix.  */\n    q15_t *pData;         /**< points to the data of the matrix. */\n  } arm_matrix_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 matrix structure.\n   */\n  typedef struct\n  {\n    uint16_t numRows;     /**< number of rows of the matrix.     */\n    uint16_t numCols;     /**< number of columns of the matrix.  */\n    q31_t *pData;         /**< points to the data of the matrix. */\n  } arm_matrix_instance_q31;\n\n\n  /**\n   * @brief Floating-point matrix addition.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_add_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix addition.\n   * @param[in]   pSrcA  points to the first input matrix structure\n   * @param[in]   pSrcB  points to the second input matrix structure\n   * @param[out]  pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_add_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst);\n\n\n  /**\n   * @brief Q31 matrix addition.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_add_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point, complex, matrix multiplication.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_cmplx_mult_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15, complex,  matrix multiplication.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_cmplx_mult_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst,\n  q15_t * pScratch);\n\n\n  /**\n   * @brief Q31, complex, matrix multiplication.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_cmplx_mult_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point matrix transpose.\n   * @param[in]  pSrc  points to the input matrix\n   * @param[out] pDst  points to the output matrix\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_trans_f32(\n  const arm_matrix_instance_f32 * pSrc,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix transpose.\n   * @param[in]  pSrc  points to the input matrix\n   * @param[out] pDst  points to the output matrix\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_trans_q15(\n  const arm_matrix_instance_q15 * pSrc,\n  arm_matrix_instance_q15 * pDst);\n\n\n  /**\n   * @brief Q31 matrix transpose.\n   * @param[in]  pSrc  points to the input matrix\n   * @param[out] pDst  points to the output matrix\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_trans_q31(\n  const arm_matrix_instance_q31 * pSrc,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point matrix multiplication\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix multiplication\n   * @param[in]  pSrcA   points to the first input matrix structure\n   * @param[in]  pSrcB   points to the second input matrix structure\n   * @param[out] pDst    points to output matrix structure\n   * @param[in]  pState  points to the array for storing intermediate results\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst,\n  q15_t * pState);\n\n\n  /**\n   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA   points to the first input matrix structure\n   * @param[in]  pSrcB   points to the second input matrix structure\n   * @param[out] pDst    points to output matrix structure\n   * @param[in]  pState  points to the array for storing intermediate results\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_fast_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst,\n  q15_t * pState);\n\n\n  /**\n   * @brief Q31 matrix multiplication\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_fast_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point matrix subtraction\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_sub_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix subtraction\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_sub_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst);\n\n\n  /**\n   * @brief Q31 matrix subtraction\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_sub_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point matrix scaling.\n   * @param[in]  pSrc   points to the input matrix\n   * @param[in]  scale  scale factor\n   * @param[out] pDst   points to the output matrix\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_scale_f32(\n  const arm_matrix_instance_f32 * pSrc,\n  float32_t scale,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix scaling.\n   * @param[in]  pSrc        points to input matrix\n   * @param[in]  scaleFract  fractional portion of the scale factor\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to output matrix\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_scale_q15(\n  const arm_matrix_instance_q15 * pSrc,\n  q15_t scaleFract,\n  int32_t shift,\n  arm_matrix_instance_q15 * pDst);\n\n\n  /**\n   * @brief Q31 matrix scaling.\n   * @param[in]  pSrc        points to input matrix\n   * @param[in]  scaleFract  fractional portion of the scale factor\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_scale_q31(\n  const arm_matrix_instance_q31 * pSrc,\n  q31_t scaleFract,\n  int32_t shift,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief  Q31 matrix initialization.\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\n   * @param[in]     nRows     number of rows in the matrix.\n   * @param[in]     nColumns  number of columns in the matrix.\n   * @param[in]     pData     points to the matrix data array.\n   */\n  void arm_mat_init_q31(\n  arm_matrix_instance_q31 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  q31_t * pData);\n\n\n  /**\n   * @brief  Q15 matrix initialization.\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\n   * @param[in]     nRows     number of rows in the matrix.\n   * @param[in]     nColumns  number of columns in the matrix.\n   * @param[in]     pData     points to the matrix data array.\n   */\n  void arm_mat_init_q15(\n  arm_matrix_instance_q15 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  q15_t * pData);\n\n\n  /**\n   * @brief  Floating-point matrix initialization.\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\n   * @param[in]     nRows     number of rows in the matrix.\n   * @param[in]     nColumns  number of columns in the matrix.\n   * @param[in]     pData     points to the matrix data array.\n   */\n  void arm_mat_init_f32(\n  arm_matrix_instance_f32 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  float32_t * pData);\n\n\n\n  /**\n   * @brief Instance structure for the Q15 PID Control.\n   */\n  typedef struct\n  {\n    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */\n#ifdef ARM_MATH_CM0_FAMILY\n    q15_t A1;\n    q15_t A2;\n#else\n    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\n#endif\n    q15_t state[3];     /**< The state array of length 3. */\n    q15_t Kp;           /**< The proportional gain. */\n    q15_t Ki;           /**< The integral gain. */\n    q15_t Kd;           /**< The derivative gain. */\n  } arm_pid_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 PID Control.\n   */\n  typedef struct\n  {\n    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */\n    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */\n    q31_t A2;            /**< The derived gain, A2 = Kd . */\n    q31_t state[3];      /**< The state array of length 3. */\n    q31_t Kp;            /**< The proportional gain. */\n    q31_t Ki;            /**< The integral gain. */\n    q31_t Kd;            /**< The derivative gain. */\n  } arm_pid_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point PID Control.\n   */\n  typedef struct\n  {\n    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */\n    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */\n    float32_t A2;          /**< The derived gain, A2 = Kd . */\n    float32_t state[3];    /**< The state array of length 3. */\n    float32_t Kp;          /**< The proportional gain. */\n    float32_t Ki;          /**< The integral gain. */\n    float32_t Kd;          /**< The derivative gain. */\n  } arm_pid_instance_f32;\n\n\n\n  /**\n   * @brief  Initialization function for the floating-point PID Control.\n   * @param[in,out] S               points to an instance of the PID structure.\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\n   */\n  void arm_pid_init_f32(\n  arm_pid_instance_f32 * S,\n  int32_t resetStateFlag);\n\n\n  /**\n   * @brief  Reset function for the floating-point PID Control.\n   * @param[in,out] S  is an instance of the floating-point PID Control structure\n   */\n  void arm_pid_reset_f32(\n  arm_pid_instance_f32 * S);\n\n\n  /**\n   * @brief  Initialization function for the Q31 PID Control.\n   * @param[in,out] S               points to an instance of the Q15 PID structure.\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\n   */\n  void arm_pid_init_q31(\n  arm_pid_instance_q31 * S,\n  int32_t resetStateFlag);\n\n\n  /**\n   * @brief  Reset function for the Q31 PID Control.\n   * @param[in,out] S   points to an instance of the Q31 PID Control structure\n   */\n\n  void arm_pid_reset_q31(\n  arm_pid_instance_q31 * S);\n\n\n  /**\n   * @brief  Initialization function for the Q15 PID Control.\n   * @param[in,out] S               points to an instance of the Q15 PID structure.\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\n   */\n  void arm_pid_init_q15(\n  arm_pid_instance_q15 * S,\n  int32_t resetStateFlag);\n\n\n  /**\n   * @brief  Reset function for the Q15 PID Control.\n   * @param[in,out] S  points to an instance of the q15 PID Control structure\n   */\n  void arm_pid_reset_q15(\n  arm_pid_instance_q15 * S);\n\n\n  /**\n   * @brief Instance structure for the floating-point Linear Interpolate function.\n   */\n  typedef struct\n  {\n    uint32_t nValues;           /**< nValues */\n    float32_t x1;               /**< x1 */\n    float32_t xSpacing;         /**< xSpacing */\n    float32_t *pYData;          /**< pointer to the table of Y values */\n  } arm_linear_interp_instance_f32;\n\n  /**\n   * @brief Instance structure for the floating-point bilinear interpolation function.\n   */\n  typedef struct\n  {\n    uint16_t numRows;   /**< number of rows in the data table. */\n    uint16_t numCols;   /**< number of columns in the data table. */\n    float32_t *pData;   /**< points to the data table. */\n  } arm_bilinear_interp_instance_f32;\n\n   /**\n   * @brief Instance structure for the Q31 bilinear interpolation function.\n   */\n  typedef struct\n  {\n    uint16_t numRows;   /**< number of rows in the data table. */\n    uint16_t numCols;   /**< number of columns in the data table. */\n    q31_t *pData;       /**< points to the data table. */\n  } arm_bilinear_interp_instance_q31;\n\n   /**\n   * @brief Instance structure for the Q15 bilinear interpolation function.\n   */\n  typedef struct\n  {\n    uint16_t numRows;   /**< number of rows in the data table. */\n    uint16_t numCols;   /**< number of columns in the data table. */\n    q15_t *pData;       /**< points to the data table. */\n  } arm_bilinear_interp_instance_q15;\n\n   /**\n   * @brief Instance structure for the Q15 bilinear interpolation function.\n   */\n  typedef struct\n  {\n    uint16_t numRows;   /**< number of rows in the data table. */\n    uint16_t numCols;   /**< number of columns in the data table. */\n    q7_t *pData;        /**< points to the data table. */\n  } arm_bilinear_interp_instance_q7;\n\n\n  /**\n   * @brief Q7 vector multiplication.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_mult_q7(\n  q7_t * pSrcA,\n  q7_t * pSrcB,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q15 vector multiplication.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_mult_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q31 vector multiplication.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_mult_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Floating-point vector multiplication.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_mult_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                 /**< length of the FFT. */\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n  } arm_cfft_radix2_instance_q15;\n\n/* Deprecated */\n  arm_status arm_cfft_radix2_init_q15(\n  arm_cfft_radix2_instance_q15 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix2_q15(\n  const arm_cfft_radix2_instance_q15 * S,\n  q15_t * pSrc);\n\n\n  /**\n   * @brief Instance structure for the Q15 CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                 /**< length of the FFT. */\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n  } arm_cfft_radix4_instance_q15;\n\n/* Deprecated */\n  arm_status arm_cfft_radix4_init_q15(\n  arm_cfft_radix4_instance_q15 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix4_q15(\n  const arm_cfft_radix4_instance_q15 * S,\n  q15_t * pSrc);\n\n  /**\n   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                 /**< length of the FFT. */\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n  } arm_cfft_radix2_instance_q31;\n\n/* Deprecated */\n  arm_status arm_cfft_radix2_init_q31(\n  arm_cfft_radix2_instance_q31 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix2_q31(\n  const arm_cfft_radix2_instance_q31 * S,\n  q31_t * pSrc);\n\n  /**\n   * @brief Instance structure for the Q31 CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                 /**< length of the FFT. */\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n  } arm_cfft_radix4_instance_q31;\n\n/* Deprecated */\n  void arm_cfft_radix4_q31(\n  const arm_cfft_radix4_instance_q31 * S,\n  q31_t * pSrc);\n\n/* Deprecated */\n  arm_status arm_cfft_radix4_init_q31(\n  arm_cfft_radix4_instance_q31 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n  /**\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */\n    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n    float32_t onebyfftLen;             /**< value of 1/fftLen. */\n  } arm_cfft_radix2_instance_f32;\n\n/* Deprecated */\n  arm_status arm_cfft_radix2_init_f32(\n  arm_cfft_radix2_instance_f32 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix2_f32(\n  const arm_cfft_radix2_instance_f32 * S,\n  float32_t * pSrc);\n\n  /**\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */\n    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n    float32_t onebyfftLen;             /**< value of 1/fftLen. */\n  } arm_cfft_radix4_instance_f32;\n\n/* Deprecated */\n  arm_status arm_cfft_radix4_init_f32(\n  arm_cfft_radix4_instance_f32 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix4_f32(\n  const arm_cfft_radix4_instance_f32 * S,\n  float32_t * pSrc);\n\n  /**\n   * @brief Instance structure for the fixed-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\n    uint16_t bitRevLength;             /**< bit reversal table length. */\n  } arm_cfft_instance_q15;\n\nvoid arm_cfft_q15(\n    const arm_cfft_instance_q15 * S,\n    q15_t * p1,\n    uint8_t ifftFlag,\n    uint8_t bitReverseFlag);\n\n  /**\n   * @brief Instance structure for the fixed-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\n    uint16_t bitRevLength;             /**< bit reversal table length. */\n  } arm_cfft_instance_q31;\n\nvoid arm_cfft_q31(\n    const arm_cfft_instance_q31 * S,\n    q31_t * p1,\n    uint8_t ifftFlag,\n    uint8_t bitReverseFlag);\n\n  /**\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\n    uint16_t bitRevLength;             /**< bit reversal table length. */\n  } arm_cfft_instance_f32;\n\n  void arm_cfft_f32(\n  const arm_cfft_instance_f32 * S,\n  float32_t * p1,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n  /**\n   * @brief Instance structure for the Q15 RFFT/RIFFT function.\n   */\n  typedef struct\n  {\n    uint32_t fftLenReal;                      /**< length of the real FFT. */\n    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\n    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\n    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */\n    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */\n    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */\n  } arm_rfft_instance_q15;\n\n  arm_status arm_rfft_init_q15(\n  arm_rfft_instance_q15 * S,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag);\n\n  void arm_rfft_q15(\n  const arm_rfft_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst);\n\n  /**\n   * @brief Instance structure for the Q31 RFFT/RIFFT function.\n   */\n  typedef struct\n  {\n    uint32_t fftLenReal;                        /**< length of the real FFT. */\n    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\n    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\n    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */\n    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */\n    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */\n  } arm_rfft_instance_q31;\n\n  arm_status arm_rfft_init_q31(\n  arm_rfft_instance_q31 * S,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag);\n\n  void arm_rfft_q31(\n  const arm_rfft_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst);\n\n  /**\n   * @brief Instance structure for the floating-point RFFT/RIFFT function.\n   */\n  typedef struct\n  {\n    uint32_t fftLenReal;                        /**< length of the real FFT. */\n    uint16_t fftLenBy2;                         /**< length of the complex FFT. */\n    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\n    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\n    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */\n    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */\n    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */\n  } arm_rfft_instance_f32;\n\n  arm_status arm_rfft_init_f32(\n  arm_rfft_instance_f32 * S,\n  arm_cfft_radix4_instance_f32 * S_CFFT,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag);\n\n  void arm_rfft_f32(\n  const arm_rfft_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst);\n\n  /**\n   * @brief Instance structure for the floating-point RFFT/RIFFT function.\n   */\ntypedef struct\n  {\n    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */\n    uint16_t fftLenRFFT;             /**< length of the real sequence */\n    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */\n  } arm_rfft_fast_instance_f32 ;\n\narm_status arm_rfft_fast_init_f32 (\n   arm_rfft_fast_instance_f32 * S,\n   uint16_t fftLen);\n\nvoid arm_rfft_fast_f32(\n  arm_rfft_fast_instance_f32 * S,\n  float32_t * p, float32_t * pOut,\n  uint8_t ifftFlag);\n\n  /**\n   * @brief Instance structure for the floating-point DCT4/IDCT4 function.\n   */\n  typedef struct\n  {\n    uint16_t N;                          /**< length of the DCT4. */\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\n    float32_t normalize;                 /**< normalizing factor. */\n    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */\n    float32_t *pCosFactor;               /**< points to the cosFactor table. */\n    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */\n    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\n  } arm_dct4_instance_f32;\n\n\n  /**\n   * @brief  Initialization function for the floating-point DCT4/IDCT4.\n   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.\n   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.\n   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.\n   * @param[in]     N          length of the DCT4.\n   * @param[in]     Nby2       half of the length of the DCT4.\n   * @param[in]     normalize  normalizing factor.\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\n   */\n  arm_status arm_dct4_init_f32(\n  arm_dct4_instance_f32 * S,\n  arm_rfft_instance_f32 * S_RFFT,\n  arm_cfft_radix4_instance_f32 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  float32_t normalize);\n\n\n  /**\n   * @brief Processing function for the floating-point DCT4/IDCT4.\n   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.\n   * @param[in]     pState         points to state buffer.\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\n   */\n  void arm_dct4_f32(\n  const arm_dct4_instance_f32 * S,\n  float32_t * pState,\n  float32_t * pInlineBuffer);\n\n\n  /**\n   * @brief Instance structure for the Q31 DCT4/IDCT4 function.\n   */\n  typedef struct\n  {\n    uint16_t N;                          /**< length of the DCT4. */\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\n    q31_t normalize;                     /**< normalizing factor. */\n    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */\n    q31_t *pCosFactor;                   /**< points to the cosFactor table. */\n    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */\n    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\n  } arm_dct4_instance_q31;\n\n\n  /**\n   * @brief  Initialization function for the Q31 DCT4/IDCT4.\n   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.\n   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure\n   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure\n   * @param[in]     N          length of the DCT4.\n   * @param[in]     Nby2       half of the length of the DCT4.\n   * @param[in]     normalize  normalizing factor.\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\n   */\n  arm_status arm_dct4_init_q31(\n  arm_dct4_instance_q31 * S,\n  arm_rfft_instance_q31 * S_RFFT,\n  arm_cfft_radix4_instance_q31 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  q31_t normalize);\n\n\n  /**\n   * @brief Processing function for the Q31 DCT4/IDCT4.\n   * @param[in]     S              points to an instance of the Q31 DCT4 structure.\n   * @param[in]     pState         points to state buffer.\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\n   */\n  void arm_dct4_q31(\n  const arm_dct4_instance_q31 * S,\n  q31_t * pState,\n  q31_t * pInlineBuffer);\n\n\n  /**\n   * @brief Instance structure for the Q15 DCT4/IDCT4 function.\n   */\n  typedef struct\n  {\n    uint16_t N;                          /**< length of the DCT4. */\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\n    q15_t normalize;                     /**< normalizing factor. */\n    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */\n    q15_t *pCosFactor;                   /**< points to the cosFactor table. */\n    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */\n    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\n  } arm_dct4_instance_q15;\n\n\n  /**\n   * @brief  Initialization function for the Q15 DCT4/IDCT4.\n   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.\n   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.\n   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.\n   * @param[in]     N          length of the DCT4.\n   * @param[in]     Nby2       half of the length of the DCT4.\n   * @param[in]     normalize  normalizing factor.\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\n   */\n  arm_status arm_dct4_init_q15(\n  arm_dct4_instance_q15 * S,\n  arm_rfft_instance_q15 * S_RFFT,\n  arm_cfft_radix4_instance_q15 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  q15_t normalize);\n\n\n  /**\n   * @brief Processing function for the Q15 DCT4/IDCT4.\n   * @param[in]     S              points to an instance of the Q15 DCT4 structure.\n   * @param[in]     pState         points to state buffer.\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\n   */\n  void arm_dct4_q15(\n  const arm_dct4_instance_q15 * S,\n  q15_t * pState,\n  q15_t * pInlineBuffer);\n\n\n  /**\n   * @brief Floating-point vector addition.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_add_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q7 vector addition.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_add_q7(\n  q7_t * pSrcA,\n  q7_t * pSrcB,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q15 vector addition.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_add_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q31 vector addition.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_add_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Floating-point vector subtraction.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_sub_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q7 vector subtraction.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_sub_q7(\n  q7_t * pSrcA,\n  q7_t * pSrcB,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q15 vector subtraction.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_sub_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q31 vector subtraction.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_sub_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Multiplies a floating-point vector by a scalar.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  scale      scale factor to be applied\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_scale_f32(\n  float32_t * pSrc,\n  float32_t scale,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Multiplies a Q7 vector by a scalar.\n   * @param[in]  pSrc        points to the input vector\n   * @param[in]  scaleFract  fractional portion of the scale value\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to the output vector\n   * @param[in]  blockSize   number of samples in the vector\n   */\n  void arm_scale_q7(\n  q7_t * pSrc,\n  q7_t scaleFract,\n  int8_t shift,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Multiplies a Q15 vector by a scalar.\n   * @param[in]  pSrc        points to the input vector\n   * @param[in]  scaleFract  fractional portion of the scale value\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to the output vector\n   * @param[in]  blockSize   number of samples in the vector\n   */\n  void arm_scale_q15(\n  q15_t * pSrc,\n  q15_t scaleFract,\n  int8_t shift,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Multiplies a Q31 vector by a scalar.\n   * @param[in]  pSrc        points to the input vector\n   * @param[in]  scaleFract  fractional portion of the scale value\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to the output vector\n   * @param[in]  blockSize   number of samples in the vector\n   */\n  void arm_scale_q31(\n  q31_t * pSrc,\n  q31_t scaleFract,\n  int8_t shift,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q7 vector absolute value.\n   * @param[in]  pSrc       points to the input buffer\n   * @param[out] pDst       points to the output buffer\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_abs_q7(\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Floating-point vector absolute value.\n   * @param[in]  pSrc       points to the input buffer\n   * @param[out] pDst       points to the output buffer\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_abs_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q15 vector absolute value.\n   * @param[in]  pSrc       points to the input buffer\n   * @param[out] pDst       points to the output buffer\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_abs_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q31 vector absolute value.\n   * @param[in]  pSrc       points to the input buffer\n   * @param[out] pDst       points to the output buffer\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_abs_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Dot product of floating-point vectors.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[in]  blockSize  number of samples in each vector\n   * @param[out] result     output result returned here\n   */\n  void arm_dot_prod_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  uint32_t blockSize,\n  float32_t * result);\n\n\n  /**\n   * @brief Dot product of Q7 vectors.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[in]  blockSize  number of samples in each vector\n   * @param[out] result     output result returned here\n   */\n  void arm_dot_prod_q7(\n  q7_t * pSrcA,\n  q7_t * pSrcB,\n  uint32_t blockSize,\n  q31_t * result);\n\n\n  /**\n   * @brief Dot product of Q15 vectors.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[in]  blockSize  number of samples in each vector\n   * @param[out] result     output result returned here\n   */\n  void arm_dot_prod_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  uint32_t blockSize,\n  q63_t * result);\n\n\n  /**\n   * @brief Dot product of Q31 vectors.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[in]  blockSize  number of samples in each vector\n   * @param[out] result     output result returned here\n   */\n  void arm_dot_prod_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  uint32_t blockSize,\n  q63_t * result);\n\n\n  /**\n   * @brief  Shifts the elements of a Q7 vector a specified number of bits.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_shift_q7(\n  q7_t * pSrc,\n  int8_t shiftBits,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Shifts the elements of a Q15 vector a specified number of bits.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_shift_q15(\n  q15_t * pSrc,\n  int8_t shiftBits,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Shifts the elements of a Q31 vector a specified number of bits.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_shift_q31(\n  q31_t * pSrc,\n  int8_t shiftBits,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Adds a constant offset to a floating-point vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  offset     is the offset to be added\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_offset_f32(\n  float32_t * pSrc,\n  float32_t offset,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Adds a constant offset to a Q7 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  offset     is the offset to be added\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_offset_q7(\n  q7_t * pSrc,\n  q7_t offset,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Adds a constant offset to a Q15 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  offset     is the offset to be added\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_offset_q15(\n  q15_t * pSrc,\n  q15_t offset,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Adds a constant offset to a Q31 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  offset     is the offset to be added\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_offset_q31(\n  q31_t * pSrc,\n  q31_t offset,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Negates the elements of a floating-point vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_negate_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Negates the elements of a Q7 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_negate_q7(\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Negates the elements of a Q15 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_negate_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Negates the elements of a Q31 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_negate_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Copies the elements of a floating-point vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_copy_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Copies the elements of a Q7 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_copy_q7(\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Copies the elements of a Q15 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_copy_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Copies the elements of a Q31 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_copy_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Fills a constant value into a floating-point vector.\n   * @param[in]  value      input value to be filled\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_fill_f32(\n  float32_t value,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Fills a constant value into a Q7 vector.\n   * @param[in]  value      input value to be filled\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_fill_q7(\n  q7_t value,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Fills a constant value into a Q15 vector.\n   * @param[in]  value      input value to be filled\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_fill_q15(\n  q15_t value,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Fills a constant value into a Q31 vector.\n   * @param[in]  value      input value to be filled\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_fill_q31(\n  q31_t value,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n/**\n * @brief Convolution of floating-point sequences.\n * @param[in]  pSrcA    points to the first input sequence.\n * @param[in]  srcALen  length of the first input sequence.\n * @param[in]  pSrcB    points to the second input sequence.\n * @param[in]  srcBLen  length of the second input sequence.\n * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.\n */\n  void arm_conv_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst);\n\n\n  /**\n   * @brief Convolution of Q15 sequences.\n   * @param[in]  pSrcA      points to the first input sequence.\n   * @param[in]  srcALen    length of the first input sequence.\n   * @param[in]  pSrcB      points to the second input sequence.\n   * @param[in]  srcBLen    length of the second input sequence.\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\n   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).\n   */\n  void arm_conv_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n/**\n * @brief Convolution of Q15 sequences.\n * @param[in]  pSrcA    points to the first input sequence.\n * @param[in]  srcALen  length of the first input sequence.\n * @param[in]  pSrcB    points to the second input sequence.\n * @param[in]  srcBLen  length of the second input sequence.\n * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.\n */\n  void arm_conv_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst);\n\n\n  /**\n   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\n   */\n  void arm_conv_fast_q15(\n          q15_t * pSrcA,\n          uint32_t srcALen,\n          q15_t * pSrcB,\n          uint32_t srcBLen,\n          q15_t * pDst);\n\n\n  /**\n   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA      points to the first input sequence.\n   * @param[in]  srcALen    length of the first input sequence.\n   * @param[in]  pSrcB      points to the second input sequence.\n   * @param[in]  srcBLen    length of the second input sequence.\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\n   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).\n   */\n  void arm_conv_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Convolution of Q31 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\n   */\n  void arm_conv_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst);\n\n\n  /**\n   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\n   */\n  void arm_conv_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst);\n\n\n    /**\n   * @brief Convolution of Q7 sequences.\n   * @param[in]  pSrcA      points to the first input sequence.\n   * @param[in]  srcALen    length of the first input sequence.\n   * @param[in]  pSrcB      points to the second input sequence.\n   * @param[in]  srcBLen    length of the second input sequence.\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\n   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\n   */\n  void arm_conv_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Convolution of Q7 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\n   */\n  void arm_conv_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst);\n\n\n  /**\n   * @brief Partial convolution of floating-point sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q15 sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Partial convolution of Q15 sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_fast_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Partial convolution of Q31 sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q7 sequences\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n/**\n   * @brief Partial convolution of Q7 sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Instance structure for the Q15 FIR decimator.\n   */\n  typedef struct\n  {\n    uint8_t M;                  /**< decimation factor. */\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\n    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/\n    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n  } arm_fir_decimate_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 FIR decimator.\n   */\n  typedef struct\n  {\n    uint8_t M;                  /**< decimation factor. */\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\n    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/\n    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n  } arm_fir_decimate_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point FIR decimator.\n   */\n  typedef struct\n  {\n    uint8_t M;                  /**< decimation factor. */\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\n    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/\n    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n  } arm_fir_decimate_instance_f32;\n\n\n  /**\n   * @brief Processing function for the floating-point FIR decimator.\n   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_decimate_f32(\n  const arm_fir_decimate_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point FIR decimator.\n   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.\n   * @param[in]     numTaps    number of coefficients in the filter.\n   * @param[in]     M          decimation factor.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\n   */\n  arm_status arm_fir_decimate_init_f32(\n  arm_fir_decimate_instance_f32 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 FIR decimator.\n   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_decimate_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_decimate_fast_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 FIR decimator.\n   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.\n   * @param[in]     numTaps    number of coefficients in the filter.\n   * @param[in]     M          decimation factor.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\n   */\n  arm_status arm_fir_decimate_init_q15(\n  arm_fir_decimate_instance_q15 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 FIR decimator.\n   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.\n   * @param[in]  pSrc  points to the block of input data.\n   * @param[out] pDst  points to the block of output data\n   * @param[in] blockSize number of input samples to process per call.\n   */\n  void arm_fir_decimate_q31(\n  const arm_fir_decimate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n  /**\n   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_decimate_fast_q31(\n  arm_fir_decimate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 FIR decimator.\n   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.\n   * @param[in]     numTaps    number of coefficients in the filter.\n   * @param[in]     M          decimation factor.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\n   */\n  arm_status arm_fir_decimate_init_q31(\n  arm_fir_decimate_instance_q31 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 FIR interpolator.\n   */\n  typedef struct\n  {\n    uint8_t L;                      /**< upsample factor. */\n    uint16_t phaseLength;           /**< length of each polyphase filter component. */\n    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */\n    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\n  } arm_fir_interpolate_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 FIR interpolator.\n   */\n  typedef struct\n  {\n    uint8_t L;                      /**< upsample factor. */\n    uint16_t phaseLength;           /**< length of each polyphase filter component. */\n    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */\n    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\n  } arm_fir_interpolate_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point FIR interpolator.\n   */\n  typedef struct\n  {\n    uint8_t L;                     /**< upsample factor. */\n    uint16_t phaseLength;          /**< length of each polyphase filter component. */\n    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */\n    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\n  } arm_fir_interpolate_instance_f32;\n\n\n  /**\n   * @brief Processing function for the Q15 FIR interpolator.\n   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_interpolate_q15(\n  const arm_fir_interpolate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 FIR interpolator.\n   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.\n   * @param[in]     L          upsample factor.\n   * @param[in]     numTaps    number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\n   */\n  arm_status arm_fir_interpolate_init_q15(\n  arm_fir_interpolate_instance_q15 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 FIR interpolator.\n   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_interpolate_q31(\n  const arm_fir_interpolate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 FIR interpolator.\n   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.\n   * @param[in]     L          upsample factor.\n   * @param[in]     numTaps    number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\n   */\n  arm_status arm_fir_interpolate_init_q31(\n  arm_fir_interpolate_instance_q31 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the floating-point FIR interpolator.\n   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_interpolate_f32(\n  const arm_fir_interpolate_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point FIR interpolator.\n   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.\n   * @param[in]     L          upsample factor.\n   * @param[in]     numTaps    number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\n   */\n  arm_status arm_fir_interpolate_init_f32(\n  arm_fir_interpolate_instance_f32 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the high precision Q31 Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */\n    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */\n    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */\n  } arm_biquad_cas_df1_32x64_ins_q31;\n\n\n  /**\n   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cas_df1_32x64_q31(\n  const arm_biquad_cas_df1_32x64_ins_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format\n   */\n  void arm_biquad_cas_df1_32x64_init_q31(\n  arm_biquad_cas_df1_32x64_ins_q31 * S,\n  uint8_t numStages,\n  q31_t * pCoeffs,\n  q63_t * pState,\n  uint8_t postShift);\n\n\n  /**\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */\n    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\n  } arm_biquad_cascade_df2T_instance_f32;\n\n  /**\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */\n    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\n  } arm_biquad_cascade_stereo_df2T_instance_f32;\n\n  /**\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */\n    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\n  } arm_biquad_cascade_df2T_instance_f64;\n\n\n  /**\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in]  S          points to an instance of the filter data structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df2T_f32(\n  const arm_biquad_cascade_df2T_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\n   * @param[in]  S          points to an instance of the filter data structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_stereo_df2T_f32(\n  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in]  S          points to an instance of the filter data structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df2T_f64(\n  const arm_biquad_cascade_df2T_instance_f64 * S,\n  float64_t * pSrc,\n  float64_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the filter data structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   */\n  void arm_biquad_cascade_df2T_init_f32(\n  arm_biquad_cascade_df2T_instance_f32 * S,\n  uint8_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState);\n\n\n  /**\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the filter data structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   */\n  void arm_biquad_cascade_stereo_df2T_init_f32(\n  arm_biquad_cascade_stereo_df2T_instance_f32 * S,\n  uint8_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState);\n\n\n  /**\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the filter data structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   */\n  void arm_biquad_cascade_df2T_init_f64(\n  arm_biquad_cascade_df2T_instance_f64 * S,\n  uint8_t numStages,\n  float64_t * pCoeffs,\n  float64_t * pState);\n\n\n  /**\n   * @brief Instance structure for the Q15 FIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of filter stages. */\n    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */\n    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */\n  } arm_fir_lattice_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 FIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of filter stages. */\n    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */\n    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */\n  } arm_fir_lattice_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point FIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of filter stages. */\n    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */\n    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */\n  } arm_fir_lattice_instance_f32;\n\n\n  /**\n   * @brief Initialization function for the Q15 FIR lattice filter.\n   * @param[in] S          points to an instance of the Q15 FIR lattice structure.\n   * @param[in] numStages  number of filter stages.\n   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\n   * @param[in] pState     points to the state buffer.  The array is of length numStages.\n   */\n  void arm_fir_lattice_init_q15(\n  arm_fir_lattice_instance_q15 * S,\n  uint16_t numStages,\n  q15_t * pCoeffs,\n  q15_t * pState);\n\n\n  /**\n   * @brief Processing function for the Q15 FIR lattice filter.\n   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_lattice_q15(\n  const arm_fir_lattice_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for the Q31 FIR lattice filter.\n   * @param[in] S          points to an instance of the Q31 FIR lattice structure.\n   * @param[in] numStages  number of filter stages.\n   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\n   * @param[in] pState     points to the state buffer.   The array is of length numStages.\n   */\n  void arm_fir_lattice_init_q31(\n  arm_fir_lattice_instance_q31 * S,\n  uint16_t numStages,\n  q31_t * pCoeffs,\n  q31_t * pState);\n\n\n  /**\n   * @brief Processing function for the Q31 FIR lattice filter.\n   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_lattice_q31(\n  const arm_fir_lattice_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n/**\n * @brief Initialization function for the floating-point FIR lattice filter.\n * @param[in] S          points to an instance of the floating-point FIR lattice structure.\n * @param[in] numStages  number of filter stages.\n * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\n * @param[in] pState     points to the state buffer.  The array is of length numStages.\n */\n  void arm_fir_lattice_init_f32(\n  arm_fir_lattice_instance_f32 * S,\n  uint16_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState);\n\n\n  /**\n   * @brief Processing function for the floating-point FIR lattice filter.\n   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_lattice_f32(\n  const arm_fir_lattice_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 IIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of stages in the filter. */\n    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */\n    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */\n    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */\n  } arm_iir_lattice_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 IIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of stages in the filter. */\n    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */\n    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */\n    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */\n  } arm_iir_lattice_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point IIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of stages in the filter. */\n    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */\n    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */\n    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */\n  } arm_iir_lattice_instance_f32;\n\n\n  /**\n   * @brief Processing function for the floating-point IIR lattice filter.\n   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_f32(\n  const arm_iir_lattice_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for the floating-point IIR lattice filter.\n   * @param[in] S          points to an instance of the floating-point IIR lattice structure.\n   * @param[in] numStages  number of stages in the filter.\n   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.\n   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.\n   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.\n   * @param[in] blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_init_f32(\n  arm_iir_lattice_instance_f32 * S,\n  uint16_t numStages,\n  float32_t * pkCoeffs,\n  float32_t * pvCoeffs,\n  float32_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 IIR lattice filter.\n   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_q31(\n  const arm_iir_lattice_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for the Q31 IIR lattice filter.\n   * @param[in] S          points to an instance of the Q31 IIR lattice structure.\n   * @param[in] numStages  number of stages in the filter.\n   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.\n   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.\n   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.\n   * @param[in] blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_init_q31(\n  arm_iir_lattice_instance_q31 * S,\n  uint16_t numStages,\n  q31_t * pkCoeffs,\n  q31_t * pvCoeffs,\n  q31_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 IIR lattice filter.\n   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_q15(\n  const arm_iir_lattice_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n/**\n * @brief Initialization function for the Q15 IIR lattice filter.\n * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.\n * @param[in] numStages  number of stages in the filter.\n * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.\n * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.\n * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.\n * @param[in] blockSize  number of samples to process per call.\n */\n  void arm_iir_lattice_init_q15(\n  arm_iir_lattice_instance_q15 * S,\n  uint16_t numStages,\n  q15_t * pkCoeffs,\n  q15_t * pvCoeffs,\n  q15_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the floating-point LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\n    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */\n    float32_t mu;        /**< step size that controls filter coefficient updates. */\n  } arm_lms_instance_f32;\n\n\n  /**\n   * @brief Processing function for floating-point LMS filter.\n   * @param[in]  S          points to an instance of the floating-point LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_f32(\n  const arm_lms_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pRef,\n  float32_t * pOut,\n  float32_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for floating-point LMS filter.\n   * @param[in] S          points to an instance of the floating-point LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to the coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   */\n  void arm_lms_init_f32(\n  arm_lms_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  float32_t mu,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\n    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */\n    q15_t mu;            /**< step size that controls filter coefficient updates. */\n    uint32_t postShift;  /**< bit shift applied to coefficients. */\n  } arm_lms_instance_q15;\n\n\n  /**\n   * @brief Initialization function for the Q15 LMS filter.\n   * @param[in] S          points to an instance of the Q15 LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to the coefficient buffer.\n   * @param[in] pState     points to the state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   * @param[in] postShift  bit shift applied to coefficients.\n   */\n  void arm_lms_init_q15(\n  arm_lms_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  q15_t mu,\n  uint32_t blockSize,\n  uint32_t postShift);\n\n\n  /**\n   * @brief Processing function for Q15 LMS filter.\n   * @param[in]  S          points to an instance of the Q15 LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_q15(\n  const arm_lms_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pRef,\n  q15_t * pOut,\n  q15_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q31 LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\n    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */\n    q31_t mu;            /**< step size that controls filter coefficient updates. */\n    uint32_t postShift;  /**< bit shift applied to coefficients. */\n  } arm_lms_instance_q31;\n\n\n  /**\n   * @brief Processing function for Q31 LMS filter.\n   * @param[in]  S          points to an instance of the Q15 LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_q31(\n  const arm_lms_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pRef,\n  q31_t * pOut,\n  q31_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for Q31 LMS filter.\n   * @param[in] S          points to an instance of the Q31 LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   * @param[in] postShift  bit shift applied to coefficients.\n   */\n  void arm_lms_init_q31(\n  arm_lms_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  q31_t mu,\n  uint32_t blockSize,\n  uint32_t postShift);\n\n\n  /**\n   * @brief Instance structure for the floating-point normalized LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;     /**< number of coefficients in the filter. */\n    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */\n    float32_t mu;         /**< step size that control filter coefficient updates. */\n    float32_t energy;     /**< saves previous frame energy. */\n    float32_t x0;         /**< saves previous input sample. */\n  } arm_lms_norm_instance_f32;\n\n\n  /**\n   * @brief Processing function for floating-point normalized LMS filter.\n   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_norm_f32(\n  arm_lms_norm_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pRef,\n  float32_t * pOut,\n  float32_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for floating-point normalized LMS filter.\n   * @param[in] S          points to an instance of the floating-point LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   */\n  void arm_lms_norm_init_f32(\n  arm_lms_norm_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  float32_t mu,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q31 normalized LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;     /**< number of coefficients in the filter. */\n    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */\n    q31_t mu;             /**< step size that controls filter coefficient updates. */\n    uint8_t postShift;    /**< bit shift applied to coefficients. */\n    q31_t *recipTable;    /**< points to the reciprocal initial value table. */\n    q31_t energy;         /**< saves previous frame energy. */\n    q31_t x0;             /**< saves previous input sample. */\n  } arm_lms_norm_instance_q31;\n\n\n  /**\n   * @brief Processing function for Q31 normalized LMS filter.\n   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_norm_q31(\n  arm_lms_norm_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pRef,\n  q31_t * pOut,\n  q31_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for Q31 normalized LMS filter.\n   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   * @param[in] postShift  bit shift applied to coefficients.\n   */\n  void arm_lms_norm_init_q31(\n  arm_lms_norm_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  q31_t mu,\n  uint32_t blockSize,\n  uint8_t postShift);\n\n\n  /**\n   * @brief Instance structure for the Q15 normalized LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;     /**< Number of coefficients in the filter. */\n    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */\n    q15_t mu;             /**< step size that controls filter coefficient updates. */\n    uint8_t postShift;    /**< bit shift applied to coefficients. */\n    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */\n    q15_t energy;         /**< saves previous frame energy. */\n    q15_t x0;             /**< saves previous input sample. */\n  } arm_lms_norm_instance_q15;\n\n\n  /**\n   * @brief Processing function for Q15 normalized LMS filter.\n   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_norm_q15(\n  arm_lms_norm_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pRef,\n  q15_t * pOut,\n  q15_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for Q15 normalized LMS filter.\n   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   * @param[in] postShift  bit shift applied to coefficients.\n   */\n  void arm_lms_norm_init_q15(\n  arm_lms_norm_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  q15_t mu,\n  uint32_t blockSize,\n  uint8_t postShift);\n\n\n  /**\n   * @brief Correlation of floating-point sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n  void arm_correlate_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst);\n\n\n   /**\n   * @brief Correlation of Q15 sequences\n   * @param[in]  pSrcA     points to the first input sequence.\n   * @param[in]  srcALen   length of the first input sequence.\n   * @param[in]  pSrcB     points to the second input sequence.\n   * @param[in]  srcBLen   length of the second input sequence.\n   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   */\n  void arm_correlate_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch);\n\n\n  /**\n   * @brief Correlation of Q15 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n\n  void arm_correlate_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst);\n\n\n  /**\n   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n\n  void arm_correlate_fast_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst);\n\n\n  /**\n   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\n   * @param[in]  pSrcA     points to the first input sequence.\n   * @param[in]  srcALen   length of the first input sequence.\n   * @param[in]  pSrcB     points to the second input sequence.\n   * @param[in]  srcBLen   length of the second input sequence.\n   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   */\n  void arm_correlate_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch);\n\n\n  /**\n   * @brief Correlation of Q31 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n  void arm_correlate_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst);\n\n\n  /**\n   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n  void arm_correlate_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst);\n\n\n /**\n   * @brief Correlation of Q7 sequences.\n   * @param[in]  pSrcA      points to the first input sequence.\n   * @param[in]  srcALen    length of the first input sequence.\n   * @param[in]  pSrcB      points to the second input sequence.\n   * @param[in]  srcBLen    length of the second input sequence.\n   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\n   */\n  void arm_correlate_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Correlation of Q7 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n  void arm_correlate_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst);\n\n\n  /**\n   * @brief Instance structure for the floating-point sparse FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\n    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\n    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\n  } arm_fir_sparse_instance_f32;\n\n  /**\n   * @brief Instance structure for the Q31 sparse FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\n    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\n    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\n  } arm_fir_sparse_instance_q31;\n\n  /**\n   * @brief Instance structure for the Q15 sparse FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\n    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\n    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\n  } arm_fir_sparse_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q7 sparse FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\n    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\n    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\n  } arm_fir_sparse_instance_q7;\n\n\n  /**\n   * @brief Processing function for the floating-point sparse FIR filter.\n   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.\n   * @param[in]  pSrc        points to the block of input data.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.\n   * @param[in]  blockSize   number of input samples to process per call.\n   */\n  void arm_fir_sparse_f32(\n  arm_fir_sparse_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  float32_t * pScratchIn,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point sparse FIR filter.\n   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     pTapDelay  points to the array of offset times.\n   * @param[in]     maxDelay   maximum offset time supported.\n   * @param[in]     blockSize  number of samples that will be processed per block.\n   */\n  void arm_fir_sparse_init_f32(\n  arm_fir_sparse_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 sparse FIR filter.\n   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.\n   * @param[in]  pSrc        points to the block of input data.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.\n   * @param[in]  blockSize   number of input samples to process per call.\n   */\n  void arm_fir_sparse_q31(\n  arm_fir_sparse_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  q31_t * pScratchIn,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 sparse FIR filter.\n   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     pTapDelay  points to the array of offset times.\n   * @param[in]     maxDelay   maximum offset time supported.\n   * @param[in]     blockSize  number of samples that will be processed per block.\n   */\n  void arm_fir_sparse_init_q31(\n  arm_fir_sparse_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 sparse FIR filter.\n   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.\n   * @param[in]  pSrc         points to the block of input data.\n   * @param[out] pDst         points to the block of output data\n   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.\n   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.\n   * @param[in]  blockSize    number of input samples to process per call.\n   */\n  void arm_fir_sparse_q15(\n  arm_fir_sparse_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  q15_t * pScratchIn,\n  q31_t * pScratchOut,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 sparse FIR filter.\n   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     pTapDelay  points to the array of offset times.\n   * @param[in]     maxDelay   maximum offset time supported.\n   * @param[in]     blockSize  number of samples that will be processed per block.\n   */\n  void arm_fir_sparse_init_q15(\n  arm_fir_sparse_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q7 sparse FIR filter.\n   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.\n   * @param[in]  pSrc         points to the block of input data.\n   * @param[out] pDst         points to the block of output data\n   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.\n   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.\n   * @param[in]  blockSize    number of input samples to process per call.\n   */\n  void arm_fir_sparse_q7(\n  arm_fir_sparse_instance_q7 * S,\n  q7_t * pSrc,\n  q7_t * pDst,\n  q7_t * pScratchIn,\n  q31_t * pScratchOut,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q7 sparse FIR filter.\n   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     pTapDelay  points to the array of offset times.\n   * @param[in]     maxDelay   maximum offset time supported.\n   * @param[in]     blockSize  number of samples that will be processed per block.\n   */\n  void arm_fir_sparse_init_q7(\n  arm_fir_sparse_instance_q7 * S,\n  uint16_t numTaps,\n  q7_t * pCoeffs,\n  q7_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Floating-point sin_cos function.\n   * @param[in]  theta   input value in degrees\n   * @param[out] pSinVal  points to the processed sine output.\n   * @param[out] pCosVal  points to the processed cos output.\n   */\n  void arm_sin_cos_f32(\n  float32_t theta,\n  float32_t * pSinVal,\n  float32_t * pCosVal);\n\n\n  /**\n   * @brief  Q31 sin_cos function.\n   * @param[in]  theta    scaled input value in degrees\n   * @param[out] pSinVal  points to the processed sine output.\n   * @param[out] pCosVal  points to the processed cosine output.\n   */\n  void arm_sin_cos_q31(\n  q31_t theta,\n  q31_t * pSinVal,\n  q31_t * pCosVal);\n\n\n  /**\n   * @brief  Floating-point complex conjugate.\n   * @param[in]  pSrc        points to the input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_conj_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples);\n\n  /**\n   * @brief  Q31 complex conjugate.\n   * @param[in]  pSrc        points to the input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_conj_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q15 complex conjugate.\n   * @param[in]  pSrc        points to the input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_conj_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Floating-point complex magnitude squared\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_squared_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q31 complex magnitude squared\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_squared_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q15 complex magnitude squared\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_squared_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples);\n\n\n /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup PID PID Motor Control\n   *\n   * A Proportional Integral Derivative (PID) controller is a generic feedback control\n   * loop mechanism widely used in industrial control systems.\n   * A PID controller is the most commonly used type of feedback controller.\n   *\n   * This set of functions implements (PID) controllers\n   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample\n   * of data and each call to the function returns a single processed value.\n   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>\n   * is the input sample value. The functions return the output value.\n   *\n   * \\par Algorithm:\n   * <pre>\n   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\n   *    A0 = Kp + Ki + Kd\n   *    A1 = (-Kp ) - (2 * Kd )\n   *    A2 = Kd  </pre>\n   *\n   * \\par\n   * where \\c Kp is proportional constant, \\c Ki is Integral constant and \\c Kd is Derivative constant\n   *\n   * \\par\n   * \\image html PID.gif \"Proportional Integral Derivative Controller\"\n   *\n   * \\par\n   * The PID controller calculates an \"error\" value as the difference between\n   * the measured output and the reference input.\n   * The controller attempts to minimize the error by adjusting the process control inputs.\n   * The proportional value determines the reaction to the current error,\n   * the integral value determines the reaction based on the sum of recent errors,\n   * and the derivative value determines the reaction based on the rate at which the error has been changing.\n   *\n   * \\par Instance Structure\n   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\n   * A separate instance structure must be defined for each PID Controller.\n   * There are separate instance structure declarations for each of the 3 supported data types.\n   *\n   * \\par Reset Functions\n   * There is also an associated reset function for each data type which clears the state array.\n   *\n   * \\par Initialization Functions\n   * There is also an associated initialization function for each data type.\n   * The initialization function performs the following operations:\n   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\n   * - Zeros out the values in the state buffer.\n   *\n   * \\par\n   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\n   *\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the fixed-point versions of the PID Controller functions.\n   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup PID\n   * @{\n   */\n\n  /**\n   * @brief  Process function for the floating-point PID Control.\n   * @param[in,out] S   is an instance of the floating-point PID Control structure\n   * @param[in]     in  input sample to process\n   * @return out processed output sample.\n   */\n  static __INLINE float32_t arm_pid_f32(\n  arm_pid_instance_f32 * S,\n  float32_t in)\n  {\n    float32_t out;\n\n    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */\n    out = (S->A0 * in) +\n      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\n\n    /* Update state */\n    S->state[1] = S->state[0];\n    S->state[0] = in;\n    S->state[2] = out;\n\n    /* return to application */\n    return (out);\n\n  }\n\n  /**\n   * @brief  Process function for the Q31 PID Control.\n   * @param[in,out] S  points to an instance of the Q31 PID Control structure\n   * @param[in]     in  input sample to process\n   * @return out processed output sample.\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 64-bit accumulator.\n   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\n   * Thus, if the accumulator result overflows it wraps around rather than clip.\n   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\n   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\n   */\n  static __INLINE q31_t arm_pid_q31(\n  arm_pid_instance_q31 * S,\n  q31_t in)\n  {\n    q63_t acc;\n    q31_t out;\n\n    /* acc = A0 * x[n]  */\n    acc = (q63_t) S->A0 * in;\n\n    /* acc += A1 * x[n-1] */\n    acc += (q63_t) S->A1 * S->state[0];\n\n    /* acc += A2 * x[n-2]  */\n    acc += (q63_t) S->A2 * S->state[1];\n\n    /* convert output to 1.31 format to add y[n-1] */\n    out = (q31_t) (acc >> 31u);\n\n    /* out += y[n-1] */\n    out += S->state[2];\n\n    /* Update state */\n    S->state[1] = S->state[0];\n    S->state[0] = in;\n    S->state[2] = out;\n\n    /* return to application */\n    return (out);\n  }\n\n\n  /**\n   * @brief  Process function for the Q15 PID Control.\n   * @param[in,out] S   points to an instance of the Q15 PID Control structure\n   * @param[in]     in  input sample to process\n   * @return out processed output sample.\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using a 64-bit internal accumulator.\n   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\n   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\n   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\n   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\n   * Lastly, the accumulator is saturated to yield a result in 1.15 format.\n   */\n  static __INLINE q15_t arm_pid_q15(\n  arm_pid_instance_q15 * S,\n  q15_t in)\n  {\n    q63_t acc;\n    q15_t out;\n\n#ifndef ARM_MATH_CM0_FAMILY\n    __SIMD32_TYPE *vstate;\n\n    /* Implementation of PID controller */\n\n    /* acc = A0 * x[n]  */\n    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\n\n    /* acc += A1 * x[n-1] + A2 * x[n-2]  */\n    vstate = __SIMD32_CONST(S->state);\n    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\n#else\n    /* acc = A0 * x[n]  */\n    acc = ((q31_t) S->A0) * in;\n\n    /* acc += A1 * x[n-1] + A2 * x[n-2]  */\n    acc += (q31_t) S->A1 * S->state[0];\n    acc += (q31_t) S->A2 * S->state[1];\n#endif\n\n    /* acc += y[n-1] */\n    acc += (q31_t) S->state[2] << 15;\n\n    /* saturate the output */\n    out = (q15_t) (__SSAT((acc >> 15), 16));\n\n    /* Update state */\n    S->state[1] = S->state[0];\n    S->state[0] = in;\n    S->state[2] = out;\n\n    /* return to application */\n    return (out);\n  }\n\n  /**\n   * @} end of PID group\n   */\n\n\n  /**\n   * @brief Floating-point matrix inverse.\n   * @param[in]  src   points to the instance of the input floating-point matrix structure.\n   * @param[out] dst   points to the instance of the output floating-point matrix structure.\n   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\n   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\n   */\n  arm_status arm_mat_inverse_f32(\n  const arm_matrix_instance_f32 * src,\n  arm_matrix_instance_f32 * dst);\n\n\n  /**\n   * @brief Floating-point matrix inverse.\n   * @param[in]  src   points to the instance of the input floating-point matrix structure.\n   * @param[out] dst   points to the instance of the output floating-point matrix structure.\n   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\n   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\n   */\n  arm_status arm_mat_inverse_f64(\n  const arm_matrix_instance_f64 * src,\n  arm_matrix_instance_f64 * dst);\n\n\n\n  /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup clarke Vector Clarke Transform\n   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\n   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\n   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\n   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\n   * \\image html clarke.gif Stator current space vector and its components in (a,b).\n   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\n   * can be calculated using only <code>Ia</code> and <code>Ib</code>.\n   *\n   * The function operates on a single sample of data and each call to the function returns the processed output.\n   * The library provides separate functions for Q31 and floating-point data types.\n   * \\par Algorithm\n   * \\image html clarkeFormula.gif\n   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\n   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the Q31 version of the Clarke transform.\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup clarke\n   * @{\n   */\n\n  /**\n   *\n   * @brief  Floating-point Clarke transform\n   * @param[in]  Ia       input three-phase coordinate <code>a</code>\n   * @param[in]  Ib       input three-phase coordinate <code>b</code>\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\n   */\n  static __INLINE void arm_clarke_f32(\n  float32_t Ia,\n  float32_t Ib,\n  float32_t * pIalpha,\n  float32_t * pIbeta)\n  {\n    /* Calculate pIalpha using the equation, pIalpha = Ia */\n    *pIalpha = Ia;\n\n    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\n    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\n  }\n\n\n  /**\n   * @brief  Clarke transform for Q31 version\n   * @param[in]  Ia       input three-phase coordinate <code>a</code>\n   * @param[in]  Ib       input three-phase coordinate <code>b</code>\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 32-bit accumulator.\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\n   * There is saturation on the addition, hence there is no risk of overflow.\n   */\n  static __INLINE void arm_clarke_q31(\n  q31_t Ia,\n  q31_t Ib,\n  q31_t * pIalpha,\n  q31_t * pIbeta)\n  {\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\n\n    /* Calculating pIalpha from Ia by equation pIalpha = Ia */\n    *pIalpha = Ia;\n\n    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\n    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\n\n    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\n    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\n\n    /* pIbeta is calculated by adding the intermediate products */\n    *pIbeta = __QADD(product1, product2);\n  }\n\n  /**\n   * @} end of clarke group\n   */\n\n  /**\n   * @brief  Converts the elements of the Q7 vector to Q31 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_q7_to_q31(\n  q7_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n\n  /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup inv_clarke Vector Inverse Clarke Transform\n   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\n   *\n   * The function operates on a single sample of data and each call to the function returns the processed output.\n   * The library provides separate functions for Q31 and floating-point data types.\n   * \\par Algorithm\n   * \\image html clarkeInvFormula.gif\n   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\n   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the Q31 version of the Clarke transform.\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup inv_clarke\n   * @{\n   */\n\n   /**\n   * @brief  Floating-point Inverse Clarke transform\n   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha\n   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta\n   * @param[out] pIa     points to output three-phase coordinate <code>a</code>\n   * @param[out] pIb     points to output three-phase coordinate <code>b</code>\n   */\n  static __INLINE void arm_inv_clarke_f32(\n  float32_t Ialpha,\n  float32_t Ibeta,\n  float32_t * pIa,\n  float32_t * pIb)\n  {\n    /* Calculating pIa from Ialpha by equation pIa = Ialpha */\n    *pIa = Ialpha;\n\n    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\n    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\n  }\n\n\n  /**\n   * @brief  Inverse Clarke transform for Q31 version\n   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha\n   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta\n   * @param[out] pIa     points to output three-phase coordinate <code>a</code>\n   * @param[out] pIb     points to output three-phase coordinate <code>b</code>\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 32-bit accumulator.\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\n   * There is saturation on the subtraction, hence there is no risk of overflow.\n   */\n  static __INLINE void arm_inv_clarke_q31(\n  q31_t Ialpha,\n  q31_t Ibeta,\n  q31_t * pIa,\n  q31_t * pIb)\n  {\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\n\n    /* Calculating pIa from Ialpha by equation pIa = Ialpha */\n    *pIa = Ialpha;\n\n    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\n    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\n\n    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\n    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\n\n    /* pIb is calculated by subtracting the products */\n    *pIb = __QSUB(product2, product1);\n  }\n\n  /**\n   * @} end of inv_clarke group\n   */\n\n  /**\n   * @brief  Converts the elements of the Q7 vector to Q15 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_q7_to_q15(\n  q7_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n\n  /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup park Vector Park Transform\n   *\n   * Forward Park transform converts the input two-coordinate vector to flux and torque components.\n   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\n   * from the stationary to the moving reference frame and control the spatial relationship between\n   * the stator vector current and rotor flux vector.\n   * If we consider the d axis aligned with the rotor flux, the diagram below shows the\n   * current vector and the relationship from the two reference frames:\n   * \\image html park.gif \"Stator current space vector and its component in (a,b) and in the d,q rotating reference frame\"\n   *\n   * The function operates on a single sample of data and each call to the function returns the processed output.\n   * The library provides separate functions for Q31 and floating-point data types.\n   * \\par Algorithm\n   * \\image html parkFormula.gif\n   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\n   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\n   * cosine and sine values of theta (rotor flux position).\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the Q31 version of the Park transform.\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup park\n   * @{\n   */\n\n  /**\n   * @brief Floating-point Park transform\n   * @param[in]  Ialpha  input two-phase vector coordinate alpha\n   * @param[in]  Ibeta   input two-phase vector coordinate beta\n   * @param[out] pId     points to output   rotor reference frame d\n   * @param[out] pIq     points to output   rotor reference frame q\n   * @param[in]  sinVal  sine value of rotation angle theta\n   * @param[in]  cosVal  cosine value of rotation angle theta\n   *\n   * The function implements the forward Park transform.\n   *\n   */\n  static __INLINE void arm_park_f32(\n  float32_t Ialpha,\n  float32_t Ibeta,\n  float32_t * pId,\n  float32_t * pIq,\n  float32_t sinVal,\n  float32_t cosVal)\n  {\n    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\n    *pId = Ialpha * cosVal + Ibeta * sinVal;\n\n    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\n    *pIq = -Ialpha * sinVal + Ibeta * cosVal;\n  }\n\n\n  /**\n   * @brief  Park transform for Q31 version\n   * @param[in]  Ialpha  input two-phase vector coordinate alpha\n   * @param[in]  Ibeta   input two-phase vector coordinate beta\n   * @param[out] pId     points to output rotor reference frame d\n   * @param[out] pIq     points to output rotor reference frame q\n   * @param[in]  sinVal  sine value of rotation angle theta\n   * @param[in]  cosVal  cosine value of rotation angle theta\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 32-bit accumulator.\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\n   * There is saturation on the addition and subtraction, hence there is no risk of overflow.\n   */\n  static __INLINE void arm_park_q31(\n  q31_t Ialpha,\n  q31_t Ibeta,\n  q31_t * pId,\n  q31_t * pIq,\n  q31_t sinVal,\n  q31_t cosVal)\n  {\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\n    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */\n\n    /* Intermediate product is calculated by (Ialpha * cosVal) */\n    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\n\n    /* Intermediate product is calculated by (Ibeta * sinVal) */\n    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\n\n\n    /* Intermediate product is calculated by (Ialpha * sinVal) */\n    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\n\n    /* Intermediate product is calculated by (Ibeta * cosVal) */\n    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\n\n    /* Calculate pId by adding the two intermediate products 1 and 2 */\n    *pId = __QADD(product1, product2);\n\n    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\n    *pIq = __QSUB(product4, product3);\n  }\n\n  /**\n   * @} end of park group\n   */\n\n  /**\n   * @brief  Converts the elements of the Q7 vector to floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q7_to_float(\n  q7_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup inv_park Vector Inverse Park transform\n   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\n   *\n   * The function operates on a single sample of data and each call to the function returns the processed output.\n   * The library provides separate functions for Q31 and floating-point data types.\n   * \\par Algorithm\n   * \\image html parkInvFormula.gif\n   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\n   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\n   * cosine and sine values of theta (rotor flux position).\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the Q31 version of the Park transform.\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup inv_park\n   * @{\n   */\n\n   /**\n   * @brief  Floating-point Inverse Park transform\n   * @param[in]  Id       input coordinate of rotor reference frame d\n   * @param[in]  Iq       input coordinate of rotor reference frame q\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\n   * @param[in]  sinVal   sine value of rotation angle theta\n   * @param[in]  cosVal   cosine value of rotation angle theta\n   */\n  static __INLINE void arm_inv_park_f32(\n  float32_t Id,\n  float32_t Iq,\n  float32_t * pIalpha,\n  float32_t * pIbeta,\n  float32_t sinVal,\n  float32_t cosVal)\n  {\n    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\n    *pIalpha = Id * cosVal - Iq * sinVal;\n\n    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\n    *pIbeta = Id * sinVal + Iq * cosVal;\n  }\n\n\n  /**\n   * @brief  Inverse Park transform for   Q31 version\n   * @param[in]  Id       input coordinate of rotor reference frame d\n   * @param[in]  Iq       input coordinate of rotor reference frame q\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\n   * @param[in]  sinVal   sine value of rotation angle theta\n   * @param[in]  cosVal   cosine value of rotation angle theta\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 32-bit accumulator.\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\n   * There is saturation on the addition, hence there is no risk of overflow.\n   */\n  static __INLINE void arm_inv_park_q31(\n  q31_t Id,\n  q31_t Iq,\n  q31_t * pIalpha,\n  q31_t * pIbeta,\n  q31_t sinVal,\n  q31_t cosVal)\n  {\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\n    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */\n\n    /* Intermediate product is calculated by (Id * cosVal) */\n    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\n\n    /* Intermediate product is calculated by (Iq * sinVal) */\n    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\n\n\n    /* Intermediate product is calculated by (Id * sinVal) */\n    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\n\n    /* Intermediate product is calculated by (Iq * cosVal) */\n    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\n\n    /* Calculate pIalpha by using the two intermediate products 1 and 2 */\n    *pIalpha = __QSUB(product1, product2);\n\n    /* Calculate pIbeta by using the two intermediate products 3 and 4 */\n    *pIbeta = __QADD(product4, product3);\n  }\n\n  /**\n   * @} end of Inverse park group\n   */\n\n\n  /**\n   * @brief  Converts the elements of the Q31 vector to floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q31_to_float(\n  q31_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n  /**\n   * @ingroup groupInterpolation\n   */\n\n  /**\n   * @defgroup LinearInterpolate Linear Interpolation\n   *\n   * Linear interpolation is a method of curve fitting using linear polynomials.\n   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\n   *\n   * \\par\n   * \\image html LinearInterp.gif \"Linear interpolation\"\n   *\n   * \\par\n   * A  Linear Interpolate function calculates an output value(y), for the input(x)\n   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\n   *\n   * \\par Algorithm:\n   * <pre>\n   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\n   *       where x0, x1 are nearest values of input x\n   *             y0, y1 are nearest values to output y\n   * </pre>\n   *\n   * \\par\n   * This set of functions implements Linear interpolation process\n   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single\n   * sample of data and each call to the function returns a single processed value.\n   * <code>S</code> points to an instance of the Linear Interpolate function data structure.\n   * <code>x</code> is the input sample value. The functions returns the output value.\n   *\n   * \\par\n   * if x is outside of the table boundary, Linear interpolation returns first value of the table\n   * if x is below input range and returns last value of table if x is above range.\n   */\n\n  /**\n   * @addtogroup LinearInterpolate\n   * @{\n   */\n\n  /**\n   * @brief  Process function for the floating-point Linear Interpolation Function.\n   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure\n   * @param[in]     x  input sample to process\n   * @return y processed output sample.\n   *\n   */\n  static __INLINE float32_t arm_linear_interp_f32(\n  arm_linear_interp_instance_f32 * S,\n  float32_t x)\n  {\n    float32_t y;\n    float32_t x0, x1;                            /* Nearest input values */\n    float32_t y0, y1;                            /* Nearest output values */\n    float32_t xSpacing = S->xSpacing;            /* spacing between input values */\n    int32_t i;                                   /* Index variable */\n    float32_t *pYData = S->pYData;               /* pointer to output table */\n\n    /* Calculation of index */\n    i = (int32_t) ((x - S->x1) / xSpacing);\n\n    if(i < 0)\n    {\n      /* Iniatilize output for below specified range as least output value of table */\n      y = pYData[0];\n    }\n    else if((uint32_t)i >= S->nValues)\n    {\n      /* Iniatilize output for above specified range as last output value of table */\n      y = pYData[S->nValues - 1];\n    }\n    else\n    {\n      /* Calculation of nearest input values */\n      x0 = S->x1 +  i      * xSpacing;\n      x1 = S->x1 + (i + 1) * xSpacing;\n\n      /* Read of nearest output values */\n      y0 = pYData[i];\n      y1 = pYData[i + 1];\n\n      /* Calculation of output */\n      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\n\n    }\n\n    /* returns output value */\n    return (y);\n  }\n\n\n   /**\n   *\n   * @brief  Process function for the Q31 Linear Interpolation Function.\n   * @param[in] pYData   pointer to Q31 Linear Interpolation table\n   * @param[in] x        input sample to process\n   * @param[in] nValues  number of table values\n   * @return y processed output sample.\n   *\n   * \\par\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\n   * This function can support maximum of table size 2^12.\n   *\n   */\n  static __INLINE q31_t arm_linear_interp_q31(\n  q31_t * pYData,\n  q31_t x,\n  uint32_t nValues)\n  {\n    q31_t y;                                     /* output */\n    q31_t y0, y1;                                /* Nearest output values */\n    q31_t fract;                                 /* fractional part */\n    int32_t index;                               /* Index to read nearest output values */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    index = ((x & (q31_t)0xFFF00000) >> 20);\n\n    if(index >= (int32_t)(nValues - 1))\n    {\n      return (pYData[nValues - 1]);\n    }\n    else if(index < 0)\n    {\n      return (pYData[0]);\n    }\n    else\n    {\n      /* 20 bits for the fractional part */\n      /* shift left by 11 to keep fract in 1.31 format */\n      fract = (x & 0x000FFFFF) << 11;\n\n      /* Read two nearest output values from the index in 1.31(q31) format */\n      y0 = pYData[index];\n      y1 = pYData[index + 1];\n\n      /* Calculation of y0 * (1-fract) and y is in 2.30 format */\n      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\n\n      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\n      y += ((q31_t) (((q63_t) y1 * fract) >> 32));\n\n      /* Convert y to 1.31 format */\n      return (y << 1u);\n    }\n  }\n\n\n  /**\n   *\n   * @brief  Process function for the Q15 Linear Interpolation Function.\n   * @param[in] pYData   pointer to Q15 Linear Interpolation table\n   * @param[in] x        input sample to process\n   * @param[in] nValues  number of table values\n   * @return y processed output sample.\n   *\n   * \\par\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\n   * This function can support maximum of table size 2^12.\n   *\n   */\n  static __INLINE q15_t arm_linear_interp_q15(\n  q15_t * pYData,\n  q31_t x,\n  uint32_t nValues)\n  {\n    q63_t y;                                     /* output */\n    q15_t y0, y1;                                /* Nearest output values */\n    q31_t fract;                                 /* fractional part */\n    int32_t index;                               /* Index to read nearest output values */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    index = ((x & (int32_t)0xFFF00000) >> 20);\n\n    if(index >= (int32_t)(nValues - 1))\n    {\n      return (pYData[nValues - 1]);\n    }\n    else if(index < 0)\n    {\n      return (pYData[0]);\n    }\n    else\n    {\n      /* 20 bits for the fractional part */\n      /* fract is in 12.20 format */\n      fract = (x & 0x000FFFFF);\n\n      /* Read two nearest output values from the index */\n      y0 = pYData[index];\n      y1 = pYData[index + 1];\n\n      /* Calculation of y0 * (1-fract) and y is in 13.35 format */\n      y = ((q63_t) y0 * (0xFFFFF - fract));\n\n      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\n      y += ((q63_t) y1 * (fract));\n\n      /* convert y to 1.15 format */\n      return (q15_t) (y >> 20);\n    }\n  }\n\n\n  /**\n   *\n   * @brief  Process function for the Q7 Linear Interpolation Function.\n   * @param[in] pYData   pointer to Q7 Linear Interpolation table\n   * @param[in] x        input sample to process\n   * @param[in] nValues  number of table values\n   * @return y processed output sample.\n   *\n   * \\par\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\n   * This function can support maximum of table size 2^12.\n   */\n  static __INLINE q7_t arm_linear_interp_q7(\n  q7_t * pYData,\n  q31_t x,\n  uint32_t nValues)\n  {\n    q31_t y;                                     /* output */\n    q7_t y0, y1;                                 /* Nearest output values */\n    q31_t fract;                                 /* fractional part */\n    uint32_t index;                              /* Index to read nearest output values */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    if (x < 0)\n    {\n      return (pYData[0]);\n    }\n    index = (x >> 20) & 0xfff;\n\n    if(index >= (nValues - 1))\n    {\n      return (pYData[nValues - 1]);\n    }\n    else\n    {\n      /* 20 bits for the fractional part */\n      /* fract is in 12.20 format */\n      fract = (x & 0x000FFFFF);\n\n      /* Read two nearest output values from the index and are in 1.7(q7) format */\n      y0 = pYData[index];\n      y1 = pYData[index + 1];\n\n      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\n      y = ((y0 * (0xFFFFF - fract)));\n\n      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\n      y += (y1 * fract);\n\n      /* convert y to 1.7(q7) format */\n      return (q7_t) (y >> 20);\n     }\n  }\n\n  /**\n   * @} end of LinearInterpolate group\n   */\n\n  /**\n   * @brief  Fast approximation to the trigonometric sine function for floating-point data.\n   * @param[in] x  input value in radians.\n   * @return  sin(x).\n   */\n  float32_t arm_sin_f32(\n  float32_t x);\n\n\n  /**\n   * @brief  Fast approximation to the trigonometric sine function for Q31 data.\n   * @param[in] x  Scaled input value in radians.\n   * @return  sin(x).\n   */\n  q31_t arm_sin_q31(\n  q31_t x);\n\n\n  /**\n   * @brief  Fast approximation to the trigonometric sine function for Q15 data.\n   * @param[in] x  Scaled input value in radians.\n   * @return  sin(x).\n   */\n  q15_t arm_sin_q15(\n  q15_t x);\n\n\n  /**\n   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.\n   * @param[in] x  input value in radians.\n   * @return  cos(x).\n   */\n  float32_t arm_cos_f32(\n  float32_t x);\n\n\n  /**\n   * @brief Fast approximation to the trigonometric cosine function for Q31 data.\n   * @param[in] x  Scaled input value in radians.\n   * @return  cos(x).\n   */\n  q31_t arm_cos_q31(\n  q31_t x);\n\n\n  /**\n   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.\n   * @param[in] x  Scaled input value in radians.\n   * @return  cos(x).\n   */\n  q15_t arm_cos_q15(\n  q15_t x);\n\n\n  /**\n   * @ingroup groupFastMath\n   */\n\n\n  /**\n   * @defgroup SQRT Square Root\n   *\n   * Computes the square root of a number.\n   * There are separate functions for Q15, Q31, and floating-point data types.\n   * The square root function is computed using the Newton-Raphson algorithm.\n   * This is an iterative algorithm of the form:\n   * <pre>\n   *      x1 = x0 - f(x0)/f'(x0)\n   * </pre>\n   * where <code>x1</code> is the current estimate,\n   * <code>x0</code> is the previous estimate, and\n   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\n   * For the square root function, the algorithm reduces to:\n   * <pre>\n   *     x0 = in/2                         [initial guess]\n   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]\n   * </pre>\n   */\n\n\n  /**\n   * @addtogroup SQRT\n   * @{\n   */\n\n  /**\n   * @brief  Floating-point square root function.\n   * @param[in]  in    input value.\n   * @param[out] pOut  square root of input value.\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\n   * <code>in</code> is negative value and returns zero output for negative values.\n   */\n  static __INLINE arm_status arm_sqrt_f32(\n  float32_t in,\n  float32_t * pOut)\n  {\n    if(in >= 0.0f)\n    {\n\n#if   (__FPU_USED == 1) && defined ( __CC_ARM   )\n      *pOut = __sqrtf(in);\n#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n      *pOut = __builtin_sqrtf(in);\n#elif (__FPU_USED == 1) && defined(__GNUC__)\n      *pOut = __builtin_sqrtf(in);\n#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\n      __ASM(\"VSQRT.F32 %0,%1\" : \"=t\"(*pOut) : \"t\"(in));\n#else\n      *pOut = sqrtf(in);\n#endif\n\n      return (ARM_MATH_SUCCESS);\n    }\n    else\n    {\n      *pOut = 0.0f;\n      return (ARM_MATH_ARGUMENT_ERROR);\n    }\n  }\n\n\n  /**\n   * @brief Q31 square root function.\n   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\n   * @param[out] pOut  square root of input value.\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\n   * <code>in</code> is negative value and returns zero output for negative values.\n   */\n  arm_status arm_sqrt_q31(\n  q31_t in,\n  q31_t * pOut);\n\n\n  /**\n   * @brief  Q15 square root function.\n   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\n   * @param[out] pOut  square root of input value.\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\n   * <code>in</code> is negative value and returns zero output for negative values.\n   */\n  arm_status arm_sqrt_q15(\n  q15_t in,\n  q15_t * pOut);\n\n  /**\n   * @} end of SQRT group\n   */\n\n\n  /**\n   * @brief floating-point Circular write function.\n   */\n  static __INLINE void arm_circularWrite_f32(\n  int32_t * circBuffer,\n  int32_t L,\n  uint16_t * writeOffset,\n  int32_t bufferInc,\n  const int32_t * src,\n  int32_t srcInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0u;\n    int32_t wOffset;\n\n    /* Copy the value of Index pointer that points\n     * to the current location where the input samples to be copied */\n    wOffset = *writeOffset;\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while(i > 0u)\n    {\n      /* copy the input sample to the circular buffer */\n      circBuffer[wOffset] = *src;\n\n      /* Update the input pointer */\n      src += srcInc;\n\n      /* Circularly update wOffset.  Watch out for positive and negative value */\n      wOffset += bufferInc;\n      if(wOffset >= L)\n        wOffset -= L;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *writeOffset = (uint16_t)wOffset;\n  }\n\n\n\n  /**\n   * @brief floating-point Circular Read function.\n   */\n  static __INLINE void arm_circularRead_f32(\n  int32_t * circBuffer,\n  int32_t L,\n  int32_t * readOffset,\n  int32_t bufferInc,\n  int32_t * dst,\n  int32_t * dst_base,\n  int32_t dst_length,\n  int32_t dstInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0u;\n    int32_t rOffset, dst_end;\n\n    /* Copy the value of Index pointer that points\n     * to the current location from where the input samples to be read */\n    rOffset = *readOffset;\n    dst_end = (int32_t) (dst_base + dst_length);\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while(i > 0u)\n    {\n      /* copy the sample from the circular buffer to the destination buffer */\n      *dst = circBuffer[rOffset];\n\n      /* Update the input pointer */\n      dst += dstInc;\n\n      if(dst == (int32_t *) dst_end)\n      {\n        dst = dst_base;\n      }\n\n      /* Circularly update rOffset.  Watch out for positive and negative value  */\n      rOffset += bufferInc;\n\n      if(rOffset >= L)\n      {\n        rOffset -= L;\n      }\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *readOffset = rOffset;\n  }\n\n\n  /**\n   * @brief Q15 Circular write function.\n   */\n  static __INLINE void arm_circularWrite_q15(\n  q15_t * circBuffer,\n  int32_t L,\n  uint16_t * writeOffset,\n  int32_t bufferInc,\n  const q15_t * src,\n  int32_t srcInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0u;\n    int32_t wOffset;\n\n    /* Copy the value of Index pointer that points\n     * to the current location where the input samples to be copied */\n    wOffset = *writeOffset;\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while(i > 0u)\n    {\n      /* copy the input sample to the circular buffer */\n      circBuffer[wOffset] = *src;\n\n      /* Update the input pointer */\n      src += srcInc;\n\n      /* Circularly update wOffset.  Watch out for positive and negative value */\n      wOffset += bufferInc;\n      if(wOffset >= L)\n        wOffset -= L;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *writeOffset = (uint16_t)wOffset;\n  }\n\n\n  /**\n   * @brief Q15 Circular Read function.\n   */\n  static __INLINE void arm_circularRead_q15(\n  q15_t * circBuffer,\n  int32_t L,\n  int32_t * readOffset,\n  int32_t bufferInc,\n  q15_t * dst,\n  q15_t * dst_base,\n  int32_t dst_length,\n  int32_t dstInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0;\n    int32_t rOffset, dst_end;\n\n    /* Copy the value of Index pointer that points\n     * to the current location from where the input samples to be read */\n    rOffset = *readOffset;\n\n    dst_end = (int32_t) (dst_base + dst_length);\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while(i > 0u)\n    {\n      /* copy the sample from the circular buffer to the destination buffer */\n      *dst = circBuffer[rOffset];\n\n      /* Update the input pointer */\n      dst += dstInc;\n\n      if(dst == (q15_t *) dst_end)\n      {\n        dst = dst_base;\n      }\n\n      /* Circularly update wOffset.  Watch out for positive and negative value */\n      rOffset += bufferInc;\n\n      if(rOffset >= L)\n      {\n        rOffset -= L;\n      }\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *readOffset = rOffset;\n  }\n\n\n  /**\n   * @brief Q7 Circular write function.\n   */\n  static __INLINE void arm_circularWrite_q7(\n  q7_t * circBuffer,\n  int32_t L,\n  uint16_t * writeOffset,\n  int32_t bufferInc,\n  const q7_t * src,\n  int32_t srcInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0u;\n    int32_t wOffset;\n\n    /* Copy the value of Index pointer that points\n     * to the current location where the input samples to be copied */\n    wOffset = *writeOffset;\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while(i > 0u)\n    {\n      /* copy the input sample to the circular buffer */\n      circBuffer[wOffset] = *src;\n\n      /* Update the input pointer */\n      src += srcInc;\n\n      /* Circularly update wOffset.  Watch out for positive and negative value */\n      wOffset += bufferInc;\n      if(wOffset >= L)\n        wOffset -= L;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *writeOffset = (uint16_t)wOffset;\n  }\n\n\n  /**\n   * @brief Q7 Circular Read function.\n   */\n  static __INLINE void arm_circularRead_q7(\n  q7_t * circBuffer,\n  int32_t L,\n  int32_t * readOffset,\n  int32_t bufferInc,\n  q7_t * dst,\n  q7_t * dst_base,\n  int32_t dst_length,\n  int32_t dstInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0;\n    int32_t rOffset, dst_end;\n\n    /* Copy the value of Index pointer that points\n     * to the current location from where the input samples to be read */\n    rOffset = *readOffset;\n\n    dst_end = (int32_t) (dst_base + dst_length);\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while(i > 0u)\n    {\n      /* copy the sample from the circular buffer to the destination buffer */\n      *dst = circBuffer[rOffset];\n\n      /* Update the input pointer */\n      dst += dstInc;\n\n      if(dst == (q7_t *) dst_end)\n      {\n        dst = dst_base;\n      }\n\n      /* Circularly update rOffset.  Watch out for positive and negative value */\n      rOffset += bufferInc;\n\n      if(rOffset >= L)\n      {\n        rOffset -= L;\n      }\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *readOffset = rOffset;\n  }\n\n\n  /**\n   * @brief  Sum of the squares of the elements of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_power_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q63_t * pResult);\n\n\n  /**\n   * @brief  Sum of the squares of the elements of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_power_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Sum of the squares of the elements of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_power_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q63_t * pResult);\n\n\n  /**\n   * @brief  Sum of the squares of the elements of a Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_power_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Mean value of a Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_mean_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * pResult);\n\n\n  /**\n   * @brief  Mean value of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_mean_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult);\n\n\n  /**\n   * @brief  Mean value of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_mean_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Mean value of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_mean_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Variance of the elements of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_var_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Variance of the elements of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_var_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Variance of the elements of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_var_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult);\n\n\n  /**\n   * @brief  Root Mean Square of the elements of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_rms_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Root Mean Square of the elements of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_rms_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Root Mean Square of the elements of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_rms_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult);\n\n\n  /**\n   * @brief  Standard deviation of the elements of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_std_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Standard deviation of the elements of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_std_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Standard deviation of the elements of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_std_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult);\n\n\n  /**\n   * @brief  Floating-point complex magnitude\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q31 complex magnitude\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q15 complex magnitude\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q15 complex dot product\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   * @param[out] realResult  real part of the result returned here\n   * @param[out] imagResult  imaginary part of the result returned here\n   */\n  void arm_cmplx_dot_prod_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  uint32_t numSamples,\n  q31_t * realResult,\n  q31_t * imagResult);\n\n\n  /**\n   * @brief  Q31 complex dot product\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   * @param[out] realResult  real part of the result returned here\n   * @param[out] imagResult  imaginary part of the result returned here\n   */\n  void arm_cmplx_dot_prod_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  uint32_t numSamples,\n  q63_t * realResult,\n  q63_t * imagResult);\n\n\n  /**\n   * @brief  Floating-point complex dot product\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   * @param[out] realResult  real part of the result returned here\n   * @param[out] imagResult  imaginary part of the result returned here\n   */\n  void arm_cmplx_dot_prod_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  uint32_t numSamples,\n  float32_t * realResult,\n  float32_t * imagResult);\n\n\n  /**\n   * @brief  Q15 complex-by-real multiplication\n   * @param[in]  pSrcCmplx   points to the complex input vector\n   * @param[in]  pSrcReal    points to the real input vector\n   * @param[out] pCmplxDst   points to the complex output vector\n   * @param[in]  numSamples  number of samples in each vector\n   */\n  void arm_cmplx_mult_real_q15(\n  q15_t * pSrcCmplx,\n  q15_t * pSrcReal,\n  q15_t * pCmplxDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q31 complex-by-real multiplication\n   * @param[in]  pSrcCmplx   points to the complex input vector\n   * @param[in]  pSrcReal    points to the real input vector\n   * @param[out] pCmplxDst   points to the complex output vector\n   * @param[in]  numSamples  number of samples in each vector\n   */\n  void arm_cmplx_mult_real_q31(\n  q31_t * pSrcCmplx,\n  q31_t * pSrcReal,\n  q31_t * pCmplxDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Floating-point complex-by-real multiplication\n   * @param[in]  pSrcCmplx   points to the complex input vector\n   * @param[in]  pSrcReal    points to the real input vector\n   * @param[out] pCmplxDst   points to the complex output vector\n   * @param[in]  numSamples  number of samples in each vector\n   */\n  void arm_cmplx_mult_real_f32(\n  float32_t * pSrcCmplx,\n  float32_t * pSrcReal,\n  float32_t * pCmplxDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Minimum value of a Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] result     is output pointer\n   * @param[in]  index      is the array index of the minimum value in the input buffer.\n   */\n  void arm_min_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * result,\n  uint32_t * index);\n\n\n  /**\n   * @brief  Minimum value of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output pointer\n   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.\n   */\n  void arm_min_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult,\n  uint32_t * pIndex);\n\n\n  /**\n   * @brief  Minimum value of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output pointer\n   * @param[out] pIndex     is the array index of the minimum value in the input buffer.\n   */\n  void arm_min_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult,\n  uint32_t * pIndex);\n\n\n  /**\n   * @brief  Minimum value of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output pointer\n   * @param[out] pIndex     is the array index of the minimum value in the input buffer.\n   */\n  void arm_min_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult,\n  uint32_t * pIndex);\n\n\n/**\n * @brief Maximum value of a Q7 vector.\n * @param[in]  pSrc       points to the input buffer\n * @param[in]  blockSize  length of the input vector\n * @param[out] pResult    maximum value returned here\n * @param[out] pIndex     index of maximum value returned here\n */\n  void arm_max_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * pResult,\n  uint32_t * pIndex);\n\n\n/**\n * @brief Maximum value of a Q15 vector.\n * @param[in]  pSrc       points to the input buffer\n * @param[in]  blockSize  length of the input vector\n * @param[out] pResult    maximum value returned here\n * @param[out] pIndex     index of maximum value returned here\n */\n  void arm_max_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult,\n  uint32_t * pIndex);\n\n\n/**\n * @brief Maximum value of a Q31 vector.\n * @param[in]  pSrc       points to the input buffer\n * @param[in]  blockSize  length of the input vector\n * @param[out] pResult    maximum value returned here\n * @param[out] pIndex     index of maximum value returned here\n */\n  void arm_max_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult,\n  uint32_t * pIndex);\n\n\n/**\n * @brief Maximum value of a floating-point vector.\n * @param[in]  pSrc       points to the input buffer\n * @param[in]  blockSize  length of the input vector\n * @param[out] pResult    maximum value returned here\n * @param[out] pIndex     index of maximum value returned here\n */\n  void arm_max_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult,\n  uint32_t * pIndex);\n\n\n  /**\n   * @brief  Q15 complex-by-complex multiplication\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_mult_cmplx_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q31 complex-by-complex multiplication\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_mult_cmplx_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Floating-point complex-by-complex multiplication\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_mult_cmplx_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief Converts the elements of the floating-point vector to Q31 vector.\n   * @param[in]  pSrc       points to the floating-point input vector\n   * @param[out] pDst       points to the Q31 output vector\n   * @param[in]  blockSize  length of the input vector\n   */\n  void arm_float_to_q31(\n  float32_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Converts the elements of the floating-point vector to Q15 vector.\n   * @param[in]  pSrc       points to the floating-point input vector\n   * @param[out] pDst       points to the Q15 output vector\n   * @param[in]  blockSize  length of the input vector\n   */\n  void arm_float_to_q15(\n  float32_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Converts the elements of the floating-point vector to Q7 vector.\n   * @param[in]  pSrc       points to the floating-point input vector\n   * @param[out] pDst       points to the Q7 output vector\n   * @param[in]  blockSize  length of the input vector\n   */\n  void arm_float_to_q7(\n  float32_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q31 vector to Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q31_to_q15(\n  q31_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q31 vector to Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q31_to_q7(\n  q31_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q15 vector to floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q15_to_float(\n  q15_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q15 vector to Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q15_to_q31(\n  q15_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q15 vector to Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q15_to_q7(\n  q15_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @ingroup groupInterpolation\n   */\n\n  /**\n   * @defgroup BilinearInterpolate Bilinear Interpolation\n   *\n   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\n   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\n   * determines values between the grid points.\n   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\n   * Bilinear interpolation is often used in image processing to rescale images.\n   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\n   *\n   * <b>Algorithm</b>\n   * \\par\n   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\n   * For floating-point, the instance structure is defined as:\n   * <pre>\n   *   typedef struct\n   *   {\n   *     uint16_t numRows;\n   *     uint16_t numCols;\n   *     float32_t *pData;\n   * } arm_bilinear_interp_instance_f32;\n   * </pre>\n   *\n   * \\par\n   * where <code>numRows</code> specifies the number of rows in the table;\n   * <code>numCols</code> specifies the number of columns in the table;\n   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\n   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\n   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\n   *\n   * \\par\n   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:\n   * <pre>\n   *     XF = floor(x)\n   *     YF = floor(y)\n   * </pre>\n   * \\par\n   * The interpolated output point is computed as:\n   * <pre>\n   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\n   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))\n   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)\n   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)\n   * </pre>\n   * Note that the coordinates (x, y) contain integer and fractional components.\n   * The integer components specify which portion of the table to use while the\n   * fractional components control the interpolation processor.\n   *\n   * \\par\n   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\n   */\n\n  /**\n   * @addtogroup BilinearInterpolate\n   * @{\n   */\n\n\n  /**\n  *\n  * @brief  Floating-point bilinear interpolation.\n  * @param[in,out] S  points to an instance of the interpolation structure.\n  * @param[in]     X  interpolation coordinate.\n  * @param[in]     Y  interpolation coordinate.\n  * @return out interpolated value.\n  */\n  static __INLINE float32_t arm_bilinear_interp_f32(\n  const arm_bilinear_interp_instance_f32 * S,\n  float32_t X,\n  float32_t Y)\n  {\n    float32_t out;\n    float32_t f00, f01, f10, f11;\n    float32_t *pData = S->pData;\n    int32_t xIndex, yIndex, index;\n    float32_t xdiff, ydiff;\n    float32_t b1, b2, b3, b4;\n\n    xIndex = (int32_t) X;\n    yIndex = (int32_t) Y;\n\n    /* Care taken for table outside boundary */\n    /* Returns zero output when values are outside table boundary */\n    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\n    {\n      return (0);\n    }\n\n    /* Calculation of index for two nearest points in X-direction */\n    index = (xIndex - 1) + (yIndex - 1) * S->numCols;\n\n\n    /* Read two nearest points in X-direction */\n    f00 = pData[index];\n    f01 = pData[index + 1];\n\n    /* Calculation of index for two nearest points in Y-direction */\n    index = (xIndex - 1) + (yIndex) * S->numCols;\n\n\n    /* Read two nearest points in Y-direction */\n    f10 = pData[index];\n    f11 = pData[index + 1];\n\n    /* Calculation of intermediate values */\n    b1 = f00;\n    b2 = f01 - f00;\n    b3 = f10 - f00;\n    b4 = f00 - f01 - f10 + f11;\n\n    /* Calculation of fractional part in X */\n    xdiff = X - xIndex;\n\n    /* Calculation of fractional part in Y */\n    ydiff = Y - yIndex;\n\n    /* Calculation of bi-linear interpolated output */\n    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\n\n    /* return to application */\n    return (out);\n  }\n\n\n  /**\n  *\n  * @brief  Q31 bilinear interpolation.\n  * @param[in,out] S  points to an instance of the interpolation structure.\n  * @param[in]     X  interpolation coordinate in 12.20 format.\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\n  * @return out interpolated value.\n  */\n  static __INLINE q31_t arm_bilinear_interp_q31(\n  arm_bilinear_interp_instance_q31 * S,\n  q31_t X,\n  q31_t Y)\n  {\n    q31_t out;                                   /* Temporary output */\n    q31_t acc = 0;                               /* output */\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\n    q31_t x1, x2, y1, y2;                        /* Nearest output values */\n    int32_t rI, cI;                              /* Row and column indices */\n    q31_t *pYData = S->pData;                    /* pointer to output table values */\n    uint32_t nCols = S->numCols;                 /* num of rows */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\n\n    /* Care taken for table outside boundary */\n    /* Returns zero output when values are outside table boundary */\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\n    {\n      return (0);\n    }\n\n    /* 20 bits for the fractional part */\n    /* shift left xfract by 11 to keep 1.31 format */\n    xfract = (X & 0x000FFFFF) << 11u;\n\n    /* Read two nearest output values from the index */\n    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];\n    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\n\n    /* 20 bits for the fractional part */\n    /* shift left yfract by 11 to keep 1.31 format */\n    yfract = (Y & 0x000FFFFF) << 11u;\n\n    /* Read two nearest output values from the index */\n    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];\n    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\n\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\n    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));\n    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\n\n    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */\n    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\n    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\n\n    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */\n    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\n    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\n\n    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */\n    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\n    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\n\n    /* Convert acc to 1.31(q31) format */\n    return ((q31_t)(acc << 2));\n  }\n\n\n  /**\n  * @brief  Q15 bilinear interpolation.\n  * @param[in,out] S  points to an instance of the interpolation structure.\n  * @param[in]     X  interpolation coordinate in 12.20 format.\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\n  * @return out interpolated value.\n  */\n  static __INLINE q15_t arm_bilinear_interp_q15(\n  arm_bilinear_interp_instance_q15 * S,\n  q31_t X,\n  q31_t Y)\n  {\n    q63_t acc = 0;                               /* output */\n    q31_t out;                                   /* Temporary output */\n    q15_t x1, x2, y1, y2;                        /* Nearest output values */\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\n    int32_t rI, cI;                              /* Row and column indices */\n    q15_t *pYData = S->pData;                    /* pointer to output table values */\n    uint32_t nCols = S->numCols;                 /* num of rows */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\n\n    /* Care taken for table outside boundary */\n    /* Returns zero output when values are outside table boundary */\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\n    {\n      return (0);\n    }\n\n    /* 20 bits for the fractional part */\n    /* xfract should be in 12.20 format */\n    xfract = (X & 0x000FFFFF);\n\n    /* Read two nearest output values from the index */\n    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];\n    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\n\n    /* 20 bits for the fractional part */\n    /* yfract should be in 12.20 format */\n    yfract = (Y & 0x000FFFFF);\n\n    /* Read two nearest output values from the index */\n    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];\n    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\n\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\n\n    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\n    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */\n    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);\n    acc = ((q63_t) out * (0xFFFFF - yfract));\n\n    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */\n    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);\n    acc += ((q63_t) out * (xfract));\n\n    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */\n    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);\n    acc += ((q63_t) out * (yfract));\n\n    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */\n    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);\n    acc += ((q63_t) out * (yfract));\n\n    /* acc is in 13.51 format and down shift acc by 36 times */\n    /* Convert out to 1.15 format */\n    return ((q15_t)(acc >> 36));\n  }\n\n\n  /**\n  * @brief  Q7 bilinear interpolation.\n  * @param[in,out] S  points to an instance of the interpolation structure.\n  * @param[in]     X  interpolation coordinate in 12.20 format.\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\n  * @return out interpolated value.\n  */\n  static __INLINE q7_t arm_bilinear_interp_q7(\n  arm_bilinear_interp_instance_q7 * S,\n  q31_t X,\n  q31_t Y)\n  {\n    q63_t acc = 0;                               /* output */\n    q31_t out;                                   /* Temporary output */\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\n    q7_t x1, x2, y1, y2;                         /* Nearest output values */\n    int32_t rI, cI;                              /* Row and column indices */\n    q7_t *pYData = S->pData;                     /* pointer to output table values */\n    uint32_t nCols = S->numCols;                 /* num of rows */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\n\n    /* Care taken for table outside boundary */\n    /* Returns zero output when values are outside table boundary */\n    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\n    {\n      return (0);\n    }\n\n    /* 20 bits for the fractional part */\n    /* xfract should be in 12.20 format */\n    xfract = (X & (q31_t)0x000FFFFF);\n\n    /* Read two nearest output values from the index */\n    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];\n    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\n\n    /* 20 bits for the fractional part */\n    /* yfract should be in 12.20 format */\n    yfract = (Y & (q31_t)0x000FFFFF);\n\n    /* Read two nearest output values from the index */\n    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];\n    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\n\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\n    out = ((x1 * (0xFFFFF - xfract)));\n    acc = (((q63_t) out * (0xFFFFF - yfract)));\n\n    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */\n    out = ((x2 * (0xFFFFF - yfract)));\n    acc += (((q63_t) out * (xfract)));\n\n    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */\n    out = ((y1 * (0xFFFFF - xfract)));\n    acc += (((q63_t) out * (yfract)));\n\n    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */\n    out = ((y2 * (yfract)));\n    acc += (((q63_t) out * (xfract)));\n\n    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\n    return ((q7_t)(acc >> 40));\n  }\n\n  /**\n   * @} end of BilinearInterpolate group\n   */\n\n\n/* SMMLAR */\n#define multAcc_32x32_keep32_R(a, x, y) \\\n    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\n\n/* SMMLSR */\n#define multSub_32x32_keep32_R(a, x, y) \\\n    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\n\n/* SMMULR */\n#define mult_32x32_keep32_R(a, x, y) \\\n    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\n\n/* SMMLA */\n#define multAcc_32x32_keep32(a, x, y) \\\n    a += (q31_t) (((q63_t) x * y) >> 32)\n\n/* SMMLS */\n#define multSub_32x32_keep32(a, x, y) \\\n    a -= (q31_t) (((q63_t) x * y) >> 32)\n\n/* SMMUL */\n#define mult_32x32_keep32(a, x, y) \\\n    a = (q31_t) (((q63_t) x * y ) >> 32)\n\n\n#if defined ( __CC_ARM )\n  /* Enter low optimization region - place directly above function definition */\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\n    #define LOW_OPTIMIZATION_ENTER \\\n       _Pragma (\"push\")         \\\n       _Pragma (\"O1\")\n  #else\n    #define LOW_OPTIMIZATION_ENTER\n  #endif\n\n  /* Exit low optimization region - place directly after end of function definition */\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\n    #define LOW_OPTIMIZATION_EXIT \\\n       _Pragma (\"pop\")\n  #else\n    #define LOW_OPTIMIZATION_EXIT\n  #endif\n\n  /* Enter low optimization region - place directly above function definition */\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n\n  /* Exit low optimization region - place directly after end of function definition */\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #define LOW_OPTIMIZATION_ENTER\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined(__GNUC__)\n  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize(\"-O1\") ))\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined(__ICCARM__)\n  /* Enter low optimization region - place directly above function definition */\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\n    #define LOW_OPTIMIZATION_ENTER \\\n       _Pragma (\"optimize=low\")\n  #else\n    #define LOW_OPTIMIZATION_ENTER\n  #endif\n\n  /* Exit low optimization region - place directly after end of function definition */\n  #define LOW_OPTIMIZATION_EXIT\n\n  /* Enter low optimization region - place directly above function definition */\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\n    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\\n       _Pragma (\"optimize=low\")\n  #else\n    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #endif\n\n  /* Exit low optimization region - place directly after end of function definition */\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined(__CSMC__)\n  #define LOW_OPTIMIZATION_ENTER\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined(__TASKING__)\n  #define LOW_OPTIMIZATION_ENTER\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#endif\n\n\n#ifdef   __cplusplus\n}\n#endif\n\n\n#if defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n#endif\n\n#endif /* _ARM_MATH_H */\n\n/**\n *\n * End of file.\n */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/cmsis_armcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armcc.h\n * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_ARMCC_H\n#define __CMSIS_ARMCC_H\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\n  #error \"Please use Arm Compiler Toolchain V4.0.677 or later!\"\n#endif\n\n/* CMSIS compiler control architecture macros */\n#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \\\n     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )\n  #define __ARM_ARCH_6M__           1\n#endif\n\n#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))\n  #define __ARM_ARCH_7M__           1\n#endif\n\n#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\n  #define __ARM_ARCH_7EM__          1\n#endif\n\n  /* __ARM_ARCH_8M_BASE__  not applicable */\n  /* __ARM_ARCH_8M_MAIN__  not applicable */\n\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE                 \n  #define __STATIC_FORCEINLINE                   static __forceinline\n#endif           \n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __declspec(noreturn)\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        __packed struct\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         __packed union\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();     */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();    */\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_INLINE uint32_t __get_CONTROL(void)\n{\n  register uint32_t __regControl         __ASM(\"control\");\n  return(__regControl);\n}\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_INLINE void __set_CONTROL(uint32_t control)\n{\n  register uint32_t __regControl         __ASM(\"control\");\n  __regControl = control;\n}\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_INLINE uint32_t __get_IPSR(void)\n{\n  register uint32_t __regIPSR          __ASM(\"ipsr\");\n  return(__regIPSR);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_INLINE uint32_t __get_APSR(void)\n{\n  register uint32_t __regAPSR          __ASM(\"apsr\");\n  return(__regAPSR);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_INLINE uint32_t __get_xPSR(void)\n{\n  register uint32_t __regXPSR          __ASM(\"xpsr\");\n  return(__regXPSR);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_INLINE uint32_t __get_PSP(void)\n{\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\n  return(__regProcessStackPointer);\n}\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\n  __regProcessStackPointer = topOfProcStack;\n}\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_INLINE uint32_t __get_MSP(void)\n{\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\n  return(__regMainStackPointer);\n}\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\n  __regMainStackPointer = topOfMainStack;\n}\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_INLINE uint32_t __get_PRIMASK(void)\n{\n  register uint32_t __regPriMask         __ASM(\"primask\");\n  return(__regPriMask);\n}\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\n{\n  register uint32_t __regPriMask         __ASM(\"primask\");\n  __regPriMask = (priMask);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_INLINE uint32_t  __get_BASEPRI(void)\n{\n  register uint32_t __regBasePri         __ASM(\"basepri\");\n  return(__regBasePri);\n}\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\n{\n  register uint32_t __regBasePri         __ASM(\"basepri\");\n  __regBasePri = (basePri & 0xFFU);\n}\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  register uint32_t __regBasePriMax      __ASM(\"basepri_max\");\n  __regBasePriMax = (basePri & 0xFFU);\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_INLINE uint32_t __get_FAULTMASK(void)\n{\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\n  return(__regFaultMask);\n}\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\n  __regFaultMask = (faultMask & (uint32_t)1U);\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_INLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  return(__regfpscr);\n#else\n   return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  __regfpscr = (fpscr);\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP                             __nop\n\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI                             __wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE                             __wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV                             __sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB() do {\\\n                   __schedule_barrier();\\\n                   __isb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB() do {\\\n                   __schedule_barrier();\\\n                   __dsb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB() do {\\\n                   __schedule_barrier();\\\n                   __dmb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n                  \n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV                             __rev\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rev16_text\"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\n{\n  rev16 r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".revsh_text\"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\n{\n  revsh r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n#define __ROR                             __ror\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __breakpoint(value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n  #define __RBIT                          __rbit\n#else\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n  return result;\n}\n#endif\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ                             __clz\n\n\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\n#else\n  #define __LDREXB(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint8_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\n#else\n  #define __LDREXH(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint16_t) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\n#else\n  #define __LDREXW(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint32_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXB(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXH(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXW(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX                           __clrex\n\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT                            __ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT                            __usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rrx_text\"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\n{\n  rrx r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRBT(value, ptr)               __strt(value, ptr)\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRHT(value, ptr)               __strt(value, ptr)\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRT(value, ptr)                __strt(value, ptr)\n\n#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n#define __SADD8                           __sadd8\n#define __QADD8                           __qadd8\n#define __SHADD8                          __shadd8\n#define __UADD8                           __uadd8\n#define __UQADD8                          __uqadd8\n#define __UHADD8                          __uhadd8\n#define __SSUB8                           __ssub8\n#define __QSUB8                           __qsub8\n#define __SHSUB8                          __shsub8\n#define __USUB8                           __usub8\n#define __UQSUB8                          __uqsub8\n#define __UHSUB8                          __uhsub8\n#define __SADD16                          __sadd16\n#define __QADD16                          __qadd16\n#define __SHADD16                         __shadd16\n#define __UADD16                          __uadd16\n#define __UQADD16                         __uqadd16\n#define __UHADD16                         __uhadd16\n#define __SSUB16                          __ssub16\n#define __QSUB16                          __qsub16\n#define __SHSUB16                         __shsub16\n#define __USUB16                          __usub16\n#define __UQSUB16                         __uqsub16\n#define __UHSUB16                         __uhsub16\n#define __SASX                            __sasx\n#define __QASX                            __qasx\n#define __SHASX                           __shasx\n#define __UASX                            __uasx\n#define __UQASX                           __uqasx\n#define __UHASX                           __uhasx\n#define __SSAX                            __ssax\n#define __QSAX                            __qsax\n#define __SHSAX                           __shsax\n#define __USAX                            __usax\n#define __UQSAX                           __uqsax\n#define __UHSAX                           __uhsax\n#define __USAD8                           __usad8\n#define __USADA8                          __usada8\n#define __SSAT16                          __ssat16\n#define __USAT16                          __usat16\n#define __UXTB16                          __uxtb16\n#define __UXTAB16                         __uxtab16\n#define __SXTB16                          __sxtb16\n#define __SXTAB16                         __sxtab16\n#define __SMUAD                           __smuad\n#define __SMUADX                          __smuadx\n#define __SMLAD                           __smlad\n#define __SMLADX                          __smladx\n#define __SMLALD                          __smlald\n#define __SMLALDX                         __smlaldx\n#define __SMUSD                           __smusd\n#define __SMUSDX                          __smusdx\n#define __SMLSD                           __smlsd\n#define __SMLSDX                          __smlsdx\n#define __SMLSLD                          __smlsld\n#define __SMLSLDX                         __smlsldx\n#define __SEL                             __sel\n#define __QADD                            __qadd\n#define __QSUB                            __qsub\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\\n                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))\n\n#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCC_H */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/cmsis_armcc_V6.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armcc_V6.h\n * @brief    CMSIS Cortex-M Core Function/Instruction Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#ifndef __CMSIS_ARMCC_V6_H\n#define __CMSIS_ARMCC_V6_H\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get IPSR Register (non-secure)\n  \\details Returns the content of the non-secure IPSR Register when in secure state.\n  \\return               IPSR Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get APSR Register (non-secure)\n  \\details Returns the content of the non-secure APSR Register when in secure state.\n  \\return               APSR Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get xPSR Register (non-secure)\n  \\details Returns the content of the non-secure xPSR Register when in secure state.\n  \\return               xPSR Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : \"sp\");\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : \"sp\");\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : \"sp\");\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : \"sp\");\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (value) : \"memory\");\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (value) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (value) : \"memory\");\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Base Priority with condition (non_secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,\n\t       or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)\n{\n  __ASM volatile (\"MSR basepri_max_ns, %0\" : : \"r\" (value) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n\n#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\n\n\n#if (__ARM_ARCH_8M__ == 1U)\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n\n  return(result);\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n  register uint32_t result;\n\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n}\n\n\n#if  (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M')     /* ToDo:  ARMCC_V6: check predefined macro for mainline */\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n}\n#endif\n\n#endif /* (__ARM_ARCH_8M__ == 1U) */\n\n\n#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=4 */\n\n/**\n  \\brief   Get FPSCR\n  \\details eturns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#define __get_FPSCR      __builtin_arm_get_fpscr\n#if 0\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)\n{\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\n  uint32_t result;\n\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  __ASM volatile (\"\");\n  return(result);\n#else\n   return(0);\n#endif\n}\n#endif\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get FPSCR (non-secure)\n  \\details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.\n  \\return               Floating Point Status/Control register value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)\n{\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\n  uint32_t result;\n\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\n  __ASM volatile (\"VMRS %0, fpscr_ns\" : \"=r\" (result) );\n  __ASM volatile (\"\");\n  return(result);\n#else\n   return(0);\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#if 0\n__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\");\n  __ASM volatile (\"\");\n#endif\n}\n#endif\n\n#if  (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set FPSCR (non-secure)\n  \\details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)\n{\n#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\n  __ASM volatile (\"\");                                 /* Empty asm statement works as a scheduling barrier */\n  __ASM volatile (\"VMSR fpscr_ns, %0\" : : \"r\" (fpscr) : \"vfpcc\");\n  __ASM volatile (\"\");\n#endif\n}\n#endif\n\n#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\n\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF);\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF);\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF);\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in integer value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV          __builtin_bswap32\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in two unsigned short values.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16          __builtin_bswap16                           /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */\n#if 0\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Reverse byte order in signed short value\n  \\details Reverses the byte order in a signed short value with sign extension to integer.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n                                                          /* ToDo:  ARMCC_V6: check if __builtin_bswap16 could be used */\n__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\n{\n  int32_t result;\n\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n            Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n    \\param [in]    value  is ignored by the processor.\n                   If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n                                                          /* ToDo:  ARMCC_V6: check if __builtin_arm_rbit is supported */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return(result);\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ             __builtin_clz\n\n\n#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U))  /* ToDo:  ARMCC_V6: check if this is ok for cortex >=3 */\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n/*#define __SSAT             __builtin_arm_ssat*/\n#define __SSAT(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n#if 0\n#define __USAT(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n#endif\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */\n\n\n#if (__ARM_ARCH_8M__ == 1U)\n\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* (__ARM_ARCH_8M__ == 1U) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (__ARM_FEATURE_DSP == 1U)        /* ToDo:  ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1U) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCC_V6_H */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/cmsis_armclang.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armclang.h\n * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\n\n#ifndef __CMSIS_ARMCLANG_H\n#define __CMSIS_ARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n#ifndef __ARM_COMPAT_H\n#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE                 \n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif                                           \n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n  \n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n  \n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\n#else\n#define __get_FPSCR()      ((uint32_t)0U)\n#endif\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#else\n#define __set_FPSCR(x)      ((void)(x))\n#endif\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF);\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF);\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF);\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)     __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT            __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ             (uint8_t)__builtin_clz\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCLANG_H */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/cmsis_compiler.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.h\n * @brief    CMSIS compiler generic header file\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_COMPILER_H\n#define __CMSIS_COMPILER_H\n\n#include <stdint.h>\n\n/*\n * Arm Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n\n/*\n * Arm Compiler 6 (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armclang.h\"\n\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iccarm.h>\n\n\n/*\n * TI Arm Compiler\n */\n#elif defined ( __TI_ARM__ )\n  #include <cmsis_ccs.h>\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __attribute__((packed))\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)                           __attribute__((aligned(x)))\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n/*\n * TASKING Compiler\n */\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __packed__\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __packed__\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __packed__\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __packed__ T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __align(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n/*\n * COSMIC Compiler\n */\n#elif defined ( __CSMC__ )\n   #include <cmsis_csm.h>\n\n #ifndef   __ASM\n    #define __ASM                                  _asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    // NO RETURN is automatically detected hence no warning here\n    #define __NO_RETURN\n  #endif\n  #ifndef   __USED\n    #warning No compiler specific solution for __USED. __USED is ignored.\n    #define __USED\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __weak\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               @packed\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        @packed struct\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         @packed union\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    @packed struct T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n#else\n  #error Unknown compiler.\n#endif\n\n\n#endif /* __CMSIS_COMPILER_H */\n\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS compiler GCC header file\n * @version  V5.0.4\n * @date     09. April 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n/* Fallback for __has_builtin */\n#ifndef __has_builtin\n  #define __has_builtin(x) (0)\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static inline\n#endif\n#ifndef   __STATIC_FORCEINLINE                 \n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\n#endif                                           \n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n  \n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n  \n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_get_fpscr) \n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  return __builtin_arm_get_fpscr();\n#else\n  uint32_t result;\n\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  return(result);\n#endif\n#else\n  return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_set_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  __builtin_arm_set_fpscr(fpscr);\n#else\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\", \"memory\");\n#endif\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP()                             __ASM volatile (\"nop\")\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI()                             __ASM volatile (\"wfi\")\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE()                             __ASM volatile (\"wfe\")\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV()                             __ASM volatile (\"sev\")\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__STATIC_FORCEINLINE void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__STATIC_FORCEINLINE void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__STATIC_FORCEINLINE void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (int16_t)__builtin_bswap16(value);\n#else\n  int16_t result;\n\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return result;\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ             (uint8_t)__builtin_clz\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__STATIC_FORCEINLINE void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1,ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1,ARG2) \\\n __extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexb %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexh %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaex %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#pragma GCC diagnostic pop\n\n#endif /* __CMSIS_GCC_H */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/cmsis_iccarm.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_iccarm.h\n * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file\n * @version  V5.0.7\n * @date     19. June 2018\n ******************************************************************************/\n\n//------------------------------------------------------------------------------\n//\n// Copyright (c) 2017-2018 IAR Systems\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\")\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//     http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n//------------------------------------------------------------------------------\n\n\n#ifndef __CMSIS_ICCARM_H__\n#define __CMSIS_ICCARM_H__\n\n#ifndef __ICCARM__\n  #error This file should only be compiled by ICCARM\n#endif\n\n#pragma system_include\n\n#define __IAR_FT _Pragma(\"inline=forced\") __intrinsic\n\n#if (__VER__ >= 8000000)\n  #define __ICCARM_V8 1\n#else\n  #define __ICCARM_V8 0\n#endif\n\n#ifndef __ALIGNED\n  #if __ICCARM_V8\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #elif (__VER__ >= 7080000)\n    /* Needs IAR language extensions */\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #else\n    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n#endif\n\n\n/* Define compiler macros for CPU architecture, used in CMSIS 5.\n */\n#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\n/* Macros already defined */\n#else\n  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #elif defined(__ARM8M_BASELINE__)\n    #define __ARM_ARCH_8M_BASE__ 1\n  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\n    #if __ARM_ARCH == 6\n      #define __ARM_ARCH_6M__ 1\n    #elif __ARM_ARCH == 7\n      #if __ARM_FEATURE_DSP\n        #define __ARM_ARCH_7EM__ 1\n      #else\n        #define __ARM_ARCH_7M__ 1\n      #endif\n    #endif /* __ARM_ARCH */\n  #endif /* __ARM_ARCH_PROFILE == 'M' */\n#endif\n\n/* Alternativ core deduction for older ICCARM's */\n#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\\n    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\n  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\n    #define __ARM_ARCH_6M__ 1\n  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\n    #define __ARM_ARCH_7M__ 1\n  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\n    #define __ARM_ARCH_7EM__  1\n  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\n    #define __ARM_ARCH_8M_BASE__ 1\n  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #else\n    #error \"Unknown target.\"\n  #endif\n#endif\n\n\n\n#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\n  #define __IAR_M0_FAMILY  1\n#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\n  #define __IAR_M0_FAMILY  1\n#else\n  #define __IAR_M0_FAMILY  0\n#endif\n\n\n#ifndef __ASM\n  #define __ASM __asm\n#endif\n\n#ifndef __INLINE\n  #define __INLINE inline\n#endif\n\n#ifndef   __NO_RETURN\n  #if __ICCARM_V8\n    #define __NO_RETURN __attribute__((__noreturn__))\n  #else\n    #define __NO_RETURN _Pragma(\"object_attribute=__noreturn\")\n  #endif\n#endif\n\n#ifndef   __PACKED\n  #if __ICCARM_V8\n    #define __PACKED __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED __packed\n  #endif\n#endif\n\n#ifndef   __PACKED_STRUCT\n  #if __ICCARM_V8\n    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_STRUCT __packed struct\n  #endif\n#endif\n\n#ifndef   __PACKED_UNION\n  #if __ICCARM_V8\n    #define __PACKED_UNION union __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_UNION __packed union\n  #endif\n#endif\n\n#ifndef   __RESTRICT\n  #define __RESTRICT            __restrict\n#endif\n\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE       static inline\n#endif\n\n#ifndef   __FORCEINLINE\n  #define __FORCEINLINE         _Pragma(\"inline=forced\")\n#endif\n\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE\n#endif\n\n#ifndef __UNALIGNED_UINT16_READ\n#pragma language=save\n#pragma language=extended\n__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\n{\n  return *(__packed uint16_t*)(ptr);\n}\n#pragma language=restore\n#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\n#endif\n\n\n#ifndef __UNALIGNED_UINT16_WRITE\n#pragma language=save\n#pragma language=extended\n__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\n{\n  *(__packed uint16_t*)(ptr) = val;;\n}\n#pragma language=restore\n#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32_READ\n#pragma language=save\n#pragma language=extended\n__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\n{\n  return *(__packed uint32_t*)(ptr);\n}\n#pragma language=restore\n#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\n#endif\n\n#ifndef __UNALIGNED_UINT32_WRITE\n#pragma language=save\n#pragma language=extended\n__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\n{\n  *(__packed uint32_t*)(ptr) = val;;\n}\n#pragma language=restore\n#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32   /* deprecated */\n#pragma language=save\n#pragma language=extended\n__packed struct  __iar_u32 { uint32_t v; };\n#pragma language=restore\n#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\n#endif\n\n#ifndef   __USED\n  #if __ICCARM_V8\n    #define __USED __attribute__((used))\n  #else\n    #define __USED _Pragma(\"__root\")\n  #endif\n#endif\n\n#ifndef   __WEAK\n  #if __ICCARM_V8\n    #define __WEAK __attribute__((weak))\n  #else\n    #define __WEAK _Pragma(\"__weak\")\n  #endif\n#endif\n\n\n#ifndef __ICCARM_INTRINSICS_VERSION__\n  #define __ICCARM_INTRINSICS_VERSION__  0\n#endif\n\n#if __ICCARM_INTRINSICS_VERSION__ == 2\n\n  #if defined(__CLZ)\n    #undef __CLZ\n  #endif\n  #if defined(__REVSH)\n    #undef __REVSH\n  #endif\n  #if defined(__RBIT)\n    #undef __RBIT\n  #endif\n  #if defined(__SSAT)\n    #undef __SSAT\n  #endif\n  #if defined(__USAT)\n    #undef __USAT\n  #endif\n\n  #include \"iccarm_builtin.h\"\n\n  #define __disable_fault_irq __iar_builtin_disable_fiq\n  #define __disable_irq       __iar_builtin_disable_interrupt\n  #define __enable_fault_irq  __iar_builtin_enable_fiq\n  #define __enable_irq        __iar_builtin_enable_interrupt\n  #define __arm_rsr           __iar_builtin_rsr\n  #define __arm_wsr           __iar_builtin_wsr\n\n\n  #define __get_APSR()                (__arm_rsr(\"APSR\"))\n  #define __get_BASEPRI()             (__arm_rsr(\"BASEPRI\"))\n  #define __get_CONTROL()             (__arm_rsr(\"CONTROL\"))\n  #define __get_FAULTMASK()           (__arm_rsr(\"FAULTMASK\"))\n\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n    #define __get_FPSCR()             (__arm_rsr(\"FPSCR\"))\n    #define __set_FPSCR(VALUE)        (__arm_wsr(\"FPSCR\", (VALUE)))\n  #else\n    #define __get_FPSCR()             ( 0 )\n    #define __set_FPSCR(VALUE)        ((void)VALUE)\n  #endif\n\n  #define __get_IPSR()                (__arm_rsr(\"IPSR\"))\n  #define __get_MSP()                 (__arm_rsr(\"MSP\"))\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure MSPLIM is RAZ/WI\n    #define __get_MSPLIM()            (0U)\n  #else\n    #define __get_MSPLIM()            (__arm_rsr(\"MSPLIM\"))\n  #endif\n  #define __get_PRIMASK()             (__arm_rsr(\"PRIMASK\"))\n  #define __get_PSP()                 (__arm_rsr(\"PSP\"))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __get_PSPLIM()            (0U)\n  #else\n    #define __get_PSPLIM()            (__arm_rsr(\"PSPLIM\"))\n  #endif\n\n  #define __get_xPSR()                (__arm_rsr(\"xPSR\"))\n\n  #define __set_BASEPRI(VALUE)        (__arm_wsr(\"BASEPRI\", (VALUE)))\n  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr(\"BASEPRI_MAX\", (VALUE)))\n  #define __set_CONTROL(VALUE)        (__arm_wsr(\"CONTROL\", (VALUE)))\n  #define __set_FAULTMASK(VALUE)      (__arm_wsr(\"FAULTMASK\", (VALUE)))\n  #define __set_MSP(VALUE)            (__arm_wsr(\"MSP\", (VALUE)))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure MSPLIM is RAZ/WI\n    #define __set_MSPLIM(VALUE)       ((void)(VALUE))\n  #else\n    #define __set_MSPLIM(VALUE)       (__arm_wsr(\"MSPLIM\", (VALUE)))\n  #endif\n  #define __set_PRIMASK(VALUE)        (__arm_wsr(\"PRIMASK\", (VALUE)))\n  #define __set_PSP(VALUE)            (__arm_wsr(\"PSP\", (VALUE)))\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __set_PSPLIM(VALUE)       ((void)(VALUE))\n  #else\n    #define __set_PSPLIM(VALUE)       (__arm_wsr(\"PSPLIM\", (VALUE)))\n  #endif\n\n  #define __TZ_get_CONTROL_NS()       (__arm_rsr(\"CONTROL_NS\"))\n  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr(\"CONTROL_NS\", (VALUE)))\n  #define __TZ_get_PSP_NS()           (__arm_rsr(\"PSP_NS\"))\n  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr(\"PSP_NS\", (VALUE)))\n  #define __TZ_get_MSP_NS()           (__arm_rsr(\"MSP_NS\"))\n  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr(\"MSP_NS\", (VALUE)))\n  #define __TZ_get_SP_NS()            (__arm_rsr(\"SP_NS\"))\n  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr(\"SP_NS\", (VALUE)))\n  #define __TZ_get_PRIMASK_NS()       (__arm_rsr(\"PRIMASK_NS\"))\n  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr(\"PRIMASK_NS\", (VALUE)))\n  #define __TZ_get_BASEPRI_NS()       (__arm_rsr(\"BASEPRI_NS\"))\n  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr(\"BASEPRI_NS\", (VALUE)))\n  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr(\"FAULTMASK_NS\"))\n  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr(\"FAULTMASK_NS\", (VALUE)))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __TZ_get_PSPLIM_NS()      (0U)\n    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\n  #else\n    #define __TZ_get_PSPLIM_NS()      (__arm_rsr(\"PSPLIM_NS\"))\n    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr(\"PSPLIM_NS\", (VALUE)))\n  #endif\n\n  #define __TZ_get_MSPLIM_NS()        (__arm_rsr(\"MSPLIM_NS\"))\n  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr(\"MSPLIM_NS\", (VALUE)))\n\n  #define __NOP     __iar_builtin_no_operation\n\n  #define __CLZ     __iar_builtin_CLZ\n  #define __CLREX   __iar_builtin_CLREX\n\n  #define __DMB     __iar_builtin_DMB\n  #define __DSB     __iar_builtin_DSB\n  #define __ISB     __iar_builtin_ISB\n\n  #define __LDREXB  __iar_builtin_LDREXB\n  #define __LDREXH  __iar_builtin_LDREXH\n  #define __LDREXW  __iar_builtin_LDREX\n\n  #define __RBIT    __iar_builtin_RBIT\n  #define __REV     __iar_builtin_REV\n  #define __REV16   __iar_builtin_REV16\n\n  __IAR_FT int16_t __REVSH(int16_t val)\n  {\n    return (int16_t) __iar_builtin_REVSH(val);\n  }\n\n  #define __ROR     __iar_builtin_ROR\n  #define __RRX     __iar_builtin_RRX\n\n  #define __SEV     __iar_builtin_SEV\n\n  #if !__IAR_M0_FAMILY\n    #define __SSAT    __iar_builtin_SSAT\n  #endif\n\n  #define __STREXB  __iar_builtin_STREXB\n  #define __STREXH  __iar_builtin_STREXH\n  #define __STREXW  __iar_builtin_STREX\n\n  #if !__IAR_M0_FAMILY\n    #define __USAT    __iar_builtin_USAT\n  #endif\n\n  #define __WFE     __iar_builtin_WFE\n  #define __WFI     __iar_builtin_WFI\n\n  #if __ARM_MEDIA__\n    #define __SADD8   __iar_builtin_SADD8\n    #define __QADD8   __iar_builtin_QADD8\n    #define __SHADD8  __iar_builtin_SHADD8\n    #define __UADD8   __iar_builtin_UADD8\n    #define __UQADD8  __iar_builtin_UQADD8\n    #define __UHADD8  __iar_builtin_UHADD8\n    #define __SSUB8   __iar_builtin_SSUB8\n    #define __QSUB8   __iar_builtin_QSUB8\n    #define __SHSUB8  __iar_builtin_SHSUB8\n    #define __USUB8   __iar_builtin_USUB8\n    #define __UQSUB8  __iar_builtin_UQSUB8\n    #define __UHSUB8  __iar_builtin_UHSUB8\n    #define __SADD16  __iar_builtin_SADD16\n    #define __QADD16  __iar_builtin_QADD16\n    #define __SHADD16 __iar_builtin_SHADD16\n    #define __UADD16  __iar_builtin_UADD16\n    #define __UQADD16 __iar_builtin_UQADD16\n    #define __UHADD16 __iar_builtin_UHADD16\n    #define __SSUB16  __iar_builtin_SSUB16\n    #define __QSUB16  __iar_builtin_QSUB16\n    #define __SHSUB16 __iar_builtin_SHSUB16\n    #define __USUB16  __iar_builtin_USUB16\n    #define __UQSUB16 __iar_builtin_UQSUB16\n    #define __UHSUB16 __iar_builtin_UHSUB16\n    #define __SASX    __iar_builtin_SASX\n    #define __QASX    __iar_builtin_QASX\n    #define __SHASX   __iar_builtin_SHASX\n    #define __UASX    __iar_builtin_UASX\n    #define __UQASX   __iar_builtin_UQASX\n    #define __UHASX   __iar_builtin_UHASX\n    #define __SSAX    __iar_builtin_SSAX\n    #define __QSAX    __iar_builtin_QSAX\n    #define __SHSAX   __iar_builtin_SHSAX\n    #define __USAX    __iar_builtin_USAX\n    #define __UQSAX   __iar_builtin_UQSAX\n    #define __UHSAX   __iar_builtin_UHSAX\n    #define __USAD8   __iar_builtin_USAD8\n    #define __USADA8  __iar_builtin_USADA8\n    #define __SSAT16  __iar_builtin_SSAT16\n    #define __USAT16  __iar_builtin_USAT16\n    #define __UXTB16  __iar_builtin_UXTB16\n    #define __UXTAB16 __iar_builtin_UXTAB16\n    #define __SXTB16  __iar_builtin_SXTB16\n    #define __SXTAB16 __iar_builtin_SXTAB16\n    #define __SMUAD   __iar_builtin_SMUAD\n    #define __SMUADX  __iar_builtin_SMUADX\n    #define __SMMLA   __iar_builtin_SMMLA\n    #define __SMLAD   __iar_builtin_SMLAD\n    #define __SMLADX  __iar_builtin_SMLADX\n    #define __SMLALD  __iar_builtin_SMLALD\n    #define __SMLALDX __iar_builtin_SMLALDX\n    #define __SMUSD   __iar_builtin_SMUSD\n    #define __SMUSDX  __iar_builtin_SMUSDX\n    #define __SMLSD   __iar_builtin_SMLSD\n    #define __SMLSDX  __iar_builtin_SMLSDX\n    #define __SMLSLD  __iar_builtin_SMLSLD\n    #define __SMLSLDX __iar_builtin_SMLSLDX\n    #define __SEL     __iar_builtin_SEL\n    #define __QADD    __iar_builtin_QADD\n    #define __QSUB    __iar_builtin_QSUB\n    #define __PKHBT   __iar_builtin_PKHBT\n    #define __PKHTB   __iar_builtin_PKHTB\n  #endif\n\n#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n  #if __IAR_M0_FAMILY\n   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\n    #define __CLZ  __cmsis_iar_clz_not_active\n    #define __SSAT __cmsis_iar_ssat_not_active\n    #define __USAT __cmsis_iar_usat_not_active\n    #define __RBIT __cmsis_iar_rbit_not_active\n    #define __get_APSR  __cmsis_iar_get_APSR_not_active\n  #endif\n\n\n  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\n    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\n    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\n  #endif\n\n  #ifdef __INTRINSICS_INCLUDED\n  #error intrinsics.h is already included previously!\n  #endif\n\n  #include <intrinsics.h>\n\n  #if __IAR_M0_FAMILY\n   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\n    #undef __CLZ\n    #undef __SSAT\n    #undef __USAT\n    #undef __RBIT\n    #undef __get_APSR\n\n    __STATIC_INLINE uint8_t __CLZ(uint32_t data)\n    {\n      if (data == 0U) { return 32U; }\n\n      uint32_t count = 0U;\n      uint32_t mask = 0x80000000U;\n\n      while ((data & mask) == 0U)\n      {\n        count += 1U;\n        mask = mask >> 1U;\n      }\n      return count;\n    }\n\n    __STATIC_INLINE uint32_t __RBIT(uint32_t v)\n    {\n      uint8_t sc = 31U;\n      uint32_t r = v;\n      for (v >>= 1U; v; v >>= 1U)\n      {\n        r <<= 1U;\n        r |= v & 1U;\n        sc--;\n      }\n      return (r << sc);\n    }\n\n    __STATIC_INLINE  uint32_t __get_APSR(void)\n    {\n      uint32_t res;\n      __asm(\"MRS      %0,APSR\" : \"=r\" (res));\n      return res;\n    }\n\n  #endif\n\n  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\n    #undef __get_FPSCR\n    #undef __set_FPSCR\n    #define __get_FPSCR()       (0)\n    #define __set_FPSCR(VALUE)  ((void)VALUE)\n  #endif\n\n  #pragma diag_suppress=Pe940\n  #pragma diag_suppress=Pe177\n\n  #define __enable_irq    __enable_interrupt\n  #define __disable_irq   __disable_interrupt\n  #define __NOP           __no_operation\n\n  #define __get_xPSR      __get_PSR\n\n  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\n\n    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\n    {\n      return __LDREX((unsigned long *)ptr);\n    }\n\n    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\n    {\n      return __STREX(value, (unsigned long *)ptr);\n    }\n  #endif\n\n\n  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\n  #if (__CORTEX_M >= 0x03)\n\n    __IAR_FT uint32_t __RRX(uint32_t value)\n    {\n      uint32_t result;\n      __ASM(\"RRX      %0, %1\" : \"=r\"(result) : \"r\" (value) : \"cc\");\n      return(result);\n    }\n\n    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\n    {\n      __asm volatile(\"MSR      BASEPRI_MAX,%0\"::\"r\" (value));\n    }\n\n\n    #define __enable_fault_irq  __enable_fiq\n    #define __disable_fault_irq __disable_fiq\n\n\n  #endif /* (__CORTEX_M >= 0x03) */\n\n  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\n  {\n    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\n  }\n\n  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n   __IAR_FT uint32_t __get_MSPLIM(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure MSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,MSPLIM\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __set_MSPLIM(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure MSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      MSPLIM,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t __get_PSPLIM(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,PSPLIM\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __set_PSPLIM(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      PSPLIM,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,CONTROL_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      CONTROL_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,PSP_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      PSP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,MSP_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      MSP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_SP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,SP_NS\" : \"=r\" (res));\n      return res;\n    }\n    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      SP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,PRIMASK_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      PRIMASK_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,BASEPRI_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      BASEPRI_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,FAULTMASK_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      FAULTMASK_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,PSPLIM_NS\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      PSPLIM_NS,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,MSPLIM_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      MSPLIM_NS,%0\" :: \"r\" (value));\n    }\n\n  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\n\n#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n#define __BKPT(value)    __asm volatile (\"BKPT     %0\" : : \"i\"(value))\n\n#if __IAR_M0_FAMILY\n  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\n  {\n    if ((sat >= 1U) && (sat <= 32U))\n    {\n      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n      const int32_t min = -1 - max ;\n      if (val > max)\n      {\n        return max;\n      }\n      else if (val < min)\n      {\n        return min;\n      }\n    }\n    return val;\n  }\n\n  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\n  {\n    if (sat <= 31U)\n    {\n      const uint32_t max = ((1U << sat) - 1U);\n      if (val > (int32_t)max)\n      {\n        return max;\n      }\n      else if (val < 0)\n      {\n        return 0U;\n      }\n    }\n    return (uint32_t)val;\n  }\n#endif\n\n#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\n\n  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRBT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRHT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\n  {\n    __ASM(\"STRBT %1, [%0]\" : : \"r\" (addr), \"r\" ((uint32_t)value) : \"memory\");\n  }\n\n  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\n  {\n    __ASM(\"STRHT %1, [%0]\" : : \"r\" (addr), \"r\" ((uint32_t)value) : \"memory\");\n  }\n\n  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\n  {\n    __ASM(\"STRT %1, [%0]\" : : \"r\" (addr), \"r\" (value) : \"memory\");\n  }\n\n#endif /* (__CORTEX_M >= 0x03) */\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n\n  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAB %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAH %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDA %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\n  {\n    __ASM volatile (\"STLB %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\n  {\n    __ASM volatile (\"STLH %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\n  {\n    __ASM volatile (\"STL %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEXB %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEXH %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEX %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEXB %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEXH %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEX %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\n\n#undef __IAR_FT\n#undef __IAR_M0_FAMILY\n#undef __ICCARM_V8\n\n#pragma diag_default=Pe940\n#pragma diag_default=Pe177\n\n#endif /* __CMSIS_ICCARM_H__ */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/cmsis_version.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_version.h\n * @brief    CMSIS Core(M) Version definitions\n * @version  V5.0.2\n * @date     19. April 2017\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CMSIS_VERSION_H\n#define __CMSIS_VERSION_H\n\n/*  CMSIS Version definitions */\n#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\n#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\n#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\n#endif\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_armv8mbl.h",
    "content": "/**************************************************************************//**\n * @file     core_armv8mbl.h\n * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\n * @version  V5.0.7\n * @date     22. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_ARMV8MBL_H_GENERIC\n#define __CORE_ARMV8MBL_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMv8MBL\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MBL_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV8MBL_H_DEPENDANT\n#define __CORE_ARMV8MBL_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv8MBL_REV\n    #define __ARMv8MBL_REV               0x0000U\n    #warning \"__ARMv8MBL_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv8MBL */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_armv8mml.h",
    "content": "/**************************************************************************//**\n * @file     core_armv8mml.h\n * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\n * @version  V5.0.7\n * @date     06. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_ARMV8MML_H_GENERIC\n#define __CORE_ARMV8MML_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMv8MML\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS Armv8MML definitions */\n#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MML_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV8MML_H_DEPENDANT\n#define __CORE_ARMV8MML_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv8MML_REV\n    #define __ARMv8MML_REV               0x0000U\n    #warning \"__ARMv8MML_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv8MML */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED3[92U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n        uint32_t RESERVED7[6U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MML_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cm0.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0.h\n * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\n * @version  V5.0.5\n * @date     28. May 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0_H_GENERIC\n#define __CORE_CM0_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M0\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM0 definitions */\n#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0_H_DEPENDANT\n#define __CORE_CM0_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0_REV\n    #define __CM0_REV               0x0000U\n    #warning \"__CM0_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M0 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cm0plus.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0plus.h\n * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\n * @version  V5.0.6\n * @date     28. May 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0PLUS_H_GENERIC\n#define __CORE_CM0PLUS_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex-M0+\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM0+ definitions */\n#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\\n                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0PLUS_H_DEPENDANT\n#define __CORE_CM0PLUS_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0PLUS_REV\n    #define __CM0PLUS_REV             0x0000U\n    #warning \"__CM0PLUS_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex-M0+ */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0+ header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n    uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cm1.h",
    "content": "/**************************************************************************//**\n * @file     core_cm1.h\n * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File\n * @version  V1.0.0\n * @date     23. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM1_H_GENERIC\n#define __CORE_CM1_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M1\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM1 definitions */\n#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM1_H_DEPENDANT\n#define __CORE_CM1_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM1_REV\n    #define __CM1_REV               0x0100U\n    #warning \"__CM1_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M1 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\n\n#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M1 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cm23.h",
    "content": "/**************************************************************************//**\n * @file     core_cm23.h\n * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File\n * @version  V5.0.7\n * @date     22. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM23_H_GENERIC\n#define __CORE_CM23_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M23\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM23_H_DEPENDANT\n#define __CORE_CM23_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM23_REV\n    #define __CM23_REV                0x0000U\n    #warning \"__CM23_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M23 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else \n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\t\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cm3.h",
    "content": "/**************************************************************************//**\n * @file     core_cm3.h\n * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM3_H_GENERIC\n#define __CORE_CM3_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M3\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM3 definitions */\n#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM3_H_DEPENDANT\n#define __CORE_CM3_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM3_REV\n    #define __CM3_REV               0x0200U\n    #warning \"__CM3_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M3 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#else\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n#else\n        uint32_t RESERVED1[1U];\n#endif\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cm33.h",
    "content": "/**************************************************************************//**\n * @file     core_cm33.h\n * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File\n * @version  V5.0.9\n * @date     06. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM33_H_GENERIC\n#define __CORE_CM33_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M33\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM33 definitions */\n#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined (__TARGET_FPU_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined (__ARM_PCS_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined (__ARMVFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined (__TI_VFP_SUPPORT__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined (__FPU_VFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM33_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM33_H_DEPENDANT\n#define __CORE_CM33_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM33_REV\n    #define __CM33_REV                0x0000U\n    #warning \"__CM33_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M33 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED3[92U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n        uint32_t RESERVED7[6U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else \n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM33_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cm4.h",
    "content": "/**************************************************************************//**\n * @file     core_cm4.h\n * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM4_H_GENERIC\n#define __CORE_CM4_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M4\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM4 definitions */\n#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM4_H_DEPENDANT\n#define __CORE_CM4_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM4_REV\n    #define __CM4_REV               0x0000U\n    #warning \"__CM4_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M4 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cm7.h",
    "content": "/**************************************************************************//**\n * @file     core_cm7.h\n * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM7_H_GENERIC\n#define __CORE_CM7_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M7\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM7 definitions */\n#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM7_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM7_H_DEPENDANT\n#define __CORE_CM7_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM7_REV\n    #define __CM7_REV               0x0000U\n    #warning \"__CM7_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ICACHE_PRESENT\n    #define __ICACHE_PRESENT          0U\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DCACHE_PRESENT\n    #define __DCACHE_PRESENT          0U\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DTCM_PRESENT\n    #define __DTCM_PRESENT            0U\n    #warning \"__DTCM_PRESENT        not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M7 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n        uint32_t RESERVED3[93U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n        uint32_t RESERVED7[6U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\n\n#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\n\n#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\n\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\n\n#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\n#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\n\n#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\n#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED3[981U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and FP Feature Register 2 Definitions */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = SCB->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################  Cache functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_CacheFunctions Cache Functions\n  \\brief    Functions that configure Instruction and Data cache.\n  @{\n */\n\n/* Cache Size ID Register Macros */\n#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\n#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\n\n\n/**\n  \\brief   Enable I-Cache\n  \\details Turns on I-Cache\n  */\n__STATIC_INLINE void SCB_EnableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable I-Cache\n  \\details Turns off I-Cache\n  */\n__STATIC_INLINE void SCB_DisableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate I-Cache\n  \\details Invalidates I-Cache\n  */\n__STATIC_INLINE void SCB_InvalidateICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Enable D-Cache\n  \\details Turns on D-Cache\n  */\n__STATIC_INLINE void SCB_EnableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n    __DSB();\n\n    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable D-Cache\n  \\details Turns off D-Cache\n  */\n__STATIC_INLINE void SCB_DisableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n    __DSB();\n\n    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate D-Cache\n  \\details Invalidates D-Cache\n  */\n__STATIC_INLINE void SCB_InvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean D-Cache\n  \\details Cleans D-Cache\n  */\n__STATIC_INLINE void SCB_CleanDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n   __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\n                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean & Invalidate D-Cache\n  \\details Cleans and Invalidates D-Cache\n  */\n__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Invalidate by address\n  \\details Invalidates D-Cache for the given address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n     int32_t op_size = dsize;\n    uint32_t op_addr = (uint32_t)addr;\n     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\n\n    __DSB();\n\n    while (op_size > 0) {\n      SCB->DCIMVAC = op_addr;\n      op_addr += (uint32_t)linesize;\n      op_size -=           linesize;\n    }\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean by address\n  \\details Cleans D-Cache for the given address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n     int32_t op_size = dsize;\n    uint32_t op_addr = (uint32_t) addr;\n     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\n\n    __DSB();\n\n    while (op_size > 0) {\n      SCB->DCCMVAC = op_addr;\n      op_addr += (uint32_t)linesize;\n      op_size -=           linesize;\n    }\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean and Invalidate by address\n  \\details Cleans and invalidates D_Cache for the given address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n     int32_t op_size = dsize;\n    uint32_t op_addr = (uint32_t) addr;\n     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\n\n    __DSB();\n\n    while (op_size > 0) {\n      SCB->DCCIMVAC = op_addr;\n      op_addr += (uint32_t)linesize;\n      op_size -=           linesize;\n    }\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/*@} end of CMSIS_Core_CacheFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM7_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cmFunc.h",
    "content": "/**************************************************************************//**\n * @file     core_cmFunc.h\n * @brief    CMSIS Cortex-M Core Function Access Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#if   defined ( __ICCARM__ )\n #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CMFUNC_H\n#define __CORE_CMFUNC_H\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n*/\n\n/*------------------ RealView Compiler -----------------*/\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n/*------------------ ARM Compiler V6 -------------------*/\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armcc_V6.h\"\n\n/*------------------ GNU Compiler ----------------------*/\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n/*------------------ ICC Compiler ----------------------*/\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iar.h>\n\n/*------------------ TI CCS Compiler -------------------*/\n#elif defined ( __TMS470__ )\n  #include <cmsis_ccs.h>\n\n/*------------------ TASKING Compiler ------------------*/\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n/*------------------ COSMIC Compiler -------------------*/\n#elif defined ( __CSMC__ )\n  #include <cmsis_csm.h>\n\n#endif\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n#endif /* __CORE_CMFUNC_H */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cmInstr.h",
    "content": "/**************************************************************************//**\n * @file     core_cmInstr.h\n * @brief    CMSIS Cortex-M Core Instruction Access Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#if   defined ( __ICCARM__ )\n #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CMINSTR_H\n#define __CORE_CMINSTR_H\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/*------------------ RealView Compiler -----------------*/\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n/*------------------ ARM Compiler V6 -------------------*/\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armcc_V6.h\"\n\n/*------------------ GNU Compiler ----------------------*/\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n/*------------------ ICC Compiler ----------------------*/\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iar.h>\n\n/*------------------ TI CCS Compiler -------------------*/\n#elif defined ( __TMS470__ )\n  #include <cmsis_ccs.h>\n\n/*------------------ TASKING Compiler ------------------*/\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n/*------------------ COSMIC Compiler -------------------*/\n#elif defined ( __CSMC__ )\n  #include <cmsis_csm.h>\n\n#endif\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n#endif /* __CORE_CMINSTR_H */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_cmSimd.h",
    "content": "/**************************************************************************//**\n * @file     core_cmSimd.h\n * @brief    CMSIS Cortex-M SIMD Header File\n * @version  V4.30\n * @date     20. October 2015\n ******************************************************************************/\n/* Copyright (c) 2009 - 2015 ARM LIMITED\n\n   All rights reserved.\n   Redistribution and use in source and binary forms, with or without\n   modification, are permitted provided that the following conditions are met:\n   - Redistributions of source code must retain the above copyright\n     notice, this list of conditions and the following disclaimer.\n   - Redistributions in binary form must reproduce the above copyright\n     notice, this list of conditions and the following disclaimer in the\n     documentation and/or other materials provided with the distribution.\n   - Neither the name of ARM nor the names of its contributors may be used\n     to endorse or promote products derived from this software without\n     specific prior written permission.\n   *\n   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\n   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n   POSSIBILITY OF SUCH DAMAGE.\n   ---------------------------------------------------------------------------*/\n\n\n#if   defined ( __ICCARM__ )\n #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CMSIMD_H\n#define __CORE_CMSIMD_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n/*------------------ RealView Compiler -----------------*/\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n/*------------------ ARM Compiler V6 -------------------*/\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armcc_V6.h\"\n\n/*------------------ GNU Compiler ----------------------*/\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n/*------------------ ICC Compiler ----------------------*/\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iar.h>\n\n/*------------------ TI CCS Compiler -------------------*/\n#elif defined ( __TMS470__ )\n  #include <cmsis_ccs.h>\n\n/*------------------ TASKING Compiler ------------------*/\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n/*------------------ COSMIC Compiler -------------------*/\n#elif defined ( __CSMC__ )\n  #include <cmsis_csm.h>\n\n#endif\n\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CMSIMD_H */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_sc000.h",
    "content": "/**************************************************************************//**\n * @file     core_sc000.h\n * @brief    CMSIS SC000 Core Peripheral Access Layer Header File\n * @version  V5.0.5\n * @date     28. May 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_SC000_H_GENERIC\n#define __CORE_SC000_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup SC000\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS SC000 definitions */\n#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC000_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_SC000_H_DEPENDANT\n#define __CORE_SC000_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __SC000_REV\n    #define __SC000_REV             0x0000U\n    #warning \"__SC000_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group SC000 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n        uint32_t RESERVED1[154U];\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the SC000 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC000_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/core_sc300.h",
    "content": "/**************************************************************************//**\n * @file     core_sc300.h\n * @brief    CMSIS SC300 Core Peripheral Access Layer Header File\n * @version  V5.0.6\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_SC300_H_GENERIC\n#define __CORE_SC300_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup SC3000\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS SC300 definitions */\n#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC300_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_SC300_H_DEPENDANT\n#define __CORE_SC300_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __SC300_REV\n    #define __SC300_REV               0x0000U\n    #warning \"__SC300_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group SC300 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n        uint32_t RESERVED1[129U];\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n        uint32_t RESERVED1[1U];\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC300_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/mpu_armv7.h",
    "content": "/******************************************************************************\n * @file     mpu_armv7.h\n * @brief    CMSIS MPU API for Armv7-M MPU\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n \n#ifndef ARM_MPU_ARMV7_H\n#define ARM_MPU_ARMV7_H\n\n#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\n#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\n#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\n#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\n#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\n#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\n#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\n#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\n#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\n#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\n#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\n#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\n#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\n#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\n#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\n#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\n#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\n#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\n#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\n#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\n#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\n#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\n#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\n#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\n#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\n#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\n#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\n#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\n\n#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\n#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\n#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only\n#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\n#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only\n#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access\n\n/** MPU Region Base Address Register Value\n*\n* \\param Region The region to be configured, number 0 to 15.\n* \\param BaseAddress The base address for the region.\n*/\n#define ARM_MPU_RBAR(Region, BaseAddress) \\\n  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \\\n   ((Region) & MPU_RBAR_REGION_Msk)    |  \\\n   (MPU_RBAR_VALID_Msk))\n\n/**\n* MPU Memory Access Attributes\n* \n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n*/  \n#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \\\n  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \\\n   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \\\n   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \\\n   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))\n\n/**\n* MPU Region Attribute and Size Register Value\n* \n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param AccessAttributes  Memory access attribution, see \\ref ARM_MPU_ACCESS_.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/\n#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \\\n  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \\\n   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \\\n   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))\n  \n/**\n* MPU Region Attribute and Size Register Value\n* \n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/                         \n#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\\n  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\n\n/**\n* MPU Memory Access Attribute for strongly ordered memory.\n*  - TEX: 000b\n*  - Shareable\n*  - Non-cacheable\n*  - Non-bufferable\n*/ \n#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\n\n/**\n* MPU Memory Access Attribute for device memory.\n*  - TEX: 000b (if non-shareable) or 010b (if shareable)\n*  - Shareable or non-shareable\n*  - Non-cacheable\n*  - Bufferable (if shareable) or non-bufferable (if non-shareable)\n*\n* \\param IsShareable Configures the device memory as shareable or non-shareable.\n*/ \n#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\n\n/**\n* MPU Memory Access Attribute for normal memory.\n*  - TEX: 1BBb (reflecting outer cacheability rules)\n*  - Shareable or non-shareable\n*  - Cacheable or non-cacheable (reflecting inner cacheability rules)\n*  - Bufferable or non-bufferable (reflecting inner cacheability rules)\n*\n* \\param OuterCp Configures the outer cache policy.\n* \\param InnerCp Configures the inner cache policy.\n* \\param IsShareable Configures the memory as shareable or non-shareable.\n*/ \n#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\n\n/**\n* MPU Memory Access Attribute non-cacheable policy.\n*/\n#define ARM_MPU_CACHEP_NOCACHE 0U\n\n/**\n* MPU Memory Access Attribute write-back, write and read allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_WRA 1U\n\n/**\n* MPU Memory Access Attribute write-through, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WT_NWA 2U\n\n/**\n* MPU Memory Access Attribute write-back, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_NWA 3U\n\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR; //!< The region base address register value (RBAR)\n  uint32_t RASR; //!< The region attribute and size register value (RASR) \\ref MPU_RASR\n} ARM_MPU_Region_t;\n    \n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  __DSB();\n  __ISB();\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DSB();\n  __ISB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  MPU->RNR = rnr;\n  MPU->RASR = 0U;\n}\n\n/** Configure an MPU region.\n* \\param rbar Value for RBAR register.\n* \\param rsar Value for RSAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\n{\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rsar Value for RSAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\n{\n  MPU->RNR = rnr;\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Memcopy with strictly ordered memory access, e.g. for register targets.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i) \n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  while (cnt > MPU_TYPE_RALIASES) {\n    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\n    table += MPU_TYPE_RALIASES;\n    cnt -= MPU_TYPE_RALIASES;\n  }\n  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\n}\n\n#endif\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/mpu_armv8.h",
    "content": "/******************************************************************************\n * @file     mpu_armv8.h\n * @brief    CMSIS MPU API for Armv8-M MPU\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef ARM_MPU_ARMV8_H\n#define ARM_MPU_ARMV8_H\n\n/** \\brief Attribute for device memory (outer only) */\n#define ARM_MPU_ATTR_DEVICE                           ( 0U )\n\n/** \\brief Attribute for non-cacheable, normal memory */\n#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )\n\n/** \\brief Attribute for normal memory (outer and inner)\n* \\param NT Non-Transient: Set to 1 for non-transient data.\n* \\param WB Write-Back: Set to 1 to use write-back update policy.\n* \\param RA Read Allocation: Set to 1 to use cache allocation on read miss.\n* \\param WA Write Allocation: Set to 1 to use cache allocation on write miss.\n*/\n#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\\n  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\n\n/** \\brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\n\n/** \\brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)\n\n/** \\brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)\n\n/** \\brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_GRE    (3U)\n\n/** \\brief Memory Attribute\n* \\param O Outer memory attributes\n* \\param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\n*/\n#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\n\n/** \\brief Normal memory non-shareable  */\n#define ARM_MPU_SH_NON   (0U)\n\n/** \\brief Normal memory outer shareable  */\n#define ARM_MPU_SH_OUTER (2U)\n\n/** \\brief Normal memory inner shareable  */\n#define ARM_MPU_SH_INNER (3U)\n\n/** \\brief Memory access permissions\n* \\param RO Read-Only: Set to 1 for read-only memory.\n* \\param NP Non-Privileged: Set to 1 for non-privileged memory.\n*/\n#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\n\n/** \\brief Region Base Address Register value\n* \\param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\n* \\param SH Defines the Shareability domain for this memory region.\n* \\param RO Read-Only: Set to 1 for a read-only memory region.\n* \\param NP Non-Privileged: Set to 1 for a non-privileged memory region.\n* \\oaram XN eXecute Never: Set to 1 for a non-executable memory region.\n*/\n#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\\n  ((BASE & MPU_RBAR_BASE_Msk) | \\\n  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\\n  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\\n  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\n\n/** \\brief Region Limit Address Register value\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\n* \\param IDX The attribute index to be associated with this memory region.\n*/\n#define ARM_MPU_RLAR(LIMIT, IDX) \\\n  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\\n  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\\n  (MPU_RLAR_EN_Msk))\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR;                   /*!< Region Base Address Register value */\n  uint32_t RLAR;                   /*!< Region Limit Address Register value */\n} ARM_MPU_Region_t;\n    \n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  __DSB();\n  __ISB();\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DSB();\n  __ISB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n\n#ifdef MPU_NS\n/** Enable the Non-secure MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\n{\n  __DSB();\n  __ISB();\n  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n}\n\n/** Disable the Non-secure MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable_NS(void)\n{\n  __DSB();\n  __ISB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n#endif\n\n/** Set the memory attribute encoding to the given MPU.\n* \\param mpu Pointer to the MPU to be configured.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\n{\n  const uint8_t reg = idx / 4U;\n  const uint32_t pos = ((idx % 4U) * 8U);\n  const uint32_t mask = 0xFFU << pos;\n  \n  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\n    return; // invalid index\n  }\n  \n  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\n}\n\n/** Set the memory attribute encoding.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\n{\n  ARM_MPU_SetMemAttrEx(MPU, idx, attr);\n}\n\n#ifdef MPU_NS\n/** Set the memory attribute encoding to the Non-secure MPU.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\n{\n  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\n}\n#endif\n\n/** Clear and disable the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\n{\n  mpu->RNR = rnr;\n  mpu->RLAR = 0U;\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  ARM_MPU_ClrRegionEx(MPU, rnr);\n}\n\n#ifdef MPU_NS\n/** Clear and disable the given Non-secure MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\n{  \n  ARM_MPU_ClrRegionEx(MPU_NS, rnr);\n}\n#endif\n\n/** Configure the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  mpu->RNR = rnr;\n  mpu->RBAR = rbar;\n  mpu->RLAR = rlar;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\n}\n\n#ifdef MPU_NS\n/** Configure the given Non-secure MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  \n}\n#endif\n\n/** Memcopy with strictly ordered memory access, e.g. for register targets.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i) \n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table to the given MPU.\n* \\param mpu Pointer to the MPU registers to be used.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  if (cnt == 1U) {\n    mpu->RNR = rnr;\n    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\n  } else {\n    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);\n    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\n    \n    mpu->RNR = rnrBase;\n    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\n      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\n      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\n      table += c;\n      cnt -= c;\n      rnrOffset = 0U;\n      rnrBase += MPU_TYPE_RALIASES;\n      mpu->RNR = rnrBase;\n    }\n    \n    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  ARM_MPU_LoadEx(MPU, rnr, table, cnt);\n}\n\n#ifdef MPU_NS\n/** Load the given number of MPU regions from a table to the Non-secure MPU.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\n}\n#endif\n\n#endif\n\n"
  },
  {
    "path": "examples/lib/st/CMSIS/Include/tz_context.h",
    "content": "/******************************************************************************\n * @file     tz_context.h\n * @brief    Context Management for Armv8-M TrustZone\n * @version  V1.0.1\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef TZ_CONTEXT_H\n#define TZ_CONTEXT_H\n \n#include <stdint.h>\n \n#ifndef TZ_MODULEID_T\n#define TZ_MODULEID_T\n/// \\details Data type that identifies secure software modules called by a process.\ntypedef uint32_t TZ_ModuleId_t;\n#endif\n \n/// \\details TZ Memory ID identifies an allocated memory slot.\ntypedef uint32_t TZ_MemoryId_t;\n  \n/// Initialize secure context memory system\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_InitContextSystem_S (void);\n \n/// Allocate context memory for calling secure software modules in TrustZone\n/// \\param[in]  module   identifies software modules called from non-secure mode\n/// \\return value != 0 id TrustZone memory slot identifier\n/// \\return value 0    no memory available or internal error\nTZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\n \n/// Free context memory that was previously allocated with \\ref TZ_AllocModuleContext_S\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\n \n/// Load secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\n \n/// Store secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\n \n#endif  // TZ_CONTEXT_H\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_bus.h\n  * @author  MCD Application Team\n  * @brief   Header file of BUS LL module.\n\n  @verbatim\n                      ##### RCC Limitations #####\n  ==============================================================================\n    [..]\n      A delay between an RCC peripheral clock enable and the effective peripheral\n      enabling should be taken into account in order to manage the peripheral read/write\n      from/to registers.\n      (+) This delay depends on the peripheral mapping.\n        (++) AHB & APB peripherals, 1 dummy read is necessary\n\n    [..]\n      Workarounds:\n      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been\n          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_BUS_H\n#define __STM32F4xx_LL_BUS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @defgroup BUS_LL BUS\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants\n  * @{\n  */\n\n/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU\n#define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN\n#define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN\n#define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN\n#if defined(GPIOD)\n#define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN\n#endif /* GPIOD */\n#if defined(GPIOE)\n#define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN\n#endif /* GPIOE */\n#if defined(GPIOF)\n#define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN\n#endif /* GPIOF */\n#if defined(GPIOG)\n#define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN\n#endif /* GPIOG */\n#if defined(GPIOH)\n#define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN\n#endif /* GPIOH */\n#if defined(GPIOI)\n#define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN\n#endif /* GPIOI */\n#if defined(GPIOJ)\n#define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN\n#endif /* GPIOJ */\n#if defined(GPIOK)\n#define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN\n#endif /* GPIOK */\n#define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN\n#if defined(RCC_AHB1ENR_BKPSRAMEN)\n#define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN\n#endif /* RCC_AHB1ENR_BKPSRAMEN */\n#if defined(RCC_AHB1ENR_CCMDATARAMEN)\n#define LL_AHB1_GRP1_PERIPH_CCMDATARAM      RCC_AHB1ENR_CCMDATARAMEN\n#endif /* RCC_AHB1ENR_CCMDATARAMEN */\n#define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN\n#define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN\n#if defined(RCC_AHB1ENR_RNGEN)\n#define LL_AHB1_GRP1_PERIPH_RNG             RCC_AHB1ENR_RNGEN\n#endif /* RCC_AHB1ENR_RNGEN */\n#if defined(DMA2D)\n#define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN\n#endif /* DMA2D */\n#if defined(ETH)\n#define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN\n#define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN\n#define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN\n#define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN\n#endif /* ETH */\n#if defined(USB_OTG_HS)\n#define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN\n#define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN\n#endif /* USB_OTG_HS */\n#define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN\n#define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN\n#if defined(RCC_AHB1LPENR_SRAM2LPEN)\n#define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN\n#endif /* RCC_AHB1LPENR_SRAM2LPEN */\n#if defined(RCC_AHB1LPENR_SRAM3LPEN)\n#define LL_AHB1_GRP1_PERIPH_SRAM3           RCC_AHB1LPENR_SRAM3LPEN\n#endif /* RCC_AHB1LPENR_SRAM3LPEN */\n/**\n  * @}\n  */\n\n#if defined(RCC_AHB2_SUPPORT)\n/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#if defined(DCMI)\n#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN\n#endif /* DCMI */\n#if defined(CRYP)\n#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN\n#endif /* CRYP */\n#if defined(AES)\n#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN\n#endif /* AES */\n#if defined(HASH)\n#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN\n#endif /* HASH */\n#if defined(RCC_AHB2ENR_RNGEN)\n#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN\n#endif /* RCC_AHB2ENR_RNGEN */\n#if defined(USB_OTG_FS)\n#define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN\n#endif /* USB_OTG_FS */\n/**\n  * @}\n  */\n#endif /* RCC_AHB2_SUPPORT */\n\n#if defined(RCC_AHB3_SUPPORT)\n/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#if defined(FSMC_Bank1)\n#define LL_AHB3_GRP1_PERIPH_FSMC           RCC_AHB3ENR_FSMCEN\n#endif /* FSMC_Bank1 */\n#if defined(FMC_Bank1)\n#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN\n#endif /* FMC_Bank1 */\n#if defined(QUADSPI)\n#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN\n#endif /* QUADSPI */\n/**\n  * @}\n  */\n#endif /* RCC_AHB3_SUPPORT */\n\n/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH\n  * @{\n  */\n#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#if defined(TIM2)\n#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN\n#endif /* TIM2 */\n#if defined(TIM3)\n#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN\n#endif /* TIM3 */\n#if defined(TIM4)\n#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN\n#endif /* TIM4 */\n#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN\n#if defined(TIM6)\n#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN\n#endif /* TIM6 */\n#if defined(TIM7)\n#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN\n#endif /* TIM7 */\n#if defined(TIM12)\n#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN\n#endif /* TIM12 */\n#if defined(TIM13)\n#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN\n#endif /* TIM13 */\n#if defined(TIM14)\n#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN\n#endif /* TIM14 */\n#if defined(LPTIM1)\n#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN\n#endif /* LPTIM1 */\n#if defined(RCC_APB1ENR_RTCAPBEN)\n#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCAPBEN\n#endif /* RCC_APB1ENR_RTCAPBEN */\n#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN\n#if defined(SPI2)\n#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN\n#endif /* SPI2 */\n#if defined(SPI3)\n#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN\n#endif /* SPI3 */\n#if defined(SPDIFRX)\n#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN\n#endif /* SPDIFRX */\n#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN\n#if defined(USART3)\n#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN\n#endif /* USART3 */\n#if defined(UART4)\n#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN\n#endif /* UART4 */\n#if defined(UART5)\n#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN\n#endif /* UART5 */\n#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN\n#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN\n#if defined(I2C3)\n#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN\n#endif /* I2C3 */\n#if defined(FMPI2C1)\n#define LL_APB1_GRP1_PERIPH_FMPI2C1        RCC_APB1ENR_FMPI2C1EN\n#endif /* FMPI2C1 */\n#if defined(CAN1)\n#define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN\n#endif /* CAN1 */\n#if defined(CAN2)\n#define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN\n#endif /* CAN2 */\n#if defined(CAN3)\n#define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN\n#endif /* CAN3 */\n#if defined(CEC)\n#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN\n#endif /* CEC */\n#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN\n#if defined(DAC1)\n#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN\n#endif /* DAC1 */\n#if defined(UART7)\n#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN\n#endif /* UART7 */\n#if defined(UART8)\n#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN\n#endif /* UART8 */\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH\n  * @{\n  */\n#define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU\n#define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN\n#if defined(TIM8)\n#define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN\n#endif /* TIM8 */\n#define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN\n#if defined(USART6)\n#define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN\n#endif /* USART6 */\n#if defined(UART9)\n#define LL_APB2_GRP1_PERIPH_UART9        RCC_APB2ENR_UART9EN\n#endif /* UART9 */\n#if defined(UART10)\n#define LL_APB2_GRP1_PERIPH_UART10       RCC_APB2ENR_UART10EN\n#endif /* UART10 */\n#define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN\n#if defined(ADC2)\n#define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN\n#endif /* ADC2 */\n#if defined(ADC3)\n#define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN\n#endif /* ADC3 */\n#if defined(SDIO)\n#define LL_APB2_GRP1_PERIPH_SDIO         RCC_APB2ENR_SDIOEN\n#endif /* SDIO */\n#define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN\n#if defined(SPI4)\n#define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN\n#endif /* SPI4 */\n#define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN\n#if defined(RCC_APB2ENR_EXTITEN)\n#define LL_APB2_GRP1_PERIPH_EXTI         RCC_APB2ENR_EXTITEN\n#endif /* RCC_APB2ENR_EXTITEN */\n#define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN\n#if defined(TIM10)\n#define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN\n#endif /* TIM10 */\n#define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN\n#if defined(SPI5)\n#define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN\n#endif /* SPI5 */\n#if defined(SPI6)\n#define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN\n#endif /* SPI6 */\n#if defined(SAI1)\n#define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN\n#endif /* SAI1 */\n#if defined(SAI2)\n#define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN\n#endif /* SAI2 */\n#if defined(LTDC)\n#define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN\n#endif /* LTDC */\n#if defined(DSI)\n#define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN\n#endif /* DSI */\n#if defined(DFSDM1_Channel0)\n#define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN\n#endif /* DFSDM1_Channel0 */\n#if defined(DFSDM2_Channel0)\n#define LL_APB2_GRP1_PERIPH_DFSDM2       RCC_APB2ENR_DFSDM2EN\n#endif /* DFSDM2_Channel0 */\n#define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions\n  * @{\n  */\n\n/** @defgroup BUS_LL_EF_AHB1 AHB1\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB1 peripherals clock.\n  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB1ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB1 peripheral clock is enabled or not\n  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB1 peripherals clock.\n  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB1 peripherals reset.\n  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB1 peripherals reset.\n  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB1 peripheral clocks in low-power mode\n  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\\n\n  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB1LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB1 peripheral clocks in low-power mode\n  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\\n\n  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n#if defined(RCC_AHB2_SUPPORT)\n/** @defgroup BUS_LL_EF_AHB2 AHB2\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB2 peripherals clock.\n  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB2ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB2 peripheral clock is enabled or not\n  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB2 peripherals clock.\n  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB2 peripherals reset.\n  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB2 peripherals reset.\n  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB2 peripheral clocks in low-power mode\n  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\\n\n  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB2LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB2 peripheral clocks in low-power mode\n  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\\n\n  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_AHB2_SUPPORT */\n\n#if defined(RCC_AHB3_SUPPORT)\n/** @defgroup BUS_LL_EF_AHB3 AHB3\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB3 peripherals clock.\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\\n\n  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_EnableClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB3ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB3 peripheral clock is enabled or not\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\\n\n  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_IsEnabledClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB3 peripherals clock.\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\\n\n  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_DisableClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB3 peripherals reset.\n  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\\n\n  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ForceReset\\n\n  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB3RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB3 peripherals reset.\n  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\\n\n  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ReleaseReset\\n\n  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB3 peripheral clocks in low-power mode\n  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\\n\n  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_EnableClockLowPower\\n\n  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB3LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB3 peripheral clocks in low-power mode\n  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\\n\n  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_DisableClockLowPower\\n\n  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_AHB3_SUPPORT */\n\n/** @defgroup BUS_LL_EF_APB1 APB1\n  * @{\n  */\n\n/**\n  * @brief  Enable APB1 peripherals clock.\n  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB1ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if APB1 peripheral clock is enabled or not\n  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable APB1 peripherals clock.\n  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1ENR, Periphs);\n}\n\n/**\n  * @brief  Force APB1 peripherals reset.\n  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->APB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Release APB1 peripherals reset.\n  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable APB1 peripheral clocks in low-power mode\n  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\\n\n  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB1LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable APB1 peripheral clocks in low-power mode\n  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\\n\n  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EF_APB2 APB2\n  * @{\n  */\n\n/**\n  * @brief  Enable APB2 peripherals clock.\n  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     UART9EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     UART10EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SDIOEN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     EXTITEN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB2ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if APB2 peripheral clock is enabled or not\n  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     UART9EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     UART10EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SDIOEN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     EXTITEN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable APB2 peripherals clock.\n  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     UART9EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     UART10EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SDIOEN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     EXTITEN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2ENR, Periphs);\n}\n\n/**\n  * @brief  Force APB2 peripherals reset.\n  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->APB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Release APB2 peripherals reset.\n  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable APB2 peripheral clocks in low-power mode\n  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\\n\n  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_EnableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB2LPENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable APB2 peripheral clocks in low-power mode\n  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\\n\n  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_DisableClockLowPower\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2LPENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_BUS_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_cortex.h\n  * @author  MCD Application Team\n  * @brief   Header file of CORTEX LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL CORTEX driver contains a set of generic APIs that can be\n    used by user:\n      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick\n          functions\n      (+) Low power mode configuration (SCB register of Cortex-MCU)\n      (+) MPU API to configure and enable regions\n          (MPU services provided only on some devices)\n      (+) API to access to MCU info (CPUID register)\n      (+) API to enable fault handler (SHCSR accesses)\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_CORTEX_H\n#define __STM32F4xx_LL_CORTEX_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n/** @defgroup CORTEX_LL CORTEX\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n\n/* Private macros ------------------------------------------------------------*/\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants\n  * @{\n  */\n\n/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source\n  * @{\n  */\n#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/\n#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type\n  * @{\n  */\n#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */\n#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */\n#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */\n/**\n  * @}\n  */\n\n#if __MPU_PRESENT\n\n/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control\n  * @{\n  */\n#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */\n#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */\n#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */\n#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION MPU Region Number\n  * @{\n  */\n#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */\n#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */\n#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */\n#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */\n#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */\n#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */\n#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */\n#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size\n  * @{\n  */\n#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges\n  * @{\n  */\n#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/\n#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/\n#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */\n#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */\n#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/\n#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level\n  * @{\n  */\n#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */\n#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */\n#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */\n#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access\n  * @{\n  */\n#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */\n#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */\n#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */\n#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */\n#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */\n/**\n  * @}\n  */\n#endif /* __MPU_PRESENT */\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions\n  * @{\n  */\n\n/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK\n  * @{\n  */\n\n/**\n  * @brief  This function checks if the Systick counter flag is active or not.\n  * @note   It can be used in timeout function on application side.\n  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)\n{\n  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));\n}\n\n/**\n  * @brief  Configures the SysTick clock source\n  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)\n{\n  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)\n  {\n    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n  }\n  else\n  {\n    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n  }\n}\n\n/**\n  * @brief  Get the SysTick clock source\n  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)\n{\n  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n}\n\n/**\n  * @brief  Enable SysTick exception request\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_EnableIT(void)\n{\n  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);\n}\n\n/**\n  * @brief  Disable SysTick exception request\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_DisableIT(void)\n{\n  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);\n}\n\n/**\n  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)\n{\n  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE\n  * @{\n  */\n\n/**\n  * @brief  Processor uses sleep as its low power mode\n  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableSleep(void)\n{\n  /* Clear SLEEPDEEP bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n}\n\n/**\n  * @brief  Processor uses deep sleep as its low power mode\n  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)\n{\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n}\n\n/**\n  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.\n  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an\n  *         empty main application.\n  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)\n{\n  /* Set SLEEPONEXIT bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\n}\n\n/**\n  * @brief  Do not sleep when returning to Thread mode.\n  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)\n{\n  /* Clear SLEEPONEXIT bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\n}\n\n/**\n  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the\n  *         processor.\n  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)\n{\n  /* Set SEVEONPEND bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\n}\n\n/**\n  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are\n  *         excluded\n  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)\n{\n  /* Clear SEVEONPEND bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_HANDLER HANDLER\n  * @{\n  */\n\n/**\n  * @brief  Enable a fault in System handler control register (SHCSR)\n  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault\n  * @param  Fault This parameter can be a combination of the following values:\n  *         @arg @ref LL_HANDLER_FAULT_USG\n  *         @arg @ref LL_HANDLER_FAULT_BUS\n  *         @arg @ref LL_HANDLER_FAULT_MEM\n  * @retval None\n  */\n__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)\n{\n  /* Enable the system handler fault */\n  SET_BIT(SCB->SHCSR, Fault);\n}\n\n/**\n  * @brief  Disable a fault in System handler control register (SHCSR)\n  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault\n  * @param  Fault This parameter can be a combination of the following values:\n  *         @arg @ref LL_HANDLER_FAULT_USG\n  *         @arg @ref LL_HANDLER_FAULT_BUS\n  *         @arg @ref LL_HANDLER_FAULT_MEM\n  * @retval None\n  */\n__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)\n{\n  /* Disable the system handler fault */\n  CLEAR_BIT(SCB->SHCSR, Fault);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO\n  * @{\n  */\n\n/**\n  * @brief  Get Implementer code\n  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer\n  * @retval Value should be equal to 0x41 for ARM\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);\n}\n\n/**\n  * @brief  Get Variant number (The r value in the rnpn product revision identifier)\n  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant\n  * @retval Value between 0 and 255 (0x0: revision 0)\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);\n}\n\n/**\n  * @brief  Get Constant number\n  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant\n  * @retval Value should be equal to 0xF for Cortex-M4 devices\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);\n}\n\n/**\n  * @brief  Get Part number\n  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo\n  * @retval Value should be equal to 0xC24 for Cortex-M4\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);\n}\n\n/**\n  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)\n  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision\n  * @retval Value between 0 and 255 (0x1: patch 1)\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);\n}\n\n/**\n  * @}\n  */\n\n#if __MPU_PRESENT\n/** @defgroup CORTEX_LL_EF_MPU MPU\n  * @{\n  */\n\n/**\n  * @brief  Enable MPU with input options\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable\n  * @param  Options This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE\n  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI\n  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT\n  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)\n{\n  /* Enable the MPU*/\n  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));\n  /* Ensure MPU settings take effects */\n  __DSB();\n  /* Sequence instruction fetches using update settings */\n  __ISB();\n}\n\n/**\n  * @brief  Disable MPU\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_Disable(void)\n{\n  /* Make sure outstanding transfers are done */\n  __DMB();\n  /* Disable MPU*/\n  WRITE_REG(MPU->CTRL, 0U);\n}\n\n/**\n  * @brief  Check if MPU is enabled or not\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)\n{\n  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));\n}\n\n/**\n  * @brief  Enable a MPU region\n  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)\n{\n  /* Set Region number */\n  WRITE_REG(MPU->RNR, Region);\n  /* Enable the MPU region */\n  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);\n}\n\n/**\n  * @brief  Configure and enable a region\n  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\\n\n  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\\n\n  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     XN            LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     AP            LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     S             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     C             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     B             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @param  Address Value of region base address\n  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF\n  * @param  Attributes This parameter can be a combination of the following values:\n  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B\n  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB\n  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB\n  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB\n  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB\n  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB\n  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS\n  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO\n  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4\n  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE\n  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE\n  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE\n  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)\n{\n  /* Set Region number */\n  WRITE_REG(MPU->RNR, Region);\n  /* Set base address */\n  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));\n  /* Configure MPU */\n  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));\n}\n\n/**\n  * @brief  Disable a region\n  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\\n\n  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)\n{\n  /* Set Region number */\n  WRITE_REG(MPU->RNR, Region);\n  /* Disable the MPU region */\n  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);\n}\n\n/**\n  * @}\n  */\n\n#endif /* __MPU_PRESENT */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_CORTEX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_dma.h\n  * @author  MCD Application Team\n  * @brief   Header file of DMA LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_DMA_H\n#define __STM32F4xx_LL_DMA_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (DMA1) || defined (DMA2)\n\n/** @defgroup DMA_LL DMA\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup DMA_LL_Private_Variables DMA Private Variables\n  * @{\n  */\n/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */\nstatic const uint8_t STREAM_OFFSET_TAB[] =\n{\n  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)\n};\n\n/**\n  * @}\n  */\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup DMA_LL_Private_Constants DMA Private Constants\n  * @{\n  */\n/**\n  * @}\n  */\n\n\n/* Private macros ------------------------------------------------------------*/\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure\n  * @{\n  */\ntypedef struct\n{\n  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer\n                                        or as Source base address in case of memory to memory transfer direction.\n\n                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */\n\n  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer\n                                        or as Destination base address in case of memory to memory transfer direction.\n\n                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */\n\n  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,\n                                        from memory to memory or from peripheral to memory.\n                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */\n\n  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.\n                                        This parameter can be a value of @ref DMA_LL_EC_MODE\n                                        @note The circular buffer mode cannot be used if the memory to memory\n                                              data transfer direction is configured on the selected Stream\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */\n\n  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction\n                                        is incremented or not.\n                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */\n\n  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction\n                                        is incremented or not.\n                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */\n\n  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)\n                                        in case of memory to memory transfer direction.\n                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */\n\n  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)\n                                        in case of memory to memory transfer direction.\n                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */\n\n  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.\n                                        The data unit is equal to the source buffer configuration set in PeripheralSize\n                                        or MemorySize parameters depending in the transfer direction.\n                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */\n\n  uint32_t Channel;                /*!< Specifies the peripheral channel.\n                                        This parameter can be a value of @ref DMA_LL_EC_CHANNEL\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */\n\n  uint32_t Priority;               /*!< Specifies the channel priority level.\n                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */\n                                        \n  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\n                                        This parameter can be a value of @ref DMA_LL_FIFOMODE\n                                        @note The Direct mode (FIFO mode disabled) cannot be used if the \n                                        memory-to-memory data transfer is configured on the selected stream\n\n                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */\n\n  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.\n                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */\n\n  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers. \n                                        It specifies the amount of data to be transferred in a single non interruptible\n                                        transaction.\n                                        This parameter can be a value of @ref DMA_LL_EC_MBURST \n                                        @note The burst mode is possible only if the address Increment mode is enabled. \n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */\n\n  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers. \n                                        It specifies the amount of data to be transferred in a single non interruptible \n                                        transaction. \n                                        This parameter can be a value of @ref DMA_LL_EC_PBURST\n                                        @note The burst mode is possible only if the address Increment mode is enabled. \n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */\n\n} LL_DMA_InitTypeDef;\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants\n  * @{\n  */\n\n/** @defgroup DMA_LL_EC_STREAM STREAM\n  * @{\n  */\n#define LL_DMA_STREAM_0                   0x00000000U\n#define LL_DMA_STREAM_1                   0x00000001U\n#define LL_DMA_STREAM_2                   0x00000002U\n#define LL_DMA_STREAM_3                   0x00000003U\n#define LL_DMA_STREAM_4                   0x00000004U\n#define LL_DMA_STREAM_5                   0x00000005U\n#define LL_DMA_STREAM_6                   0x00000006U\n#define LL_DMA_STREAM_7                   0x00000007U\n#define LL_DMA_STREAM_ALL                 0xFFFF0000U\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_DIRECTION DIRECTION\n  * @{\n  */\n#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */\n#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */\n#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_MODE MODE\n  * @{\n  */\n#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */\n#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */\n#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE\n  * @{\n  */\n#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */\n#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_PERIPH PERIPH\n  * @{\n  */\n#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */\n#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_MEMORY MEMORY\n  * @{\n  */\n#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */\n#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN\n  * @{\n  */\n#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */\n#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */\n#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN\n  * @{\n  */\n#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */\n#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */\n#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE\n  * @{\n  */\n#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE */\n#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_PRIORITY PRIORITY\n  * @{\n  */\n#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */\n#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */\n#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */\n#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_CHANNEL CHANNEL\n  * @{\n  */\n#define LL_DMA_CHANNEL_0                  0x00000000U                                                /* Select Channel0 of DMA Instance */\n#define LL_DMA_CHANNEL_1                  DMA_SxCR_CHSEL_0                                           /* Select Channel1 of DMA Instance */\n#define LL_DMA_CHANNEL_2                  DMA_SxCR_CHSEL_1                                           /* Select Channel2 of DMA Instance */\n#define LL_DMA_CHANNEL_3                  (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)                      /* Select Channel3 of DMA Instance */\n#define LL_DMA_CHANNEL_4                  DMA_SxCR_CHSEL_2                                           /* Select Channel4 of DMA Instance */\n#define LL_DMA_CHANNEL_5                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                      /* Select Channel5 of DMA Instance */\n#define LL_DMA_CHANNEL_6                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                      /* Select Channel6 of DMA Instance */\n#define LL_DMA_CHANNEL_7                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)   /* Select Channel7 of DMA Instance */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_MBURST MBURST\n  * @{\n  */\n#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration */\n#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration */\n#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration */\n#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_PBURST PBURST\n  * @{\n  */\n#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration */\n#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration */\n#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration */\n#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */\n/**\n  * @}\n  */\n  \n/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE\n  * @{\n  */\n#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */\n#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable  */\n/**\n  * @}\n  */  \n\n/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0\n  * @{\n  */\n#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */\n#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */\n#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */\n#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */\n#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */\n#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD\n  * @{\n  */\n#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */\n#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */\n#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */\n#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */\n/**\n  * @}\n  */\n    \n/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM\n  * @{\n  */\n#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */\n#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros\n  * @{\n  */\n\n/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros\n  * @{\n  */\n/**\n  * @brief  Write a value in DMA register\n  * @param  __INSTANCE__ DMA Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in DMA register\n  * @param  __INSTANCE__ DMA Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy\n  * @{\n  */\n/**\n  * @brief  Convert DMAx_Streamy into DMAx\n  * @param  __STREAM_INSTANCE__ DMAx_Streamy\n  * @retval DMAx\n  */\n#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \\\n(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)\n\n/**\n  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y\n  * @param  __STREAM_INSTANCE__ DMAx_Streamy\n  * @retval LL_DMA_CHANNEL_y\n  */\n#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \\\n(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \\\n ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \\\n LL_DMA_STREAM_7)\n\n/**\n  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy\n  * @param  __DMA_INSTANCE__ DMAx\n  * @param  __STREAM__ LL_DMA_STREAM_y\n  * @retval DMAx_Streamy\n  */\n#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \\\n((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \\\n DMA2_Stream7)\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n/* Exported functions --------------------------------------------------------*/\n /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions\n  * @{\n  */\n\n/** @defgroup DMA_LL_EF_Configuration Configuration\n  * @{\n  */\n/**\n  * @brief Enable DMA stream.\n  * @rmtoll CR          EN            LL_DMA_EnableStream\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);\n}\n\n/**\n  * @brief Disable DMA stream.\n  * @rmtoll CR          EN            LL_DMA_DisableStream\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);\n}\n\n/**\n  * @brief Check if DMA stream is enabled or disabled.\n  * @rmtoll CR          EN            LL_DMA_IsEnabledStream\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));\n}\n\n/**\n  * @brief  Configure all parameters linked to DMA transfer.\n  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\\n\n  *         CR          CIRC          LL_DMA_ConfigTransfer\\n\n  *         CR          PINC          LL_DMA_ConfigTransfer\\n\n  *         CR          MINC          LL_DMA_ConfigTransfer\\n\n  *         CR          PSIZE         LL_DMA_ConfigTransfer\\n\n  *         CR          MSIZE         LL_DMA_ConfigTransfer\\n\n  *         CR          PL            LL_DMA_ConfigTransfer\\n\n  *         CR          PFCTRL        LL_DMA_ConfigTransfer\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Configuration This parameter must be a combination of all the following values:\n  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY\n  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL\n  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT\n  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT\n  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD\n  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD\n  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH\n  *@retval None\n  */\n__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,\n             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,\n             Configuration);\n}\n\n/**\n  * @brief Set Data transfer direction (read from peripheral or from memory).\n  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Direction This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);\n}\n\n/**\n  * @brief Get Data transfer direction (read from peripheral or from memory).\n  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));\n}\n\n/**\n  * @brief Set DMA mode normal, circular or peripheral flow control.\n  * @rmtoll CR          CIRC           LL_DMA_SetMode\\n\n  *         CR          PFCTRL         LL_DMA_SetMode\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Mode This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_MODE_NORMAL\n  *         @arg @ref LL_DMA_MODE_CIRCULAR\n  *         @arg @ref LL_DMA_MODE_PFCTRL\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);\n}\n\n/**\n  * @brief Get DMA mode normal, circular or peripheral flow control.\n  * @rmtoll CR          CIRC           LL_DMA_GetMode\\n\n  *         CR          PFCTRL         LL_DMA_GetMode\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_MODE_NORMAL\n  *         @arg @ref LL_DMA_MODE_CIRCULAR\n  *         @arg @ref LL_DMA_MODE_PFCTRL\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));\n}\n\n/**\n  * @brief Set Peripheral increment mode.\n  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  IncrementMode This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT\n  *         @arg @ref LL_DMA_PERIPH_INCREMENT\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);\n}\n\n/**\n  * @brief Get Peripheral increment mode.\n  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT\n  *         @arg @ref LL_DMA_PERIPH_INCREMENT\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));\n}\n\n/**\n  * @brief Set Memory increment mode.\n  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  IncrementMode This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT\n  *         @arg @ref LL_DMA_MEMORY_INCREMENT\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);\n}\n\n/**\n  * @brief Get Memory increment mode.\n  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT\n  *         @arg @ref LL_DMA_MEMORY_INCREMENT\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));\n}\n\n/**\n  * @brief Set Peripheral size.\n  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Size This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_PDATAALIGN_BYTE\n  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD\n  *         @arg @ref LL_DMA_PDATAALIGN_WORD\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);\n}\n\n/**\n  * @brief Get Peripheral size.\n  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_PDATAALIGN_BYTE\n  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD\n  *         @arg @ref LL_DMA_PDATAALIGN_WORD\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));\n}\n\n/**\n  * @brief Set Memory size.\n  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Size This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_MDATAALIGN_BYTE\n  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD\n  *         @arg @ref LL_DMA_MDATAALIGN_WORD\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);\n}\n\n/**\n  * @brief Get Memory size.\n  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_MDATAALIGN_BYTE\n  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD\n  *         @arg @ref LL_DMA_MDATAALIGN_WORD\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));\n}\n\n/**\n  * @brief Set Peripheral increment offset size.\n  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  OffsetSize This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE\n  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);\n}\n\n/**\n  * @brief Get Peripheral increment offset size.\n  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE\n  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));\n}\n\n/**\n  * @brief Set Stream priority level.\n  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Priority This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_PRIORITY_LOW\n  *         @arg @ref LL_DMA_PRIORITY_MEDIUM\n  *         @arg @ref LL_DMA_PRIORITY_HIGH\n  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);\n}\n\n/**\n  * @brief Get Stream priority level.\n  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_PRIORITY_LOW\n  *         @arg @ref LL_DMA_PRIORITY_MEDIUM\n  *         @arg @ref LL_DMA_PRIORITY_HIGH\n  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));\n}\n\n/**\n  * @brief Set Number of data to transfer.\n  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength\n  * @note   This action has no effect if\n  *         stream is enabled.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  NbData Between 0 to 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);\n}\n\n/**\n  * @brief Get Number of data to transfer.\n  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength\n  * @note   Once the stream is enabled, the return value indicate the\n  *         remaining bytes to be transmitted.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Between 0 to 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));\n}\n\n/**\n  * @brief Select Channel number associated to the Stream.\n  * @rmtoll CR          CHSEL           LL_DMA_SetChannelSelection\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_0\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);\n}\n\n/**\n  * @brief Get the Channel number associated to the Stream.\n  * @rmtoll CR          CHSEL           LL_DMA_GetChannelSelection\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_0\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));\n}\n\n/**\n  * @brief Set Memory burst transfer configuration.\n  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Mburst This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_MBURST_SINGLE\n  *         @arg @ref LL_DMA_MBURST_INC4\n  *         @arg @ref LL_DMA_MBURST_INC8\n  *         @arg @ref LL_DMA_MBURST_INC16\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);\n}\n\n/**\n  * @brief Get Memory burst transfer configuration.\n  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_MBURST_SINGLE\n  *         @arg @ref LL_DMA_MBURST_INC4\n  *         @arg @ref LL_DMA_MBURST_INC8\n  *         @arg @ref LL_DMA_MBURST_INC16\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));\n}\n\n/**\n  * @brief Set  Peripheral burst transfer configuration.\n  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Pburst This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_PBURST_SINGLE\n  *         @arg @ref LL_DMA_PBURST_INC4\n  *         @arg @ref LL_DMA_PBURST_INC8\n  *         @arg @ref LL_DMA_PBURST_INC16\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);\n}\n\n/**\n  * @brief Get Peripheral burst transfer configuration.\n  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_PBURST_SINGLE\n  *         @arg @ref LL_DMA_PBURST_INC4\n  *         @arg @ref LL_DMA_PBURST_INC8\n  *         @arg @ref LL_DMA_PBURST_INC16\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));\n}\n\n/**\n  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.\n  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem \n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param CurrentMemory This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CURRENTTARGETMEM0\n  *         @arg @ref LL_DMA_CURRENTTARGETMEM1\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)\n{\n   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);\n}\n\n/**\n  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.\n  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem \n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_CURRENTTARGETMEM0\n  *         @arg @ref LL_DMA_CURRENTTARGETMEM1\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));\n}\n\n/**\n  * @brief Enable the double buffer mode.\n  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);\n}\n\n/**\n  * @brief Disable the double buffer mode.\n  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode \n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);\n}\n\n/**\n  * @brief Get FIFO status.\n  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_FIFOSTATUS_0_25\n  *         @arg @ref LL_DMA_FIFOSTATUS_25_50\n  *         @arg @ref LL_DMA_FIFOSTATUS_50_75\n  *         @arg @ref LL_DMA_FIFOSTATUS_75_100\n  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY\n  *         @arg @ref LL_DMA_FIFOSTATUS_FULL\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));\n}\n\n/**\n  * @brief Disable Fifo mode.\n  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);\n}\n\n/**\n  * @brief Enable Fifo mode.\n  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode \n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);\n}\n\n/**\n  * @brief Select FIFO threshold.\n  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Threshold This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);\n}\n\n/**\n  * @brief Get FIFO threshold.\n  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));\n}\n\n/**\n  * @brief Configure the FIFO .\n  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\\n\n  *         FCR         DMDIS        LL_DMA_ConfigFifo\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  FifoMode This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_FIFOMODE_ENABLE\n  *         @arg @ref LL_DMA_FIFOMODE_DISABLE\n  * @param  FifoThreshold This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);\n}\n\n/**\n  * @brief Configure the Source and Destination addresses.\n  * @note   This API must not be called when the DMA stream is enabled.\n  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\\n \n  *         PAR         PA          LL_DMA_ConfigAddresses\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  SrcAddress Between 0 to 0xFFFFFFFF\n  * @param  DstAddress Between 0 to 0xFFFFFFFF\n  * @param  Direction This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)\n{\n  /* Direction Memory to Periph */\n  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)\n  {\n    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);\n    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);\n  }\n  /* Direction Periph to Memory and Memory to Memory */\n  else\n  {\n    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);\n    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);\n  }\n}\n\n/**\n  * @brief  Set the Memory address.\n  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress\n  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  MemoryAddress Between 0 to 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)\n{\n  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);\n}\n\n/**\n  * @brief  Set the Peripheral address.\n  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress\n  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  PeriphAddress Between 0 to 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)\n{\n  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);\n}\n\n/**\n  * @brief  Get the Memory address.\n  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress\n  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Between 0 to 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)\n{\n  return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));\n}\n\n/**\n  * @brief  Get the Peripheral address.\n  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress\n  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Between 0 to 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)\n{\n  return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));\n}\n\n/**\n  * @brief  Set the Memory to Memory Source address.\n  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress\n  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  MemoryAddress Between 0 to 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)\n{\n  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);\n}\n\n/**\n  * @brief  Set the Memory to Memory Destination address.\n  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress\n  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  MemoryAddress Between 0 to 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)\n  {\n    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);\n  }\n\n/**\n  * @brief  Get the Memory to Memory Source address.\n  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress\n  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Between 0 to 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)\n  {\n   return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));\n  }\n\n/**\n  * @brief  Get the Memory to Memory Destination address.\n  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress\n  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Between 0 to 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)\n{\n return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));\n}\n\n/**\n  * @brief Set Memory 1 address (used in case of Double buffer mode).\n  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  Address Between 0 to 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)\n{\n  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);\n}\n\n/**\n  * @brief Get Memory 1 address (used in case of Double buffer mode).\n  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval Between 0 to 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief Get Stream 0 half transfer flag.\n  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));\n}\n\n/**\n  * @brief Get Stream 1 half transfer flag.\n  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));\n}\n\n/**\n  * @brief Get Stream 2 half transfer flag.\n  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));\n}\n\n/**\n  * @brief Get Stream 3 half transfer flag.\n  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));\n}\n\n/**\n  * @brief Get Stream 4 half transfer flag.\n  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));\n}\n\n/**\n  * @brief Get Stream 5 half transfer flag.\n  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));\n}\n\n/**\n  * @brief Get Stream 6 half transfer flag.\n  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));\n}\n\n/**\n  * @brief Get Stream 7 half transfer flag.\n  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));\n} \n\n/**\n  * @brief Get Stream 0 transfer complete flag.\n  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));\n}\n\n/**\n  * @brief Get Stream 1 transfer complete flag.\n  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));\n}\n\n/**\n  * @brief Get Stream 2 transfer complete flag.\n  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));\n}\n\n/**\n  * @brief Get Stream 3 transfer complete flag.\n  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));\n}\n\n/**\n  * @brief Get Stream 4 transfer complete flag.\n  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));\n}\n\n/**\n  * @brief Get Stream 5 transfer complete flag.\n  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));\n}\n\n/**\n  * @brief Get Stream 6 transfer complete flag.\n  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));\n}\n\n/**\n  * @brief Get Stream 7 transfer complete flag.\n  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));\n} \n\n/**\n  * @brief Get Stream 0 transfer error flag.\n  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));\n}\n\n/**\n  * @brief Get Stream 1 transfer error flag.\n  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));\n}\n\n/**\n  * @brief Get Stream 2 transfer error flag.\n  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));\n}\n\n/**\n  * @brief Get Stream 3 transfer error flag.\n  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));\n}\n\n/**\n  * @brief Get Stream 4 transfer error flag.\n  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));\n}\n\n/**\n  * @brief Get Stream 5 transfer error flag.\n  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));\n}\n\n/**\n  * @brief Get Stream 6 transfer error flag.\n  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));\n}\n\n/**\n  * @brief Get Stream 7 transfer error flag.\n  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));\n} \n\n/**\n  * @brief Get Stream 0 direct mode error flag.\n  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));\n}\n\n/**\n  * @brief Get Stream 1 direct mode error flag.\n  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));\n}\n\n/**\n  * @brief Get Stream 2 direct mode error flag.\n  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));\n}\n\n/**\n  * @brief Get Stream 3 direct mode error flag.\n  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));\n}\n\n/**\n  * @brief Get Stream 4 direct mode error flag.\n  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));\n}\n\n/**\n  * @brief Get Stream 5 direct mode error flag.\n  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));\n}\n\n/**\n  * @brief Get Stream 6 direct mode error flag.\n  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));\n}\n\n/**\n  * @brief Get Stream 7 direct mode error flag.\n  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));\n}\n\n/**\n  * @brief Get Stream 0 FIFO error flag.\n  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));\n}\n\n/**\n  * @brief Get Stream 1 FIFO error flag.\n  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));\n}\n\n/**\n  * @brief Get Stream 2 FIFO error flag.\n  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));\n}\n\n/**\n  * @brief Get Stream 3 FIFO error flag.\n  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));\n}\n\n/**\n  * @brief Get Stream 4 FIFO error flag.\n  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));\n}\n\n/**\n  * @brief Get Stream 5 FIFO error flag.\n  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));\n}\n\n/**\n  * @brief Get Stream 6 FIFO error flag.\n  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));\n}\n\n/**\n  * @brief Get Stream 7 FIFO error flag.\n  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));\n}\n\n/**\n  * @brief Clear Stream 0 half transfer flag.\n  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);\n}\n\n/**\n  * @brief Clear Stream 1 half transfer flag.\n  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);\n}\n\n/**\n  * @brief Clear Stream 2 half transfer flag.\n  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);\n}\n\n/**\n  * @brief Clear Stream 3 half transfer flag.\n  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);\n}\n\n/**\n  * @brief Clear Stream 4 half transfer flag.\n  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);\n}\n\n/**\n  * @brief Clear Stream 5 half transfer flag.\n  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);\n}\n\n/**\n  * @brief Clear Stream 6 half transfer flag.\n  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);\n}\n\n/**\n  * @brief Clear Stream 7 half transfer flag.\n  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);\n}\n\n/**\n  * @brief Clear Stream 0 transfer complete flag.\n  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);\n}\n\n/**\n  * @brief Clear Stream 1 transfer complete flag.\n  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);\n}\n\n/**\n  * @brief Clear Stream 2 transfer complete flag.\n  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);\n}\n\n/**\n  * @brief Clear Stream 3 transfer complete flag.\n  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);\n}\n\n/**\n  * @brief Clear Stream 4 transfer complete flag.\n  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);\n}\n\n/**\n  * @brief Clear Stream 5 transfer complete flag.\n  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);\n}\n\n/**\n  * @brief Clear Stream 6 transfer complete flag.\n  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);\n}\n\n/**\n  * @brief Clear Stream 7 transfer complete flag.\n  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);\n}\n\n/**\n  * @brief Clear Stream 0 transfer error flag.\n  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);\n}\n\n/**\n  * @brief Clear Stream 1 transfer error flag.\n  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);\n}\n\n/**\n  * @brief Clear Stream 2 transfer error flag.\n  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);\n}\n\n/**\n  * @brief Clear Stream 3 transfer error flag.\n  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);\n}\n\n/**\n  * @brief Clear Stream 4 transfer error flag.\n  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);\n}\n\n/**\n  * @brief Clear Stream 5 transfer error flag.\n  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);\n}\n\n/**\n  * @brief Clear Stream 6 transfer error flag.\n  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);\n}\n\n/**\n  * @brief Clear Stream 7 transfer error flag.\n  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);\n}\n\n/**\n  * @brief Clear Stream 0 direct mode error flag.\n  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);\n}\n\n/**\n  * @brief Clear Stream 1 direct mode error flag.\n  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);\n}\n\n/**\n  * @brief Clear Stream 2 direct mode error flag.\n  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);\n}\n\n/**\n  * @brief Clear Stream 3 direct mode error flag.\n  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);\n}\n\n/**\n  * @brief Clear Stream 4 direct mode error flag.\n  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);\n}\n\n/**\n  * @brief Clear Stream 5 direct mode error flag.\n  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);\n}\n\n/**\n  * @brief Clear Stream 6 direct mode error flag.\n  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);\n}\n\n/**\n  * @brief Clear Stream 7 direct mode error flag.\n  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);\n}\n\n/**\n  * @brief Clear Stream 0 FIFO error flag.\n  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);\n}\n\n/**\n  * @brief Clear Stream 1 FIFO error flag.\n  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);\n}\n\n/**\n  * @brief Clear Stream 2 FIFO error flag.\n  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);\n}\n\n/**\n  * @brief Clear Stream 3 FIFO error flag.\n  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);\n}\n\n/**\n  * @brief Clear Stream 4 FIFO error flag.\n  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);\n}\n\n/**\n  * @brief Clear Stream 5 FIFO error flag.\n  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);\n}\n\n/**\n  * @brief Clear Stream 6 FIFO error flag.\n  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);\n}\n\n/**\n  * @brief Clear Stream 7 FIFO error flag.\n  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EF_IT_Management IT_Management\n  * @{\n  */\n\n/**\n  * @brief Enable Half transfer interrupt.\n  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);\n}\n\n/**\n  * @brief Enable Transfer error interrupt.\n  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);\n}\n\n/**\n  * @brief Enable Transfer complete interrupt.\n  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);\n}\n\n/**\n  * @brief Enable Direct mode error interrupt.\n  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);\n}\n\n/**\n  * @brief Enable FIFO error interrupt.\n  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);\n}\n\n/**\n  * @brief Disable Half transfer interrupt.\n  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);\n}\n\n/**\n  * @brief Disable Transfer error interrupt.\n  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);\n}\n\n/**\n  * @brief Disable Transfer complete interrupt.\n  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);\n}\n\n/**\n  * @brief Disable Direct mode error interrupt.\n  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);\n}\n\n/**\n  * @brief Disable FIFO error interrupt.\n  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);\n}\n\n/**\n  * @brief Check if Half transfer interrup is enabled.\n  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);\n}\n\n/**\n  * @brief Check if Transfer error nterrup is enabled.\n  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);\n}\n\n/**\n  * @brief Check if Transfer complete interrup is enabled.\n  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);\n}\n\n/**\n  * @brief Check if Direct mode error interrupt is enabled.\n  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);\n}\n\n/**\n  * @brief Check if FIFO error interrup is enabled.\n  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\nuint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);\nuint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);\nvoid LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* DMA1 || DMA2 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_DMA_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_exti.h\n  * @author  MCD Application Team\n  * @brief   Header file of EXTI LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_EXTI_H\n#define __STM32F4xx_LL_EXTI_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (EXTI)\n\n/** @defgroup EXTI_LL EXTI\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private Macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure\n  * @{\n  */\ntypedef struct\n{\n\n  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31\n                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */\n\n  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.\n                                     This parameter can be set either to ENABLE or DISABLE */\n\n  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.\n                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */\n\n  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.\n                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */\n} LL_EXTI_InitTypeDef;\n\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants\n  * @{\n  */\n\n/** @defgroup EXTI_LL_EC_LINE LINE\n  * @{\n  */\n#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */\n#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */\n#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */\n#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */\n#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */\n#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */\n#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */\n#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */\n#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */\n#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */\n#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */\n#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */\n#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */\n#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */\n#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */\n#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */\n#if defined(EXTI_IMR_IM16)\n#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */\n#endif\n#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */\n#if defined(EXTI_IMR_IM18)\n#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */\n#endif\n#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */\n#if defined(EXTI_IMR_IM20)\n#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */\n#endif\n#if defined(EXTI_IMR_IM21)\n#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */\n#endif\n#if defined(EXTI_IMR_IM22)\n#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */\n#endif\n#if defined(EXTI_IMR_IM23)\n#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */\n#endif\n#if defined(EXTI_IMR_IM24)\n#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */\n#endif\n#if defined(EXTI_IMR_IM25)\n#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */\n#endif\n#if defined(EXTI_IMR_IM26)\n#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */\n#endif\n#if defined(EXTI_IMR_IM27)\n#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */\n#endif\n#if defined(EXTI_IMR_IM28)\n#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */\n#endif\n#if defined(EXTI_IMR_IM29)\n#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */\n#endif\n#if defined(EXTI_IMR_IM30)\n#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */\n#endif\n#if defined(EXTI_IMR_IM31)\n#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */\n#endif\n#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/\n\n\n#define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */\n\n#if defined(USE_FULL_LL_DRIVER)\n#define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/**\n  * @}\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/** @defgroup EXTI_LL_EC_MODE Mode\n  * @{\n  */\n#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */\n#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */\n#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger\n  * @{\n  */\n#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */\n#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */\n#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */\n#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */\n\n/**\n  * @}\n  */\n\n\n#endif /*USE_FULL_LL_DRIVER*/\n\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros\n  * @{\n  */\n\n/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in EXTI register\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in EXTI register\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)\n/**\n  * @}\n  */\n\n\n/**\n  * @}\n  */\n\n\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions\n * @{\n */\n/** @defgroup EXTI_LL_EF_IT_Management IT_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31\n  * @note The reset value for the direct or internal lines (see RM)\n  *       is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->IMR, ExtiLine);\n}\n\n/**\n  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31\n  * @note The reset value for the direct or internal lines (see RM)\n  *       is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->IMR, ExtiLine);\n}\n\n\n/**\n  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31\n  * @note The reset value for the direct or internal lines (see RM)\n  *       is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));\n}\n\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Event_Management Event_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31\n  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->EMR, ExtiLine);\n\n}\n\n\n/**\n  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31\n  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->EMR, ExtiLine);\n}\n\n\n/**\n  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31\n  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));\n\n}\n\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a rising edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_RTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->RTSR, ExtiLine);\n\n}\n\n\n/**\n  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a rising edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_RTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->RTSR, ExtiLine);\n\n}\n\n\n/**\n  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31\n  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));\n}\n\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a falling edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_FTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->FTSR, ExtiLine);\n}\n\n\n/**\n  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a Falling edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_FTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for the same interrupt line.\n  *       In this case, both generate a trigger condition.\n  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->FTSR, ExtiLine);\n}\n\n\n/**\n  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31\n  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));\n}\n\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management\n  * @{\n  */\n\n/**\n  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31\n  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to\n  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR\n  *       resulting in an interrupt request generation.\n  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR\n  *       register (by writing a 1 into the bit)\n  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->SWIER, ExtiLine);\n}\n\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management\n  * @{\n  */\n\n/**\n  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));\n}\n\n\n/**\n  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval @note This bit is set when the selected edge event arrives on the interrupt\n  */\n__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)\n{\n  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));\n}\n\n\n/**\n  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19(*)\n  *         @arg @ref LL_EXTI_LINE_20(*)\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  * @note   (*): Available in some devices\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)\n{\n  WRITE_REG(EXTI->PR, ExtiLine);\n}\n\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\nuint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);\nuint32_t LL_EXTI_DeInit(void);\nvoid LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);\n\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* EXTI */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_EXTI_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_gpio.h\n  * @author  MCD Application Team\n  * @brief   Header file of GPIO LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_GPIO_H\n#define __STM32F4xx_LL_GPIO_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)\n\n/** @defgroup GPIO_LL GPIO\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures\n  * @{\n  */\n\n/**\n  * @brief LL GPIO Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.\n                              This parameter can be any value of @ref GPIO_LL_EC_PIN */\n\n  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_MODE.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/\n\n  uint32_t Speed;        /*!< Specifies the speed for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/\n\n  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/\n\n  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_PULL.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/\n\n  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_AF.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/\n} LL_GPIO_InitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EC_PIN PIN\n  * @{\n  */\n#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */\n#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */\n#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */\n#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */\n#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */\n#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */\n#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */\n#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */\n#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */\n#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */\n#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */\n#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */\n#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */\n#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */\n#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */\n#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */\n#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \\\n                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \\\n                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \\\n                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \\\n                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \\\n                                           GPIO_BSRR_BS_15) /*!< Select all pins */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_MODE Mode\n  * @{\n  */\n#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */\n#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */\n#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */\n#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_OUTPUT Output Type\n  * @{\n  */\n#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */\n#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_SPEED Output Speed\n  * @{\n  */\n#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */\n#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */\n#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed   */\n#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down\n  * @{\n  */\n#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */\n#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */\n#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_AF Alternate Function\n  * @{\n  */\n#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */\n#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */\n#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */\n#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */\n#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */\n#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */\n#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */\n#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */\n#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */\n#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */\n#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */\n#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */\n#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */\n#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */\n#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */\n#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in GPIO register\n  * @param  __INSTANCE__ GPIO Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in GPIO register\n  * @param  __INSTANCE__ GPIO Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration\n  * @{\n  */\n\n/**\n  * @brief  Configure gpio mode for a dedicated pin on dedicated port.\n  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Mode This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_MODE_INPUT\n  *         @arg @ref LL_GPIO_MODE_OUTPUT\n  *         @arg @ref LL_GPIO_MODE_ALTERNATE\n  *         @arg @ref LL_GPIO_MODE_ANALOG\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)\n{\n  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio mode for a dedicated pin on dedicated port.\n  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_MODE_INPUT\n  *         @arg @ref LL_GPIO_MODE_OUTPUT\n  *         @arg @ref LL_GPIO_MODE_ALTERNATE\n  *         @arg @ref LL_GPIO_MODE_ANALOG\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->MODER,\n                             (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio output type for several pins on dedicated port.\n  * @note   Output type as to be set when gpio pin is in output or\n  *         alternate modes. Possible type are Push-pull or Open-drain.\n  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @param  OutputType This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL\n  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)\n{\n  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));\n}\n\n/**\n  * @brief  Return gpio output type for several pins on dedicated port.\n  * @note   Output type as to be set when gpio pin is in output or\n  *         alternate modes. Possible type are Push-pull or Open-drain.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL\n  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));\n}\n\n/**\n  * @brief  Configure gpio speed for a dedicated pin on dedicated port.\n  * @note   I/O speed can be Low, Medium, Fast or High speed.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @note   Refer to datasheet for frequency specifications and the power\n  *         supply and load conditions for each speed.\n  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Speed This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW\n  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM\n  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH\n  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)\n{\n  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),\n             (Speed << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio speed for a dedicated pin on dedicated port.\n  * @note   I/O speed can be Low, Medium, Fast or High speed.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @note   Refer to datasheet for frequency specifications and the power\n  *         supply and load conditions for each speed.\n  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW\n  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM\n  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH\n  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,\n                             (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Pull This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PULL_NO\n  *         @arg @ref LL_GPIO_PULL_UP\n  *         @arg @ref LL_GPIO_PULL_DOWN\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)\n{\n  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_PULL_NO\n  *         @arg @ref LL_GPIO_PULL_UP\n  *         @arg @ref LL_GPIO_PULL_DOWN\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->PUPDR,\n                             (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  * @param  Alternate This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)\n{\n  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),\n             (Alternate << (POSITION_VAL(Pin) * 4U)));\n}\n\n/**\n  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.\n  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->AFR[0],\n                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));\n}\n\n/**\n  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Alternate This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)\n{\n  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),\n             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));\n}\n\n/**\n  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->AFR[1],\n                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));\n}\n\n\n/**\n  * @brief  Lock configuration of several pins for a dedicated port.\n  * @note   When the lock sequence has been applied on a port bit, the\n  *         value of this port bit can no longer be modified until the\n  *         next reset.\n  * @note   Each lock bit freezes a specific configuration register\n  *         (control and alternate function registers).\n  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  __IO uint32_t temp;\n  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);\n  WRITE_REG(GPIOx->LCKR, PinMask);\n  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);\n  temp = READ_REG(GPIOx->LCKR);\n  (void) temp;\n}\n\n/**\n  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.\n  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.\n  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked\n  * @param  GPIOx GPIO Port\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)\n{\n  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EF_Data_Access Data Access\n  * @{\n  */\n\n/**\n  * @brief  Return full input data register value for a dedicated port.\n  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort\n  * @param  GPIOx GPIO Port\n  * @retval Input data register value of port\n  */\n__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)\n{\n  return (uint32_t)(READ_REG(GPIOx->IDR));\n}\n\n/**\n  * @brief  Return if input data level for several pins of dedicated port is high or low.\n  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Write output data register for the port.\n  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort\n  * @param  GPIOx GPIO Port\n  * @param  PortValue Level value for each pin of the port\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)\n{\n  WRITE_REG(GPIOx->ODR, PortValue);\n}\n\n/**\n  * @brief  Return full output data register value for a dedicated port.\n  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort\n  * @param  GPIOx GPIO Port\n  * @retval Output data register value of port\n  */\n__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)\n{\n  return (uint32_t)(READ_REG(GPIOx->ODR));\n}\n\n/**\n  * @brief  Return if input data level for several pins of dedicated port is high or low.\n  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Set several pins to high level on dedicated gpio port.\n  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->BSRR, PinMask);\n}\n\n/**\n  * @brief  Set several pins to low level on dedicated gpio port.\n  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->BSRR, (PinMask << 16));\n}\n\n/**\n  * @brief  Toggle data value for several pin of dedicated port.\n  * @rmtoll ODR          ODy           LL_GPIO_TogglePin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\nErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);\nErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);\nvoid        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_GPIO_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_pwr.h\n  * @author  MCD Application Team\n  * @brief   Header file of PWR LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_PWR_H\n#define __STM32F4xx_LL_PWR_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(PWR)\n\n/** @defgroup PWR_LL PWR\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants\n  * @{\n  */\n\n/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_PWR_WriteReg function\n  * @{\n  */\n#define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */\n#define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_PWR_ReadReg function\n  * @{\n  */\n#define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */\n#define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */\n#define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */\n#define LL_PWR_CSR_VOS                     PWR_CSR_VOSRDY            /*!< Voltage scaling select flag */\n#if defined(PWR_CSR_EWUP)\n#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP           /*!< Enable WKUP pin */\n#elif defined(PWR_CSR_EWUP1)\n#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */\n#endif /* PWR_CSR_EWUP */\n#if defined(PWR_CSR_EWUP2)\n#define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */\n#endif /* PWR_CSR_EWUP2 */\n#if defined(PWR_CSR_EWUP3)\n#define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */\n#endif /* PWR_CSR_EWUP3 */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage\n  * @{\n  */\n#if defined(PWR_CR_VOS_0)\n#define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0)\n#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)\n#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */\n#else\n#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS)\n#define LL_PWR_REGU_VOLTAGE_SCALE2         0x00000000U\n#endif /* PWR_CR_VOS_0 */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_MODE_PWR Mode Power\n  * @{\n  */\n#define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */\n#define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */\n#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)\n#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE  (PWR_CR_MRUDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */\n#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE    (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */\n#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */\n#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)\n#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP  (PWR_CR_MRLVDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */\n#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP    (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */\n#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */\n#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode\n * @{\n */\n#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */\n#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level\n  * @{\n  */\n#define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */\n#define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */\n#define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */\n#define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */\n#define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */\n#define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */\n#define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */\n#define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */\n/**\n  * @}\n  */\n/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins\n  * @{\n  */\n#if defined(PWR_CSR_EWUP)\n#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)         /*!< WKUP pin : PA0 */\n#endif /* PWR_CSR_EWUP */\n#if defined(PWR_CSR_EWUP1)\n#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */\n#endif /* PWR_CSR_EWUP1 */\n#if defined(PWR_CSR_EWUP2)\n#define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC0 or PC13 according to device */\n#endif /* PWR_CSR_EWUP2 */\n#if defined(PWR_CSR_EWUP3)\n#define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PC1 */\n#endif /* PWR_CSR_EWUP3 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros\n  * @{\n  */\n\n/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in PWR register\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in PWR register\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions\n  * @{\n  */\n\n/** @defgroup PWR_LL_EF_Configuration Configuration\n  * @{\n  */\n#if defined(PWR_CR_FISSR)\n/**\n  * @brief  Enable FLASH interface STOP while system Run is ON\n  * @rmtoll CR    FISSR       LL_PWR_EnableFLASHInterfaceSTOP\n  * @note  This mode is enabled only with STOP low power mode.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_FISSR);\n}\n\n/**\n  * @brief  Disable FLASH Interface STOP while system Run is ON\n  * @rmtoll CR    FISSR       LL_PWR_DisableFLASHInterfaceSTOP\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);\n}\n\n/**\n  * @brief  Check if FLASH Interface STOP while system Run feature is enabled\n  * @rmtoll CR    FISSR       LL_PWR_IsEnabledFLASHInterfaceSTOP\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));\n}\n#endif /* PWR_CR_FISSR */\n\n#if defined(PWR_CR_FMSSR)\n/**\n  * @brief  Enable FLASH Memory STOP while system Run is ON\n  * @rmtoll CR    FMSSR       LL_PWR_EnableFLASHMemorySTOP\n  * @note  This mode is enabled only with STOP low power mode.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_FMSSR);\n}\n\n/**\n  * @brief  Disable FLASH Memory STOP while system Run is ON\n  * @rmtoll CR    FMSSR       LL_PWR_DisableFLASHMemorySTOP\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);\n}\n\n/**\n  * @brief  Check if FLASH Memory STOP while system Run feature is enabled\n  * @rmtoll CR    FMSSR       LL_PWR_IsEnabledFLASHMemorySTOP\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));\n}\n#endif /* PWR_CR_FMSSR */\n#if defined(PWR_CR_UDEN)\n/**\n  * @brief  Enable Under Drive Mode\n  * @rmtoll CR    UDEN       LL_PWR_EnableUnderDriveMode\n  * @note  This mode is enabled only with STOP low power mode.\n  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This \n  *        mode is only available when the main Regulator or the low power Regulator \n  *        is in low voltage mode.      \n  * @note  If the Under-drive mode was enabled, it is automatically disabled after \n  *        exiting Stop mode. \n  *        When the voltage Regulator operates in Under-drive mode, an additional  \n  *        startup delay is induced when waking up from Stop mode.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_UDEN);\n}\n\n/**\n  * @brief  Disable Under Drive Mode\n  * @rmtoll CR    UDEN       LL_PWR_DisableUnderDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_UDEN);\n}\n\n/**\n  * @brief  Check if Under Drive Mode is enabled\n  * @rmtoll CR    UDEN       LL_PWR_IsEnabledUnderDriveMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));\n}\n#endif /* PWR_CR_UDEN */\n\n#if defined(PWR_CR_ODSWEN)\n/**\n  * @brief  Enable Over drive switching\n  * @rmtoll CR    ODSWEN       LL_PWR_EnableOverDriveSwitching\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_ODSWEN);\n}\n\n/**\n  * @brief  Disable Over drive switching\n  * @rmtoll CR    ODSWEN       LL_PWR_DisableOverDriveSwitching\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);\n}\n\n/**\n  * @brief  Check if Over drive switching is enabled\n  * @rmtoll CR    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));\n}\n#endif /* PWR_CR_ODSWEN */\n#if defined(PWR_CR_ODEN)\n/**\n  * @brief  Enable Over drive Mode\n  * @rmtoll CR    ODEN       LL_PWR_EnableOverDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_ODEN);\n}\n\n/**\n  * @brief  Disable Over drive Mode\n  * @rmtoll CR    ODEN       LL_PWR_DisableOverDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_ODEN);\n}\n\n/**\n  * @brief  Check if Over drive switching is enabled\n  * @rmtoll CR    ODEN       LL_PWR_IsEnabledOverDriveMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));\n}\n#endif /* PWR_CR_ODEN */\n#if defined(PWR_CR_MRUDS)\n/**\n  * @brief  Enable Main Regulator in deepsleep under-drive Mode\n  * @rmtoll CR    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_MRUDS);\n}\n\n/**\n  * @brief  Disable Main Regulator in deepsleep under-drive Mode\n  * @rmtoll CR    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);\n}\n\n/**\n  * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled\n  * @rmtoll CR    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));\n}\n#endif /* PWR_CR_MRUDS */\n\n#if defined(PWR_CR_LPUDS)\n/**\n  * @brief  Enable Low Power Regulator in deepsleep under-drive Mode\n  * @rmtoll CR    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_LPUDS);\n}\n\n/**\n  * @brief  Disable Low Power Regulator in deepsleep under-drive Mode\n  * @rmtoll CR    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);\n}\n\n/**\n  * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled\n  * @rmtoll CR    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));\n}\n#endif /* PWR_CR_LPUDS */\n\n#if defined(PWR_CR_MRLVDS)\n/**\n  * @brief  Enable Main Regulator low voltage Mode\n  * @rmtoll CR    MRLVDS       LL_PWR_EnableMainRegulatorLowVoltageMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_MRLVDS);\n}\n\n/**\n  * @brief  Disable Main Regulator low voltage Mode\n  * @rmtoll CR    MRLVDS       LL_PWR_DisableMainRegulatorLowVoltageMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);\n}\n\n/**\n  * @brief  Check if Main Regulator low voltage Mode is enabled\n  * @rmtoll CR    MRLVDS       LL_PWR_IsEnabledMainRegulatorLowVoltageMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));\n}\n#endif /* PWR_CR_MRLVDS */\n\n#if defined(PWR_CR_LPLVDS)\n/**\n  * @brief  Enable Low Power Regulator low voltage Mode\n  * @rmtoll CR    LPLVDS       LL_PWR_EnableLowPowerRegulatorLowVoltageMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_LPLVDS);\n}\n\n/**\n  * @brief  Disable Low Power Regulator low voltage Mode\n  * @rmtoll CR    LPLVDS       LL_PWR_DisableLowPowerRegulatorLowVoltageMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);\n}\n\n/**\n  * @brief  Check if Low Power Regulator low voltage Mode is enabled\n  * @rmtoll CR    LPLVDS       LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));\n}\n#endif /* PWR_CR_LPLVDS */\n/**\n  * @brief  Set the main internal Regulator output voltage\n  * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling\n  * @param  VoltageScaling This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3\n  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)\n{\n  MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);\n}\n\n/**\n  * @brief  Get the main internal Regulator output voltage\n  * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3\n  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));\n}\n/**\n  * @brief  Enable the Flash Power Down in Stop Mode\n  * @rmtoll CR    FPDS       LL_PWR_EnableFlashPowerDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_FPDS);\n}\n\n/**\n  * @brief  Disable the Flash Power Down in Stop Mode\n  * @rmtoll CR    FPDS       LL_PWR_DisableFlashPowerDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_FPDS);\n}\n\n/**\n  * @brief  Check if the Flash Power Down in Stop Mode is enabled\n  * @rmtoll CR    FPDS       LL_PWR_IsEnabledFlashPowerDown\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));\n}\n\n/**\n  * @brief  Enable access to the backup domain\n  * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_DBP);\n}\n\n/**\n  * @brief  Disable access to the backup domain\n  * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_DBP);\n}\n\n/**\n  * @brief  Check if the backup domain is enabled\n  * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));\n}\n/**\n  * @brief  Enable the backup Regulator\n  * @rmtoll CSR    BRE       LL_PWR_EnableBkUpRegulator\n  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.\n  * The LL_PWR_EnableBkUpAccess() must be called before using this API.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)\n{\n  SET_BIT(PWR->CSR, PWR_CSR_BRE);\n}\n\n/**\n  * @brief  Disable the backup Regulator\n  * @rmtoll CSR    BRE       LL_PWR_DisableBkUpRegulator\n  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.\n  * The LL_PWR_EnableBkUpAccess() must be called before using this API.\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)\n{\n  CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);\n}\n\n/**\n  * @brief  Check if the backup Regulator is enabled\n  * @rmtoll CSR    BRE       LL_PWR_IsEnabledBkUpRegulator\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));\n}\n\n/**\n  * @brief  Set voltage Regulator mode during deep sleep mode\n  * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS\n  * @param  RegulMode This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN\n  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)\n{\n  MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);\n}\n\n/**\n  * @brief  Get voltage Regulator mode during deep sleep mode\n  * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN\n  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));\n}\n\n/**\n  * @brief  Set Power Down mode when CPU enters deepsleep\n  * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    MRUDS        LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    LPUDS        LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    MRLVDS       LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    LPlVDS       LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\\n\n  * @rmtoll CR    LPDS         LL_PWR_SetPowerMode\n  * @param  PDMode This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)\n  *\n  *         (*) not available on all devices\n  *         @arg @ref LL_PWR_MODE_STANDBY\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)\n{\n#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)\n  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);\n#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)\n  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);\n#else\n  MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);\n#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */\n}\n\n/**\n  * @brief  Get Power Down mode when CPU enters deepsleep\n  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    MRUDS        LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    LPUDS        LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    MRLVDS       LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    LPLVDS       LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\\n\n  * @rmtoll CR    LPDS         LL_PWR_GetPowerMode\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)\n  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)\n  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)\n  *\n  *         (*) not available on all devices\n  *         @arg @ref LL_PWR_MODE_STANDBY\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)\n{\n#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)\n  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));\n#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)\n  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));\n#else\n  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));\n#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */\n}\n\n/**\n  * @brief  Configure the voltage threshold detected by the Power Voltage Detector\n  * @rmtoll CR    PLS       LL_PWR_SetPVDLevel\n  * @param  PVDLevel This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_PVDLEVEL_0\n  *         @arg @ref LL_PWR_PVDLEVEL_1\n  *         @arg @ref LL_PWR_PVDLEVEL_2\n  *         @arg @ref LL_PWR_PVDLEVEL_3\n  *         @arg @ref LL_PWR_PVDLEVEL_4\n  *         @arg @ref LL_PWR_PVDLEVEL_5\n  *         @arg @ref LL_PWR_PVDLEVEL_6\n  *         @arg @ref LL_PWR_PVDLEVEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)\n{\n  MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);\n}\n\n/**\n  * @brief  Get the voltage threshold detection\n  * @rmtoll CR    PLS       LL_PWR_GetPVDLevel\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_PVDLEVEL_0\n  *         @arg @ref LL_PWR_PVDLEVEL_1\n  *         @arg @ref LL_PWR_PVDLEVEL_2\n  *         @arg @ref LL_PWR_PVDLEVEL_3\n  *         @arg @ref LL_PWR_PVDLEVEL_4\n  *         @arg @ref LL_PWR_PVDLEVEL_5\n  *         @arg @ref LL_PWR_PVDLEVEL_6\n  *         @arg @ref LL_PWR_PVDLEVEL_7\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));\n}\n\n/**\n  * @brief  Enable Power Voltage Detector\n  * @rmtoll CR    PVDE       LL_PWR_EnablePVD\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnablePVD(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_PVDE);\n}\n\n/**\n  * @brief  Disable Power Voltage Detector\n  * @rmtoll CR    PVDE       LL_PWR_DisablePVD\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisablePVD(void)\n{\n  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);\n}\n\n/**\n  * @brief  Check if Power Voltage Detector is enabled\n  * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)\n{\n  return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));\n}\n\n/**\n  * @brief  Enable the WakeUp PINx functionality\n  * @rmtoll CSR   EWUP        LL_PWR_EnableWakeUpPin\\n\n  * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\\n\n  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\\n\n  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)\n  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)\n  *\n  *         (*) not available on all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)\n{\n  SET_BIT(PWR->CSR, WakeUpPin);\n}\n\n/**\n  * @brief  Disable the WakeUp PINx functionality\n  * @rmtoll CSR   EWUP        LL_PWR_DisableWakeUpPin\\n\n  * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\\n\n  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\\n\n  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)\n  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)\n  *\n  *         (*) not available on all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)\n{\n  CLEAR_BIT(PWR->CSR, WakeUpPin);\n}\n\n/**\n  * @brief  Check if the WakeUp PINx functionality is enabled\n  * @rmtoll CSR   EWUP        LL_PWR_IsEnabledWakeUpPin\\n\n  * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\\n\n  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\\n\n  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)\n  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)\n  *\n  *         (*) not available on all devices\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)\n{\n  return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));\n}\n\n\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Get Wake-up Flag\n  * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));\n}\n\n/**\n  * @brief  Get Standby Flag\n  * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));\n}\n\n/**\n  * @brief  Get Backup Regulator ready Flag\n  * @rmtoll CSR   BRR       LL_PWR_IsActiveFlag_BRR\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));\n}\n/**\n  * @brief  Indicate whether VDD voltage is below the selected PVD threshold\n  * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));\n}\n\n/**\n  * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level\n  * @rmtoll CSR   VOS       LL_PWR_IsActiveFlag_VOS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)\n{\n  return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));\n}\n#if defined(PWR_CR_ODEN)\n/**\n  * @brief  Indicate whether the Over-Drive mode is ready or not\n  * @rmtoll CSR   ODRDY       LL_PWR_IsActiveFlag_OD\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));\n}\n#endif /* PWR_CR_ODEN */\n\n#if defined(PWR_CR_ODSWEN)\n/**\n  * @brief  Indicate whether the Over-Drive mode switching is ready or not\n  * @rmtoll CSR   ODSWRDY       LL_PWR_IsActiveFlag_ODSW\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));\n}\n#endif /* PWR_CR_ODSWEN */\n\n#if defined(PWR_CR_UDEN)\n/**\n  * @brief  Indicate whether the Under-Drive mode is ready or not\n  * @rmtoll CSR   UDRDY       LL_PWR_IsActiveFlag_UD\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)\n{\n  return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));\n}\n#endif /* PWR_CR_UDEN */\n/**\n  * @brief  Clear Standby Flag\n  * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_CSBF);\n}\n\n/**\n  * @brief  Clear Wake-up Flags\n  * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)\n{\n  SET_BIT(PWR->CR, PWR_CR_CWUF);\n}\n#if defined(PWR_CSR_UDRDY)\n/**\n  * @brief  Clear Under-Drive ready Flag\n  * @rmtoll CSR          UDRDY         LL_PWR_ClearFlag_UD\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)\n{\n  WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);\n}\n#endif /* PWR_CSR_UDRDY */\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup PWR_LL_EF_Init De-initialization function\n  * @{\n  */\nErrorStatus LL_PWR_DeInit(void);\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(PWR) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_PWR_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_rcc.h\n  * @author  MCD Application Team\n  * @brief   Header file of RCC LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_RCC_H\n#define __STM32F4xx_LL_RCC_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @defgroup RCC_LL RCC\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup RCC_LL_Private_Variables RCC Private Variables\n  * @{\n  */\n\n#if defined(RCC_DCKCFGR_PLLSAIDIVR)\nstatic const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};\n#endif /* RCC_DCKCFGR_PLLSAIDIVR */\n\n/**\n  * @}\n  */\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_Private_Macros RCC Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_Exported_Types RCC Exported Types\n  * @{\n  */\n\n/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure\n  * @{\n  */\n\n/**\n  * @brief  RCC Clocks Frequency Structure\n  */\ntypedef struct\n{\n  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */\n  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */\n  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */\n  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */\n} LL_RCC_ClocksTypeDef;\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants\n  * @{\n  */\n\n/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation\n  * @brief    Defines used to adapt values of different oscillators\n  * @note     These values could be modified in the user environment according to \n  *           HW set-up.\n  * @{\n  */\n#if !defined  (HSE_VALUE)\n#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSI_VALUE)\n#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */\n#endif /* HSI_VALUE */\n\n#if !defined  (LSE_VALUE)\n#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */\n#endif /* LSE_VALUE */\n\n#if !defined  (LSI_VALUE)\n#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */\n#endif /* LSI_VALUE */\n\n#if !defined  (EXTERNAL_CLOCK_VALUE)\n#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */\n#endif /* EXTERNAL_CLOCK_VALUE */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_RCC_WriteReg function\n  * @{\n  */\n#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */\n#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */\n#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */\n#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */\n#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */\n#if defined(RCC_PLLI2S_SUPPORT)\n#define LL_RCC_CIR_PLLI2SRDYC             RCC_CIR_PLLI2SRDYC  /*!< PLLI2S Ready Interrupt Clear */\n#endif /* RCC_PLLI2S_SUPPORT */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_CIR_PLLSAIRDYC             RCC_CIR_PLLSAIRDYC  /*!< PLLSAI Ready Interrupt Clear */\n#endif /* RCC_PLLSAI_SUPPORT */\n#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_RCC_ReadReg function\n  * @{\n  */\n#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */\n#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */\n#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */\n#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */\n#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */\n#if defined(RCC_PLLI2S_SUPPORT)\n#define LL_RCC_CIR_PLLI2SRDYF             RCC_CIR_PLLI2SRDYF  /*!< PLLI2S Ready Interrupt flag */\n#endif /* RCC_PLLI2S_SUPPORT */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_CIR_PLLSAIRDYF             RCC_CIR_PLLSAIRDYF  /*!< PLLSAI Ready Interrupt flag */\n#endif /* RCC_PLLSAI_SUPPORT */\n#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt flag */\n#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */\n#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */\n#define LL_RCC_CSR_PORRSTF                 RCC_CSR_PORRSTF    /*!< POR/PDR reset flag */\n#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */\n#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */\n#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */\n#if defined(RCC_CSR_BORRSTF)\n#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */\n#endif /* RCC_CSR_BORRSTF */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions\n  * @{\n  */\n#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */\n#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */\n#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */\n#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */\n#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */\n#if defined(RCC_PLLI2S_SUPPORT)\n#define LL_RCC_CIR_PLLI2SRDYIE            RCC_CIR_PLLI2SRDYIE   /*!< PLLI2S Ready Interrupt Enable */\n#endif /* RCC_PLLI2S_SUPPORT */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_CIR_PLLSAIRDYIE            RCC_CIR_PLLSAIRDYIE   /*!< PLLSAI Ready Interrupt Enable */\n#endif /* RCC_PLLSAI_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch\n  * @{\n  */\n#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */\n#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */\n#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */\n#if defined(RCC_CFGR_SW_PLLR)\n#define LL_RCC_SYS_CLKSOURCE_PLLR          RCC_CFGR_SW_PLLR   /*!< PLLR selection as system clock */\n#endif /* RCC_CFGR_SW_PLLR */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status\n  * @{\n  */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR   RCC_CFGR_SWS_PLLR  /*!< PLLR used as system clock */\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler\n  * @{\n  */\n#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */\n#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */\n#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */\n#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */\n#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */\n#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */\n#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */\n#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */\n#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)\n  * @{\n  */\n#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */\n#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */\n#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */\n#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */\n#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)\n  * @{\n  */\n#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */\n#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */\n#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */\n#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */\n#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection\n  * @{\n  */\n#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)(RCC_CFGR_MCO1|0x00000000U)                    /*!< HSI selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))       /*!< LSE selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))       /*!< HSE selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U))       /*!< PLLCLK selection as MCO1 source */\n#if defined(RCC_CFGR_MCO2)\n#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)(RCC_CFGR_MCO2|0x00000000U)                    /*!< SYSCLK selection as MCO2 source */\n#define LL_RCC_MCO2SOURCE_PLLI2S           (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))       /*!< PLLI2S selection as MCO2 source */\n#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))       /*!< HSE selection as MCO2 source */\n#define LL_RCC_MCO2SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U))       /*!< PLLCLK selection as MCO2 source */\n#endif /* RCC_CFGR_MCO2 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler\n  * @{\n  */\n#define LL_RCC_MCO1_DIV_1                  (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)                       /*!< MCO1 not divided */\n#define LL_RCC_MCO1_DIV_2                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))       /*!< MCO1 divided by 2 */\n#define LL_RCC_MCO1_DIV_3                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U))       /*!< MCO1 divided by 3 */\n#define LL_RCC_MCO1_DIV_4                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U))       /*!< MCO1 divided by 4 */\n#define LL_RCC_MCO1_DIV_5                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))         /*!< MCO1 divided by 5 */\n#if defined(RCC_CFGR_MCO2PRE)\n#define LL_RCC_MCO2_DIV_1                  (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)                       /*!< MCO2 not divided */\n#define LL_RCC_MCO2_DIV_2                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))       /*!< MCO2 divided by 2 */\n#define LL_RCC_MCO2_DIV_3                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U))       /*!< MCO2 divided by 3 */\n#define LL_RCC_MCO2_DIV_4                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U))       /*!< MCO2 divided by 4 */\n#define LL_RCC_MCO2_DIV_5                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))         /*!< MCO2 divided by 5 */\n#endif /* RCC_CFGR_MCO2PRE */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock\n  * @{\n  */\n#define LL_RCC_RTC_NOCLOCK                  0x00000000U             /*!< HSE not divided */\n#define LL_RCC_RTC_HSE_DIV_2                RCC_CFGR_RTCPRE_1       /*!< HSE clock divided by 2 */\n#define LL_RCC_RTC_HSE_DIV_3                (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 3 */\n#define LL_RCC_RTC_HSE_DIV_4                RCC_CFGR_RTCPRE_2       /*!< HSE clock divided by 4 */\n#define LL_RCC_RTC_HSE_DIV_5                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 5 */\n#define LL_RCC_RTC_HSE_DIV_6                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 6 */\n#define LL_RCC_RTC_HSE_DIV_7                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 7 */\n#define LL_RCC_RTC_HSE_DIV_8                RCC_CFGR_RTCPRE_3       /*!< HSE clock divided by 8 */\n#define LL_RCC_RTC_HSE_DIV_9                (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 9 */\n#define LL_RCC_RTC_HSE_DIV_10               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 10 */\n#define LL_RCC_RTC_HSE_DIV_11               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 11 */\n#define LL_RCC_RTC_HSE_DIV_12               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 12 */\n#define LL_RCC_RTC_HSE_DIV_13               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 13 */\n#define LL_RCC_RTC_HSE_DIV_14               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 14 */\n#define LL_RCC_RTC_HSE_DIV_15               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 15 */\n#define LL_RCC_RTC_HSE_DIV_16               RCC_CFGR_RTCPRE_4       /*!< HSE clock divided by 16 */\n#define LL_RCC_RTC_HSE_DIV_17               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 17 */\n#define LL_RCC_RTC_HSE_DIV_18               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 18 */\n#define LL_RCC_RTC_HSE_DIV_19               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 19 */\n#define LL_RCC_RTC_HSE_DIV_20               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 20 */\n#define LL_RCC_RTC_HSE_DIV_21               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 21 */\n#define LL_RCC_RTC_HSE_DIV_22               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 22 */\n#define LL_RCC_RTC_HSE_DIV_23               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 23 */\n#define LL_RCC_RTC_HSE_DIV_24               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)       /*!< HSE clock divided by 24 */\n#define LL_RCC_RTC_HSE_DIV_25               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 25 */\n#define LL_RCC_RTC_HSE_DIV_26               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 26 */\n#define LL_RCC_RTC_HSE_DIV_27               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 27 */\n#define LL_RCC_RTC_HSE_DIV_28               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 28 */\n#define LL_RCC_RTC_HSE_DIV_29               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 29 */\n#define LL_RCC_RTC_HSE_DIV_30               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 30 */\n#define LL_RCC_RTC_HSE_DIV_31               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 31 */\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency\n  * @{\n  */\n#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */\n#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n#if defined(FMPI2C1)\n/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE  Peripheral FMPI2C clock source selection\n  * @{\n  */\n#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1        0x00000000U               /*!< PCLK1 clock used as FMPI2C1 clock source */\n#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK       RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */\n#define LL_RCC_FMPI2C1_CLKSOURCE_HSI          RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */\n/**\n  * @}\n  */\n#endif /* FMPI2C1 */\n\n#if defined(LPTIM1)\n/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection\n  * @{\n  */\n#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       0x00000000U                 /*!< PCLK1 clock used as LPTIM1 clock */\n#define LL_RCC_LPTIM1_CLKSOURCE_HSI         RCC_DCKCFGR2_LPTIM1SEL_0    /*!< LSI oscillator clock used as LPTIM1 clock */\n#define LL_RCC_LPTIM1_CLKSOURCE_LSI         RCC_DCKCFGR2_LPTIM1SEL_1    /*!< HSI oscillator clock used as LPTIM1 clock */\n#define LL_RCC_LPTIM1_CLKSOURCE_LSE         (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)      /*!< LSE oscillator clock used as LPTIM1 clock */\n/**\n  * @}\n  */\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection\n  * @{\n  */\n#if defined(RCC_DCKCFGR_SAI1SRC)\n#define LL_RCC_SAI1_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16))   /*!< PLLI2S clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16))   /*!< PLL clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16))     /*!< External pin clock used as SAI1 clock source */\n#endif /* RCC_DCKCFGR_SAI1SRC */\n#if defined(RCC_DCKCFGR_SAI2SRC)\n#define LL_RCC_SAI2_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16))   /*!< PLLI2S clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16))   /*!< PLL clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16))     /*!< PLL Main clock used as SAI2 clock source */\n#endif /* RCC_DCKCFGR_SAI2SRC */\n#if defined(RCC_DCKCFGR_SAI1ASRC)\n#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)\n#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16))   /*!< PLL Main clock used as SAI1 block A clock source */\n#else\n#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */\n#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */\n#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */\n#endif /* RCC_DCKCFGR_SAI1ASRC */\n#if defined(RCC_DCKCFGR_SAI1BSRC)\n#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)\n#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16))   /*!< PLL Main clock used as SAI1 block B clock source */\n#else\n#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */\n#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */\n#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */\n#endif /* RCC_DCKCFGR_SAI1BSRC */\n/**\n  * @}\n  */\n#endif /* SAI1 */\n\n#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)\n/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE  Peripheral SDIO clock source selection\n  * @{\n  */\n#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK       0x00000000U                 /*!< PLL 48M domain clock used as SDIO clock */\n#if defined(RCC_DCKCFGR_SDIOSEL)\n#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR_SDIOSEL         /*!< System clock clock used as SDIO clock */\n#else\n#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR2_SDIOSEL        /*!< System clock clock used as SDIO clock */\n#endif /* RCC_DCKCFGR_SDIOSEL */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */\n\n#if defined(DSI)\n/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection\n  * @{\n  */\n#define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U                       /*!< DSI-PHY clock used as DSI byte lane clock source */\n#define LL_RCC_DSI_CLKSOURCE_PLL          RCC_DCKCFGR_DSISEL                /*!< PLL clock used as DSI byte lane clock source */\n/**\n  * @}\n  */\n#endif /* DSI */\n\n#if defined(CEC)\n/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection\n  * @{\n  */\n#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488    0x00000000U                /*!< HSI oscillator clock divided by 488 used as CEC clock */\n#define LL_RCC_CEC_CLKSOURCE_LSE           RCC_DCKCFGR2_CECSEL        /*!< LSE oscillator clock used as CEC clock */\n/**\n  * @}\n  */\n#endif /* CEC */\n\n/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE  Peripheral I2S clock source selection\n  * @{\n  */\n#if defined(RCC_CFGR_I2SSRC)\n#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     0x00000000U                /*!< I2S oscillator clock used as I2S1 clock */\n#define LL_RCC_I2S1_CLKSOURCE_PIN        RCC_CFGR_I2SSRC            /*!< External pin clock used as I2S1 clock */\n#endif /* RCC_CFGR_I2SSRC */\n#if defined(RCC_DCKCFGR_I2SSRC)\n#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U)                    /*!< PLL clock used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16))   /*!< External pin used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16))   /*!< PLL Main clock used as I2S1 clock source */\n#endif /* RCC_DCKCFGR_I2SSRC */\n#if defined(RCC_DCKCFGR_I2S1SRC)\n#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */\n#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16))   /*!< PLL Main clock used as I2S1 clock source */\n#endif /* RCC_DCKCFGR_I2S1SRC */\n#if defined(RCC_DCKCFGR_I2S2SRC)\n#define LL_RCC_I2S2_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S2 clock source */\n#define LL_RCC_I2S2_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */\n#define LL_RCC_I2S2_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */\n#define LL_RCC_I2S2_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16))   /*!< PLL Main clock used as I2S2 clock source */\n#endif /* RCC_DCKCFGR_I2S2SRC */\n/**\n  * @}\n  */\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE  Peripheral 48Mhz domain clock source selection\n  * @{\n  */\n#if defined(RCC_DCKCFGR_CK48MSEL)\n#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */\n#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR_CK48MSEL       /*!< PLLSAI oscillator clock used as 48Mhz domain clock */\n#endif /* RCC_DCKCFGR_CK48MSEL */\n#if defined(RCC_DCKCFGR2_CK48MSEL)\n#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR2_CK48MSEL      /*!< PLLSAI oscillator clock used as 48Mhz domain clock */\n#endif /* RCC_PLLSAI_SUPPORT */\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n#define LL_RCC_CK48M_CLKSOURCE_PLLI2S      RCC_DCKCFGR2_CK48MSEL      /*!< PLLI2S oscillator clock used as 48Mhz domain clock */\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n#endif /* RCC_DCKCFGR2_CK48MSEL */\n/**\n  * @}\n  */\n\n#if defined(RNG)\n/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection\n  * @{\n  */\n#define LL_RCC_RNG_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as RNG clock source */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_RNG_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as RNG clock source */\n#endif /* RCC_PLLSAI_SUPPORT */\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n#define LL_RCC_RNG_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as RNG clock source */\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n/**\n  * @}\n  */\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection\n  * @{\n  */\n#define LL_RCC_USB_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as USB clock source */\n#if defined(RCC_PLLSAI_SUPPORT)\n#define LL_RCC_USB_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as USB clock source */\n#endif /* RCC_PLLSAI_SUPPORT */\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n#define LL_RCC_USB_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as USB clock source */\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n/**\n  * @}\n  */\n#endif /* USB_OTG_FS || USB_OTG_HS */\n\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)\n/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM Audio clock source selection\n  * @{\n  */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM1 Audio clock source */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */\n#if defined(DFSDM2_Channel0)\n#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM2 Audio clock source */\n#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */\n#endif /* DFSDM2_Channel0 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM clock source selection\n  * @{\n  */\n#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM1 clock */\n#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM1 clock */\n#if defined(DFSDM2_Channel0)\n#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM2 clock */\n#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM2 clock */\n#endif /* DFSDM2_Channel0 */\n/**\n  * @}\n  */\n#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */\n\n#if defined(FMPI2C1)\n/** @defgroup RCC_LL_EC_FMPI2C1  Peripheral FMPI2C get clock source\n  * @{\n  */\n#define LL_RCC_FMPI2C1_CLKSOURCE              RCC_DCKCFGR2_FMPI2C1SEL  /*!< FMPI2C1 Clock source selection */\n/**\n  * @}\n  */\n#endif /* FMPI2C1 */\n\n#if defined(SPDIFRX)\n/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE  Peripheral SPDIFRX clock source selection\n  * @{\n  */\n#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL          0x00000000U             /*!< PLL clock used as SPDIFRX clock source */\n#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S       RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */\n/**\n  * @}\n  */\n#endif /* SPDIFRX */\n\n#if defined(LPTIM1)\n/** @defgroup RCC_LL_EC_LPTIM1  Peripheral LPTIM get clock source\n  * @{\n  */\n#define LL_RCC_LPTIM1_CLKSOURCE            RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */\n/**\n  * @}\n  */\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_SAI1ASRC)\n#define LL_RCC_SAI1_A_CLKSOURCE            RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */\n#endif /* RCC_DCKCFGR_SAI1ASRC */\n#if defined(RCC_DCKCFGR_SAI1BSRC)\n#define LL_RCC_SAI1_B_CLKSOURCE            RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */\n#endif /* RCC_DCKCFGR_SAI1BSRC */\n#if defined(RCC_DCKCFGR_SAI1SRC)\n#define LL_RCC_SAI1_CLKSOURCE              RCC_DCKCFGR_SAI1SRC  /*!< SAI1 Clock source selection */\n#endif /* RCC_DCKCFGR_SAI1SRC */\n#if defined(RCC_DCKCFGR_SAI2SRC)\n#define LL_RCC_SAI2_CLKSOURCE              RCC_DCKCFGR_SAI2SRC  /*!< SAI2 Clock source selection */\n#endif /* RCC_DCKCFGR_SAI2SRC */\n/**\n  * @}\n  */\n#endif /* SAI1 */\n\n#if defined(SDIO)\n/** @defgroup RCC_LL_EC_SDIOx  Peripheral SDIO get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_SDIOSEL)\n#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR_SDIOSEL   /*!< SDIO Clock source selection */\n#elif defined(RCC_DCKCFGR2_SDIOSEL)\n#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR2_SDIOSEL  /*!< SDIO Clock source selection */\n#else\n#define LL_RCC_SDIO_CLKSOURCE            RCC_PLLCFGR_PLLQ      /*!< SDIO Clock source selection */\n#endif\n/**\n  * @}\n  */\n#endif /* SDIO */\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n/** @defgroup RCC_LL_EC_CK48M  Peripheral CK48M get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_CK48MSEL)\n#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR_CK48MSEL  /*!< CK48M Domain clock source selection */\n#endif /* RCC_DCKCFGR_CK48MSEL */\n#if defined(RCC_DCKCFGR2_CK48MSEL)\n#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */\n#endif /* RCC_DCKCFGR_CK48MSEL */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n#if defined(RNG)\n/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n#define LL_RCC_RNG_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */\n#else\n#define LL_RCC_RNG_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< RNG Clock source selection */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n/**\n  * @}\n  */\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source\n  * @{\n  */\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n#define LL_RCC_USB_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */\n#else\n#define LL_RCC_USB_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< USB Clock source selection */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n/**\n  * @}\n  */\n#endif /* USB_OTG_FS || USB_OTG_HS */\n\n#if defined(CEC)\n/** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source\n  * @{\n  */\n#define LL_RCC_CEC_CLKSOURCE               RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */\n/**\n  * @}\n  */\n#endif /* CEC */\n\n/** @defgroup RCC_LL_EC_I2S1  Peripheral I2S get clock source\n  * @{\n  */\n#if defined(RCC_CFGR_I2SSRC)\n#define LL_RCC_I2S1_CLKSOURCE              RCC_CFGR_I2SSRC     /*!< I2S1 Clock source selection */\n#endif /* RCC_CFGR_I2SSRC */\n#if defined(RCC_DCKCFGR_I2SSRC)\n#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2SSRC  /*!< I2S1 Clock source selection */\n#endif /* RCC_DCKCFGR_I2SSRC */\n#if defined(RCC_DCKCFGR_I2S1SRC)\n#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */\n#endif /* RCC_DCKCFGR_I2S1SRC */\n#if defined(RCC_DCKCFGR_I2S2SRC)\n#define LL_RCC_I2S2_CLKSOURCE              RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */\n#endif /* RCC_DCKCFGR_I2S2SRC */\n/**\n  * @}\n  */\n\n#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)\n/** @defgroup RCC_LL_EC_DFSDM_AUDIO  Peripheral DFSDM Audio get clock source\n  * @{\n  */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */\n#if defined(DFSDM2_Channel0)\n#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */\n#endif /* DFSDM2_Channel0 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source\n  * @{\n  */\n#define LL_RCC_DFSDM1_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */\n#if defined(DFSDM2_Channel0)\n#define LL_RCC_DFSDM2_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */\n#endif /* DFSDM2_Channel0 */\n/**\n  * @}\n  */\n#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */\n\n#if defined(SPDIFRX)\n/** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source\n  * @{\n  */\n#define LL_RCC_SPDIFRX1_CLKSOURCE          RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */\n/**\n  * @}\n  */\n#endif /* SPDIFRX */\n\n#if defined(DSI)\n/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source\n  * @{\n  */\n#define LL_RCC_DSI_CLKSOURCE               RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */\n/**\n  * @}\n  */\n#endif /* DSI */\n\n#if defined(LTDC)\n/** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source\n  * @{\n  */\n#define LL_RCC_LTDC_CLKSOURCE              RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */\n/**\n  * @}\n  */\n#endif /* LTDC */\n\n\n/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection\n  * @{\n  */\n#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */\n/**\n  * @}\n  */\n\n#if defined(RCC_DCKCFGR_TIMPRE)\n/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection\n  * @{\n  */\n#define LL_RCC_TIM_PRESCALER_TWICE          0x00000000U                  /*!< Timers clock to twice PCLK */\n#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     RCC_DCKCFGR_TIMPRE          /*!< Timers clock to four time PCLK */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_TIMPRE */\n\n/** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLI2S and PLLSAI entry clock source\n  * @{\n  */\n#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */\n#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n#define LL_RCC_PLLI2SSOURCE_PIN            (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U)  /*!< I2S External pin input clock selected as PLLI2S entry clock source */\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLI2S and PLLSAI division factor\n  * @{\n  */\n#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */\n#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */\n#define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */\n#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */\n#define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */\n#define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */\n#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */\n#define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */\n#define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */\n#define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */\n#define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */\n#define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */\n#define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */\n#define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */\n#define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */\n#define LL_RCC_PLLM_DIV_17                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */\n#define LL_RCC_PLLM_DIV_18                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */\n#define LL_RCC_PLLM_DIV_19                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */\n#define LL_RCC_PLLM_DIV_20                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */\n#define LL_RCC_PLLM_DIV_21                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */\n#define LL_RCC_PLLM_DIV_22                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */\n#define LL_RCC_PLLM_DIV_23                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */\n#define LL_RCC_PLLM_DIV_24                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */\n#define LL_RCC_PLLM_DIV_25                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */\n#define LL_RCC_PLLM_DIV_26                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */\n#define LL_RCC_PLLM_DIV_27                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */\n#define LL_RCC_PLLM_DIV_28                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */\n#define LL_RCC_PLLM_DIV_29                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */\n#define LL_RCC_PLLM_DIV_30                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */\n#define LL_RCC_PLLM_DIV_31                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */\n#define LL_RCC_PLLM_DIV_32                 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */\n#define LL_RCC_PLLM_DIV_33                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */\n#define LL_RCC_PLLM_DIV_34                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */\n#define LL_RCC_PLLM_DIV_35                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */\n#define LL_RCC_PLLM_DIV_36                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */\n#define LL_RCC_PLLM_DIV_37                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */\n#define LL_RCC_PLLM_DIV_38                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */\n#define LL_RCC_PLLM_DIV_39                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */\n#define LL_RCC_PLLM_DIV_40                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */\n#define LL_RCC_PLLM_DIV_41                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */\n#define LL_RCC_PLLM_DIV_42                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */\n#define LL_RCC_PLLM_DIV_43                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */\n#define LL_RCC_PLLM_DIV_44                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */\n#define LL_RCC_PLLM_DIV_45                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */\n#define LL_RCC_PLLM_DIV_46                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */\n#define LL_RCC_PLLM_DIV_47                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */\n#define LL_RCC_PLLM_DIV_48                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */\n#define LL_RCC_PLLM_DIV_49                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */\n#define LL_RCC_PLLM_DIV_50                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */\n#define LL_RCC_PLLM_DIV_51                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */\n#define LL_RCC_PLLM_DIV_52                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */\n#define LL_RCC_PLLM_DIV_53                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */\n#define LL_RCC_PLLM_DIV_54                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */\n#define LL_RCC_PLLM_DIV_55                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */\n#define LL_RCC_PLLM_DIV_56                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */\n#define LL_RCC_PLLM_DIV_57                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */\n#define LL_RCC_PLLM_DIV_58                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */\n#define LL_RCC_PLLM_DIV_59                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */\n#define LL_RCC_PLLM_DIV_60                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */\n#define LL_RCC_PLLM_DIV_61                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */\n#define LL_RCC_PLLM_DIV_62                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */\n#define LL_RCC_PLLM_DIV_63                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLCFGR_PLLR)\n/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)\n  * @{\n  */\n#define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */\n#define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 3 */\n#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 4 */\n#define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 5 */\n#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */\n#define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 7 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLCFGR_PLLR */\n\n#if defined(RCC_DCKCFGR_PLLDIVR)\n/** @defgroup RCC_LL_EC_PLLDIVR  PLLDIVR division factor (PLLDIVR)\n  * @{\n  */\n#define LL_RCC_PLLDIVR_DIV_1           (RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 1 */\n#define LL_RCC_PLLDIVR_DIV_2           (RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 2 */\n#define LL_RCC_PLLDIVR_DIV_3           (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 3 */\n#define LL_RCC_PLLDIVR_DIV_4           (RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 4 */\n#define LL_RCC_PLLDIVR_DIV_5           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 5 */\n#define LL_RCC_PLLDIVR_DIV_6           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 6 */\n#define LL_RCC_PLLDIVR_DIV_7           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 7 */\n#define LL_RCC_PLLDIVR_DIV_8           (RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 8 */\n#define LL_RCC_PLLDIVR_DIV_9           (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 9 */\n#define LL_RCC_PLLDIVR_DIV_10          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 10 */\n#define LL_RCC_PLLDIVR_DIV_11          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 11 */\n#define LL_RCC_PLLDIVR_DIV_12          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 12 */\n#define LL_RCC_PLLDIVR_DIV_13          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 13 */\n#define LL_RCC_PLLDIVR_DIV_14          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 14 */\n#define LL_RCC_PLLDIVR_DIV_15          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 15 */\n#define LL_RCC_PLLDIVR_DIV_16          (RCC_DCKCFGR_PLLDIVR_4)             /*!< PLL division factor for PLLDIVR output by 16 */\n#define LL_RCC_PLLDIVR_DIV_17          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 17 */\n#define LL_RCC_PLLDIVR_DIV_18          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 18 */\n#define LL_RCC_PLLDIVR_DIV_19          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 19 */\n#define LL_RCC_PLLDIVR_DIV_20          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 20 */\n#define LL_RCC_PLLDIVR_DIV_21          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 21 */\n#define LL_RCC_PLLDIVR_DIV_22          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 22 */\n#define LL_RCC_PLLDIVR_DIV_23          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 23 */\n#define LL_RCC_PLLDIVR_DIV_24          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 24 */\n#define LL_RCC_PLLDIVR_DIV_25          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 25 */\n#define LL_RCC_PLLDIVR_DIV_26          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 26 */\n#define LL_RCC_PLLDIVR_DIV_27          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 27 */\n#define LL_RCC_PLLDIVR_DIV_28          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 28 */\n#define LL_RCC_PLLDIVR_DIV_29          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 29 */\n#define LL_RCC_PLLDIVR_DIV_30          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 30 */\n#define LL_RCC_PLLDIVR_DIV_31          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 31 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLDIVR */\n\n/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)\n  * @{\n  */\n#define LL_RCC_PLLP_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLP output by 2 */\n#define LL_RCC_PLLP_DIV_4                  RCC_PLLCFGR_PLLP_0     /*!< Main PLL division factor for PLLP output by 4 */\n#define LL_RCC_PLLP_DIV_6                  RCC_PLLCFGR_PLLP_1     /*!< Main PLL division factor for PLLP output by 6 */\n#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)   /*!< Main PLL division factor for PLLP output by 8 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)\n  * @{\n  */\n#define LL_RCC_PLLQ_DIV_2                  RCC_PLLCFGR_PLLQ_1                      /*!< Main PLL division factor for PLLQ output by 2 */\n#define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */\n#define LL_RCC_PLLQ_DIV_4                  RCC_PLLCFGR_PLLQ_2                      /*!< Main PLL division factor for PLLQ output by 4 */\n#define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */\n#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */\n#define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */\n#define LL_RCC_PLLQ_DIV_8                  RCC_PLLCFGR_PLLQ_3                      /*!< Main PLL division factor for PLLQ output by 8 */\n#define LL_RCC_PLLQ_DIV_9                  (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */\n#define LL_RCC_PLLQ_DIV_10                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */\n#define LL_RCC_PLLQ_DIV_11                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */\n#define LL_RCC_PLLQ_DIV_12                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */\n#define LL_RCC_PLLQ_DIV_13                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */\n#define LL_RCC_PLLQ_DIV_14                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */\n#define LL_RCC_PLLQ_DIV_15                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLL_SPRE_SEL  PLL Spread Spectrum Selection\n  * @{\n  */\n#define LL_RCC_SPREAD_SELECT_CENTER        0x00000000U                   /*!< PLL center spread spectrum selection */\n#define LL_RCC_SPREAD_SELECT_DOWN          RCC_SSCGR_SPREADSEL           /*!< PLL down spread spectrum selection */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLI2SM  PLLI2SM division factor (PLLI2SM)\n  * @{\n  */\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n#define LL_RCC_PLLI2SM_DIV_2             (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */\n#define LL_RCC_PLLI2SM_DIV_3             (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */\n#define LL_RCC_PLLI2SM_DIV_4             (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */\n#define LL_RCC_PLLI2SM_DIV_5             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */\n#define LL_RCC_PLLI2SM_DIV_6             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */\n#define LL_RCC_PLLI2SM_DIV_7             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */\n#define LL_RCC_PLLI2SM_DIV_8             (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */\n#define LL_RCC_PLLI2SM_DIV_9             (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */\n#define LL_RCC_PLLI2SM_DIV_10            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */\n#define LL_RCC_PLLI2SM_DIV_11            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */\n#define LL_RCC_PLLI2SM_DIV_12            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */\n#define LL_RCC_PLLI2SM_DIV_13            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */\n#define LL_RCC_PLLI2SM_DIV_14            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */\n#define LL_RCC_PLLI2SM_DIV_15            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */\n#define LL_RCC_PLLI2SM_DIV_16            (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */\n#define LL_RCC_PLLI2SM_DIV_17            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */\n#define LL_RCC_PLLI2SM_DIV_18            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */\n#define LL_RCC_PLLI2SM_DIV_19            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */\n#define LL_RCC_PLLI2SM_DIV_20            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */\n#define LL_RCC_PLLI2SM_DIV_21            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */\n#define LL_RCC_PLLI2SM_DIV_22            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */\n#define LL_RCC_PLLI2SM_DIV_23            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */\n#define LL_RCC_PLLI2SM_DIV_24            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */\n#define LL_RCC_PLLI2SM_DIV_25            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */\n#define LL_RCC_PLLI2SM_DIV_26            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */\n#define LL_RCC_PLLI2SM_DIV_27            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */\n#define LL_RCC_PLLI2SM_DIV_28            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */\n#define LL_RCC_PLLI2SM_DIV_29            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */\n#define LL_RCC_PLLI2SM_DIV_30            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */\n#define LL_RCC_PLLI2SM_DIV_31            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */\n#define LL_RCC_PLLI2SM_DIV_32            (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */\n#define LL_RCC_PLLI2SM_DIV_33            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */\n#define LL_RCC_PLLI2SM_DIV_34            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */\n#define LL_RCC_PLLI2SM_DIV_35            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */\n#define LL_RCC_PLLI2SM_DIV_36            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */\n#define LL_RCC_PLLI2SM_DIV_37            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */\n#define LL_RCC_PLLI2SM_DIV_38            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */\n#define LL_RCC_PLLI2SM_DIV_39            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */\n#define LL_RCC_PLLI2SM_DIV_40            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */\n#define LL_RCC_PLLI2SM_DIV_41            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */\n#define LL_RCC_PLLI2SM_DIV_42            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */\n#define LL_RCC_PLLI2SM_DIV_43            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */\n#define LL_RCC_PLLI2SM_DIV_44            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */\n#define LL_RCC_PLLI2SM_DIV_45            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */\n#define LL_RCC_PLLI2SM_DIV_46            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */\n#define LL_RCC_PLLI2SM_DIV_47            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */\n#define LL_RCC_PLLI2SM_DIV_48            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */\n#define LL_RCC_PLLI2SM_DIV_49            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */\n#define LL_RCC_PLLI2SM_DIV_50            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */\n#define LL_RCC_PLLI2SM_DIV_51            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */\n#define LL_RCC_PLLI2SM_DIV_52            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */\n#define LL_RCC_PLLI2SM_DIV_53            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */\n#define LL_RCC_PLLI2SM_DIV_54            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */\n#define LL_RCC_PLLI2SM_DIV_55            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */\n#define LL_RCC_PLLI2SM_DIV_56            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */\n#define LL_RCC_PLLI2SM_DIV_57            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */\n#define LL_RCC_PLLI2SM_DIV_58            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */\n#define LL_RCC_PLLI2SM_DIV_59            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */\n#define LL_RCC_PLLI2SM_DIV_60            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */\n#define LL_RCC_PLLI2SM_DIV_61            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */\n#define LL_RCC_PLLI2SM_DIV_62            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */\n#define LL_RCC_PLLI2SM_DIV_63            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */\n#else\n#define LL_RCC_PLLI2SM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLI2S division factor for PLLI2SM output by 2 */\n#define LL_RCC_PLLI2SM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLI2S division factor for PLLI2SM output by 3 */\n#define LL_RCC_PLLI2SM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLI2S division factor for PLLI2SM output by 4 */\n#define LL_RCC_PLLI2SM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLI2S division factor for PLLI2SM output by 5 */\n#define LL_RCC_PLLI2SM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLI2S division factor for PLLI2SM output by 6 */\n#define LL_RCC_PLLI2SM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLI2S division factor for PLLI2SM output by 7 */\n#define LL_RCC_PLLI2SM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLI2S division factor for PLLI2SM output by 8 */\n#define LL_RCC_PLLI2SM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLI2S division factor for PLLI2SM output by 9 */\n#define LL_RCC_PLLI2SM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLI2S division factor for PLLI2SM output by 10 */\n#define LL_RCC_PLLI2SM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLI2S division factor for PLLI2SM output by 11 */\n#define LL_RCC_PLLI2SM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLI2S division factor for PLLI2SM output by 12 */\n#define LL_RCC_PLLI2SM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLI2S division factor for PLLI2SM output by 13 */\n#define LL_RCC_PLLI2SM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLI2S division factor for PLLI2SM output by 14 */\n#define LL_RCC_PLLI2SM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLI2S division factor for PLLI2SM output by 15 */\n#define LL_RCC_PLLI2SM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLI2S division factor for PLLI2SM output by 16 */\n#define LL_RCC_PLLI2SM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLI2S division factor for PLLI2SM output by 17 */\n#define LL_RCC_PLLI2SM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLI2S division factor for PLLI2SM output by 18 */\n#define LL_RCC_PLLI2SM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLI2S division factor for PLLI2SM output by 19 */\n#define LL_RCC_PLLI2SM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLI2S division factor for PLLI2SM output by 20 */\n#define LL_RCC_PLLI2SM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLI2S division factor for PLLI2SM output by 21 */\n#define LL_RCC_PLLI2SM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLI2S division factor for PLLI2SM output by 22 */\n#define LL_RCC_PLLI2SM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLI2S division factor for PLLI2SM output by 23 */\n#define LL_RCC_PLLI2SM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLI2S division factor for PLLI2SM output by 24 */\n#define LL_RCC_PLLI2SM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLI2S division factor for PLLI2SM output by 25 */\n#define LL_RCC_PLLI2SM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLI2S division factor for PLLI2SM output by 26 */\n#define LL_RCC_PLLI2SM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLI2S division factor for PLLI2SM output by 27 */\n#define LL_RCC_PLLI2SM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLI2S division factor for PLLI2SM output by 28 */\n#define LL_RCC_PLLI2SM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLI2S division factor for PLLI2SM output by 29 */\n#define LL_RCC_PLLI2SM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLI2S division factor for PLLI2SM output by 30 */\n#define LL_RCC_PLLI2SM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLI2S division factor for PLLI2SM output by 31 */\n#define LL_RCC_PLLI2SM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLI2S division factor for PLLI2SM output by 32 */\n#define LL_RCC_PLLI2SM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLI2S division factor for PLLI2SM output by 33 */\n#define LL_RCC_PLLI2SM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLI2S division factor for PLLI2SM output by 34 */\n#define LL_RCC_PLLI2SM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLI2S division factor for PLLI2SM output by 35 */\n#define LL_RCC_PLLI2SM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLI2S division factor for PLLI2SM output by 36 */\n#define LL_RCC_PLLI2SM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLI2S division factor for PLLI2SM output by 37 */\n#define LL_RCC_PLLI2SM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLI2S division factor for PLLI2SM output by 38 */\n#define LL_RCC_PLLI2SM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLI2S division factor for PLLI2SM output by 39 */\n#define LL_RCC_PLLI2SM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLI2S division factor for PLLI2SM output by 40 */\n#define LL_RCC_PLLI2SM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLI2S division factor for PLLI2SM output by 41 */\n#define LL_RCC_PLLI2SM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLI2S division factor for PLLI2SM output by 42 */\n#define LL_RCC_PLLI2SM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLI2S division factor for PLLI2SM output by 43 */\n#define LL_RCC_PLLI2SM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLI2S division factor for PLLI2SM output by 44 */\n#define LL_RCC_PLLI2SM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLI2S division factor for PLLI2SM output by 45 */\n#define LL_RCC_PLLI2SM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLI2S division factor for PLLI2SM output by 46 */\n#define LL_RCC_PLLI2SM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLI2S division factor for PLLI2SM output by 47 */\n#define LL_RCC_PLLI2SM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLI2S division factor for PLLI2SM output by 48 */\n#define LL_RCC_PLLI2SM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLI2S division factor for PLLI2SM output by 49 */\n#define LL_RCC_PLLI2SM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLI2S division factor for PLLI2SM output by 50 */\n#define LL_RCC_PLLI2SM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLI2S division factor for PLLI2SM output by 51 */\n#define LL_RCC_PLLI2SM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLI2S division factor for PLLI2SM output by 52 */\n#define LL_RCC_PLLI2SM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLI2S division factor for PLLI2SM output by 53 */\n#define LL_RCC_PLLI2SM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLI2S division factor for PLLI2SM output by 54 */\n#define LL_RCC_PLLI2SM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLI2S division factor for PLLI2SM output by 55 */\n#define LL_RCC_PLLI2SM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLI2S division factor for PLLI2SM output by 56 */\n#define LL_RCC_PLLI2SM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLI2S division factor for PLLI2SM output by 57 */\n#define LL_RCC_PLLI2SM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLI2S division factor for PLLI2SM output by 58 */\n#define LL_RCC_PLLI2SM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLI2S division factor for PLLI2SM output by 59 */\n#define LL_RCC_PLLI2SM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLI2S division factor for PLLI2SM output by 60 */\n#define LL_RCC_PLLI2SM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLI2S division factor for PLLI2SM output by 61 */\n#define LL_RCC_PLLI2SM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLI2S division factor for PLLI2SM output by 62 */\n#define LL_RCC_PLLI2SM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLI2S division factor for PLLI2SM output by 63 */\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ)\n/** @defgroup RCC_LL_EC_PLLI2SQ  PLLI2SQ division factor (PLLI2SQ)\n  * @{\n  */\n#define LL_RCC_PLLI2SQ_DIV_2              RCC_PLLI2SCFGR_PLLI2SQ_1        /*!< PLLI2S division factor for PLLI2SQ output by 2 */\n#define LL_RCC_PLLI2SQ_DIV_3              (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 3 */\n#define LL_RCC_PLLI2SQ_DIV_4              RCC_PLLI2SCFGR_PLLI2SQ_2        /*!< PLLI2S division factor for PLLI2SQ output by 4 */\n#define LL_RCC_PLLI2SQ_DIV_5              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 5 */\n#define LL_RCC_PLLI2SQ_DIV_6              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 6 */\n#define LL_RCC_PLLI2SQ_DIV_7              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 7 */\n#define LL_RCC_PLLI2SQ_DIV_8              RCC_PLLI2SCFGR_PLLI2SQ_3        /*!< PLLI2S division factor for PLLI2SQ output by 8 */\n#define LL_RCC_PLLI2SQ_DIV_9              (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 9 */\n#define LL_RCC_PLLI2SQ_DIV_10             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 10 */\n#define LL_RCC_PLLI2SQ_DIV_11             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 11 */\n#define LL_RCC_PLLI2SQ_DIV_12             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)        /*!< PLLI2S division factor for PLLI2SQ output by 12 */\n#define LL_RCC_PLLI2SQ_DIV_13             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 13 */\n#define LL_RCC_PLLI2SQ_DIV_14             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 14 */\n#define LL_RCC_PLLI2SQ_DIV_15             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 15 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ */\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/** @defgroup RCC_LL_EC_PLLI2SDIVQ  PLLI2SDIVQ division factor (PLLI2SDIVQ)\n  * @{\n  */\n#define LL_RCC_PLLI2SDIVQ_DIV_1           0x00000000U                        /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */\n#define LL_RCC_PLLI2SDIVQ_DIV_2           RCC_DCKCFGR_PLLI2SDIVQ_0          /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */\n#define LL_RCC_PLLI2SDIVQ_DIV_3           RCC_DCKCFGR_PLLI2SDIVQ_1          /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */\n#define LL_RCC_PLLI2SDIVQ_DIV_4           (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */\n#define LL_RCC_PLLI2SDIVQ_DIV_5           RCC_DCKCFGR_PLLI2SDIVQ_2          /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */\n#define LL_RCC_PLLI2SDIVQ_DIV_6           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */\n#define LL_RCC_PLLI2SDIVQ_DIV_7           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */\n#define LL_RCC_PLLI2SDIVQ_DIV_8           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */\n#define LL_RCC_PLLI2SDIVQ_DIV_9           RCC_DCKCFGR_PLLI2SDIVQ_3          /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */\n#define LL_RCC_PLLI2SDIVQ_DIV_10          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */\n#define LL_RCC_PLLI2SDIVQ_DIV_11          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */\n#define LL_RCC_PLLI2SDIVQ_DIV_12          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */\n#define LL_RCC_PLLI2SDIVQ_DIV_13          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */\n#define LL_RCC_PLLI2SDIVQ_DIV_14          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */\n#define LL_RCC_PLLI2SDIVQ_DIV_15          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */\n#define LL_RCC_PLLI2SDIVQ_DIV_16          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */\n#define LL_RCC_PLLI2SDIVQ_DIV_17          RCC_DCKCFGR_PLLI2SDIVQ_4          /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */\n#define LL_RCC_PLLI2SDIVQ_DIV_18          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */\n#define LL_RCC_PLLI2SDIVQ_DIV_19          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */\n#define LL_RCC_PLLI2SDIVQ_DIV_20          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */\n#define LL_RCC_PLLI2SDIVQ_DIV_21          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */\n#define LL_RCC_PLLI2SDIVQ_DIV_22          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */\n#define LL_RCC_PLLI2SDIVQ_DIV_23          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */\n#define LL_RCC_PLLI2SDIVQ_DIV_24          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */\n#define LL_RCC_PLLI2SDIVQ_DIV_25          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */\n#define LL_RCC_PLLI2SDIVQ_DIV_26          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */\n#define LL_RCC_PLLI2SDIVQ_DIV_27          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */\n#define LL_RCC_PLLI2SDIVQ_DIV_28          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */\n#define LL_RCC_PLLI2SDIVQ_DIV_29          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */\n#define LL_RCC_PLLI2SDIVQ_DIV_30          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */\n#define LL_RCC_PLLI2SDIVQ_DIV_31          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */\n#define LL_RCC_PLLI2SDIVQ_DIV_32          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVR)\n/** @defgroup RCC_LL_EC_PLLI2SDIVR  PLLI2SDIVR division factor (PLLI2SDIVR)\n  * @{\n  */\n#define LL_RCC_PLLI2SDIVR_DIV_1           (RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */\n#define LL_RCC_PLLI2SDIVR_DIV_2           (RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */\n#define LL_RCC_PLLI2SDIVR_DIV_3           (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */\n#define LL_RCC_PLLI2SDIVR_DIV_4           (RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */\n#define LL_RCC_PLLI2SDIVR_DIV_5           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */\n#define LL_RCC_PLLI2SDIVR_DIV_6           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */\n#define LL_RCC_PLLI2SDIVR_DIV_7           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */\n#define LL_RCC_PLLI2SDIVR_DIV_8           (RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */\n#define LL_RCC_PLLI2SDIVR_DIV_9           (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */\n#define LL_RCC_PLLI2SDIVR_DIV_10          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */\n#define LL_RCC_PLLI2SDIVR_DIV_11          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */\n#define LL_RCC_PLLI2SDIVR_DIV_12          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */\n#define LL_RCC_PLLI2SDIVR_DIV_13          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */\n#define LL_RCC_PLLI2SDIVR_DIV_14          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */\n#define LL_RCC_PLLI2SDIVR_DIV_15          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */\n#define LL_RCC_PLLI2SDIVR_DIV_16          (RCC_DCKCFGR_PLLI2SDIVR_4)             /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */\n#define LL_RCC_PLLI2SDIVR_DIV_17          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */\n#define LL_RCC_PLLI2SDIVR_DIV_18          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */\n#define LL_RCC_PLLI2SDIVR_DIV_19          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */\n#define LL_RCC_PLLI2SDIVR_DIV_20          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */\n#define LL_RCC_PLLI2SDIVR_DIV_21          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */\n#define LL_RCC_PLLI2SDIVR_DIV_22          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */\n#define LL_RCC_PLLI2SDIVR_DIV_23          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */\n#define LL_RCC_PLLI2SDIVR_DIV_24          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */\n#define LL_RCC_PLLI2SDIVR_DIV_25          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */\n#define LL_RCC_PLLI2SDIVR_DIV_26          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */\n#define LL_RCC_PLLI2SDIVR_DIV_27          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */\n#define LL_RCC_PLLI2SDIVR_DIV_28          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */\n#define LL_RCC_PLLI2SDIVR_DIV_29          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */\n#define LL_RCC_PLLI2SDIVR_DIV_30          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */\n#define LL_RCC_PLLI2SDIVR_DIV_31          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLI2SDIVR */\n\n/** @defgroup RCC_LL_EC_PLLI2SR  PLLI2SR division factor (PLLI2SR)\n  * @{\n  */\n#define LL_RCC_PLLI2SR_DIV_2              RCC_PLLI2SCFGR_PLLI2SR_1                                     /*!< PLLI2S division factor for PLLI2SR output by 2 */\n#define LL_RCC_PLLI2SR_DIV_3              (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 3 */\n#define LL_RCC_PLLI2SR_DIV_4              RCC_PLLI2SCFGR_PLLI2SR_2                                     /*!< PLLI2S division factor for PLLI2SR output by 4 */\n#define LL_RCC_PLLI2SR_DIV_5              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 5 */\n#define LL_RCC_PLLI2SR_DIV_6              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)        /*!< PLLI2S division factor for PLLI2SR output by 6 */\n#define LL_RCC_PLLI2SR_DIV_7              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 7 */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SP)\n/** @defgroup RCC_LL_EC_PLLI2SP  PLLI2SP division factor (PLLI2SP)\n  * @{\n  */\n#define LL_RCC_PLLI2SP_DIV_2              0x00000000U            /*!< PLLI2S division factor for PLLI2SP output by 2 */\n#define LL_RCC_PLLI2SP_DIV_4              RCC_PLLI2SCFGR_PLLI2SP_0        /*!< PLLI2S division factor for PLLI2SP output by 4 */\n#define LL_RCC_PLLI2SP_DIV_6              RCC_PLLI2SCFGR_PLLI2SP_1        /*!< PLLI2S division factor for PLLI2SP output by 6 */\n#define LL_RCC_PLLI2SP_DIV_8              (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)        /*!< PLLI2S division factor for PLLI2SP output by 8 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLI2SCFGR_PLLI2SP */\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLSAIM  PLLSAIM division factor (PLLSAIM or PLLM)\n  * @{\n  */\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n#define LL_RCC_PLLSAIM_DIV_2             (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */\n#define LL_RCC_PLLSAIM_DIV_3             (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */\n#define LL_RCC_PLLSAIM_DIV_4             (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */\n#define LL_RCC_PLLSAIM_DIV_5             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */\n#define LL_RCC_PLLSAIM_DIV_6             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */\n#define LL_RCC_PLLSAIM_DIV_7             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */\n#define LL_RCC_PLLSAIM_DIV_8             (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */\n#define LL_RCC_PLLSAIM_DIV_9             (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */\n#define LL_RCC_PLLSAIM_DIV_10            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */\n#define LL_RCC_PLLSAIM_DIV_11            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */\n#define LL_RCC_PLLSAIM_DIV_12            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */\n#define LL_RCC_PLLSAIM_DIV_13            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */\n#define LL_RCC_PLLSAIM_DIV_14            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */\n#define LL_RCC_PLLSAIM_DIV_15            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */\n#define LL_RCC_PLLSAIM_DIV_16            (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */\n#define LL_RCC_PLLSAIM_DIV_17            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */\n#define LL_RCC_PLLSAIM_DIV_18            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */\n#define LL_RCC_PLLSAIM_DIV_19            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */\n#define LL_RCC_PLLSAIM_DIV_20            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */\n#define LL_RCC_PLLSAIM_DIV_21            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */\n#define LL_RCC_PLLSAIM_DIV_22            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */\n#define LL_RCC_PLLSAIM_DIV_23            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */\n#define LL_RCC_PLLSAIM_DIV_24            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */\n#define LL_RCC_PLLSAIM_DIV_25            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */\n#define LL_RCC_PLLSAIM_DIV_26            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */\n#define LL_RCC_PLLSAIM_DIV_27            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */\n#define LL_RCC_PLLSAIM_DIV_28            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */\n#define LL_RCC_PLLSAIM_DIV_29            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */\n#define LL_RCC_PLLSAIM_DIV_30            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */\n#define LL_RCC_PLLSAIM_DIV_31            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */\n#define LL_RCC_PLLSAIM_DIV_32            (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */\n#define LL_RCC_PLLSAIM_DIV_33            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */\n#define LL_RCC_PLLSAIM_DIV_34            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */\n#define LL_RCC_PLLSAIM_DIV_35            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */\n#define LL_RCC_PLLSAIM_DIV_36            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */\n#define LL_RCC_PLLSAIM_DIV_37            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */\n#define LL_RCC_PLLSAIM_DIV_38            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */\n#define LL_RCC_PLLSAIM_DIV_39            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */\n#define LL_RCC_PLLSAIM_DIV_40            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */\n#define LL_RCC_PLLSAIM_DIV_41            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */\n#define LL_RCC_PLLSAIM_DIV_42            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */\n#define LL_RCC_PLLSAIM_DIV_43            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */\n#define LL_RCC_PLLSAIM_DIV_44            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */\n#define LL_RCC_PLLSAIM_DIV_45            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */\n#define LL_RCC_PLLSAIM_DIV_46            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */\n#define LL_RCC_PLLSAIM_DIV_47            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */\n#define LL_RCC_PLLSAIM_DIV_48            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */\n#define LL_RCC_PLLSAIM_DIV_49            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */\n#define LL_RCC_PLLSAIM_DIV_50            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */\n#define LL_RCC_PLLSAIM_DIV_51            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */\n#define LL_RCC_PLLSAIM_DIV_52            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */\n#define LL_RCC_PLLSAIM_DIV_53            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */\n#define LL_RCC_PLLSAIM_DIV_54            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */\n#define LL_RCC_PLLSAIM_DIV_55            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */\n#define LL_RCC_PLLSAIM_DIV_56            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */\n#define LL_RCC_PLLSAIM_DIV_57            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */\n#define LL_RCC_PLLSAIM_DIV_58            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */\n#define LL_RCC_PLLSAIM_DIV_59            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */\n#define LL_RCC_PLLSAIM_DIV_60            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */\n#define LL_RCC_PLLSAIM_DIV_61            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */\n#define LL_RCC_PLLSAIM_DIV_62            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */\n#define LL_RCC_PLLSAIM_DIV_63            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */\n#else\n#define LL_RCC_PLLSAIM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLSAI division factor for PLLSAIM output by 2 */\n#define LL_RCC_PLLSAIM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLSAI division factor for PLLSAIM output by 3 */\n#define LL_RCC_PLLSAIM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLSAI division factor for PLLSAIM output by 4 */\n#define LL_RCC_PLLSAIM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLSAI division factor for PLLSAIM output by 5 */\n#define LL_RCC_PLLSAIM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLSAI division factor for PLLSAIM output by 6 */\n#define LL_RCC_PLLSAIM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLSAI division factor for PLLSAIM output by 7 */\n#define LL_RCC_PLLSAIM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLSAI division factor for PLLSAIM output by 8 */\n#define LL_RCC_PLLSAIM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLSAI division factor for PLLSAIM output by 9 */\n#define LL_RCC_PLLSAIM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLSAI division factor for PLLSAIM output by 10 */\n#define LL_RCC_PLLSAIM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLSAI division factor for PLLSAIM output by 11 */\n#define LL_RCC_PLLSAIM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLSAI division factor for PLLSAIM output by 12 */\n#define LL_RCC_PLLSAIM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLSAI division factor for PLLSAIM output by 13 */\n#define LL_RCC_PLLSAIM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLSAI division factor for PLLSAIM output by 14 */\n#define LL_RCC_PLLSAIM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLSAI division factor for PLLSAIM output by 15 */\n#define LL_RCC_PLLSAIM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLSAI division factor for PLLSAIM output by 16 */\n#define LL_RCC_PLLSAIM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLSAI division factor for PLLSAIM output by 17 */\n#define LL_RCC_PLLSAIM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLSAI division factor for PLLSAIM output by 18 */\n#define LL_RCC_PLLSAIM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLSAI division factor for PLLSAIM output by 19 */\n#define LL_RCC_PLLSAIM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLSAI division factor for PLLSAIM output by 20 */\n#define LL_RCC_PLLSAIM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLSAI division factor for PLLSAIM output by 21 */\n#define LL_RCC_PLLSAIM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLSAI division factor for PLLSAIM output by 22 */\n#define LL_RCC_PLLSAIM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLSAI division factor for PLLSAIM output by 23 */\n#define LL_RCC_PLLSAIM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLSAI division factor for PLLSAIM output by 24 */\n#define LL_RCC_PLLSAIM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLSAI division factor for PLLSAIM output by 25 */\n#define LL_RCC_PLLSAIM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLSAI division factor for PLLSAIM output by 26 */\n#define LL_RCC_PLLSAIM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLSAI division factor for PLLSAIM output by 27 */\n#define LL_RCC_PLLSAIM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLSAI division factor for PLLSAIM output by 28 */\n#define LL_RCC_PLLSAIM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLSAI division factor for PLLSAIM output by 29 */\n#define LL_RCC_PLLSAIM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLSAI division factor for PLLSAIM output by 30 */\n#define LL_RCC_PLLSAIM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLSAI division factor for PLLSAIM output by 31 */\n#define LL_RCC_PLLSAIM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLSAI division factor for PLLSAIM output by 32 */\n#define LL_RCC_PLLSAIM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLSAI division factor for PLLSAIM output by 33 */\n#define LL_RCC_PLLSAIM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLSAI division factor for PLLSAIM output by 34 */\n#define LL_RCC_PLLSAIM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLSAI division factor for PLLSAIM output by 35 */\n#define LL_RCC_PLLSAIM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLSAI division factor for PLLSAIM output by 36 */\n#define LL_RCC_PLLSAIM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLSAI division factor for PLLSAIM output by 37 */\n#define LL_RCC_PLLSAIM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLSAI division factor for PLLSAIM output by 38 */\n#define LL_RCC_PLLSAIM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLSAI division factor for PLLSAIM output by 39 */\n#define LL_RCC_PLLSAIM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLSAI division factor for PLLSAIM output by 40 */\n#define LL_RCC_PLLSAIM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLSAI division factor for PLLSAIM output by 41 */\n#define LL_RCC_PLLSAIM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLSAI division factor for PLLSAIM output by 42 */\n#define LL_RCC_PLLSAIM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLSAI division factor for PLLSAIM output by 43 */\n#define LL_RCC_PLLSAIM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLSAI division factor for PLLSAIM output by 44 */\n#define LL_RCC_PLLSAIM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLSAI division factor for PLLSAIM output by 45 */\n#define LL_RCC_PLLSAIM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLSAI division factor for PLLSAIM output by 46 */\n#define LL_RCC_PLLSAIM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLSAI division factor for PLLSAIM output by 47 */\n#define LL_RCC_PLLSAIM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLSAI division factor for PLLSAIM output by 48 */\n#define LL_RCC_PLLSAIM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLSAI division factor for PLLSAIM output by 49 */\n#define LL_RCC_PLLSAIM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLSAI division factor for PLLSAIM output by 50 */\n#define LL_RCC_PLLSAIM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLSAI division factor for PLLSAIM output by 51 */\n#define LL_RCC_PLLSAIM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLSAI division factor for PLLSAIM output by 52 */\n#define LL_RCC_PLLSAIM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLSAI division factor for PLLSAIM output by 53 */\n#define LL_RCC_PLLSAIM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLSAI division factor for PLLSAIM output by 54 */\n#define LL_RCC_PLLSAIM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLSAI division factor for PLLSAIM output by 55 */\n#define LL_RCC_PLLSAIM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLSAI division factor for PLLSAIM output by 56 */\n#define LL_RCC_PLLSAIM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLSAI division factor for PLLSAIM output by 57 */\n#define LL_RCC_PLLSAIM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLSAI division factor for PLLSAIM output by 58 */\n#define LL_RCC_PLLSAIM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLSAI division factor for PLLSAIM output by 59 */\n#define LL_RCC_PLLSAIM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLSAI division factor for PLLSAIM output by 60 */\n#define LL_RCC_PLLSAIM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLSAI division factor for PLLSAIM output by 61 */\n#define LL_RCC_PLLSAIM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLSAI division factor for PLLSAIM output by 62 */\n#define LL_RCC_PLLSAIM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLSAI division factor for PLLSAIM output by 63 */\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLSAIQ  PLLSAIQ division factor (PLLSAIQ)\n  * @{\n  */\n#define LL_RCC_PLLSAIQ_DIV_2              RCC_PLLSAICFGR_PLLSAIQ_1        /*!< PLLSAI division factor for PLLSAIQ output by 2 */\n#define LL_RCC_PLLSAIQ_DIV_3              (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 3 */\n#define LL_RCC_PLLSAIQ_DIV_4              RCC_PLLSAICFGR_PLLSAIQ_2        /*!< PLLSAI division factor for PLLSAIQ output by 4 */\n#define LL_RCC_PLLSAIQ_DIV_5              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 5 */\n#define LL_RCC_PLLSAIQ_DIV_6              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 6 */\n#define LL_RCC_PLLSAIQ_DIV_7              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 7 */\n#define LL_RCC_PLLSAIQ_DIV_8              RCC_PLLSAICFGR_PLLSAIQ_3        /*!< PLLSAI division factor for PLLSAIQ output by 8 */\n#define LL_RCC_PLLSAIQ_DIV_9              (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 9 */\n#define LL_RCC_PLLSAIQ_DIV_10             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 10 */\n#define LL_RCC_PLLSAIQ_DIV_11             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 11 */\n#define LL_RCC_PLLSAIQ_DIV_12             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)        /*!< PLLSAI division factor for PLLSAIQ output by 12 */\n#define LL_RCC_PLLSAIQ_DIV_13             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 13 */\n#define LL_RCC_PLLSAIQ_DIV_14             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 14 */\n#define LL_RCC_PLLSAIQ_DIV_15             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 15 */\n/**\n  * @}\n  */\n\n#if defined(RCC_DCKCFGR_PLLSAIDIVQ)\n/** @defgroup RCC_LL_EC_PLLSAIDIVQ  PLLSAIDIVQ division factor (PLLSAIDIVQ)\n  * @{\n  */\n#define LL_RCC_PLLSAIDIVQ_DIV_1           0x00000000U               /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */\n#define LL_RCC_PLLSAIDIVQ_DIV_2           RCC_DCKCFGR_PLLSAIDIVQ_0          /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */\n#define LL_RCC_PLLSAIDIVQ_DIV_3           RCC_DCKCFGR_PLLSAIDIVQ_1          /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */\n#define LL_RCC_PLLSAIDIVQ_DIV_4           (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */\n#define LL_RCC_PLLSAIDIVQ_DIV_5           RCC_DCKCFGR_PLLSAIDIVQ_2          /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */\n#define LL_RCC_PLLSAIDIVQ_DIV_6           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */\n#define LL_RCC_PLLSAIDIVQ_DIV_7           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */\n#define LL_RCC_PLLSAIDIVQ_DIV_8           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */\n#define LL_RCC_PLLSAIDIVQ_DIV_9           RCC_DCKCFGR_PLLSAIDIVQ_3          /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */\n#define LL_RCC_PLLSAIDIVQ_DIV_10          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */\n#define LL_RCC_PLLSAIDIVQ_DIV_11          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */\n#define LL_RCC_PLLSAIDIVQ_DIV_12          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */\n#define LL_RCC_PLLSAIDIVQ_DIV_13          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */\n#define LL_RCC_PLLSAIDIVQ_DIV_14          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */\n#define LL_RCC_PLLSAIDIVQ_DIV_15          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */\n#define LL_RCC_PLLSAIDIVQ_DIV_16          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */\n#define LL_RCC_PLLSAIDIVQ_DIV_17          RCC_DCKCFGR_PLLSAIDIVQ_4         /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */\n#define LL_RCC_PLLSAIDIVQ_DIV_18          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */\n#define LL_RCC_PLLSAIDIVQ_DIV_19          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */\n#define LL_RCC_PLLSAIDIVQ_DIV_20          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */\n#define LL_RCC_PLLSAIDIVQ_DIV_21          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */\n#define LL_RCC_PLLSAIDIVQ_DIV_22          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */\n#define LL_RCC_PLLSAIDIVQ_DIV_23          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */\n#define LL_RCC_PLLSAIDIVQ_DIV_24          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */\n#define LL_RCC_PLLSAIDIVQ_DIV_25          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */\n#define LL_RCC_PLLSAIDIVQ_DIV_26          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */\n#define LL_RCC_PLLSAIDIVQ_DIV_27          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */\n#define LL_RCC_PLLSAIDIVQ_DIV_28          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */\n#define LL_RCC_PLLSAIDIVQ_DIV_29          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */\n#define LL_RCC_PLLSAIDIVQ_DIV_30          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */\n#define LL_RCC_PLLSAIDIVQ_DIV_31          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */\n#define LL_RCC_PLLSAIDIVQ_DIV_32          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLSAIDIVQ */\n\n#if defined(RCC_PLLSAICFGR_PLLSAIR)\n/** @defgroup RCC_LL_EC_PLLSAIR  PLLSAIR division factor (PLLSAIR)\n  * @{\n  */\n#define LL_RCC_PLLSAIR_DIV_2              RCC_PLLSAICFGR_PLLSAIR_1                                     /*!< PLLSAI division factor for PLLSAIR output by 2 */\n#define LL_RCC_PLLSAIR_DIV_3              (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 3 */\n#define LL_RCC_PLLSAIR_DIV_4              RCC_PLLSAICFGR_PLLSAIR_2                                     /*!< PLLSAI division factor for PLLSAIR output by 4 */\n#define LL_RCC_PLLSAIR_DIV_5              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 5 */\n#define LL_RCC_PLLSAIR_DIV_6              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)        /*!< PLLSAI division factor for PLLSAIR output by 6 */\n#define LL_RCC_PLLSAIR_DIV_7              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 7 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAICFGR_PLLSAIR */\n\n#if defined(RCC_DCKCFGR_PLLSAIDIVR)\n/** @defgroup RCC_LL_EC_PLLSAIDIVR  PLLSAIDIVR division factor (PLLSAIDIVR)\n  * @{\n  */\n#define LL_RCC_PLLSAIDIVR_DIV_2           0x00000000U             /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */\n#define LL_RCC_PLLSAIDIVR_DIV_4           RCC_DCKCFGR_PLLSAIDIVR_0        /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */\n#define LL_RCC_PLLSAIDIVR_DIV_8           RCC_DCKCFGR_PLLSAIDIVR_1        /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */\n#define LL_RCC_PLLSAIDIVR_DIV_16          (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0)        /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_PLLSAIDIVR */\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/** @defgroup RCC_LL_EC_PLLSAIP  PLLSAIP division factor (PLLSAIP)\n  * @{\n  */\n#define LL_RCC_PLLSAIP_DIV_2              0x00000000U               /*!< PLLSAI division factor for PLLSAIP output by 2 */\n#define LL_RCC_PLLSAIP_DIV_4              RCC_PLLSAICFGR_PLLSAIP_0        /*!< PLLSAI division factor for PLLSAIP output by 4 */\n#define LL_RCC_PLLSAIP_DIV_6              RCC_PLLSAICFGR_PLLSAIP_1        /*!< PLLSAI division factor for PLLSAIP output by 6 */\n#define LL_RCC_PLLSAIP_DIV_8              (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)        /*!< PLLSAI division factor for PLLSAIP output by 8 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n#endif /* RCC_PLLSAI_SUPPORT */\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros\n  * @{\n  */\n\n/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in RCC register\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in RCC register\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies\n  * @{\n  */\n\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency on system domain\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLP__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))\n\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLRCLK frequency on system domain\n  * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_3\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_5\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_7\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  *         @arg @ref LL_RCC_PLLQ_DIV_9\n  *         @arg @ref LL_RCC_PLLQ_DIV_10\n  *         @arg @ref LL_RCC_PLLQ_DIV_11\n  *         @arg @ref LL_RCC_PLLQ_DIV_12\n  *         @arg @ref LL_RCC_PLLQ_DIV_13\n  *         @arg @ref LL_RCC_PLLQ_DIV_14\n  *         @arg @ref LL_RCC_PLLQ_DIV_15\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))\n\n#if defined(DSI)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on DSI\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n#endif /* DSI */\n\n#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on I2S\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on SPDIFRX\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n#endif /* SPDIFRX */\n\n#if defined(RCC_PLLCFGR_PLLR)\n#if defined(SAI1)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  __PLLN__ Between 50 and 432\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @param  __PLLDIVR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval PLL clock frequency (in Hz)\n  */\n#if defined(RCC_DCKCFGR_PLLDIVR)\n#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))\n#else\n#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \\\n                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))\n#endif /* RCC_DCKCFGR_PLLDIVR */\n#endif /* SAI1 */\n#endif /* RCC_PLLCFGR_PLLR */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),\n  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  __PLLSAIN__ Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLSAIQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15\n  * @param  __PLLSAIDIVQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32\n  * @retval PLLSAI clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \\\n                   (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/**\n  * @brief  Helper macro to calculate the PLLSAI frequency used on 48Mhz domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),\n  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  __PLLSAIN__ Between 50 and 432\n  * @param  __PLLSAIP__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_8\n  * @retval PLLSAI clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \\\n                   ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n\n#if defined(LTDC)\n/**\n  * @brief  Helper macro to calculate the PLLSAI frequency used for LTDC domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),\n  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  __PLLSAIN__ Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLSAIR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_7\n  * @param  __PLLSAIDIVR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16\n  * @retval PLLSAI clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \\\n                   (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))\n#endif /* LTDC */\n#endif /* RCC_PLLSAI_SUPPORT */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)\n/**\n  * @brief  Helper macro to calculate the PLLI2S frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),\n  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  __PLLI2SN__ Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLI2SQ_R__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLI2SDIVQ_R__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval PLLI2S clock frequency (in Hz)\n  */\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))\n#else\n#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))\n\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain\n  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),\n  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  __PLLI2SN__ Between 50 and 432\n  * @param  __PLLI2SP__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_8\n  * @retval PLLI2S clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))\n\n#endif /* SPDIFRX */\n\n/**\n  * @brief  Helper macro to calculate the PLLI2S frequency used for I2S domain\n  * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),\n  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  __PLLI2SN__ Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLI2SR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7\n  * @retval PLLI2S clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/**\n  * @brief  Helper macro to calculate the PLLI2S frequency used for 48Mhz domain\n  * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),\n  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  __PLLI2SN__ Between 50 and 432\n  * @param  __PLLI2SQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15\n  * @retval PLLI2S clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \\\n                   ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))\n\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n#endif /* RCC_PLLI2S_SUPPORT */\n\n/**\n  * @brief  Helper macro to calculate the HCLK frequency\n  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)\n  * @param  __AHBPRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  * @retval HCLK clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])\n\n/**\n  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)\n  * @param  __HCLKFREQ__ HCLK frequency\n  * @param  __APB1PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  * @retval PCLK1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])\n\n/**\n  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)\n  * @param  __HCLKFREQ__ HCLK frequency\n  * @param  __APB2PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  * @retval PCLK2 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions\n  * @{\n  */\n\n/** @defgroup RCC_LL_EF_HSE HSE\n  * @{\n  */\n\n/**\n  * @brief  Enable the Clock Security System.\n  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_CSSON);\n}\n\n/**\n  * @brief  Enable HSE external oscillator (HSE Bypass)\n  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSEBYP);\n}\n\n/**\n  * @brief  Disable HSE external oscillator (HSE Bypass)\n  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\n}\n\n/**\n  * @brief  Enable HSE crystal oscillator (HSE ON)\n  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSEON);\n}\n\n/**\n  * @brief  Disable HSE crystal oscillator (HSE ON)\n  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);\n}\n\n/**\n  * @brief  Check if HSE oscillator Ready\n  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_HSI HSI\n  * @{\n  */\n\n/**\n  * @brief  Enable HSI oscillator\n  * @rmtoll CR           HSION         LL_RCC_HSI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSION);\n}\n\n/**\n  * @brief  Disable HSI oscillator\n  * @rmtoll CR           HSION         LL_RCC_HSI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSION);\n}\n\n/**\n  * @brief  Check if HSI clock is ready\n  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));\n}\n\n/**\n  * @brief  Get HSI Calibration value\n  * @note When HSITRIM is written, HSICAL is updated with the sum of\n  *       HSITRIM and the factory trim value\n  * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration\n  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);\n}\n\n/**\n  * @brief  Set HSI Calibration trimming\n  * @note user-programmable trimming value that is added to the HSICAL\n  * @note Default value is 16, which, when added to the HSICAL value,\n  *       should trim the HSI to 16 MHz +/- 1 %\n  * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming\n  * @param  Value Between Min_Data = 0 and Max_Data = 31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)\n{\n  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);\n}\n\n/**\n  * @brief  Get HSI Calibration trimming\n  * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming\n  * @retval Between Min_Data = 0 and Max_Data = 31\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_LSE LSE\n  * @{\n  */\n\n/**\n  * @brief  Enable  Low Speed External (LSE) crystal.\n  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_Enable(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\n}\n\n/**\n  * @brief  Disable  Low Speed External (LSE) crystal.\n  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_Disable(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);\n}\n\n/**\n  * @brief  Enable external clock source (LSE bypass).\n  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\n}\n\n/**\n  * @brief  Disable external clock source (LSE bypass).\n  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\n}\n\n/**\n  * @brief  Check if LSE oscillator Ready\n  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)\n{\n  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));\n}\n\n#if defined(RCC_BDCR_LSEMOD)\n/**\n  * @brief  Enable LSE high drive mode.\n  * @note LSE high drive mode can be enabled only when the LSE clock is disabled\n  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_EnableHighDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);\n}\n\n/**\n  * @brief  Disable LSE high drive mode.\n  * @note LSE high drive mode can be disabled only when the LSE clock is disabled\n  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_DisableHighDriveMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);\n}\n#endif /* RCC_BDCR_LSEMOD */\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_LSI LSI\n  * @{\n  */\n\n/**\n  * @brief  Enable LSI Oscillator\n  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSI_Enable(void)\n{\n  SET_BIT(RCC->CSR, RCC_CSR_LSION);\n}\n\n/**\n  * @brief  Disable LSI Oscillator\n  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSI_Disable(void)\n{\n  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);\n}\n\n/**\n  * @brief  Check if LSI is Ready\n  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_System System\n  * @{\n  */\n\n/**\n  * @brief  Configure the system clock source\n  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);\n}\n\n/**\n  * @brief  Get the system clock source\n  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));\n}\n\n/**\n  * @brief  Set AHB prescaler\n  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);\n}\n\n/**\n  * @brief  Set APB1 prescaler\n  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);\n}\n\n/**\n  * @brief  Set APB2 prescaler\n  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);\n}\n\n/**\n  * @brief  Get AHB prescaler\n  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));\n}\n\n/**\n  * @brief  Get APB1 prescaler\n  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));\n}\n\n/**\n  * @brief  Get APB2 prescaler\n  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_MCO MCO\n  * @{\n  */\n\n#if defined(RCC_CFGR_MCO1EN)\n/**\n  * @brief  Enable MCO1 output\n  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MCO1_Enable(void)\n{\n  SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);\n}\n\n/**\n  * @brief  Disable MCO1 output\n  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MCO1_Disable(void)\n{\n  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);\n}\n#endif /* RCC_CFGR_MCO1EN */\n\n#if defined(RCC_CFGR_MCO2EN)\n/**\n  * @brief  Enable MCO2 output\n  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MCO2_Enable(void)\n{\n  SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);\n}\n\n/**\n  * @brief  Disable MCO2 output\n  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MCO2_Disable(void)\n{\n  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);\n}\n#endif /* RCC_CFGR_MCO2EN */\n\n/**\n  * @brief  Configure MCOx\n  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\\n\n  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\\n\n  *         CFGR         MCO2          LL_RCC_ConfigMCO\\n\n  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO\n  * @param  MCOxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MCO1SOURCE_HSI\n  *         @arg @ref LL_RCC_MCO1SOURCE_LSE\n  *         @arg @ref LL_RCC_MCO1SOURCE_HSE\n  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK\n  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK\n  *         @arg @ref LL_RCC_MCO2SOURCE_PLLI2S\n  *         @arg @ref LL_RCC_MCO2SOURCE_HSE\n  *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK\n  * @param  MCOxPrescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MCO1_DIV_1\n  *         @arg @ref LL_RCC_MCO1_DIV_2\n  *         @arg @ref LL_RCC_MCO1_DIV_3\n  *         @arg @ref LL_RCC_MCO1_DIV_4\n  *         @arg @ref LL_RCC_MCO1_DIV_5\n  *         @arg @ref LL_RCC_MCO2_DIV_1\n  *         @arg @ref LL_RCC_MCO2_DIV_2\n  *         @arg @ref LL_RCC_MCO2_DIV_3\n  *         @arg @ref LL_RCC_MCO2_DIV_4\n  *         @arg @ref LL_RCC_MCO2_DIV_5\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)\n{\n  MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U),  (MCOxSource << 16U) | (MCOxPrescaler << 16U));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source\n  * @{\n  */\n#if defined(FMPI2C1)\n/**\n  * @brief  Configure FMPI2C clock source\n  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_SetFMPI2CClockSource\n  * @param  FMPI2CxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)\n{\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);\n}\n#endif /* FMPI2C1 */\n\n#if defined(LPTIM1)\n/**\n  * @brief  Configure LPTIMx clock source\n  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_SetLPTIMClockSource\n  * @param  LPTIMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)\n{\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);\n}\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/**\n  * @brief  Configure SAIx clock source\n  * @rmtoll DCKCFGR        SAI1SRC       LL_RCC_SetSAIClockSource\\n\n  *         DCKCFGR        SAI2SRC       LL_RCC_SetSAIClockSource\\n\n  *         DCKCFGR        SAI1ASRC      LL_RCC_SetSAIClockSource\\n\n  *         DCKCFGR        SAI1BSRC      LL_RCC_SetSAIClockSource\n  * @param  SAIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)\n{\n  MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));\n}\n#endif /* SAI1 */\n\n#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)\n/**\n  * @brief  Configure SDIO clock source\n  * @rmtoll DCKCFGR         SDIOSEL      LL_RCC_SetSDIOClockSource\\n\n  *         DCKCFGR2        SDIOSEL      LL_RCC_SetSDIOClockSource\n  * @param  SDIOxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)\n{\n#if defined(RCC_DCKCFGR_SDIOSEL)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);\n#else\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);\n#endif /* RCC_DCKCFGR_SDIOSEL */\n}\n#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n/**\n  * @brief  Configure 48Mhz domain clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetCK48MClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_SetCK48MClockSource\n  * @param  CK48MxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);\n#else\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n\n#if defined(RNG)\n/**\n  * @brief  Configure RNG clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetRNGClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_SetRNGClockSource\n  * @param  RNGxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);\n#else\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/**\n  * @brief  Configure USB clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetUSBClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_SetUSBClockSource\n  * @param  USBxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);\n#else\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n#endif /* USB_OTG_FS || USB_OTG_HS */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n#if defined(CEC)\n/**\n  * @brief  Configure CEC clock source\n  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_SetCECClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);\n}\n#endif /* CEC */\n\n/**\n  * @brief  Configure I2S clock source\n  * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource\\n\n  *         DCKCFGR      I2SSRC        LL_RCC_SetI2SClockSource\\n\n  *         DCKCFGR      I2S1SRC       LL_RCC_SetI2SClockSource\\n\n  *         DCKCFGR      I2S2SRC       LL_RCC_SetI2SClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)\n{\n#if defined(RCC_CFGR_I2SSRC)\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);\n#else\n  MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));\n#endif /* RCC_CFGR_I2SSRC */\n}\n\n#if defined(DSI)\n/**\n  * @brief  Configure DSI clock source\n  * @rmtoll DCKCFGR         DSISEL        LL_RCC_SetDSIClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);\n}\n#endif /* DSI */\n\n#if defined(DFSDM1_Channel0)\n/**\n  * @brief  Configure DFSDM Audio clock source\n  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_SetDFSDMAudioClockSource\\n\n  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_SetDFSDMAudioClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));\n}\n\n/**\n  * @brief  Configure DFSDM Kernel clock source\n  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_SetDFSDMClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);\n}\n#endif /* DFSDM1_Channel0 */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Configure SPDIFRX clock source\n  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_SetSPDIFRXClockSource\n  * @param  SPDIFRXxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)\n{\n  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);\n}\n#endif /* SPDIFRX */\n\n#if defined(FMPI2C1)\n/**\n  * @brief  Get FMPI2C clock source\n  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_GetFMPI2CClockSource\n  * @param  FMPI2Cx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI\n */\n__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));\n}\n#endif /* FMPI2C1 */\n\n#if defined(LPTIM1)\n/**\n  * @brief  Get LPTIMx clock source\n  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n  * @param  LPTIMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));\n}\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/**\n  * @brief  Get SAIx clock source\n  * @rmtoll DCKCFGR         SAI1SEL       LL_RCC_GetSAIClockSource\\n\n  *         DCKCFGR         SAI2SEL       LL_RCC_GetSAIClockSource\\n\n  *         DCKCFGR         SAI1ASRC      LL_RCC_GetSAIClockSource\\n\n  *         DCKCFGR         SAI1BSRC      LL_RCC_GetSAIClockSource\n  * @param  SAIx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);\n}\n#endif /* SAI1 */\n\n#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)\n/**\n  * @brief  Get SDIOx clock source\n  * @rmtoll DCKCFGR        SDIOSEL      LL_RCC_GetSDIOClockSource\\n\n  *         DCKCFGR2       SDIOSEL      LL_RCC_GetSDIOClockSource\n  * @param  SDIOx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)\n{\n#if defined(RCC_DCKCFGR_SDIOSEL)\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));\n#endif /* RCC_DCKCFGR_SDIOSEL */\n}\n#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n/**\n  * @brief  Get 48Mhz domain clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetCK48MClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_GetCK48MClockSource\n  * @param  CK48Mx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n\n#if defined(RNG)\n/**\n  * @brief  Get RNGx clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetRNGClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_GetRNGClockSource\n  * @param  RNGx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/**\n  * @brief  Get USBx clock source\n  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetUSBClockSource\\n\n  *         DCKCFGR2        CK48MSEL      LL_RCC_GetUSBClockSource\n  * @param  USBx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)\n{\n#if defined(RCC_DCKCFGR_CK48MSEL)\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));\n#endif /* RCC_DCKCFGR_CK48MSEL */\n}\n#endif /* USB_OTG_FS || USB_OTG_HS */\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n#if defined(CEC)\n/**\n  * @brief  Get CEC Clock Source\n  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_GetCECClockSource\n  * @param  CECx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));\n}\n#endif /* CEC */\n\n/**\n  * @brief  Get I2S Clock Source\n  * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource\\n\n  *         DCKCFGR      I2SSRC        LL_RCC_GetI2SClockSource\\n\n  *         DCKCFGR      I2S1SRC       LL_RCC_GetI2SClockSource\\n\n  *         DCKCFGR      I2S2SRC       LL_RCC_GetI2SClockSource\n  * @param  I2Sx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE (*)\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)\n{\n#if defined(RCC_CFGR_I2SSRC)\n  return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));\n#else\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);\n#endif /* RCC_CFGR_I2SSRC */\n}\n\n#if defined(DFSDM1_Channel0)\n/**\n  * @brief  Get DFSDM Audio Clock Source\n  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_GetDFSDMAudioClockSource\\n\n  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_GetDFSDMAudioClockSource\n  * @param  DFSDMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);\n}\n\n/**\n  * @brief  Get DFSDM Audio Clock Source\n  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_GetDFSDMClockSource\n  * @param  DFSDMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));\n}\n#endif /* DFSDM1_Channel0 */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Get SPDIFRX clock source\n  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_GetSPDIFRXClockSource\n  * @param  SPDIFRXx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));\n}\n#endif /* SPDIFRX */\n\n#if defined(DSI)\n/**\n  * @brief  Get DSI Clock Source\n  * @rmtoll DCKCFGR         DSISEL        LL_RCC_GetDSIClockSource\n  * @param  DSIx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));\n}\n#endif /* DSI */\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_RTC RTC\n  * @{\n  */\n\n/**\n  * @brief  Set RTC Clock Source\n  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless\n  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is\n  *       set). The BDRST bit can be used to reset them.\n  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);\n}\n\n/**\n  * @brief  Get RTC Clock Source\n  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));\n}\n\n/**\n  * @brief  Enable RTC\n  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableRTC(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);\n}\n\n/**\n  * @brief  Disable RTC\n  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableRTC(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);\n}\n\n/**\n  * @brief  Check if RTC has been enabled or not\n  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)\n{\n  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));\n}\n\n/**\n  * @brief  Force the Backup domain reset\n  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);\n}\n\n/**\n  * @brief  Release the Backup domain reset\n  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);\n}\n\n/**\n  * @brief  Set HSE Prescalers for RTC Clock\n  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_NOCLOCK\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_2\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_3\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_4\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_5\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_6\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_7\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_8\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_9\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_10\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_11\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_12\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_13\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_14\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_15\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_16\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_17\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_18\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_19\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_20\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_21\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_22\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_23\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_24\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_25\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_26\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_27\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_28\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_29\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_30\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);\n}\n\n/**\n  * @brief  Get HSE Prescalers for RTC Clock\n  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_NOCLOCK\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_2\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_3\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_4\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_5\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_6\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_7\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_8\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_9\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_10\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_11\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_12\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_13\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_14\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_15\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_16\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_17\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_18\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_19\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_20\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_21\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_22\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_23\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_24\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_25\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_26\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_27\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_28\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_29\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_30\n  *         @arg @ref LL_RCC_RTC_HSE_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));\n}\n\n/**\n  * @}\n  */\n\n#if defined(RCC_DCKCFGR_TIMPRE)\n/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM\n  * @{\n  */\n\n/**\n  * @brief  Set Timers Clock Prescalers\n  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_SetTIMPrescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE\n  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);\n}\n\n/**\n  * @brief  Get Timers Clock Prescalers\n  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_GetTIMPrescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE\n  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_DCKCFGR_TIMPRE */\n\n/** @defgroup RCC_LL_EF_PLL PLL\n  * @{\n  */\n\n/**\n  * @brief  Enable PLL\n  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLON);\n}\n\n/**\n  * @brief  Disable PLL\n  * @note Cannot be disabled if the PLL clock is used as the system clock\n  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);\n}\n\n/**\n  * @brief  Check if PLL Ready\n  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));\n}\n\n/**\n  * @brief  Configure PLL used for SYSCLK Domain\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLP can be written only when PLL is disabled\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SYS\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLP_R This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  *         @arg @ref LL_RCC_PLLR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLR_DIV_7 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n}\n\n/**\n  * @brief  Configure PLL used for 48Mhz domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLQ can be written only when PLL is disabled\n  * @note This  can be selected for USB, RNG, SDIO\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_3\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_5\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_7\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  *         @arg @ref LL_RCC_PLLQ_DIV_9\n  *         @arg @ref LL_RCC_PLLQ_DIV_10\n  *         @arg @ref LL_RCC_PLLQ_DIV_11\n  *         @arg @ref LL_RCC_PLLQ_DIV_12\n  *         @arg @ref LL_RCC_PLLQ_DIV_13\n  *         @arg @ref LL_RCC_PLLQ_DIV_14\n  *         @arg @ref LL_RCC_PLLQ_DIV_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);\n}\n\n#if defined(DSI)\n/**\n  * @brief  Configure PLL used for DSI clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI are disabled\n  * @note PLLN/PLLR can be written only when PLL is disabled\n  * @note This  can be selected for DSI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_DSI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_DSI\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_DSI\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_DSI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n}\n#endif /* DSI */\n\n#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)\n/**\n  * @brief  Configure PLL used for I2S clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI are disabled\n  * @note PLLN/PLLR can be written only when PLL is disabled\n  * @note This  can be selected for I2S\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_I2S\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n}\n#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Configure PLL used for SPDIFRX clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI are disabled\n  * @note PLLN/PLLR can be written only when PLL is disabled\n  * @note This  can be selected for SPDIFRX\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SPDIFRX\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SPDIFRX\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SPDIFRX\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SPDIFRX\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n}\n#endif /* SPDIFRX */\n\n#if defined(RCC_PLLCFGR_PLLR)\n#if defined(SAI1)\n/**\n  * @brief  Configure PLL used for SAI clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI are disabled\n  * @note PLLN/PLLR can be written only when PLL is disabled\n  * @note This  can be selected for SAI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         DCKCFGR      PLLDIVR       LL_RCC_PLL_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  * @param  PLLDIVR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n#if defined(RCC_DCKCFGR_PLLDIVR)\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)\n#else\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n#endif /* RCC_DCKCFGR_PLLDIVR */\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n#if defined(RCC_DCKCFGR_PLLDIVR)\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);\n#endif /* RCC_DCKCFGR_PLLDIVR */\n}\n#endif /* SAI1 */\n#endif /* RCC_PLLCFGR_PLLR */\n\n/**\n  * @brief  Configure PLL clock source\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource\n  * @param PLLSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);\n}\n\n/**\n  * @brief  Get the oscillator used as PLL clock source.\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));\n}\n\n/**\n  * @brief  Get Main PLL multiplication factor for VCO\n  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN\n  * @retval Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);\n}\n\n/**\n  * @brief  Get Main PLL division factor for PLLP \n  * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));\n}\n\n/**\n  * @brief  Get Main PLL division factor for PLLQ\n  * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)\n  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_3\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_5\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_7\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  *         @arg @ref LL_RCC_PLLQ_DIV_9\n  *         @arg @ref LL_RCC_PLLQ_DIV_10\n  *         @arg @ref LL_RCC_PLLQ_DIV_11\n  *         @arg @ref LL_RCC_PLLQ_DIV_12\n  *         @arg @ref LL_RCC_PLLQ_DIV_13\n  *         @arg @ref LL_RCC_PLLQ_DIV_14\n  *         @arg @ref LL_RCC_PLLQ_DIV_15\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));\n}\n\n#if defined(RCC_PLLCFGR_PLLR)\n/**\n  * @brief  Get Main PLL division factor for PLLR\n  * @note used for PLLCLK (system clock)\n  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_3\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_5\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_7\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));\n}\n#endif /* RCC_PLLCFGR_PLLR */\n\n#if defined(RCC_DCKCFGR_PLLDIVR)\n/**\n  * @brief  Get Main PLL division factor for PLLDIVR\n  * @note used for PLLSAICLK (SAI1 and SAI2 clock)\n  * @rmtoll DCKCFGR      PLLDIVR          LL_RCC_PLL_GetDIVR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_1\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_3\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_5\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_6\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_7\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_9\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_10\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_11\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_12\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_13\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_14\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_15\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_16\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_17\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_18\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_19\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_20\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_21\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_22\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_23\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_24\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_25\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_26\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_27\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_28\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_29\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_30\n  *         @arg @ref LL_RCC_PLLDIVR_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));\n}\n#endif /* RCC_DCKCFGR_PLLDIVR */\n\n/**\n  * @brief  Get Division factor for the main PLL and other PLL\n  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9\n  *         @arg @ref LL_RCC_PLLM_DIV_10\n  *         @arg @ref LL_RCC_PLLM_DIV_11\n  *         @arg @ref LL_RCC_PLLM_DIV_12\n  *         @arg @ref LL_RCC_PLLM_DIV_13\n  *         @arg @ref LL_RCC_PLLM_DIV_14\n  *         @arg @ref LL_RCC_PLLM_DIV_15\n  *         @arg @ref LL_RCC_PLLM_DIV_16\n  *         @arg @ref LL_RCC_PLLM_DIV_17\n  *         @arg @ref LL_RCC_PLLM_DIV_18\n  *         @arg @ref LL_RCC_PLLM_DIV_19\n  *         @arg @ref LL_RCC_PLLM_DIV_20\n  *         @arg @ref LL_RCC_PLLM_DIV_21\n  *         @arg @ref LL_RCC_PLLM_DIV_22\n  *         @arg @ref LL_RCC_PLLM_DIV_23\n  *         @arg @ref LL_RCC_PLLM_DIV_24\n  *         @arg @ref LL_RCC_PLLM_DIV_25\n  *         @arg @ref LL_RCC_PLLM_DIV_26\n  *         @arg @ref LL_RCC_PLLM_DIV_27\n  *         @arg @ref LL_RCC_PLLM_DIV_28\n  *         @arg @ref LL_RCC_PLLM_DIV_29\n  *         @arg @ref LL_RCC_PLLM_DIV_30\n  *         @arg @ref LL_RCC_PLLM_DIV_31\n  *         @arg @ref LL_RCC_PLLM_DIV_32\n  *         @arg @ref LL_RCC_PLLM_DIV_33\n  *         @arg @ref LL_RCC_PLLM_DIV_34\n  *         @arg @ref LL_RCC_PLLM_DIV_35\n  *         @arg @ref LL_RCC_PLLM_DIV_36\n  *         @arg @ref LL_RCC_PLLM_DIV_37\n  *         @arg @ref LL_RCC_PLLM_DIV_38\n  *         @arg @ref LL_RCC_PLLM_DIV_39\n  *         @arg @ref LL_RCC_PLLM_DIV_40\n  *         @arg @ref LL_RCC_PLLM_DIV_41\n  *         @arg @ref LL_RCC_PLLM_DIV_42\n  *         @arg @ref LL_RCC_PLLM_DIV_43\n  *         @arg @ref LL_RCC_PLLM_DIV_44\n  *         @arg @ref LL_RCC_PLLM_DIV_45\n  *         @arg @ref LL_RCC_PLLM_DIV_46\n  *         @arg @ref LL_RCC_PLLM_DIV_47\n  *         @arg @ref LL_RCC_PLLM_DIV_48\n  *         @arg @ref LL_RCC_PLLM_DIV_49\n  *         @arg @ref LL_RCC_PLLM_DIV_50\n  *         @arg @ref LL_RCC_PLLM_DIV_51\n  *         @arg @ref LL_RCC_PLLM_DIV_52\n  *         @arg @ref LL_RCC_PLLM_DIV_53\n  *         @arg @ref LL_RCC_PLLM_DIV_54\n  *         @arg @ref LL_RCC_PLLM_DIV_55\n  *         @arg @ref LL_RCC_PLLM_DIV_56\n  *         @arg @ref LL_RCC_PLLM_DIV_57\n  *         @arg @ref LL_RCC_PLLM_DIV_58\n  *         @arg @ref LL_RCC_PLLM_DIV_59\n  *         @arg @ref LL_RCC_PLLM_DIV_60\n  *         @arg @ref LL_RCC_PLLM_DIV_61\n  *         @arg @ref LL_RCC_PLLM_DIV_62\n  *         @arg @ref LL_RCC_PLLM_DIV_63\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));\n}\n\n/**\n  * @brief  Configure Spread Spectrum used for PLL\n  * @note These bits must be written before enabling PLL\n  * @rmtoll SSCGR        MODPER        LL_RCC_PLL_ConfigSpreadSpectrum\\n\n  *         SSCGR        INCSTEP       LL_RCC_PLL_ConfigSpreadSpectrum\\n\n  *         SSCGR        SPREADSEL     LL_RCC_PLL_ConfigSpreadSpectrum\n  * @param  Mod Between Min_Data=0 and Max_Data=8191\n  * @param  Inc Between Min_Data=0 and Max_Data=32767\n  * @param  Sel This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER\n  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)\n{\n  MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);\n}\n\n/**\n  * @brief  Get Spread Spectrum Modulation Period for PLL\n  * @rmtoll SSCGR         MODPER        LL_RCC_PLL_GetPeriodModulation\n  * @retval Between Min_Data=0 and Max_Data=8191\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)\n{\n  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));\n}\n\n/**\n  * @brief  Get Spread Spectrum Incrementation Step for PLL\n  * @note Must be written before enabling PLL\n  * @rmtoll SSCGR         INCSTEP        LL_RCC_PLL_GetStepIncrementation\n  * @retval Between Min_Data=0 and Max_Data=32767\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)\n{\n  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);\n}\n\n/**\n  * @brief  Get Spread Spectrum Selection for PLL\n  * @note Must be written before enabling PLL\n  * @rmtoll SSCGR         SPREADSEL        LL_RCC_PLL_GetSpreadSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER\n  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)\n{\n  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));\n}\n\n/**\n  * @brief  Enable Spread Spectrum for PLL.\n  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)\n{\n  SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);\n}\n\n/**\n  * @brief  Disable Spread Spectrum for PLL.\n  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)\n{\n  CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);\n}\n\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/** @defgroup RCC_LL_EF_PLLI2S PLLI2S\n  * @{\n  */\n\n/**\n  * @brief  Enable PLLI2S\n  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLI2SON);\n}\n\n/**\n  * @brief  Disable PLLI2S\n  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);\n}\n\n/**\n  * @brief  Check if PLLI2S Ready\n  * @rmtoll CR           PLLI2SRDY    LL_RCC_PLLI2S_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));\n}\n\n#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))\n/**\n  * @brief  Configure PLLI2S used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled\n  * @note This can be selected for SAI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         DCKCFGR      PLLI2SDIVQ    LL_RCC_PLLI2S_ConfigDomain_SAI\\n\n  *         DCKCFGR      PLLI2SDIVR    LL_RCC_PLLI2S_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  PLLN Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLQ_R This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLDIVQ_R This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)\n{\n  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));\n  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);\n#else\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n}\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/**\n  * @brief  Configure PLLI2S used for 48Mhz domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLQ can be written only when PLLI2S is disabled\n  * @note This can be selected for RNG, USB, SDIO\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_48M\\n\n  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)\n{\n  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));\n  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);\n}\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(SPDIFRX)\n/**\n  * @brief Configure PLLI2S used for SPDIFRX domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLP can be written only when PLLI2S is disabled\n  * @note This  can be selected for SPDIFRX\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\\n\n  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\\n\n  *         PLLI2SCFGR   PLLI2SP       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);\n}\n#endif /* SPDIFRX */\n\n/**\n  * @brief  Configure PLLI2S used for I2S1 domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLR can be written only when PLLI2S is disabled\n  * @note This  can be selected for I2S\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_I2S\\n\n  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_I2S\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  * @param  PLLN Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));\n  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);\n}\n\n/**\n  * @brief  Get I2SPLL multiplication factor for VCO\n  * @rmtoll PLLI2SCFGR  PLLI2SN      LL_RCC_PLLI2S_GetN\n  * @retval Between 50/192(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\n}\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ)\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SQ\n  * @rmtoll PLLI2SCFGR  PLLI2SQ      LL_RCC_PLLI2S_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));\n}\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ */\n\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SR\n  * @note used for PLLI2SCLK (I2S clock)\n  * @rmtoll PLLI2SCFGR  PLLI2SR      LL_RCC_PLLI2S_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SR_DIV_7\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));\n}\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SP)\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SP\n  * @note used for PLLSPDIFRXCLK (SPDIFRX clock)\n  * @rmtoll PLLI2SCFGR  PLLI2SP      LL_RCC_PLLI2S_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SP_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));\n}\n#endif /* RCC_PLLI2SCFGR_PLLI2SP */\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SDIVQ\n  * @note used PLLSAICLK selected (SAI clock)\n  * @rmtoll DCKCFGR   PLLI2SDIVQ      LL_RCC_PLLI2S_GetDIVQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));\n}\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVR)\n/**\n  * @brief  Get I2SPLL division factor for PLLI2SDIVR\n  * @note used PLLSAICLK selected (SAI clock)\n  * @rmtoll DCKCFGR   PLLI2SDIVR      LL_RCC_PLLI2S_GetDIVR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));\n}\n#endif /* RCC_DCKCFGR_PLLI2SDIVR */\n\n/**\n  * @brief  Get division factor for PLLI2S input clock\n  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLI2S_GetDivider\\n\n  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_2\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_3\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_4\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_5\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_6\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_7\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_8\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_9\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_10\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_11\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_12\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_13\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_14\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_15\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_16\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_17\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_18\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_19\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_20\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_21\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_22\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_23\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_24\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_25\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_26\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_27\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_28\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_29\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_30\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_31\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_32\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_33\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_34\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_35\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_36\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_37\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_38\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_39\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_40\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_41\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_42\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_43\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_44\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_45\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_46\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_47\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_48\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_49\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_50\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_51\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_52\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_53\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_54\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_55\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_56\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_57\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_58\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_59\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_60\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_61\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_62\n  *         @arg @ref LL_RCC_PLLI2SM_DIV_63\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)\n{\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));\n#else\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n}\n\n/**\n  * @brief  Get the oscillator used as PLL clock source.\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_GetMainSource\\n\n  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_GetMainSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)\n{\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n  register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);\n  register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);\n  register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;\n  return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);\n#else\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/** @defgroup RCC_LL_EF_PLLSAI PLLSAI\n  * @{\n  */\n\n/**\n  * @brief  Enable PLLSAI\n  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLSAION);\n}\n\n/**\n  * @brief  Disable PLLSAI\n  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);\n}\n\n/**\n  * @brief  Check if PLLSAI Ready\n  * @rmtoll CR           PLLSAIRDY    LL_RCC_PLLSAI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));\n}\n\n/**\n  * @brief  Configure PLLSAI used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLQ can be written only when PLLSAI is disabled\n  * @note This can be selected for SAI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         PLLSAICFGR   PLLSAIQ       LL_RCC_PLLSAI_ConfigDomain_SAI\\n\n  *         DCKCFGR      PLLSAIDIVQ    LL_RCC_PLLSAI_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  PLLN Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15\n  * @param  PLLDIVQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);\n}\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/**\n  * @brief Configure PLLSAI used for 48Mhz domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLP can be written only when PLLSAI is disabled\n  * @note This  can be selected for USB, RNG, SDIO\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_48M\\n\n  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_48M\\n\n  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_48M\\n\n  *         PLLSAICFGR   PLLSAIP       LL_RCC_PLLSAI_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  PLLN Between 50 and 432\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);\n}\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n\n#if defined(LTDC)\n/**\n  * @brief  Configure PLLSAI used for LTDC domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLI2S and PLLSAI(*) are disabled\n  * @note PLLN/PLLR can be written only when PLLSAI is disabled\n  * @note This  can be selected for LTDC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_LTDC\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_LTDC\\n\n  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_LTDC\\n\n  *         PLLSAICFGR   PLLSAIR       LL_RCC_PLLSAI_ConfigDomain_LTDC\\n\n  *         DCKCFGR      PLLSAIDIVR    LL_RCC_PLLSAI_ConfigDomain_LTDC\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  * @param  PLLN Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_7\n  * @param  PLLDIVR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);\n  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);\n}\n#endif /* LTDC */\n\n/**\n  * @brief  Get division factor for PLLSAI input clock\n  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLSAI_GetDivider\\n\n  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_32\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_33\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_34\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_35\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_36\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_37\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_38\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_39\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_40\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_41\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_42\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_43\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_44\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_45\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_46\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_47\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_48\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_49\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_50\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_51\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_52\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_53\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_54\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_55\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_56\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_57\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_58\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_59\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_60\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_61\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_62\n  *         @arg @ref LL_RCC_PLLSAIM_DIV_63\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)\n{\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));\n#else\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n}\n\n/**\n  * @brief  Get SAIPLL multiplication factor for VCO\n  * @rmtoll PLLSAICFGR  PLLSAIN      LL_RCC_PLLSAI_GetN\n  * @retval Between 49/50(*) and 432\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\n}\n\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIQ\n  * @rmtoll PLLSAICFGR  PLLSAIQ      LL_RCC_PLLSAI_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));\n}\n\n#if defined(RCC_PLLSAICFGR_PLLSAIR)\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIR\n  * @note used for PLLSAICLK (SAI clock)\n  * @rmtoll PLLSAICFGR  PLLSAIR      LL_RCC_PLLSAI_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIR_DIV_7\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));\n}\n#endif /* RCC_PLLSAICFGR_PLLSAIR */\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIP\n  * @note used for PLL48MCLK (48M domain clock)\n  * @rmtoll PLLSAICFGR  PLLSAIP      LL_RCC_PLLSAI_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIP_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));\n}\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIDIVQ\n  * @note used PLLSAICLK selected (SAI clock)\n  * @rmtoll DCKCFGR   PLLSAIDIVQ      LL_RCC_PLLSAI_GetDIVQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31\n  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));\n}\n\n#if defined(RCC_DCKCFGR_PLLSAIDIVR)\n/**\n  * @brief  Get SAIPLL division factor for PLLSAIDIVR\n  * @note used for LTDC domain clock\n  * @rmtoll DCKCFGR  PLLSAIDIVR      LL_RCC_PLLSAI_GetDIVR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));\n}\n#endif /* RCC_DCKCFGR_PLLSAIDIVR */\n\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management\n  * @{\n  */\n\n/**\n  * @brief  Clear LSI ready interrupt flag\n  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);\n}\n\n/**\n  * @brief  Clear LSE ready interrupt flag\n  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);\n}\n\n/**\n  * @brief  Clear HSI ready interrupt flag\n  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);\n}\n\n/**\n  * @brief  Clear HSE ready interrupt flag\n  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);\n}\n\n/**\n  * @brief  Clear PLL ready interrupt flag\n  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Clear PLLI2S ready interrupt flag\n  * @rmtoll CIR         PLLI2SRDYC   LL_RCC_ClearFlag_PLLI2SRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);\n}\n\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Clear PLLSAI ready interrupt flag\n  * @rmtoll CIR         PLLSAIRDYC   LL_RCC_ClearFlag_PLLSAIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);\n}\n\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @brief  Clear Clock security system interrupt flag\n  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_CSSC);\n}\n\n/**\n  * @brief  Check if LSI ready interrupt occurred or not\n  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));\n}\n\n/**\n  * @brief  Check if LSE ready interrupt occurred or not\n  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));\n}\n\n/**\n  * @brief  Check if HSI ready interrupt occurred or not\n  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));\n}\n\n/**\n  * @brief  Check if HSE ready interrupt occurred or not\n  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));\n}\n\n/**\n  * @brief  Check if PLL ready interrupt occurred or not\n  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Check if PLLI2S ready interrupt occurred or not\n  * @rmtoll CIR         PLLI2SRDYF   LL_RCC_IsActiveFlag_PLLI2SRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));\n}\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Check if PLLSAI ready interrupt occurred or not\n  * @rmtoll CIR         PLLSAIRDYF   LL_RCC_IsActiveFlag_PLLSAIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));\n}\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @brief  Check if Clock security system interrupt occurred or not\n  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));\n}\n\n/**\n  * @brief  Check if RCC flag Independent Watchdog reset is set or not.\n  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Low Power reset is set or not.\n  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Pin reset is set or not.\n  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag POR/PDR reset is set or not.\n  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Software reset is set or not.\n  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Window Watchdog reset is set or not.\n  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));\n}\n\n#if defined(RCC_CSR_BORRSTF)\n/**\n  * @brief  Check if RCC flag BOR reset is set or not.\n  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));\n}\n#endif /* RCC_CSR_BORRSTF */\n\n/**\n  * @brief  Set RMVF bit to clear the reset flags.\n  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearResetFlags(void)\n{\n  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_IT_Management IT Management\n  * @{\n  */\n\n/**\n  * @brief  Enable LSI ready interrupt\n  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);\n}\n\n/**\n  * @brief  Enable LSE ready interrupt\n  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);\n}\n\n/**\n  * @brief  Enable HSI ready interrupt\n  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);\n}\n\n/**\n  * @brief  Enable HSE ready interrupt\n  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);\n}\n\n/**\n  * @brief  Enable PLL ready interrupt\n  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Enable PLLI2S ready interrupt\n  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_EnableIT_PLLI2SRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);\n}\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Enable PLLSAI ready interrupt\n  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_EnableIT_PLLSAIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)\n{\n  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);\n}\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @brief  Disable LSI ready interrupt\n  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);\n}\n\n/**\n  * @brief  Disable LSE ready interrupt\n  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);\n}\n\n/**\n  * @brief  Disable HSI ready interrupt\n  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);\n}\n\n/**\n  * @brief  Disable HSE ready interrupt\n  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);\n}\n\n/**\n  * @brief  Disable PLL ready interrupt\n  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Disable PLLI2S ready interrupt\n  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_DisableIT_PLLI2SRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);\n}\n\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Disable PLLSAI ready interrupt\n  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_DisableIT_PLLSAIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)\n{\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);\n}\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @brief  Checks if LSI ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));\n}\n\n/**\n  * @brief  Checks if LSE ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));\n}\n\n/**\n  * @brief  Checks if HSI ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));\n}\n\n/**\n  * @brief  Checks if HSE ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));\n}\n\n/**\n  * @brief  Checks if PLL ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));\n}\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Checks if PLLI2S ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_IsEnabledIT_PLLI2SRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));\n}\n\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Checks if PLLSAI ready interrupt source is enabled or disabled.\n  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_IsEnabledIT_PLLSAIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)\n{\n  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));\n}\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_EF_Init De-initialization function\n  * @{\n  */\nErrorStatus LL_RCC_DeInit(void);\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions\n  * @{\n  */\nvoid        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);\n#if defined(FMPI2C1)\nuint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);\n#endif /* FMPI2C1 */\n#if defined(LPTIM1)\nuint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);\n#endif /* LPTIM1 */\n#if defined(SAI1)\nuint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);\n#endif /* SAI1 */\n#if defined(SDIO)\nuint32_t    LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);\n#endif /* SDIO */\n#if defined(RNG)\nuint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);\n#endif /* RNG */\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\nuint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);\n#endif /* USB_OTG_FS || USB_OTG_HS */\n#if defined(DFSDM1_Channel0)\nuint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);\nuint32_t    LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);\n#endif /* DFSDM1_Channel0 */\nuint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);\n#if defined(CEC)\nuint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);\n#endif /* CEC */\n#if defined(LTDC)\nuint32_t    LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);\n#endif /* LTDC */\n#if defined(SPDIFRX)\nuint32_t    LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);\n#endif /* SPDIFRX */\n#if defined(DSI)\nuint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);\n#endif /* DSI */\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_RCC_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_system.h\n  * @author  MCD Application Team\n  * @brief   Header file of SYSTEM LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL SYSTEM driver contains a set of generic APIs that can be\n    used by user:\n      (+) Some of the FLASH features need to be handled in the SYSTEM file.\n      (+) Access to DBGCMU registers\n      (+) Access to SYSCFG registers\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_SYSTEM_H\n#define __STM32F4xx_LL_SYSTEM_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)\n\n/** @defgroup SYSTEM_LL SYSTEM\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants\n  * @{\n  */\n\n/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP\n* @{\n*/\n#define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                  /*!< Main Flash memory mapped at 0x00000000              */\n#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */\n#if defined(FSMC_Bank1)\n#define LL_SYSCFG_REMAP_FSMC               SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000        */\n#endif /* FSMC_Bank1 */\n#if defined(FMC_Bank1)\n#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000         */\n#define LL_SYSCFG_REMAP_SDRAM              SYSCFG_MEMRMP_MEM_MODE_2                              /*!< FMC/SDRAM mapped at 0x00000000                      */\n#endif /* FMC_Bank1 */\n#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */\n\n/**\n  * @}\n  */\n\n#if defined(SYSCFG_PMC_MII_RMII_SEL)\n /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC\n* @{\n*/\n#define LL_SYSCFG_PMC_ETHMII               (uint32_t)0x00000000                                /*!< ETH Media MII interface */\n#define LL_SYSCFG_PMC_ETHRMII              (uint32_t)SYSCFG_PMC_MII_RMII_SEL                   /*!< ETH Media RMII interface */\n\n/**\n  * @}\n  */\n#endif /* SYSCFG_PMC_MII_RMII_SEL */\n\n\n\n#if defined(SYSCFG_MEMRMP_UFB_MODE)\n/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE\n  * @{\n  */\n#define LL_SYSCFG_BANKMODE_BANK1          (uint32_t)0x00000000       /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)\n                                                                      and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/\n#define LL_SYSCFG_BANKMODE_BANK2          SYSCFG_MEMRMP_UFB_MODE     /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)\n                                                                      and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */\n/**\n  * @}\n  */\n#endif /* SYSCFG_MEMRMP_UFB_MODE */\n/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS\n  * @{\n  */ \n#if defined(SYSCFG_CFGR_FMPI2C1_SCL)\n#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL         SYSCFG_CFGR_FMPI2C1_SCL   /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */\n#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA         SYSCFG_CFGR_FMPI2C1_SDA   /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/\n#endif /* SYSCFG_CFGR_FMPI2C1_SCL */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT\n  * @{\n  */\n#define LL_SYSCFG_EXTI_PORTA               (uint32_t)0               /*!< EXTI PORT A                        */\n#define LL_SYSCFG_EXTI_PORTB               (uint32_t)1               /*!< EXTI PORT B                        */\n#define LL_SYSCFG_EXTI_PORTC               (uint32_t)2               /*!< EXTI PORT C                        */\n#define LL_SYSCFG_EXTI_PORTD               (uint32_t)3               /*!< EXTI PORT D                        */\n#define LL_SYSCFG_EXTI_PORTE               (uint32_t)4               /*!< EXTI PORT E                        */\n#if defined(GPIOF)\n#define LL_SYSCFG_EXTI_PORTF               (uint32_t)5               /*!< EXTI PORT F                        */\n#endif /* GPIOF */\n#if defined(GPIOG)\n#define LL_SYSCFG_EXTI_PORTG               (uint32_t)6               /*!< EXTI PORT G                        */\n#endif /* GPIOG */\n#define LL_SYSCFG_EXTI_PORTH               (uint32_t)7               /*!< EXTI PORT H                        */\n#if defined(GPIOI)\n#define LL_SYSCFG_EXTI_PORTI               (uint32_t)8               /*!< EXTI PORT I                        */\n#endif /* GPIOI */\n#if defined(GPIOJ)\n#define LL_SYSCFG_EXTI_PORTJ               (uint32_t)9               /*!< EXTI PORT J                        */\n#endif /* GPIOJ */\n#if defined(GPIOK)\n#define LL_SYSCFG_EXTI_PORTK               (uint32_t)10              /*!< EXTI PORT k                        */\n#endif /* GPIOK */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE\n  * @{\n  */\n#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16 | 0)  /*!< EXTI_POSITION_0  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16 | 0)  /*!< EXTI_POSITION_4  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16 | 0)  /*!< EXTI_POSITION_8  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16 | 0)  /*!< EXTI_POSITION_12 | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16 | 1)  /*!< EXTI_POSITION_0  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16 | 1)  /*!< EXTI_POSITION_4  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16 | 1)  /*!< EXTI_POSITION_8  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16 | 1)  /*!< EXTI_POSITION_12 | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16 | 2)  /*!< EXTI_POSITION_0  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16 | 2)  /*!< EXTI_POSITION_4  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16 | 2)  /*!< EXTI_POSITION_8  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16 | 2)  /*!< EXTI_POSITION_12 | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16 | 3)  /*!< EXTI_POSITION_0  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16 | 3)  /*!< EXTI_POSITION_4  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16 | 3)  /*!< EXTI_POSITION_8  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16 | 3)  /*!< EXTI_POSITION_12 | EXTICR[3] */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK\n  * @{\n  */\n#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)\n#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_LOCKUP_LOCK   /*!< Enables and locks the LOCKUP output of CortexM4 \n                                                                      with Break Input of TIM1/8                                    */\n#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVD_LOCK      /*!< Enables and locks the PVD connection with TIM1/8 Break Input \n                                                                      and also the PVDE and PLS bits of the Power Control Interface  */\n#endif /* SYSCFG_CFGR2_CLL */\n/**\n  * @}\n  */\n\n#if defined(SYSCFG_MCHDLYCR_BSCKSEL)\n/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL\n  * @{\n  */\n#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1          (uint32_t)0x00000000\n#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2           SYSCFG_MCHDLYCR_BSCKSEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN              SYSCFG MCHDLY MCHDLYEN\n  * @{\n  */  \n#define LL_SYSCFG_DFSDM1_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY1EN\n#define LL_SYSCFG_DFSDM2_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY2EN\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source       SYSCFG MCHDLY DFSDMD0SEL\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_DataIn0                   SYSCFG_MCHDLYCR_DFSDM1D0SEL\n#define LL_SYSCFG_DFSDM2_DataIn0                   SYSCFG_MCHDLYCR_DFSDM2D0SEL\n\n#define LL_SYSCFG_DFSDM1_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)\n#define LL_SYSCFG_DFSDM1_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)\n#define LL_SYSCFG_DFSDM2_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)\n#define LL_SYSCFG_DFSDM2_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source       SYSCFG MCHDLY DFSDMD2SEL\n  * @{\n  */   \n#define LL_SYSCFG_DFSDM1_DataIn2                   SYSCFG_MCHDLYCR_DFSDM1D2SEL\n#define LL_SYSCFG_DFSDM2_DataIn2                   SYSCFG_MCHDLYCR_DFSDM2D2SEL\n\n#define LL_SYSCFG_DFSDM1_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)\n#define LL_SYSCFG_DFSDM1_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)\n#define LL_SYSCFG_DFSDM2_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)\n#define LL_SYSCFG_DFSDM2_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK02SEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2           SYSCFG_MCHDLYCR_DFSDM1CK02SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK13SEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3           SYSCFG_MCHDLYCR_DFSDM1CK13SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG\n  * @{\n  */\n#define LL_SYSCFG_DFSDM1_CKIN_PAD                 (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM1_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM1CFG\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM1_CKOUT                    (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM1_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM1CKOSEL\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM2_DataIn4_PAD              (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_DataIn4_DM               SYSCFG_MCHDLYCR_DFSDM2D4SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM2_DataIn6_PAD              (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_DataIn6_DM               SYSCFG_MCHDLYCR_DFSDM2D6SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK04SEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4           SYSCFG_MCHDLYCR_DFSDM2CK04SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK15SEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5           SYSCFG_MCHDLYCR_DFSDM2CK15SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK26SEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6           SYSCFG_MCHDLYCR_DFSDM2CK26SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK37SEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3           (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7           SYSCFG_MCHDLYCR_DFSDM2CK37SEL\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM2_CKIN_PAD                 (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM2CFG\n/**\n  * @}\n  */\n/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL\n  * @{\n  */ \n#define LL_SYSCFG_DFSDM2_CKOUT                    (uint32_t)0x00000000\n#define LL_SYSCFG_DFSDM2_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM2CKOSEL\n/**\n  * @}\n  */ \n#endif /* SYSCFG_MCHDLYCR_BSCKSEL */  \n\n/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment\n  * @{\n  */\n#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */\n#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP\n  * @{\n  */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */\n#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)\n#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)\n#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP     DBGMCU_APB1_FZ_DBG_LPTIM_STOP         /*!< LPTIM counter stopped when core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */\n#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */\n#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */\n#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */\n#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */\n#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */\n#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)\n#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */\n#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)\n#define LL_DBGMCU_APB1_GRP1_I2C4_STOP      DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */\n#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */\n#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)\n#define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_APB1_FZ_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */\n#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)\n#define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1_FZ_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */\n#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */\n#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)\n#define LL_DBGMCU_APB1_GRP1_CAN3_STOP      DBGMCU_APB1_FZ_DBG_CAN3_STOP          /*!< CAN3 debug stopped when Core is halted  */\n#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP\n  * @{\n  */\n#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */\n#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)\n#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */\n#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */\n#define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */\n#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)\n#define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */\n#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */\n#define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY\n  * @{\n  */\n#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */\n#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */\n#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */\n#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */\n#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */\n#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */\n#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */\n#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */\n#define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */\n#define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */\n#define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS   /*!< FLASH ten wait states */\n#define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS   /*!< FLASH eleven wait states */\n#define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS   /*!< FLASH twelve wait states */\n#define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS   /*!< FLASH thirteen wait states */\n#define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS   /*!< FLASH fourteen wait states */\n#define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS   /*!< FLASH fifteen wait states */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions\n  * @{\n  */\n\n/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG\n  * @{\n  */\n/**\n  * @brief  Set memory mapping at address 0x00000000\n  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory\n  * @param  Memory This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_REMAP_FLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SRAM\n  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)\n  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)\n{\n  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);\n}\n\n/**\n  * @brief  Get memory mapping at address 0x00000000\n  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_REMAP_FLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SRAM\n  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)\n  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));\n}\n\n#if defined(SYSCFG_MEMRMP_SWP_FMC)\n/**\n  * @brief  Enables the FMC Memory Mapping Swapping\n  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_EnableFMCMemorySwapping\n  * @note   SDRAM is accessible at 0x60000000 and NOR/RAM \n  *         is accessible at 0xC0000000   \n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)\n{\n  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);\n}\n\n/**\n  * @brief  Disables the FMC Memory Mapping Swapping\n  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_DisableFMCMemorySwapping\n  * @note   SDRAM is accessible at 0xC0000000 (default mapping)  \n  *         and NOR/RAM is accessible at 0x60000000 (default mapping)\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)\n{\n  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);\n}\n\n#endif /* SYSCFG_MEMRMP_SWP_FMC */\n/**\n  * @brief  Enables the Compensation cell Power Down\n  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_EnableCompensationCell\n  * @note   The I/O compensation cell can be used only when the device supply\n  *         voltage ranges from 2.4 to 3.6 V\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)\n{\n  SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);\n}\n\n/**\n  * @brief  Disables the Compensation cell Power Down\n  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_DisableCompensationCell\n  * @note   The I/O compensation cell can be used only when the device supply\n  *         voltage ranges from 2.4 to 3.6 V\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)\n{\n  CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);\n}\n\n/**\n  * @brief  Get Compensation Cell ready Flag\n  * @rmtoll SYSCFG_CMPCR READY  LL_SYSCFG_IsActiveFlag_CMPCR\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)\n{\n  return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));\n}\n\n#if defined(SYSCFG_PMC_MII_RMII_SEL)\n/**\n  * @brief  Select Ethernet PHY interface \n  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_SetPHYInterface\n  * @param  Interface This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_PMC_ETHMII\n  *         @arg @ref LL_SYSCFG_PMC_ETHRMII\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)\n{\n  MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);\n}\n\n/**\n  * @brief  Get Ethernet PHY interface \n  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_GetPHYInterface\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_PMC_ETHMII\n  *         @arg @ref LL_SYSCFG_PMC_ETHRMII\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));\n}\n#endif /* SYSCFG_PMC_MII_RMII_SEL */\n \n\n\n#if defined(SYSCFG_MEMRMP_UFB_MODE)\n/**\n  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)\n  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_SetFlashBankMode\n  * @param  Bank This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)\n{ \n  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);\n}\n\n/**\n  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)\n  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_GetFlashBankMode\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));\n}\n#endif /* SYSCFG_MEMRMP_UFB_MODE */\n\n#if defined(SYSCFG_CFGR_FMPI2C1_SCL)\n/**\n  * @brief  Enable the I2C fast mode plus driving capability.\n  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL   LL_SYSCFG_EnableFastModePlus\\n\n  *         SYSCFG_CFGR FMPI2C1_SDA   LL_SYSCFG_EnableFastModePlus\n  * @param  ConfigFastModePlus This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)\n{\n  SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);\n}\n\n/**\n  * @brief  Disable the I2C fast mode plus driving capability.\n  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL  LL_SYSCFG_DisableFastModePlus\\n\n  *         SYSCFG_CFGR FMPI2C1_SDA  LL_SYSCFG_DisableFastModePlus\\n\n  * @param  ConfigFastModePlus This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)\n{\n  CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);\n}\n#endif /* SYSCFG_CFGR_FMPI2C1_SCL */\n\n/**\n  * @brief  Configure source input for the EXTI external interrupt.\n  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource\n  * @param  Port This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_PORTA\n  *         @arg @ref LL_SYSCFG_EXTI_PORTB\n  *         @arg @ref LL_SYSCFG_EXTI_PORTC\n  *         @arg @ref LL_SYSCFG_EXTI_PORTD\n  *         @arg @ref LL_SYSCFG_EXTI_PORTE\n  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTH\n  *\n  *         (*) value not defined in all devices\n  * @param  Line This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_LINE0\n  *         @arg @ref LL_SYSCFG_EXTI_LINE1\n  *         @arg @ref LL_SYSCFG_EXTI_LINE2\n  *         @arg @ref LL_SYSCFG_EXTI_LINE3\n  *         @arg @ref LL_SYSCFG_EXTI_LINE4\n  *         @arg @ref LL_SYSCFG_EXTI_LINE5\n  *         @arg @ref LL_SYSCFG_EXTI_LINE6\n  *         @arg @ref LL_SYSCFG_EXTI_LINE7\n  *         @arg @ref LL_SYSCFG_EXTI_LINE8\n  *         @arg @ref LL_SYSCFG_EXTI_LINE9\n  *         @arg @ref LL_SYSCFG_EXTI_LINE10\n  *         @arg @ref LL_SYSCFG_EXTI_LINE11\n  *         @arg @ref LL_SYSCFG_EXTI_LINE12\n  *         @arg @ref LL_SYSCFG_EXTI_LINE13\n  *         @arg @ref LL_SYSCFG_EXTI_LINE14\n  *         @arg @ref LL_SYSCFG_EXTI_LINE15\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)\n{\n  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));\n}\n\n/**\n  * @brief  Get the configured defined for specific EXTI Line\n  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource\n  * @param  Line This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_LINE0\n  *         @arg @ref LL_SYSCFG_EXTI_LINE1\n  *         @arg @ref LL_SYSCFG_EXTI_LINE2\n  *         @arg @ref LL_SYSCFG_EXTI_LINE3\n  *         @arg @ref LL_SYSCFG_EXTI_LINE4\n  *         @arg @ref LL_SYSCFG_EXTI_LINE5\n  *         @arg @ref LL_SYSCFG_EXTI_LINE6\n  *         @arg @ref LL_SYSCFG_EXTI_LINE7\n  *         @arg @ref LL_SYSCFG_EXTI_LINE8\n  *         @arg @ref LL_SYSCFG_EXTI_LINE9\n  *         @arg @ref LL_SYSCFG_EXTI_LINE10\n  *         @arg @ref LL_SYSCFG_EXTI_LINE11\n  *         @arg @ref LL_SYSCFG_EXTI_LINE12\n  *         @arg @ref LL_SYSCFG_EXTI_LINE13\n  *         @arg @ref LL_SYSCFG_EXTI_LINE14\n  *         @arg @ref LL_SYSCFG_EXTI_LINE15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_PORTA\n  *         @arg @ref LL_SYSCFG_EXTI_PORTB\n  *         @arg @ref LL_SYSCFG_EXTI_PORTC\n  *         @arg @ref LL_SYSCFG_EXTI_PORTD\n  *         @arg @ref LL_SYSCFG_EXTI_PORTE\n  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTH\n  *         (*) value not defined in all devices\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));\n}\n\n#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)\n/**\n  * @brief  Set connections to TIM1/8 break inputs\n  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \\n\n  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs\n  * @param  Break This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP\n  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)\n{\n  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);\n}\n\n/**\n  * @brief  Get connections to TIM1/8 Break inputs\n  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \\n\n  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs\n  * @retval Returned value can be can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP\n  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)\n{   \n  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));\n}\n#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */\n#if defined(SYSCFG_MCHDLYCR_BSCKSEL)\n/**\n  * @brief  Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.\n  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL        LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2\n  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);\n}\n/**\n  * @brief  Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.\n  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL       LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2\n  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));\n}\n/**\n  * @brief  Enables the DFSDM1 or DFSDM2 Delay clock\n  * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN      LL_SYSCFG_DFSDM_EnableDelayClock\n  * @param MCHDLY This paramater can be one of the following values\n  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN\n  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)\n{\n  SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);\n}\n\n/**\n  * @brief  Disables the DFSDM1 or the DFSDM2 Delay clock\n  * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN      LL_SYSCFG_DFSDM1_DisableDelayClock\n  * @param MCHDLY This paramater can be one of the following values\n  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN\n  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)\n{\n  CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);\n}\n\n/**\n  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn0 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL        LL_SYSCFG_DFSDM_SetDataIn0Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));\n}\n/**\n  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn0.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL       LL_SYSCFG_DFSDM_GetDataIn0Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));\n}\n/**\n  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn2 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL        LL_SYSCFG_DFSDM_SetDataIn2Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));\n}\n/**\n  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn2.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL       LL_SYSCFG_DFSDM_GetDataIn2Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC2 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL        LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC2 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC1 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL        LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC1 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1\n  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));\n}\n\n/**\n  * @brief  Select the DFSDM1 Clock In \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG        LL_SYSCFG_DFSDM1_SetClockInSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);\n}\n/**\n  * @brief  GET the DFSDM1 Clock In\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG       LL_SYSCFG_DFSDM1_GetClockInSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));\n}\n\n/**\n  * @brief  Select the DFSDM1 Clock Out \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL        LL_SYSCFG_DFSDM1_SetClockOutSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);\n}\n/**\n  * @brief  GET the DFSDM1 Clock Out\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL       LL_SYSCFG_DFSDM1_GetClockOutSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT\n  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));\n}\n\n/**\n  * @brief  Enables the DFSDM2 Delay clock\n  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_EnableDelayClock\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)\n{\n  SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);\n}\n\n/**\n  * @brief  Disables the DFSDM2 Delay clock\n  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_DisableDelayClock\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)\n{\n  CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);\n}\n/**\n  * @brief  Select the source for DFSDM2 DatIn0 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL        LL_SYSCFG_DFSDM2_SetDataIn0Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);\n}\n/**\n  * @brief  Get the source for DFSDM2 DatIn0.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL       LL_SYSCFG_DFSDM2_GetDataIn0Source\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));\n}\n\n/**\n  * @brief  Select the source for DFSDM2 DatIn2 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL        LL_SYSCFG_DFSDM2_SetDataIn2Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);\n}\n/**\n  * @brief  Get the source for DFSDM2 DatIn2.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL       LL_SYSCFG_DFSDM2_GetDataIn2Source\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));\n}\n\n/**\n  * @brief  Select the source for DFSDM2 DatIn4 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL        LL_SYSCFG_DFSDM2_SetDataIn4Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);\n}\n/**\n  * @brief  Get the source for DFSDM2 DatIn4.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL       LL_SYSCFG_DFSDM2_GetDataIn4Source\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));\n}\n\n/**\n  * @brief  Select the source for DFSDM2 DatIn6 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL        LL_SYSCFG_DFSDM2_SetDataIn6Source\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);\n}\n/**\n  * @brief  Get the source for DFSDM2 DatIn6.\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL       LL_SYSCFG_DFSDM2_GetDataIn6Source\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC4 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL        LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC3 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL        LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC2 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL        LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC2 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));\n}\n\n/**\n  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC1 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL        LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);\n}\n/**\n  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC1 \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL       LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3\n  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));\n}\n\n/**\n  * @brief  Select the DFSDM2 Clock In \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG        LL_SYSCFG_DFSDM2_SetClockInSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);\n}\n/**\n  * @brief  GET the DFSDM2 Clock In\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG       LL_SYSCFG_DFSDM2_GetClockInSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));\n}\n\n/**\n  * @brief  Select the DFSDM2 Clock Out \n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL        LL_SYSCFG_DFSDM2_SetClockOutSourceSelection\n  * @param  ClockSource This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)\n{\n  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);\n}\n/**\n  * @brief  GET the DFSDM2 Clock Out\n  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL       LL_SYSCFG_DFSDM2_GetClockOutSourceSelection\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT\n  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27\n  * @retval None\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));\n}\n\n#endif /* SYSCFG_MCHDLYCR_BSCKSEL */\n/**\n  * @}\n  */\n\n\n/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU\n  * @{\n  */\n\n/**\n  * @brief  Return the device identifier\n  * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413\n  * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419\n  * @note For STM32F401xx devices, the device ID is 0x423\n  * @note For STM32F401xx devices, the device ID is 0x433\n  * @note For STM32F411xx devices, the device ID is 0x431\n  * @note For STM32F410xx devices, the device ID is 0x458\n  * @note For STM32F412xx devices, the device ID is 0x441\n  * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463\n  * @note For STM32F446xx devices, the device ID is 0x421\n  * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434\n  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID\n  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));\n}\n\n/**\n  * @brief  Return the device revision identifier\n  * @note This field indicates the revision of the device.\n          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices\n          For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices\n          For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices\n          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices\n          For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices\n          For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices\n  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID\n  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);\n}\n\n/**\n  * @brief  Enable the Debug Module during SLEEP mode\n  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Disable the Debug Module during SLEEP mode\n  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STOP mode\n  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Disable the Debug Module during STOP mode\n  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STANDBY mode\n  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Disable the Debug Module during STANDBY mode\n  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Set Trace pin assignment control\n  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\\n\n  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment\n  * @param  PinAssignment This parameter can be one of the following values:\n  *         @arg @ref LL_DBGMCU_TRACE_NONE\n  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)\n{\n  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);\n}\n\n/**\n  * @brief  Get Trace pin assignment control\n  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\\n\n  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DBGMCU_TRACE_NONE\n  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));\n}\n\n/**\n  * @brief  Freeze APB1 peripherals (group1 peripherals)\n  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP \n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)\n  *         \n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)\n{\n  SET_BIT(DBGMCU->APB1FZ, Periphs);\n}\n\n/**\n  * @brief  Unfreeze APB1 peripherals (group1 peripherals)\n  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP         LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP \n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)\n  *         \n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)\n{\n  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);\n}\n\n/**\n  * @brief  Freeze APB2 peripherals\n  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)\n{\n  SET_BIT(DBGMCU->APB2FZ, Periphs);\n}\n\n/**\n  * @brief  Unfreeze APB2 peripherals\n  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\\n\n  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)\n{\n  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);\n}\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EF_FLASH FLASH\n  * @{\n  */\n\n/**\n  * @brief  Set FLASH Latency\n  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency\n  * @param  Latency This parameter can be one of the following values:\n  *         @arg @ref LL_FLASH_LATENCY_0\n  *         @arg @ref LL_FLASH_LATENCY_1\n  *         @arg @ref LL_FLASH_LATENCY_2\n  *         @arg @ref LL_FLASH_LATENCY_3\n  *         @arg @ref LL_FLASH_LATENCY_4\n  *         @arg @ref LL_FLASH_LATENCY_5\n  *         @arg @ref LL_FLASH_LATENCY_6\n  *         @arg @ref LL_FLASH_LATENCY_7\n  *         @arg @ref LL_FLASH_LATENCY_8\n  *         @arg @ref LL_FLASH_LATENCY_9\n  *         @arg @ref LL_FLASH_LATENCY_10\n  *         @arg @ref LL_FLASH_LATENCY_11\n  *         @arg @ref LL_FLASH_LATENCY_12\n  *         @arg @ref LL_FLASH_LATENCY_13\n  *         @arg @ref LL_FLASH_LATENCY_14\n  *         @arg @ref LL_FLASH_LATENCY_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)\n{\n  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);\n}\n\n/**\n  * @brief  Get FLASH Latency\n  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_FLASH_LATENCY_0\n  *         @arg @ref LL_FLASH_LATENCY_1\n  *         @arg @ref LL_FLASH_LATENCY_2\n  *         @arg @ref LL_FLASH_LATENCY_3\n  *         @arg @ref LL_FLASH_LATENCY_4\n  *         @arg @ref LL_FLASH_LATENCY_5\n  *         @arg @ref LL_FLASH_LATENCY_6\n  *         @arg @ref LL_FLASH_LATENCY_7\n  *         @arg @ref LL_FLASH_LATENCY_8\n  *         @arg @ref LL_FLASH_LATENCY_9\n  *         @arg @ref LL_FLASH_LATENCY_10\n  *         @arg @ref LL_FLASH_LATENCY_11\n  *         @arg @ref LL_FLASH_LATENCY_12\n  *         @arg @ref LL_FLASH_LATENCY_13\n  *         @arg @ref LL_FLASH_LATENCY_14\n  *         @arg @ref LL_FLASH_LATENCY_15\n  */\n__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)\n{\n  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));\n}\n\n/**\n  * @brief  Enable Prefetch\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);\n}\n\n/**\n  * @brief  Disable Prefetch\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);\n}\n\n/**\n  * @brief  Check if Prefetch buffer is enabled\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)\n{\n  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));\n}\n\n/**\n  * @brief  Enable Instruction cache\n  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableInstCache(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);\n}\n\n/**\n  * @brief  Disable Instruction cache\n  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableInstCache(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);\n}\n\n/**\n  * @brief  Enable Data cache\n  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableDataCache(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);\n}\n\n/**\n  * @brief  Disable Data cache\n  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableDataCache(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);\n}\n\n/**\n  * @brief  Enable Instruction cache reset\n  * @note  bit can be written only when the instruction cache is disabled\n  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);\n}\n\n/**\n  * @brief  Disable Instruction cache reset\n  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);\n}\n\n/**\n  * @brief  Enable Data cache reset\n  * @note bit can be written only when the data cache is disabled\n  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);\n}\n\n/**\n  * @brief  Disable Data cache reset\n  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);\n}\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_SYSTEM_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_usart.h\n  * @author  MCD Application Team\n  * @brief   Header file of USART LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_USART_H\n#define __STM32F4xx_LL_USART_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)\n\n/** @defgroup USART_LL USART\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup USART_LL_Private_Constants USART Private Constants\n  * @{\n  */\n\n/* Defines used for the bit position in the register and perform offsets*/\n#define USART_POSITION_GTPR_GT                  USART_GTPR_GT_Pos\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_Private_Macros USART Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_ES_INIT USART Exported Init structures\n  * @{\n  */\n\n/**\n  * @brief LL USART Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/\n\n  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.\n                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/\n\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\n                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/\n\n  uint32_t Parity;                    /*!< Specifies the parity mode.\n                                           This parameter can be a value of @ref USART_LL_EC_PARITY.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/\n\n  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/\n\n  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/\n\n  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.\n                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/\n\n} LL_USART_InitTypeDef;\n\n/**\n  * @brief LL USART Clock Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.\n\n                                           USART HW configuration can be modified afterwards using unitary functions\n                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().\n                                           For more details, refer to description of this function. */\n\n  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.\n                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().\n                                           For more details, refer to description of this function. */\n\n  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.\n                                           This parameter can be a value of @ref USART_LL_EC_PHASE.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().\n                                           For more details, refer to description of this function. */\n\n  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted\n                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.\n                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().\n                                           For more details, refer to description of this function. */\n\n} LL_USART_ClockInitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup USART_LL_Exported_Constants USART Exported Constants\n  * @{\n  */\n\n/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_USART_ReadReg function\n  * @{\n  */\n#define LL_USART_SR_PE                          USART_SR_PE                   /*!< Parity error flag */\n#define LL_USART_SR_FE                          USART_SR_FE                   /*!< Framing error flag */\n#define LL_USART_SR_NE                          USART_SR_NE                   /*!< Noise detected flag */\n#define LL_USART_SR_ORE                         USART_SR_ORE                  /*!< Overrun error flag */\n#define LL_USART_SR_IDLE                        USART_SR_IDLE                 /*!< Idle line detected flag */\n#define LL_USART_SR_RXNE                        USART_SR_RXNE                 /*!< Read data register not empty flag */\n#define LL_USART_SR_TC                          USART_SR_TC                   /*!< Transmission complete flag */\n#define LL_USART_SR_TXE                         USART_SR_TXE                  /*!< Transmit data register empty flag */\n#define LL_USART_SR_LBD                         USART_SR_LBD                  /*!< LIN break detection flag */\n#define LL_USART_SR_CTS                         USART_SR_CTS                  /*!< CTS flag */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions\n  * @{\n  */\n#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */\n#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */\n#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */\n#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */\n#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */\n#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */\n#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */\n#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_DIRECTION Communication Direction\n  * @{\n  */\n#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */\n#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */\n#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */\n#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_PARITY Parity Control\n  * @{\n  */ \n#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */\n#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */\n#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_WAKEUP Wakeup\n  * @{\n  */\n#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */\n#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_DATAWIDTH Datawidth\n  * @{\n  */\n#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */\n#define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling\n  * @{\n  */\n#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */\n#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_EC_CLOCK Clock Signal\n  * @{\n  */\n\n#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */\n#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse\n  * @{\n  */\n#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */\n#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_PHASE Clock Phase\n  * @{\n  */\n#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */\n#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_POLARITY Clock Polarity\n  * @{\n  */\n#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/\n#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_STOPBITS Stop Bits\n  * @{\n  */\n#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */\n#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */\n#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */\n#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_HWCONTROL Hardware Control\n  * @{\n  */\n#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */\n#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */\n#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */\n#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power\n  * @{\n  */\n#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */\n#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length\n  * @{\n  */\n#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */\n#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup USART_LL_Exported_Macros USART Exported Macros\n  * @{\n  */\n\n/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in USART register\n  * @param  __INSTANCE__ USART Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in USART register\n  * @param  __INSTANCE__ USART Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper\n  * @{\n  */\n\n/**\n  * @brief  Compute USARTDIV value according to Peripheral Clock and\n  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)\n  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance\n  * @param  __BAUDRATE__ Baud rate value to achieve\n  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case\n  */\n#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__)      (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))\n#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)\n#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)\n/* UART BRR = mantissa + overflow + fraction\n            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */\n#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)             (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \\\n                                                                           ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \\\n                                                                           (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))\n\n/**\n  * @brief  Compute USARTDIV value according to Peripheral Clock and\n  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)\n  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance\n  * @param  __BAUDRATE__ Baud rate value to achieve\n  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case\n  */\n#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__)     (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))\n#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)\n#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)\n/* USART BRR = mantissa + overflow + fraction\n            = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */\n#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)            (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \\\n                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \\\n                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup USART_LL_Exported_Functions USART Exported Functions\n  * @{\n  */\n\n/** @defgroup USART_LL_EF_Configuration Configuration functions\n  * @{\n  */\n\n/**\n  * @brief  USART Enable\n  * @rmtoll CR1          UE            LL_USART_Enable\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_UE);\n}\n\n/**\n  * @brief  USART Disable (all USART prescalers and outputs are disabled)\n  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,\n  *         and current operations are discarded. The configuration of the USART is kept, but all the status\n  *         flags, in the USARTx_SR are set to their default values.\n  * @rmtoll CR1          UE            LL_USART_Disable\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);\n}\n\n/**\n  * @brief  Indicate if USART is enabled\n  * @rmtoll CR1          UE            LL_USART_IsEnabled\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));\n}\n\n/**\n  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)\n  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RE);\n}\n\n/**\n  * @brief  Receiver Disable\n  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);\n}\n\n/**\n  * @brief  Transmitter Enable\n  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TE);\n}\n\n/**\n  * @brief  Transmitter Disable\n  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);\n}\n\n/**\n  * @brief  Configure simultaneously enabled/disabled states\n  *         of Transmitter and Receiver\n  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\\n\n  *         CR1          TE            LL_USART_SetTransferDirection\n  * @param  USARTx USART Instance\n  * @param  TransferDirection This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DIRECTION_NONE\n  *         @arg @ref LL_USART_DIRECTION_RX\n  *         @arg @ref LL_USART_DIRECTION_TX\n  *         @arg @ref LL_USART_DIRECTION_TX_RX\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);\n}\n\n/**\n  * @brief  Return enabled/disabled states of Transmitter and Receiver\n  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\\n\n  *         CR1          TE            LL_USART_GetTransferDirection\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_DIRECTION_NONE\n  *         @arg @ref LL_USART_DIRECTION_RX\n  *         @arg @ref LL_USART_DIRECTION_TX\n  *         @arg @ref LL_USART_DIRECTION_TX_RX\n  */\n__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));\n}\n\n/**\n  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).\n  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.\n  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position\n  *         (9th or 8th bit depending on data width) and parity is checked on the received data.\n  * @rmtoll CR1          PS            LL_USART_SetParity\\n\n  *         CR1          PCE           LL_USART_SetParity\n  * @param  USARTx USART Instance\n  * @param  Parity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);\n}\n\n/**\n  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)\n  * @rmtoll CR1          PS            LL_USART_GetParity\\n\n  *         CR1          PCE           LL_USART_GetParity\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  */\n__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));\n}\n\n/**\n  * @brief  Set Receiver Wake Up method from Mute mode.\n  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod\n  * @param  USARTx USART Instance\n  * @param  Method This parameter can be one of the following values:\n  *         @arg @ref LL_USART_WAKEUP_IDLELINE\n  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);\n}\n\n/**\n  * @brief  Return Receiver Wake Up method from Mute mode\n  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_WAKEUP_IDLELINE\n  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK\n  */\n__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));\n}\n\n/**\n  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)\n  * @rmtoll CR1          M             LL_USART_SetDataWidth\n  * @param  USARTx USART Instance\n  * @param  DataWidth This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);\n}\n\n/**\n  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)\n  * @rmtoll CR1          M             LL_USART_GetDataWidth\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  */\n__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));\n}\n\n/**\n  * @brief  Set Oversampling to 8-bit or 16-bit mode\n  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling\n  * @param  USARTx USART Instance\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);\n}\n\n/**\n  * @brief  Return Oversampling mode\n  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  */\n__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));\n}\n\n/**\n  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput\n  * @param  USARTx USART Instance\n  * @param  LastBitClockPulse This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);\n}\n\n/**\n  * @brief  Retrieve Clock pulse of the last data bit output configuration\n  *         (Last bit Clock pulse output to the SCLK pin or not)\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  */\n__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));\n}\n\n/**\n  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase\n  * @param  USARTx USART Instance\n  * @param  ClockPhase This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);\n}\n\n/**\n  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  */\n__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));\n}\n\n/**\n  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity\n  * @param  USARTx USART Instance\n  * @param  ClockPolarity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);\n}\n\n/**\n  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  */\n__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));\n}\n\n/**\n  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function\n  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function\n  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function\n  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\\n\n  *         CR2          CPOL          LL_USART_ConfigClock\\n\n  *         CR2          LBCL          LL_USART_ConfigClock\n  * @param  USARTx USART Instance\n  * @param  Phase This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  * @param  Polarity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  * @param  LBCPOutput This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);\n}\n\n/**\n  * @brief  Enable Clock output on SCLK pin\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Disable Clock output on SCLK pin\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Indicate if Clock output on SCLK pin is enabled\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));\n}\n\n/**\n  * @brief  Set the length of the stop bits\n  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength\n  * @param  USARTx USART Instance\n  * @param  StopBits This parameter can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);\n}\n\n/**\n  * @brief  Retrieve the length of the stop bits\n  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  */\n__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));\n}\n\n/**\n  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function\n  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function\n  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function\n  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\\n\n  *         CR1          PCE           LL_USART_ConfigCharacter\\n\n  *         CR1          M             LL_USART_ConfigCharacter\\n\n  *         CR2          STOP          LL_USART_ConfigCharacter\n  * @param  USARTx USART Instance\n  * @param  DataWidth This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  * @param  Parity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  * @param  StopBits This parameter can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,\n                                              uint32_t StopBits)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);\n  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);\n}\n\n/**\n  * @brief  Set Address of the USART node.\n  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,\n  *         for wake up with address mark detection.\n  * @rmtoll CR2          ADD           LL_USART_SetNodeAddress\n  * @param  USARTx USART Instance\n  * @param  NodeAddress 4 bit Address of the USART node.\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));\n}\n\n/**\n  * @brief  Return 4 bit Address of the USART node as set in ADD field of CR2.\n  * @note   only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)\n  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress\n  * @param  USARTx USART Instance\n  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));\n}\n\n/**\n  * @brief  Enable RTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_RTSE);\n}\n\n/**\n  * @brief  Disable RTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);\n}\n\n/**\n  * @brief  Enable CTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_CTSE);\n}\n\n/**\n  * @brief  Disable CTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);\n}\n\n/**\n  * @brief  Configure HW Flow Control mode (both CTS and RTS)\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\\n\n  *         CR3          CTSE          LL_USART_SetHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @param  HardwareFlowControl This parameter can be one of the following values:\n  *         @arg @ref LL_USART_HWCONTROL_NONE\n  *         @arg @ref LL_USART_HWCONTROL_RTS\n  *         @arg @ref LL_USART_HWCONTROL_CTS\n  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);\n}\n\n/**\n  * @brief  Return HW Flow Control configuration (both CTS and RTS)\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\\n\n  *         CR3          CTSE          LL_USART_GetHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_HWCONTROL_NONE\n  *         @arg @ref LL_USART_HWCONTROL_RTS\n  *         @arg @ref LL_USART_HWCONTROL_CTS\n  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS\n  */\n__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));\n}\n\n/**\n  * @brief  Enable One bit sampling method\n  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);\n}\n\n/**\n  * @brief  Disable One bit sampling method\n  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);\n}\n\n/**\n  * @brief  Indicate if One bit sampling method is enabled\n  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));\n}\n\n/**\n  * @brief  Configure USART BRR register for achieving expected Baud Rate value.\n  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)\n  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values\n  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid\n  *         (Baud rate value != 0)\n  * @rmtoll BRR          BRR           LL_USART_SetBaudRate\n  * @param  USARTx USART Instance\n  * @param  PeriphClk Peripheral Clock\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @param  BaudRate Baud Rate\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,\n                                          uint32_t BaudRate)\n{\n  if (OverSampling == LL_USART_OVERSAMPLING_8)\n  {\n    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));\n  }\n  else\n  {\n    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));\n  }\n}\n\n/**\n  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register\n  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values\n  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.\n  * @rmtoll BRR          BRR           LL_USART_GetBaudRate\n  * @param  USARTx USART Instance\n  * @param  PeriphClk Peripheral Clock\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @retval Baud Rate\n  */\n__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)\n{\n  register uint32_t usartdiv = 0x0U;\n  register uint32_t brrresult = 0x0U;\n\n  usartdiv = USARTx->BRR;\n\n  if (OverSampling == LL_USART_OVERSAMPLING_8)\n  {\n    if ((usartdiv & 0xFFF7U) != 0U)\n    {\n      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;\n      brrresult = (PeriphClk * 2U) / usartdiv;\n    }\n  }\n  else\n  {\n    if ((usartdiv & 0xFFFFU) != 0U)\n    {\n      brrresult = PeriphClk / usartdiv;\n    }\n  }\n  return (brrresult);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature\n  * @{\n  */\n\n/**\n  * @brief  Enable IrDA mode\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_EnableIrda\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Disable IrDA mode\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_DisableIrda\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Indicate if IrDA mode is enabled\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));\n}\n\n/**\n  * @brief  Configure IrDA Power Mode (Normal or Low Power)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode\n  * @param  USARTx USART Instance\n  * @param  PowerMode This parameter can be one of the following values:\n  *         @arg @ref LL_USART_IRDA_POWER_NORMAL\n  *         @arg @ref LL_USART_IRDA_POWER_LOW\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);\n}\n\n/**\n  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_IRDA_POWER_NORMAL\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  */\n__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));\n}\n\n/**\n  * @brief  Set Irda prescaler value, used for dividing the USART clock source\n  *         to achieve the Irda Low Power frequency (8 bits value)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler\n  * @param  USARTx USART Instance\n  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);\n}\n\n/**\n  * @brief  Return Irda prescaler value, used for dividing the USART clock source\n  *         to achieve the Irda Low Power frequency (8 bits value)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler\n  * @param  USARTx USART Instance\n  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature\n  * @{\n  */\n\n/**\n  * @brief  Enable Smartcard NACK transmission\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_NACK);\n}\n\n/**\n  * @brief  Disable Smartcard NACK transmission\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);\n}\n\n/**\n  * @brief  Indicate if Smartcard NACK transmission is enabled\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));\n}\n\n/**\n  * @brief  Enable Smartcard mode\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Disable Smartcard mode\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Indicate if Smartcard mode is enabled\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));\n}\n\n/**\n  * @brief  Set Smartcard prescaler value, used for dividing the USART clock\n  *         source to provide the SMARTCARD Clock (5 bits value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler\n  * @param  USARTx USART Instance\n  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);\n}\n\n/**\n  * @brief  Return Smartcard prescaler value, used for dividing the USART clock\n  *         source to provide the SMARTCARD Clock (5 bits value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler\n  * @param  USARTx USART Instance\n  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));\n}\n\n/**\n  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods\n  *         (GT[7:0] bits : Guard time value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime\n  * @param  USARTx USART Instance\n  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);\n}\n\n/**\n  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods\n  *         (GT[7:0] bits : Guard time value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime\n  * @param  USARTx USART Instance\n  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature\n  * @{\n  */\n\n/**\n  * @brief  Enable Single Wire Half-Duplex mode\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Disable Single Wire Half-Duplex mode\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Indicate if Single Wire Half-Duplex mode is enabled\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature\n  * @{\n  */\n\n/**\n  * @brief  Set LIN Break Detection Length\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen\n  * @param  USARTx USART Instance\n  * @param  LINBDLength This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LINBREAK_DETECT_10B\n  *         @arg @ref LL_USART_LINBREAK_DETECT_11B\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);\n}\n\n/**\n  * @brief  Return LIN Break Detection Length\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_LINBREAK_DETECT_10B\n  *         @arg @ref LL_USART_LINBREAK_DETECT_11B\n  */\n__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));\n}\n\n/**\n  * @brief  Enable LIN mode\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_EnableLIN\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Disable LIN mode\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_DisableLIN\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Indicate if LIN mode is enabled\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services\n  * @{\n  */\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)\n  * @note   In UART mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  * @note   Other remaining configurations items related to Asynchronous Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\\n\n  *         CR3          SCEN          LL_USART_ConfigAsyncMode\\n\n  *         CR3          IREN          LL_USART_ConfigAsyncMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigAsyncMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)\n{\n  /* In Asynchronous mode, the following bits must be kept cleared:\n  - LINEN, CLKEN bits in the USART_CR2 register,\n  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode\n  * @note   In Synchronous mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also sets the USART in Synchronous mode.\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function\n  * @note   Other remaining configurations items related to Synchronous Mode\n  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigSyncMode\\n\n  *         CR3          SCEN          LL_USART_ConfigSyncMode\\n\n  *         CR3          IREN          LL_USART_ConfigSyncMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigSyncMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)\n{\n  /* In Synchronous mode, the following bits must be kept cleared:\n  - LINEN bit in the USART_CR2 register,\n  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));\n  /* set the UART/USART in Synchronous mode */\n  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in LIN Mode\n  * @note   In LIN mode, the following bits must be kept cleared:\n  *           - STOP and CLKEN bits in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also set the UART/USART in LIN mode.\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function\n  * @note   Other remaining configurations items related to LIN Mode\n  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\\n\n  *         CR2          STOP          LL_USART_ConfigLINMode\\n\n  *         CR2          LINEN         LL_USART_ConfigLINMode\\n\n  *         CR3          IREN          LL_USART_ConfigLINMode\\n\n  *         CR3          SCEN          LL_USART_ConfigLINMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigLINMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)\n{\n  /* In LIN mode, the following bits must be kept cleared:\n  - STOP and CLKEN bits in the USART_CR2 register,\n  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));\n  /* Set the UART/USART in LIN mode */\n  SET_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode\n  * @note   In Half Duplex mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *         This function also sets the UART/USART in Half Duplex mode.\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function\n  * @note   Other remaining configurations items related to Half Duplex Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)\n{\n  /* In Half Duplex mode, the following bits must be kept cleared:\n  - LINEN and CLKEN bits in the USART_CR2 register,\n  - SCEN and IREN bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));\n  /* set the UART/USART in Half Duplex mode */\n  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode\n  * @note   In Smartcard mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also configures Stop bits to 1.5 bits and\n  *         sets the USART in Smartcard mode (SCEN bit).\n  *         Clock Output is also enabled (CLKEN).\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function\n  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function\n  * @note   Other remaining configurations items related to Smartcard Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\\n\n  *         CR2          STOP          LL_USART_ConfigSmartcardMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\\n\n  *         CR3          SCEN          LL_USART_ConfigSmartcardMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)\n{\n  /* In Smartcard mode, the following bits must be kept cleared:\n  - LINEN bit in the USART_CR2 register,\n  - IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));\n  /* Configure Stop bits to 1.5 bits */\n  /* Synchronous mode is activated by default */\n  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));\n  /* set the UART/USART in Smartcard mode */\n  SET_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Irda Mode\n  * @note   In IRDA mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - STOP and CLKEN bits in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also sets the UART/USART in IRDA mode (IREN bit).\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function\n  * @note   Other remaining configurations items related to Irda Mode\n  *         (as Baud Rate, Word length, Power mode, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\\n\n  *         CR2          STOP          LL_USART_ConfigIrdaMode\\n\n  *         CR3          SCEN          LL_USART_ConfigIrdaMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\\n\n  *         CR3          IREN          LL_USART_ConfigIrdaMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)\n{\n  /* In IRDA mode, the following bits must be kept cleared:\n  - LINEN, STOP and CLKEN bits in the USART_CR2 register,\n  - SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));\n  /* set the UART/USART in IRDA mode */\n  SET_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode\n  *         (several USARTs connected in a network, one of the USARTs can be the master,\n  *         its TX output connected to the RX inputs of the other slaves USARTs).\n  * @note   In MultiProcessor mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  * @note   Other remaining configurations items related to Multi processor Mode\n  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          IREN          LL_USART_ConfigMultiProcessMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)\n{\n  /* In Multi Processor mode, the following bits must be kept cleared:\n  - LINEN and CLKEN bits in the USART_CR2 register,\n  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Check if the USART Parity Error Flag is set or not\n  * @rmtoll SR           PE            LL_USART_IsActiveFlag_PE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));\n}\n\n/**\n  * @brief  Check if the USART Framing Error Flag is set or not\n  * @rmtoll SR           FE            LL_USART_IsActiveFlag_FE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));\n}\n\n/**\n  * @brief  Check if the USART Noise error detected Flag is set or not\n  * @rmtoll SR           NF            LL_USART_IsActiveFlag_NE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));\n}\n\n/**\n  * @brief  Check if the USART OverRun Error Flag is set or not\n  * @rmtoll SR           ORE           LL_USART_IsActiveFlag_ORE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));\n}\n\n/**\n  * @brief  Check if the USART IDLE line detected Flag is set or not\n  * @rmtoll SR           IDLE          LL_USART_IsActiveFlag_IDLE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));\n}\n\n/**\n  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not\n  * @rmtoll SR           RXNE          LL_USART_IsActiveFlag_RXNE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));\n}\n\n/**\n  * @brief  Check if the USART Transmission Complete Flag is set or not\n  * @rmtoll SR           TC            LL_USART_IsActiveFlag_TC\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));\n}\n\n/**\n  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not\n  * @rmtoll SR           TXE           LL_USART_IsActiveFlag_TXE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));\n}\n\n/**\n  * @brief  Check if the USART LIN Break Detection Flag is set or not\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll SR           LBD           LL_USART_IsActiveFlag_LBD\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));\n}\n\n/**\n  * @brief  Check if the USART CTS Flag is set or not\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll SR           CTS           LL_USART_IsActiveFlag_nCTS\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));\n}\n\n/**\n  * @brief  Check if the USART Send Break Flag is set or not\n  * @rmtoll CR1          SBK           LL_USART_IsActiveFlag_SBK\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));\n}\n\n/**\n  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not\n  * @rmtoll CR1          RWU           LL_USART_IsActiveFlag_RWU\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));\n}\n\n/**\n  * @brief  Clear Parity Error Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as \n  *         NE, FE, ORE, IDLE would also be cleared.\n  * @rmtoll SR           PE            LL_USART_ClearFlag_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear Framing Error Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as \n  *         PE, NE, ORE, IDLE would also be cleared.\n  * @rmtoll SR           FE            LL_USART_ClearFlag_FE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear Noise detected Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as \n  *         PE, FE, ORE, IDLE would also be cleared.\n  * @rmtoll SR           NF            LL_USART_ClearFlag_NE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear OverRun Error Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as \n  *         PE, NE, FE, IDLE would also be cleared.\n  * @rmtoll SR           ORE           LL_USART_ClearFlag_ORE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear IDLE line detected Flag\n  * @note   Clearing this flag is done by a read access to the USARTx_SR\n  *         register followed by a read access to the USARTx_DR register.\n  * @note   Please also consider that when clearing this flag, other flags as \n  *         PE, NE, FE, ORE would also be cleared.\n  * @rmtoll SR           IDLE          LL_USART_ClearFlag_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)\n{\n  __IO uint32_t tmpreg;\n  tmpreg = USARTx->SR;\n  (void) tmpreg;\n  tmpreg = USARTx->DR;\n  (void) tmpreg;\n}\n\n/**\n  * @brief  Clear Transmission Complete Flag\n  * @rmtoll SR           TC            LL_USART_ClearFlag_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->SR , ~(USART_SR_TC));\n}\n\n/**\n  * @brief  Clear RX Not Empty Flag\n  * @rmtoll SR           RXNE          LL_USART_ClearFlag_RXNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));\n}\n\n/**\n  * @brief  Clear LIN Break Detection Flag\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll SR           LBD           LL_USART_ClearFlag_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->SR , ~(USART_SR_LBD));\n}\n\n/**\n  * @brief  Clear CTS Interrupt Flag\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll SR           CTS           LL_USART_ClearFlag_nCTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->SR , ~(USART_SR_CTS));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_IT_Management IT_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable IDLE Interrupt\n  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);\n}\n\n/**\n  * @brief  Enable RX Not Empty Interrupt\n  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);\n}\n\n/**\n  * @brief  Enable Transmission Complete Interrupt\n  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TCIE);\n}\n\n/**\n  * @brief  Enable TX Empty Interrupt\n  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TXEIE);\n}\n\n/**\n  * @brief  Enable Parity Error Interrupt\n  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_PEIE);\n}\n\n/**\n  * @brief  Enable LIN Break Detection Interrupt\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);\n}\n\n/**\n  * @brief  Enable Error Interrupt\n  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing\n  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).\n  *           0: Interrupt is inhibited\n  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.\n  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_EIE);\n}\n\n/**\n  * @brief  Enable CTS Interrupt\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);\n}\n\n/**\n  * @brief  Disable IDLE Interrupt\n  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);\n}\n\n/**\n  * @brief  Disable RX Not Empty Interrupt\n  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);\n}\n\n/**\n  * @brief  Disable Transmission Complete Interrupt\n  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);\n}\n\n/**\n  * @brief  Disable TX Empty Interrupt\n  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);\n}\n\n/**\n  * @brief  Disable Parity Error Interrupt\n  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);\n}\n\n/**\n  * @brief  Disable LIN Break Detection Interrupt\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);\n}\n\n/**\n  * @brief  Disable Error Interrupt\n  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing\n  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).\n  *           0: Interrupt is inhibited\n  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.\n  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);\n}\n\n/**\n  * @brief  Disable CTS Interrupt\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);\n}\n\n/**\n  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.\n  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));\n}\n\n/**\n  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));\n}\n\n/**\n  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.\n  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));\n}\n\n/**\n  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));\n}\n\n/**\n  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.\n  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));\n}\n\n/**\n  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));\n}\n\n/**\n  * @brief  Check if the USART Error Interrupt is enabled or disabled.\n  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));\n}\n\n/**\n  * @brief  Check if the USART CTS Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_DMA_Management DMA_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable DMA Mode for reception\n  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_DMAR);\n}\n\n/**\n  * @brief  Disable DMA Mode for reception\n  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);\n}\n\n/**\n  * @brief  Check if DMA Mode is enabled for reception\n  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));\n}\n\n/**\n  * @brief  Enable DMA Mode for transmission\n  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_DMAT);\n}\n\n/**\n  * @brief  Disable DMA Mode for transmission\n  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);\n}\n\n/**\n  * @brief  Check if DMA Mode is enabled for transmission\n  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));\n}\n\n/**\n  * @brief  Get the data register address used for DMA transfer\n  * @rmtoll DR           DR            LL_USART_DMA_GetRegAddr\n  * @note   Address of Data Register is valid for both Transmit and Receive transfers.\n  * @param  USARTx USART Instance\n  * @retval Address of data register\n  */\n__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)\n{\n  /* return address of DR register */\n  return ((uint32_t) &(USARTx->DR));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Data_Management Data_Management\n  * @{\n  */\n\n/**\n  * @brief  Read Receiver Data register (Receive Data value, 8 bits)\n  * @rmtoll DR           DR            LL_USART_ReceiveData8\n  * @param  USARTx USART Instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)\n{\n  return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));\n}\n\n/**\n  * @brief  Read Receiver Data register (Receive Data value, 9 bits)\n  * @rmtoll DR           DR            LL_USART_ReceiveData9\n  * @param  USARTx USART Instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF\n  */\n__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)\n{\n  return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));\n}\n\n/**\n  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)\n  * @rmtoll DR           DR            LL_USART_TransmitData8\n  * @param  USARTx USART Instance\n  * @param  Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)\n{\n  USARTx->DR = Value;\n}\n\n/**\n  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)\n  * @rmtoll DR           DR            LL_USART_TransmitData9\n  * @param  USARTx USART Instance\n  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)\n{\n  USARTx->DR = Value & 0x1FFU;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Execution Execution\n  * @{\n  */\n\n/**\n  * @brief  Request Break sending\n  * @rmtoll CR1          SBK           LL_USART_RequestBreakSending\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_SBK);\n}\n\n/**\n  * @brief  Put USART in Mute mode\n  * @rmtoll CR1          RWU           LL_USART_RequestEnterMuteMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RWU);\n}\n\n/**\n  * @brief  Put USART in Active mode\n  * @rmtoll CR1          RWU           LL_USART_RequestExitMuteMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\nErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);\nErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);\nvoid        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);\nErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);\nvoid        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_USART_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_utils.h\n  * @author  MCD Application Team\n  * @brief   Header file of UTILS LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL UTILS driver contains a set of generic APIs that can be\n    used by user:\n      (+) Device electronic signature\n      (+) Timing functions\n      (+) PLL configuration functions\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_UTILS_H\n#define __STM32F4xx_LL_UTILS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n/** @defgroup UTILS_LL UTILS\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants\n  * @{\n  */\n\n/* Max delay can be used in LL_mDelay */\n#define LL_MAX_DELAY                  0xFFFFFFFFU\n\n/**\n * @brief Unique device ID register base address\n */\n#define UID_BASE_ADDRESS              UID_BASE\n\n/**\n * @brief Flash size data register base address\n */\n#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE\n\n/**\n * @brief Package data register base address\n */\n#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures\n  * @{\n  */\n/**\n  * @brief  UTILS PLL structure definition\n  */\ntypedef struct\n{\n  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.\n                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n\n  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.\n                        This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE\n                        and Max_Data = @ref RCC_PLLN_MIN_VALUE\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n\n  uint32_t PLLP;   /*!< Division for the main system clock.\n                        This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n} LL_UTILS_PLLInitTypeDef;\n\n/**\n  * @brief  UTILS System, AHB and APB buses clock configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAHBPrescaler(). */\n\n  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAPB1Prescaler(). */\n\n  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAPB2Prescaler(). */\n\n} LL_UTILS_ClkInitTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants\n  * @{\n  */\n\n/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation\n  * @{\n  */\n#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */\n#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE\n  * @{\n  */\n#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64                        0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type                         */\n#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48       0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type  */\n#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176               0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type             */\n#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100             0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type           */\n#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216                       0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type                        */\n#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216                               0x00000500U /*!< LQFP208 or TFBGA216 package type                                   */\n#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144                        0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type                         */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions\n  * @{\n  */\n\n/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE\n  * @{\n  */\n\n/**\n  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[31:0]\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word0(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));\n}\n\n/**\n  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[63:32]\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word1(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));\n}\n\n/**\n  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[95:64]\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word2(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));\n}\n\n/**\n  * @brief  Get Flash memory size\n  * @note   This bitfield indicates the size of the device Flash memory expressed in\n  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.\n  * @retval FLASH_SIZE[15:0]: Flash memory size\n  */\n__STATIC_INLINE uint32_t LL_GetFlashSize(void)\n{\n  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));\n}\n\n/**\n  * @brief  Get Package type\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)\n  * \n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_GetPackageType(void)\n{\n  return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_LL_EF_DELAY DELAY\n  * @{\n  */\n\n/**\n  * @brief  This function configures the Cortex-M SysTick source of the time base.\n  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)\n  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick \n  *         configuration by calling this function, for a delay use rather osDelay RTOS service.\n  * @param  Ticks Number of ticks\n  * @retval None\n  */\n__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)\n{\n  /* Configure the SysTick to have interrupt in 1ms time base */\n  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */\n  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */\n}\n\nvoid        LL_Init1msTick(uint32_t HCLKFrequency);\nvoid        LL_mDelay(uint32_t Delay);\n\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_EF_SYSTEM SYSTEM\n  * @{\n  */\n\nvoid        LL_SetSystemCoreClock(uint32_t HCLKFrequency);\nErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,\n                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\nErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,\n                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_UTILS_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_dma.c\n  * @author  MCD Application Team\n  * @brief   DMA LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_dma.h\"\n#include \"stm32f4xx_ll_bus.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (DMA1) || defined (DMA2)\n\n/** @defgroup DMA_LL DMA\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup DMA_LL_Private_Macros\n  * @{\n  */\n#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \\\n                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \\\n                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))\n\n#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \\\n                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \\\n                                                 ((__VALUE__) == LL_DMA_MODE_PFCTRL))\n\n#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \\\n                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))\n\n#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \\\n                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))\n\n#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \\\n                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \\\n                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))\n\n#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \\\n                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \\\n                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))\n\n#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)\n\n#define IS_LL_DMA_CHANNEL(__VALUE__)            (((__VALUE__) == LL_DMA_CHANNEL_0)  || \\\n                                                 ((__VALUE__) == LL_DMA_CHANNEL_1)  || \\\n                                                 ((__VALUE__) == LL_DMA_CHANNEL_2)  || \\\n                                                 ((__VALUE__) == LL_DMA_CHANNEL_3)  || \\\n                                                 ((__VALUE__) == LL_DMA_CHANNEL_4)  || \\\n                                                 ((__VALUE__) == LL_DMA_CHANNEL_5)  || \\\n                                                 ((__VALUE__) == LL_DMA_CHANNEL_6)  || \\\n                                                 ((__VALUE__) == LL_DMA_CHANNEL_7))\n\n#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \\\n                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \\\n                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \\\n                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))\n\n#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \\\n                                                           (((STREAM) == LL_DMA_STREAM_0) || \\\n                                                            ((STREAM) == LL_DMA_STREAM_1) || \\\n                                                            ((STREAM) == LL_DMA_STREAM_2) || \\\n                                                            ((STREAM) == LL_DMA_STREAM_3) || \\\n                                                            ((STREAM) == LL_DMA_STREAM_4) || \\\n                                                            ((STREAM) == LL_DMA_STREAM_5) || \\\n                                                            ((STREAM) == LL_DMA_STREAM_6) || \\\n                                                            ((STREAM) == LL_DMA_STREAM_7) || \\\n                                                            ((STREAM) == LL_DMA_STREAM_ALL))) ||\\\n                                                            (((INSTANCE) == DMA2) && \\\n                                                          (((STREAM) == LL_DMA_STREAM_0) || \\\n                                                           ((STREAM) == LL_DMA_STREAM_1) || \\\n                                                           ((STREAM) == LL_DMA_STREAM_2) || \\\n                                                           ((STREAM) == LL_DMA_STREAM_3) || \\\n                                                           ((STREAM) == LL_DMA_STREAM_4) || \\\n                                                           ((STREAM) == LL_DMA_STREAM_5) || \\\n                                                           ((STREAM) == LL_DMA_STREAM_6) || \\\n                                                           ((STREAM) == LL_DMA_STREAM_7) || \\\n                                                           ((STREAM) == LL_DMA_STREAM_ALL))))\n\n#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \\\n                                          ((STATE) == LL_DMA_FIFOMODE_ENABLE))\n\n#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \\\n                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \\\n                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \\\n                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))\n\n#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \\\n                                       ((BURST) == LL_DMA_MBURST_INC4)   || \\\n                                       ((BURST) == LL_DMA_MBURST_INC8)   || \\\n                                       ((BURST) == LL_DMA_MBURST_INC16))\n\n#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \\\n                                           ((BURST) == LL_DMA_PBURST_INC4)   || \\\n                                           ((BURST) == LL_DMA_PBURST_INC8)   || \\\n                                           ((BURST) == LL_DMA_PBURST_INC16))\n\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup DMA_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup DMA_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize the DMA registers to their default reset values.\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  *         @arg @ref LL_DMA_STREAM_ALL\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: DMA registers are de-initialized\n  *          - ERROR: DMA registers are not de-initialized\n  */\nuint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)\n{\n  DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;\n  ErrorStatus status = SUCCESS;\n\n  /* Check the DMA Instance DMAx and Stream parameters*/\n  assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));\n\n  if (Stream == LL_DMA_STREAM_ALL)\n  {\n    if (DMAx == DMA1)\n    {\n      /* Force reset of DMA clock */\n      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);\n\n      /* Release reset of DMA clock */\n      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);\n    }\n    else if (DMAx == DMA2)\n    {\n      /* Force reset of DMA clock */\n      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);\n\n      /* Release reset of DMA clock */\n      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);\n    }\n    else\n    {\n      status = ERROR;\n    }\n  }\n  else\n  {\n    /* Disable the selected Stream */\n    LL_DMA_DisableStream(DMAx,Stream);\n\n    /* Get the DMA Stream Instance */\n    tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));\n\n    /* Reset DMAx_Streamy configuration register */\n    LL_DMA_WriteReg(tmp, CR, 0U);\n\n    /* Reset DMAx_Streamy remaining bytes register */\n    LL_DMA_WriteReg(tmp, NDTR, 0U);\n\n    /* Reset DMAx_Streamy peripheral address register */\n    LL_DMA_WriteReg(tmp, PAR, 0U);\n\n    /* Reset DMAx_Streamy memory address register */\n    LL_DMA_WriteReg(tmp, M0AR, 0U);\n\n    /* Reset DMAx_Streamy memory address register */\n    LL_DMA_WriteReg(tmp, M1AR, 0U);\n\n    /* Reset DMAx_Streamy FIFO control register */\n    LL_DMA_WriteReg(tmp, FCR, 0x00000021U);\n\n    /* Reset Channel register field for DMAx Stream*/\n    LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);\n\n    if(Stream == LL_DMA_STREAM_0)\n    {\n       /* Reset the Stream0 pending flags */\n       DMAx->LIFCR = 0x0000003FU;\n    }\n    else if(Stream == LL_DMA_STREAM_1)\n    {\n       /* Reset the Stream1 pending flags */\n       DMAx->LIFCR = 0x00000F40U;\n    }\n    else if(Stream == LL_DMA_STREAM_2)\n    {\n       /* Reset the Stream2 pending flags */\n       DMAx->LIFCR = 0x003F0000U;\n    }\n    else if(Stream == LL_DMA_STREAM_3)\n    {\n       /* Reset the Stream3 pending flags */\n       DMAx->LIFCR = 0x0F400000U;\n    }\n    else if(Stream == LL_DMA_STREAM_4)\n    {\n       /* Reset the Stream4 pending flags */\n       DMAx->HIFCR = 0x0000003FU;\n    }\n    else if(Stream == LL_DMA_STREAM_5)\n    {\n       /* Reset the Stream5 pending flags */\n       DMAx->HIFCR = 0x00000F40U;\n    }\n    else if(Stream == LL_DMA_STREAM_6)\n    {\n       /* Reset the Stream6 pending flags */\n       DMAx->HIFCR = 0x003F0000U;\n    }\n    else if(Stream == LL_DMA_STREAM_7)\n    {\n       /* Reset the Stream7 pending flags */\n       DMAx->HIFCR = 0x0F400000U;\n    }\n    else\n    {\n      status = ERROR;\n    }\n  }\n\n  return status;\n}\n\n/**\n  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.\n  * @note   To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :\n  *         @arg @ref __LL_DMA_GET_INSTANCE\n  *         @arg @ref __LL_DMA_GET_STREAM\n  * @param  DMAx DMAx Instance\n  * @param  Stream This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_STREAM_0\n  *         @arg @ref LL_DMA_STREAM_1\n  *         @arg @ref LL_DMA_STREAM_2\n  *         @arg @ref LL_DMA_STREAM_3\n  *         @arg @ref LL_DMA_STREAM_4\n  *         @arg @ref LL_DMA_STREAM_5\n  *         @arg @ref LL_DMA_STREAM_6\n  *         @arg @ref LL_DMA_STREAM_7\n  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: DMA registers are initialized\n  *          - ERROR: Not applicable\n  */\nuint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)\n{\n  /* Check the DMA Instance DMAx and Stream parameters*/\n  assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));\n\n  /* Check the DMA parameters from DMA_InitStruct */\n  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));\n  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));\n  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));\n  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));\n  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));\n  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));\n  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));\n  assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));\n  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));\n  assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));\n  /* Check the memory burst, peripheral burst and FIFO threshold parameters only\n     when FIFO mode is enabled */\n  if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)\n  {\n    assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));\n    assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));\n    assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));\n  }\n\n  /*---------------------------- DMAx SxCR Configuration ------------------------\n   * Configure DMAx_Streamy: data transfer direction, data transfer mode,\n   *                          peripheral and memory increment mode,\n   *                          data size alignment and  priority level with parameters :\n   * - Direction:      DMA_SxCR_DIR[1:0] bits\n   * - Mode:           DMA_SxCR_CIRC bit\n   * - PeriphOrM2MSrcIncMode:  DMA_SxCR_PINC bit\n   * - MemoryOrM2MDstIncMode:  DMA_SxCR_MINC bit\n   * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits\n   * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits\n   * - Priority:               DMA_SxCR_PL[1:0] bits\n   */\n  LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \\\n                        DMA_InitStruct->Mode                    | \\\n                        DMA_InitStruct->PeriphOrM2MSrcIncMode   | \\\n                        DMA_InitStruct->MemoryOrM2MDstIncMode   | \\\n                        DMA_InitStruct->PeriphOrM2MSrcDataSize  | \\\n                        DMA_InitStruct->MemoryOrM2MDstDataSize  | \\\n                        DMA_InitStruct->Priority\n                        );\n\n  if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)\n  {\n    /*---------------------------- DMAx SxFCR Configuration ------------------------\n     * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :\n     * - FIFOMode:                DMA_SxFCR_DMDIS bit\n     * - FIFOThreshold:           DMA_SxFCR_FTH[1:0] bits\n     */\n    LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);   \n\n    /*---------------------------- DMAx SxCR Configuration --------------------------\n     * Configure DMAx_Streamy:  memory burst transfer with parameters :\n     * - MemBurst:                DMA_SxCR_MBURST[1:0] bits\n     */\n    LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); \n\n    /*---------------------------- DMAx SxCR Configuration --------------------------\n     * Configure DMAx_Streamy:  peripheral burst transfer with parameters :\n     * - PeriphBurst:             DMA_SxCR_PBURST[1:0] bits\n     */\n    LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);\n  }\n\n  /*-------------------------- DMAx SxM0AR Configuration --------------------------\n   * Configure the memory or destination base address with parameter :\n   * - MemoryOrM2MDstAddress:     DMA_SxM0AR_M0A[31:0] bits\n   */\n  LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);\n\n  /*-------------------------- DMAx SxPAR Configuration ---------------------------\n   * Configure the peripheral or source base address with parameter :\n   * - PeriphOrM2MSrcAddress:     DMA_SxPAR_PA[31:0] bits\n   */\n  LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);\n\n  /*--------------------------- DMAx SxNDTR Configuration -------------------------\n   * Configure the peripheral base address with parameter :\n   * - NbData:                    DMA_SxNDT[15:0] bits\n   */\n  LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);\n\n  /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------\n   * Configure the peripheral base address with parameter :\n   * - PeriphRequest:             DMA_SxCR_CHSEL[2:0] bits\n   */\n  LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);\n\n  return SUCCESS;\n}\n\n/**\n  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.\n  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.\n  * @retval None\n  */\nvoid LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)\n{\n  /* Set DMA_InitStruct fields to default values */\n  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;\n  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;\n  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;\n  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;\n  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;\n  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;\n  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;\n  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;\n  DMA_InitStruct->NbData                 = 0x00000000U;\n  DMA_InitStruct->Channel                = LL_DMA_CHANNEL_0;\n  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;\n  DMA_InitStruct->FIFOMode               = LL_DMA_FIFOMODE_DISABLE;\n  DMA_InitStruct->FIFOThreshold          = LL_DMA_FIFOTHRESHOLD_1_4;\n  DMA_InitStruct->MemBurst               = LL_DMA_MBURST_SINGLE;\n  DMA_InitStruct->PeriphBurst            = LL_DMA_PBURST_SINGLE;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* DMA1 || DMA2 */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_exti.c\n  * @author  MCD Application Team\n  * @brief   EXTI LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_exti.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (EXTI)\n\n/** @defgroup EXTI_LL EXTI\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup EXTI_LL_Private_Macros\n  * @{\n  */\n\n#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)\n\n#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \\\n                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \\\n                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))\n\n\n#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \\\n                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \\\n                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \\\n                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))\n\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup EXTI_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup EXTI_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize the EXTI registers to their default reset values.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: EXTI registers are de-initialized\n  *          - ERROR: not applicable\n  */\nuint32_t LL_EXTI_DeInit(void)\n{\n  /* Interrupt mask register set to default reset values */\n  LL_EXTI_WriteReg(IMR,   0x00000000U);\n  /* Event mask register set to default reset values */\n  LL_EXTI_WriteReg(EMR,   0x00000000U);\n  /* Rising Trigger selection register set to default reset values */\n  LL_EXTI_WriteReg(RTSR,  0x00000000U);\n  /* Falling Trigger selection register set to default reset values */\n  LL_EXTI_WriteReg(FTSR,  0x00000000U);\n  /* Software interrupt event register set to default reset values */\n  LL_EXTI_WriteReg(SWIER, 0x00000000U);\n  /* Pending register set to default reset values */\n  LL_EXTI_WriteReg(PR,    0x00FFFFFFU);\n\n  return SUCCESS;\n}\n\n/**\n  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.\n  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: EXTI registers are initialized\n  *          - ERROR: not applicable\n  */\nuint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  /* Check the parameters */\n  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));\n  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));\n  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));\n\n  /* ENABLE LineCommand */\n  if (EXTI_InitStruct->LineCommand != DISABLE)\n  {\n    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));\n\n    /* Configure EXTI Lines in range from 0 to 31 */\n    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)\n    {\n      switch (EXTI_InitStruct->Mode)\n      {\n        case LL_EXTI_MODE_IT:\n          /* First Disable Event on provided Lines */\n          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);\n          /* Then Enable IT on provided Lines */\n          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);\n          break;\n        case LL_EXTI_MODE_EVENT:\n          /* First Disable IT on provided Lines */\n          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);\n          /* Then Enable Event on provided Lines */\n          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);\n          break;\n        case LL_EXTI_MODE_IT_EVENT:\n          /* Directly Enable IT & Event on provided Lines */\n          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);\n          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);\n          break;\n        default:\n          status = ERROR;\n          break;\n      }\n      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)\n      {\n        switch (EXTI_InitStruct->Trigger)\n        {\n          case LL_EXTI_TRIGGER_RISING:\n            /* First Disable Falling Trigger on provided Lines */\n            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            /* Then Enable Rising Trigger on provided Lines */\n            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            break;\n          case LL_EXTI_TRIGGER_FALLING:\n            /* First Disable Rising Trigger on provided Lines */\n            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            /* Then Enable Falling Trigger on provided Lines */\n            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            break;\n          case LL_EXTI_TRIGGER_RISING_FALLING:\n            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            break;\n          default:\n            status = ERROR;\n            break;\n        }\n      }\n    }\n  }\n  /* DISABLE LineCommand */\n  else\n  {\n    /* De-configure EXTI Lines in range from 0 to 31 */\n    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);\n    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);\n  }\n  return status;\n}\n\n/**\n  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.\n  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.\n  * @retval None\n  */\nvoid LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)\n{\n  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;\n  EXTI_InitStruct->LineCommand    = DISABLE;\n  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;\n  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (EXTI) */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_gpio.c\n  * @author  MCD Application Team\n  * @brief   GPIO LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_gpio.h\"\n#include \"stm32f4xx_ll_bus.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)\n\n/** @addtogroup GPIO_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup GPIO_LL_Private_Macros\n  * @{\n  */\n#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))\n\n#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\\\n                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\\\n                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\\\n                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))\n\n#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\\\n                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))\n\n#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\\\n                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\\\n                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\\\n                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))\n\n#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\\\n                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\\\n                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))\n\n#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_15 ))\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup GPIO_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup GPIO_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize GPIO registers (Registers restored to their default values).\n  * @param  GPIOx GPIO Port\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: GPIO registers are de-initialized\n  *          - ERROR:   Wrong GPIO Port\n  */\nErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\n\n  /* Force and Release reset on clock of GPIOx Port */\n  if (GPIOx == GPIOA)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);\n  }\n  else if (GPIOx == GPIOB)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);\n  }\n  else if (GPIOx == GPIOC)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);\n  }\n#if defined(GPIOD)\n  else if (GPIOx == GPIOD)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);\n  }\n#endif /* GPIOD */\n#if defined(GPIOE)\n  else if (GPIOx == GPIOE)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);\n  }\n#endif /* GPIOE */\n#if defined(GPIOF)\n  else if (GPIOx == GPIOF)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);\n  }\n#endif /* GPIOF */\n#if defined(GPIOG)\n  else if (GPIOx == GPIOG)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);\n  }\n#endif /* GPIOG */\n#if defined(GPIOH)\n  else if (GPIOx == GPIOH)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);\n  }\n#endif /* GPIOH */\n#if defined(GPIOI)\n  else if (GPIOx == GPIOI)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);\n  }\n#endif /* GPIOI */\n#if defined(GPIOJ)\n  else if (GPIOx == GPIOJ)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);\n  }\n#endif /* GPIOJ */\n#if defined(GPIOK)\n  else if (GPIOx == GPIOK)\n  {\n    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK);\n    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);\n  }\n#endif /* GPIOK */\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.\n  * @param  GPIOx GPIO Port\n  * @param  GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure\n  *         that contains the configuration information for the specified GPIO peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content\n  *          - ERROR:   Not applicable\n  */\nErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)\n{\n  uint32_t pinpos     = 0x00000000U;\n  uint32_t currentpin = 0x00000000U;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\n  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));\n  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));\n  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));\n\n  /* ------------------------- Configure the port pins ---------------- */\n  /* Initialize  pinpos on first pin set */\n  pinpos = POSITION_VAL(GPIO_InitStruct->Pin);\n\n  /* Configure the port pins */\n  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)\n  {\n    /* Get current io position */\n    currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);\n\n    if (currentpin)\n    {\n      /* Pin Mode configuration */\n      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);\n\n      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))\n      {\n        /* Check Speed mode parameters */\n        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));\n\n        /* Speed mode configuration */\n        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);\n      }\n\n      /* Pull-up Pull down resistor configuration*/\n      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);\n\n      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)\n      {\n        /* Check Alternate parameter */\n        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));\n\n        /* Speed mode configuration */\n        if (POSITION_VAL(currentpin) < 0x00000008U)\n        {\n          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);\n        }\n        else\n        {\n          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);\n        }\n      }\n    }\n    pinpos++;\n  }\n\n  if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))\n  {\n    /* Check Output mode parameters */\n    assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));\n\n    /* Output mode configuration*/\n    LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);\n\n  }\n  return (SUCCESS);\n}\n\n/**\n  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.\n  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure\n  *                          whose fields will be set to default values.\n  * @retval None\n  */\n\nvoid LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)\n{\n  /* Reset GPIO init structure parameters values */\n  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;\n  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;\n  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;\n  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;\n  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;\n  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_pwr.c\n  * @author  MCD Application Team\n  * @brief   PWR LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_pwr.h\"\n#include \"stm32f4xx_ll_bus.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(PWR)\n\n/** @defgroup PWR_LL PWR\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup PWR_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup PWR_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize the PWR registers to their default reset values.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: PWR registers are de-initialized\n  *          - ERROR: not applicable\n  */\nErrorStatus LL_PWR_DeInit(void)\n{\n  /* Force reset of PWR clock */\n  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);\n\n  /* Release reset of PWR clock */\n  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);\n\n  return SUCCESS;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* defined(PWR) */\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_rcc.c\n  * @author  MCD Application Team\n  * @brief   RCC LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_rcc.h\"\n#ifdef  USE_FULL_ASSERT\n  #include \"stm32_assert.h\"\n#else\n  #define assert_param(expr) ((void)0U)\n#endif\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @addtogroup RCC_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup RCC_LL_Private_Macros\n  * @{\n  */\n#if defined(FMPI2C1)\n#define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)\n#endif /* FMPI2C1 */\n\n#if defined(LPTIM1)\n#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n#if defined(RCC_DCKCFGR_SAI1SRC)\n#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))\n#elif defined(RCC_DCKCFGR_SAI1ASRC)\n#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))\n#endif /* RCC_DCKCFGR_SAI1SRC */\n#endif /* SAI1 */\n\n#if defined(SDIO)\n#define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))\n#endif /* SDIO */\n\n#if defined(RNG)\n#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))\n#endif /* RNG */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))\n#endif /* USB_OTG_FS || USB_OTG_HS */\n\n#if defined(DFSDM2_Channel0)\n#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))\n\n#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \\\n                                                    || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))\n#elif defined(DFSDM1_Channel0)\n#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))\n\n#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))\n#endif /* DFSDM2_Channel0 */\n\n#if defined(RCC_DCKCFGR_I2S2SRC)\n#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))\n#else\n#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))\n#endif /* RCC_DCKCFGR_I2S2SRC */\n\n#if defined(CEC)\n#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))\n#endif /* CEC */\n\n#if defined(DSI)\n#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))\n#endif /* DSI */\n\n#if defined(LTDC)\n#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))\n#endif /* LTDC */\n\n#if defined(SPDIFRX)\n#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))\n#endif /* SPDIFRX */\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n/** @defgroup RCC_LL_Private_Functions RCC Private functions\n  * @{\n  */\nuint32_t RCC_GetSystemClockFreq(void);\nuint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);\nuint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);\nuint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);\nuint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);\nuint32_t RCC_PLL_GetFreqDomain_48M(void);\n#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)\nuint32_t RCC_PLL_GetFreqDomain_I2S(void);\n#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */\n#if defined(SPDIFRX)\nuint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);\n#endif /* SPDIFRX */\n#if defined(RCC_PLLCFGR_PLLR)\n#if defined(SAI1)\nuint32_t RCC_PLL_GetFreqDomain_SAI(void);\n#endif /* SAI1 */\n#endif /* RCC_PLLCFGR_PLLR */\n#if defined(DSI)\nuint32_t RCC_PLL_GetFreqDomain_DSI(void);\n#endif /* DSI */\n#if defined(RCC_PLLSAI_SUPPORT)\nuint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\nuint32_t RCC_PLLSAI_GetFreqDomain_48M(void);\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n#if defined(LTDC)\nuint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);\n#endif /* LTDC */\n#endif /* RCC_PLLSAI_SUPPORT */\n#if defined(RCC_PLLI2S_SUPPORT)\nuint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\nuint32_t RCC_PLLI2S_GetFreqDomain_48M(void);\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n#if defined(SAI1)\nuint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);\n#endif /* SAI1 */\n#if defined(SPDIFRX)\nuint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);\n#endif /* SPDIFRX */\n#endif /* RCC_PLLI2S_SUPPORT */\n/**\n  * @}\n  */\n\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup RCC_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup RCC_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  Reset the RCC clock configuration to the default reset state.\n  * @note   The default reset state of the clock configuration is given below:\n  *         - HSI ON and used as system clock source\n  *         - HSE and PLL OFF\n  *         - AHB, APB1 and APB2 prescaler set to 1.\n  *         - CSS, MCO OFF\n  *         - All interrupts disabled\n  * @note   This function doesn't modify the configuration of the\n  *         - Peripheral clocks\n  *         - LSI, LSE and RTC clocks\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: RCC registers are de-initialized\n  *          - ERROR: not applicable\n  */\nErrorStatus LL_RCC_DeInit(void)\n{\n  uint32_t vl_mask = 0U;\n\n  /* Set HSION bit */\n  LL_RCC_HSI_Enable();\n\n  /* Wait for HSI READY bit */\n  while(LL_RCC_HSI_IsReady() != 1U)\n  {}\n\n  /* Reset CFGR register */\n  LL_RCC_WriteReg(CFGR, 0x00000000U);\n\n  vl_mask = 0xFFFFFFFFU;\n\n  /* Reset HSEON, PLLSYSON bits */\n  CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));\n\n#if defined(RCC_PLLSAI_SUPPORT)\n  /* Reset PLLSAION bit */\n  CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);\n#endif /* RCC_PLLSAI_SUPPORT */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n  /* Reset PLLI2SON bit */\n  CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);\n#endif /* RCC_PLLI2S_SUPPORT */\n\n  /* Write new mask in CR register */\n  LL_RCC_WriteReg(CR, vl_mask);\n\n  /* Set HSITRIM bits to the reset value*/\n  LL_RCC_HSI_SetCalibTrimming(0x10U);\n\n  /* Wait for PLL READY bit to be reset */\n  while(LL_RCC_PLL_IsReady() != 0U)\n  {}\n\n  /* Reset PLLCFGR register */\n  LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);\n\n#if defined(RCC_PLLI2S_SUPPORT)\n  /* Reset PLLI2SCFGR register */\n  LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n  /* Reset PLLSAICFGR register */\n  LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);\n#endif /* RCC_PLLSAI_SUPPORT */\n\n  /* Disable all interrupts */\n  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);\n\n#if defined(RCC_CIR_PLLI2SRDYIE)\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);\n#endif /* RCC_CIR_PLLI2SRDYIE */\n\n#if defined(RCC_CIR_PLLSAIRDYIE)\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);\n#endif /* RCC_CIR_PLLSAIRDYIE */\n\n  /* Clear all interrupt flags */\n  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);\n\n#if defined(RCC_CIR_PLLI2SRDYC)\n  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);\n#endif /* RCC_CIR_PLLI2SRDYC */\n\n#if defined(RCC_CIR_PLLSAIRDYC)\n  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);\n#endif /* RCC_CIR_PLLSAIRDYC */\n\n  /* Clear LSION bit */\n  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);\n\n  /* Reset all CSR flags */\n  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\n\n  return SUCCESS;\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup RCC_LL_EF_Get_Freq\n  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks\n  *         and different peripheral clocks available on the device.\n  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)\n  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)\n  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)\n  *         or HSI_VALUE(**) multiplied/divided by the PLL factors.\n  * @note   (**) HSI_VALUE is a constant defined in this file (default value\n  *              16 MHz) but the real value may vary depending on the variations\n  *              in voltage and temperature.\n  * @note   (***) HSE_VALUE is a constant defined in this file (default value\n  *               25 MHz), user has to ensure that HSE_VALUE is same as the real\n  *               frequency of the crystal used. Otherwise, this function may\n  *               have wrong result.\n  * @note   The result of this function could be incorrect when using fractional\n  *         value for HSE crystal.\n  * @note   This function can be used by the user application to compute the\n  *         baud-rate for the communication peripherals or configure other parameters.\n  * @{\n  */\n\n/**\n  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks\n  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function\n  *         must be called to update structure fields. Otherwise, any\n  *         configuration based on this function will be incorrect.\n  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies\n  * @retval None\n  */\nvoid LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)\n{\n  /* Get SYSCLK frequency */\n  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();\n\n  /* HCLK clock frequency */\n  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);\n\n  /* PCLK1 clock frequency */\n  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);\n\n  /* PCLK2 clock frequency */\n  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);\n}\n\n#if defined(FMPI2C1)\n/**\n  * @brief  Return FMPI2Cx clock frequency\n  * @param  FMPI2CxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE\n  * @retval FMPI2C clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready\n  */\nuint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)\n{\n  uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));\n\n  if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)\n  {\n    /* FMPI2C1 CLK clock frequency */\n    switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))\n    {\n      case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */\n        FMPI2C_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_FMPI2C1_CLKSOURCE_HSI:    /* FMPI2C1 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          FMPI2C_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1:  /* FMPI2C1 Clock is PCLK1 */\n      default:\n        FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n\n  return FMPI2C_frequency;\n}\n#endif /* FMPI2C1 */\n\n/**\n  * @brief  Return I2Sx clock frequency\n  * @param  I2SxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2S1_CLKSOURCE\n  *         @arg @ref LL_RCC_I2S2_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval I2S clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)\n{\n  uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));\n\n  if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)\n  {\n    /* I2S1 CLK clock frequency */\n    switch (LL_RCC_GetI2SClockSource(I2SxSource))\n    {\n#if defined(RCC_PLLI2S_SUPPORT)\n      case LL_RCC_I2S1_CLKSOURCE_PLLI2S:       /* I2S1 Clock is PLLI2S */\n        if (LL_RCC_PLLI2S_IsReady())\n        {\n          i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();\n        }\n        break;\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)\n      case LL_RCC_I2S1_CLKSOURCE_PLL:          /* I2S1 Clock is PLL */\n        if (LL_RCC_PLL_IsReady())\n        {\n          i2s_frequency = RCC_PLL_GetFreqDomain_I2S();\n        }\n        break;\n\n      case LL_RCC_I2S1_CLKSOURCE_PLLSRC:       /* I2S1 Clock is PLL Main source */\n        switch (LL_RCC_PLL_GetMainSource())\n        {\n           case LL_RCC_PLLSOURCE_HSE:          /* I2S1 Clock is HSE Osc. */\n             if (LL_RCC_HSE_IsReady())\n             {\n               i2s_frequency = HSE_VALUE;\n             }\n             break;\n\n           case LL_RCC_PLLSOURCE_HSI:          /* I2S1 Clock is HSI Osc. */\n           default:\n             if (LL_RCC_HSI_IsReady())\n             {\n               i2s_frequency = HSI_VALUE;\n             }\n             break;\n        }\n        break;\n#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */\n\n      case LL_RCC_I2S1_CLKSOURCE_PIN:          /* I2S1 Clock is External clock */\n      default:\n        i2s_frequency = EXTERNAL_CLOCK_VALUE;\n        break;\n    }\n  }\n#if defined(RCC_DCKCFGR_I2S2SRC)\n  else\n  {\n    /* I2S2 CLK clock frequency */\n    switch (LL_RCC_GetI2SClockSource(I2SxSource))\n    {\n      case LL_RCC_I2S2_CLKSOURCE_PLLI2S:       /* I2S2 Clock is PLLI2S */\n        if (LL_RCC_PLLI2S_IsReady())\n        {\n          i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();\n        }\n        break;\n\n      case LL_RCC_I2S2_CLKSOURCE_PLL:          /* I2S2 Clock is PLL */\n        if (LL_RCC_PLL_IsReady())\n        {\n          i2s_frequency = RCC_PLL_GetFreqDomain_I2S();\n        }\n        break;\n\n      case LL_RCC_I2S2_CLKSOURCE_PLLSRC:       /* I2S2 Clock is PLL Main source */\n        switch (LL_RCC_PLL_GetMainSource())\n        {\n           case LL_RCC_PLLSOURCE_HSE:          /* I2S2 Clock is HSE Osc. */\n             if (LL_RCC_HSE_IsReady())\n             {\n               i2s_frequency = HSE_VALUE;\n             }\n             break;\n\n           case LL_RCC_PLLSOURCE_HSI:          /* I2S2 Clock is HSI Osc. */\n           default:\n             if (LL_RCC_HSI_IsReady())\n             {\n               i2s_frequency = HSI_VALUE;\n             }\n             break;\n        }\n        break;\n\n      case LL_RCC_I2S2_CLKSOURCE_PIN:          /* I2S2 Clock is External clock */\n      default:\n        i2s_frequency = EXTERNAL_CLOCK_VALUE;\n        break;\n    } \n  }\n#endif /* RCC_DCKCFGR_I2S2SRC */\n\n  return i2s_frequency;\n}\n\n#if defined(LPTIM1)\n/**\n  * @brief  Return LPTIMx clock frequency\n  * @param  LPTIMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE\n  * @retval LPTIM clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready\n  */\nuint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)\n{\n  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));\n\n  if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)\n  {\n    /* LPTIM1CLK clock frequency */\n    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))\n    {\n      case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */\n        if (LL_RCC_LSI_IsReady())\n        {\n          lptim_frequency = LSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          lptim_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */\n        if (LL_RCC_LSE_IsReady())\n        {\n          lptim_frequency = LSE_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */\n      default:\n        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n\n  return lptim_frequency;\n}\n#endif /* LPTIM1 */\n\n#if defined(SAI1)\n/**\n  * @brief  Return SAIx clock frequency\n  * @param  SAIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval SAI clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)\n{\n  uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));\n\n#if defined(RCC_DCKCFGR_SAI1SRC)\n  if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))\n  {\n    /* SAI1CLK clock frequency */\n    switch (LL_RCC_GetSAIClockSource(SAIxSource))\n    {\n      case LL_RCC_SAI1_CLKSOURCE_PLLSAI:     /* PLLSAI clock used as SAI1 clock source */\n      case LL_RCC_SAI2_CLKSOURCE_PLLSAI:     /* PLLSAI clock used as SAI2 clock source */\n        if (LL_RCC_PLLSAI_IsReady())\n        {\n          sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI1_CLKSOURCE_PLLI2S:     /* PLLI2S clock used as SAI1 clock source */\n      case LL_RCC_SAI2_CLKSOURCE_PLLI2S:     /* PLLI2S clock used as SAI2 clock source */\n        if (LL_RCC_PLLI2S_IsReady())\n        {\n          sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */\n      case LL_RCC_SAI2_CLKSOURCE_PLL:        /* PLL clock used as SAI2 clock source */\n        if (LL_RCC_PLL_IsReady())\n        {\n          sai_frequency = RCC_PLL_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI2_CLKSOURCE_PLLSRC:\n        switch (LL_RCC_PLL_GetMainSource())\n        {\n           case LL_RCC_PLLSOURCE_HSE:        /* HSE clock used as SAI2 clock source */\n             if (LL_RCC_HSE_IsReady())\n             {\n               sai_frequency = HSE_VALUE;\n             }\n             break;\n\n           case LL_RCC_PLLSOURCE_HSI:        /* HSI clock used as SAI2 clock source */\n           default:\n             if (LL_RCC_HSI_IsReady())\n             {\n               sai_frequency = HSI_VALUE;\n             }\n             break;\n        }\n        break;\n\n      case LL_RCC_SAI1_CLKSOURCE_PIN:        /* External input clock used as SAI1 clock source */\n      default:\n        sai_frequency = EXTERNAL_CLOCK_VALUE;\n        break;\n    }\n  }\n#endif /* RCC_DCKCFGR_SAI1SRC */\n#if defined(RCC_DCKCFGR_SAI1ASRC)\n  if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))\n  {\n    /* SAI1CLK clock frequency */\n    switch (LL_RCC_GetSAIClockSource(SAIxSource))\n    {\n#if defined(RCC_PLLSAI_SUPPORT)\n      case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI:     /* PLLSAI clock used as SAI1 Block A clock source */\n      case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI:     /* PLLSAI clock used as SAI1 Block B clock source */\n        if (LL_RCC_PLLSAI_IsReady())\n        {\n          sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();\n        }\n        break;\n#endif /* RCC_PLLSAI_SUPPORT */\n\n      case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S:     /* PLLI2S clock used as SAI1 Block A clock source */\n      case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S:     /* PLLI2S clock used as SAI1 Block B clock source */\n        if (LL_RCC_PLLI2S_IsReady())\n        {\n          sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();\n        }\n        break;\n\n#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)\n      case LL_RCC_SAI1_A_CLKSOURCE_PLL:        /* PLL clock used as SAI1 Block A clock source */\n      case LL_RCC_SAI1_B_CLKSOURCE_PLL:        /* PLL clock used as SAI1 Block B clock source */\n        if (LL_RCC_PLL_IsReady())\n        {\n          sai_frequency = RCC_PLL_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:\n      case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:\n        switch (LL_RCC_PLL_GetMainSource())\n        {\n           case LL_RCC_PLLSOURCE_HSE:          /* HSE clock used as SAI1 Block A or B clock source */\n             if (LL_RCC_HSE_IsReady())\n             {\n               sai_frequency = HSE_VALUE;\n             }\n             break;\n\n           case LL_RCC_PLLSOURCE_HSI:          /* HSI clock used as SAI1 Block A or B clock source */\n           default:\n             if (LL_RCC_HSI_IsReady())\n             {\n               sai_frequency = HSI_VALUE;\n             }\n             break;\n        }\n        break;\n#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */\n\n      case LL_RCC_SAI1_A_CLKSOURCE_PIN:        /* External input clock used as SAI1 Block A clock source */\n      case LL_RCC_SAI1_B_CLKSOURCE_PIN:        /* External input clock used as SAI1 Block B clock source */\n      default:\n        sai_frequency = EXTERNAL_CLOCK_VALUE;\n        break;\n    }\n  }\n#endif /* RCC_DCKCFGR_SAI1ASRC */\n\n  return sai_frequency;\n}\n#endif /* SAI1 */\n\n#if defined(SDIO)\n/**\n  * @brief  Return SDIOx clock frequency\n  * @param  SDIOxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDIO_CLKSOURCE\n  * @retval SDIO clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)\n{\n  uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));\n\n  if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)\n  {\n#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)\n    /* SDIOCLK clock frequency */\n    switch (LL_RCC_GetSDIOClockSource(SDIOxSource))\n    {\n      case LL_RCC_SDIO_CLKSOURCE_PLL48CLK:         /* PLL48M clock used as SDIO clock source */\n        switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))\n        {\n          case LL_RCC_CK48M_CLKSOURCE_PLL:         /* PLL clock used as 48Mhz domain clock */\n            if (LL_RCC_PLL_IsReady())\n            {\n              SDIO_frequency = RCC_PLL_GetFreqDomain_48M();\n            }\n          break;\n\n#if defined(RCC_PLLSAI_SUPPORT)\n          case LL_RCC_CK48M_CLKSOURCE_PLLSAI:      /* PLLSAI clock used as 48Mhz domain clock */\n          default:\n            if (LL_RCC_PLLSAI_IsReady())\n            {\n              SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();\n            }\n            break;\n#endif /* RCC_PLLSAI_SUPPORT */\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n          case LL_RCC_CK48M_CLKSOURCE_PLLI2S:      /* PLLI2S clock used as 48Mhz domain clock */\n          default:\n            if (LL_RCC_PLLI2S_IsReady())\n            {\n              SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();\n            }\n            break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n        }\n        break;\n\n      case LL_RCC_SDIO_CLKSOURCE_SYSCLK:           /* PLL clock used as SDIO clock source */\n      default:\n      SDIO_frequency = RCC_GetSystemClockFreq();\n      break;\n    }\n#else\n    /* PLL clock used as 48Mhz domain clock */\n    if (LL_RCC_PLL_IsReady())\n    {\n      SDIO_frequency = RCC_PLL_GetFreqDomain_48M();\n    }\n#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */\n  }\n\n  return SDIO_frequency;\n}\n#endif /* SDIO */\n\n#if defined(RNG)\n/**\n  * @brief  Return RNGx clock frequency\n  * @param  RNGxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE\n  * @retval RNG clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)\n{\n  uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n  /* RNGCLK clock frequency */\n  switch (LL_RCC_GetRNGClockSource(RNGxSource))\n  {\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n    case LL_RCC_RNG_CLKSOURCE_PLLI2S:        /* PLLI2S clock used as RNG clock source */\n      if (LL_RCC_PLLI2S_IsReady())\n      {\n        rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();\n      }\n      break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n    case LL_RCC_RNG_CLKSOURCE_PLLSAI:        /* PLLSAI clock used as RNG clock source */\n      if (LL_RCC_PLLSAI_IsReady())\n      {\n        rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();\n      }\n      break;\n#endif /* RCC_PLLSAI_SUPPORT */\n\n    case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */\n    default:\n      if (LL_RCC_PLL_IsReady())\n      {\n        rng_frequency = RCC_PLL_GetFreqDomain_48M();\n      }\n      break;\n  }\n#else\n  /* PLL clock used as RNG clock source */\n  if (LL_RCC_PLL_IsReady())\n  {\n    rng_frequency = RCC_PLL_GetFreqDomain_48M();\n  }\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n  return rng_frequency;\n}\n#endif /* RNG */\n\n#if defined(CEC)\n/**\n  * @brief  Return CEC clock frequency\n  * @param  CECxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_CEC_CLKSOURCE\n  * @retval CEC clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready\n  */\nuint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)\n{\n  uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));\n\n  /* CECCLK clock frequency */\n  switch (LL_RCC_GetCECClockSource(CECxSource))\n  {\n    case LL_RCC_CEC_CLKSOURCE_LSE:           /* CEC Clock is LSE Osc. */\n      if (LL_RCC_LSE_IsReady())\n      {\n        cec_frequency = LSE_VALUE;\n      }\n      break;\n\n    case LL_RCC_CEC_CLKSOURCE_HSI_DIV488:    /* CEC Clock is HSI Osc. */\n    default:\n      if (LL_RCC_HSI_IsReady())\n      {\n        cec_frequency = HSI_VALUE/488U;\n      }\n      break;\n  }\n\n  return cec_frequency;\n}\n#endif /* CEC */\n\n#if defined(USB_OTG_FS) || defined(USB_OTG_HS)\n/**\n  * @brief  Return USBx clock frequency\n  * @param  USBxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE\n  * @retval USB clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)\n{\n  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));\n\n#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)\n  /* USBCLK clock frequency */\n  switch (LL_RCC_GetUSBClockSource(USBxSource))\n  {\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n    case LL_RCC_USB_CLKSOURCE_PLLI2S:       /* PLLI2S clock used as USB clock source */\n      if (LL_RCC_PLLI2S_IsReady())\n      {\n        usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();\n      }\n      break;\n\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n    case LL_RCC_USB_CLKSOURCE_PLLSAI:       /* PLLSAI clock used as USB clock source */\n      if (LL_RCC_PLLSAI_IsReady())\n      {\n        usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();\n      }\n      break;\n#endif /* RCC_PLLSAI_SUPPORT */\n\n    case LL_RCC_USB_CLKSOURCE_PLL:          /* PLL clock used as USB clock source */\n    default:\n      if (LL_RCC_PLL_IsReady())\n      {\n        usb_frequency = RCC_PLL_GetFreqDomain_48M();\n      }\n      break;\n  }\n#else\n  /* PLL clock used as USB clock source */\n  if (LL_RCC_PLL_IsReady())\n  {\n    usb_frequency = RCC_PLL_GetFreqDomain_48M();\n  }\n#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */\n\n  return usb_frequency;\n}\n#endif /* USB_OTG_FS || USB_OTG_HS */\n\n#if defined(DFSDM1_Channel0)\n/**\n  * @brief  Return DFSDMx clock frequency\n  * @param  DFSDMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE\n  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval DFSDM clock frequency (in Hz)\n  */\nuint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)\n{\n  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));\n\n  if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)\n  {\n    /* DFSDM1CLK clock frequency */\n    switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))\n    {\n      case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:      /* DFSDM1 Clock is SYSCLK */\n        dfsdm_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:       /* DFSDM1 Clock is PCLK2 */\n      default:\n        dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n#if defined(DFSDM2_Channel0)\n  else\n  {\n    /* DFSDM2CLK clock frequency */\n    switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))\n    {\n      case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK:      /* DFSDM2 Clock is SYSCLK */\n        dfsdm_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_DFSDM2_CLKSOURCE_PCLK2:       /* DFSDM2 Clock is PCLK2 */\n      default:\n        dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n#endif /* DFSDM2_Channel0 */\n\n  return dfsdm_frequency;\n}\n\n/**\n  * @brief  Return DFSDMx Audio clock frequency\n  * @param  DFSDMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE\n  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval DFSDM clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)\n{\n  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));\n\n  if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)\n  {\n    /* DFSDM1CLK clock frequency */\n    switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))\n    {\n      case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1:     /* I2S1 clock used as DFSDM1 clock */\n        dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);\n        break;\n\n      case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2:     /* I2S2 clock used as DFSDM1 clock */\n      default:\n        dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);\n        break;\n    }\n  }\n#if defined(DFSDM2_Channel0)\n  else\n  {\n    /* DFSDM2CLK clock frequency */\n    switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))\n    {\n      case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1:     /* I2S1 clock used as DFSDM2 clock */\n        dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);\n        break;\n\n      case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2:     /* I2S2 clock used as DFSDM2 clock */\n      default:\n        dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);\n        break;\n    }\n  }\n#endif /* DFSDM2_Channel0 */\n\n  return dfsdm_frequency;\n}\n#endif /* DFSDM1_Channel0 */\n\n#if defined(DSI)\n/**\n  * @brief  Return DSI clock frequency\n  * @param  DSIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE\n  * @retval DSI clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used\n  */\nuint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)\n{\n  uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));\n\n  /* DSICLK clock frequency */\n  switch (LL_RCC_GetDSIClockSource(DSIxSource))\n  {\n    case LL_RCC_DSI_CLKSOURCE_PLL:     /* DSI Clock is PLL Osc. */\n      if (LL_RCC_PLL_IsReady())\n      {\n        dsi_frequency = RCC_PLL_GetFreqDomain_DSI();\n      }\n      break;\n\n    case LL_RCC_DSI_CLKSOURCE_PHY:    /* DSI Clock is DSI physical clock. */\n    default:\n      dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n      break;\n  }\n\n  return dsi_frequency;\n}\n#endif /* DSI */\n\n#if defined(LTDC)\n/**\n  * @brief  Return LTDC clock frequency\n  * @param  LTDCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE\n  * @retval LTDC clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready\n  */\nuint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)\n{\n  uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));\n\n  if (LL_RCC_PLLSAI_IsReady())\n  {\n     ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();\n  }\n\n  return ltdc_frequency;\n}\n#endif /* LTDC */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Return SPDIFRX clock frequency\n  * @param  SPDIFRXxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE\n  * @retval SPDIFRX clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)\n{\n  uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));\n\n  /* SPDIFRX1CLK clock frequency */\n  switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))\n  {\n    case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S:  /* SPDIFRX Clock is PLLI2S Osc. */\n      if (LL_RCC_PLLI2S_IsReady())\n      {\n        spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();\n      }\n      break;\n\n    case LL_RCC_SPDIFRX1_CLKSOURCE_PLL:     /* SPDIFRX Clock is PLL Osc. */\n    default:\n      if (LL_RCC_PLL_IsReady())\n      {\n        spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();\n      }\n      break;\n  }\n\n  return spdifrx_frequency;\n}\n#endif /* SPDIFRX */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup RCC_LL_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Return SYSTEM clock frequency\n  * @retval SYSTEM clock frequency (in Hz)\n  */\nuint32_t RCC_GetSystemClockFreq(void)\n{\n  uint32_t frequency = 0U;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  switch (LL_RCC_GetSysClkSource())\n  {\n    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */\n      frequency = HSI_VALUE;\n      break;\n\n    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */\n      frequency = HSE_VALUE;\n      break;\n\n    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */\n      frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);\n      break;\n\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n    case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock  source */\n      frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);\n      break;\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n\n    default:\n      frequency = HSI_VALUE;\n      break;\n  }\n\n  return frequency;\n}\n\n/**\n  * @brief  Return HCLK clock frequency\n  * @param  SYSCLK_Frequency SYSCLK clock frequency\n  * @retval HCLK clock frequency (in Hz)\n  */\nuint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)\n{\n  /* HCLK clock frequency */\n  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());\n}\n\n/**\n  * @brief  Return PCLK1 clock frequency\n  * @param  HCLK_Frequency HCLK clock frequency\n  * @retval PCLK1 clock frequency (in Hz)\n  */\nuint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)\n{\n  /* PCLK1 clock frequency */\n  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());\n}\n\n/**\n  * @brief  Return PCLK2 clock frequency\n  * @param  HCLK_Frequency HCLK clock frequency\n  * @retval PCLK2 clock frequency (in Hz)\n  */\nuint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)\n{\n  /* PCLK2 clock frequency */\n  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());\n}\n\n/**\n  * @brief  Return PLL clock frequency used for system domain\n  * @param  SYSCLK_Source System clock source\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     SYSCLK = PLL_VCO / (PLLP or PLLR)\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n\n  if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)\n  {\n    plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());\n  }\n#if defined(RCC_PLLR_SYSCLK_SUPPORT)\n  else\n  {\n    plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n  }\n#endif /* RCC_PLLR_SYSCLK_SUPPORT */\n\n  return plloutputfreq;\n}\n\n/**\n  * @brief  Return PLL clock frequency used for 48 MHz domain\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_48M(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN\n     48M Domain clock = PLL_VCO / PLLQ\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());\n}\n\n#if defined(DSI)\n/**\n  * @brief  Return PLL clock frequency used for DSI clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_DSI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     DSICLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n}\n#endif /* DSI */\n\n#if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)\n/**\n  * @brief  Return PLL clock frequency used for I2S clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_I2S(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     I2SCLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n}\n#endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Return PLL clock frequency used for SPDIFRX clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     SPDIFRXCLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n}\n#endif /* SPDIFRX */\n\n#if defined(RCC_PLLCFGR_PLLR)\n#if defined(SAI1)\n/**\n  * @brief  Return PLL clock frequency used for SAI clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_SAI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n     SAICLK = (PLL_VCO / PLLR) / PLLDIVR\n     or\n     SAICLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n\n#if defined(RCC_DCKCFGR_PLLDIVR)\n  plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());\n#else\n  plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n#endif /* RCC_DCKCFGR_PLLDIVR */\n\n  return plloutputfreq;\n}\n#endif /* SAI1 */\n#endif /* RCC_PLLCFGR_PLLR */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Return PLLSAI clock frequency used for SAI domain\n  * @retval PLLSAI clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN\n     SAI domain clock  = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),\n                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());\n}\n\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n/**\n  * @brief  Return PLLSAI clock frequency used for 48Mhz domain\n  * @retval PLLSAI clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI_GetFreqDomain_48M(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN\n     48M Domain clock  = PLLSAI_VCO / PLLSAIP\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),\n                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());\n}\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n\n#if defined(LTDC)\n/**\n  * @brief  Return PLLSAI clock frequency used for LTDC domain\n  * @retval PLLSAI clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN\n     LTDC Domain clock  = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),\n                                        LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());\n}\n#endif /* LTDC */\n#endif /* RCC_PLLSAI_SUPPORT */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n#if defined(SAI1)\n/**\n  * @brief  Return PLLI2S clock frequency used for SAI domains\n  * @retval PLLI2S clock frequency (in Hz)\n  */\nuint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)\n{\n  uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;\n\n  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN\n     SAI domain clock  = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ\n     or\n     SAI domain clock  = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR\n  */\n  plli2ssource = LL_RCC_PLLI2S_GetMainSource();\n\n  switch (plli2ssource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:     /* HSE used as PLLI2S clock source */\n      plli2sinputfreq = HSE_VALUE;\n      break;\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n    case LL_RCC_PLLI2SSOURCE_PIN:  /* External pin input clock used as PLLI2S clock source */\n      plli2sinputfreq = EXTERNAL_CLOCK_VALUE;\n      break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n\n    case LL_RCC_PLLSOURCE_HSI:     /* HSI used as PLLI2S clock source */\n    default:\n      plli2sinputfreq = HSI_VALUE;\n      break;\n  }\n\n#if defined(RCC_DCKCFGR_PLLI2SDIVQ)\n  plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                          LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());\n#else\n  plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                          LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());\n#endif /* RCC_DCKCFGR_PLLI2SDIVQ */\n\n  return plli2soutputfreq;\n}\n#endif /* SAI1 */\n\n#if defined(SPDIFRX)\n/**\n  * @brief  Return PLLI2S clock frequency used for SPDIFRX domain\n  * @retval PLLI2S clock frequency (in Hz)\n  */\nuint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN\n     SPDIFRX Domain clock  = PLLI2S_VCO / PLLI2SP\n  */\n  pllsource = LL_RCC_PLLI2S_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLI2S clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLI2S clock source */\n    default:\n      pllinputfreq = HSI_VALUE;\n      break;\n  }\n\n  return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                           LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());\n}\n#endif /* SPDIFRX */\n\n/**\n  * @brief  Return PLLI2S clock frequency used for I2S domain\n  * @retval PLLI2S clock frequency (in Hz)\n  */\nuint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)\n{\n  uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;\n\n  /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN\n     I2S Domain clock  = PLLI2S_VCO / PLLI2SR\n  */\n  plli2ssource = LL_RCC_PLLI2S_GetMainSource();\n\n  switch (plli2ssource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:     /* HSE used as PLLI2S clock source */\n      plli2sinputfreq = HSE_VALUE;\n      break;\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n    case LL_RCC_PLLI2SSOURCE_PIN:  /* External pin input clock used as PLLI2S clock source */\n      plli2sinputfreq = EXTERNAL_CLOCK_VALUE;\n      break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n\n    case LL_RCC_PLLSOURCE_HSI:     /* HSI used as PLLI2S clock source */\n    default:\n      plli2sinputfreq = HSI_VALUE;\n      break;\n  }\n\n  plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                                   LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());\n\n  return plli2soutputfreq;\n}\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)\n/**\n  * @brief  Return PLLI2S clock frequency used for 48Mhz domain\n  * @retval PLLI2S clock frequency (in Hz)\n  */\nuint32_t RCC_PLLI2S_GetFreqDomain_48M(void)\n{\n  uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;\n\n  /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN\n     48M Domain clock  = PLLI2S_VCO / PLLI2SQ\n  */\n  plli2ssource = LL_RCC_PLLI2S_GetMainSource();\n\n  switch (plli2ssource)\n  {\n    case LL_RCC_PLLSOURCE_HSE:     /* HSE used as PLLI2S clock source */\n      plli2sinputfreq = HSE_VALUE;\n      break;\n\n#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)\n    case LL_RCC_PLLI2SSOURCE_PIN:  /* External pin input clock used as PLLI2S clock source */\n      plli2sinputfreq = EXTERNAL_CLOCK_VALUE;\n      break;\n#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */\n\n    case LL_RCC_PLLSOURCE_HSI:     /* HSI used as PLLI2S clock source */\n    default:\n      plli2sinputfreq = HSI_VALUE;\n      break;\n  }\n\n  plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),\n                                                   LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());\n\n  return plli2soutputfreq;\n}\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */\n#endif /* RCC_PLLI2S_SUPPORT */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_usart.c\n  * @author  MCD Application Team\n  * @brief   USART LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_usart.h\"\n#include \"stm32f4xx_ll_rcc.h\"\n#include \"stm32f4xx_ll_bus.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)\n\n/** @addtogroup USART_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @addtogroup USART_LL_Private_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup USART_LL_Private_Macros\n  * @{\n  */\n\n/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available\n *              divided by the smallest oversampling used on the USART (i.e. 8)    */\n#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)\n\n/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */\n#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)\n\n/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */\n#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)\n\n#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))\n\n#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \\\n                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \\\n                                    || ((__VALUE__) == LL_USART_PARITY_ODD))\n\n#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \\\n                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))\n\n#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \\\n                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))\n\n#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \\\n                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))\n\n#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \\\n                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))\n\n#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \\\n                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))\n\n#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \\\n                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))\n\n#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_2))\n\n#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))\n\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup USART_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup USART_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize USART registers (Registers restored to their default values).\n  * @param  USARTx USART Instance\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers are de-initialized\n  *          - ERROR: USART registers are not de-initialized\n  */\nErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n\n  if (USARTx == USART1)\n  {\n    /* Force reset of USART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);\n\n    /* Release reset of USART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);\n  }\n  else if (USARTx == USART2)\n  {\n    /* Force reset of USART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);\n\n    /* Release reset of USART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);\n  }\n#if defined(USART3)\n  else if (USARTx == USART3)\n  {\n    /* Force reset of USART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);\n\n    /* Release reset of USART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);\n  }\n#endif /* USART3 */\n#if defined(USART6)\n  else if (USARTx == USART6)\n  {\n    /* Force reset of USART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);\n\n    /* Release reset of USART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);\n  }\n#endif /* USART6 */\n#if defined(UART4)\n  else if (USARTx == UART4)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);\n  }\n#endif /* UART4 */\n#if defined(UART5)\n  else if (USARTx == UART5)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);\n  }\n#endif /* UART5 */\n#if defined(UART7)\n  else if (USARTx == UART7)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);\n  }\n#endif /* UART7 */\n#if defined(UART8)\n  else if (USARTx == UART8)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);\n  }\n#endif /* UART8 */\n#if defined(UART9)\n  else if (USARTx == UART9)\n  {\n    /* Force reset of UART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);\n\n    /* Release reset of UART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);\n  }\n#endif /* UART9 */\n#if defined(UART10)\n  else if (USARTx == UART10)\n  {\n    /* Force reset of UART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART10);\n\n    /* Release reset of UART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART10);\n  }\n#endif /* UART10 */\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief  Initialize USART registers according to the specified\n  *         parameters in USART_InitStruct.\n  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),\n  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.\n  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).\n  * @param  USARTx USART Instance\n  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure\n  *         that contains the configuration information for the specified USART peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content\n  *          - ERROR: Problem occurred during USART Registers initialization\n  */\nErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)\n{\n  ErrorStatus status = ERROR;\n  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;\n  LL_RCC_ClocksTypeDef rcc_clocks;\n\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));\n  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));\n  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));\n  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));\n  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));\n  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));\n  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));\n\n  /* USART needs to be in disabled state, in order to be able to configure some bits in\n     CRx registers */\n  if (LL_USART_IsEnabled(USARTx) == 0U)\n  {\n    /*---------------------------- USART CR1 Configuration -----------------------\n     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:\n     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value\n     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value\n     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value\n     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.\n     */\n    MODIFY_REG(USARTx->CR1,\n               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |\n                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),\n               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |\n                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));\n\n    /*---------------------------- USART CR2 Configuration -----------------------\n     * Configure USARTx CR2 (Stop bits) with parameters:\n     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.\n     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().\n     */\n    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);\n\n    /*---------------------------- USART CR3 Configuration -----------------------\n     * Configure USARTx CR3 (Hardware Flow Control) with parameters:\n     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.\n     */\n    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);\n\n    /*---------------------------- USART BRR Configuration -----------------------\n     * Retrieve Clock frequency used for USART Peripheral\n     */\n    LL_RCC_GetSystemClocksFreq(&rcc_clocks);\n    if (USARTx == USART1)\n    {\n      periphclk = rcc_clocks.PCLK2_Frequency;\n    }\n    else if (USARTx == USART2)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#if defined(USART3)\n    else if (USARTx == USART3)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* USART3 */\n#if defined(USART6)\n    else if (USARTx == USART6)\n    {\n      periphclk = rcc_clocks.PCLK2_Frequency;\n    }\n#endif /* USART6 */\n#if defined(UART4)\n    else if (USARTx == UART4)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART4 */\n#if defined(UART5)\n    else if (USARTx == UART5)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART5 */\n#if defined(UART7)\n    else if (USARTx == UART7)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART7 */\n#if defined(UART8)\n    else if (USARTx == UART8)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART8 */\n#if defined(UART9)\n    else if (USARTx == UART9)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART9 */\n#if defined(UART10)\n    else if (USARTx == UART10)\n    {\n      periphclk = rcc_clocks.PCLK1_Frequency;\n    }\n#endif /* UART10 */\n    else\n    {\n      /* Nothing to do, as error code is already assigned to ERROR value */\n    }\n\n    /* Configure the USART Baud Rate :\n       - valid baud rate value (different from 0) is required\n       - Peripheral clock as returned by RCC service, should be valid (different from 0).\n    */\n    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)\n        && (USART_InitStruct->BaudRate != 0U))\n    {\n      status = SUCCESS;\n      LL_USART_SetBaudRate(USARTx,\n                           periphclk,\n                           USART_InitStruct->OverSampling,\n                           USART_InitStruct->BaudRate);\n\n      /* Check BRR is greater than or equal to 16d */\n      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));\n\n      /* Check BRR is greater than or equal to 16d */\n      assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));\n    }\n  }\n  /* Endif (=> USART not in Disabled state => return ERROR) */\n\n  return (status);\n}\n\n/**\n  * @brief Set each @ref LL_USART_InitTypeDef field to default value.\n  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure\n  *                          whose fields will be set to default values.\n  * @retval None\n  */\n\nvoid LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)\n{\n  /* Set USART_InitStruct fields to default values */\n  USART_InitStruct->BaudRate            = 9600U;\n  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;\n  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;\n  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;\n  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;\n  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;\n  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;\n}\n\n/**\n  * @brief  Initialize USART Clock related settings according to the\n  *         specified parameters in the USART_ClockInitStruct.\n  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),\n  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.\n  * @param  USARTx USART Instance\n  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure\n  *         that contains the Clock configuration information for the specified USART peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content\n  *          - ERROR: Problem occurred during USART Registers initialization\n  */\nErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check USART Instance and Clock signal output parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));\n\n  /* USART needs to be in disabled state, in order to be able to configure some bits in\n     CRx registers */\n  if (LL_USART_IsEnabled(USARTx) == 0U)\n  {\n    /*---------------------------- USART CR2 Configuration -----------------------*/\n    /* If Clock signal has to be output */\n    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)\n    {\n      /* Deactivate Clock signal delivery :\n       * - Disable Clock Output:        USART_CR2_CLKEN cleared\n       */\n      LL_USART_DisableSCLKOutput(USARTx);\n    }\n    else\n    {\n      /* Ensure USART instance is USART capable */\n      assert_param(IS_USART_INSTANCE(USARTx));\n\n      /* Check clock related parameters */\n      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));\n      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));\n      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));\n\n      /*---------------------------- USART CR2 Configuration -----------------------\n       * Configure USARTx CR2 (Clock signal related bits) with parameters:\n       * - Enable Clock Output:         USART_CR2_CLKEN set\n       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value\n       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value\n       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.\n       */\n      MODIFY_REG(USARTx->CR2,\n                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,\n                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |\n                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);\n    }\n  }\n  /* Else (USART not in Disabled state => return ERROR */\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.\n  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure\n  *                               whose fields will be set to default values.\n  * @retval None\n  */\nvoid LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)\n{\n  /* Set LL_USART_ClockInitStruct fields with default values */\n  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;\n  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n\n"
  },
  {
    "path": "examples/lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_utils.c\n  * @author  MCD Application Team\n  * @brief   UTILS LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_utils.h\"\n#include \"stm32f4xx_ll_rcc.h\"\n#include \"stm32f4xx_ll_system.h\"\n#include \"stm32f4xx_ll_pwr.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n/** @addtogroup UTILS_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Private_Constants\n  * @{\n  */\n#if defined(RCC_MAX_FREQUENCY_SCALE1)\n#define UTILS_MAX_FREQUENCY_SCALE1  RCC_MAX_FREQUENCY           /*!< Maximum frequency for system clock at power scale1, in Hz */\n#endif /*RCC_MAX_FREQUENCY_SCALE1 */\n#define UTILS_MAX_FREQUENCY_SCALE2  RCC_MAX_FREQUENCY_SCALE2    /*!< Maximum frequency for system clock at power scale2, in Hz */\n#if defined(RCC_MAX_FREQUENCY_SCALE3)\n#define UTILS_MAX_FREQUENCY_SCALE3  RCC_MAX_FREQUENCY_SCALE3    /*!< Maximum frequency for system clock at power scale3, in Hz */\n#endif /* MAX_FREQUENCY_SCALE3 */\n\n/* Defines used for PLL range */\n#define UTILS_PLLVCO_INPUT_MIN      RCC_PLLVCO_INPUT_MIN        /*!< Frequency min for PLLVCO input, in Hz   */\n#define UTILS_PLLVCO_INPUT_MAX      RCC_PLLVCO_INPUT_MAX        /*!< Frequency max for PLLVCO input, in Hz   */\n#define UTILS_PLLVCO_OUTPUT_MIN     RCC_PLLVCO_OUTPUT_MIN       /*!< Frequency min for PLLVCO output, in Hz  */\n#define UTILS_PLLVCO_OUTPUT_MAX     RCC_PLLVCO_OUTPUT_MAX       /*!< Frequency max for PLLVCO output, in Hz  */\n\n/* Defines used for HSE range */\n#define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */\n#define UTILS_HSE_FREQUENCY_MAX     26000000U        /*!< Frequency max for HSE frequency, in Hz   */\n\n/* Defines used for FLASH latency according to HCLK Frequency */\n#if defined(FLASH_SCALE1_LATENCY1_FREQ)\n#define UTILS_SCALE1_LATENCY1_FREQ  FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */\n#endif\n#if defined(FLASH_SCALE1_LATENCY2_FREQ)\n#define UTILS_SCALE1_LATENCY2_FREQ  FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */\n#endif\n#if defined(FLASH_SCALE1_LATENCY3_FREQ)\n#define UTILS_SCALE1_LATENCY3_FREQ  FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */\n#endif\n#if defined(FLASH_SCALE1_LATENCY4_FREQ)\n#define UTILS_SCALE1_LATENCY4_FREQ  FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */\n#endif\n#if defined(FLASH_SCALE1_LATENCY5_FREQ)\n#define UTILS_SCALE1_LATENCY5_FREQ  FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */\n#endif\n#define UTILS_SCALE2_LATENCY1_FREQ  FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */\n#define UTILS_SCALE2_LATENCY2_FREQ  FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */\n#if defined(FLASH_SCALE2_LATENCY3_FREQ)\n#define UTILS_SCALE2_LATENCY3_FREQ  FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */\n#endif\n#if defined(FLASH_SCALE2_LATENCY4_FREQ)\n#define UTILS_SCALE2_LATENCY4_FREQ  FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */\n#endif\n#if defined(FLASH_SCALE2_LATENCY5_FREQ)\n#define UTILS_SCALE2_LATENCY5_FREQ  FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY1_FREQ)\n#define UTILS_SCALE3_LATENCY1_FREQ  FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY2_FREQ)\n#define UTILS_SCALE3_LATENCY2_FREQ  FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY3_FREQ)\n#define UTILS_SCALE3_LATENCY3_FREQ  FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY4_FREQ)\n#define UTILS_SCALE3_LATENCY4_FREQ  FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */\n#endif\n#if defined(FLASH_SCALE3_LATENCY5_FREQ)\n#define UTILS_SCALE3_LATENCY5_FREQ  FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */\n#endif\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Private_Macros\n  * @{\n  */\n#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))\n\n#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))\n\n#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))\n\n#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_9)  \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_63))\n\n#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))\n\n#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \\\n                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \\\n                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \\\n                                        || ((__VALUE__) == LL_RCC_PLLP_DIV_8))\n\n#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))\n\n#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))\n\n#if !defined(RCC_MAX_FREQUENCY_SCALE1)\n#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \\\n                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))\n                                             \n#elif defined(RCC_MAX_FREQUENCY_SCALE3) \n#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \\\n                                              (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \\\n                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))\n\n#else\n#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \\\n                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))\n\n#endif /* RCC_MAX_FREQUENCY_SCALE1*/\n#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \\\n                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))\n\n#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))\n/**\n  * @}\n  */\n/* Private function prototypes -----------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Functions UTILS Private functions\n  * @{\n  */\nstatic uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,\n                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);\nstatic ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);\nstatic ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\nstatic ErrorStatus UTILS_PLL_IsBusy(void);\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup UTILS_LL_EF_DELAY\n  * @{\n  */\n\n/**\n  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.\n  * @note   When a RTOS is used, it is recommended to avoid changing the Systick\n  *         configuration by calling this function, for a delay use rather osDelay RTOS service.\n  * @param  HCLKFrequency HCLK frequency in Hz\n  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq\n  * @retval None\n  */\nvoid LL_Init1msTick(uint32_t HCLKFrequency)\n{\n  /* Use frequency provided in argument */\n  LL_InitTick(HCLKFrequency, 1000U);\n}\n\n/**\n  * @brief  This function provides accurate delay (in milliseconds) based\n  *         on SysTick counter flag\n  * @note   When a RTOS is used, it is recommended to avoid using blocking delay\n  *         and use rather osDelay service.\n  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which\n  *         will configure Systick to 1ms\n  * @param  Delay specifies the delay time length, in milliseconds.\n  * @retval None\n  */\nvoid LL_mDelay(uint32_t Delay)\n{\n  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */\n  /* Add this code to indicate that local variable is not used */\n  ((void)tmp);\n\n  /* Add a period to guaranty minimum wait */\n  if(Delay < LL_MAX_DELAY)\n  {\n    Delay++;\n  }\n\n  while (Delay)\n  {\n    if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)\n    {\n      Delay--;\n    }\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup UTILS_EF_SYSTEM\n  *  @brief    System Configuration functions\n  *\n  @verbatim\n ===============================================================================\n           ##### System Configuration functions #####\n ===============================================================================\n    [..]\n         System, AHB and APB buses clocks configuration\n\n         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.\n  @endverbatim\n  @internal\n             Depending on the device voltage range, the maximum frequency should be\n             adapted accordingly to the Refenece manual.\n  @endinternal\n  * @{\n  */\n\n/**\n  * @brief  This function sets directly SystemCoreClock CMSIS variable.\n  * @note   Variable can be calculated also through SystemCoreClockUpdate function.\n  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)\n  * @retval None\n  */\nvoid LL_SetSystemCoreClock(uint32_t HCLKFrequency)\n{\n  /* HCLK clock frequency */\n  SystemCoreClock = HCLKFrequency;\n}\n\n/**\n  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL\n  * @note   The application need to ensure that PLL is disabled.\n  * @note   Function is based on the following formula:\n  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)\n  *         - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)\n  *         - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)\n  *         - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Max frequency configuration done\n  *          - ERROR: Max frequency configuration not done\n  */\nErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,\n                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t pllfreq = 0U;\n\n  /* Check if one of the PLL is enabled */\n  if(UTILS_PLL_IsBusy() == SUCCESS)\n  {\n    /* Calculate the new PLL output frequency */\n    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);\n\n    /* Enable HSI if not enabled */\n    if(LL_RCC_HSI_IsReady() != 1U)\n    {\n      LL_RCC_HSI_Enable();\n      while (LL_RCC_HSI_IsReady() != 1U)\n      {\n        /* Wait for HSI ready */\n      }\n    }\n\n    /* Configure PLL */\n    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,\n                                UTILS_PLLInitStruct->PLLP);\n\n    /* Enable PLL and switch system clock to PLL */\n    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);\n  }\n  else\n  {\n    /* Current PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @brief  This function configures system clock with HSE as clock source of the PLL\n  * @note   The application need to ensure that PLL is disabled.\n  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)\n  *         - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)\n  *         - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)\n  *         - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)\n  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000\n  * @param  HSEBypass This parameter can be one of the following values:\n  *         @arg @ref LL_UTILS_HSEBYPASS_ON\n  *         @arg @ref LL_UTILS_HSEBYPASS_OFF\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Max frequency configuration done\n  *          - ERROR: Max frequency configuration not done\n  */\nErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,\n                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t pllfreq = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));\n  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));\n\n  /* Check if one of the PLL is enabled */\n  if(UTILS_PLL_IsBusy() == SUCCESS)\n  {\n    /* Calculate the new PLL output frequency */\n    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);\n\n    /* Enable HSE if not enabled */\n    if(LL_RCC_HSE_IsReady() != 1U)\n    {\n      /* Check if need to enable HSE bypass feature or not */\n      if(HSEBypass == LL_UTILS_HSEBYPASS_ON)\n      {\n        LL_RCC_HSE_EnableBypass();\n      }\n      else\n      {\n        LL_RCC_HSE_DisableBypass();\n      }\n\n      /* Enable HSE */\n      LL_RCC_HSE_Enable();\n      while (LL_RCC_HSE_IsReady() != 1U)\n      {\n        /* Wait for HSE ready */\n      }\n    }\n\n    /* Configure PLL */\n    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,\n                                UTILS_PLLInitStruct->PLLP);\n\n    /* Enable PLL and switch system clock to PLL */\n    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);\n  }\n  else\n  {\n    /* Current PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup UTILS_LL_Private_Functions\n  * @{\n  */\n/**\n  * @brief  Update number of Flash wait states in line with new frequency and current\n            voltage range.\n  * @note   This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V\n  * @param  HCLK_Frequency  HCLK frequency\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Latency has been modified\n  *          - ERROR: Latency cannot be modified\n  */\nstatic ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)\n{\n  ErrorStatus status = SUCCESS;\n\n  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */\n\n  /* Frequency cannot be equal to 0 */\n  if(HCLK_Frequency == 0U)\n  {\n    status = ERROR;\n  }\n  else\n  {\n    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)\n    {\n#if defined (UTILS_SCALE1_LATENCY5_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_5;\n      }\n#endif /*UTILS_SCALE1_LATENCY5_FREQ */\n#if defined (UTILS_SCALE1_LATENCY4_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_4;\n      }\n#endif /* UTILS_SCALE1_LATENCY4_FREQ */\n#if defined (UTILS_SCALE1_LATENCY3_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_3;\n      }\n#endif /* UTILS_SCALE1_LATENCY3_FREQ */\n#if defined (UTILS_SCALE1_LATENCY2_FREQ) \n      if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n        {\n          latency = LL_FLASH_LATENCY_1;\n        }\n      }\n#endif /* UTILS_SCALE1_LATENCY2_FREQ */\n    }\n    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)\n    {\n#if defined (UTILS_SCALE2_LATENCY5_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_5;\n      }\n#endif /*UTILS_SCALE1_LATENCY5_FREQ */\n#if defined (UTILS_SCALE2_LATENCY4_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_4;\n      }\n#endif /*UTILS_SCALE1_LATENCY4_FREQ */\n#if defined (UTILS_SCALE2_LATENCY3_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_3;\n      }\n#endif /*UTILS_SCALE1_LATENCY3_FREQ */\n      if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n        {\n          latency = LL_FLASH_LATENCY_1;\n        }\n      }\n    }\n#if defined (LL_PWR_REGU_VOLTAGE_SCALE3)\n    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)\n    {\n#if defined (UTILS_SCALE3_LATENCY3_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_3;\n      }\n#endif /*UTILS_SCALE1_LATENCY3_FREQ */\n#if defined (UTILS_SCALE3_LATENCY2_FREQ)\n      if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n      {\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))\n        {\n          latency = LL_FLASH_LATENCY_1;\n        }\n      }\n    }\n#endif /*UTILS_SCALE1_LATENCY2_FREQ */\n#endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */\n\n    LL_FLASH_SetLatency(latency);\n\n    /* Check that the new number of wait states is taken into account to access the Flash\n       memory by reading the FLASH_ACR register */\n    if(LL_FLASH_GetLatency() != latency)\n    {\n      status = ERROR;\n    }\n  }\n  return status;\n}\n\n/**\n  * @brief  Function to check that PLL can be modified\n  * @param  PLL_InputFrequency  PLL input frequency (in Hz)\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @retval PLL output frequency (in Hz)\n  */\nstatic uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)\n{\n  uint32_t pllfreq = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));\n  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));\n  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));\n  \n  /* Check different PLL parameters according to RM                          */\n  /*  - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz.   */\n  pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));\n  assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));\n\n  /*  - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/\n  pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));\n  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));\n  \n  /*  - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached     */\n  pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);\n  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));\n\n  return pllfreq;\n}\n\n/**\n  * @brief  Function to check that PLL can be modified\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: PLL modification can be done\n  *          - ERROR: PLL is busy\n  */\nstatic ErrorStatus UTILS_PLL_IsBusy(void)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check if PLL is busy*/\n  if(LL_RCC_PLL_IsReady() != 0U)\n  {\n    /* PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n#if defined(RCC_PLLSAI_SUPPORT)\n  /* Check if PLLSAI is busy*/\n  if(LL_RCC_PLLSAI_IsReady() != 0U)\n  {\n    /* PLLSAI1 configuration cannot be modified */\n    status = ERROR;\n  }\n#endif /*RCC_PLLSAI_SUPPORT*/\n#if defined(RCC_PLLI2S_SUPPORT)\n  /* Check if PLLI2S is busy*/\n  if(LL_RCC_PLLI2S_IsReady() != 0U)\n  {\n    /* PLLI2S configuration cannot be modified */\n    status = ERROR;\n  }\n#endif /*RCC_PLLI2S_SUPPORT*/\n  return status;\n}\n\n/**\n  * @brief  Function to enable PLL and switch system clock to PLL\n  * @param  SYSCLK_Frequency SYSCLK frequency\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: No problem to switch system to PLL\n  *          - ERROR: Problem to switch system to PLL\n  */\nstatic ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t hclk_frequency = 0U;\n\n  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));\n  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));\n  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));\n\n  /* Calculate HCLK frequency */\n  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);\n\n  /* Increasing the number of wait states because of higher CPU frequency */\n  if(SystemCoreClock < hclk_frequency)\n  {\n    /* Set FLASH latency to highest latency */\n    status = UTILS_SetFlashLatency(hclk_frequency);\n  }\n\n  /* Update system clock configuration */\n  if(status == SUCCESS)\n  {\n    /* Enable PLL */\n    LL_RCC_PLL_Enable();\n    while (LL_RCC_PLL_IsReady() != 1U)\n    {\n      /* Wait for PLL ready */\n    }\n\n    /* Sysclk activation on the main PLL */\n    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);\n    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);\n    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)\n    {\n      /* Wait for system clock switch to PLL */\n    }\n\n    /* Set APB1 & APB2 prescaler*/\n    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);\n    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);\n  }\n    \n  /* Decreasing the number of wait states because of lower CPU frequency */\n  if(SystemCoreClock > hclk_frequency)\n  {\n    /* Set FLASH latency to lowest latency */\n    status = UTILS_SetFlashLatency(hclk_frequency);\n  }\n\n  /* Update SystemCoreClock variable */\n  if(status == SUCCESS)\n  {\n    LL_SetSystemCoreClock(hclk_frequency);\n  }\n\n  return status;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_adc.h\n  * @author  MCD Application Team\n  * @brief   Header file of ADC LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_ADC_H\n#define __STM32L4xx_LL_ADC_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (ADC1) || defined (ADC2) || defined (ADC3)\n\n/** @defgroup ADC_LL ADC\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup ADC_LL_Private_Constants ADC Private Constants\n  * @{\n  */\n\n/* Internal mask for ADC group regular sequencer:                             */\n/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */\n/* - sequencer register offset                                                */\n/* - sequencer rank bits position into the selected register                  */\n\n/* Internal register offset for ADC group regular sequencer configuration */\n/* (offset placed into a spare area of literal definition) */\n#define ADC_SQR1_REGOFFSET                 (0x00000000U)\n#define ADC_SQR2_REGOFFSET                 (0x00000100U)\n#define ADC_SQR3_REGOFFSET                 (0x00000200U)\n#define ADC_SQR4_REGOFFSET                 (0x00000300U)\n\n#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)\n#if defined(CORE_CM0PLUS)\n#define ADC_SQRX_REGOFFSET_POS             (8U) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */\n#endif\n#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)\n\n/* Definition of ADC group regular sequencer bits information to be inserted  */\n/* into ADC group regular sequencer ranks literals definition.                */\n#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ1) */\n#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (12U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ2) */\n#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (18U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ3) */\n#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ4) */\n#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ5) */\n#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ6) */\n#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (12U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */\n#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (18U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */\n#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */\n#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ10) */\n#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ11) */\n#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ12) */\n#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */\n#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */\n#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ15) */\n#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ16) */\n\n\n\n/* Internal mask for ADC group injected sequencer:                            */\n/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */\n/* - data register offset                                                     */\n/* - sequencer rank bits position into the selected register                  */\n\n/* Internal register offset for ADC group injected data register */\n/* (offset placed into a spare area of literal definition) */\n#define ADC_JDR1_REGOFFSET                 (0x00000000U)\n#define ADC_JDR2_REGOFFSET                 (0x00000100U)\n#define ADC_JDR3_REGOFFSET                 (0x00000200U)\n#define ADC_JDR4_REGOFFSET                 (0x00000300U)\n\n#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)\n#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)\n#if defined(CORE_CM0PLUS)\n#define ADC_JDRX_REGOFFSET_POS             (8U) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */\n#endif\n\n/* Definition of ADC group injected sequencer bits information to be inserted */\n/* into ADC group injected sequencer ranks literals definition.               */\n#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ( 8U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */\n#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (14U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */\n#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (20U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */\n#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (26U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */\n\n\n\n/* Internal mask for ADC group regular trigger:                               */\n/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */\n/* - regular trigger source                                                   */\n/* - regular trigger edge                                                     */\n#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */\n\n/* Mask containing trigger source masks for each of possible                  */\n/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */\n/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */\n#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0U)) | \\\n                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1U)) | \\\n                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2U)) | \\\n                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3U))  )\n\n/* Mask containing trigger edge masks for each of possible                    */\n/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */\n/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */\n#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0U)) | \\\n                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1U)) | \\\n                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2U)) | \\\n                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3U))  )\n\n/* Definition of ADC group regular trigger bits information.                  */\n#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTSEL) */\n#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR_EXTEN) */\n\n\n\n/* Internal mask for ADC group injected trigger:                              */\n/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */\n/* - injected trigger source                                                  */\n/* - injected trigger edge                                                    */\n#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */\n\n/* Mask containing trigger source masks for each of possible                  */\n/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */\n/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */\n#define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0U)) | \\\n                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 1U)) | \\\n                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 2U)) | \\\n                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 3U))  )\n\n/* Mask containing trigger edge masks for each of possible                    */\n/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */\n/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */\n#define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0U)) | \\\n                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1U)) | \\\n                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2U)) | \\\n                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3U))  )\n\n/* Definition of ADC group injected trigger bits information.                 */\n#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ( 2U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTSEL) */\n#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ( 6U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JEXTEN) */\n\n\n\n\n\n\n/* Internal mask for ADC channel:                                             */\n/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */\n/* - channel identifier defined by number                                     */\n/* - channel identifier defined by bitfield                                   */\n/* - channel differentiation between external channels (connected to          */\n/*   GPIO pins) and internal channels (connected to internal paths)           */\n/* - channel sampling time defined by SMPRx register offset                   */\n/*   and SMPx bits positions into SMPRx register                              */\n#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)\n#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)\n#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */\n#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)\n/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */\n#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */\n\n/* Channel differentiation between external and internal channels */\n#define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000U) /* Marker of internal channel */\n#define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */\n#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)\n\n/* Internal register offset for ADC channel sampling time configuration */\n/* (offset placed into a spare area of literal definition) */\n#define ADC_SMPR1_REGOFFSET                (0x00000000U)\n#define ADC_SMPR2_REGOFFSET                (0x02000000U)\n#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)\n#if defined(CORE_CM0PLUS)\n#define ADC_SMPRX_REGOFFSET_POS            (25U) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */\n#endif\n\n#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000U)\n#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */\n\n/* Definition of channels ID number information to be inserted into           */\n/* channels literals definition.                                              */\n#define ADC_CHANNEL_0_NUMBER               (0x00000000U)\n#define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )\n#define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )\n#define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )\n#define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )\n#define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )\n#define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )\n#define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )\n#define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )\n#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)\n#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )\n\n/* Definition of channels ID bitfield information to be inserted into         */\n/* channels literals definition.                                              */\n#define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)\n#define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)\n#define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)\n#define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)\n#define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)\n#define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)\n#define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)\n#define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)\n#define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)\n#define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)\n#define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)\n#define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)\n#define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)\n#define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)\n#define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)\n#define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)\n#define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)\n#define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)\n#define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)\n\n/* Definition of channels sampling time information to be inserted into       */\n/* channels literals definition.                                              */\n#define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP0) */\n#define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP1) */\n#define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP2) */\n#define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP3) */\n#define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP4) */\n#define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP5) */\n#define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP6) */\n#define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP7) */\n#define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP8) */\n#define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP9) */\n#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */\n#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */\n#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */\n#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */\n#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */\n#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */\n#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */\n#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */\n#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */\n\n\n/* Internal mask for ADC mode single or differential ended:                   */\n/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */\n/* the relevant bits for:                                                     */\n/* (concatenation of multiple bits used in different registers)               */\n/* - ADC calibration: calibration start, calibration factor get or set        */\n/* - ADC channels: set each ADC channel ending mode                           */\n#define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)\n#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)\n#define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */\n#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_5) /* Bit chosen to perform of shift when single mode is selected, shift value out of channels bits range. */\n#if defined(CORE_CM0PLUS)\n#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000U)                           /* Selection of 1 bit to discriminate differential mode: mask of bit */\n#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16U)                                   /* Selection of 1 bit to discriminate differential mode: position of bit */\n#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4U) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */\n#endif\n\n/* Internal mask for ADC analog watchdog:                                     */\n/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */\n/* (concatenation of multiple bits used in different analog watchdogs,        */\n/* (feature of several watchdogs not available on all STM32 families)).       */\n/* - analog watchdog 1: monitored channel defined by number,                  */\n/*   selection of ADC group (ADC groups regular and-or injected).             */\n/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */\n/*   selection on groups.                                                     */\n\n/* Internal register offset for ADC analog watchdog channel configuration */\n#define ADC_AWD_CR1_REGOFFSET              (0x00000000U)\n#define ADC_AWD_CR2_REGOFFSET              (0x00100000U)\n#define ADC_AWD_CR3_REGOFFSET              (0x00200000U)\n\n/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */\n/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */\n#define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)\n#define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024U)\n\n#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)\n\n#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)\n#define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)\n#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)\n\n#define ADC_AWD_CRX_REGOFFSET_POS          (20U) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */\n\n/* Internal register offset for ADC analog watchdog threshold configuration */\n#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)\n#define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)\n#define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)\n#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)\n#if defined(CORE_CM0PLUS)\n#define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */\n#define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000U)                   /* Selection of 1 bit to discriminate threshold high: mask of bit */\n#define ADC_AWD_TRX_BIT_HIGH_POS           (16U)                           /* Selection of 1 bit to discriminate threshold high: position of bit */\n#define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4U) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */\n#endif\n\n/* Internal mask for ADC offset:                                              */\n/* Internal register offset for ADC offset number configuration */\n#define ADC_OFR1_REGOFFSET                 (0x00000000U)\n#define ADC_OFR2_REGOFFSET                 (0x00000001U)\n#define ADC_OFR3_REGOFFSET                 (0x00000002U)\n#define ADC_OFR4_REGOFFSET                 (0x00000003U)\n#define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)\n\n\n/* ADC registers bits positions */\n#define ADC_CFGR_RES_BITOFFSET_POS         ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR_RES) */\n#define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1SGL) */\n#define ADC_CFGR_AWD1EN_BITOFFSET_POS      (23U) /* Value equivalent to POSITION_VAL(ADC_CFGR_AWD1EN) */\n#define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (24U) /* Value equivalent to POSITION_VAL(ADC_CFGR_JAWD1EN) */\n#define ADC_TR1_HT1_BITOFFSET_POS          (16U) /* Value equivalent to POSITION_VAL(ADC_TR1_HT1) */\n\n\n/* ADC registers bits groups */\n#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property \"rs\": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */\n\n\n/* ADC internal channels related definitions */\n/* Internal voltage reference VrefInt */\n#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */\n#define VREFINT_CAL_VREF                   ( 3000U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */\n/* Temperature sensor */\n#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8U)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */\n#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */\n#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */\n#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */\n#define TEMPSENSOR_CAL_VREFANALOG          ( 3000U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */\n\n\n/**\n  * @}\n  */\n\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup ADC_LL_Private_Macros ADC Private Macros\n  * @{\n  */\n\n/**\n  * @brief  Driver macro reserved for internal use: isolate bits with the\n  *         selected mask and shift them to the register LSB\n  *         (shift mask on register position bit 0).\n  * @param  __BITS__ Bits in register 32 bits\n  * @param  __MASK__ Mask in register 32 bits\n  * @retval Bits in register 32 bits\n  */\n#define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \\\n  (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))\n\n/**\n  * @brief  Driver macro reserved for internal use: set a pointer to\n  *         a register from a register basis from which an offset\n  *         is applied.\n  * @param  __REG__ Register basis from which the offset is applied.\n  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).\n  * @retval Pointer to register address\n  */\n#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \\\n ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))\n\n/**\n  * @}\n  */\n\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure\n  * @{\n  */\n\n/**\n  * @brief  Structure definition of some features of ADC common parameters\n  *         and multimode\n  *         (all ADC instances belonging to the same ADC common instance).\n  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()\n  *         is conditioned to ADC instances state (all ADC instances\n  *         sharing the same ADC common instance):\n  *         All ADC instances sharing the same ADC common instance must be\n  *         disabled.\n  */\ntypedef struct\n{\n  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.\n                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE\n                                             @note On this STM32 serie, if ADC group injected is used, some\n                                                   clock ratio constraints between ADC clock and AHB clock\n                                                   must be respected. Refer to reference manual.\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n  uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).\n                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */\n\n  uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.\n                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */\n\n  uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.\n                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n} LL_ADC_CommonInitTypeDef;\n\n/**\n  * @brief  Structure definition of some features of ADC instance.\n  * @note   These parameters have an impact on ADC scope: ADC instance.\n  *         Affects both group regular and group injected (availability\n  *         of ADC group injected depends on STM32 families).\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Instance .\n  * @note   The setting of these parameters by function @ref LL_ADC_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  */\ntypedef struct\n{\n  uint32_t Resolution;                  /*!< Set ADC resolution.\n                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */\n\n  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.\n                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */\n\n  uint32_t LowPowerMode;                /*!< Set ADC low power mode.\n                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */\n\n} LL_ADC_InitTypeDef;\n\n/**\n  * @brief  Structure definition of some features of ADC group regular.\n  * @note   These parameters have an impact on ADC scope: ADC group regular.\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular\n  *         (functions with prefix \"REG\").\n  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  */\ntypedef struct\n{\n  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE\n                                             @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge\n                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).\n                                                   In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */\n\n  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */\n\n  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE\n                                             @note This parameter has an effect only if group regular sequencer is enabled\n                                                   (scan length of 2 ranks or more).\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */\n\n  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE\n                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */\n\n  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */\n\n  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:\n                                             data preserved or overwritten.\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */\n\n} LL_ADC_REG_InitTypeDef;\n\n/**\n  * @brief  Structure definition of some features of ADC group injected.\n  * @note   These parameters have an impact on ADC scope: ADC group injected.\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular\n  *         (functions with prefix \"INJ\").\n  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  */\ntypedef struct\n{\n  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).\n                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE\n                                             @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge\n                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).\n                                                   In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */\n\n  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.\n                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */\n\n  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.\n                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE\n                                             @note This parameter has an effect only if group injected sequencer is enabled\n                                                   (scan length of 2 ranks or more).\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */\n\n  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.\n                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO\n                                             Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. \n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */\n\n} LL_ADC_INJ_InitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants\n  * @{\n  */\n\n/** @defgroup ADC_LL_EC_FLAG ADC flags\n  * @brief    Flags defines which can be used with LL_ADC_ReadReg function\n  * @{\n  */\n#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */\n#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */\n#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */\n#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */\n#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */\n#define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */\n#define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */\n#define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */\n#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */\n#define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */\n#define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */\n#if defined(ADC_MULTIMODE_SUPPORT)\n#define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */\n#define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */\n#define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */\n#define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */\n#define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */\n#define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */\n#define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */\n#define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */\n#define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */\n#define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */\n#define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */\n#define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */\n#define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */\n#define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */\n#define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */\n#define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */\n#define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */\n#define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */\n#define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */\n#define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */\n#define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */\n#define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)\n  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions\n  * @{\n  */\n#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */\n#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */\n#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */\n#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */\n#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */\n#define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */\n#define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */\n#define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */\n#define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */\n#define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */\n#define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose\n  * @{\n  */\n/* List of ADC registers intended to be used (most commonly) with             */\n/* DMA transfer.                                                              */\n/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */\n#define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */\n#if defined(ADC_MULTIMODE_SUPPORT)\n#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source\n  * @{\n  */\n#define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */\n#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */\n#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */\n#define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000U)                               /*!< ADC asynchronous clock without prescaler */\n#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */\n#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */\n#define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */\n#define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */\n#define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */\n#define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */\n#define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */\n#define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */\n#define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */\n#define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */\n#define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels\n  * @{\n  */\n/* Note: Other measurement paths to internal channels may be available        */\n/*       (connections to other peripherals).                                  */\n/*       If they are not listed below, they do not require any specific       */\n/*       path enable. In this case, Access to measurement path is done        */\n/*       only by selecting the corresponding ADC internal channel.            */\n#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000U)/*!< ADC measurement pathes all disabled */\n#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */\n#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */\n#define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution\n  * @{\n  */\n#define LL_ADC_RESOLUTION_12B              (0x00000000U)             /*!< ADC resolution 12 bits */\n#define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */\n#define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */\n#define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment\n  * @{\n  */\n#define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/\n#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)       /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode\n  * @{\n  */\n#define LL_ADC_LP_MODE_NONE                (0x00000000U)             /*!< No ADC low power mode activated */\n#define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number\n  * @{\n  */\n#define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\n#define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\n#define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\n#define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state\n  * @{\n  */\n#define LL_ADC_OFFSET_DISABLE              (0x00000000U)/*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */\n#define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups\n  * @{\n  */\n#define LL_ADC_GROUP_REGULAR               (0x00000001U) /*!< ADC group regular (available on all STM32 devices) */\n#define LL_ADC_GROUP_INJECTED              (0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/\n#define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003U) /*!< ADC both groups regular and injected */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number\n  * @{\n  */\n#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */\n#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */\n#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */\n#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */\n#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */\n#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */\n#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */\n#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */\n#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */\n#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */\n#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */\n#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */\n#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */\n#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */\n#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */\n#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */\n#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */\n#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */\n#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */\n#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_0  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32L4, ADC channel available only on ADC instance: ADC1. */\n#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */\n#define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32L4, ADC channel available only on ADC instances: ADC1, ADC3. */\n#if defined(ADC1) && !defined(ADC2)\n#define LL_ADC_CHANNEL_DAC1CH1             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */\n#define LL_ADC_CHANNEL_DAC1CH2             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */\n#elif defined(ADC2)\n#define LL_ADC_CHANNEL_DAC1CH1_ADC2        (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */\n#define LL_ADC_CHANNEL_DAC1CH2_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */\n#if defined(ADC3)\n#define LL_ADC_CHANNEL_DAC1CH1_ADC3        (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */\n#define LL_ADC_CHANNEL_DAC1CH2_ADC3        (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */\n#endif\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source\n  * @{\n  */\n#define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000U)                                                                                                   /*!< ADC group regular conversion trigger internal: SW start. */\n#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge\n  * @{\n  */\n#define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */\n#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */\n#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode\n* @{\n*/\n#define LL_ADC_REG_CONV_SINGLE             (0x00000000U)           /*!< ADC conversions are performed in single mode: one conversion per trigger */\n#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data\n  * @{\n  */\n#define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000U)                        /*!< ADC conversions are not transferred by DMA */\n#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                  ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */\n#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */\n/**\n  * @}\n  */\n\n#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)\n/** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data\n  * @{\n  */\n#define LL_ADC_REG_DFSDM_TRANSFER_NONE     (0x00000000U)           /*!< ADC conversions are not transferred by DFSDM. */\n#define LL_ADC_REG_DFSDM_TRANSFER_ENABLE   (ADC_CFGR_DFSDMCFG)     /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */\n/**\n  * @}\n  */\n#endif\n\n#if defined(ADC_SMPR1_SMPPLUS)\n/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration\n  * @{\n  */\n#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT      (0x00000000U)       /*!< ADC sampling time let to default settings. */\n#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */\n/**\n  * @}\n  */\n#endif\n\n/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data\n* @{\n*/\n#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000U)          /*!< ADC group regular behavior in case of overrun: data preserved */\n#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length\n  * @{\n  */\n#define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000U)                                               /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode\n  * @{\n  */\n#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000U)                                                                /*!< ADC group regular sequencer discontinuous mode disable */\n#define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */\n#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks\n  * @{\n  */\n#define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */\n#define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */\n#define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */\n#define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */\n#define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */\n#define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */\n#define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */\n#define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */\n#define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */\n#define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */\n#define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */\n#define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */\n#define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */\n#define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */\n#define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */\n#define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source\n  * @{\n  */\n#define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000U)                                                                                                       /*!< ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                     /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge\n  * @{\n  */\n#define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */\n#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */\n#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode\n* @{\n*/\n#define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000U)          /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */\n#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode\n  * @{\n  */\n#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000U)          /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */\n#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */\n#define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length\n  * @{\n  */\n#define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000U)                   /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */\n#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */\n#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */\n#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode\n  * @{\n  */\n#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000U)          /*!< ADC group injected sequencer discontinuous mode disable */\n#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks\n  * @{\n  */\n#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */\n#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */\n#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */\n#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time\n  * @{\n  */\n#define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000U)                                               /*!< Sampling time 2.5 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_6CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 12.5 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_24CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 47.5 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending\n  * @{\n  */\n#define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */\n#define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */\n#define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number\n  * @{\n  */\n#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */\n#define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */\n#define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels\n  * @{\n  */\n#define LL_ADC_AWD_DISABLE                 (0x00000000U)                                                                                       /*!< ADC analog watchdog monitoring disabled */\n#define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */\n#define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */\n#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */\n#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */\n#define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */\n#define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */\n#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */\n#define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */\n#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */\n#define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */\n#define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */\n#define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */\n#if defined(ADC1) && !defined(ADC2)\n#define LL_ADC_AWD_CH_DAC1CH1_REG          ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */\n#define LL_ADC_AWD_CH_DAC1CH1_INJ          ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */\n#define LL_ADC_AWD_CH_DAC1CH1_REG_INJ      ((LL_ADC_CHANNEL_DAC1CH1       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */\n#define LL_ADC_AWD_CH_DAC1CH2_REG          ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group regular only */\n#define LL_ADC_AWD_CH_DAC1CH2_INJ          ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by group injected only */\n#define LL_ADC_AWD_CH_DAC1CH2_REG_INJ      ((LL_ADC_CHANNEL_DAC1CH2       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC1, converted by either group regular or injected */\n#elif defined(ADC2)\n#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */\n#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */\n#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */\n#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */\n#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */\n#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */\n#if defined(ADC3)\n#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */\n#define LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */\n#define LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */\n#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group regular only */\n#define LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by group injected only */\n#define LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC3, converted by either group regular or injected */\n#endif\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds\n  * @{\n  */\n#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */\n#define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */\n#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope\n  * @{\n  */\n#define LL_ADC_OVS_DISABLE                 (0x00000000U)                                         /*!< ADC oversampling disabled. */\n#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */\n#define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */\n#define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */\n#define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode\n  * @{\n  */\n#define LL_ADC_OVS_REG_CONT                (0x00000000U)          /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */\n#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio\n  * @{\n  */\n#define LL_ADC_OVS_RATIO_2                 (0x00000000U)                                            /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\n#define LL_ADC_OVS_RATIO_4                 (                                      ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\n#define LL_ADC_OVS_RATIO_8                 (                   ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\n#define LL_ADC_OVS_RATIO_16                (                   ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\n#define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2                                      ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\n#define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2                    | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\n#define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1                   ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\n#define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift\n  * @{\n  */\n#define LL_ADC_OVS_SHIFT_NONE              (0x00000000U)                                                               /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */\n#define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */\n#define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */\n#define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */\n#define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */\n#define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */\n#define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */\n#define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */\n#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */\n/**\n  * @}\n  */\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode\n  * @{\n  */\n#define LL_ADC_MULTI_INDEPENDENT           (0x00000000U)                                                       /*!< ADC dual mode disabled (ADC independent mode) */\n#define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */\n#define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */\n#define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */\n#define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */\n#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */\n#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */\n#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer\n  * @{\n  */\n#define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000U)                                      /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */\n#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (                 ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */\n#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (                 ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */\n#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1                 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */\n#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases\n  * @{\n  */\n#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   (0x00000000U)                                                           /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */\n#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave\n  * @{\n  */\n#define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */\n#define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */\n#define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */\n/**\n  * @}\n  */\n\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n/** @defgroup ADC_LL_EC_LEGACY ADC literals legacy naming\n  * @{\n  */\n#define LL_ADC_REG_TRIG_SW_START           (LL_ADC_REG_TRIG_SOFTWARE)\n#define LL_ADC_REG_TRIG_EXT_TIM1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)\n#define LL_ADC_REG_TRIG_EXT_TIM1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)\n#define LL_ADC_REG_TRIG_EXT_TIM1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)\n#define LL_ADC_REG_TRIG_EXT_TIM2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)\n#define LL_ADC_REG_TRIG_EXT_TIM3_CC4       (LL_ADC_REG_TRIG_EXT_TIM3_CH4)\n#define LL_ADC_REG_TRIG_EXT_TIM4_CC4       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)\n\n#define LL_ADC_INJ_TRIG_SW_START           (LL_ADC_INJ_TRIG_SOFTWARE)\n#define LL_ADC_INJ_TRIG_EXT_TIM1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)\n#define LL_ADC_INJ_TRIG_EXT_TIM2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)\n#define LL_ADC_INJ_TRIG_EXT_TIM3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)\n#define LL_ADC_INJ_TRIG_EXT_TIM3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)\n#define LL_ADC_INJ_TRIG_EXT_TIM3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)\n#define LL_ADC_INJ_TRIG_EXT_TIM8_CC4       (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)\n\n#define LL_ADC_OVS_DATA_SHIFT_NONE        (LL_ADC_OVS_SHIFT_NONE)\n#define LL_ADC_OVS_DATA_SHIFT_1           (LL_ADC_OVS_SHIFT_RIGHT_1)\n#define LL_ADC_OVS_DATA_SHIFT_2           (LL_ADC_OVS_SHIFT_RIGHT_2)\n#define LL_ADC_OVS_DATA_SHIFT_3           (LL_ADC_OVS_SHIFT_RIGHT_3)\n#define LL_ADC_OVS_DATA_SHIFT_4           (LL_ADC_OVS_SHIFT_RIGHT_4)\n#define LL_ADC_OVS_DATA_SHIFT_5           (LL_ADC_OVS_SHIFT_RIGHT_5)\n#define LL_ADC_OVS_DATA_SHIFT_6           (LL_ADC_OVS_SHIFT_RIGHT_6)\n#define LL_ADC_OVS_DATA_SHIFT_7           (LL_ADC_OVS_SHIFT_RIGHT_7)\n#define LL_ADC_OVS_DATA_SHIFT_8           (LL_ADC_OVS_SHIFT_RIGHT_8)\n\n/**\n  * @}\n  */\n\n\n/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays\n  * @note   Only ADC IP HW delays are defined in ADC LL driver driver,\n  *         not timeout values.\n  *         For details on delays values, refer to descriptions in source code\n  *         above each literal definition.\n  * @{\n  */\n  \n/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */\n/*       not timeout values.                                                  */\n/*       Timeout values for ADC operations are dependent to device clock      */\n/*       configuration (system clock versus ADC clock),                       */\n/*       and therefore must be defined in user application.                   */\n/*       Indications for estimation of ADC timeout delays, for this           */\n/*       STM32 serie:                                                         */\n/*       - ADC calibration time: maximum delay is 112/fADC.                   */\n/*         (refer to device datasheet, parameter \"tCAL\")                      */\n/*       - ADC enable time: maximum delay is 1 conversion cycle.              */\n/*         (refer to device datasheet, parameter \"tSTAB\")                     */\n/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */\n/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */\n/*         cycles                                                             */\n/*       - ADC conversion time: duration depending on ADC clock and ADC       */\n/*         configuration.                                                     */\n/*         (refer to device reference manual, section \"Timing\")               */\n\n/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */\n/* Delay set to maximum value (refer to device datasheet,                     */\n/* parameter \"tADCVREG_STUP\").                                                */\n/* Unit: us                                                                   */\n#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US (  10U)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */\n\n/* Delay for internal voltage reference stabilization time.                   */\n/* Delay set to maximum value (refer to device datasheet,                     */\n/* parameter \"tstart_vrefint\").                                               */\n/* Unit: us                                                                   */\n#define LL_ADC_DELAY_VREFINT_STAB_US       (  12U)  /*!< Delay for internal voltage reference stabilization time */\n\n/* Delay for temperature sensor stabilization time.                           */\n/* Literal set to maximum value (refer to device datasheet,                   */\n/* parameter \"tSTART\").                                                       */\n/* Unit: us                                                                   */\n#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ( 120U)  /*!< Delay for temperature sensor stabilization time */\n\n/* Delay required between ADC end of calibration and ADC enable.              */\n/* Note: On this STM32 serie, a minimum number of ADC clock cycles            */\n/*       are required between ADC end of calibration and ADC enable.          */\n/*       Wait time can be computed in user application by waiting for the     */\n/*       equivalent number of CPU cycles, by taking into account              */\n/*       ratio of CPU clock versus ADC clock prescalers.                      */\n/* Unit: ADC clock cycles.                                                    */\n#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4U)  /*!< Delay required between ADC end of calibration and ADC enable */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros\n  * @{\n  */\n\n/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in ADC register\n  * @param  __INSTANCE__ ADC Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in ADC register\n  * @param  __INSTANCE__ ADC Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro\n  * @{\n  */\n\n/**\n  * @brief  Helper macro to get ADC channel number in decimal format\n  *         from literals LL_ADC_CHANNEL_x.\n  * @note   Example:\n  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)\n  *           will return decimal number \"4\".\n  * @note   The input can be a value from functions where a channel\n  *         number is returned, either defined with number\n  *         or with bitfield (only one bit must be set).\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @retval Value between Min_Data=0 and Max_Data=18\n  */\n#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \\\n  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U)                                  \\\n    ? (                                                                                    \\\n       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \\\n      )                                                                                    \\\n      :                                                                                    \\\n      (                                                                                    \\\n       POSITION_VAL((__CHANNEL__))                                                         \\\n      )                                                                                    \\\n  )\n\n/**\n  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x\n  *         from number in decimal format.\n  * @note   Example:\n  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)\n  *           will return a data equivalent to \"LL_ADC_CHANNEL_4\".\n  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\\n\n  *         (1, 2, 3, 4) For ADC channel read back from ADC register,\n  *                      comparison with internal channel parameter to be done\n  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  */\n#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \\\n  (((__DECIMAL_NB__) <= 9U)                                                                                     \\\n    ? (                                                                                                         \\\n       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \\\n       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       |        \\\n       (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \\\n      )                                                                                                         \\\n      :                                                                                                         \\\n      (                                                                                                         \\\n       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \\\n       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                              | \\\n       (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \\\n      )                                                                                                         \\\n  )\n\n/**\n  * @brief  Helper macro to determine whether the selected channel\n  *         corresponds to literal definitions of driver.\n  * @note   The different literal definitions of ADC channels are:\n  *         - ADC internal channel:\n  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...\n  *         - ADC external channel (channel connected to a GPIO pin):\n  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...\n  * @note   The channel parameter must be a value defined from literal\n  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\n  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),\n  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),\n  *         must not be a value from functions where a channel number is\n  *         returned from ADC registers,\n  *         because internal and external channels share the same channel\n  *         number in ADC registers. The differentiation is made only with\n  *         parameters definitions of driver.\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @retval Value \"0\" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).\n  *         Value \"1\" if the channel corresponds to a parameter definition of a ADC internal channel.\n  */\n#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \\\n  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)\n\n/**\n  * @brief  Helper macro to convert a channel defined from parameter\n  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\n  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),\n  *         to its equivalent parameter definition of a ADC external channel\n  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).\n  * @note   The channel parameter can be, additionally to a value\n  *         defined from parameter definition of a ADC internal channel\n  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),\n  *         a value defined from parameter definition of\n  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)\n  *         or a value from functions where a channel number is returned\n  *         from ADC registers.\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  */\n#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \\\n  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)\n\n/**\n  * @brief  Helper macro to determine whether the internal channel\n  *         selected is available on the ADC instance selected.\n  * @note   The channel parameter must be a value defined from parameter\n  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\n  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),\n  *         must not be a value defined from parameter definition of\n  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)\n  *         or a value from functions where a channel number is\n  *         returned from ADC registers,\n  *         because internal and external channels share the same channel\n  *         number in ADC registers. The differentiation is made only with\n  *         parameters definitions of driver.\n  * @param  __ADC_INSTANCE__ ADC instance\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n  * @retval Value \"0\" if the internal channel selected is not available on the ADC instance selected.\n  *         Value \"1\" if the internal channel selected is available on the ADC instance selected.\n  */\n#if defined (ADC1) && defined (ADC2) && defined (ADC3)\n#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \\\n  (((__ADC_INSTANCE__) == ADC1)                                                \\\n    ? (                                                                        \\\n       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \\\n       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \\\n       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \\\n      )                                                                        \\\n      :                                                                        \\\n      ((__ADC_INSTANCE__) == ADC2)                                             \\\n      ? (                                                                      \\\n         ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \\\n         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \\\n         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \\\n        )                                                                      \\\n        :                                                                      \\\n        ((__ADC_INSTANCE__) == ADC3)                                           \\\n        ? (                                                                    \\\n           ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                   \\\n           ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                   \\\n           ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                   \\\n           ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC3) ||                   \\\n           ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC3)                      \\\n          )                                                                    \\\n          :                                                                    \\\n          (0U)                                                                 \\\n  )\n#elif defined (ADC1) && defined (ADC2)\n#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \\\n  (((__ADC_INSTANCE__) == ADC1)                                                \\\n    ? (                                                                        \\\n       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                         \\\n       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                         \\\n       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                  \\\n      )                                                                        \\\n      :                                                                        \\\n      ((__ADC_INSTANCE__) == ADC2)                                             \\\n      ? (                                                                      \\\n         ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)      ||                     \\\n         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                     \\\n         ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                        \\\n        )                                                                      \\\n        :                                                                      \\\n        (0U)                                                                   \\\n  )\n#elif defined (ADC1)\n#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \\\n  (                                                                            \\\n    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                            \\\n    ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                            \\\n    ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)       ||                            \\\n    ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1)    ||                            \\\n    ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2)                                  \\\n  )\n#endif\n\n/**\n  * @brief  Helper macro to define ADC analog watchdog parameter:\n  *         define a single channel to monitor with analog watchdog\n  *         from sequencer channel and groups definition.\n  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().\n  *         Example:\n  *           LL_ADC_SetAnalogWDMonitChannels(\n  *             ADC1, LL_ADC_AWD1,\n  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\\n\n  *         (1, 2, 3, 4) For ADC channel read back from ADC register,\n  *                      comparison with internal channel parameter to be done\n  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  * @param  __GROUP__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_GROUP_REGULAR\n  *         @arg @ref LL_ADC_GROUP_INJECTED\n  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_DISABLE\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(4)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG          (0)(2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ          (0)(2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ         (2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG          (0)(2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ          (0)(2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ         (2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)(6)\n  *         \n  *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\\n\n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n  */\n#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \\\n  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \\\n    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                        \\\n      :                                                                                                   \\\n      ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \\\n       ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    \\\n         :                                                                                                \\\n         (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)  \\\n  )\n\n/**\n  * @brief  Helper macro to set the value of ADC analog watchdog threshold high\n  *         or low in function of ADC resolution, when ADC resolution is\n  *         different of 12 bits.\n  * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()\n  *         or @ref LL_ADC_SetAnalogWDThresholds().\n  *         Example, with a ADC resolution of 8 bits, to set the value of\n  *         analog watchdog threshold high (on 8 bits):\n  *           LL_ADC_SetAnalogWDThresholds\n  *            (< ADCx param >,\n  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)\n  *            );\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \\\n  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))\n\n/**\n  * @brief  Helper macro to get the value of ADC analog watchdog threshold high\n  *         or low in function of ADC resolution, when ADC resolution is \n  *         different of 12 bits.\n  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().\n  *         Example, with a ADC resolution of 8 bits, to get the value of\n  *         analog watchdog threshold high (on 8 bits):\n  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION\n  *            (LL_ADC_RESOLUTION_8B,\n  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)\n  *            );\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \\\n  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))\n\n/**\n  * @brief  Helper macro to get the ADC analog watchdog threshold high\n  *         or low from raw value containing both thresholds concatenated.\n  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().\n  *         Example, to get analog watchdog threshold high from the register raw value:\n  *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);\n  * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW\n  * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n#if defined(CORE_CM0PLUS)\n#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \\\n  (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)\n#else\n#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)       \\\n  (((__AWD_THRESHOLDS__) >> POSITION_VAL((__AWD_THRESHOLD_TYPE__))) & LL_ADC_AWD_THRESHOLD_LOW)\n#endif\n\n/**\n  * @brief  Helper macro to set the ADC calibration value with both single ended\n  *         and differential modes calibration factors concatenated.\n  * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().\n  *         Example, to set calibration factors single ended to 0x55\n  *         and differential ended to 0x2A:\n  *           LL_ADC_SetCalibrationFactor(\n  *             ADC1,\n  *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))\n  * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F\n  * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F\n  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\n  */\n#if defined(CORE_CM0PLUS)\n#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \\\n  (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))\n#else\n#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \\\n  (((__CALIB_FACTOR_DIFFERENTIAL__) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) | (__CALIB_FACTOR_SINGLE_ENDED__))\n#endif\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/**\n  * @brief  Helper macro to get the ADC multimode conversion data of ADC master\n  *         or ADC slave from raw value with both ADC conversion data concatenated.\n  * @note   This macro is intended to be used when multimode transfer by DMA\n  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().\n  *         In this case the transferred data need to processed with this macro\n  *         to separate the conversion data of ADC master and ADC slave.\n  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_MASTER\n  *         @arg @ref LL_ADC_MULTI_SLAVE\n  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \\\n  (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)\n#endif\n\n/**\n  * @brief  Helper macro to select the ADC common instance\n  *         to which is belonging the selected ADC instance.\n  * @note   ADC common register instance can be used for:\n  *         - Set parameters common to several ADC instances\n  *         - Multimode (for devices with several ADC instances)\n  *         Refer to functions having argument \"ADCxy_COMMON\" as parameter.\n  * @param  __ADCx__ ADC instance\n  * @retval ADC common register instance\n  */\n#if defined(ADC1) && defined(ADC2) && defined(ADC3)\n#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \\\n  (ADC123_COMMON)\n#elif defined(ADC1) && defined(ADC2)\n#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \\\n  (ADC12_COMMON)\n#else\n#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \\\n  (ADC1_COMMON)\n#endif\n\n/**\n  * @brief  Helper macro to check if all ADC instances sharing the same\n  *         ADC common instance are disabled.\n  * @note   This check is required by functions with setting conditioned to\n  *         ADC state:\n  *         All ADC instances of the ADC common group must be disabled.\n  *         Refer to functions having argument \"ADCxy_COMMON\" as parameter.\n  * @note   On devices with only 1 ADC common instance, parameter of this macro\n  *         is useless and can be ignored (parameter kept for compatibility\n  *         with devices featuring several ADC common instances).\n  * @param  __ADCXY_COMMON__ ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Value \"0\" if all ADC instances sharing the same ADC common instance\n  *         are disabled.\n  *         Value \"1\" if at least one ADC instance sharing the same ADC common instance\n  *         is enabled.\n  */\n#if defined(ADC1) && defined(ADC2) && defined(ADC3)\n#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \\\n  (LL_ADC_IsEnabled(ADC1) |                                                    \\\n   LL_ADC_IsEnabled(ADC2) |                                                    \\\n   LL_ADC_IsEnabled(ADC3)  )\n#elif defined(ADC1) && defined(ADC2)\n#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \\\n  (LL_ADC_IsEnabled(ADC1) |                                                    \\\n   LL_ADC_IsEnabled(ADC2)  )\n#else\n#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \\\n  (LL_ADC_IsEnabled(ADC1))\n#endif\n\n/**\n  * @brief  Helper macro to define the ADC conversion data full-scale digital\n  *         value corresponding to the selected ADC resolution.\n  * @note   ADC conversion data full-scale corresponds to voltage range\n  *         determined by analog voltage references Vref+ and Vref-\n  *         (refer to reference manual).\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval ADC conversion data equivalent voltage value (unit: mVolt)\n  */\n#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \\\n  (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))\n\n/**\n  * @brief  Helper macro to convert the ADC conversion data from\n  *         a resolution to another resolution.\n  * @param  __DATA__ ADC conversion data to be converted \n  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted\n  *         This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion\n  *         This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval ADC conversion data to the requested resolution\n  */\n#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\\\n                                         __ADC_RESOLUTION_CURRENT__,\\\n                                         __ADC_RESOLUTION_TARGET__)            \\\n  (((__DATA__)                                                                 \\\n    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U)))    \\\n   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U))       \\\n  )\n\n/**\n  * @brief  Helper macro to calculate the voltage (unit: mVolt)\n  *         corresponding to a ADC conversion data (unit: digital value).\n  * @note   Analog reference voltage (Vref+) must be either known from\n  *         user board environment or can be calculated using ADC measurement\n  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\n  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)\n  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)\n  *                       (unit: digital value).\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval ADC conversion data equivalent voltage value (unit: mVolt)\n  */\n#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\\\n                                      __ADC_DATA__,\\\n                                      __ADC_RESOLUTION__)                      \\\n  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \\\n   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \\\n  )\n\n/* Legacy define */\n#define __LL_ADC_CALC_DATA_VOLTAGE()  __LL_ADC_CALC_DATA_TO_VOLTAGE()\n\n/**\n  * @brief  Helper macro to calculate analog reference voltage (Vref+)\n  *         (unit: mVolt) from ADC conversion data of internal voltage\n  *         reference VrefInt.\n  * @note   Computation is using VrefInt calibration value\n  *         stored in system memory for each device during production.\n  * @note   This voltage depends on user board environment: voltage level\n  *         connected to pin Vref+.\n  *         On devices with small package, the pin Vref+ is not present\n  *         and internally bonded to pin Vdda.\n  * @note   On this STM32 serie, calibration data of internal voltage reference\n  *         VrefInt corresponds to a resolution of 12 bits,\n  *         this is the recommended ADC resolution to convert voltage of\n  *         internal voltage reference VrefInt.\n  *         Otherwise, this macro performs the processing to scale\n  *         ADC conversion data to 12 bits.\n  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)\n  *         of internal voltage reference VrefInt (unit: digital value).\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval Analog reference voltage (unit: mV)\n  */\n#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\\\n                                         __ADC_RESOLUTION__)                   \\\n  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \\\n    / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \\\n                                       (__ADC_RESOLUTION__),                   \\\n                                       LL_ADC_RESOLUTION_12B)                  \\\n  )\n\n/**\n  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)\n  *         from ADC conversion data of internal temperature sensor.\n  * @note   Computation is using temperature sensor calibration values\n  *         stored in system memory for each device during production.\n  * @note   Calculation formula:\n  *           Temperature = ((TS_ADC_DATA - TS_CAL1)\n  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))\n  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP\n  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC\n  *                Avg_Slope = (TS_CAL2 - TS_CAL1)\n  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)\n  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature\n  *                            TEMP_DEGC_CAL1 (calibrated in factory)\n  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature\n  *                            TEMP_DEGC_CAL2 (calibrated in factory)\n  *         Caution: Calculation relevancy under reserve that calibration\n  *                  parameters are correct (address and data).\n  *                  To calculate temperature using temperature sensor\n  *                  datasheet typical values (generic values less, therefore\n  *                  less accurate than calibrated values),\n  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().\n  * @note   As calculation input, the analog reference voltage (Vref+) must be\n  *         defined as it impacts the ADC LSB equivalent voltage.\n  * @note   Analog reference voltage (Vref+) must be either known from\n  *         user board environment or can be calculated using ADC measurement\n  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\n  * @note   On this STM32 serie, calibration data of temperature sensor\n  *         corresponds to a resolution of 12 bits,\n  *         this is the recommended ADC resolution to convert voltage of\n  *         temperature sensor.\n  *         Otherwise, this macro performs the processing to scale\n  *         ADC conversion data to 12 bits.\n  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)\n  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal\n  *                                 temperature sensor (unit: digital value).\n  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature\n  *                                 sensor voltage has been measured.\n  *         This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval Temperature (unit: degree Celsius)\n  */\n#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\\\n                                  __TEMPSENSOR_ADC_DATA__,\\\n                                  __ADC_RESOLUTION__)                              \\\n  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \\\n                                                    (__ADC_RESOLUTION__),          \\\n                                                    LL_ADC_RESOLUTION_12B)         \\\n                   * (__VREFANALOG_VOLTAGE__))                                     \\\n                  / TEMPSENSOR_CAL_VREFANALOG)                                     \\\n        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \\\n     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \\\n    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \\\n   ) + TEMPSENSOR_CAL1_TEMP                                                        \\\n  )\n\n/**\n  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)\n  *         from ADC conversion data of internal temperature sensor.\n  * @note   Computation is using temperature sensor typical values\n  *         (refer to device datasheet).\n  * @note   Calculation formula:\n  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)\n  *                         / Avg_Slope + CALx_TEMP\n  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC\n  *                                   (unit: digital value)\n  *                Avg_Slope        = temperature sensor slope\n  *                                   (unit: uV/Degree Celsius)\n  *                TS_TYP_CALx_VOLT = temperature sensor digital value at\n  *                                   temperature CALx_TEMP (unit: mV)\n  *         Caution: Calculation relevancy under reserve the temperature sensor\n  *                  of the current device has characteristics in line with\n  *                  datasheet typical values.\n  *                  If temperature sensor calibration values are available on\n  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),\n  *                  temperature calculation will be more accurate using\n  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().\n  * @note   As calculation input, the analog reference voltage (Vref+) must be\n  *         defined as it impacts the ADC LSB equivalent voltage.\n  * @note   Analog reference voltage (Vref+) must be either known from\n  *         user board environment or can be calculated using ADC measurement\n  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\n  * @note   ADC measurement data must correspond to a resolution of 12bits\n  *         (full scale digital value 4095). If not the case, the data must be\n  *         preliminarily rescaled to an equivalent resolution of 12 bits.\n  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).\n  *                                       On STM32L4, refer to device datasheet parameter \"Avg_Slope\".\n  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).\n  *                                       On STM32L4, refer to device datasheet parameter \"V30\" (corresponding to TS_CAL1).\n  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)\n  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)\n  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).\n  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.\n  *         This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval Temperature (unit: degree Celsius)\n  */\n#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\\\n                                             __TEMPSENSOR_TYP_CALX_V__,\\\n                                             __TEMPSENSOR_CALX_TEMP__,\\\n                                             __VREFANALOG_VOLTAGE__,\\\n                                             __TEMPSENSOR_ADC_DATA__,\\\n                                             __ADC_RESOLUTION__)               \\\n  ((( (                                                                        \\\n       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \\\n                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \\\n                 * 1000)                                                       \\\n       -                                                                       \\\n       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \\\n                 * 1000)                                                       \\\n      )                                                                        \\\n    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \\\n   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \\\n  )\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions\n  * @{\n  */\n\n/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management\n  * @{\n  */\n/* Note: LL ADC functions to set DMA transfer are located into sections of    */\n/*       configuration of ADC instance, groups and multimode (if available):  */\n/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */\n\n/**\n  * @brief  Function to help to configure DMA transfer from ADC: retrieve the\n  *         ADC register address from ADC instance and a list of ADC registers\n  *         intended to be used (most commonly) with DMA transfer.\n  * @note   These ADC registers are data registers:\n  *         when ADC conversion data is available in ADC data registers,\n  *         ADC generates a DMA transfer request.\n  * @note   This macro is intended to be used with LL DMA driver, refer to\n  *         function \"LL_DMA_ConfigAddresses()\".\n  *         Example:\n  *           LL_DMA_ConfigAddresses(DMA1,\n  *                                  LL_DMA_CHANNEL_1,\n  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),\n  *                                  (uint32_t)&< array or variable >,\n  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);\n  * @note   For devices with several ADC: in multimode, some devices\n  *         use a different data register outside of ADC instance scope\n  *         (common data register). This macro manages this register difference,\n  *         only ADC instance has to be set as parameter.\n  * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\\n\n  *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\\n\n  *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr\n  * @param  ADCx ADC instance\n  * @param  Register This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA\n  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)\n  *         \n  *         (1) Available on devices with several ADC instances.\n  * @retval ADC register address\n  */\n#if defined(ADC_MULTIMODE_SUPPORT)\n__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)\n{\n  register uint32_t data_reg_addr = 0U;\n  \n  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)\n  {\n    /* Retrieve address of register DR */\n    data_reg_addr = (uint32_t)&(ADCx->DR);\n  }\n  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */\n  {\n    /* Retrieve address of register CDR */\n    data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);\n  }\n  \n  return data_reg_addr;\n}\n#else\n__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)\n{\n  /* Retrieve address of register DR */\n  return (uint32_t)&(ADCx->DR);\n}\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances\n  * @{\n  */\n\n/**\n  * @brief  Set parameter common to several ADC: Clock source and prescaler.\n  * @note   On this STM32 serie, if ADC group injected is used, some\n  *         clock ratio constraints between ADC clock and AHB clock\n  *         must be respected.\n  *         Refer to reference manual.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         All ADC instances of the ADC common group must be disabled.\n  *         This check can be done with function @ref LL_ADC_IsEnabled() for each\n  *         ADC instance or by using helper macro helper macro\n  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().\n  * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\\n\n  *         CCR      PRESC          LL_ADC_SetCommonClock\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  CommonClock This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);\n}\n\n/**\n  * @brief  Get parameter common to several ADC: Clock source and prescaler.\n  * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\\n\n  *         CCR      PRESC          LL_ADC_GetCommonClock\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128\n  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));\n}\n\n/**\n  * @brief  Set parameter common to several ADC: measurement path to internal\n  *         channels (VrefInt, temperature sensor, ...).\n  * @note   One or several values can be selected.\n  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |\n  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)\n  * @note   Stabilization time of measurement path to internal channel:\n  *         After enabling internal paths, before starting ADC conversion,\n  *         a delay is required for internal voltage reference and\n  *         temperature sensor stabilization time.\n  *         Refer to device datasheet.\n  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.\n  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.\n  * @note   ADC internal channel sampling time constraint:\n  *         For ADC conversion of internal channels,\n  *         a sampling time minimum value is required.\n  *         Refer to device datasheet.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         All ADC instances of the ADC common group must be disabled.\n  *         This check can be done with function @ref LL_ADC_IsEnabled() for each\n  *         ADC instance or by using helper macro helper macro\n  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().\n  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\\n\n  *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\\n\n  *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  PathInternal This parameter can be a combination of the following values:\n  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE\n  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT\n  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR\n  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);\n}\n\n/**\n  * @brief  Get parameter common to several ADC: measurement path to internal\n  *         channels (VrefInt, temperature sensor, ...).\n  * @note   One or several values can be selected.\n  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |\n  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)\n  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\\n\n  *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\\n\n  *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be a combination of the following values:\n  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE\n  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT\n  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR\n  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance\n  * @{\n  */\n\n/**\n  * @brief  Set ADC calibration factor in the mode single-ended\n  *         or differential (for devices with differential mode available).\n  * @note   This function is intended to set calibration parameters\n  *         without having to perform a new calibration using\n  *         @ref LL_ADC_StartCalibration().\n  * @note   For devices with differential mode available:\n  *         Calibration of offset is specific to each of\n  *         single-ended and differential modes\n  *         (calibration factor must be specified for each of these\n  *         differential modes, if used afterwards and if the application\n  *         requires their calibration).\n  * @note   In case of setting calibration factors of both modes single ended\n  *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):\n  *         both calibration factors must be concatenated.\n  *         To perform this processing, use helper macro\n  *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be enabled, without calibration on going, without conversion\n  *         on going on group regular.\n  * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\\n\n  *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor\n  * @param  ADCx ADC instance\n  * @param  SingleDiff This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_SINGLE_ENDED\n  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED\n  *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED\n  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)\n{\n#if defined(CORE_CM0PLUS)\n  MODIFY_REG(ADCx->CALFACT,\n             SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,\n             CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));\n#else\n  MODIFY_REG(ADCx->CALFACT,\n             SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,\n             CalibrationFactor << POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));\n#endif\n}\n\n/**\n  * @brief  Get ADC calibration factor in the mode single-ended\n  *         or differential (for devices with differential mode available).\n  * @note   Calibration factors are set by hardware after performing\n  *         a calibration run using function @ref LL_ADC_StartCalibration().\n  * @note   For devices with differential mode available:\n  *         Calibration of offset is specific to each of\n  *         single-ended and differential modes\n  * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\\n\n  *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor\n  * @param  ADCx ADC instance\n  * @param  SingleDiff This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_SINGLE_ENDED\n  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED\n  * @retval Value between Min_Data=0x00 and Max_Data=0x7F\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)\n{\n  /* Retrieve bits with position in register depending on parameter           */\n  /* \"SingleDiff\".                                                            */\n  /* Parameter used with mask \"ADC_SINGLEDIFF_CALIB_FACTOR_MASK\" because      */\n  /* containing other bits reserved for other purpose.                        */\n#if defined(CORE_CM0PLUS)\n  return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));\n#else\n  return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> POSITION_VAL(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK));\n#endif\n}\n\n/**\n  * @brief  Set ADC resolution.\n  *         Refer to reference manual for alignments formats\n  *         dependencies to ADC resolutions.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     RES            LL_ADC_SetResolution\n  * @param  ADCx ADC instance\n  * @param  Resolution This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);\n}\n\n/**\n  * @brief  Get ADC resolution.\n  *         Refer to reference manual for alignments formats\n  *         dependencies to ADC resolutions.\n  * @rmtoll CFGR     RES            LL_ADC_GetResolution\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));\n}\n\n/**\n  * @brief  Set ADC conversion data alignment.\n  * @note   Refer to reference manual for alignments formats\n  *         dependencies to ADC resolutions.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment\n  * @param  ADCx ADC instance\n  * @param  DataAlignment This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT\n  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);\n}\n\n/**\n  * @brief  Get ADC conversion data alignment.\n  * @note   Refer to reference manual for alignments formats\n  *         dependencies to ADC resolutions.\n  * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT\n  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));\n}\n\n/**\n  * @brief  Set ADC low power mode.\n  * @note   Description of ADC low power modes:\n  *         - ADC low power mode \"auto wait\": Dynamic low power mode,\n  *           ADC conversions occurrences are limited to the minimum necessary\n  *           in order to reduce power consumption.\n  *           New ADC conversion starts only when the previous\n  *           unitary conversion data (for ADC group regular)\n  *           or previous sequence conversions data (for ADC group injected)\n  *           has been retrieved by user software.\n  *           In the meantime, ADC remains idle: does not performs any\n  *           other conversion.\n  *           This mode allows to automatically adapt the ADC conversions\n  *           triggers to the speed of the software that reads the data.\n  *           Moreover, this avoids risk of overrun for low frequency\n  *           applications.\n  *           How to use this low power mode:\n  *           - Do not use with interruption or DMA since these modes\n  *             have to clear immediately the EOC flag to free the\n  *             IRQ vector sequencer.\n  *           - Do use with polling: 1. Start conversion,\n  *             2. Later on, when conversion data is needed: poll for end of\n  *             conversion  to ensure that conversion is completed and\n  *             retrieve ADC conversion data. This will trig another\n  *             ADC conversion start.\n  *         - ADC low power mode \"auto power-off\" (feature available on\n  *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):\n  *           the ADC automatically powers-off after a conversion and\n  *           automatically wakes up when a new conversion is triggered\n  *           (with startup time between trigger and start of sampling).\n  *           This feature can be combined with low power mode \"auto wait\".\n  * @note   With ADC low power mode \"auto wait\", the ADC conversion data read\n  *         is corresponding to previous ADC conversion start, independently\n  *         of delay during which ADC was idle.\n  *         Therefore, the ADC conversion data may be outdated: does not\n  *         correspond to the current voltage level on the selected\n  *         ADC channel.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode\n  * @param  ADCx ADC instance\n  * @param  LowPowerMode This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_LP_MODE_NONE\n  *         @arg @ref LL_ADC_LP_AUTOWAIT\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);\n}\n\n/**\n  * @brief  Get ADC low power mode:\n  * @note   Description of ADC low power modes:\n  *         - ADC low power mode \"auto wait\": Dynamic low power mode,\n  *           ADC conversions occurrences are limited to the minimum necessary\n  *           in order to reduce power consumption.\n  *           New ADC conversion starts only when the previous\n  *           unitary conversion data (for ADC group regular)\n  *           or previous sequence conversions data (for ADC group injected)\n  *           has been retrieved by user software.\n  *           In the meantime, ADC remains idle: does not performs any\n  *           other conversion.\n  *           This mode allows to automatically adapt the ADC conversions\n  *           triggers to the speed of the software that reads the data.\n  *           Moreover, this avoids risk of overrun for low frequency\n  *           applications.\n  *           How to use this low power mode:\n  *           - Do not use with interruption or DMA since these modes\n  *             have to clear immediately the EOC flag to free the\n  *             IRQ vector sequencer.\n  *           - Do use with polling: 1. Start conversion,\n  *             2. Later on, when conversion data is needed: poll for end of\n  *             conversion  to ensure that conversion is completed and\n  *             retrieve ADC conversion data. This will trig another\n  *             ADC conversion start.\n  *         - ADC low power mode \"auto power-off\" (feature available on\n  *           this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):\n  *           the ADC automatically powers-off after a conversion and\n  *           automatically wakes up when a new conversion is triggered\n  *           (with startup time between trigger and start of sampling).\n  *           This feature can be combined with low power mode \"auto wait\".\n  * @note   With ADC low power mode \"auto wait\", the ADC conversion data read\n  *         is corresponding to previous ADC conversion start, independently\n  *         of delay during which ADC was idle.\n  *         Therefore, the ADC conversion data may be outdated: does not\n  *         correspond to the current voltage level on the selected\n  *         ADC channel.\n  * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_LP_MODE_NONE\n  *         @arg @ref LL_ADC_LP_AUTOWAIT\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));\n}\n\n/**\n  * @brief  Set ADC selected offset number 1, 2, 3 or 4.\n  * @note   This function set the 2 items of offset configuration:\n  *         - ADC channel to which the offset programmed will be applied\n  *           (independently of channel mapped on ADC group regular\n  *           or group injected)\n  *         - Offset level (offset to be subtracted from the raw\n  *           converted data).\n  * @note   Caution: Offset format is dependent to ADC resolution:\n  *         offset has to be left-aligned on bit 11, the LSB (right bits)\n  *         are set to 0.\n  * @note   This function enables the offset, by default. It can be forced\n  *         to disable state using function LL_ADC_SetOffsetState().\n  * @note   If a channel is mapped on several offsets numbers, only the offset\n  *         with the lowest value is considered for the subtraction.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @note   On STM32L4, some fast channels are available: fast analog inputs\n  *         coming from GPIO pads (ADC_IN1..5).\n  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\\n\n  *         OFR1     OFFSET1        LL_ADC_SetOffset\\n\n  *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\\n\n  *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\\n\n  *         OFR2     OFFSET2        LL_ADC_SetOffset\\n\n  *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\\n\n  *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\\n\n  *         OFR3     OFFSET3        LL_ADC_SetOffset\\n\n  *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\\n\n  *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\\n\n  *         OFR4     OFFSET4        LL_ADC_SetOffset\\n\n  *         OFR4     OFFSET4_EN     LL_ADC_SetOffset\n  * @param  ADCx ADC instance\n  * @param  Offsety This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OFFSET_1\n  *         @arg @ref LL_ADC_OFFSET_2\n  *         @arg @ref LL_ADC_OFFSET_3\n  *         @arg @ref LL_ADC_OFFSET_4\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)\n{\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\n  \n  MODIFY_REG(*preg,\n             ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,\n             ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);\n}\n\n/**\n  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:\n  *         Channel to which the offset programmed will be applied\n  *         (independently of channel mapped on ADC group regular\n  *         or group injected)\n  * @note   Usage of the returned channel number:\n  *         - To reinject this channel into another function LL_ADC_xxx:\n  *           the returned channel number is only partly formatted on definition\n  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\n  *           with parts of literals LL_ADC_CHANNEL_x or using\n  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Then the selected literal LL_ADC_CHANNEL_x can be used\n  *           as parameter for another function.\n  *         - To get the channel number in decimal format:\n  *           process the returned value with the helper macro\n  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  * @note   On STM32L4, some fast channels are available: fast analog inputs\n  *         coming from GPIO pads (ADC_IN1..5).\n  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\\n\n  *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\\n\n  *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\\n\n  *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel\n  * @param  ADCx ADC instance\n  * @param  Offsety This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OFFSET_1\n  *         @arg @ref LL_ADC_OFFSET_2\n  *         @arg @ref LL_ADC_OFFSET_3\n  *         @arg @ref LL_ADC_OFFSET_4\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\\n\n  *         (1, 2, 3, 4) For ADC channel read back from ADC register,\n  *                      comparison with internal channel parameter to be done\n  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)\n{\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\n  \n  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);\n}\n\n/**\n  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:\n  *         Offset level (offset to be subtracted from the raw\n  *         converted data).\n  * @note   Caution: Offset format is dependent to ADC resolution:\n  *         offset has to be left-aligned on bit 11, the LSB (right bits)\n  *         are set to 0.\n  * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\\n\n  *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\\n\n  *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\\n\n  *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel\n  * @param  ADCx ADC instance\n  * @param  Offsety This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OFFSET_1\n  *         @arg @ref LL_ADC_OFFSET_2\n  *         @arg @ref LL_ADC_OFFSET_3\n  *         @arg @ref LL_ADC_OFFSET_4\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)\n{\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\n  \n  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);\n}\n\n/**\n  * @brief  Set for the ADC selected offset number 1, 2, 3 or 4:\n  *         force offset state disable or enable\n  *         without modifying offset channel or offset value.\n  * @note   This function should be needed only in case of offset to be\n  *         enabled-disabled dynamically, and should not be needed in other cases:\n  *         function LL_ADC_SetOffset() automatically enables the offset.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\\n\n  *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\\n\n  *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\\n\n  *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState\n  * @param  ADCx ADC instance\n  * @param  Offsety This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OFFSET_1\n  *         @arg @ref LL_ADC_OFFSET_2\n  *         @arg @ref LL_ADC_OFFSET_3\n  *         @arg @ref LL_ADC_OFFSET_4\n  * @param  OffsetState This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OFFSET_DISABLE\n  *         @arg @ref LL_ADC_OFFSET_ENABLE\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)\n{\n  register uint32_t *preg = (uint32_t *)((uint32_t)\n                            ((uint32_t)(&ADCx->OFR1) + (Offsety*4U)));\n  \n  MODIFY_REG(*preg,\n             ADC_OFR1_OFFSET1_EN,\n             OffsetState);\n}\n\n/**\n  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:\n  *         offset state disabled or enabled.\n  * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\\n\n  *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\\n\n  *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\\n\n  *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState\n  * @param  ADCx ADC instance\n  * @param  Offsety This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OFFSET_1\n  *         @arg @ref LL_ADC_OFFSET_2\n  *         @arg @ref LL_ADC_OFFSET_3\n  *         @arg @ref LL_ADC_OFFSET_4\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_OFFSET_DISABLE\n  *         @arg @ref LL_ADC_OFFSET_ENABLE\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)\n{\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);\n  \n  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);\n}\n\n#if defined(ADC_SMPR1_SMPPLUS)\n/**\n  * @brief  Set ADC sampling time common configuration impacting\n  *         settings of sampling time channel wise.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll SMPR1    SMPPLUS        LL_ADC_SetSamplingTimeCommonConfig\n  * @param  ADCx ADC instance\n  * @param  SamplingTimeCommonConfig This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT\n  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)\n{\n  MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);\n}\n\n/**\n  * @brief  Get ADC sampling time common configuration impacting\n  *         settings of sampling time channel wise.\n  * @rmtoll SMPR1    SMPPLUS        LL_ADC_GetSamplingTimeCommonConfig\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT\n  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));\n}\n#endif /* ADC_SMPR1_SMPPLUS */\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular\n  * @{\n  */\n\n/**\n  * @brief  Set ADC group regular conversion trigger source:\n  *         internal (SW start) or from external IP (timer event,\n  *         external interrupt line).\n  * @note   On this STM32 serie, setting trigger source to external trigger\n  *         also set trigger polarity to rising edge \n  *         (default setting for compatibility with some ADC on other\n  *         STM32 families having this setting set by HW default value).\n  *         In case of need to modify trigger edge, use\n  *         function @ref LL_ADC_REG_SetTriggerEdge().\n  * @note   Availability of parameters of trigger sources from timer \n  *         depends on timers availability on the selected device.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on group regular.\n  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\\n\n  *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource\n  * @param  ADCx ADC instance\n  * @param  TriggerSource This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);\n}\n\n/**\n  * @brief  Get ADC group regular conversion trigger source:\n  *         internal (SW start) or from external IP (timer event,\n  *         external interrupt line).\n  * @note   To determine whether group regular trigger source is\n  *         internal (SW start) or external, without detail\n  *         of which peripheral is selected as external trigger,\n  *         (equivalent to \n  *         \"if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)\")\n  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.\n  * @note   Availability of parameters of trigger sources from timer \n  *         depends on timers availability on the selected device.\n  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\\n\n  *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)\n{\n  register uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);\n  \n  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */\n  /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */\n  register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));\n  \n  /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */\n  /* to match with triggers literals definition.                              */\n  return ((TriggerSource\n           & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)\n          | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)\n         );\n}\n\n/**\n  * @brief  Get ADC group regular conversion trigger source internal (SW start)\n            or external.\n  * @note   In case of group regular trigger source set to external trigger,\n  *         to determine which peripheral is selected as external trigger,\n  *         use function @ref LL_ADC_REG_GetTriggerSource().\n  * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart\n  * @param  ADCx ADC instance\n  * @retval Value \"0\" if trigger source external trigger\n  *         Value \"1\" if trigger source SW start.\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN));\n}\n\n/**\n  * @brief  Set ADC group regular conversion trigger polarity.\n  * @note   Applicable only for trigger source set to external trigger.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on group regular.\n  * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge\n  * @param  ADCx ADC instance\n  * @param  ExternalTriggerEdge This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);\n}\n\n/**\n  * @brief  Get ADC group regular conversion trigger polarity.\n  * @note   Applicable only for trigger source set to external trigger.\n  * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));\n}\n\n/**\n  * @brief  Set ADC group regular sequencer length and scan direction.\n  * @note   Description of ADC group regular sequencer features:\n  *         - For devices with sequencer fully configurable\n  *           (function \"LL_ADC_REG_SetSequencerRanks()\" available):\n  *           sequencer length and each rank affectation to a channel\n  *           are configurable.\n  *           This function performs configuration of:\n  *           - Sequence length: Number of ranks in the scan sequence.\n  *           - Sequence direction: Unless specified in parameters, sequencer\n  *             scan direction is forward (from rank 1 to rank n).\n  *           Sequencer ranks are selected using\n  *           function \"LL_ADC_REG_SetSequencerRanks()\".\n  *         - For devices with sequencer not fully configurable\n  *           (function \"LL_ADC_REG_SetSequencerChannels()\" available):\n  *           sequencer length and each rank affectation to a channel\n  *           are defined by channel number.\n  *           This function performs configuration of:\n  *           - Sequence length: Number of ranks in the scan sequence is\n  *             defined by number of channels set in the sequence,\n  *             rank of each channel is fixed by channel HW number.\n  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).\n  *           - Sequence direction: Unless specified in parameters, sequencer\n  *             scan direction is forward (from lowest channel number to\n  *             highest channel number).\n  *           Sequencer ranks are selected using\n  *           function \"LL_ADC_REG_SetSequencerChannels()\".\n  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:\n  *         ADC conversion on only 1 channel.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on group regular.\n  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength\n  * @param  ADCx ADC instance\n  * @param  SequencerNbRanks This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)\n{\n  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);\n}\n\n/**\n  * @brief  Get ADC group regular sequencer length and scan direction.\n  * @note   Description of ADC group regular sequencer features:\n  *         - For devices with sequencer fully configurable\n  *           (function \"LL_ADC_REG_SetSequencerRanks()\" available):\n  *           sequencer length and each rank affectation to a channel\n  *           are configurable.\n  *           This function retrieves:\n  *           - Sequence length: Number of ranks in the scan sequence.\n  *           - Sequence direction: Unless specified in parameters, sequencer\n  *             scan direction is forward (from rank 1 to rank n).\n  *           Sequencer ranks are selected using\n  *           function \"LL_ADC_REG_SetSequencerRanks()\".\n  *         - For devices with sequencer not fully configurable\n  *           (function \"LL_ADC_REG_SetSequencerChannels()\" available):\n  *           sequencer length and each rank affectation to a channel\n  *           are defined by channel number.\n  *           This function retrieves:\n  *           - Sequence length: Number of ranks in the scan sequence is\n  *             defined by number of channels set in the sequence,\n  *             rank of each channel is fixed by channel HW number.\n  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).\n  *           - Sequence direction: Unless specified in parameters, sequencer\n  *             scan direction is forward (from lowest channel number to\n  *             highest channel number).\n  *           Sequencer ranks are selected using\n  *           function \"LL_ADC_REG_SetSequencerChannels()\".\n  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:\n  *         ADC conversion on only 1 channel.\n  * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));\n}\n\n/**\n  * @brief  Set ADC group regular sequencer discontinuous mode:\n  *         sequence subdivided and scan conversions interrupted every selected\n  *         number of ranks.\n  * @note   It is not possible to enable both ADC group regular \n  *         continuous mode and sequencer discontinuous mode.\n  * @note   It is not possible to enable both ADC auto-injected mode\n  *         and ADC group regular sequencer discontinuous mode.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on group regular.\n  * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\\n\n  *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont\n  * @param  ADCx ADC instance\n  * @param  SeqDiscont This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);\n}\n\n/**\n  * @brief  Get ADC group regular sequencer discontinuous mode:\n  *         sequence subdivided and scan conversions interrupted every selected\n  *         number of ranks.\n  * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\\n\n  *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));\n}\n\n/**\n  * @brief  Set ADC group regular sequence: channel on the selected\n  *         scan sequence rank.\n  * @note   This function performs configuration of:\n  *         - Channels ordering into each rank of scan sequence:\n  *           whatever channel can be placed into whatever rank.\n  * @note   On this STM32 serie, ADC group regular sequencer is\n  *         fully configurable: sequencer length and each rank\n  *         affectation to a channel are configurable.\n  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().\n  * @note   Depending on devices and packages, some channels may not be available.\n  *         Refer to device datasheet for channels availability.\n  * @note   On this STM32 serie, to measure internal channels (VrefInt,\n  *         TempSensor, ...), measurement paths to internal channels must be\n  *         enabled separately.\n  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on group regular.\n  * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_RANK_1\n  *         @arg @ref LL_ADC_REG_RANK_2\n  *         @arg @ref LL_ADC_REG_RANK_3\n  *         @arg @ref LL_ADC_REG_RANK_4\n  *         @arg @ref LL_ADC_REG_RANK_5\n  *         @arg @ref LL_ADC_REG_RANK_6\n  *         @arg @ref LL_ADC_REG_RANK_7\n  *         @arg @ref LL_ADC_REG_RANK_8\n  *         @arg @ref LL_ADC_REG_RANK_9\n  *         @arg @ref LL_ADC_REG_RANK_10\n  *         @arg @ref LL_ADC_REG_RANK_11\n  *         @arg @ref LL_ADC_REG_RANK_12\n  *         @arg @ref LL_ADC_REG_RANK_13\n  *         @arg @ref LL_ADC_REG_RANK_14\n  *         @arg @ref LL_ADC_REG_RANK_15\n  *         @arg @ref LL_ADC_REG_RANK_16\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)\n{\n  /* Set bits with content of parameter \"Channel\" with bits position          */\n  /* in register and register position depending on parameter \"Rank\".         */\n  /* Parameters \"Rank\" and \"Channel\" are used with masks because containing   */\n  /* other bits reserved for other purpose.                                   */\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));\n#endif\n  \n  MODIFY_REG(*preg,\n             ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),\n             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));\n}\n\n/**\n  * @brief  Get ADC group regular sequence: channel on the selected\n  *         scan sequence rank.\n  * @note   On this STM32 serie, ADC group regular sequencer is\n  *         fully configurable: sequencer length and each rank\n  *         affectation to a channel are configurable.\n  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().\n  * @note   Depending on devices and packages, some channels may not be available.\n  *         Refer to device datasheet for channels availability.\n  * @note   Usage of the returned channel number:\n  *         - To reinject this channel into another function LL_ADC_xxx:\n  *           the returned channel number is only partly formatted on definition\n  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\n  *           with parts of literals LL_ADC_CHANNEL_x or using\n  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Then the selected literal LL_ADC_CHANNEL_x can be used\n  *           as parameter for another function.\n  *         - To get the channel number in decimal format:\n  *           process the returned value with the helper macro\n  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_RANK_1\n  *         @arg @ref LL_ADC_REG_RANK_2\n  *         @arg @ref LL_ADC_REG_RANK_3\n  *         @arg @ref LL_ADC_REG_RANK_4\n  *         @arg @ref LL_ADC_REG_RANK_5\n  *         @arg @ref LL_ADC_REG_RANK_6\n  *         @arg @ref LL_ADC_REG_RANK_7\n  *         @arg @ref LL_ADC_REG_RANK_8\n  *         @arg @ref LL_ADC_REG_RANK_9\n  *         @arg @ref LL_ADC_REG_RANK_10\n  *         @arg @ref LL_ADC_REG_RANK_11\n  *         @arg @ref LL_ADC_REG_RANK_12\n  *         @arg @ref LL_ADC_REG_RANK_13\n  *         @arg @ref LL_ADC_REG_RANK_14\n  *         @arg @ref LL_ADC_REG_RANK_15\n  *         @arg @ref LL_ADC_REG_RANK_16\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\\n\n  *         (1, 2, 3, 4) For ADC channel read back from ADC register,\n  *                      comparison with internal channel parameter to be done\n  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));\n#endif\n  \n  return (uint32_t) ((READ_BIT(*preg,\n                              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))\n                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS\n                    );\n}\n\n/**\n  * @brief  Set ADC continuous conversion mode on ADC group regular.\n  * @note   Description of ADC continuous conversion mode:\n  *         - single mode: one conversion per trigger\n  *         - continuous mode: after the first trigger, following\n  *           conversions launched successively automatically.\n  * @note   It is not possible to enable both ADC group regular \n  *         continuous mode and sequencer discontinuous mode.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on group regular.\n  * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode\n  * @param  ADCx ADC instance\n  * @param  Continuous This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_CONV_SINGLE\n  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);\n}\n\n/**\n  * @brief  Get ADC continuous conversion mode on ADC group regular.\n  * @note   Description of ADC continuous conversion mode:\n  *         - single mode: one conversion per trigger\n  *         - continuous mode: after the first trigger, following\n  *           conversions launched successively automatically.\n  * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_CONV_SINGLE\n  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));\n}\n\n/**\n  * @brief  Set ADC group regular conversion data transfer: no transfer or\n  *         transfer by DMA, and DMA requests mode.\n  * @note   If transfer by DMA selected, specifies the DMA requests\n  *         mode:\n  *         - Limited mode (One shot mode): DMA transfer requests are stopped\n  *           when number of DMA data transfers (number of\n  *           ADC conversions) is reached.\n  *           This ADC mode is intended to be used with DMA mode non-circular.\n  *         - Unlimited mode: DMA transfer requests are unlimited,\n  *           whatever number of DMA data transfers (number of\n  *           ADC conversions).\n  *           This ADC mode is intended to be used with DMA mode circular.\n  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to\n  *         mode non-circular:\n  *         when DMA transfers size will be reached, DMA will stop transfers of\n  *         ADC conversions data ADC will raise an overrun error\n  *        (overrun flag and interruption if enabled).\n  * @note   For devices with several ADC instances: ADC multimode DMA\n  *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().\n  * @note   To configure DMA source address (peripheral address),\n  *         use function @ref LL_ADC_DMA_GetRegAddr().\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\\n\n  *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer\n  * @param  ADCx ADC instance\n  * @param  DMATransfer This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);\n}\n\n/**\n  * @brief  Get ADC group regular conversion data transfer: no transfer or\n  *         transfer by DMA, and DMA requests mode.\n  * @note   If transfer by DMA selected, specifies the DMA requests\n  *         mode:\n  *         - Limited mode (One shot mode): DMA transfer requests are stopped\n  *           when number of DMA data transfers (number of\n  *           ADC conversions) is reached.\n  *           This ADC mode is intended to be used with DMA mode non-circular.\n  *         - Unlimited mode: DMA transfer requests are unlimited,\n  *           whatever number of DMA data transfers (number of\n  *           ADC conversions).\n  *           This ADC mode is intended to be used with DMA mode circular.\n  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to\n  *         mode non-circular:\n  *         when DMA transfers size will be reached, DMA will stop transfers of\n  *         ADC conversions data ADC will raise an overrun error\n  *         (overrun flag and interruption if enabled).\n  * @note   For devices with several ADC instances: ADC multimode DMA\n  *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().\n  * @note   To configure DMA source address (peripheral address),\n  *         use function @ref LL_ADC_DMA_GetRegAddr().\n  * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\\n\n  *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));\n}\n\n#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)\n/**\n  * @brief  Set ADC group regular conversion data transfer to DFSDM.\n  * @note   DFSDM transfer cannot be used if DMA transfer is enabled.\n  * @note   To configure DFSDM source address (peripheral address),\n  *         use the same function as for DMA transfer:\n  *         function @ref LL_ADC_DMA_GetRegAddr().\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     DFSDMCFG       LL_ADC_REG_GetDFSDMTransfer\n  * @param  ADCx ADC instance\n  * @param  DFSDMTransfer This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE\n  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetDFSDMTransfer(ADC_TypeDef *ADCx, uint32_t DFSDMTransfer)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DFSDMCFG, DFSDMTransfer);\n}\n\n/**\n  * @brief  Get ADC group regular conversion data transfer to DFSDM.\n  * @rmtoll CFGR     DFSDMCFG       LL_ADC_REG_GetDFSDMTransfer\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER_NONE\n  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER_ENABLE\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetDFSDMTransfer(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));\n}\n#endif\n\n/**\n  * @brief  Set ADC group regular behavior in case of overrun:\n  *         data preserved or overwritten.\n  * @note   Compatibility with devices without feature overrun:\n  *         other devices without this feature have a behavior\n  *         equivalent to data overwritten.\n  *         The default setting of overrun is data preserved.\n  *         Therefore, for compatibility with all devices, parameter\n  *         overrun should be set to data overwritten.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on group regular.\n  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun\n  * @param  ADCx ADC instance\n  * @param  Overrun This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED\n  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);\n}\n\n/**\n  * @brief  Get ADC group regular behavior in case of overrun:\n  *         data preserved or overwritten.\n  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED\n  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected\n  * @{\n  */\n\n/**\n  * @brief  Set ADC group injected conversion trigger source:\n  *         internal (SW start) or from external IP (timer event,\n  *         external interrupt line).\n  * @note   On this STM32 serie, setting trigger source to external trigger\n  *         also set trigger polarity to rising edge \n  *         (default setting for compatibility with some ADC on other\n  *         STM32 families having this setting set by HW default value).\n  *         In case of need to modify trigger edge, use\n  *         function @ref LL_ADC_INJ_SetTriggerEdge().\n  * @note   Availability of parameters of trigger sources from timer \n  *         depends on timers availability on the selected device.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must not be disabled. Can be enabled with or without conversion\n  *         on going on either groups regular or injected.\n  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\\n\n  *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource\n  * @param  ADCx ADC instance\n  * @param  TriggerSource This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)\n{\n  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);\n}\n\n/**\n  * @brief  Get ADC group injected conversion trigger source:\n  *         internal (SW start) or from external IP (timer event,\n  *         external interrupt line).\n  * @note   To determine whether group injected trigger source is\n  *         internal (SW start) or external, without detail\n  *         of which peripheral is selected as external trigger,\n  *         (equivalent to \n  *         \"if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)\")\n  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.\n  * @note   Availability of parameters of trigger sources from timer \n  *         depends on timers availability on the selected device.\n  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\\n\n  *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)\n{\n  register uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);\n  \n  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */\n  /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */\n  register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));\n  \n  /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */\n  /* to match with triggers literals definition.                              */\n  return ((TriggerSource\n           & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)\n          | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)\n         );\n}\n\n/**\n  * @brief  Get ADC group injected conversion trigger source internal (SW start)\n            or external\n  * @note   In case of group injected trigger source set to external trigger,\n  *         to determine which peripheral is selected as external trigger,\n  *         use function @ref LL_ADC_INJ_GetTriggerSource.\n  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart\n  * @param  ADCx ADC instance\n  * @retval Value \"0\" if trigger source external trigger\n  *         Value \"1\" if trigger source SW start.\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN));\n}\n\n/**\n  * @brief  Set ADC group injected conversion trigger polarity.\n  *         Applicable only for trigger source set to external trigger.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must not be disabled. Can be enabled with or without conversion\n  *         on going on either groups regular or injected.\n  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge\n  * @param  ADCx ADC instance\n  * @param  ExternalTriggerEdge This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)\n{\n  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);\n}\n\n/**\n  * @brief  Get ADC group injected conversion trigger polarity.\n  *         Applicable only for trigger source set to external trigger.\n  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));\n}\n\n/**\n  * @brief  Set ADC group injected sequencer length and scan direction.\n  * @note   This function performs configuration of:\n  *         - Sequence length: Number of ranks in the scan sequence.\n  *         - Sequence direction: Unless specified in parameters, sequencer\n  *           scan direction is forward (from rank 1 to rank n).\n  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:\n  *         ADC conversion on only 1 channel.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must not be disabled. Can be enabled with or without conversion\n  *         on going on either groups regular or injected.\n  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength\n  * @param  ADCx ADC instance\n  * @param  SequencerNbRanks This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)\n{\n  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);\n}\n\n/**\n  * @brief  Get ADC group injected sequencer length and scan direction.\n  * @note   This function retrieves:\n  *         - Sequence length: Number of ranks in the scan sequence.\n  *         - Sequence direction: Unless specified in parameters, sequencer\n  *           scan direction is forward (from rank 1 to rank n).\n  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:\n  *         ADC conversion on only 1 channel.\n  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));\n}\n\n/**\n  * @brief  Set ADC group injected sequencer discontinuous mode:\n  *         sequence subdivided and scan conversions interrupted every selected\n  *         number of ranks.\n  * @note   It is not possible to enable both ADC group injected\n  *         auto-injected mode and sequencer discontinuous mode.\n  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont\n  * @param  ADCx ADC instance\n  * @param  SeqDiscont This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);\n}\n\n/**\n  * @brief  Get ADC group injected sequencer discontinuous mode:\n  *         sequence subdivided and scan conversions interrupted every selected\n  *         number of ranks.\n  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));\n}\n\n/**\n  * @brief  Set ADC group injected sequence: channel on the selected\n  *         sequence rank.\n  * @note   Depending on devices and packages, some channels may not be available.\n  *         Refer to device datasheet for channels availability.\n  * @note   On this STM32 serie, to measure internal channels (VrefInt,\n  *         TempSensor, ...), measurement paths to internal channels must be\n  *         enabled separately.\n  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().\n  * @note   On STM32L4, some fast channels are available: fast analog inputs\n  *         coming from GPIO pads (ADC_IN1..5).\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must not be disabled. Can be enabled with or without conversion\n  *         on going on either groups regular or injected.\n  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)\n{\n  /* Set bits with content of parameter \"Channel\" with bits position          */\n  /* in register depending on parameter \"Rank\".                               */\n  /* Parameters \"Rank\" and \"Channel\" are used with masks because containing   */\n  /* other bits reserved for other purpose.                                   */\n  MODIFY_REG(ADCx->JSQR,\n             (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),\n             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));\n}\n\n/**\n  * @brief  Get ADC group injected sequence: channel on the selected\n  *         sequence rank.\n  * @note   Depending on devices and packages, some channels may not be available.\n  *         Refer to device datasheet for channels availability.\n  * @note   Usage of the returned channel number:\n  *         - To reinject this channel into another function LL_ADC_xxx:\n  *           the returned channel number is only partly formatted on definition\n  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\n  *           with parts of literals LL_ADC_CHANNEL_x or using\n  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Then the selected literal LL_ADC_CHANNEL_x can be used\n  *           as parameter for another function.\n  *         - To get the channel number in decimal format:\n  *           process the returned value with the helper macro\n  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\\n\n  *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\\n\n  *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\\n\n  *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\\n\n  *         (1, 2, 3, 4) For ADC channel read back from ADC register,\n  *                      comparison with internal channel parameter to be done\n  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  return (uint32_t)((READ_BIT(ADCx->JSQR,\n                             (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))\n                    >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS\n                   );\n}\n\n/**\n  * @brief  Set ADC group injected conversion trigger:\n  *         independent or from ADC group regular.\n  * @note   This mode can be used to extend number of data registers\n  *         updated after one ADC conversion trigger and with data \n  *         permanently kept (not erased by successive conversions of scan of\n  *         ADC sequencer ranks), up to 5 data registers:\n  *         1 data register on ADC group regular, 4 data registers\n  *         on ADC group injected.            \n  * @note   If ADC group injected injected trigger source is set to an\n  *         external trigger, this feature must be must be set to\n  *         independent trigger.\n  *         ADC group injected automatic trigger is compliant only with \n  *         group injected trigger source set to SW start, without any \n  *         further action on  ADC group injected conversion start or stop: \n  *         in this case, ADC group injected is controlled only \n  *         from ADC group regular.\n  * @note   It is not possible to enable both ADC group injected\n  *         auto-injected mode and sequencer discontinuous mode.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto\n  * @param  ADCx ADC instance\n  * @param  TrigAuto This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT\n  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);\n}\n\n/**\n  * @brief  Get ADC group injected conversion trigger:\n  *         independent or from ADC group regular.\n  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT\n  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));\n}\n\n/**\n  * @brief  Set ADC group injected contexts queue mode.\n  * @note   A context is a setting of group injected sequencer:\n  *         - group injected trigger\n  *         - sequencer length\n  *         - sequencer ranks\n  *         If contexts queue is disabled:\n  *         - only 1 sequence can be configured\n  *           and is active perpetually.\n  *         If contexts queue is enabled:\n  *         - up to 2 contexts can be queued\n  *           and are checked in and out as a FIFO stack (first-in, first-out).\n  *         - If a new context is set when queues is full, error is triggered\n  *           by interruption \"Injected Queue Overflow\".\n  *         - Two behaviors are possible when all contexts have been processed:\n  *           the contexts queue can maintain the last context active perpetually\n  *           or can be empty and injected group triggers are disabled.\n  *         - Triggers can be only external (not internal SW start)\n  *         - Caution: The sequence must be fully configured in one time\n  *           (one write of register JSQR makes a check-in of a new context\n  *           into the queue).\n  *           Therefore functions to set separately injected trigger and\n  *           sequencer channels cannot be used, register JSQR must be set\n  *           using function @ref LL_ADC_INJ_ConfigQueueContext().\n  * @note   This parameter can be modified only when no conversion is on going\n  *         on either groups regular or injected.\n  * @note   A modification of the context mode (bit JQDIS) causes the contexts\n  *         queue to be flushed and the register JSQR is cleared.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\\n\n  *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode\n  * @param  ADCx ADC instance\n  * @param  QueueMode This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE\n  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE\n  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)\n{\n  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);\n}\n\n/**\n  * @brief  Get ADC group injected context queue mode.\n  * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\\n\n  *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE\n  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE\n  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));\n}\n\n/**\n  * @brief  Set one context on ADC group injected that will be checked in\n  *         contexts queue.\n  * @note   A context is a setting of group injected sequencer:\n  *         - group injected trigger\n  *         - sequencer length\n  *         - sequencer ranks\n  *         This function is intended to be used when contexts queue is enabled,\n  *         because the sequence must be fully configured in one time\n  *         (functions to set separately injected trigger and sequencer channels\n  *         cannot be used):\n  *         Refer to function @ref LL_ADC_INJ_SetQueueMode().\n  * @note   In the contexts queue, only the active context can be read.\n  *         The parameters of this function can be read using functions:\n  *         @arg @ref LL_ADC_INJ_GetTriggerSource()\n  *         @arg @ref LL_ADC_INJ_GetTriggerEdge()\n  *         @arg @ref LL_ADC_INJ_GetSequencerRanks()\n  * @note   On this STM32 serie, to measure internal channels (VrefInt,\n  *         TempSensor, ...), measurement paths to internal channels must be\n  *         enabled separately.\n  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().\n  * @note   On STM32L4, some fast channels are available: fast analog inputs\n  *         coming from GPIO pads (ADC_IN1..5).\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must not be disabled. Can be enabled with or without conversion\n  *         on going on either groups regular or injected.\n  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\\n\n  *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\\n\n  *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\\n\n  *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\\n\n  *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\\n\n  *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\\n\n  *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext\n  * @param  ADCx ADC instance\n  * @param  TriggerSource This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15\n  * @param  ExternalTriggerEdge This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING\n  *\n  *         Note: This parameter is discarded in case of SW start:\n  *               parameter \"TriggerSource\" set to \"LL_ADC_INJ_TRIG_SOFTWARE\".\n  * @param  SequencerNbRanks This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS\n  * @param  Rank1_Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @param  Rank2_Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @param  Rank3_Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @param  Rank4_Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,\n                                                   uint32_t TriggerSource,\n                                                   uint32_t ExternalTriggerEdge,\n                                                   uint32_t SequencerNbRanks,\n                                                   uint32_t Rank1_Channel,\n                                                   uint32_t Rank2_Channel,\n                                                   uint32_t Rank3_Channel,\n                                                   uint32_t Rank4_Channel)\n{\n  /* Set bits with content of parameter \"Rankx_Channel\" with bits position    */\n  /* in register depending on literal \"LL_ADC_INJ_RANK_x\".                    */\n  /* Parameters \"Rankx_Channel\" and \"LL_ADC_INJ_RANK_x\" are used with masks   */\n  /* because containing other bits reserved for other purpose.                */\n  /* If parameter \"TriggerSource\" is set to SW start, then parameter          */\n  /* \"ExternalTriggerEdge\" is discarded.                                      */\n  MODIFY_REG(ADCx->JSQR           ,\n             ADC_JSQR_JEXTSEL |\n             ADC_JSQR_JEXTEN  |\n             ADC_JSQR_JSQ4    |\n             ADC_JSQR_JSQ3    |\n             ADC_JSQR_JSQ2    |\n             ADC_JSQR_JSQ1    |\n             ADC_JSQR_JL          ,\n             TriggerSource       |\n             (ExternalTriggerEdge * ((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE))) |\n             (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |\n             (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |\n             (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |\n             (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |\n             SequencerNbRanks\n            );\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels\n  * @{\n  */\n\n/**\n  * @brief  Set sampling time of the selected ADC channel\n  *         Unit: ADC clock cycles.\n  * @note   On this device, sampling time is on channel scope: independently\n  *         of channel mapped on ADC group regular or injected.\n  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be\n  *         converted:\n  *         sampling time constraints must be respected (sampling time can be\n  *         adjusted in function of ADC clock frequency and sampling time\n  *         setting).\n  *         Refer to device datasheet for timings values (parameters TS_vrefint,\n  *         TS_temp, ...).\n  * @note   Conversion time is the addition of sampling time and processing time.\n  *         On this STM32 serie, ADC processing time is:\n  *         - 12.5 ADC clock cycles at ADC resolution 12 bits\n  *         - 10.5 ADC clock cycles at ADC resolution 10 bits\n  *         - 8.5 ADC clock cycles at ADC resolution 8 bits\n  *         - 6.5 ADC clock cycles at ADC resolution 6 bits\n  * @note   In case of ADC conversion of internal channel (VrefInt,\n  *         temperature sensor, ...), a sampling time minimum value\n  *         is required.\n  *         Refer to device datasheet.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime\n  * @param  ADCx ADC instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @param  SamplingTime This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)\n  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5\n  *\n  *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles\n  *             can be replaced by 3.5 ADC clock cycles.\n  *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)\n{\n  /* Set bits with content of parameter \"SamplingTime\" with bits position     */\n  /* in register and register position depending on parameter \"Channel\".      */\n  /* Parameter \"Channel\" is used with masks because containing                */\n  /* other bits reserved for other purpose.                                   */\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));\n  \n  MODIFY_REG(*preg,\n             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),\n             SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));\n  \n  MODIFY_REG(*preg,\n             ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),\n             SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));\n#endif\n}\n\n/**\n  * @brief  Get sampling time of the selected ADC channel\n  *         Unit: ADC clock cycles.\n  * @note   On this device, sampling time is on channel scope: independently\n  *         of channel mapped on ADC group regular or injected.\n  * @note   Conversion time is the addition of sampling time and processing time.\n  *         On this STM32 serie, ADC processing time is:\n  *         - 12.5 ADC clock cycles at ADC resolution 12 bits\n  *         - 10.5 ADC clock cycles at ADC resolution 10 bits\n  *         - 8.5 ADC clock cycles at ADC resolution 8 bits\n  *         - 6.5 ADC clock cycles at ADC resolution 6 bits\n  * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime\n  * @param  ADCx ADC instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1            (7)\n  *         @arg @ref LL_ADC_CHANNEL_2            (7)\n  *         @arg @ref LL_ADC_CHANNEL_3            (7)\n  *         @arg @ref LL_ADC_CHANNEL_4            (7)\n  *         @arg @ref LL_ADC_CHANNEL_5            (7)\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (4)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (4)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2         (5)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC3 (3)(6)\n  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC3 (3)(6)\n  *         \n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\\n\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\\n\n  *         (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).\n  *             Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)\n  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5\n  *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5\n  *\n  *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles\n  *             can be replaced by 3.5 ADC clock cycles.\n  *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)\n{\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));\n  \n  return (uint32_t)(READ_BIT(*preg,\n                             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))\n                    >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)\n                   );\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));\n  \n  return (uint32_t)(READ_BIT(*preg,\n                             ADC_SMPR1_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))\n                    >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)\n                   );\n#endif\n}\n\n/**\n  * @brief  Set mode single-ended or differential input of the selected\n  *         ADC channel.\n  * @note   Channel ending is on channel scope: independently of channel mapped\n  *         on ADC group regular or injected.\n  *         In differential mode: Differential measurement is carried out\n  *         between the selected channel 'i' (positive input) and\n  *         channel 'i+1' (negative input). Only channel 'i' has to be\n  *         configured, channel 'i+1' is configured automatically.\n  * @note   Refer to Reference Manual to ensure the selected channel is\n  *         available in differential mode.\n  *         For example, internal channels (VrefInt, TempSensor, ...) are\n  *         not available in differential mode.\n  * @note   When configuring a channel 'i' in differential mode,\n  *         the channel 'i+1' is not usable separately.\n  * @note   On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)\n  *         are internally fixed to single-ended inputs configuration.\n  * @note   For ADC channels configured in differential mode, both inputs\n  *         should be biased at (Vref+)/2 +/-200mV.\n  *         (Vref+ is the analog voltage reference)\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be ADC disabled.\n  * @note   One or several values can be selected.\n  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)\n  * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime\n  * @param  ADCx ADC instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  * @param  SingleDiff This parameter can be a combination of the following values:\n  *         @arg @ref LL_ADC_SINGLE_ENDED\n  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)\n{\n  /* Bits of channels in single or differential mode are set only for         */\n  /* differential mode (for single mode, mask of bits allowed to be set is    */\n  /* shifted out of range of bits of channels in single or differential mode. */\n  MODIFY_REG(ADCx->DIFSEL,\n             Channel & ADC_SINGLEDIFF_CHANNEL_MASK,\n             (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL << (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));\n}\n\n/**\n  * @brief  Get mode single-ended or differential input of the selected\n  *         ADC channel.\n  * @note   When configuring a channel 'i' in differential mode,\n  *         the channel 'i+1' is not usable separately.\n  *         Therefore, to ensure a channel is configured in single-ended mode,\n  *         the configuration of channel itself and the channel 'i-1' must be\n  *         read back (to ensure that the selected channel channel has not been\n  *         configured in differential mode by the previous channel).\n  * @note   Refer to Reference Manual to ensure the selected channel is\n  *         available in differential mode.\n  *         For example, internal channels (VrefInt, TempSensor, ...) are\n  *         not available in differential mode.\n  * @note   When configuring a channel 'i' in differential mode,\n  *         the channel 'i+1' is not usable separately.\n  * @note   On STM32L4, channels 15, 16, 17, 18 of ADC1, ADC2, ADC3 (if available)\n  *         are internally fixed to single-ended inputs configuration.\n  * @note   One or several values can be selected. In this case, the value\n  *         returned is null if all channels are in single ended-mode.\n  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)\n  * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSamplingTime\n  * @param  ADCx ADC instance\n  * @param  Channel This parameter can be a combination of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  * @retval 0: channel in single-ended mode, else: channel in differential mode\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)\n{\n  return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog\n  * @{\n  */\n\n/**\n  * @brief  Set ADC analog watchdog monitored channels:\n  *         a single channel, multiple channels or all channels,\n  *         on ADC groups regular and-or injected.\n  * @note   Once monitored channels are selected, analog watchdog\n  *         is enabled.\n  * @note   In case of need to define a single channel to monitor\n  *         with analog watchdog from sequencer channel definition,\n  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().\n  * @note   On this STM32 serie, there are 2 kinds of analog watchdog\n  *         instance:\n  *         - AWD standard (instance AWD1):\n  *           - channels monitored: can monitor 1 channel or all channels.\n  *           - groups monitored: ADC groups regular and-or injected.\n  *           - resolution: resolution is not limited (corresponds to\n  *             ADC resolution configured).\n  *         - AWD flexible (instances AWD2, AWD3):\n  *           - channels monitored: flexible on channels monitored, selection is\n  *             channel wise, from from 1 to all channels.\n  *             Specificity of this analog watchdog: Multiple channels can\n  *             be selected. For example:\n  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)\n  *           - groups monitored: not selection possible (monitoring on both\n  *             groups regular and injected).\n  *             Channels selected are monitored on groups regular and injected:\n  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters\n  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)\n  *           - resolution: resolution is limited to 8 bits: if ADC resolution is\n  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits\n  *             the 2 LSB are ignored.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\\n\n  *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\\n\n  *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\\n\n  *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\\n\n  *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\\n\n  *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels\n  * @param  ADCx ADC instance\n  * @param  AWDy This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD1\n  *         @arg @ref LL_ADC_AWD2\n  *         @arg @ref LL_ADC_AWD3\n  * @param  AWDChannelGroup This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_DISABLE\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(4)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(4)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (4)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(4)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(4)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (4)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG          (0)(2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_INJ          (0)(2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_REG_INJ         (2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG          (0)(2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_INJ          (0)(2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_REG_INJ         (2)(5)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG     (0)(3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_INJ     (0)(3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC3_REG_INJ    (3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG     (0)(3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_INJ     (0)(3)(6)\n  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC3_REG_INJ    (3)(6)\n  *         \n  *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\\n\n  *         (1) On STM32L4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On STM32L4, parameter available only on ADC instance: ADC2.\\n\n  *         (3) On STM32L4, parameter available only on ADC instance: ADC3.\\n\n  *         (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n  *         (5) On STM32L4, parameter available on devices with only 1 ADC instance.\\n\n  *         (6) On STM32L4, parameter available on devices with several ADC instances.\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)\n{\n  /* Set bits with content of parameter \"AWDChannelGroup\" with bits position  */\n  /* in register and register position depending on parameter \"AWDy\".         */\n  /* Parameters \"AWDChannelGroup\" and \"AWDy\" are used with masks because      */\n  /* containing other bits reserved for other purpose.                        */\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)\n                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));\n  \n  MODIFY_REG(*preg,\n             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),\n             AWDChannelGroup & AWDy);\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, __ADC_MASK_SHIFT(AWDy, ADC_AWD_CRX_REGOFFSET_MASK)\n                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));\n  \n  MODIFY_REG(*preg,\n             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),\n             AWDChannelGroup & AWDy);\n#endif\n}\n\n/**\n  * @brief  Get ADC analog watchdog monitored channel.\n  * @note   Usage of the returned channel number:\n  *         - To reinject this channel into another function LL_ADC_xxx:\n  *           the returned channel number is only partly formatted on definition\n  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\n  *           with parts of literals LL_ADC_CHANNEL_x or using\n  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Then the selected literal LL_ADC_CHANNEL_x can be used\n  *           as parameter for another function.\n  *         - To get the channel number in decimal format:\n  *           process the returned value with the helper macro\n  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Applicable only when the analog watchdog is set to monitor\n  *           one channel.\n  * @note   On this STM32 serie, there are 2 kinds of analog watchdog\n  *         instance:\n  *         - AWD standard (instance AWD1):\n  *           - channels monitored: can monitor 1 channel or all channels.\n  *           - groups monitored: ADC groups regular and-or injected.\n  *           - resolution: resolution is not limited (corresponds to\n  *             ADC resolution configured).\n  *         - AWD flexible (instances AWD2, AWD3):\n  *           - channels monitored: flexible on channels monitored, selection is\n  *             channel wise, from from 1 to all channels.\n  *             Specificity of this analog watchdog: Multiple channels can\n  *             be selected. For example:\n  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)\n  *           - groups monitored: not selection possible (monitoring on both\n  *             groups regular and injected).\n  *             Channels selected are monitored on groups regular and injected:\n  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters\n  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)\n  *           - resolution: resolution is limited to 8 bits: if ADC resolution is\n  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits\n  *             the 2 LSB are ignored.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\\n\n  *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\\n\n  *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\\n\n  *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\\n\n  *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\\n\n  *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels\n  * @param  ADCx ADC instance\n  * @param  AWDy This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD1\n  *         @arg @ref LL_ADC_AWD2 (1)\n  *         @arg @ref LL_ADC_AWD3 (1)\n  *         \n  *         (1) On this AWD number, monitored channel can be retrieved\n  *             if only 1 channel is programmed (or none or all channels).\n  *             This function cannot retrieve monitored channel if\n  *             multiple channels are programmed simultaneously\n  *             by bitfield.\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_DISABLE\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\n  *         \n  *         (0) On STM32L4, parameter available only on analog watchdog number: AWD1.\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)\n{\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)\n                                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));\n  \n  register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);\n  \n  /* If \"AnalogWDMonitChannels\" == 0, then the selected AWD is disabled       */\n  /* (parameter value LL_ADC_AWD_DISABLE).                                    */\n  /* Else, the selected AWD is enabled and is monitoring a group of channels  */\n  /* or a single channel.                                                     */\n  if(AnalogWDMonitChannels != 0)\n  {\n    if(AWDy == LL_ADC_AWD1)\n    {\n      if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0)\n      {\n        /* AWD monitoring a group of channels */\n        AnalogWDMonitChannels = ((  AnalogWDMonitChannels\n                                  | (ADC_AWD_CR23_CHANNEL_MASK)\n                                 )\n                                 & (~(ADC_CFGR_AWD1CH))\n                                );\n      }\n      else\n      {\n        /* AWD monitoring a single channel */\n        AnalogWDMonitChannels = (AnalogWDMonitChannels\n                                 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))\n                                );\n      }\n    }\n    else\n    {\n      if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)\n      {\n        /* AWD monitoring a group of channels */\n        AnalogWDMonitChannels = (  ADC_AWD_CR23_CHANNEL_MASK\n                                 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))\n                                );\n      }\n      else\n      {\n        /* AWD monitoring a single channel */\n        /* AWD monitoring a group of channels */\n        AnalogWDMonitChannels = (  AnalogWDMonitChannels\n                                 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)\n                                 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)\n                                );\n      }\n    }\n  }\n  \n  return AnalogWDMonitChannels;\n\n}\n\n/**\n  * @brief  Set ADC analog watchdog thresholds value of both thresholds\n  *         high and low.\n  * @note   If value of only one threshold high or low must be set,\n  *         use function @ref LL_ADC_SetAnalogWDThresholds().\n  * @note   In case of ADC resolution different of 12 bits,\n  *         analog watchdog thresholds data require a specific shift.\n  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().\n  * @note   On this STM32 serie, there are 2 kinds of analog watchdog\n  *         instance:\n  *         - AWD standard (instance AWD1):\n  *           - channels monitored: can monitor 1 channel or all channels.\n  *           - groups monitored: ADC groups regular and-or injected.\n  *           - resolution: resolution is not limited (corresponds to\n  *             ADC resolution configured).\n  *         - AWD flexible (instances AWD2, AWD3):\n  *           - channels monitored: flexible on channels monitored, selection is\n  *             channel wise, from from 1 to all channels.\n  *             Specificity of this analog watchdog: Multiple channels can\n  *             be selected. For example:\n  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)\n  *           - groups monitored: not selection possible (monitoring on both\n  *             groups regular and injected).\n  *             Channels selected are monitored on groups regular and injected:\n  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters\n  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)\n  *           - resolution: resolution is limited to 8 bits: if ADC resolution is\n  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits\n  *             the 2 LSB are ignored.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\\n\n  *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\\n\n  *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\\n\n  *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\\n\n  *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\\n\n  *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds\n  * @param  ADCx ADC instance\n  * @param  AWDy This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD1\n  *         @arg @ref LL_ADC_AWD2\n  *         @arg @ref LL_ADC_AWD3\n  * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)\n{\n  /* Set bits with content of parameter \"AWDThresholdxxxValue\" with bits      */\n  /* position in register and register position depending on parameter        */\n  /* \"AWDy\".                                                                  */\n  /* Parameters \"AWDy\" and \"AWDThresholdxxxValue\" are used with masks because */\n  /* containing other bits reserved for other purpose.                        */\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));\n#endif\n  \n  MODIFY_REG(*preg,\n             ADC_TR1_HT1 | ADC_TR1_LT1,\n             (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);\n}\n\n/**\n  * @brief  Set ADC analog watchdog threshold value of threshold\n  *         high or low.\n  * @note   If values of both thresholds high or low must be set,\n  *         use function @ref LL_ADC_ConfigAnalogWDThresholds().\n  * @note   In case of ADC resolution different of 12 bits,\n  *         analog watchdog thresholds data require a specific shift.\n  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().\n  * @note   On this STM32 serie, there are 2 kinds of analog watchdog\n  *         instance:\n  *         - AWD standard (instance AWD1):\n  *           - channels monitored: can monitor 1 channel or all channels.\n  *           - groups monitored: ADC groups regular and-or injected.\n  *           - resolution: resolution is not limited (corresponds to\n  *             ADC resolution configured).\n  *         - AWD flexible (instances AWD2, AWD3):\n  *           - channels monitored: flexible on channels monitored, selection is\n  *             channel wise, from from 1 to all channels.\n  *             Specificity of this analog watchdog: Multiple channels can\n  *             be selected. For example:\n  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)\n  *           - groups monitored: not selection possible (monitoring on both\n  *             groups regular and injected).\n  *             Channels selected are monitored on groups regular and injected:\n  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters\n  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)\n  *           - resolution: resolution is limited to 8 bits: if ADC resolution is\n  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits\n  *             the 2 LSB are ignored.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either ADC groups regular or injected.\n  * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\\n\n  *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\\n\n  *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\\n\n  *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\\n\n  *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\\n\n  *         TR3      LT3            LL_ADC_SetAnalogWDThresholds\n  * @param  ADCx ADC instance\n  * @param  AWDy This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD1\n  *         @arg @ref LL_ADC_AWD2\n  *         @arg @ref LL_ADC_AWD3\n  * @param  AWDThresholdsHighLow This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW\n  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)\n{\n  /* Set bits with content of parameter \"AWDThresholdValue\" with bits         */\n  /* position in register and register position depending on parameters       */\n  /* \"AWDThresholdsHighLow\" and \"AWDy\".                                       */\n  /* Parameters \"AWDy\" and \"AWDThresholdValue\" are used with masks because    */\n  /* containing other bits reserved for other purpose.                        */\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));\n  \n  MODIFY_REG(*preg,\n             AWDThresholdsHighLow,\n             AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));\n  \n  MODIFY_REG(*preg,\n             AWDThresholdsHighLow,\n             AWDThresholdValue << POSITION_VAL(AWDThresholdsHighLow));\n#endif\n}\n\n/**\n  * @brief  Get ADC analog watchdog threshold value of threshold high,\n  *         threshold low or raw data with ADC thresholds high and low\n  *         concatenated.\n  * @note   If raw data with ADC thresholds high and low is retrieved,\n  *         the data of each threshold high or low can be isolated\n  *         using helper macro:\n  *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().\n  * @note   In case of ADC resolution different of 12 bits,\n  *         analog watchdog thresholds data require a specific shift.\n  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().\n  * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\\n\n  *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\\n\n  *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\\n\n  *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\\n\n  *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\\n\n  *         TR3      LT3            LL_ADC_GetAnalogWDThresholds\n  * @param  ADCx ADC instance\n  * @param  AWDy This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD1\n  *         @arg @ref LL_ADC_AWD2\n  *         @arg @ref LL_ADC_AWD3\n  * @param  AWDThresholdsHighLow This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW\n  *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n*/\n__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)\n{\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));\n  \n  return (uint32_t)(READ_BIT(*preg,\n                             (AWDThresholdsHighLow | ADC_TR1_LT1))\n                    >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))\n                   );\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, __ADC_MASK_SHIFT(AWDy, ADC_AWD_TRX_REGOFFSET_MASK));\n  \n  return (uint32_t)(READ_BIT(*preg,\n                             (AWDThresholdsHighLow | ADC_TR1_LT1))\n                    >> POSITION_VAL(AWDThresholdsHighLow)\n                   );\n#endif\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling\n  * @{\n  */\n\n/**\n  * @brief  Set ADC oversampling scope: ADC groups regular and-or injected\n  *         (availability of ADC group injected depends on STM32 families).\n  * @note   If both groups regular and injected are selected,\n  *         specify behavior of ADC group injected interrupting\n  *         group regular: when ADC group injected is triggered,\n  *         the oversampling on ADC group regular is either\n  *         temporary stopped and continued, or resumed from start\n  *         (oversampler buffer reset).\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\\n\n  *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\\n\n  *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope\n  * @param  ADCx ADC instance\n  * @param  OvsScope This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OVS_DISABLE\n  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED\n  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED\n  *         @arg @ref LL_ADC_OVS_GRP_INJECTED\n  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)\n{\n  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);\n}\n\n/**\n  * @brief  Get ADC oversampling scope: ADC groups regular and-or injected\n  *         (availability of ADC group injected depends on STM32 families).\n  * @note   If both groups regular and injected are selected,\n  *         specify behavior of ADC group injected interrupting\n  *         group regular: when ADC group injected is triggered,\n  *         the oversampling on ADC group regular is either\n  *         temporary stopped and continued, or resumed from start\n  *         (oversampler buffer reset).\n  * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\\n\n  *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\\n\n  *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_OVS_DISABLE\n  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED\n  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED\n  *         @arg @ref LL_ADC_OVS_GRP_INJECTED\n  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));\n}\n\n/**\n  * @brief  Set ADC oversampling discontinuous mode (triggered mode)\n  *         on the selected ADC group.\n  * @note   Number of oversampled conversions are done either in:\n  *         - continuous mode (all conversions of oversampling ratio\n  *           are done from 1 trigger)\n  *         - discontinuous mode (each conversion of oversampling ratio\n  *           needs a trigger)\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on group regular.\n  * @note   On this STM32 serie, oversampling discontinuous mode \n  *         (triggered mode) can be used only when oversampling is \n  *         set on group regular only and in resumed mode.\n  * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont\n  * @param  ADCx ADC instance\n  * @param  OverSamplingDiscont This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OVS_REG_CONT\n  *         @arg @ref LL_ADC_OVS_REG_DISCONT\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)\n{\n  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);\n}\n\n/**\n  * @brief  Get ADC oversampling discontinuous mode (triggered mode)\n  *         on the selected ADC group.\n  * @note   Number of oversampled conversions are done either in:\n  *         - continuous mode (all conversions of oversampling ratio\n  *           are done from 1 trigger)\n  *         - discontinuous mode (each conversion of oversampling ratio\n  *           needs a trigger)\n  * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_OVS_REG_CONT\n  *         @arg @ref LL_ADC_OVS_REG_DISCONT\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));\n}\n\n/**\n  * @brief  Set ADC oversampling\n  *         (impacting both ADC groups regular and injected)\n  * @note   This function set the 2 items of oversampling configuration:\n  *         - ratio\n  *         - shift\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be disabled or enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\\n\n  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift\n  * @param  ADCx ADC instance\n  * @param  Ratio This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OVS_RATIO_2\n  *         @arg @ref LL_ADC_OVS_RATIO_4\n  *         @arg @ref LL_ADC_OVS_RATIO_8\n  *         @arg @ref LL_ADC_OVS_RATIO_16\n  *         @arg @ref LL_ADC_OVS_RATIO_32\n  *         @arg @ref LL_ADC_OVS_RATIO_64\n  *         @arg @ref LL_ADC_OVS_RATIO_128\n  *         @arg @ref LL_ADC_OVS_RATIO_256\n  * @param  Shift This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OVS_SHIFT_NONE\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)\n{\n  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));\n}\n\n/**\n  * @brief  Get ADC oversampling ratio\n  *        (impacting both ADC groups regular and injected)\n  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio\n  * @param  ADCx ADC instance\n  * @retval Ratio This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OVS_RATIO_2\n  *         @arg @ref LL_ADC_OVS_RATIO_4\n  *         @arg @ref LL_ADC_OVS_RATIO_8\n  *         @arg @ref LL_ADC_OVS_RATIO_16\n  *         @arg @ref LL_ADC_OVS_RATIO_32\n  *         @arg @ref LL_ADC_OVS_RATIO_64\n  *         @arg @ref LL_ADC_OVS_RATIO_128\n  *         @arg @ref LL_ADC_OVS_RATIO_256\n*/\n__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));\n}\n\n/**\n  * @brief  Get ADC oversampling shift\n  *        (impacting both ADC groups regular and injected)\n  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift\n  * @param  ADCx ADC instance\n  * @retval Shift This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_OVS_SHIFT_NONE\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7\n  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8\n*/\n__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode\n  * @{\n  */\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/**\n  * @brief  Set ADC multimode configuration to operate in independent mode\n  *         or multimode (for devices with several ADC instances).\n  * @note   If multimode configuration: the selected ADC instance is\n  *         either master or slave depending on hardware.\n  *         Refer to reference manual.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         All ADC instances of the ADC common group must be disabled.\n  *         This check can be done with function @ref LL_ADC_IsEnabled() for each\n  *         ADC instance or by using helper macro\n  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().\n  * @rmtoll CCR      DUAL           LL_ADC_SetMultimode\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  Multimode This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_INDEPENDENT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL\n  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT\n  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);\n}\n\n/**\n  * @brief  Get ADC multimode configuration to operate in independent mode\n  *         or multimode (for devices with several ADC instances).\n  * @note   If multimode configuration: the selected ADC instance is\n  *         either master or slave depending on hardware.\n  *         Refer to reference manual.\n  * @rmtoll CCR      DUAL           LL_ADC_GetMultimode\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_INDEPENDENT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL\n  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT\n  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));\n}\n\n/**\n  * @brief  Set ADC multimode conversion data transfer: no transfer\n  *         or transfer by DMA.\n  * @note   If ADC multimode transfer by DMA is not selected:\n  *         each ADC uses its own DMA channel, with its individual\n  *         DMA transfer settings.\n  *         If ADC multimode transfer by DMA is selected:\n  *         One DMA channel is used for both ADC (DMA of ADC master)\n  *         Specifies the DMA requests mode:\n  *         - Limited mode (One shot mode): DMA transfer requests are stopped\n  *           when number of DMA data transfers (number of\n  *           ADC conversions) is reached.\n  *           This ADC mode is intended to be used with DMA mode non-circular.\n  *         - Unlimited mode: DMA transfer requests are unlimited,\n  *           whatever number of DMA data transfers (number of\n  *           ADC conversions).\n  *           This ADC mode is intended to be used with DMA mode circular.\n  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to\n  *         mode non-circular:\n  *         when DMA transfers size will be reached, DMA will stop transfers of\n  *         ADC conversions data ADC will raise an overrun error\n  *         (overrun flag and interruption if enabled).\n  * @note   How to retrieve multimode conversion data:\n  *         Whatever multimode transfer by DMA setting: using function\n  *         @ref LL_ADC_REG_ReadMultiConversionData32().\n  *         If ADC multimode transfer by DMA is selected: conversion data\n  *         is a raw data with ADC master and slave concatenated.\n  *         A macro is available to get the conversion data of\n  *         ADC master or ADC slave: see helper macro\n  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         All ADC instances of the ADC common group must be disabled\n  *         or enabled without conversion on going on group regular.\n  * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\\n\n  *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  MultiDMATransfer This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);\n}\n\n/**\n  * @brief  Get ADC multimode conversion data transfer: no transfer\n  *         or transfer by DMA.\n  * @note   If ADC multimode transfer by DMA is not selected:\n  *         each ADC uses its own DMA channel, with its individual\n  *         DMA transfer settings.\n  *         If ADC multimode transfer by DMA is selected:\n  *         One DMA channel is used for both ADC (DMA of ADC master)\n  *         Specifies the DMA requests mode:\n  *         - Limited mode (One shot mode): DMA transfer requests are stopped\n  *           when number of DMA data transfers (number of\n  *           ADC conversions) is reached.\n  *           This ADC mode is intended to be used with DMA mode non-circular.\n  *         - Unlimited mode: DMA transfer requests are unlimited,\n  *           whatever number of DMA data transfers (number of\n  *           ADC conversions).\n  *           This ADC mode is intended to be used with DMA mode circular.\n  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to\n  *         mode non-circular:\n  *         when DMA transfers size will be reached, DMA will stop transfers of\n  *         ADC conversions data ADC will raise an overrun error\n  *         (overrun flag and interruption if enabled).\n  * @note   How to retrieve multimode conversion data:\n  *         Whatever multimode transfer by DMA setting: using function\n  *         @ref LL_ADC_REG_ReadMultiConversionData32().\n  *         If ADC multimode transfer by DMA is selected: conversion data\n  *         is a raw data with ADC master and slave concatenated.\n  *         A macro is available to get the conversion data of\n  *         ADC master or ADC slave: see helper macro\n  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\n  * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\\n\n  *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));\n}\n\n/**\n  * @brief  Set ADC multimode delay between 2 sampling phases.\n  * @note   The sampling delay range depends on ADC resolution:\n  *         - ADC resolution 12 bits can have maximum delay of 12 cycles.\n  *         - ADC resolution 10 bits can have maximum delay of 10 cycles.\n  *         - ADC resolution  8 bits can have maximum delay of  8 cycles.\n  *         - ADC resolution  6 bits can have maximum delay of  6 cycles.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         All ADC instances of the ADC common group must be disabled.\n  *         This check can be done with function @ref LL_ADC_IsEnabled() for each\n  *         ADC instance or by using helper macro helper macro\n  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().\n  * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  MultiTwoSamplingDelay This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)\n  *         \n  *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\\n\n  *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\\n\n  *         (3) Parameter available only if ADC resolution is 12 bits.\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);\n}\n\n/**\n  * @brief  Get ADC multimode delay between 2 sampling phases.\n  * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)\n  *         \n  *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\\n\n  *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\\n\n  *         (3) Parameter available only if ADC resolution is 12 bits.\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));\n}\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n/**\n  * @}\n  */\n/** @defgroup ADC_LL_EF_Configuration_Leg_Functions Configuration of ADC alternate functions name\n  * @{\n  */\n/* Old functions name kept for legacy purpose, to be replaced by the          */\n/* current functions name.                                                    */\n__STATIC_INLINE void LL_ADC_REG_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)\n{\n  LL_ADC_REG_SetTriggerSource(ADCx, TriggerSource);\n}\n__STATIC_INLINE void LL_ADC_INJ_SetTrigSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)\n{\n  LL_ADC_INJ_SetTriggerSource(ADCx, TriggerSource);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance\n  * @{\n  */\n\n/**\n  * @brief  Put ADC instance in deep power down state.\n  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down\n  *         state, the internal analog calibration is lost. After exiting from\n  *         deep power down, calibration must be relaunched or calibration factor\n  *         (preliminarily saved) must be set back into calibration register.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be ADC disabled.\n  * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_DEEPPWD);\n}\n\n/**\n  * @brief  Disable ADC deep power down mode.\n  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down\n  *         state, the internal analog calibration is lost. After exiting from\n  *         deep power down, calibration must be relaunched or calibration factor\n  *         (preliminarily saved) must be set back into calibration register.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be ADC disabled.\n  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));\n}\n\n/**\n  * @brief  Get the selected ADC instance deep power down state.\n  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled\n  * @param  ADCx ADC instance\n  * @retval 0: deep power down is disabled, 1: deep power down is enabled.\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD));\n}\n\n/**\n  * @brief  Enable ADC instance internal voltage regulator.\n  * @note   On this STM32 serie, after ADC internal voltage regulator enable,\n  *         a delay for ADC internal voltage regulator stabilization\n  *         is required before performing a ADC calibration or ADC enable.\n  *         Refer to device datasheet, parameter tADCVREG_STUP.\n  *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be ADC disabled.\n  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_ADVREGEN);\n}\n\n/**\n  * @brief  Disable ADC internal voltage regulator.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be ADC disabled.\n  * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));\n}\n\n/**\n  * @brief  Get the selected ADC instance internal voltage regulator state.\n  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled\n  * @param  ADCx ADC instance\n  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN));\n}\n\n/**\n  * @brief  Enable the selected ADC instance.\n  * @note   On this STM32 serie, after ADC enable, a delay for \n  *         ADC internal analog stabilization is required before performing a\n  *         ADC conversion start.\n  *         Refer to device datasheet, parameter tSTAB.\n  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC\n  *         is enabled and when conversion clock is active.\n  *         (not only core clock: this ADC has a dual clock domain)\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.\n  * @rmtoll CR       ADEN           LL_ADC_Enable\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_ADEN);\n}\n\n/**\n  * @brief  Disable the selected ADC instance.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be not disabled. Must be enabled without conversion on going\n  *         on either groups regular or injected.\n  * @rmtoll CR       ADDIS          LL_ADC_Disable\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_ADDIS);\n}\n\n/**\n  * @brief  Get the selected ADC instance enable state.\n  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC\n  *         is enabled and when conversion clock is active.\n  *         (not only core clock: this ADC has a dual clock domain)\n  * @rmtoll CR       ADEN           LL_ADC_IsEnabled\n  * @param  ADCx ADC instance\n  * @retval 0: ADC is disabled, 1: ADC is enabled.\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));\n}\n\n/**\n  * @brief  Get the selected ADC instance disable state.\n  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing\n  * @param  ADCx ADC instance\n  * @retval 0: no ADC disable command on going.\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));\n}\n\n/**\n  * @brief  Start ADC calibration in the mode single-ended\n  *         or differential (for devices with differential mode available).\n  * @note   On this STM32 serie, a minimum number of ADC clock cycles\n  *         are required between ADC end of calibration and ADC enable.\n  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.\n  * @note   For devices with differential mode available:\n  *         Calibration of offset is specific to each of\n  *         single-ended and differential modes\n  *         (calibration run must be performed for each of these\n  *         differential modes, if used afterwards and if the application\n  *         requires their calibration).\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be ADC disabled.\n  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\\n\n  *         CR       ADCALDIF       LL_ADC_StartCalibration\n  * @param  ADCx ADC instance\n  * @param  SingleDiff This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_SINGLE_ENDED\n  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));\n}\n\n/**\n  * @brief  Get ADC calibration state.\n  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing\n  * @param  ADCx ADC instance\n  * @retval 0: calibration complete, 1: calibration in progress.\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular\n  * @{\n  */\n\n/**\n  * @brief  Start ADC group regular conversion.\n  * @note   On this STM32 serie, this function is relevant for both \n  *         internal trigger (SW start) and external trigger:\n  *         - If ADC trigger has been set to software start, ADC conversion\n  *           starts immediately.\n  *         - If ADC trigger has been set to external trigger, ADC conversion\n  *           will start at next trigger event (on the selected trigger edge)\n  *           following the ADC start conversion command.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be enabled without conversion on going on group regular,\n  *         without conversion stop command on going on group regular,\n  *         without ADC disable command on going.\n  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_ADSTART);\n}\n\n/**\n  * @brief  Stop ADC group regular conversion.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be enabled with conversion on going on group regular,\n  *         without ADC disable command on going.\n  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_ADSTP);\n}\n\n/**\n  * @brief  Get ADC group regular conversion state.\n  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing\n  * @param  ADCx ADC instance\n  * @retval 0: no conversion is on going on ADC group regular.\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));\n}\n\n/**\n  * @brief  Get ADC group regular command of conversion stop state\n  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing\n  * @param  ADCx ADC instance\n  * @retval 0: no command of conversion stop is on going on ADC group regular.\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         all ADC configurations: all ADC resolutions and\n  *         all oversampling increased data width (for devices\n  *         with feature oversampling).\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         ADC resolution 12 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)\n{\n  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         ADC resolution 10 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF\n  */\n__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)\n{\n  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         ADC resolution 8 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)\n{\n  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         ADC resolution 6 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0x3F\n  */\n__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)\n{\n  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));\n}\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/**\n  * @brief  Get ADC multimode conversion data of ADC master, ADC slave\n  *         or raw data with ADC master and slave concatenated.\n  * @note   If raw data with ADC master and slave concatenated is retrieved,\n  *         a macro is available to get the conversion data of\n  *         ADC master or ADC slave: see helper macro\n  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\n  *         (however this macro is mainly intended for multimode\n  *         transfer by DMA, because this function can do the same\n  *         by getting multimode conversion data of ADC master or ADC slave\n  *         separately).\n  * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\\n\n  *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  ConversionData This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_MASTER\n  *         @arg @ref LL_ADC_MULTI_SLAVE\n  *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE\n  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,\n                             ConversionData)\n                    >> POSITION_VAL(ConversionData)\n                   );\n}\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected\n  * @{\n  */\n\n/**\n  * @brief  Start ADC group injected conversion.\n  * @note   On this STM32 serie, this function is relevant for both \n  *         internal trigger (SW start) and external trigger:\n  *         - If ADC trigger has been set to software start, ADC conversion\n  *           starts immediately.\n  *         - If ADC trigger has been set to external trigger, ADC conversion\n  *           will start at next trigger event (on the selected trigger edge)\n  *           following the ADC start conversion command.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be enabled without conversion on going on group injected,\n  *         without conversion stop command on going on group injected,\n  *         without ADC disable command on going.\n  * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_JADSTART);\n}\n\n/**\n  * @brief  Stop ADC group injected conversion.\n  * @note   On this STM32 serie, setting of this feature is conditioned to\n  *         ADC state:\n  *         ADC must be enabled with conversion on going on group injected,\n  *         without ADC disable command on going.\n  * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)\n{\n  /* Note: Write register with some additional bits forced to state reset     */\n  /*       instead of modifying only the selected bit for this function,      */\n  /*       to not interfere with bits with HW property \"rs\".                  */\n  MODIFY_REG(ADCx->CR,\n             ADC_CR_BITS_PROPERTY_RS,\n             ADC_CR_JADSTP);\n}\n\n/**\n  * @brief  Get ADC group injected conversion state.\n  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing\n  * @param  ADCx ADC instance\n  * @retval 0: no conversion is on going on ADC group injected.\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART));\n}\n\n/**\n  * @brief  Get ADC group injected command of conversion stop state\n  * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing\n  * @param  ADCx ADC instance\n  * @retval 0: no command of conversion stop is on going on ADC group injected.\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         all ADC configurations: all ADC resolutions and\n  *         all oversampling increased data width (for devices\n  *         with feature oversampling).\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n#endif\n  \n  return (uint32_t)(READ_BIT(*preg,\n                             ADC_JDR1_JDATA)\n                   );\n}\n\n/**\n  * @brief  Get ADC group injected conversion data, range fit for\n  *         ADC resolution 12 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n#endif\n  \n  return (uint16_t)(READ_BIT(*preg,\n                             ADC_JDR1_JDATA)\n                   );\n}\n\n/**\n  * @brief  Get ADC group injected conversion data, range fit for\n  *         ADC resolution 10 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF\n  */\n__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n#endif\n  \n  return (uint16_t)(READ_BIT(*preg,\n                             ADC_JDR1_JDATA)\n                   );\n}\n\n/**\n  * @brief  Get ADC group injected conversion data, range fit for\n  *         ADC resolution 8 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n#endif\n  \n  return (uint8_t)(READ_BIT(*preg,\n                            ADC_JDR1_JDATA)\n                  );\n}\n\n/**\n  * @brief  Get ADC group injected conversion data, range fit for\n  *         ADC resolution 6 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x00 and Max_Data=0x3F\n  */\n__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n#if defined(CORE_CM0PLUS)\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));\n#else\n  register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n#endif\n  \n  return (uint8_t)(READ_BIT(*preg,\n                            ADC_JDR1_JDATA)\n                  );\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management\n  * @{\n  */\n\n/**\n  * @brief  Get flag ADC ready.\n  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC\n  *         is enabled and when conversion clock is active.\n  *         (not only core clock: this ADC has a dual clock domain)\n  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));\n}\n\n/**\n  * @brief  Get flag ADC group regular end of unitary conversion.\n  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));\n}\n\n/**\n  * @brief  Get flag ADC group regular end of sequence conversions.\n  * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));\n}\n\n/**\n  * @brief  Get flag ADC group regular overrun.\n  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));\n}\n\n/**\n  * @brief  Get flag ADC group regular end of sampling phase.\n  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));\n}\n\n/**\n  * @brief  Get flag ADC group injected end of unitary conversion.\n  * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC));\n}\n\n/**\n  * @brief  Get flag ADC group injected end of sequence conversions.\n  * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));\n}\n\n/**\n  * @brief  Get flag ADC group injected contexts queue overflow.\n  * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF));\n}\n\n/**\n  * @brief  Get flag ADC analog watchdog 1 flag\n  * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));\n}\n\n/**\n  * @brief  Get flag ADC analog watchdog 2.\n  * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2));\n}\n\n/**\n  * @brief  Get flag ADC analog watchdog 3.\n  * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3));\n}\n\n/**\n  * @brief  Clear flag ADC ready.\n  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC\n  *         is enabled and when conversion clock is active.\n  *         (not only core clock: this ADC has a dual clock domain)\n  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);\n}\n\n/**\n  * @brief  Clear flag ADC group regular end of unitary conversion.\n  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);\n}\n\n/**\n  * @brief  Clear flag ADC group regular end of sequence conversions.\n  * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);\n}\n\n/**\n  * @brief  Clear flag ADC group regular overrun.\n  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);\n}\n\n/**\n  * @brief  Clear flag ADC group regular end of sampling phase.\n  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);\n}\n\n/**\n  * @brief  Clear flag ADC group injected end of unitary conversion.\n  * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);\n}\n\n/**\n  * @brief  Clear flag ADC group injected end of sequence conversions.\n  * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);\n}\n\n/**\n  * @brief  Clear flag ADC group injected contexts queue overflow.\n  * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);\n}\n\n/**\n  * @brief  Clear flag ADC analog watchdog 1.\n  * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);\n}\n\n/**\n  * @brief  Clear flag ADC analog watchdog 2.\n  * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);\n}\n\n/**\n  * @brief  Clear flag ADC analog watchdog 3.\n  * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);\n}\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/**\n  * @brief  Get flag multimode ADC ready of the ADC master.\n  * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC ready of the ADC slave.\n  * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.\n  * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.\n  * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.\n  * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.\n  * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular overrun of the ADC master.\n  * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular overrun of the ADC slave.\n  * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.\n  * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.\n  * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.\n  * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.\n  * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.\n  * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.\n  * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.\n  * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.\n  * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.\n  * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));\n}\n\n/**\n  * @brief  Get flag multimode analog watchdog 1 of the ADC slave.\n  * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.\n  * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.\n  * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV));\n}\n\n/**\n  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.\n  * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.\n  * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV));\n}\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_IT_Management ADC IT management\n  * @{\n  */\n\n/**\n  * @brief  Enable ADC ready.\n  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);\n}\n\n/**\n  * @brief  Enable interruption ADC group regular end of unitary conversion.\n  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);\n}\n\n/**\n  * @brief  Enable interruption ADC group regular end of sequence conversions.\n  * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);\n}\n\n/**\n  * @brief  Enable ADC group regular interruption overrun.\n  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);\n}\n\n/**\n  * @brief  Enable interruption ADC group regular end of sampling.\n  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);\n}\n\n/**\n  * @brief  Enable interruption ADC group injected end of unitary conversion.\n  * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);\n}\n\n/**\n  * @brief  Enable interruption ADC group injected end of sequence conversions.\n  * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);\n}\n\n/**\n  * @brief  Enable interruption ADC group injected context queue overflow.\n  * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);\n}\n\n/**\n  * @brief  Enable interruption ADC analog watchdog 1.\n  * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);\n}\n\n/**\n  * @brief  Enable interruption ADC analog watchdog 2.\n  * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);\n}\n\n/**\n  * @brief  Enable interruption ADC analog watchdog 3.\n  * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);\n}\n\n/**\n  * @brief  Disable interruption ADC ready.\n  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);\n}\n\n/**\n  * @brief  Disable interruption ADC group regular end of unitary conversion.\n  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);\n}\n\n/**\n  * @brief  Disable interruption ADC group regular end of sequence conversions.\n  * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);\n}\n\n/**\n  * @brief  Disable interruption ADC group regular overrun.\n  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);\n}\n\n/**\n  * @brief  Disable interruption ADC group regular end of sampling.\n  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);\n}\n\n/**\n  * @brief  Disable interruption ADC group regular end of unitary conversion.\n  * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);\n}\n\n/**\n  * @brief  Disable interruption ADC group injected end of sequence conversions.\n  * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);\n}\n\n/**\n  * @brief  Disable interruption ADC group injected context queue overflow.\n  * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);\n}\n\n/**\n  * @brief  Disable interruption ADC analog watchdog 1.\n  * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);\n}\n\n/**\n  * @brief  Disable interruption ADC analog watchdog 2.\n  * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);\n}\n\n/**\n  * @brief  Disable interruption ADC analog watchdog 3.\n  * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);\n}\n\n/**\n  * @brief  Get state of interruption ADC ready\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));\n}\n\n/**\n  * @brief  Get state of interruption ADC group regular end of unitary conversion\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));\n}\n\n/**\n  * @brief  Get state of interruption ADC group regular end of sequence conversions\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));\n}\n\n/**\n  * @brief  Get state of interruption ADC group regular overrun\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));\n}\n\n/**\n  * @brief  Get state of interruption ADC group regular end of sampling\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));\n}\n\n/**\n  * @brief  Get state of interruption ADC group injected end of unitary conversion\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC));\n}\n\n/**\n  * @brief  Get state of interruption ADC group injected end of sequence conversions\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));\n}\n\n/**\n  * @brief  Get state of interruption ADC group injected context queue overflow interrupt state\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF));\n}\n\n/**\n  * @brief  Get state of interruption ADC analog watchdog 1\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));\n}\n\n/**\n  * @brief  Get state of interruption Get ADC analog watchdog 2\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2));\n}\n\n/**\n  * @brief  Get state of interruption Get ADC analog watchdog 3\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3));\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\n/* Initialization of some features of ADC common parameters and multimode */\nErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);\nErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);\nvoid        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);\n\n/* De-initialization of ADC instance, ADC group regular and ADC group injected */\n/* (availability of ADC group injected depends on STM32 families) */\nErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);\n\n/* Initialization of some features of ADC instance */\nErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);\nvoid        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);\n\n/* Initialization of some features of ADC instance and ADC group regular */\nErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);\nvoid        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);\n\n/* Initialization of some features of ADC instance and ADC group injected */\nErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);\nvoid        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* ADC1 || ADC2 || ADC3 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_ADC_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_bus.h\n  * @author  MCD Application Team\n  * @brief   Header file of BUS LL module.\n\n  @verbatim                \n                      ##### RCC Limitations #####\n  ==============================================================================\n    [..]  \n      A delay between an RCC peripheral clock enable and the effective peripheral \n      enabling should be taken into account in order to manage the peripheral read/write \n      from/to registers.\n      (+) This delay depends on the peripheral mapping.\n        (++) AHB & APB peripherals, 1 dummy read is necessary\n\n    [..]  \n      Workarounds:\n      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been\n          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_BUS_H\n#define __STM32L4xx_LL_BUS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @defgroup BUS_LL BUS\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n\n/* Private macros ------------------------------------------------------------*/\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants\n  * @{\n  */\n\n/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN\n#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN\n#if defined(DMAMUX1)\n#define LL_AHB1_GRP1_PERIPH_DMAMUX1        RCC_AHB1ENR_DMAMUX1EN\n#endif /* DMAMUX1 */\n#define LL_AHB1_GRP1_PERIPH_FLASH          RCC_AHB1ENR_FLASHEN\n#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN\n#define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHB1ENR_TSCEN\n#if defined(DMA2D)\n#define LL_AHB1_GRP1_PERIPH_DMA2D          RCC_AHB1ENR_DMA2DEN\n#endif /* DMA2D */\n#if defined(GFXMMU)\n#define LL_AHB1_GRP1_PERIPH_GFXMMU         RCC_AHB1ENR_GFXMMUEN\n#endif /* GFXMMU */\n#define LL_AHB1_GRP1_PERIPH_SRAM1          RCC_AHB1SMENR_SRAM1SMEN\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#define LL_AHB2_GRP1_PERIPH_GPIOA          RCC_AHB2ENR_GPIOAEN\n#define LL_AHB2_GRP1_PERIPH_GPIOB          RCC_AHB2ENR_GPIOBEN\n#define LL_AHB2_GRP1_PERIPH_GPIOC          RCC_AHB2ENR_GPIOCEN\n#if defined(GPIOD)\n#define LL_AHB2_GRP1_PERIPH_GPIOD          RCC_AHB2ENR_GPIODEN\n#endif /*GPIOD*/\n#if defined(GPIOE)\n#define LL_AHB2_GRP1_PERIPH_GPIOE          RCC_AHB2ENR_GPIOEEN\n#endif /*GPIOE*/\n#if defined(GPIOF)\n#define LL_AHB2_GRP1_PERIPH_GPIOF          RCC_AHB2ENR_GPIOFEN\n#endif /* GPIOF */\n#if defined(GPIOG)\n#define LL_AHB2_GRP1_PERIPH_GPIOG          RCC_AHB2ENR_GPIOGEN\n#endif /* GPIOG */\n#define LL_AHB2_GRP1_PERIPH_GPIOH          RCC_AHB2ENR_GPIOHEN\n#if defined(GPIOI)\n#define LL_AHB2_GRP1_PERIPH_GPIOI          RCC_AHB2ENR_GPIOIEN\n#endif /* GPIOI */\n#if defined(USB_OTG_FS)\n#define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN\n#endif /* USB_OTG_FS */\n#define LL_AHB2_GRP1_PERIPH_ADC            RCC_AHB2ENR_ADCEN\n#if defined(DCMI)\n#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN\n#endif /* DCMI */\n#if defined(AES)\n#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN\n#endif /* AES */\n#if defined(HASH)\n#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN\n#endif /* HASH */\n#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN\n#if defined(OCTOSPIM)\n#define LL_AHB2_GRP1_PERIPH_OSPIM          RCC_AHB2ENR_OSPIMEN\n#endif /* OCTOSPIM */\n#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)\n#define LL_AHB2_GRP1_PERIPH_SDMMC1         RCC_AHB2ENR_SDMMC1EN\n#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */\n#define LL_AHB2_GRP1_PERIPH_SRAM2          RCC_AHB2SMENR_SRAM2SMEN\n#if defined(SRAM3_BASE)\n#define LL_AHB2_GRP1_PERIPH_SRAM3          RCC_AHB2SMENR_SRAM3SMEN\n#endif /* SRAM3_BASE */\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH\n  * @{\n  */\n#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#if defined(FMC_Bank1_R)\n#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN\n#endif /* FMC_Bank1_R */\n#if defined(QUADSPI)\n#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN\n#endif /* QUADSPI */\n#if defined(OCTOSPI1)\n#define LL_AHB3_GRP1_PERIPH_OSPI1          RCC_AHB3ENR_OSPI1EN\n#endif /* OCTOSPI1 */\n#if defined(OCTOSPI2)\n#define LL_AHB3_GRP1_PERIPH_OSPI2          RCC_AHB3ENR_OSPI2EN\n#endif /* OCTOSPI2 */\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH\n  * @{\n  */\n#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR1_TIM2EN\n#if defined(TIM3)\n#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR1_TIM3EN\n#endif /* TIM3 */\n#if defined(TIM4)\n#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR1_TIM4EN\n#endif /* TIM4 */\n#if defined(TIM5)\n#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR1_TIM5EN\n#endif /* TIM5 */\n#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR1_TIM6EN\n#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR1_TIM7EN\n#if defined(LCD)\n#define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR1_LCDEN\n#endif /* LCD */\n#if defined(RCC_APB1ENR1_RTCAPBEN)\n#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR1_RTCAPBEN\n#endif /* RCC_APB1ENR1_RTCAPBEN */\n#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR1_WWDGEN\n#if defined(SPI2)\n#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR1_SPI2EN\n#endif /* SPI2 */\n#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR1_SPI3EN\n#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR1_USART2EN\n#if defined(USART3)\n#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR1_USART3EN\n#endif /* USART3 */\n#if defined(UART4)\n#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR1_UART4EN\n#endif /* UART4 */\n#if defined(UART5)\n#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR1_UART5EN\n#endif /* UART5 */\n#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR1_I2C1EN\n#if defined(I2C2)\n#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR1_I2C2EN\n#endif /* I2C2 */\n#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR1_I2C3EN\n#if defined(CRS)\n#define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR1_CRSEN\n#endif /* CRS */\n#define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR1_CAN1EN\n#if defined(CAN2)\n#define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR1_CAN2EN\n#endif /* CAN2 */\n#if defined(USB)\n#define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR1_USBFSEN\n#endif /* USB */\n#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR1_PWREN\n#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR1_DAC1EN\n#define LL_APB1_GRP1_PERIPH_OPAMP          RCC_APB1ENR1_OPAMPEN\n#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR1_LPTIM1EN\n/**\n  * @}\n  */\n\n\n/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH\n  * @{\n  */\n#define LL_APB1_GRP2_PERIPH_ALL            0xFFFFFFFFU\n#define LL_APB1_GRP2_PERIPH_LPUART1        RCC_APB1ENR2_LPUART1EN\n#if defined(I2C4)\n#define LL_APB1_GRP2_PERIPH_I2C4           RCC_APB1ENR2_I2C4EN\n#endif /* I2C4 */\n#if defined(SWPMI1)\n#define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1ENR2_SWPMI1EN\n#endif /* SWPMI1 */\n#define LL_APB1_GRP2_PERIPH_LPTIM2         RCC_APB1ENR2_LPTIM2EN\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH\n  * @{\n  */\n#define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU\n#define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN\n#define LL_APB2_GRP1_PERIPH_FW             RCC_APB2ENR_FWEN\n#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)\n#define LL_APB2_GRP1_PERIPH_SDMMC1         RCC_APB2ENR_SDMMC1EN\n#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */\n#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN\n#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN\n#if defined(TIM8)\n#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN\n#endif /* TIM8 */\n#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN\n#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN\n#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN\n#if defined(TIM17)\n#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN\n#endif /* TIM17 */\n#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN\n#if defined(SAI2)\n#define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN\n#endif /* SAI2 */\n#if defined(DFSDM1_Channel0)\n#define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN\n#endif /* DFSDM1_Channel0 */\n#if defined(LTDC)\n#define LL_APB2_GRP1_PERIPH_LTDC           RCC_APB2ENR_LTDCEN\n#endif /* LTDC */\n#if defined(DSI)\n#define LL_APB2_GRP1_PERIPH_DSI            RCC_APB2ENR_DSIEN\n#endif /* DSI */\n/**\n  * @}\n  */\n\n/** Legacy definitions for compatibility purpose\n@cond 0\n*/\n#if defined(DFSDM1_Channel0)\n#define LL_APB2_GRP1_PERIPH_DFSDM          LL_APB2_GRP1_PERIPH_DFSDM1\n#endif /* DFSDM1_Channel0 */\n/**\n@endcond\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions\n  * @{\n  */\n\n/** @defgroup BUS_LL_EF_AHB1 AHB1\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB1 peripherals clock.\n  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMAMUX1EN     LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      TSCEN         LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      DMA2DEN       LL_AHB1_GRP1_EnableClock\\n\n  *         AHB1ENR      GFXMMUEN      LL_AHB1_GRP1_EnableClock  \n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB1ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB1 peripheral clock is enabled or not\n  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMAMUX1EN     LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      TSCEN         LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      DMA2DEN       LL_AHB1_GRP1_IsEnabledClock\\n\n  *         AHB1ENR      GFXMMUEN      LL_AHB1_GRP1_IsEnabledClock  \n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB1 peripherals clock.\n  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMAMUX1EN     LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      FLASHEN       LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      TSCEN         LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      DMA2DEN       LL_AHB1_GRP1_DisableClock\\n\n  *         AHB1ENR      GFXMMUEN      LL_AHB1_GRP1_DisableClock  \n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB1 peripherals reset.\n  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMAMUX1RST     LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ForceReset\\n\n  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\\n \n  *         AHB1RSTR     GFXMMURST     LL_AHB1_GRP1_ForceReset \n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB1 peripherals reset.\n  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMAMUX1RST     LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     FLASHRST      LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     TSCRST        LL_AHB1_GRP1_ReleaseReset\\n\n  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\\n \n  *         AHB1RSTR     GFXMMURST     LL_AHB1_GRP1_ReleaseReset \n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB1 peripheral clocks in Sleep and Stop modes\n  * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_EnableClockStopSleep\\n\n  *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_EnableClockStopSleep\\n\n  *         AHB1SMENR    DMAMUX1SMEN   LL_AHB1_GRP1_EnableClockStopSleep\\n\n  *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_EnableClockStopSleep\\n\n  *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_EnableClockStopSleep\\n\n  *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_EnableClockStopSleep\\n\n  *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_EnableClockStopSleep\\n\n  *         AHB1SMENR    DMA2DSMEN     LL_AHB1_GRP1_EnableClockStopSleep\\n\n  *         AHB1SMENR    GFXMMUSMEN    LL_AHB1_GRP1_EnableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB1SMENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB1 peripheral clocks in Sleep and Stop modes\n  * @rmtoll AHB1SMENR    DMA1SMEN      LL_AHB1_GRP1_DisableClockStopSleep\\n\n  *         AHB1SMENR    DMA2SMEN      LL_AHB1_GRP1_DisableClockStopSleep\\n\n  *         AHB1SMENR    DMAMUX1SMEN   LL_AHB1_GRP1_DisableClockStopSleep\\n\n  *         AHB1SMENR    FLASHSMEN     LL_AHB1_GRP1_DisableClockStopSleep\\n\n  *         AHB1SMENR    SRAM1SMEN     LL_AHB1_GRP1_DisableClockStopSleep\\n\n  *         AHB1SMENR    CRCSMEN       LL_AHB1_GRP1_DisableClockStopSleep\\n\n  *         AHB1SMENR    TSCSMEN       LL_AHB1_GRP1_DisableClockStopSleep\\n\n  *         AHB1SMENR    DMA2DSMEN     LL_AHB1_GRP1_DisableClockStopSleep\\n\n  *         AHB1SMENR    GFXMMUSMEN    LL_AHB1_GRP1_DisableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLASH\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)\n  *         @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB1SMENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EF_AHB2 AHB2\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB2 peripherals clock.\n  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      GPIOIEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      ADCEN         LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      AESEN         LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      OSPIMEN       LL_AHB2_GRP1_EnableClock\\n\n  *         AHB2ENR      SDMMC1EN      LL_AHB2_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB2ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB2 peripheral clock is enabled or not\n  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      GPIOIEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      ADCEN         LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      AESEN         LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      OSPIMEN       LL_AHB2_GRP1_IsEnabledClock\\n\n  *         AHB2ENR      SDMMC1EN      LL_AHB2_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB2 peripherals clock.\n  * @rmtoll AHB2ENR      GPIOAEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      GPIOBEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      GPIOCEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      GPIODEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      GPIOEEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      GPIOFEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      GPIOGEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      GPIOHEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      GPIOIEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      OTGFSEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      ADCEN         LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      AESEN         LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      OSPIMEN       LL_AHB2_GRP1_DisableClock\\n\n  *         AHB2ENR      SDMMC1EN      LL_AHB2_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB2 peripherals reset.\n  * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     GPIOFRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     GPIOGRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     GPIOIRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     OTGFSRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     AESRST        LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     OSPIMRST      LL_AHB2_GRP1_ForceReset\\n\n  *         AHB2RSTR     SDMMC1RST     LL_AHB2_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB2 peripherals reset.\n  * @rmtoll AHB2RSTR     GPIOARST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     GPIOBRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     GPIOCRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     GPIODRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     GPIOERST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     GPIOFRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     GPIOGRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     GPIOHRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     GPIOIRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     OTGFSRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     ADCRST        LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     AESRST        LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     OSPIMRST      LL_AHB2_GRP1_ReleaseReset\\n\n  *         AHB2RSTR     SDMMC1RST     LL_AHB2_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB2 peripheral clocks in Sleep and Stop modes\n  * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    GPIOISMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    SRAM3SMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    OTGFSSMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    DCMISMEN      LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    HASHSMEN      LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    OSPIMSMEN     LL_AHB2_GRP1_EnableClockStopSleep\\n\n  *         AHB2SMENR    SDMMC1SMEN    LL_AHB2_GRP1_EnableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB2SMENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB2 peripheral clocks in Sleep and Stop modes\n  * @rmtoll AHB2SMENR    GPIOASMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    GPIOBSMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    GPIOCSMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    GPIODSMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    GPIOESMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    GPIOFSMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    GPIOGSMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    GPIOHSMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    GPIOISMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    SRAM2SMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    SRAM3SMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    OTGFSSMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    ADCSMEN       LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    DCMISMEN      LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    AESSMEN       LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    HASHSMEN      LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    RNGSMEN       LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    OSPIMSMEN     LL_AHB2_GRP1_DisableClockStopSleep\\n\n  *         AHB2SMENR    SDMMC1SMEN    LL_AHB2_GRP1_DisableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ADC\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB2SMENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EF_AHB3 AHB3\n  * @{\n  */\n\n/**\n  * @brief  Enable AHB3 peripherals clock.\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\\n\n  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_EnableClock\\n\n  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB3ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if AHB3 peripheral clock is enabled or not\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\\n\n  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_IsEnabledClock\\n\n  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable AHB3 peripherals clock.\n  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\\n\n  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\\n\n  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_DisableClock\\n\n  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3ENR, Periphs);\n}\n\n/**\n  * @brief  Force AHB3 peripherals reset.\n  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\\n\n  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\\n\n  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ForceReset\\n\n  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->AHB3RSTR, Periphs);\n}\n\n/**\n  * @brief  Release AHB3 peripherals reset.\n  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\\n\n  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\\n\n  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ReleaseReset\\n\n  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable AHB3 peripheral clocks in Sleep and Stop modes\n  * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_EnableClockStopSleep\\n\n  *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_EnableClockStopSleep\\n\n  *         AHB3SMENR    OSPI1SMEN     LL_AHB3_GRP1_EnableClockStopSleep\\n\n  *         AHB3SMENR    OSPI2SMEN     LL_AHB3_GRP1_EnableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->AHB3SMENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable AHB3 peripheral clocks in Sleep and Stop modes\n  * @rmtoll AHB3SMENR    FMCSMEN       LL_AHB3_GRP1_DisableClockStopSleep\\n\n  *         AHB3SMENR    QSPISMEN      LL_AHB3_GRP1_DisableClockStopSleep\\n\n  *         AHB3SMENR    OSPI1SMEN     LL_AHB3_GRP1_DisableClockStopSleep\\n\n  *         AHB3SMENR    OSPI2SMEN     LL_AHB3_GRP1_DisableClockStopSleep\\n\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)\n  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->AHB3SMENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EF_APB1 APB1\n  * @{\n  */\n\n/**\n  * @brief  Enable APB1 peripherals clock.\n  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     LCDEN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     USART2EN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     USART3EN      LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     UART4EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     UART5EN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     CRSEN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     CAN1EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     USBFSEN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     CAN2EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     PWREN         LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     DAC1EN        LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_EnableClock\\n\n  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB1ENR1, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Enable APB1 peripherals clock.\n  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_EnableClock\\n\n  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_EnableClock\\n\n  *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_EnableClock\\n\n  *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1\n  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB1ENR2, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if APB1 peripheral clock is enabled or not\n  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     LCDEN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     USART2EN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     USART3EN      LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     UART4EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     UART5EN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     CRSEN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     CAN1EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     USBFSEN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     CAN2EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     PWREN         LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     DAC1EN        LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_IsEnabledClock\\n\n  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Check if APB1 peripheral clock is enabled or not\n  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_IsEnabledClock\\n\n  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_IsEnabledClock\\n\n  *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_IsEnabledClock\\n\n  *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1\n  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable APB1 peripherals clock.\n  * @rmtoll APB1ENR1     TIM2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     TIM3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     TIM4EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     TIM5EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     TIM6EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     TIM7EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     LCDEN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     RTCAPBEN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     WWDGEN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     SPI2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     SPI3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     USART2EN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     USART3EN      LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     UART4EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     UART5EN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     I2C1EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     I2C2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     I2C3EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     CRSEN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     CAN1EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     USBFSEN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     CAN2EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     PWREN         LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     DAC1EN        LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     OPAMPEN       LL_APB1_GRP1_DisableClock\\n\n  *         APB1ENR1     LPTIM1EN      LL_APB1_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1ENR1, Periphs);\n}\n\n/**\n  * @brief  Disable APB1 peripherals clock.\n  * @rmtoll APB1ENR2     LPUART1EN     LL_APB1_GRP2_DisableClock\\n\n  *         APB1ENR2     I2C4EN        LL_APB1_GRP2_DisableClock\\n\n  *         APB1ENR2     SWPMI1EN      LL_APB1_GRP2_DisableClock\\n\n  *         APB1ENR2     LPTIM2EN      LL_APB1_GRP2_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1\n  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1ENR2, Periphs);\n}\n\n/**\n  * @brief  Force APB1 peripherals reset.\n  * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    TIM3RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    TIM4RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    TIM5RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    TIM6RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    TIM7RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    SPI3RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    USART2RST     LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    USART3RST     LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    UART4RST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    UART5RST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    I2C2RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    CAN1RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    USBFSRST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    CAN2RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    PWRRST        LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    DAC1RST       LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    OPAMPRST      LL_APB1_GRP1_ForceReset\\n\n  *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->APB1RSTR1, Periphs);\n}\n\n/**\n  * @brief  Force APB1 peripherals reset.\n  * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ForceReset\\n\n  *         APB1RSTR2    I2C4RST       LL_APB1_GRP2_ForceReset\\n\n  *         APB1RSTR2    SWPMI1RST     LL_APB1_GRP2_ForceReset\\n\n  *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP2_PERIPH_ALL\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1\n  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->APB1RSTR2, Periphs);\n}\n\n/**\n  * @brief  Release APB1 peripherals reset.\n  * @rmtoll APB1RSTR1    TIM2RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    TIM3RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    TIM4RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    TIM5RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    TIM6RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    TIM7RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    LCDRST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    SPI2RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    SPI3RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    USART2RST     LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    USART3RST     LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    UART4RST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    UART5RST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    I2C1RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    I2C2RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    I2C3RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    CRSRST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    CAN1RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    USBFSRST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    CAN2RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    PWRRST        LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    DAC1RST       LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    OPAMPRST      LL_APB1_GRP1_ReleaseReset\\n\n  *         APB1RSTR1    LPTIM1RST     LL_APB1_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_ALL\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1RSTR1, Periphs);\n}\n\n/**\n  * @brief  Release APB1 peripherals reset.\n  * @rmtoll APB1RSTR2    LPUART1RST    LL_APB1_GRP2_ReleaseReset\\n\n  *         APB1RSTR2    I2C4RST       LL_APB1_GRP2_ReleaseReset\\n\n  *         APB1RSTR2    SWPMI1RST     LL_APB1_GRP2_ReleaseReset\\n\n  *         APB1RSTR2    LPTIM2RST     LL_APB1_GRP2_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP2_PERIPH_ALL\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1\n  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1RSTR2, Periphs);\n}\n\n/**\n  * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes\n  * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   TIM3SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   TIM4SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   TIM5SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   TIM6SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   TIM7SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   SPI3SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   USART2SMEN    LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   USART3SMEN    LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   UART4SMEN     LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   UART5SMEN     LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   I2C2SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   CAN1SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   USBFSSMEN     LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   CAN2SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   PWRSMEN       LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   DAC1SMEN      LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   OPAMPSMEN     LL_APB1_GRP1_EnableClockStopSleep\\n\n  *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_EnableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB1SMENR1, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Enable APB1 peripheral clocks in Sleep and Stop modes\n  * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_EnableClockStopSleep\\n\n  *         APB1SMENR2   I2C4SMEN      LL_APB1_GRP2_EnableClockStopSleep\\n\n  *         APB1SMENR2   SWPMI1SMEN    LL_APB1_GRP2_EnableClockStopSleep\\n\n  *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_EnableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1\n  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB1SMENR2, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes\n  * @rmtoll APB1SMENR1   TIM2SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   TIM3SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   TIM4SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   TIM5SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   TIM6SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   TIM7SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   LCDSMEN       LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   RTCAPBSMEN    LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   WWDGSMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   SPI2SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   SPI3SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   USART2SMEN    LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   USART3SMEN    LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   UART4SMEN     LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   UART5SMEN     LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   I2C1SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   I2C2SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   I2C3SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   CRSSMEN       LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   CAN1SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   USBFSSMEN     LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   CAN2SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   PWRSMEN       LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   DAC1SMEN      LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   OPAMPSMEN     LL_APB1_GRP1_DisableClockStopSleep\\n\n  *         APB1SMENR1   LPTIM1SMEN    LL_APB1_GRP1_DisableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6\n  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)\n  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR\n  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1\n  *         @arg @ref LL_APB1_GRP1_PERIPH_OPAMP\n  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1SMENR1, Periphs);\n}\n\n/**\n  * @brief  Disable APB1 peripheral clocks in Sleep and Stop modes\n  * @rmtoll APB1SMENR2   LPUART1SMEN   LL_APB1_GRP2_DisableClockStopSleep\\n\n  *         APB1SMENR2   I2C4SMEN      LL_APB1_GRP2_DisableClockStopSleep\\n\n  *         APB1SMENR2   SWPMI1SMEN    LL_APB1_GRP2_DisableClockStopSleep\\n\n  *         APB1SMENR2   LPTIM2SMEN    LL_APB1_GRP2_DisableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPUART1\n  *         @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)\n  *         @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB1SMENR2, Periphs);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup BUS_LL_EF_APB2 APB2\n  * @{\n  */\n\n/**\n  * @brief  Enable APB2 peripherals clock.\n  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      FWEN          LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      LTDCEN        LL_APB2_GRP1_EnableClock\\n\n  *         APB2ENR      DSIEN         LL_APB2_GRP1_EnableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_FW\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB2ENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Check if APB2 peripheral clock is enabled or not\n  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      FWEN          LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      LTDCEN        LL_APB2_GRP1_IsEnabledClock\\n\n  *         APB2ENR      DSIEN         LL_APB2_GRP1_IsEnabledClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_FW\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval State of Periphs (1 or 0).\n*/\n__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)\n{\n  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);\n}\n\n/**\n  * @brief  Disable APB2 peripherals clock.\n  * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      SDMMC1EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      LTDCEN        LL_APB2_GRP1_DisableClock\\n\n  *         APB2ENR      DSIEN         LL_APB2_GRP1_DisableClock\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2ENR, Periphs);\n}\n\n/**\n  * @brief  Force APB2 peripherals reset.\n  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SDMMC1RST     LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     LTDCRST       LL_APB2_GRP1_ForceReset\\n\n  *         APB2RSTR     DSIRST        LL_APB2_GRP1_ForceReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)\n{\n  SET_BIT(RCC->APB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Release APB2 peripherals reset.\n  * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SDMMC1RST     LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     LTDCRST       LL_APB2_GRP1_ReleaseReset\\n\n  *         APB2RSTR     DSIRST        LL_APB2_GRP1_ReleaseReset\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2RSTR, Periphs);\n}\n\n/**\n  * @brief  Enable APB2 peripheral clocks in Sleep and Stop modes\n  * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    SDMMC1SMEN    LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    TIM1SMEN      LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    TIM8SMEN      LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    TIM15SMEN     LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    SAI2SMEN      LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    DFSDM1SMEN    LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    LTDCSMEN      LL_APB2_GRP1_EnableClockStopSleep\\n\n  *         APB2SMENR    DSISMEN       LL_APB2_GRP1_EnableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)\n{\n  __IO uint32_t tmpreg;\n  SET_BIT(RCC->APB2SMENR, Periphs);\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);\n  (void)tmpreg;\n}\n\n/**\n  * @brief  Disable APB2 peripheral clocks in Sleep and Stop modes\n  * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    SDMMC1SMEN    LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    TIM1SMEN      LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    TIM8SMEN      LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    TIM15SMEN     LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    TIM16SMEN     LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    TIM17SMEN     LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    SAI1SMEN      LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    SAI2SMEN      LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    DFSDM1SMEN    LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    LTDCSMEN      LL_APB2_GRP1_DisableClockStopSleep\\n\n  *         APB2SMENR    DSISMEN       LL_APB2_GRP1_DisableClockStopSleep\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16\n  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1\n  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)\n  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n*/\n__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)\n{\n  CLEAR_BIT(RCC->APB2SMENR, Periphs);\n}\n\n/**\n  * @}\n  */\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_BUS_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_cortex.h\n  * @author  MCD Application Team\n  * @brief   Header file of CORTEX LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL CORTEX driver contains a set of generic APIs that can be\n    used by user:\n      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick\n          functions\n      (+) Low power mode configuration (SCB register of Cortex-MCU)\n      (+) MPU API to configure and enable regions\n      (+) API to access to MCU info (CPUID register)\n      (+) API to enable fault handler (SHCSR accesses)\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_CORTEX_H\n#define __STM32L4xx_LL_CORTEX_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n/** @defgroup CORTEX_LL CORTEX\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n\n/* Private macros ------------------------------------------------------------*/\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants\n  * @{\n  */\n\n/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source\n  * @{\n  */\n#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/\n#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type\n  * @{\n  */\n#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */\n#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */\n#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */\n/**\n  * @}\n  */\n\n#if __MPU_PRESENT\n\n/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control\n  * @{\n  */\n#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */\n#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */\n#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */\n#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION MPU Region Number\n  * @{\n  */\n#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */\n#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */\n#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */\n#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */\n#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */\n#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */\n#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */\n#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size\n  * @{\n  */\n#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */\n#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges\n  * @{\n  */\n#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/\n#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/\n#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */\n#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */\n#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/\n#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level\n  * @{\n  */\n#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */\n#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */\n#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */\n#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access\n  * @{\n  */\n#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */\n#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */\n#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */\n#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access\n  * @{\n  */\n#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */\n#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */\n/**\n  * @}\n  */\n#endif /* __MPU_PRESENT */\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions\n  * @{\n  */\n\n/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK\n  * @{\n  */\n\n/**\n  * @brief  This function checks if the Systick counter flag is active or not.\n  * @note   It can be used in timeout function on application side.\n  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)\n{\n  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));\n}\n\n/**\n  * @brief  Configures the SysTick clock source\n  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)\n{\n  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)\n  {\n    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n  }\n  else\n  {\n    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n  }\n}\n\n/**\n  * @brief  Get the SysTick clock source\n  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8\n  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)\n{\n  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);\n}\n\n/**\n  * @brief  Enable SysTick exception request\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_EnableIT(void)\n{\n  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);\n}\n\n/**\n  * @brief  Disable SysTick exception request\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSTICK_DisableIT(void)\n{\n  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);\n}\n\n/**\n  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.\n  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)\n{\n  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE\n  * @{\n  */\n\n/**\n  * @brief  Processor uses sleep as its low power mode\n  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableSleep(void)\n{\n  /* Clear SLEEPDEEP bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n}\n\n/**\n  * @brief  Processor uses deep sleep as its low power mode\n  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)\n{\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n}\n\n/**\n  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.\n  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an\n  *         empty main application.\n  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)\n{\n  /* Set SLEEPONEXIT bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\n}\n\n/**\n  * @brief  Do not sleep when returning to Thread mode.\n  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)\n{\n  /* Clear SLEEPONEXIT bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\n}\n\n/**\n  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the\n  *         processor.\n  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)\n{\n  /* Set SEVEONPEND bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\n}\n\n/**\n  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are\n  *         excluded\n  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)\n{\n  /* Clear SEVEONPEND bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_HANDLER HANDLER\n  * @{\n  */\n\n/**\n  * @brief  Enable a fault in System handler control register (SHCSR)\n  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault\n  * @param  Fault This parameter can be a combination of the following values:\n  *         @arg @ref LL_HANDLER_FAULT_USG\n  *         @arg @ref LL_HANDLER_FAULT_BUS\n  *         @arg @ref LL_HANDLER_FAULT_MEM\n  * @retval None\n  */\n__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)\n{\n  /* Enable the system handler fault */\n  SET_BIT(SCB->SHCSR, Fault);\n}\n\n/**\n  * @brief  Disable a fault in System handler control register (SHCSR)\n  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault\n  * @param  Fault This parameter can be a combination of the following values:\n  *         @arg @ref LL_HANDLER_FAULT_USG\n  *         @arg @ref LL_HANDLER_FAULT_BUS\n  *         @arg @ref LL_HANDLER_FAULT_MEM\n  * @retval None\n  */\n__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)\n{\n  /* Disable the system handler fault */\n  CLEAR_BIT(SCB->SHCSR, Fault);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO\n  * @{\n  */\n\n/**\n  * @brief  Get Implementer code\n  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer\n  * @retval Value should be equal to 0x41 for ARM\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);\n}\n\n/**\n  * @brief  Get Variant number (The r value in the rnpn product revision identifier)\n  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant\n  * @retval Value between 0 and 255 (0x0: revision 0)\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);\n}\n\n/**\n  * @brief  Get Constant number\n  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant\n  * @retval Value should be equal to 0xF for Cortex-M4 devices\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);\n}\n\n/**\n  * @brief  Get Part number\n  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo\n  * @retval Value should be equal to 0xC24 for Cortex-M4\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);\n}\n\n/**\n  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)\n  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision\n  * @retval Value between 0 and 255 (0x1: patch 1)\n  */\n__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)\n{\n  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);\n}\n\n/**\n  * @}\n  */\n\n#if __MPU_PRESENT\n/** @defgroup CORTEX_LL_EF_MPU MPU\n  * @{\n  */\n\n/**\n  * @brief  Enable MPU with input options\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable\n  * @param  Options This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE\n  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI\n  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT\n  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)\n{\n  /* Enable the MPU*/\n  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));\n  /* Ensure MPU settings take effects */\n  __DSB();\n  /* Sequence instruction fetches using update settings */\n  __ISB();\n}\n\n/**\n  * @brief  Disable MPU\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_Disable(void)\n{\n  /* Make sure outstanding transfers are done */\n  __DMB();\n  /* Disable MPU*/\n  WRITE_REG(MPU->CTRL, 0U);\n}\n\n/**\n  * @brief  Check if MPU is enabled or not\n  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)\n{\n  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));\n}\n\n/**\n  * @brief  Enable a MPU region\n  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)\n{\n  /* Set Region number */\n  WRITE_REG(MPU->RNR, Region);\n  /* Enable the MPU region */\n  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);\n}\n\n/**\n  * @brief  Configure and enable a region\n  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\\n\n  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\\n\n  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     XN            LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     AP            LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     S             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     C             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     B             LL_MPU_ConfigRegion\\n\n  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @param  Address Value of region base address\n  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF\n  * @param  Attributes This parameter can be a combination of the following values:\n  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B\n  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB\n  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB\n  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB\n  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB\n  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB\n  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS\n  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO\n  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4\n  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE\n  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE\n  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE\n  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)\n{\n  /* Set Region number */\n  WRITE_REG(MPU->RNR, Region);\n  /* Set base address */\n  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));\n  /* Configure MPU */\n  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));\n}\n\n/**\n  * @brief  Disable a region\n  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\\n\n  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion\n  * @param  Region This parameter can be one of the following values:\n  *         @arg @ref LL_MPU_REGION_NUMBER0\n  *         @arg @ref LL_MPU_REGION_NUMBER1\n  *         @arg @ref LL_MPU_REGION_NUMBER2\n  *         @arg @ref LL_MPU_REGION_NUMBER3\n  *         @arg @ref LL_MPU_REGION_NUMBER4\n  *         @arg @ref LL_MPU_REGION_NUMBER5\n  *         @arg @ref LL_MPU_REGION_NUMBER6\n  *         @arg @ref LL_MPU_REGION_NUMBER7\n  * @retval None\n  */\n__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)\n{\n  /* Set Region number */\n  WRITE_REG(MPU->RNR, Region);\n  /* Disable the MPU region */\n  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);\n}\n\n/**\n  * @}\n  */\n\n#endif /* __MPU_PRESENT */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_CORTEX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_dma.h\n  * @author  MCD Application Team\n  * @brief   Header file of DMA LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_DMA_H\n#define __STM32L4xx_LL_DMA_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n#if defined(DMAMUX1)\n#include \"stm32l4xx_ll_dmamux.h\"\n#endif /* DMAMUX1 */\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (DMA1) || defined (DMA2)\n\n/** @defgroup DMA_LL DMA\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup DMA_LL_Private_Variables DMA Private Variables\n  * @{\n  */\n/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */\nstatic const uint8_t CHANNEL_OFFSET_TAB[] =\n{\n  (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),\n  (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)\n};\n/**\n  * @}\n  */\n\n/* Private constants ---------------------------------------------------------*/\n#if defined(DMAMUX1)\n#else\n/** @defgroup DMA_LL_Private_Constants DMA Private Constants\n  * @{\n  */\n/* Define used to get CSELR register offset */\n#define DMA_CSELR_OFFSET                  (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)\n\n/* Defines used for the bit position in the register and perform offsets */\n#define DMA_POSITION_CSELR_CXS            POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))\n/**\n  * @}\n  */\n#endif /* DMAMUX1 */\n\n/* Private macros ------------------------------------------------------------*/\n#if defined(DMAMUX1)\n/** @defgroup DMA_LL_Private_Macros DMA Private Macros\n  * @{\n  */\n/**\n  * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel\n  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.\n  *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.\n  * @param  __DMA_INSTANCE__ DMAx\n  * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).\n  */\n#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \\\n(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)\n\n/**\n  * @}\n  */\n#else\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup DMA_LL_Private_Macros DMA Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n#endif /* DMAMUX1 */\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure\n  * @{\n  */\ntypedef struct\n{\n  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer\n                                        or as Source base address in case of memory to memory transfer direction.\n\n                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */\n\n  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer\n                                        or as Destination base address in case of memory to memory transfer direction.\n\n                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */\n\n  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,\n                                        from memory to memory or from peripheral to memory.\n                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */\n\n  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.\n                                        This parameter can be a value of @ref DMA_LL_EC_MODE\n                                        @note: The circular buffer mode cannot be used if the memory to memory\n                                               data transfer direction is configured on the selected Channel\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */\n\n  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction\n                                        is incremented or not.\n                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */\n\n  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction\n                                        is incremented or not.\n                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */\n\n  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)\n                                        in case of memory to memory transfer direction.\n                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */\n\n  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)\n                                        in case of memory to memory transfer direction.\n                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */\n\n  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.\n                                        The data unit is equal to the source buffer configuration set in PeripheralSize\n                                        or MemorySize parameters depending in the transfer direction.\n                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */\n#if defined(DMAMUX1)\n\n  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.\n                                        This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */\n#else\n\n  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.\n                                        This parameter can be a value of @ref DMA_LL_EC_REQUEST\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */\n#endif /* DMAMUX1 */\n\n  uint32_t Priority;               /*!< Specifies the channel priority level.\n                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY\n\n                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */\n\n} LL_DMA_InitTypeDef;\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants\n  * @{\n  */\n/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_DMA_WriteReg function\n  * @{\n  */\n#define LL_DMA_IFCR_CGIF1                 DMA_IFCR_CGIF1        /*!< Channel 1 global flag            */\n#define LL_DMA_IFCR_CTCIF1                DMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */\n#define LL_DMA_IFCR_CHTIF1                DMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */\n#define LL_DMA_IFCR_CTEIF1                DMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */\n#define LL_DMA_IFCR_CGIF2                 DMA_IFCR_CGIF2        /*!< Channel 2 global flag            */\n#define LL_DMA_IFCR_CTCIF2                DMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */\n#define LL_DMA_IFCR_CHTIF2                DMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */\n#define LL_DMA_IFCR_CTEIF2                DMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */\n#define LL_DMA_IFCR_CGIF3                 DMA_IFCR_CGIF3        /*!< Channel 3 global flag            */\n#define LL_DMA_IFCR_CTCIF3                DMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */\n#define LL_DMA_IFCR_CHTIF3                DMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */\n#define LL_DMA_IFCR_CTEIF3                DMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */\n#define LL_DMA_IFCR_CGIF4                 DMA_IFCR_CGIF4        /*!< Channel 4 global flag            */\n#define LL_DMA_IFCR_CTCIF4                DMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */\n#define LL_DMA_IFCR_CHTIF4                DMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */\n#define LL_DMA_IFCR_CTEIF4                DMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */\n#define LL_DMA_IFCR_CGIF5                 DMA_IFCR_CGIF5        /*!< Channel 5 global flag            */\n#define LL_DMA_IFCR_CTCIF5                DMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */\n#define LL_DMA_IFCR_CHTIF5                DMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */\n#define LL_DMA_IFCR_CTEIF5                DMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */\n#define LL_DMA_IFCR_CGIF6                 DMA_IFCR_CGIF6        /*!< Channel 6 global flag            */\n#define LL_DMA_IFCR_CTCIF6                DMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */\n#define LL_DMA_IFCR_CHTIF6                DMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */\n#define LL_DMA_IFCR_CTEIF6                DMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */\n#define LL_DMA_IFCR_CGIF7                 DMA_IFCR_CGIF7        /*!< Channel 7 global flag            */\n#define LL_DMA_IFCR_CTCIF7                DMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */\n#define LL_DMA_IFCR_CHTIF7                DMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */\n#define LL_DMA_IFCR_CTEIF7                DMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_DMA_ReadReg function\n  * @{\n  */\n#define LL_DMA_ISR_GIF1                   DMA_ISR_GIF1          /*!< Channel 1 global flag            */\n#define LL_DMA_ISR_TCIF1                  DMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */\n#define LL_DMA_ISR_HTIF1                  DMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */\n#define LL_DMA_ISR_TEIF1                  DMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */\n#define LL_DMA_ISR_GIF2                   DMA_ISR_GIF2          /*!< Channel 2 global flag            */\n#define LL_DMA_ISR_TCIF2                  DMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */\n#define LL_DMA_ISR_HTIF2                  DMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */\n#define LL_DMA_ISR_TEIF2                  DMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */\n#define LL_DMA_ISR_GIF3                   DMA_ISR_GIF3          /*!< Channel 3 global flag            */\n#define LL_DMA_ISR_TCIF3                  DMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */\n#define LL_DMA_ISR_HTIF3                  DMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */\n#define LL_DMA_ISR_TEIF3                  DMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */\n#define LL_DMA_ISR_GIF4                   DMA_ISR_GIF4          /*!< Channel 4 global flag            */\n#define LL_DMA_ISR_TCIF4                  DMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */\n#define LL_DMA_ISR_HTIF4                  DMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */\n#define LL_DMA_ISR_TEIF4                  DMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */\n#define LL_DMA_ISR_GIF5                   DMA_ISR_GIF5          /*!< Channel 5 global flag            */\n#define LL_DMA_ISR_TCIF5                  DMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */\n#define LL_DMA_ISR_HTIF5                  DMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */\n#define LL_DMA_ISR_TEIF5                  DMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */\n#define LL_DMA_ISR_GIF6                   DMA_ISR_GIF6          /*!< Channel 6 global flag            */\n#define LL_DMA_ISR_TCIF6                  DMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */\n#define LL_DMA_ISR_HTIF6                  DMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */\n#define LL_DMA_ISR_TEIF6                  DMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */\n#define LL_DMA_ISR_GIF7                   DMA_ISR_GIF7          /*!< Channel 7 global flag            */\n#define LL_DMA_ISR_TCIF7                  DMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */\n#define LL_DMA_ISR_HTIF7                  DMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */\n#define LL_DMA_ISR_TEIF7                  DMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMA_WriteReg functions\n  * @{\n  */\n#define LL_DMA_CCR_TCIE                   DMA_CCR_TCIE          /*!< Transfer complete interrupt */\n#define LL_DMA_CCR_HTIE                   DMA_CCR_HTIE          /*!< Half Transfer interrupt     */\n#define LL_DMA_CCR_TEIE                   DMA_CCR_TEIE          /*!< Transfer error interrupt    */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_CHANNEL CHANNEL\n  * @{\n  */\n#define LL_DMA_CHANNEL_1                  0x00000001U /*!< DMA Channel 1 */\n#define LL_DMA_CHANNEL_2                  0x00000002U /*!< DMA Channel 2 */\n#define LL_DMA_CHANNEL_3                  0x00000003U /*!< DMA Channel 3 */\n#define LL_DMA_CHANNEL_4                  0x00000004U /*!< DMA Channel 4 */\n#define LL_DMA_CHANNEL_5                  0x00000005U /*!< DMA Channel 5 */\n#define LL_DMA_CHANNEL_6                  0x00000006U /*!< DMA Channel 6 */\n#define LL_DMA_CHANNEL_7                  0x00000007U /*!< DMA Channel 7 */\n#if defined(USE_FULL_LL_DRIVER)\n#define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */\n#endif /*USE_FULL_LL_DRIVER*/\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction\n  * @{\n  */\n#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */\n#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */\n#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_MODE Transfer mode\n  * @{\n  */\n#define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */\n#define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode\n  * @{\n  */\n#define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */\n#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_MEMORY Memory increment mode\n  * @{\n  */\n#define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */\n#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment\n  * @{\n  */\n#define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */\n#define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */\n#define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment\n  * @{\n  */\n#define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */\n#define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */\n#define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level\n  * @{\n  */\n#define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */\n#define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */\n#define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */\n#define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */\n/**\n  * @}\n  */\n\n#if defined(DMAMUX1)\n/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request\n  * @{\n  */\n#define LL_DMAMUX_REQUEST_MEM2MEM          0U   /*!< Memory to memory transfer  */\n#define LL_DMAMUX_REQUEST_GENERATOR0       1U   /*!< DMAMUX request generator 0 */\n#define LL_DMAMUX_REQUEST_GENERATOR1       2U   /*!< DMAMUX request generator 1 */\n#define LL_DMAMUX_REQUEST_GENERATOR2       3U   /*!< DMAMUX request generator 2 */\n#define LL_DMAMUX_REQUEST_GENERATOR3       4U   /*!< DMAMUX request generator 3 */\n#define LL_DMAMUX_REQUEST_ADC1             5U   /*!< DMAMUX ADC1 request        */\n#define LL_DMAMUX_REQUEST_DAC1_CH1         6U   /*!< DMAMUX DAC1 CH1 request    */\n#define LL_DMAMUX_REQUEST_DAC1_CH2         7U   /*!< DMAMUX DAC1 CH2 request    */\n#define LL_DMAMUX_REQUEST_TIM6_UP          8U   /*!< DMAMUX TIM6 UP request     */\n#define LL_DMAMUX_REQUEST_TIM7_UP          9U   /*!< DMAMUX TIM7 UP request     */\n#define LL_DMAMUX_REQUEST_SPI1_RX         10U   /*!< DMAMUX SPI1 RX request     */\n#define LL_DMAMUX_REQUEST_SPI1_TX         11U   /*!< DMAMUX SPI1 TX request     */\n#define LL_DMAMUX_REQUEST_SPI2_RX         12U   /*!< DMAMUX SPI2 RX request     */\n#define LL_DMAMUX_REQUEST_SPI2_TX         13U   /*!< DMAMUX SPI2 TX request     */\n#define LL_DMAMUX_REQUEST_SPI3_RX         14U   /*!< DMAMUX SPI3 RX request     */\n#define LL_DMAMUX_REQUEST_SPI3_TX         15U   /*!< DMAMUX SPI3 TX request     */\n#define LL_DMAMUX_REQUEST_I2C1_RX         16U   /*!< DMAMUX I2C1 RX request     */\n#define LL_DMAMUX_REQUEST_I2C1_TX         17U   /*!< DMAMUX I2C1 TX request     */\n#define LL_DMAMUX_REQUEST_I2C2_RX         18U   /*!< DMAMUX I2C2 RX request     */\n#define LL_DMAMUX_REQUEST_I2C2_TX         19U   /*!< DMAMUX I2C2 TX request     */\n#define LL_DMAMUX_REQUEST_I2C3_RX         20U   /*!< DMAMUX I2C3 RX request     */\n#define LL_DMAMUX_REQUEST_I2C3_TX         21U   /*!< DMAMUX I2C3 TX request     */\n#define LL_DMAMUX_REQUEST_I2C4_RX         22U   /*!< DMAMUX I2C4 RX request     */\n#define LL_DMAMUX_REQUEST_I2C4_TX         23U   /*!< DMAMUX I2C4 TX request     */\n#define LL_DMAMUX_REQUEST_USART1_RX       24U   /*!< DMAMUX USART1 RX request   */\n#define LL_DMAMUX_REQUEST_USART1_TX       25U   /*!< DMAMUX USART1 TX request   */\n#define LL_DMAMUX_REQUEST_USART2_RX       26U   /*!< DMAMUX USART2 RX request   */\n#define LL_DMAMUX_REQUEST_USART2_TX       27U   /*!< DMAMUX USART2 TX request   */\n#define LL_DMAMUX_REQUEST_USART3_RX       28U   /*!< DMAMUX USART3 RX request   */\n#define LL_DMAMUX_REQUEST_USART3_TX       29U   /*!< DMAMUX USART3 TX request   */\n#define LL_DMAMUX_REQUEST_UART4_RX        30U   /*!< DMAMUX UART4 RX request    */\n#define LL_DMAMUX_REQUEST_UART4_TX        31U   /*!< DMAMUX UART4 TX request    */\n#define LL_DMAMUX_REQUEST_UART5_RX        32U   /*!< DMAMUX UART5 RX request    */\n#define LL_DMAMUX_REQUEST_UART5_TX        33U   /*!< DMAMUX UART5 TX request    */\n#define LL_DMAMUX_REQUEST_LPUART1_RX      34U   /*!< DMAMUX LPUART1 RX request  */\n#define LL_DMAMUX_REQUEST_LPUART1_TX      35U   /*!< DMAMUX LPUART1 TX request  */\n#define LL_DMAMUX_REQUEST_SAI1_A          36U   /*!< DMAMUX SAI1 A request      */\n#define LL_DMAMUX_REQUEST_SAI1_B          37U   /*!< DMAMUX SAI1 B request      */\n#define LL_DMAMUX_REQUEST_SAI2_A          38U   /*!< DMAMUX SAI2 A request      */\n#define LL_DMAMUX_REQUEST_SAI2_B          39U   /*!< DMAMUX SAI2 B request      */\n#define LL_DMAMUX_REQUEST_OSPI1           40U   /*!< DMAMUX OCTOSPI1 request    */\n#define LL_DMAMUX_REQUEST_OSPI2           41U   /*!< DMAMUX OCTOSPI2 request    */\n#define LL_DMAMUX_REQUEST_TIM1_CH1        42U   /*!< DMAMUX TIM1 CH1 request    */\n#define LL_DMAMUX_REQUEST_TIM1_CH2        43U   /*!< DMAMUX TIM1 CH2 request    */\n#define LL_DMAMUX_REQUEST_TIM1_CH3        44U   /*!< DMAMUX TIM1 CH3 request    */\n#define LL_DMAMUX_REQUEST_TIM1_CH4        45U   /*!< DMAMUX TIM1 CH4 request    */\n#define LL_DMAMUX_REQUEST_TIM1_UP         46U   /*!< DMAMUX TIM1 UP request     */\n#define LL_DMAMUX_REQUEST_TIM1_TRIG       47U   /*!< DMAMUX TIM1 TRIG request   */\n#define LL_DMAMUX_REQUEST_TIM1_COM        48U   /*!< DMAMUX TIM1 COM request    */\n#define LL_DMAMUX_REQUEST_TIM8_CH1        49U   /*!< DMAMUX TIM8 CH1 request    */\n#define LL_DMAMUX_REQUEST_TIM8_CH2        50U   /*!< DMAMUX TIM8 CH2 request    */\n#define LL_DMAMUX_REQUEST_TIM8_CH3        51U   /*!< DMAMUX TIM8 CH3 request    */\n#define LL_DMAMUX_REQUEST_TIM8_CH4        52U   /*!< DMAMUX TIM8 CH4 request    */\n#define LL_DMAMUX_REQUEST_TIM8_UP         53U   /*!< DMAMUX TIM8 UP request     */\n#define LL_DMAMUX_REQUEST_TIM8_TRIG       54U   /*!< DMAMUX TIM8 TRIG request   */\n#define LL_DMAMUX_REQUEST_TIM8_COM        55U   /*!< DMAMUX TIM8 COM request    */\n#define LL_DMAMUX_REQUEST_TIM2_CH1        56U   /*!< DMAMUX TIM2 CH1 request    */\n#define LL_DMAMUX_REQUEST_TIM2_CH2        57U   /*!< DMAMUX TIM2 CH2 request    */\n#define LL_DMAMUX_REQUEST_TIM2_CH3        58U   /*!< DMAMUX TIM2 CH3 request    */\n#define LL_DMAMUX_REQUEST_TIM2_CH4        59U   /*!< DMAMUX TIM2 CH4 request    */\n#define LL_DMAMUX_REQUEST_TIM2_UP         60U   /*!< DMAMUX TIM2 UP request     */\n#define LL_DMAMUX_REQUEST_TIM3_CH1        61U   /*!< DMAMUX TIM3 CH1 request    */\n#define LL_DMAMUX_REQUEST_TIM3_CH2        62U   /*!< DMAMUX TIM3 CH2 request    */\n#define LL_DMAMUX_REQUEST_TIM3_CH3        63U   /*!< DMAMUX TIM3 CH3 request    */\n#define LL_DMAMUX_REQUEST_TIM3_CH4        64U   /*!< DMAMUX TIM3 CH4 request    */\n#define LL_DMAMUX_REQUEST_TIM3_UP         65U   /*!< DMAMUX TIM3 UP request     */\n#define LL_DMAMUX_REQUEST_TIM3_TRIG       66U   /*!< DMAMUX TIM3 TRIG request   */\n#define LL_DMAMUX_REQUEST_TIM4_CH1        67U   /*!< DMAMUX TIM4 CH1 request    */\n#define LL_DMAMUX_REQUEST_TIM4_CH2        68U   /*!< DMAMUX TIM4 CH2 request    */\n#define LL_DMAMUX_REQUEST_TIM4_CH3        69U   /*!< DMAMUX TIM4 CH3 request    */\n#define LL_DMAMUX_REQUEST_TIM4_CH4        70U   /*!< DMAMUX TIM4 CH4 request    */\n#define LL_DMAMUX_REQUEST_TIM4_UP         71U   /*!< DMAMUX TIM4 UP request     */\n#define LL_DMAMUX_REQUEST_TIM5_CH1        72U   /*!< DMAMUX TIM5 CH1 request    */\n#define LL_DMAMUX_REQUEST_TIM5_CH2        73U   /*!< DMAMUX TIM5 CH2 request    */\n#define LL_DMAMUX_REQUEST_TIM5_CH3        74U   /*!< DMAMUX TIM5 CH3 request    */\n#define LL_DMAMUX_REQUEST_TIM5_CH4        75U   /*!< DMAMUX TIM5 CH4 request    */\n#define LL_DMAMUX_REQUEST_TIM5_UP         76U   /*!< DMAMUX TIM5 UP request     */\n#define LL_DMAMUX_REQUEST_TIM5_TRIG       77U   /*!< DMAMUX TIM5 TRIG request   */\n#define LL_DMAMUX_REQUEST_TIM15_CH1       78U   /*!< DMAMUX TIM15 CH1 request   */\n#define LL_DMAMUX_REQUEST_TIM15_UP        79U   /*!< DMAMUX TIM15 UP request    */\n#define LL_DMAMUX_REQUEST_TIM15_TRIG      80U   /*!< DMAMUX TIM15 TRIG request  */\n#define LL_DMAMUX_REQUEST_TIM15_COM       81U   /*!< DMAMUX TIM15 COM request   */\n#define LL_DMAMUX_REQUEST_TIM16_CH1       82U   /*!< DMAMUX TIM16 CH1 request   */\n#define LL_DMAMUX_REQUEST_TIM16_UP        83U   /*!< DMAMUX TIM16 UP request    */\n#define LL_DMAMUX_REQUEST_TIM17_CH1       84U   /*!< DMAMUX TIM17 CH1 request   */\n#define LL_DMAMUX_REQUEST_TIM17_UP        85U   /*!< DMAMUX TIM17 UP request    */\n#define LL_DMAMUX_REQUEST_DFSDM1_FLT0     86U   /*!< DMAMUX DFSDM1_FLT0 request */\n#define LL_DMAMUX_REQUEST_DFSDM1_FLT1     87U   /*!< DMAMUX DFSDM1_FLT1 request */\n#define LL_DMAMUX_REQUEST_DFSDM1_FLT2     88U   /*!< DMAMUX DFSDM1_FLT2 request */\n#define LL_DMAMUX_REQUEST_DFSDM1_FLT3     89U   /*!< DMAMUX DFSDM1_FLT3 request */\n#define LL_DMAMUX_REQUEST_DCMI            90U   /*!< DMAMUX DCMI request        */\n#define LL_DMAMUX_REQUEST_AES_IN          91U   /*!< DMAMUX AES_IN request      */\n#define LL_DMAMUX_REQUEST_AES_OUT         92U   /*!< DMAMUX AES_OUT request     */\n#define LL_DMAMUX_REQUEST_HASH_IN         93U   /*!< DMAMUX HASH_IN request     */\n/**\n  * @}\n  */\n#else\n/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request\n  * @{\n  */\n#define LL_DMA_REQUEST_0                  0x00000000U /*!< DMA peripheral request 0  */\n#define LL_DMA_REQUEST_1                  0x00000001U /*!< DMA peripheral request 1  */\n#define LL_DMA_REQUEST_2                  0x00000002U /*!< DMA peripheral request 2  */\n#define LL_DMA_REQUEST_3                  0x00000003U /*!< DMA peripheral request 3  */\n#define LL_DMA_REQUEST_4                  0x00000004U /*!< DMA peripheral request 4  */\n#define LL_DMA_REQUEST_5                  0x00000005U /*!< DMA peripheral request 5  */\n#define LL_DMA_REQUEST_6                  0x00000006U /*!< DMA peripheral request 6  */\n#define LL_DMA_REQUEST_7                  0x00000007U /*!< DMA peripheral request 7  */\n/**\n  * @}\n  */\n#endif /* DMAMUX1 */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros\n  * @{\n  */\n\n/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros\n  * @{\n  */\n/**\n  * @brief  Write a value in DMA register\n  * @param  __INSTANCE__ DMA Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in DMA register\n  * @param  __INSTANCE__ DMA Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely\n  * @{\n  */\n/**\n  * @brief  Convert DMAx_Channely into DMAx\n  * @param  __CHANNEL_INSTANCE__ DMAx_Channely\n  * @retval DMAx\n  */\n#if defined(DMA2)\n#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)   \\\n(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ?  DMA2 : DMA1)\n#else\n#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (DMA1)\n#endif\n\n/**\n  * @brief  Convert DMAx_Channely into LL_DMA_CHANNEL_y\n  * @param  __CHANNEL_INSTANCE__ DMAx_Channely\n  * @retval LL_DMA_CHANNEL_y\n  */\n#if defined (DMA2)\n#if defined (DMA2_Channel6) && defined (DMA2_Channel7)\n#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \\\n(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \\\n LL_DMA_CHANNEL_7)\n#else\n#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \\\n(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \\\n LL_DMA_CHANNEL_7)\n#endif\n#else\n#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \\\n(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \\\n ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \\\n LL_DMA_CHANNEL_7)\n#endif\n\n/**\n  * @brief  Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely\n  * @param  __DMA_INSTANCE__ DMAx\n  * @param  __CHANNEL__ LL_DMA_CHANNEL_y\n  * @retval DMAx_Channely\n  */\n#if defined (DMA2)\n#if defined (DMA2_Channel6) && defined (DMA2_Channel7)\n#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \\\n((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \\\n DMA2_Channel7)\n#else\n#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \\\n((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \\\n DMA1_Channel7)\n#endif\n#else\n#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__)   \\\n((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \\\n (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \\\n DMA1_Channel7)\n#endif\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions\n * @{\n */\n\n/** @defgroup DMA_LL_EF_Configuration Configuration\n  * @{\n  */\n/**\n  * @brief  Enable DMA channel.\n  * @rmtoll CCR          EN            LL_DMA_EnableChannel\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);\n}\n\n/**\n  * @brief  Disable DMA channel.\n  * @rmtoll CCR          EN            LL_DMA_DisableChannel\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);\n}\n\n/**\n  * @brief  Check if DMA channel is enabled or disabled.\n  * @rmtoll CCR          EN            LL_DMA_IsEnabledChannel\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_EN) == (DMA_CCR_EN));\n}\n\n/**\n  * @brief  Configure all parameters link to DMA transfer.\n  * @rmtoll CCR          DIR           LL_DMA_ConfigTransfer\\n\n  *         CCR          MEM2MEM       LL_DMA_ConfigTransfer\\n\n  *         CCR          CIRC          LL_DMA_ConfigTransfer\\n\n  *         CCR          PINC          LL_DMA_ConfigTransfer\\n\n  *         CCR          MINC          LL_DMA_ConfigTransfer\\n\n  *         CCR          PSIZE         LL_DMA_ConfigTransfer\\n\n  *         CCR          MSIZE         LL_DMA_ConfigTransfer\\n\n  *         CCR          PL            LL_DMA_ConfigTransfer\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  Configuration This parameter must be a combination of all the following values:\n  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY\n  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR\n  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT\n  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT\n  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD\n  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD\n  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n             DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,\n             Configuration);\n}\n\n/**\n  * @brief  Set Data transfer direction (read from peripheral or from memory).\n  * @rmtoll CCR          DIR           LL_DMA_SetDataTransferDirection\\n\n  *         CCR          MEM2MEM       LL_DMA_SetDataTransferDirection\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  Direction This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n             DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);\n}\n\n/**\n  * @brief  Get Data transfer direction (read from peripheral or from memory).\n  * @rmtoll CCR          DIR           LL_DMA_GetDataTransferDirection\\n\n  *         CCR          MEM2MEM       LL_DMA_GetDataTransferDirection\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_DIR | DMA_CCR_MEM2MEM));\n}\n\n/**\n  * @brief  Set DMA mode circular or normal.\n  * @note The circular buffer mode cannot be used if the memory-to-memory\n  * data transfer is configured on the selected Channel.\n  * @rmtoll CCR          CIRC          LL_DMA_SetMode\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  Mode This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_MODE_NORMAL\n  *         @arg @ref LL_DMA_MODE_CIRCULAR\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,\n             Mode);\n}\n\n/**\n  * @brief  Get DMA mode circular or normal.\n  * @rmtoll CCR          CIRC          LL_DMA_GetMode\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_MODE_NORMAL\n  *         @arg @ref LL_DMA_MODE_CIRCULAR\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_CIRC));\n}\n\n/**\n  * @brief  Set Peripheral increment mode.\n  * @rmtoll CCR          PINC          LL_DMA_SetPeriphIncMode\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_PERIPH_INCREMENT\n  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,\n             PeriphOrM2MSrcIncMode);\n}\n\n/**\n  * @brief  Get Peripheral increment mode.\n  * @rmtoll CCR          PINC          LL_DMA_GetPeriphIncMode\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_PERIPH_INCREMENT\n  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_PINC));\n}\n\n/**\n  * @brief  Set Memory increment mode.\n  * @rmtoll CCR          MINC          LL_DMA_SetMemoryIncMode\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_MEMORY_INCREMENT\n  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,\n             MemoryOrM2MDstIncMode);\n}\n\n/**\n  * @brief  Get Memory increment mode.\n  * @rmtoll CCR          MINC          LL_DMA_GetMemoryIncMode\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_MEMORY_INCREMENT\n  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_MINC));\n}\n\n/**\n  * @brief  Set Peripheral size.\n  * @rmtoll CCR          PSIZE         LL_DMA_SetPeriphSize\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_PDATAALIGN_BYTE\n  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD\n  *         @arg @ref LL_DMA_PDATAALIGN_WORD\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,\n             PeriphOrM2MSrcDataSize);\n}\n\n/**\n  * @brief  Get Peripheral size.\n  * @rmtoll CCR          PSIZE         LL_DMA_GetPeriphSize\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_PDATAALIGN_BYTE\n  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD\n  *         @arg @ref LL_DMA_PDATAALIGN_WORD\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_PSIZE));\n}\n\n/**\n  * @brief  Set Memory size.\n  * @rmtoll CCR          MSIZE         LL_DMA_SetMemorySize\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_MDATAALIGN_BYTE\n  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD\n  *         @arg @ref LL_DMA_MDATAALIGN_WORD\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,\n             MemoryOrM2MDstDataSize);\n}\n\n/**\n  * @brief  Get Memory size.\n  * @rmtoll CCR          MSIZE         LL_DMA_GetMemorySize\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_MDATAALIGN_BYTE\n  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD\n  *         @arg @ref LL_DMA_MDATAALIGN_WORD\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_MSIZE));\n}\n\n/**\n  * @brief  Set Channel priority level.\n  * @rmtoll CCR          PL            LL_DMA_SetChannelPriorityLevel\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  Priority This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_PRIORITY_LOW\n  *         @arg @ref LL_DMA_PRIORITY_MEDIUM\n  *         @arg @ref LL_DMA_PRIORITY_HIGH\n  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,\n             Priority);\n}\n\n/**\n  * @brief  Get Channel priority level.\n  * @rmtoll CCR          PL            LL_DMA_GetChannelPriorityLevel\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_PRIORITY_LOW\n  *         @arg @ref LL_DMA_PRIORITY_MEDIUM\n  *         @arg @ref LL_DMA_PRIORITY_HIGH\n  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_PL));\n}\n\n/**\n  * @brief  Set Number of data to transfer.\n  * @note   This action has no effect if\n  *         channel is enabled.\n  * @rmtoll CNDTR        NDT           LL_DMA_SetDataLength\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)\n{\n  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,\n             DMA_CNDTR_NDT, NbData);\n}\n\n/**\n  * @brief  Get Number of data to transfer.\n  * @note   Once the channel is enabled, the return value indicate the\n  *         remaining bytes to be transmitted.\n  * @rmtoll CNDTR        NDT           LL_DMA_GetDataLength\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,\n                   DMA_CNDTR_NDT));\n}\n\n/**\n  * @brief  Configure the Source and Destination addresses.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).\n  * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\\n\n  *         CMAR         MA            LL_DMA_ConfigAddresses\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  * @param  Direction This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH\n  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,\n                                            uint32_t DstAddress, uint32_t Direction)\n{\n  /* Direction Memory to Periph */\n  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)\n  {\n    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);\n    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);\n  }\n  /* Direction Periph to Memory and Memory to Memory */\n  else\n  {\n    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);\n    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);\n  }\n}\n\n/**\n  * @brief  Set the Memory address.\n  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)\n{\n  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);\n}\n\n/**\n  * @brief  Set the Peripheral address.\n  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)\n{\n  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);\n}\n\n/**\n  * @brief  Get Memory address.\n  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.\n  * @rmtoll CMAR         MA            LL_DMA_GetMemoryAddress\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));\n}\n\n/**\n  * @brief  Get Peripheral address.\n  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.\n  * @rmtoll CPAR         PA            LL_DMA_GetPeriphAddress\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));\n}\n\n/**\n  * @brief  Set the Memory to Memory Source address.\n  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)\n{\n  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);\n}\n\n/**\n  * @brief  Set the Memory to Memory Destination address.\n  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.\n  * @note   This API must not be called when the DMA channel is enabled.\n  * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)\n{\n  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);\n}\n\n/**\n  * @brief  Get the Memory to Memory Source address.\n  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.\n  * @rmtoll CPAR         PA            LL_DMA_GetM2MSrcAddress\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));\n}\n\n/**\n  * @brief  Get the Memory to Memory Destination address.\n  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.\n  * @rmtoll CMAR         MA            LL_DMA_GetM2MDstAddress\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));\n}\n\n#if defined(DMAMUX1)\n/**\n  * @brief  Set DMA request for DMA Channels on DMAMUX Channel x.\n  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.\n  *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.\n  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  Request This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQUEST_MEM2MEM\n  *         @arg @ref LL_DMAMUX_REQUEST_GENERATOR0\n  *         @arg @ref LL_DMAMUX_REQUEST_GENERATOR1\n  *         @arg @ref LL_DMAMUX_REQUEST_GENERATOR2\n  *         @arg @ref LL_DMAMUX_REQUEST_GENERATOR3\n  *         @arg @ref LL_DMAMUX_REQUEST_ADC1\n  *         @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM6_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM7_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI1_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI1_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI2_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI2_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI3_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI3_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C1_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C1_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C2_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C2_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C3_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C3_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C4_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C4_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART1_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART1_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART2_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART2_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART3_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART3_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_UART4_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_UART4_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_UART5_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_UART5_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_SAI1_A\n  *         @arg @ref LL_DMAMUX_REQUEST_SAI1_B\n  *         @arg @ref LL_DMAMUX_REQUEST_SAI2_A\n  *         @arg @ref LL_DMAMUX_REQUEST_SAI2_B\n  *         @arg @ref LL_DMAMUX_REQUEST_OSPI1\n  *         @arg @ref LL_DMAMUX_REQUEST_OSPI2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_COM\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_COM\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM15_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM15_COM\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM16_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM17_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0\n  *         @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1\n  *         @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2\n  *         @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3\n  *         @arg @ref LL_DMAMUX_REQUEST_DCMI\n  *         @arg @ref LL_DMAMUX_REQUEST_AES_IN\n  *         @arg @ref LL_DMAMUX_REQUEST_AES_OUT\n  *         @arg @ref LL_DMAMUX_REQUEST_HASH_IN\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)\n{\n  MODIFY_REG(((DMAMUX_Channel_TypeDef*)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);\n}\n\n/**\n  * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.\n  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.\n  *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.\n  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQUEST_MEM2MEM\n  *         @arg @ref LL_DMAMUX_REQUEST_GENERATOR0\n  *         @arg @ref LL_DMAMUX_REQUEST_GENERATOR1\n  *         @arg @ref LL_DMAMUX_REQUEST_GENERATOR2\n  *         @arg @ref LL_DMAMUX_REQUEST_GENERATOR3\n  *         @arg @ref LL_DMAMUX_REQUEST_ADC1\n  *         @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM6_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM7_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI1_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI1_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI2_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI2_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI3_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_SPI3_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C1_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C1_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C2_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C2_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C3_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C3_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C4_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_I2C4_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART1_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART1_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART2_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART2_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART3_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_USART3_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_UART4_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_UART4_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_UART5_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_UART5_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX\n  *         @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX\n  *         @arg @ref LL_DMAMUX_REQUEST_SAI1_A\n  *         @arg @ref LL_DMAMUX_REQUEST_SAI1_B\n  *         @arg @ref LL_DMAMUX_REQUEST_SAI2_A\n  *         @arg @ref LL_DMAMUX_REQUEST_SAI2_B\n  *         @arg @ref LL_DMAMUX_REQUEST_OSPI1\n  *         @arg @ref LL_DMAMUX_REQUEST_OSPI2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM1_COM\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM8_COM\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM2_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM4_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM15_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM15_COM\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM16_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1\n  *         @arg @ref LL_DMAMUX_REQUEST_TIM17_UP\n  *         @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0\n  *         @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1\n  *         @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2\n  *         @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3\n  *         @arg @ref LL_DMAMUX_REQUEST_DCMI\n  *         @arg @ref LL_DMAMUX_REQUEST_AES_IN\n  *         @arg @ref LL_DMAMUX_REQUEST_AES_OUT\n  *         @arg @ref LL_DMAMUX_REQUEST_HASH_IN\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));\n}\n#else\n/**\n  * @brief  Set DMA request for DMA instance on Channel x.\n  * @note   Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.\n  * @rmtoll CSELR        C1S           LL_DMA_SetPeriphRequest\\n\n  *         CSELR        C2S           LL_DMA_SetPeriphRequest\\n\n  *         CSELR        C3S           LL_DMA_SetPeriphRequest\\n\n  *         CSELR        C4S           LL_DMA_SetPeriphRequest\\n\n  *         CSELR        C5S           LL_DMA_SetPeriphRequest\\n\n  *         CSELR        C6S           LL_DMA_SetPeriphRequest\\n\n  *         CSELR        C7S           LL_DMA_SetPeriphRequest\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  PeriphRequest This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_REQUEST_0\n  *         @arg @ref LL_DMA_REQUEST_1\n  *         @arg @ref LL_DMA_REQUEST_2\n  *         @arg @ref LL_DMA_REQUEST_3\n  *         @arg @ref LL_DMA_REQUEST_4\n  *         @arg @ref LL_DMA_REQUEST_5\n  *         @arg @ref LL_DMA_REQUEST_6\n  *         @arg @ref LL_DMA_REQUEST_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)\n{\n  MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,\n             DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS);\n}\n\n/**\n  * @brief  Get DMA request for DMA instance on Channel x.\n  * @rmtoll CSELR        C1S           LL_DMA_GetPeriphRequest\\n\n  *         CSELR        C2S           LL_DMA_GetPeriphRequest\\n\n  *         CSELR        C3S           LL_DMA_GetPeriphRequest\\n\n  *         CSELR        C4S           LL_DMA_GetPeriphRequest\\n\n  *         CSELR        C5S           LL_DMA_GetPeriphRequest\\n\n  *         CSELR        C6S           LL_DMA_GetPeriphRequest\\n\n  *         CSELR        C7S           LL_DMA_GetPeriphRequest\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMA_REQUEST_0\n  *         @arg @ref LL_DMA_REQUEST_1\n  *         @arg @ref LL_DMA_REQUEST_2\n  *         @arg @ref LL_DMA_REQUEST_3\n  *         @arg @ref LL_DMA_REQUEST_4\n  *         @arg @ref LL_DMA_REQUEST_5\n  *         @arg @ref LL_DMA_REQUEST_6\n  *         @arg @ref LL_DMA_REQUEST_7\n  */\n__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,\n                   DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS);\n}\n#endif /* DMAMUX1 */\n\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Get Channel 1 global interrupt flag.\n  * @rmtoll ISR          GIF1          LL_DMA_IsActiveFlag_GI1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));\n}\n\n/**\n  * @brief  Get Channel 2 global interrupt flag.\n  * @rmtoll ISR          GIF2          LL_DMA_IsActiveFlag_GI2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));\n}\n\n/**\n  * @brief  Get Channel 3 global interrupt flag.\n  * @rmtoll ISR          GIF3          LL_DMA_IsActiveFlag_GI3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));\n}\n\n/**\n  * @brief  Get Channel 4 global interrupt flag.\n  * @rmtoll ISR          GIF4          LL_DMA_IsActiveFlag_GI4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));\n}\n\n/**\n  * @brief  Get Channel 5 global interrupt flag.\n  * @rmtoll ISR          GIF5          LL_DMA_IsActiveFlag_GI5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));\n}\n\n/**\n  * @brief  Get Channel 6 global interrupt flag.\n  * @rmtoll ISR          GIF6          LL_DMA_IsActiveFlag_GI6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));\n}\n\n/**\n  * @brief  Get Channel 7 global interrupt flag.\n  * @rmtoll ISR          GIF7          LL_DMA_IsActiveFlag_GI7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));\n}\n\n/**\n  * @brief  Get Channel 1 transfer complete flag.\n  * @rmtoll ISR          TCIF1         LL_DMA_IsActiveFlag_TC1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));\n}\n\n/**\n  * @brief  Get Channel 2 transfer complete flag.\n  * @rmtoll ISR          TCIF2         LL_DMA_IsActiveFlag_TC2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));\n}\n\n/**\n  * @brief  Get Channel 3 transfer complete flag.\n  * @rmtoll ISR          TCIF3         LL_DMA_IsActiveFlag_TC3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));\n}\n\n/**\n  * @brief  Get Channel 4 transfer complete flag.\n  * @rmtoll ISR          TCIF4         LL_DMA_IsActiveFlag_TC4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));\n}\n\n/**\n  * @brief  Get Channel 5 transfer complete flag.\n  * @rmtoll ISR          TCIF5         LL_DMA_IsActiveFlag_TC5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));\n}\n\n/**\n  * @brief  Get Channel 6 transfer complete flag.\n  * @rmtoll ISR          TCIF6         LL_DMA_IsActiveFlag_TC6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));\n}\n\n/**\n  * @brief  Get Channel 7 transfer complete flag.\n  * @rmtoll ISR          TCIF7         LL_DMA_IsActiveFlag_TC7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));\n}\n\n/**\n  * @brief  Get Channel 1 half transfer flag.\n  * @rmtoll ISR          HTIF1         LL_DMA_IsActiveFlag_HT1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));\n}\n\n/**\n  * @brief  Get Channel 2 half transfer flag.\n  * @rmtoll ISR          HTIF2         LL_DMA_IsActiveFlag_HT2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));\n}\n\n/**\n  * @brief  Get Channel 3 half transfer flag.\n  * @rmtoll ISR          HTIF3         LL_DMA_IsActiveFlag_HT3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));\n}\n\n/**\n  * @brief  Get Channel 4 half transfer flag.\n  * @rmtoll ISR          HTIF4         LL_DMA_IsActiveFlag_HT4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));\n}\n\n/**\n  * @brief  Get Channel 5 half transfer flag.\n  * @rmtoll ISR          HTIF5         LL_DMA_IsActiveFlag_HT5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));\n}\n\n/**\n  * @brief  Get Channel 6 half transfer flag.\n  * @rmtoll ISR          HTIF6         LL_DMA_IsActiveFlag_HT6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));\n}\n\n/**\n  * @brief  Get Channel 7 half transfer flag.\n  * @rmtoll ISR          HTIF7         LL_DMA_IsActiveFlag_HT7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));\n}\n\n/**\n  * @brief  Get Channel 1 transfer error flag.\n  * @rmtoll ISR          TEIF1         LL_DMA_IsActiveFlag_TE1\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));\n}\n\n/**\n  * @brief  Get Channel 2 transfer error flag.\n  * @rmtoll ISR          TEIF2         LL_DMA_IsActiveFlag_TE2\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));\n}\n\n/**\n  * @brief  Get Channel 3 transfer error flag.\n  * @rmtoll ISR          TEIF3         LL_DMA_IsActiveFlag_TE3\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));\n}\n\n/**\n  * @brief  Get Channel 4 transfer error flag.\n  * @rmtoll ISR          TEIF4         LL_DMA_IsActiveFlag_TE4\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));\n}\n\n/**\n  * @brief  Get Channel 5 transfer error flag.\n  * @rmtoll ISR          TEIF5         LL_DMA_IsActiveFlag_TE5\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));\n}\n\n/**\n  * @brief  Get Channel 6 transfer error flag.\n  * @rmtoll ISR          TEIF6         LL_DMA_IsActiveFlag_TE6\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));\n}\n\n/**\n  * @brief  Get Channel 7 transfer error flag.\n  * @rmtoll ISR          TEIF7         LL_DMA_IsActiveFlag_TE7\n  * @param  DMAx DMAx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)\n{\n  return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));\n}\n\n/**\n  * @brief  Clear Channel 1 global interrupt flag.\n  * @rmtoll IFCR         CGIF1         LL_DMA_ClearFlag_GI1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);\n}\n\n/**\n  * @brief  Clear Channel 2 global interrupt flag.\n  * @rmtoll IFCR         CGIF2         LL_DMA_ClearFlag_GI2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);\n}\n\n/**\n  * @brief  Clear Channel 3 global interrupt flag.\n  * @rmtoll IFCR         CGIF3         LL_DMA_ClearFlag_GI3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);\n}\n\n/**\n  * @brief  Clear Channel 4 global interrupt flag.\n  * @rmtoll IFCR         CGIF4         LL_DMA_ClearFlag_GI4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);\n}\n\n/**\n  * @brief  Clear Channel 5 global interrupt flag.\n  * @rmtoll IFCR         CGIF5         LL_DMA_ClearFlag_GI5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);\n}\n\n/**\n  * @brief  Clear Channel 6 global interrupt flag.\n  * @rmtoll IFCR         CGIF6         LL_DMA_ClearFlag_GI6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);\n}\n\n/**\n  * @brief  Clear Channel 7 global interrupt flag.\n  * @rmtoll IFCR         CGIF7         LL_DMA_ClearFlag_GI7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);\n}\n\n/**\n  * @brief  Clear Channel 1  transfer complete flag.\n  * @rmtoll IFCR         CTCIF1        LL_DMA_ClearFlag_TC1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);\n}\n\n/**\n  * @brief  Clear Channel 2  transfer complete flag.\n  * @rmtoll IFCR         CTCIF2        LL_DMA_ClearFlag_TC2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);\n}\n\n/**\n  * @brief  Clear Channel 3  transfer complete flag.\n  * @rmtoll IFCR         CTCIF3        LL_DMA_ClearFlag_TC3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);\n}\n\n/**\n  * @brief  Clear Channel 4  transfer complete flag.\n  * @rmtoll IFCR         CTCIF4        LL_DMA_ClearFlag_TC4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);\n}\n\n/**\n  * @brief  Clear Channel 5  transfer complete flag.\n  * @rmtoll IFCR         CTCIF5        LL_DMA_ClearFlag_TC5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);\n}\n\n/**\n  * @brief  Clear Channel 6  transfer complete flag.\n  * @rmtoll IFCR         CTCIF6        LL_DMA_ClearFlag_TC6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);\n}\n\n/**\n  * @brief  Clear Channel 7  transfer complete flag.\n  * @rmtoll IFCR         CTCIF7        LL_DMA_ClearFlag_TC7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);\n}\n\n/**\n  * @brief  Clear Channel 1  half transfer flag.\n  * @rmtoll IFCR         CHTIF1        LL_DMA_ClearFlag_HT1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);\n}\n\n/**\n  * @brief  Clear Channel 2  half transfer flag.\n  * @rmtoll IFCR         CHTIF2        LL_DMA_ClearFlag_HT2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);\n}\n\n/**\n  * @brief  Clear Channel 3  half transfer flag.\n  * @rmtoll IFCR         CHTIF3        LL_DMA_ClearFlag_HT3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);\n}\n\n/**\n  * @brief  Clear Channel 4  half transfer flag.\n  * @rmtoll IFCR         CHTIF4        LL_DMA_ClearFlag_HT4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);\n}\n\n/**\n  * @brief  Clear Channel 5  half transfer flag.\n  * @rmtoll IFCR         CHTIF5        LL_DMA_ClearFlag_HT5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);\n}\n\n/**\n  * @brief  Clear Channel 6  half transfer flag.\n  * @rmtoll IFCR         CHTIF6        LL_DMA_ClearFlag_HT6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);\n}\n\n/**\n  * @brief  Clear Channel 7  half transfer flag.\n  * @rmtoll IFCR         CHTIF7        LL_DMA_ClearFlag_HT7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);\n}\n\n/**\n  * @brief  Clear Channel 1 transfer error flag.\n  * @rmtoll IFCR         CTEIF1        LL_DMA_ClearFlag_TE1\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);\n}\n\n/**\n  * @brief  Clear Channel 2 transfer error flag.\n  * @rmtoll IFCR         CTEIF2        LL_DMA_ClearFlag_TE2\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);\n}\n\n/**\n  * @brief  Clear Channel 3 transfer error flag.\n  * @rmtoll IFCR         CTEIF3        LL_DMA_ClearFlag_TE3\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);\n}\n\n/**\n  * @brief  Clear Channel 4 transfer error flag.\n  * @rmtoll IFCR         CTEIF4        LL_DMA_ClearFlag_TE4\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);\n}\n\n/**\n  * @brief  Clear Channel 5 transfer error flag.\n  * @rmtoll IFCR         CTEIF5        LL_DMA_ClearFlag_TE5\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);\n}\n\n/**\n  * @brief  Clear Channel 6 transfer error flag.\n  * @rmtoll IFCR         CTEIF6        LL_DMA_ClearFlag_TE6\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);\n}\n\n/**\n  * @brief  Clear Channel 7 transfer error flag.\n  * @rmtoll IFCR         CTEIF7        LL_DMA_ClearFlag_TE7\n  * @param  DMAx DMAx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)\n{\n  WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup DMA_LL_EF_IT_Management IT_Management\n  * @{\n  */\n/**\n  * @brief  Enable Transfer complete interrupt.\n  * @rmtoll CCR          TCIE          LL_DMA_EnableIT_TC\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);\n}\n\n/**\n  * @brief  Enable Half transfer interrupt.\n  * @rmtoll CCR          HTIE          LL_DMA_EnableIT_HT\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);\n}\n\n/**\n  * @brief  Enable Transfer error interrupt.\n  * @rmtoll CCR          TEIE          LL_DMA_EnableIT_TE\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);\n}\n\n/**\n  * @brief  Disable Transfer complete interrupt.\n  * @rmtoll CCR          TCIE          LL_DMA_DisableIT_TC\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);\n}\n\n/**\n  * @brief  Disable Half transfer interrupt.\n  * @rmtoll CCR          HTIE          LL_DMA_DisableIT_HT\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);\n}\n\n/**\n  * @brief  Disable Transfer error interrupt.\n  * @rmtoll CCR          TEIE          LL_DMA_DisableIT_TE\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);\n}\n\n/**\n  * @brief  Check if Transfer complete Interrupt is enabled.\n  * @rmtoll CCR          TCIE          LL_DMA_IsEnabledIT_TC\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_TCIE) == (DMA_CCR_TCIE));\n}\n\n/**\n  * @brief  Check if Half transfer Interrupt is enabled.\n  * @rmtoll CCR          HTIE          LL_DMA_IsEnabledIT_HT\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_HTIE) == (DMA_CCR_HTIE));\n}\n\n/**\n  * @brief  Check if Transfer error Interrupt is enabled.\n  * @rmtoll CCR          TEIE          LL_DMA_IsEnabledIT_TE\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,\n                   DMA_CCR_TEIE) == (DMA_CCR_TEIE));\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\nuint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);\nuint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);\nvoid LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* DMA1 || DMA2 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_DMA_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dmamux.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_dmamux.h\n  * @author  MCD Application Team\n  * @brief   Header file of DMAMUX LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_DMAMUX_H\n#define __STM32L4xx_LL_DMAMUX_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (DMAMUX1)\n\n/** @defgroup DMAMUX_LL DMAMUX\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants\n  * @{\n  */\n/* Define used to get DMAMUX CCR register size */\n#define DMAMUX_CCR_SIZE                   0x00000004U\n\n/* Define used to get DMAMUX RGCR register size */\n#define DMAMUX_RGCR_SIZE                  0x00000004U\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants\n  * @{\n  */\n/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function\n  * @{\n  */\n#define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0  */\n#define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1  */\n#define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2  */\n#define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3  */\n#define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4  */\n#define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5  */\n#define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6  */\n#define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7  */\n#define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8  */\n#define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9  */\n#define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10 */\n#define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11 */\n#define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12 */\n#define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13 */\n#define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */\n#define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */\n#define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */\n#define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function\n  * @{\n  */\n#define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0  */\n#define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1  */\n#define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2  */\n#define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3  */\n#define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4  */\n#define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5  */\n#define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6  */\n#define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7  */\n#define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8  */\n#define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9  */\n#define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10 */\n#define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11 */\n#define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12 */\n#define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13 */\n#define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */\n#define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */\n#define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */\n#define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions\n  * @{\n  */\n#define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt */\n#define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request\n  * @{\n  */\n#define LL_DMAMUX_REQ_MEM2MEM          0U   /*!< Memory to memory transfer  */\n#define LL_DMAMUX_REQ_GENERATOR0       1U   /*!< DMAMUX request generator 0 */\n#define LL_DMAMUX_REQ_GENERATOR1       2U   /*!< DMAMUX request generator 1 */\n#define LL_DMAMUX_REQ_GENERATOR2       3U   /*!< DMAMUX request generator 2 */\n#define LL_DMAMUX_REQ_GENERATOR3       4U   /*!< DMAMUX request generator 3 */\n#define LL_DMAMUX_REQ_ADC1             5U   /*!< DMAMUX ADC1 request        */\n#define LL_DMAMUX_REQ_DAC1_CH1         6U   /*!< DMAMUX DAC1 CH1 request    */\n#define LL_DMAMUX_REQ_DAC1_CH2         7U   /*!< DMAMUX DAC1 CH2 request    */\n#define LL_DMAMUX_REQ_TIM6_UP          8U   /*!< DMAMUX TIM6 UP request     */\n#define LL_DMAMUX_REQ_TIM7_UP          9U   /*!< DMAMUX TIM7 UP request     */\n#define LL_DMAMUX_REQ_SPI1_RX         10U   /*!< DMAMUX SPI1 RX request     */\n#define LL_DMAMUX_REQ_SPI1_TX         11U   /*!< DMAMUX SPI1 TX request     */\n#define LL_DMAMUX_REQ_SPI2_RX         12U   /*!< DMAMUX SPI2 RX request     */\n#define LL_DMAMUX_REQ_SPI2_TX         13U   /*!< DMAMUX SPI2 TX request     */\n#define LL_DMAMUX_REQ_SPI3_RX         14U   /*!< DMAMUX SPI3 RX request     */\n#define LL_DMAMUX_REQ_SPI3_TX         15U   /*!< DMAMUX SPI3 TX request     */\n#define LL_DMAMUX_REQ_I2C1_RX         16U   /*!< DMAMUX I2C1 RX request     */\n#define LL_DMAMUX_REQ_I2C1_TX         17U   /*!< DMAMUX I2C1 TX request     */\n#define LL_DMAMUX_REQ_I2C2_RX         18U   /*!< DMAMUX I2C2 RX request     */\n#define LL_DMAMUX_REQ_I2C2_TX         19U   /*!< DMAMUX I2C2 TX request     */\n#define LL_DMAMUX_REQ_I2C3_RX         20U   /*!< DMAMUX I2C3 RX request     */\n#define LL_DMAMUX_REQ_I2C3_TX         21U   /*!< DMAMUX I2C3 TX request     */\n#define LL_DMAMUX_REQ_I2C4_RX         22U   /*!< DMAMUX I2C4 RX request     */\n#define LL_DMAMUX_REQ_I2C4_TX         23U   /*!< DMAMUX I2C4 TX request     */\n#define LL_DMAMUX_REQ_USART1_RX       24U   /*!< DMAMUX USART1 RX request   */\n#define LL_DMAMUX_REQ_USART1_TX       25U   /*!< DMAMUX USART1 TX request   */\n#define LL_DMAMUX_REQ_USART2_RX       26U   /*!< DMAMUX USART2 RX request   */\n#define LL_DMAMUX_REQ_USART2_TX       27U   /*!< DMAMUX USART2 TX request   */\n#define LL_DMAMUX_REQ_USART3_RX       28U   /*!< DMAMUX USART3 RX request   */\n#define LL_DMAMUX_REQ_USART3_TX       29U   /*!< DMAMUX USART3 TX request   */\n#define LL_DMAMUX_REQ_UART4_RX        30U   /*!< DMAMUX UART4 RX request    */\n#define LL_DMAMUX_REQ_UART4_TX        31U   /*!< DMAMUX UART4 TX request    */\n#define LL_DMAMUX_REQ_UART5_RX        32U   /*!< DMAMUX UART5 RX request    */\n#define LL_DMAMUX_REQ_UART5_TX        33U   /*!< DMAMUX UART5 TX request    */\n#define LL_DMAMUX_REQ_LPUART1_RX      34U   /*!< DMAMUX LPUART1 RX request  */\n#define LL_DMAMUX_REQ_LPUART1_TX      35U   /*!< DMAMUX LPUART1 TX request  */\n#define LL_DMAMUX_REQ_SAI1_A          36U   /*!< DMAMUX SAI1 A request      */\n#define LL_DMAMUX_REQ_SAI1_B          37U   /*!< DMAMUX SAI1 B request      */\n#define LL_DMAMUX_REQ_SAI2_A          38U   /*!< DMAMUX SAI2 A request      */\n#define LL_DMAMUX_REQ_SAI2_B          39U   /*!< DMAMUX SAI2 B request      */\n#define LL_DMAMUX_REQ_OSPI1           40U   /*!< DMAMUX OCTOSPI1 request    */\n#define LL_DMAMUX_REQ_OSPI2           41U   /*!< DMAMUX OCTOSPI2 request    */\n#define LL_DMAMUX_REQ_TIM1_CH1        42U   /*!< DMAMUX TIM1 CH1 request    */\n#define LL_DMAMUX_REQ_TIM1_CH2        43U   /*!< DMAMUX TIM1 CH2 request    */\n#define LL_DMAMUX_REQ_TIM1_CH3        44U   /*!< DMAMUX TIM1 CH3 request    */\n#define LL_DMAMUX_REQ_TIM1_CH4        45U   /*!< DMAMUX TIM1 CH4 request    */\n#define LL_DMAMUX_REQ_TIM1_UP         46U   /*!< DMAMUX TIM1 UP request     */\n#define LL_DMAMUX_REQ_TIM1_TRIG       47U   /*!< DMAMUX TIM1 TRIG request   */\n#define LL_DMAMUX_REQ_TIM1_COM        48U   /*!< DMAMUX TIM1 COM request    */\n#define LL_DMAMUX_REQ_TIM8_CH1        49U   /*!< DMAMUX TIM8 CH1 request    */\n#define LL_DMAMUX_REQ_TIM8_CH2        50U   /*!< DMAMUX TIM8 CH2 request    */\n#define LL_DMAMUX_REQ_TIM8_CH3        51U   /*!< DMAMUX TIM8 CH3 request    */\n#define LL_DMAMUX_REQ_TIM8_CH4        52U   /*!< DMAMUX TIM8 CH4 request    */\n#define LL_DMAMUX_REQ_TIM8_UP         53U   /*!< DMAMUX TIM8 UP request     */\n#define LL_DMAMUX_REQ_TIM8_TRIG       54U   /*!< DMAMUX TIM8 TRIG request   */\n#define LL_DMAMUX_REQ_TIM8_COM        55U   /*!< DMAMUX TIM8 COM request    */\n#define LL_DMAMUX_REQ_TIM2_CH1        56U   /*!< DMAMUX TIM2 CH1 request    */\n#define LL_DMAMUX_REQ_TIM2_CH2        57U   /*!< DMAMUX TIM2 CH2 request    */\n#define LL_DMAMUX_REQ_TIM2_CH3        58U   /*!< DMAMUX TIM2 CH3 request    */\n#define LL_DMAMUX_REQ_TIM2_CH4        59U   /*!< DMAMUX TIM2 CH4 request    */\n#define LL_DMAMUX_REQ_TIM2_UP         60U   /*!< DMAMUX TIM2 UP request     */\n#define LL_DMAMUX_REQ_TIM3_CH1        61U   /*!< DMAMUX TIM3 CH1 request    */\n#define LL_DMAMUX_REQ_TIM3_CH2        62U   /*!< DMAMUX TIM3 CH2 request    */\n#define LL_DMAMUX_REQ_TIM3_CH3        63U   /*!< DMAMUX TIM3 CH3 request    */\n#define LL_DMAMUX_REQ_TIM3_CH4        64U   /*!< DMAMUX TIM3 CH4 request    */\n#define LL_DMAMUX_REQ_TIM3_UP         65U   /*!< DMAMUX TIM3 UP request     */\n#define LL_DMAMUX_REQ_TIM3_TRIG       66U   /*!< DMAMUX TIM3 TRIG request   */\n#define LL_DMAMUX_REQ_TIM4_CH1        67U   /*!< DMAMUX TIM4 CH1 request    */\n#define LL_DMAMUX_REQ_TIM4_CH2        68U   /*!< DMAMUX TIM4 CH2 request    */\n#define LL_DMAMUX_REQ_TIM4_CH3        69U   /*!< DMAMUX TIM4 CH3 request    */\n#define LL_DMAMUX_REQ_TIM4_CH4        70U   /*!< DMAMUX TIM4 CH4 request    */\n#define LL_DMAMUX_REQ_TIM4_UP         71U   /*!< DMAMUX TIM4 UP request     */\n#define LL_DMAMUX_REQ_TIM5_CH1        72U   /*!< DMAMUX TIM5 CH1 request    */\n#define LL_DMAMUX_REQ_TIM5_CH2        73U   /*!< DMAMUX TIM5 CH2 request    */\n#define LL_DMAMUX_REQ_TIM5_CH3        74U   /*!< DMAMUX TIM5 CH3 request    */\n#define LL_DMAMUX_REQ_TIM5_CH4        75U   /*!< DMAMUX TIM5 CH4 request    */\n#define LL_DMAMUX_REQ_TIM5_UP         76U   /*!< DMAMUX TIM5 UP request     */\n#define LL_DMAMUX_REQ_TIM5_TRIG       77U   /*!< DMAMUX TIM5 TRIG request   */\n#define LL_DMAMUX_REQ_TIM15_CH1       78U   /*!< DMAMUX TIM15 CH1 request   */\n#define LL_DMAMUX_REQ_TIM15_UP        79U   /*!< DMAMUX TIM15 UP request    */\n#define LL_DMAMUX_REQ_TIM15_TRIG      80U   /*!< DMAMUX TIM15 TRIG request  */\n#define LL_DMAMUX_REQ_TIM15_COM       81U   /*!< DMAMUX TIM15 COM request   */\n#define LL_DMAMUX_REQ_TIM16_CH1       82U   /*!< DMAMUX TIM16 CH1 request   */\n#define LL_DMAMUX_REQ_TIM16_UP        83U   /*!< DMAMUX TIM16 UP request    */\n#define LL_DMAMUX_REQ_TIM17_CH1       84U   /*!< DMAMUX TIM17 CH1 request   */\n#define LL_DMAMUX_REQ_TIM17_UP        85U   /*!< DMAMUX TIM17 UP request    */\n#define LL_DMAMUX_REQ_DFSDM1_FLT0     86U   /*!< DMAMUX DFSDM1_FLT0 request */\n#define LL_DMAMUX_REQ_DFSDM1_FLT1     87U   /*!< DMAMUX DFSDM1_FLT1 request */\n#define LL_DMAMUX_REQ_DFSDM1_FLT2     88U   /*!< DMAMUX DFSDM1_FLT2 request */\n#define LL_DMAMUX_REQ_DFSDM1_FLT3     89U   /*!< DMAMUX DFSDM1_FLT3 request */\n#define LL_DMAMUX_REQ_DCMI            90U   /*!< DMAMUX DCMI request        */\n#define LL_DMAMUX_REQ_AES_IN          91U   /*!< DMAMUX AES_IN request      */\n#define LL_DMAMUX_REQ_AES_OUT         92U   /*!< DMAMUX AES_OUT request     */\n#define LL_DMAMUX_REQ_HASH_IN         93U   /*!< DMAMUX HASH_IN request     */\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel\n  * @{\n  */\n#define LL_DMAMUX_CHANNEL_0               0x00000000U               /*!< DMAMUX Channel 0 connected to DMA1 Channel 1  */\n#define LL_DMAMUX_CHANNEL_1               0x00000001U               /*!< DMAMUX Channel 1 connected to DMA1 Channel 2  */\n#define LL_DMAMUX_CHANNEL_2               0x00000002U               /*!< DMAMUX Channel 2 connected to DMA1 Channel 3  */\n#define LL_DMAMUX_CHANNEL_3               0x00000003U               /*!< DMAMUX Channel 3 connected to DMA1 Channel 4  */\n#define LL_DMAMUX_CHANNEL_4               0x00000004U               /*!< DMAMUX Channel 4 connected to DMA1 Channel 5  */\n#define LL_DMAMUX_CHANNEL_5               0x00000005U               /*!< DMAMUX Channel 5 connected to DMA1 Channel 6  */\n#define LL_DMAMUX_CHANNEL_6               0x00000006U               /*!< DMAMUX Channel 6 connected to DMA1 Channel 7  */\n#define LL_DMAMUX_CHANNEL_7               0x00000007U               /*!< DMAMUX Channel 7 connected to DMA2 Channel 1  */\n#define LL_DMAMUX_CHANNEL_8               0x00000008U               /*!< DMAMUX Channel 8 connected to DMA2 Channel 2  */\n#define LL_DMAMUX_CHANNEL_9               0x00000009U               /*!< DMAMUX Channel 9 connected to DMA2 Channel 3  */\n#define LL_DMAMUX_CHANNEL_10              0x0000000AU               /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */\n#define LL_DMAMUX_CHANNEL_11              0x0000000BU               /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */\n#define LL_DMAMUX_CHANNEL_12              0x0000000CU               /*!< DMAMUX Channel 12 connected to DMA2 Channel 6 */\n#define LL_DMAMUX_CHANNEL_13              0x0000000DU               /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity\n  * @{\n  */\n#define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked   */\n#define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge */\n#define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge */\n#define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event\n  * @{\n  */\n#define LL_DMAMUX_SYNC_EXTI_LINE0          0U   /*!< Synchronization signal from EXTI Line0  */\n#define LL_DMAMUX_SYNC_EXTI_LINE1          1U   /*!< Synchronization signal from EXTI Line1  */\n#define LL_DMAMUX_SYNC_EXTI_LINE2          2U   /*!< Synchronization signal from EXTI Line2  */\n#define LL_DMAMUX_SYNC_EXTI_LINE3          3U   /*!< Synchronization signal from EXTI Line3  */\n#define LL_DMAMUX_SYNC_EXTI_LINE4          4U   /*!< Synchronization signal from EXTI Line4  */\n#define LL_DMAMUX_SYNC_EXTI_LINE5          5U   /*!< Synchronization signal from EXTI Line5  */\n#define LL_DMAMUX_SYNC_EXTI_LINE6          6U   /*!< Synchronization signal from EXTI Line6  */\n#define LL_DMAMUX_SYNC_EXTI_LINE7          7U   /*!< Synchronization signal from EXTI Line7  */\n#define LL_DMAMUX_SYNC_EXTI_LINE8          8U   /*!< Synchronization signal from EXTI Line8  */\n#define LL_DMAMUX_SYNC_EXTI_LINE9          9U   /*!< Synchronization signal from EXTI Line9  */\n#define LL_DMAMUX_SYNC_EXTI_LINE10        10U   /*!< Synchronization signal from EXTI Line10 */\n#define LL_DMAMUX_SYNC_EXTI_LINE11        11U   /*!< Synchronization signal from EXTI Line11 */\n#define LL_DMAMUX_SYNC_EXTI_LINE12        12U   /*!< Synchronization signal from EXTI Line12 */\n#define LL_DMAMUX_SYNC_EXTI_LINE13        13U   /*!< Synchronization signal from EXTI Line13 */\n#define LL_DMAMUX_SYNC_EXTI_LINE14        14U   /*!< Synchronization signal from EXTI Line14 */\n#define LL_DMAMUX_SYNC_EXTI_LINE15        15U   /*!< Synchronization signal from EXTI Line15 */\n#define LL_DMAMUX_SYNC_DMAMUX_CH0         16U   /*!< Synchronization signal from DMAMUX channel0 Event */\n#define LL_DMAMUX_SYNC_DMAMUX_CH1         17U   /*!< Synchronization signal from DMAMUX channel1 Event */\n#define LL_DMAMUX_SYNC_DMAMUX_CH2         18U   /*!< Synchronization signal from DMAMUX channel2 Event */\n#define LL_DMAMUX_SYNC_DMAMUX_CH3         19U   /*!< Synchronization signal from DMAMUX channel3 Event */\n#define LL_DMAMUX_SYNC_LPTIM1_OUT         20U   /*!< Synchronization signal from LPTIM1 Ouput */\n#define LL_DMAMUX_SYNC_LPTIM2_OUT         21U   /*!< Synchronization signal from LPTIM2 Ouput */\n#define LL_DMAMUX_SYNC_DSI_TE             22U   /*!< Synchronization signal from DSI Tearing Effect */\n#define LL_DMAMUX_SYNC_DSI_REFRESH_END    23U   /*!< Synchronization signal from DSI End of Refresh */\n#define LL_DMAMUX_SYNC_DMA2D_TX_END       24U   /*!< Synchronization signal from DMA2D End of Transfer */\n#define LL_DMAMUX_SYNC_LTDC_LINE_IT       25U   /*!< Synchronization signal from LTDC Line Interrupt   */\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel\n  * @{\n  */\n#define LL_DMAMUX_REQ_GEN_0           0x00000000U\n#define LL_DMAMUX_REQ_GEN_1           0x00000001U\n#define LL_DMAMUX_REQ_GEN_2           0x00000002U\n#define LL_DMAMUX_REQ_GEN_3           0x00000003U\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity\n  * @{\n  */\n#define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation */\n#define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge */\n#define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge */\n#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation\n  * @{\n  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE0       0U   /*!< Request signal generation from EXTI Line0  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE1       1U   /*!< Request signal generation from EXTI Line1  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE2       2U   /*!< Request signal generation from EXTI Line2  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE3       3U   /*!< Request signal generation from EXTI Line3  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE4       4U   /*!< Request signal generation from EXTI Line4  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE5       5U   /*!< Request signal generation from EXTI Line5  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE6       6U   /*!< Request signal generation from EXTI Line6  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE7       7U   /*!< Request signal generation from EXTI Line7  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE8       8U   /*!< Request signal generation from EXTI Line8  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE9       9U   /*!< Request signal generation from EXTI Line9  */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE10     10U   /*!< Request signal generation from EXTI Line10 */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE11     11U   /*!< Request signal generation from EXTI Line11 */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE12     12U   /*!< Request signal generation from EXTI Line12 */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE13     13U   /*!< Request signal generation from EXTI Line13 */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE14     14U   /*!< Request signal generation from EXTI Line14 */\n#define LL_DMAMUX_REQ_GEN_EXTI_LINE15     15U   /*!< Request signal generation from EXTI Line15 */\n#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0      16U   /*!< Request signal generation from DMAMUX channel0 Event */\n#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1      17U   /*!< Request signal generation from DMAMUX channel1 Event */\n#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2      18U   /*!< Request signal generation from DMAMUX channel2 Event */\n#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3      19U   /*!< Request signal generation from DMAMUX channel3 Event */\n#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT      20U   /*!< Request signal generation from LPTIM1 Ouput */\n#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT      21U   /*!< Request signal generation from LPTIM2 Ouput */\n#define LL_DMAMUX_REQ_GEN_DSI_TE          22U   /*!< Request signal generation from DSI Tearing Effect */\n#define LL_DMAMUX_REQ_GEN_DSI_REFRESH_END 23U   /*!< Request signal generation from DSI End of Refresh */\n#define LL_DMAMUX_REQ_GEN_DMA2D_TX_END    24U   /*!< Request signal generation from DMA2D End of Transfer */\n#define LL_DMAMUX_REQ_GEN_LTDC_LINE_IT    25U   /*!< Request signal generation from LTDC Line Interrupt   */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros\n  * @{\n  */\n\n/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros\n  * @{\n  */\n/**\n  * @brief  Write a value in DMAMUX register\n  * @param  __INSTANCE__ DMAMUX Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in DMAMUX register\n  * @param  __INSTANCE__ DMAMUX Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions\n * @{\n */\n\n/** @defgroup DMAMUX_LL_EF_Configuration Configuration\n  * @{\n  */\n/**\n  * @brief  Set DMAMUX request ID for DMAMUX Channel x.\n  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.\n  *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.\n  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @param  Request This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM\n  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0\n  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1\n  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2\n  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3\n  *         @arg @ref LL_DMAMUX_REQ_ADC1\n  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1\n  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP\n  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX\n  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX\n  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX\n  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX\n  *         @arg @ref LL_DMAMUX_REQ_SPI3_RX\n  *         @arg @ref LL_DMAMUX_REQ_SPI3_TX\n  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX\n  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX\n  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX\n  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX\n  *         @arg @ref LL_DMAMUX_REQ_I2C3_RX\n  *         @arg @ref LL_DMAMUX_REQ_I2C3_TX\n  *         @arg @ref LL_DMAMUX_REQ_I2C4_RX\n  *         @arg @ref LL_DMAMUX_REQ_I2C4_TX\n  *         @arg @ref LL_DMAMUX_REQ_USART1_RX\n  *         @arg @ref LL_DMAMUX_REQ_USART1_TX\n  *         @arg @ref LL_DMAMUX_REQ_USART2_RX\n  *         @arg @ref LL_DMAMUX_REQ_USART2_TX\n  *         @arg @ref LL_DMAMUX_REQ_USART3_RX\n  *         @arg @ref LL_DMAMUX_REQ_USART3_TX\n  *         @arg @ref LL_DMAMUX_REQ_UART4_RX\n  *         @arg @ref LL_DMAMUX_REQ_UART4_TX\n  *         @arg @ref LL_DMAMUX_REQ_UART5_RX\n  *         @arg @ref LL_DMAMUX_REQ_UART5_TX\n  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX\n  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX\n  *         @arg @ref LL_DMAMUX_REQ_SAI1_A\n  *         @arg @ref LL_DMAMUX_REQ_SAI1_B\n  *         @arg @ref LL_DMAMUX_REQ_SAI2_A\n  *         @arg @ref LL_DMAMUX_REQ_SAI2_B\n  *         @arg @ref LL_DMAMUX_REQ_OSPI1\n  *         @arg @ref LL_DMAMUX_REQ_OSPI2\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_COM\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_COM\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM15_COM\n  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP\n  *         @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0\n  *         @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1\n  *         @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2\n  *         @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3\n  *         @arg @ref LL_DMAMUX_REQ_DCMI\n  *         @arg @ref LL_DMAMUX_REQ_AES_IN\n  *         @arg @ref LL_DMAMUX_REQ_AES_OUT\n  *         @arg @ref LL_DMAMUX_REQ_HASH_IN\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)\n{\n  MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);\n}\n\n/**\n  * @brief  Get DMAMUX request ID for DMAMUX Channel x.\n  * @note   DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.\n  *         DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.\n  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_MEM2MEM\n  *         @arg @ref LL_DMAMUX_REQ_GENERATOR0\n  *         @arg @ref LL_DMAMUX_REQ_GENERATOR1\n  *         @arg @ref LL_DMAMUX_REQ_GENERATOR2\n  *         @arg @ref LL_DMAMUX_REQ_GENERATOR3\n  *         @arg @ref LL_DMAMUX_REQ_ADC1\n  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH1\n  *         @arg @ref LL_DMAMUX_REQ_DAC1_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM6_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM7_UP\n  *         @arg @ref LL_DMAMUX_REQ_SPI1_RX\n  *         @arg @ref LL_DMAMUX_REQ_SPI1_TX\n  *         @arg @ref LL_DMAMUX_REQ_SPI2_RX\n  *         @arg @ref LL_DMAMUX_REQ_SPI2_TX\n  *         @arg @ref LL_DMAMUX_REQ_SPI3_RX\n  *         @arg @ref LL_DMAMUX_REQ_SPI3_TX\n  *         @arg @ref LL_DMAMUX_REQ_I2C1_RX\n  *         @arg @ref LL_DMAMUX_REQ_I2C1_TX\n  *         @arg @ref LL_DMAMUX_REQ_I2C2_RX\n  *         @arg @ref LL_DMAMUX_REQ_I2C2_TX\n  *         @arg @ref LL_DMAMUX_REQ_I2C3_RX\n  *         @arg @ref LL_DMAMUX_REQ_I2C3_TX\n  *         @arg @ref LL_DMAMUX_REQ_I2C4_RX\n  *         @arg @ref LL_DMAMUX_REQ_I2C4_TX\n  *         @arg @ref LL_DMAMUX_REQ_USART1_RX\n  *         @arg @ref LL_DMAMUX_REQ_USART1_TX\n  *         @arg @ref LL_DMAMUX_REQ_USART2_RX\n  *         @arg @ref LL_DMAMUX_REQ_USART2_TX\n  *         @arg @ref LL_DMAMUX_REQ_USART3_RX\n  *         @arg @ref LL_DMAMUX_REQ_USART3_TX\n  *         @arg @ref LL_DMAMUX_REQ_UART4_RX\n  *         @arg @ref LL_DMAMUX_REQ_UART4_TX\n  *         @arg @ref LL_DMAMUX_REQ_UART5_RX\n  *         @arg @ref LL_DMAMUX_REQ_UART5_TX\n  *         @arg @ref LL_DMAMUX_REQ_LPUART1_RX\n  *         @arg @ref LL_DMAMUX_REQ_LPUART1_TX\n  *         @arg @ref LL_DMAMUX_REQ_SAI1_A\n  *         @arg @ref LL_DMAMUX_REQ_SAI1_B\n  *         @arg @ref LL_DMAMUX_REQ_SAI2_A\n  *         @arg @ref LL_DMAMUX_REQ_SAI2_B\n  *         @arg @ref LL_DMAMUX_REQ_OSPI1\n  *         @arg @ref LL_DMAMUX_REQ_OSPI2\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM1_COM\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM8_COM\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM2_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM3_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM4_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH2\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH3\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_CH4\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM5_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM15_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM15_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM15_TRIG\n  *         @arg @ref LL_DMAMUX_REQ_TIM15_COM\n  *         @arg @ref LL_DMAMUX_REQ_TIM16_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM16_UP\n  *         @arg @ref LL_DMAMUX_REQ_TIM17_CH1\n  *         @arg @ref LL_DMAMUX_REQ_TIM17_UP\n  *         @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT0\n  *         @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT1\n  *         @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT2\n  *         @arg @ref LL_DMAMUX_REQ_DFSDM1_FLT3\n  *         @arg @ref LL_DMAMUX_REQ_DCMI\n  *         @arg @ref LL_DMAMUX_REQ_AES_IN\n  *         @arg @ref LL_DMAMUX_REQ_AES_OUT\n  *         @arg @ref LL_DMAMUX_REQ_HASH_IN\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel-1)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));\n}\n\n/**\n  * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.\n  * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)\n{\n  MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ, RequestNb - 1);\n}\n\n/**\n  * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.\n  * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval Between Min_Data = 1 and Max_Data = 32\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_NBREQ) + 1);\n}\n\n/**\n  * @brief  Set the polarity of the signal on which the DMA request is synchronized.\n  * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @param  Polarity This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT\n  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING\n  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING\n  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)\n{\n  MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL, Polarity);\n}\n\n/**\n  * @brief  Get the polarity of the signal on which the DMA request is synchronized.\n  * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT\n  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING\n  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING\n  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SPOL));\n}\n\n/**\n  * @brief  Enable the Event Generation on DMAMUX channel x.\n  * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE);\n}\n\n/**\n  * @brief  Disable the Event Generation on DMAMUX channel x.\n  * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE);\n}\n\n/**\n  * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.\n  * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE));\n}\n\n/**\n  * @brief  Enable the synchronization mode.\n  * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE);\n}\n\n/**\n  * @brief  Disable the synchronization mode.\n  * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE);\n}\n\n/**\n  * @brief  Check if the synchronization mode is enabled or disabled.\n  * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE));\n}\n\n/**\n  * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.\n  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @param  SyncID This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15\n  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0\n  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1\n  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2\n  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3\n  *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT\n  *         @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT\n  *         @arg @ref LL_DMAMUX_SYNC_DSI_TE\n  *         @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END\n  *         @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END\n  *         @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)\n{\n  MODIFY_REG(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);\n}\n\n/**\n  * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.\n  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14\n  *         @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15\n  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0\n  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1\n  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2\n  *         @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3\n  *         @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT\n  *         @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT\n  *         @arg @ref LL_DMAMUX_SYNC_DSI_TE\n  *         @arg @ref LL_DMAMUX_SYNC_DSI_REFRESH_END\n  *         @arg @ref LL_DMAMUX_SYNC_DMA2D_TX_END\n  *         @arg @ref LL_DMAMUX_SYNC_LTDC_LINE_IT\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SYNC_ID));\n}\n\n/**\n  * @brief  Enable the Request Generator.\n  * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);\n}\n\n/**\n  * @brief  Disable the Request Generator.\n  * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);\n}\n\n/**\n  * @brief  Check if the Request Generator is enabled or disabled.\n  * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE));\n}\n\n/**\n  * @brief  Set the polarity of the signal on which the DMA request is generated.\n  * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @param  Polarity This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT\n  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING\n  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING\n  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)\n{\n  MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);\n}\n\n/**\n  * @brief  Get the polarity of the signal on which the DMA request is generated.\n  * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT\n  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING\n  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING\n  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));\n}\n\n/**\n  * @brief  Set the number of DMA request that will be autorized after a generation event.\n  * @note   This field can only be written when Generator is disabled.\n  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)\n{\n  MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1) << DMAMUX_RGxCR_GNBREQ_Pos);\n}\n\n/**\n  * @brief  Get the number of DMA request that will be autorized after a generation event.\n  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval Between Min_Data = 1 and Max_Data = 32\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1);\n}\n\n/**\n  * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.\n  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @param  RequestSignalID This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3\n  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT\n  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END\n  *         @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)\n{\n  MODIFY_REG(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);\n}\n\n/**\n  * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.\n  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14\n  *         @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3\n  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT\n  *         @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DSI_TE\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DSI_REFRESH_END\n  *         @arg @ref LL_DMAMUX_REQ_GEN_DMA2D_TX_END\n  *         @arg @ref LL_DMAMUX_REQ_GEN_LTDC_LINE_IT\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 0.\n  * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 1.\n  * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 2.\n  * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 3.\n  * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 4.\n  * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 5.\n  * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 6.\n  * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 7.\n  * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 8.\n  * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 9.\n  * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 10.\n  * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 11.\n  * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 12.\n  * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12));\n}\n\n/**\n  * @brief  Get Synchronization Event Overrun Flag Channel 13.\n  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13));\n}\n\n/**\n  * @brief  Get Request Generator 0 Trigger Event Overrun Flag.\n  * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0));\n}\n\n/**\n  * @brief  Get Request Generator 1 Trigger Event Overrun Flag.\n  * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1));\n}\n\n/**\n  * @brief  Get Request Generator 2 Trigger Event Overrun Flag.\n  * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2));\n}\n\n/**\n  * @brief  Get Request Generator 3 Trigger Event Overrun Flag.\n  * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  return (READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3));\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 0.\n  * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 1.\n  * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 2.\n  * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 3.\n  * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 4.\n  * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 5.\n  * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 6.\n  * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 7.\n  * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 8.\n  * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 9.\n  * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 10.\n  * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 11.\n  * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 12.\n  * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);\n}\n\n/**\n  * @brief  Clear Synchronization Event Overrun Flag Channel 13.\n  * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);\n}\n\n/**\n  * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.\n  * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);\n}\n\n/**\n  * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.\n  * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);\n}\n\n/**\n  * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.\n  * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);\n}\n\n/**\n  * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.\n  * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3\n  * @param  DMAMUXx DMAMUXx DMAMUXx Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)\n{\n  SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.\n  * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  SET_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE);\n}\n\n/**\n  * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.\n  * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  CLEAR_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE);\n}\n\n/**\n  * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.\n  * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_CHANNEL_0\n  *         @arg @ref LL_DMAMUX_CHANNEL_1\n  *         @arg @ref LL_DMAMUX_CHANNEL_2\n  *         @arg @ref LL_DMAMUX_CHANNEL_3\n  *         @arg @ref LL_DMAMUX_CHANNEL_4\n  *         @arg @ref LL_DMAMUX_CHANNEL_5\n  *         @arg @ref LL_DMAMUX_CHANNEL_6\n  *         @arg @ref LL_DMAMUX_CHANNEL_7\n  *         @arg @ref LL_DMAMUX_CHANNEL_8\n  *         @arg @ref LL_DMAMUX_CHANNEL_9\n  *         @arg @ref LL_DMAMUX_CHANNEL_10\n  *         @arg @ref LL_DMAMUX_CHANNEL_11\n  *         @arg @ref LL_DMAMUX_CHANNEL_12\n  *         @arg @ref LL_DMAMUX_CHANNEL_13\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)\n{\n  return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUXx + (DMAMUX_CCR_SIZE*(Channel)))))->CCR, DMAMUX_CxCR_SOIE));\n}\n\n/**\n  * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.\n  * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  SET_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE);\n}\n\n/**\n  * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.\n  * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval None\n  */\n__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE);\n}\n\n/**\n  * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.\n  * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO\n  * @param  DMAMUXx DMAMUXx Instance\n  * @param  RequestGenChannel This parameter can be one of the following values:\n  *         @arg @ref LL_DMAMUX_REQ_GEN_0\n  *         @arg @ref LL_DMAMUX_REQ_GEN_1\n  *         @arg @ref LL_DMAMUX_REQ_GEN_2\n  *         @arg @ref LL_DMAMUX_REQ_GEN_3\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)\n{\n  return (READ_BIT(((DMAMUX_RequestGen_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE*(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE));\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* DMAMUX1 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_DMAMUX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_exti.h\n  * @author  MCD Application Team\n  * @brief   Header file of EXTI LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_EXTI_H\n#define __STM32L4xx_LL_EXTI_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (EXTI)\n\n/** @defgroup EXTI_LL EXTI\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private Macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure\n  * @{\n  */\ntypedef struct\n{\n\n  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31\n                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */\n\n  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63\n                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */\n\n  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.\n                                     This parameter can be set either to ENABLE or DISABLE */\n\n  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.\n                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */\n\n  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.\n                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */\n} LL_EXTI_InitTypeDef;\n\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants\n  * @{\n  */\n\n/** @defgroup EXTI_LL_EC_LINE LINE\n  * @{\n  */\n#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */\n#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */\n#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */\n#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */\n#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */\n#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */\n#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */\n#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */\n#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */\n#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */\n#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */\n#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */\n#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */\n#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */\n#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */\n#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */\n#if defined(EXTI_IMR1_IM16)\n#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */\n#endif\n#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */\n#if defined(EXTI_IMR1_IM18)\n#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */\n#endif\n#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */\n#if defined(EXTI_IMR1_IM20)\n#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */\n#endif\n#if defined(EXTI_IMR1_IM21)\n#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */\n#endif\n#if defined(EXTI_IMR1_IM22)\n#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */\n#endif\n#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */\n#if defined(EXTI_IMR1_IM24)\n#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */\n#endif\n#if defined(EXTI_IMR1_IM25)\n#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */\n#endif\n#if defined(EXTI_IMR1_IM26)\n#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */\n#endif\n#if defined(EXTI_IMR1_IM27)\n#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */\n#endif\n#if defined(EXTI_IMR1_IM28)\n#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */\n#endif\n#if defined(EXTI_IMR1_IM29)\n#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */\n#endif\n#if defined(EXTI_IMR1_IM30)\n#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */\n#endif\n#if defined(EXTI_IMR1_IM31)\n#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */\n#endif\n#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/\n\n#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */\n#if defined(EXTI_IMR2_IM33)\n#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */\n#endif\n#if defined(EXTI_IMR2_IM34)\n#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */\n#endif\n#if defined(EXTI_IMR2_IM35)\n#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */\n#endif\n#if defined(EXTI_IMR2_IM36)\n#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */\n#endif\n#if defined(EXTI_IMR2_IM37)\n#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */\n#endif\n#if defined(EXTI_IMR2_IM38)\n#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */\n#endif\n#if defined(EXTI_IMR2_IM39)\n#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */\n#endif\n#if defined(EXTI_IMR2_IM40)\n#define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */\n#endif\n#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/\n\n\n#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */\n\n#if defined(USE_FULL_LL_DRIVER)\n#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/**\n  * @}\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/** @defgroup EXTI_LL_EC_MODE Mode\n  * @{\n  */\n#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */\n#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */\n#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger\n  * @{\n  */\n#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */\n#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */\n#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */\n#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */\n\n/**\n  * @}\n  */\n\n\n#endif /*USE_FULL_LL_DRIVER*/\n\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros\n  * @{\n  */\n\n/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in EXTI register\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in EXTI register\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)\n/**\n  * @}\n  */\n\n\n/**\n  * @}\n  */\n\n\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions\n * @{\n */\n/** @defgroup EXTI_LL_EF_IT_Management IT_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31\n  * @note The reset value for the direct or internal lines (see RM)\n  *       is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23\n  *         @arg @ref LL_EXTI_LINE_24\n  *         @arg @ref LL_EXTI_LINE_25\n  *         @arg @ref LL_EXTI_LINE_26\n  *         @arg @ref LL_EXTI_LINE_27\n  *         @arg @ref LL_EXTI_LINE_28\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->IMR1, ExtiLine);\n}\n/**\n  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63\n  * @note The reset value for the direct lines (lines from 32 to 34, line\n  *       39) is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_32\n  *         @arg @ref LL_EXTI_LINE_33\n  *         @arg @ref LL_EXTI_LINE_34(*)\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  *         @arg @ref LL_EXTI_LINE_39(*)\n  *         @arg @ref LL_EXTI_LINE_40(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_32_63\n  * @note   (*): Available in some devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->IMR2, ExtiLine);\n}\n\n/**\n  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31\n  * @note The reset value for the direct or internal lines (see RM)\n  *       is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23\n  *         @arg @ref LL_EXTI_LINE_24\n  *         @arg @ref LL_EXTI_LINE_25\n  *         @arg @ref LL_EXTI_LINE_26\n  *         @arg @ref LL_EXTI_LINE_27\n  *         @arg @ref LL_EXTI_LINE_28\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->IMR1, ExtiLine);\n}\n\n/**\n  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63\n  * @note The reset value for the direct lines (lines from 32 to 34, line\n  *       39) is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_32\n  *         @arg @ref LL_EXTI_LINE_33\n  *         @arg @ref LL_EXTI_LINE_34(*)\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  *         @arg @ref LL_EXTI_LINE_39(*)\n  *         @arg @ref LL_EXTI_LINE_40(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_32_63\n  * @note   (*): Available in some devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->IMR2, ExtiLine);\n}\n\n/**\n  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31\n  * @note The reset value for the direct or internal lines (see RM)\n  *       is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23\n  *         @arg @ref LL_EXTI_LINE_24\n  *         @arg @ref LL_EXTI_LINE_25\n  *         @arg @ref LL_EXTI_LINE_26\n  *         @arg @ref LL_EXTI_LINE_27\n  *         @arg @ref LL_EXTI_LINE_28\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63\n  * @note The reset value for the direct lines (lines from 32 to 34, line\n  *       39) is set to 1 in order to enable the interrupt by default.\n  *       Bits are set automatically at Power on.\n  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_32\n  *         @arg @ref LL_EXTI_LINE_33\n  *         @arg @ref LL_EXTI_LINE_34(*)\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  *         @arg @ref LL_EXTI_LINE_39(*)\n  *         @arg @ref LL_EXTI_LINE_40(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_32_63\n  * @note   (*): Available in some devices\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Event_Management Event_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31\n  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23\n  *         @arg @ref LL_EXTI_LINE_24\n  *         @arg @ref LL_EXTI_LINE_25\n  *         @arg @ref LL_EXTI_LINE_26\n  *         @arg @ref LL_EXTI_LINE_27\n  *         @arg @ref LL_EXTI_LINE_28\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->EMR1, ExtiLine);\n\n}\n\n/**\n  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63\n  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_32\n  *         @arg @ref LL_EXTI_LINE_33\n  *         @arg @ref LL_EXTI_LINE_34(*)\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  *         @arg @ref LL_EXTI_LINE_39(*)\n  *         @arg @ref LL_EXTI_LINE_40(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_32_63\n  * @note   (*): Available in some devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->EMR2, ExtiLine);\n}\n\n/**\n  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31\n  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23\n  *         @arg @ref LL_EXTI_LINE_24\n  *         @arg @ref LL_EXTI_LINE_25\n  *         @arg @ref LL_EXTI_LINE_26\n  *         @arg @ref LL_EXTI_LINE_27\n  *         @arg @ref LL_EXTI_LINE_28\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->EMR1, ExtiLine);\n}\n\n/**\n  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63\n  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_32\n  *         @arg @ref LL_EXTI_LINE_33\n  *         @arg @ref LL_EXTI_LINE_34(*)\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  *         @arg @ref LL_EXTI_LINE_39(*)\n  *         @arg @ref LL_EXTI_LINE_40(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_32_63\n  * @note   (*): Available in some devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->EMR2, ExtiLine);\n}\n\n/**\n  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31\n  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31\n  * @param  ExtiLine This parameter can be one of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_17\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_23\n  *         @arg @ref LL_EXTI_LINE_24\n  *         @arg @ref LL_EXTI_LINE_25\n  *         @arg @ref LL_EXTI_LINE_26\n  *         @arg @ref LL_EXTI_LINE_27\n  *         @arg @ref LL_EXTI_LINE_28\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  *         @arg @ref LL_EXTI_LINE_ALL_0_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine));\n\n}\n\n/**\n  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63\n  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_32\n  *         @arg @ref LL_EXTI_LINE_33\n  *         @arg @ref LL_EXTI_LINE_34(*)\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  *         @arg @ref LL_EXTI_LINE_39(*)\n  *         @arg @ref LL_EXTI_LINE_40(*)\n  *         @arg @ref LL_EXTI_LINE_ALL_32_63\n  * @note   (*): Available in some devices\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a rising edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_RTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->RTSR1, ExtiLine);\n\n}\n\n/**\n  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a rising edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_RTSR register, the\n  *       pending bit is not set.Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->RTSR2, ExtiLine);\n}\n\n/**\n  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a rising edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_RTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->RTSR1, ExtiLine);\n\n}\n\n/**\n  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a rising edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_RTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->RTSR2, ExtiLine);\n}\n\n/**\n  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31\n  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63\n  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a falling edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_FTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->FTSR1, ExtiLine);\n}\n\n/**\n  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a Falling edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_FTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for\n  *       the same interrupt line. In this case, both generate a trigger\n  *       condition.\n  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->FTSR2, ExtiLine);\n}\n\n/**\n  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a Falling edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_FTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for the same interrupt line.\n  *       In this case, both generate a trigger condition.\n  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->FTSR1, ExtiLine);\n}\n\n/**\n  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63\n  * @note The configurable wakeup lines are edge-triggered. No glitch must be\n  *       generated on these lines. If a Falling edge on a configurable interrupt\n  *       line occurs during a write operation in the EXTI_FTSR register, the\n  *       pending bit is not set.\n  *       Rising and falling edge triggers can be set for the same interrupt line.\n  *       In this case, both generate a trigger condition.\n  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)\n{\n  CLEAR_BIT(EXTI->FTSR2, ExtiLine);\n}\n\n/**\n  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31\n  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63\n  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management\n  * @{\n  */\n\n/**\n  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31\n  * @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to\n  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1\n  *       resulting in an interrupt request generation.\n  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1\n  *       register (by writing a 1 into the bit)\n  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->SWIER1, ExtiLine);\n}\n\n/**\n  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63\n  * @note If the interrupt is enabled on this line inthe EXTI_IMR2, writing a 1 to\n  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2\n  *       resulting in an interrupt request generation.\n  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2\n  *       register (by writing a 1 into the bit)\n  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)\n{\n  SET_BIT(EXTI->SWIER2, ExtiLine);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management\n  * @{\n  */\n\n/**\n  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)\n{\n  return (READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine));\n}\n\n/**\n  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval @note This bit is set when the selected edge event arrives on the interrupt\n  */\n__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)\n{\n  return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));\n}\n\n\n/**\n  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval @note This bit is set when the selected edge event arrives on the interrupt\n  */\n__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)\n{\n  return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));\n}\n\n/**\n  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_0\n  *         @arg @ref LL_EXTI_LINE_1\n  *         @arg @ref LL_EXTI_LINE_2\n  *         @arg @ref LL_EXTI_LINE_3\n  *         @arg @ref LL_EXTI_LINE_4\n  *         @arg @ref LL_EXTI_LINE_5\n  *         @arg @ref LL_EXTI_LINE_6\n  *         @arg @ref LL_EXTI_LINE_7\n  *         @arg @ref LL_EXTI_LINE_8\n  *         @arg @ref LL_EXTI_LINE_9\n  *         @arg @ref LL_EXTI_LINE_10\n  *         @arg @ref LL_EXTI_LINE_11\n  *         @arg @ref LL_EXTI_LINE_12\n  *         @arg @ref LL_EXTI_LINE_13\n  *         @arg @ref LL_EXTI_LINE_14\n  *         @arg @ref LL_EXTI_LINE_15\n  *         @arg @ref LL_EXTI_LINE_16\n  *         @arg @ref LL_EXTI_LINE_18\n  *         @arg @ref LL_EXTI_LINE_19\n  *         @arg @ref LL_EXTI_LINE_20\n  *         @arg @ref LL_EXTI_LINE_21\n  *         @arg @ref LL_EXTI_LINE_22\n  *         @arg @ref LL_EXTI_LINE_29\n  *         @arg @ref LL_EXTI_LINE_30\n  *         @arg @ref LL_EXTI_LINE_31\n  * @note   Please check each device line mapping for EXTI Line availability\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)\n{\n  WRITE_REG(EXTI->PR1, ExtiLine);\n}\n\n/**\n  * @brief  Clear ExtLine Flags for  Lines in range 32 to 63\n  * @note This bit is set when the selected edge event arrives on the interrupt\n  *       line. This bit is cleared by writing a 1 to the bit.\n  * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63\n  * @param  ExtiLine This parameter can be a combination of the following values:\n  *         @arg @ref LL_EXTI_LINE_35\n  *         @arg @ref LL_EXTI_LINE_36\n  *         @arg @ref LL_EXTI_LINE_37\n  *         @arg @ref LL_EXTI_LINE_38\n  * @retval None\n  */\n__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)\n{\n  WRITE_REG(EXTI->PR2, ExtiLine);\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\nuint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);\nuint32_t LL_EXTI_DeInit(void);\nvoid LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);\n\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* EXTI */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_EXTI_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_gpio.h\n  * @author  MCD Application Team\n  * @brief   Header file of GPIO LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_GPIO_H\n#define __STM32L4xx_LL_GPIO_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)\n\n/** @defgroup GPIO_LL GPIO\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures\n  * @{\n  */\n\n/**\n  * @brief LL GPIO Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.\n                              This parameter can be any value of @ref GPIO_LL_EC_PIN */\n\n  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_MODE.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/\n\n  uint32_t Speed;        /*!< Specifies the speed for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/\n\n  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/\n\n  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_PULL.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/\n\n  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.\n                              This parameter can be a value of @ref GPIO_LL_EC_AF.\n\n                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/\n} LL_GPIO_InitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EC_PIN PIN\n  * @{\n  */\n#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */\n#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */\n#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */\n#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */\n#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */\n#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */\n#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */\n#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */\n#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */\n#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */\n#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */\n#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */\n#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */\n#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */\n#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */\n#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */\n#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \\\n                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \\\n                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \\\n                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \\\n                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \\\n                                           GPIO_BSRR_BS15) /*!< Select all pins */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_MODE Mode\n  * @{\n  */\n#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */\n#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */\n#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */\n#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_OUTPUT Output Type\n  * @{\n  */\n#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */\n#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_SPEED Output Speed\n  * @{\n  */\n#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */\n#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */\n#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */\n#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */\n/**\n  * @}\n  */\n#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW\n#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM\n#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH\n#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH\n\n/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down\n  * @{\n  */\n#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */\n#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */\n#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EC_AF Alternate Function\n  * @{\n  */\n#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */\n#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */\n#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */\n#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */\n#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */\n#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */\n#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */\n#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */\n#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */\n#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */\n#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */\n#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */\n#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */\n#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */\n#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */\n#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in GPIO register\n  * @param  __INSTANCE__ GPIO Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in GPIO register\n  * @param  __INSTANCE__ GPIO Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions\n  * @{\n  */\n\n/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration\n  * @{\n  */\n\n/**\n  * @brief  Configure gpio mode for a dedicated pin on dedicated port.\n  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Mode This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_MODE_INPUT\n  *         @arg @ref LL_GPIO_MODE_OUTPUT\n  *         @arg @ref LL_GPIO_MODE_ALTERNATE\n  *         @arg @ref LL_GPIO_MODE_ANALOG\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)\n{\n  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio mode for a dedicated pin on dedicated port.\n  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_MODE_INPUT\n  *         @arg @ref LL_GPIO_MODE_OUTPUT\n  *         @arg @ref LL_GPIO_MODE_ALTERNATE\n  *         @arg @ref LL_GPIO_MODE_ANALOG\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->MODER,\n                             (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio output type for several pins on dedicated port.\n  * @note   Output type as to be set when gpio pin is in output or\n  *         alternate modes. Possible type are Push-pull or Open-drain.\n  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @param  OutputType This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL\n  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)\n{\n  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));\n}\n\n/**\n  * @brief  Return gpio output type for several pins on dedicated port.\n  * @note   Output type as to be set when gpio pin is in output or\n  *         alternate modes. Possible type are Push-pull or Open-drain.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL\n  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));\n}\n\n/**\n  * @brief  Configure gpio speed for a dedicated pin on dedicated port.\n  * @note   I/O speed can be Low, Medium, Fast or High speed.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @note   Refer to datasheet for frequency specifications and the power\n  *         supply and load conditions for each speed.\n  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Speed This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW\n  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM\n  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH\n  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)\n{\n  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),\n             (Speed << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio speed for a dedicated pin on dedicated port.\n  * @note   I/O speed can be Low, Medium, Fast or High speed.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @note   Refer to datasheet for frequency specifications and the power\n  *         supply and load conditions for each speed.\n  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW\n  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM\n  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH\n  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,\n                             (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Pull This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PULL_NO\n  *         @arg @ref LL_GPIO_PULL_UP\n  *         @arg @ref LL_GPIO_PULL_DOWN\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)\n{\n  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));\n}\n\n/**\n  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_PULL_NO\n  *         @arg @ref LL_GPIO_PULL_UP\n  *         @arg @ref LL_GPIO_PULL_DOWN\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->PUPDR,\n                             (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));\n}\n\n/**\n  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  * @param  Alternate This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)\n{\n  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),\n             (Alternate << (POSITION_VAL(Pin) * 4U)));\n}\n\n/**\n  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.\n  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->AFR[0],\n                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));\n}\n\n/**\n  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @note   Warning: only one pin can be passed as parameter.\n  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @param  Alternate This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)\n{\n  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),\n             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));\n}\n\n/**\n  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.\n  * @note   Possible values are from AF0 to AF15 depending on target.\n  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15\n  * @param  GPIOx GPIO Port\n  * @param  Pin This parameter can be one of the following values:\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_GPIO_AF_0\n  *         @arg @ref LL_GPIO_AF_1\n  *         @arg @ref LL_GPIO_AF_2\n  *         @arg @ref LL_GPIO_AF_3\n  *         @arg @ref LL_GPIO_AF_4\n  *         @arg @ref LL_GPIO_AF_5\n  *         @arg @ref LL_GPIO_AF_6\n  *         @arg @ref LL_GPIO_AF_7\n  *         @arg @ref LL_GPIO_AF_8\n  *         @arg @ref LL_GPIO_AF_9\n  *         @arg @ref LL_GPIO_AF_10\n  *         @arg @ref LL_GPIO_AF_11\n  *         @arg @ref LL_GPIO_AF_12\n  *         @arg @ref LL_GPIO_AF_13\n  *         @arg @ref LL_GPIO_AF_14\n  *         @arg @ref LL_GPIO_AF_15\n  */\n__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)\n{\n  return (uint32_t)(READ_BIT(GPIOx->AFR[1],\n                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));\n}\n\n#if defined(GPIO_ASCR_ASC0)\n/**\n  * @brief  Connect analog switch to ADC input of several pins for a dedicated port.\n  * @note   This bit must be set prior to the ADC conversion.\n  *         Only the IO which connected to the ADC input are effective.\n  *         Other IO must be kept reset value\n  * @rmtoll ASCR         ASCy          LL_GPIO_EnablePinAnalogControl\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_EnablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  SET_BIT(GPIOx->ASCR, PinMask);\n}\n\n/**\n  * @brief  Disconnect analog switch to ADC input of several pins for a dedicated port.\n  * @rmtoll ASCR         ASCy          LL_GPIO_DisablePinAnalogControl\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_DisablePinAnalogControl(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  CLEAR_BIT(GPIOx->ASCR, PinMask);\n}\n#endif /* GPIO_ASCR_ASC0 */\n\n/**\n  * @brief  Lock configuration of several pins for a dedicated port.\n  * @note   When the lock sequence has been applied on a port bit, the\n  *         value of this port bit can no longer be modified until the\n  *         next reset.\n  * @note   Each lock bit freezes a specific configuration register\n  *         (control and alternate function registers).\n  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  __IO uint32_t temp;\n  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);\n  WRITE_REG(GPIOx->LCKR, PinMask);\n  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);\n  temp = READ_REG(GPIOx->LCKR);\n  (void) temp;\n}\n\n/**\n  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.\n  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.\n  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked\n  * @param  GPIOx GPIO Port\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)\n{\n  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_LL_EF_Data_Access Data Access\n  * @{\n  */\n\n/**\n  * @brief  Return full input data register value for a dedicated port.\n  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort\n  * @param  GPIOx GPIO Port\n  * @retval Input data register value of port\n  */\n__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)\n{\n  return (uint32_t)(READ_REG(GPIOx->IDR));\n}\n\n/**\n  * @brief  Return if input data level for several pins of dedicated port is high or low.\n  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Write output data register for the port.\n  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort\n  * @param  GPIOx GPIO Port\n  * @param  PortValue Level value for each pin of the port\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)\n{\n  WRITE_REG(GPIOx->ODR, PortValue);\n}\n\n/**\n  * @brief  Return full output data register value for a dedicated port.\n  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort\n  * @param  GPIOx GPIO Port\n  * @retval Output data register value of port\n  */\n__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)\n{\n  return (uint32_t)(READ_REG(GPIOx->ODR));\n}\n\n/**\n  * @brief  Return if input data level for several pins of dedicated port is high or low.\n  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));\n}\n\n/**\n  * @brief  Set several pins to high level on dedicated gpio port.\n  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->BSRR, PinMask);\n}\n\n/**\n  * @brief  Set several pins to low level on dedicated gpio port.\n  * @rmtoll BRR          BRy           LL_GPIO_ResetOutputPin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->BRR, PinMask);\n}\n\n/**\n  * @brief  Toggle data value for several pin of dedicated port.\n  * @rmtoll ODR          ODy           LL_GPIO_TogglePin\n  * @param  GPIOx GPIO Port\n  * @param  PinMask This parameter can be a combination of the following values:\n  *         @arg @ref LL_GPIO_PIN_0\n  *         @arg @ref LL_GPIO_PIN_1\n  *         @arg @ref LL_GPIO_PIN_2\n  *         @arg @ref LL_GPIO_PIN_3\n  *         @arg @ref LL_GPIO_PIN_4\n  *         @arg @ref LL_GPIO_PIN_5\n  *         @arg @ref LL_GPIO_PIN_6\n  *         @arg @ref LL_GPIO_PIN_7\n  *         @arg @ref LL_GPIO_PIN_8\n  *         @arg @ref LL_GPIO_PIN_9\n  *         @arg @ref LL_GPIO_PIN_10\n  *         @arg @ref LL_GPIO_PIN_11\n  *         @arg @ref LL_GPIO_PIN_12\n  *         @arg @ref LL_GPIO_PIN_13\n  *         @arg @ref LL_GPIO_PIN_14\n  *         @arg @ref LL_GPIO_PIN_15\n  *         @arg @ref LL_GPIO_PIN_ALL\n  * @retval None\n  */\n__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)\n{\n  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\nErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);\nErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);\nvoid        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_GPIO_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_lpuart.h\n  * @author  MCD Application Team\n  * @brief   Header file of LPUART LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_LPUART_H\n#define __STM32L4xx_LL_LPUART_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (LPUART1)\n\n/** @defgroup LPUART_LL LPUART\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n#if defined(USART_PRESC_PRESCALER)\n/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables\n  * @{\n  */\n/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */\nstatic const uint16_t LPUART_PRESCALER_TAB[] =\n{\n  (uint16_t)1,\n  (uint16_t)2,\n  (uint16_t)4,\n  (uint16_t)6,\n  (uint16_t)8,\n  (uint16_t)10,\n  (uint16_t)12,\n  (uint16_t)16,\n  (uint16_t)32,\n  (uint16_t)64,\n  (uint16_t)128,\n  (uint16_t)256\n};\n/**\n  * @}\n  */\n#endif\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants\n  * @{\n  */\n/* Defines used in Baud Rate related macros and corresponding register setting computation */\n#define LPUART_LPUARTDIV_FREQ_MUL     256U\n#define LPUART_BRR_MASK               0x000FFFFFU\n#define LPUART_BRR_MIN_VALUE          0x00000300U\n/**\n  * @}\n  */\n\n\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures\n  * @{\n  */\n\n/**\n  * @brief LL LPUART Init Structure definition\n  */\ntypedef struct\n{\n#if defined(USART_PRESC_PRESCALER)\n  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.\n                                           This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/\n\n#endif\n  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/\n\n  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.\n                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/\n\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\n                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/\n\n  uint32_t Parity;                    /*!< Specifies the parity mode.\n                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/\n\n  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.\n                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/\n\n  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.\n                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/\n\n} LL_LPUART_InitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants\n  * @{\n  */\n\n/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function\n  * @{\n  */\n#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error flag */\n#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error flag */\n#define LL_LPUART_ICR_NCF                  USART_ICR_NCF                 /*!< Noise detected flag */\n#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error flag */\n#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected flag */\n#if defined(USART_CR1_FIFOEN)\n#define LL_LPUART_ICR_TXFECF               USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */\n#endif\n#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete flag */\n#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS flag */\n#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match flag */\n#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function\n  * @{\n  */\n#define LL_LPUART_ISR_PE                   USART_ISR_PE                  /*!< Parity error flag */\n#define LL_LPUART_ISR_FE                   USART_ISR_FE                  /*!< Framing error flag */\n#define LL_LPUART_ISR_NE                   USART_ISR_NE                  /*!< Noise detected flag */\n#define LL_LPUART_ISR_ORE                  USART_ISR_ORE                 /*!< Overrun error flag */\n#define LL_LPUART_ISR_IDLE                 USART_ISR_IDLE                /*!< Idle line detected flag */\n#if defined(USART_CR1_FIFOEN)\n#define LL_LPUART_ISR_RXNE_RXFNE           USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */\n#else\n#define LL_LPUART_ISR_RXNE                 USART_ISR_RXNE                /*!< Read data register not empty flag */\n#endif\n#define LL_LPUART_ISR_TC                   USART_ISR_TC                  /*!< Transmission complete flag */\n#if defined(USART_CR1_FIFOEN)\n#define LL_LPUART_ISR_TXE_TXFNF            USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/\n#else\n#define LL_LPUART_ISR_TXE                  USART_ISR_TXE                 /*!< Transmit data register empty flag */\n#endif\n#define LL_LPUART_ISR_CTSIF                USART_ISR_CTSIF               /*!< CTS interrupt flag */\n#define LL_LPUART_ISR_CTS                  USART_ISR_CTS                 /*!< CTS flag */\n#define LL_LPUART_ISR_BUSY                 USART_ISR_BUSY                /*!< Busy flag */\n#define LL_LPUART_ISR_CMF                  USART_ISR_CMF                 /*!< Character match flag */\n#define LL_LPUART_ISR_SBKF                 USART_ISR_SBKF                /*!< Send break flag */\n#define LL_LPUART_ISR_RWU                  USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */\n#define LL_LPUART_ISR_WUF                  USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */\n#define LL_LPUART_ISR_TEACK                USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */\n#define LL_LPUART_ISR_REACK                USART_ISR_REACK               /*!< Receive enable acknowledge flag */\n#if defined(USART_CR1_FIFOEN)\n#define LL_LPUART_ISR_TXFE                 USART_ISR_TXFE                /*!< TX FIFO empty flag */\n#define LL_LPUART_ISR_RXFF                 USART_ISR_RXFF                /*!< RX FIFO full flag */\n#define LL_LPUART_ISR_RXFT                 USART_ISR_RXFT                /*!< RX FIFO threshold flag */\n#define LL_LPUART_ISR_TXFT                 USART_ISR_TXFT                /*!< TX FIFO threshold flag */\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions\n  * @{\n  */\n#define LL_LPUART_CR1_IDLEIE               USART_CR1_IDLEIE              /*!< IDLE interrupt enable */\n#if defined(USART_CR1_FIFOEN)\n#define LL_LPUART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */\n#else\n#define LL_LPUART_CR1_RXNEIE               USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */\n#endif\n#define LL_LPUART_CR1_TCIE                 USART_CR1_TCIE                /*!< Transmission complete interrupt enable */\n#if defined(USART_CR1_FIFOEN)\n#define LL_LPUART_CR1_TXEIE_TXFNFIE        USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */\n#else\n#define LL_LPUART_CR1_TXEIE                USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */\n#endif\n#define LL_LPUART_CR1_PEIE                 USART_CR1_PEIE                /*!< Parity error */\n#define LL_LPUART_CR1_CMIE                 USART_CR1_CMIE                /*!< Character match interrupt enable */\n#if defined(USART_CR1_FIFOEN)\n#define LL_LPUART_CR1_TXFEIE               USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */\n#define LL_LPUART_CR1_RXFFIE               USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */\n#endif\n#define LL_LPUART_CR3_EIE                  USART_CR3_EIE                 /*!< Error interrupt enable */\n#define LL_LPUART_CR3_CTSIE                USART_CR3_CTSIE               /*!< CTS interrupt enable */\n#define LL_LPUART_CR3_WUFIE                USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */\n#if defined(USART_CR1_FIFOEN)\n#define LL_LPUART_CR3_TXFTIE               USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */\n#define LL_LPUART_CR3_RXFTIE               USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */\n#endif\n/**\n  * @}\n  */\n#if defined(USART_CR1_FIFOEN)\n\n/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold\n  * @{\n  */\n#define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */\n#define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */\n#define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */\n#define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */\n#define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */\n#define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */\n/**\n  * @}\n  */\n#endif\n\n/** @defgroup LPUART_LL_EC_DIRECTION Direction\n  * @{\n  */\n#define LL_LPUART_DIRECTION_NONE           0x00000000U                        /*!< Transmitter and Receiver are disabled */\n#define LL_LPUART_DIRECTION_RX             USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */\n#define LL_LPUART_DIRECTION_TX             USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */\n#define LL_LPUART_DIRECTION_TX_RX          (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_PARITY Parity Control\n  * @{\n  */\n#define LL_LPUART_PARITY_NONE              0x00000000U                        /*!< Parity control disabled */\n#define LL_LPUART_PARITY_EVEN              USART_CR1_PCE                      /*!< Parity control enabled and Even Parity is selected */\n#define LL_LPUART_PARITY_ODD               (USART_CR1_PCE | USART_CR1_PS)     /*!< Parity control enabled and Odd Parity is selected */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_WAKEUP Wakeup\n  * @{\n  */\n#define LL_LPUART_WAKEUP_IDLELINE          0x00000000U                        /*!<  LPUART wake up from Mute mode on Idle Line */\n#define LL_LPUART_WAKEUP_ADDRESSMARK       USART_CR1_WAKE                     /*!<  LPUART wake up from Mute mode on Address Mark */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth\n  * @{\n  */\n#define LL_LPUART_DATAWIDTH_7B             USART_CR1_M1                       /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */\n#define LL_LPUART_DATAWIDTH_8B             0x00000000U                        /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */\n#define LL_LPUART_DATAWIDTH_9B             USART_CR1_M0                       /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */\n/**\n  * @}\n  */\n#if defined(USART_PRESC_PRESCALER)\n\n/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler\n  * @{\n  */\n#define LL_LPUART_PRESCALER_DIV1           0x00000000U                                                                   /*!< Input clock not devided   */\n#define LL_LPUART_PRESCALER_DIV2           (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */\n#define LL_LPUART_PRESCALER_DIV4           (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */\n#define LL_LPUART_PRESCALER_DIV6           (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */\n#define LL_LPUART_PRESCALER_DIV8           (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */\n#define LL_LPUART_PRESCALER_DIV10          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */\n#define LL_LPUART_PRESCALER_DIV12          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */\n#define LL_LPUART_PRESCALER_DIV16          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */\n#define LL_LPUART_PRESCALER_DIV32          (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */\n#define LL_LPUART_PRESCALER_DIV64          (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */\n#define LL_LPUART_PRESCALER_DIV128         (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */\n#define LL_LPUART_PRESCALER_DIV256         (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */\n/**\n  * @}\n  */\n#endif\n\n/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits\n  * @{\n  */\n#define LL_LPUART_STOPBITS_1               0x00000000U                        /*!< 1 stop bit */\n#define LL_LPUART_STOPBITS_2               USART_CR2_STOP_1                   /*!< 2 stop bits */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap\n  * @{\n  */\n#define LL_LPUART_TXRX_STANDARD            0x00000000U                        /*!< TX/RX pins are used as defined in standard pinout */\n#define LL_LPUART_TXRX_SWAPPED             (USART_CR2_SWAP)                   /*!< TX and RX pins functions are swapped.             */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion\n  * @{\n  */\n#define LL_LPUART_RXPIN_LEVEL_STANDARD     0x00000000U                        /*!< RX pin signal works using the standard logic levels */\n#define LL_LPUART_RXPIN_LEVEL_INVERTED     (USART_CR2_RXINV)                  /*!< RX pin signal values are inverted.                  */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion\n  * @{\n  */\n#define LL_LPUART_TXPIN_LEVEL_STANDARD     0x00000000U                        /*!< TX pin signal works using the standard logic levels */\n#define LL_LPUART_TXPIN_LEVEL_INVERTED     (USART_CR2_TXINV)                  /*!< TX pin signal values are inverted.                  */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion\n  * @{\n  */\n#define LL_LPUART_BINARY_LOGIC_POSITIVE    0x00000000U                        /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */\n#define LL_LPUART_BINARY_LOGIC_NEGATIVE    USART_CR2_DATAINV                  /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_BITORDER Bit Order\n  * @{\n  */\n#define LL_LPUART_BITORDER_LSBFIRST        0x00000000U                        /*!< data is transmitted/received with data bit 0 first, following the start bit */\n#define LL_LPUART_BITORDER_MSBFIRST        USART_CR2_MSBFIRST                 /*!< data is transmitted/received with the MSB first, following the start bit */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection\n  * @{\n  */\n#define LL_LPUART_ADDRESS_DETECT_4B        0x00000000U                        /*!< 4-bit address detection method selected */\n#define LL_LPUART_ADDRESS_DETECT_7B        USART_CR2_ADDM7                    /*!< 7-bit address detection (in 8-bit data mode) method selected */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control\n  * @{\n  */\n#define LL_LPUART_HWCONTROL_NONE           0x00000000U                        /*!< CTS and RTS hardware flow control disabled */\n#define LL_LPUART_HWCONTROL_RTS            USART_CR3_RTSE                     /*!< RTS output enabled, data is only requested when there is space in the receive buffer */\n#define LL_LPUART_HWCONTROL_CTS            USART_CR3_CTSE                     /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */\n#define LL_LPUART_HWCONTROL_RTS_CTS        (USART_CR3_RTSE | USART_CR3_CTSE)  /*!< CTS and RTS hardware flow control enabled */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation\n  * @{\n  */\n#define LL_LPUART_WAKEUP_ON_ADDRESS        0x00000000U                             /*!< Wake up active on address match */\n#define LL_LPUART_WAKEUP_ON_STARTBIT       USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */\n#define LL_LPUART_WAKEUP_ON_RXNE           (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity\n  * @{\n  */\n#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U                        /*!< DE signal is active high */\n#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP                      /*!< DE signal is active low */\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data\n  * @{\n  */\n#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U                       /*!< Get address of data register used for transmission */\n#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U                       /*!< Get address of data register used for reception */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros\n  * @{\n  */\n\n/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in LPUART register\n  * @param  __INSTANCE__ LPUART Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in LPUART register\n  * @param  __INSTANCE__ LPUART Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros\n  * @{\n  */\n\n/**\n  * @brief  Compute LPUARTDIV value according to Peripheral Clock and\n  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)\n  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance\n  @if USART_PRESC_PRESCALER\n  * @param  __PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_PRESCALER_DIV1\n  *         @arg @ref LL_LPUART_PRESCALER_DIV2\n  *         @arg @ref LL_LPUART_PRESCALER_DIV4\n  *         @arg @ref LL_LPUART_PRESCALER_DIV6\n  *         @arg @ref LL_LPUART_PRESCALER_DIV8\n  *         @arg @ref LL_LPUART_PRESCALER_DIV10\n  *         @arg @ref LL_LPUART_PRESCALER_DIV12\n  *         @arg @ref LL_LPUART_PRESCALER_DIV16\n  *         @arg @ref LL_LPUART_PRESCALER_DIV32\n  *         @arg @ref LL_LPUART_PRESCALER_DIV64\n  *         @arg @ref LL_LPUART_PRESCALER_DIV128\n  *         @arg @ref LL_LPUART_PRESCALER_DIV256\n  * @param  __PRESCALER__ Prescaler value\n  @endif\n  * @param  __BAUDRATE__ Baud Rate value to achieve\n  * @retval LPUARTDIV value to be used for BRR register filling\n  */\n#if defined(USART_PRESC_PRESCALER)\n#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)\n#else\n#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2))/(__BAUDRATE__)) & LPUART_BRR_MASK)\n#endif\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions\n  * @{\n  */\n\n/** @defgroup LPUART_LL_EF_Configuration Configuration functions\n  * @{\n  */\n\n/**\n  * @brief  LPUART Enable\n  * @rmtoll CR1          UE            LL_LPUART_Enable\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_UE);\n}\n\n/**\n  * @brief  LPUART Disable\n  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,\n  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status\n  *         flags, in the LPUARTx_ISR are set to their default values.\n  * @note   In order to go into low-power mode without generating errors on the line,\n  *         the TE bit must be reset before and the software must wait\n  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.\n  *         The DMA requests are also reset when UE = 0 so the DMA channel must\n  *         be disabled before resetting the UE bit.\n  * @rmtoll CR1          UE            LL_LPUART_Disable\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);\n}\n\n/**\n  * @brief  Indicate if LPUART is enabled\n  * @rmtoll CR1          UE            LL_LPUART_IsEnabled\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n/**\n  * @brief  FIFO Mode Enable\n  * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);\n}\n\n/**\n  * @brief  FIFO Mode Disable\n  * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);\n}\n\n/**\n  * @brief  Indicate if FIFO Mode is enabled\n  * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN));\n}\n\n/**\n  * @brief  Configure TX FIFO Threshold\n  * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold\n  * @param  LPUARTx LPUART Instance\n  * @param  Threshold This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)\n{\n  MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);\n}\n\n/**\n  * @brief  Return TX FIFO Threshold Configuration\n  * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);\n}\n\n/**\n  * @brief  Configure RX FIFO Threshold\n  * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold\n  * @param  LPUARTx LPUART Instance\n  * @param  Threshold This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)\n{\n  MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);\n}\n\n/**\n  * @brief  Return RX FIFO Threshold Configuration\n  * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);\n}\n\n/**\n  * @brief  Configure TX and RX FIFOs Threshold\n  * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\\n\n  *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n  * @param  LPUARTx LPUART Instance\n  * @param  TXThreshold This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8\n  * @param  RXThreshold This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)\n{\n  MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos);\n}\n#endif\n\n/**\n  * @brief  LPUART enabled in STOP Mode\n  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that\n  *         LPUART clock selection is HSI or LSE in RCC.\n  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_UESM);\n}\n\n/**\n  * @brief  LPUART disabled in STOP Mode\n  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode\n  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);\n}\n\n/**\n  * @brief  Indicate if LPUART is enabled in STOP Mode\n  *         (able to wake up MCU from Stop mode or not)\n  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));\n}\n\n/**\n  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)\n  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_RE);\n}\n\n/**\n  * @brief  Receiver Disable\n  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);\n}\n\n/**\n  * @brief  Transmitter Enable\n  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_TE);\n}\n\n/**\n  * @brief  Transmitter Disable\n  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);\n}\n\n/**\n  * @brief  Configure simultaneously enabled/disabled states\n  *         of Transmitter and Receiver\n  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\\n\n  *         CR1          TE            LL_LPUART_SetTransferDirection\n  * @param  LPUARTx LPUART Instance\n  * @param  TransferDirection This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_DIRECTION_NONE\n  *         @arg @ref LL_LPUART_DIRECTION_RX\n  *         @arg @ref LL_LPUART_DIRECTION_TX\n  *         @arg @ref LL_LPUART_DIRECTION_TX_RX\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)\n{\n  MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);\n}\n\n/**\n  * @brief  Return enabled/disabled states of Transmitter and Receiver\n  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\\n\n  *         CR1          TE            LL_LPUART_GetTransferDirection\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_DIRECTION_NONE\n  *         @arg @ref LL_LPUART_DIRECTION_RX\n  *         @arg @ref LL_LPUART_DIRECTION_TX\n  *         @arg @ref LL_LPUART_DIRECTION_TX_RX\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));\n}\n\n/**\n  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)\n  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.\n  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position\n  *         (depending on data width) and parity is checked on the received data.\n  * @rmtoll CR1          PS            LL_LPUART_SetParity\\n\n  *         CR1          PCE           LL_LPUART_SetParity\n  * @param  LPUARTx LPUART Instance\n  * @param  Parity This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_PARITY_NONE\n  *         @arg @ref LL_LPUART_PARITY_EVEN\n  *         @arg @ref LL_LPUART_PARITY_ODD\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)\n{\n  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);\n}\n\n/**\n  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)\n  * @rmtoll CR1          PS            LL_LPUART_GetParity\\n\n  *         CR1          PCE           LL_LPUART_GetParity\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_PARITY_NONE\n  *         @arg @ref LL_LPUART_PARITY_EVEN\n  *         @arg @ref LL_LPUART_PARITY_ODD\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));\n}\n\n/**\n  * @brief  Set Receiver Wake Up method from Mute mode.\n  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod\n  * @param  LPUARTx LPUART Instance\n  * @param  Method This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE\n  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)\n{\n  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);\n}\n\n/**\n  * @brief  Return Receiver Wake Up method from Mute mode\n  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE\n  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));\n}\n\n/**\n  * @brief  Set Word length (nb of data bits, excluding start and stop bits)\n  * @rmtoll CR1          M             LL_LPUART_SetDataWidth\n  * @param  LPUARTx LPUART Instance\n  * @param  DataWidth This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_DATAWIDTH_7B\n  *         @arg @ref LL_LPUART_DATAWIDTH_8B\n  *         @arg @ref LL_LPUART_DATAWIDTH_9B\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)\n{\n  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);\n}\n\n/**\n  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)\n  * @rmtoll CR1          M             LL_LPUART_GetDataWidth\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_DATAWIDTH_7B\n  *         @arg @ref LL_LPUART_DATAWIDTH_8B\n  *         @arg @ref LL_LPUART_DATAWIDTH_9B\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));\n}\n\n/**\n  * @brief  Allow switch between Mute Mode and Active mode\n  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_MME);\n}\n\n/**\n  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.\n  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);\n}\n\n/**\n  * @brief  Indicate if switch between Mute Mode and Active mode is allowed\n  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));\n}\n\n#if defined(USART_PRESC_PRESCALER)\n/**\n  * @brief  Configure Clock source prescaler for baudrate generator and oversampling\n  * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler\n  * @param  LPUARTx LPUART Instance\n  * @param  PrescalerValue This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_PRESCALER_DIV1\n  *         @arg @ref LL_LPUART_PRESCALER_DIV2\n  *         @arg @ref LL_LPUART_PRESCALER_DIV4\n  *         @arg @ref LL_LPUART_PRESCALER_DIV6\n  *         @arg @ref LL_LPUART_PRESCALER_DIV8\n  *         @arg @ref LL_LPUART_PRESCALER_DIV10\n  *         @arg @ref LL_LPUART_PRESCALER_DIV12\n  *         @arg @ref LL_LPUART_PRESCALER_DIV16\n  *         @arg @ref LL_LPUART_PRESCALER_DIV32\n  *         @arg @ref LL_LPUART_PRESCALER_DIV64\n  *         @arg @ref LL_LPUART_PRESCALER_DIV128\n  *         @arg @ref LL_LPUART_PRESCALER_DIV256\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)\n{\n  MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue);\n}\n\n/**\n  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling\n  * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_PRESCALER_DIV1\n  *         @arg @ref LL_LPUART_PRESCALER_DIV2\n  *         @arg @ref LL_LPUART_PRESCALER_DIV4\n  *         @arg @ref LL_LPUART_PRESCALER_DIV6\n  *         @arg @ref LL_LPUART_PRESCALER_DIV8\n  *         @arg @ref LL_LPUART_PRESCALER_DIV10\n  *         @arg @ref LL_LPUART_PRESCALER_DIV12\n  *         @arg @ref LL_LPUART_PRESCALER_DIV16\n  *         @arg @ref LL_LPUART_PRESCALER_DIV32\n  *         @arg @ref LL_LPUART_PRESCALER_DIV64\n  *         @arg @ref LL_LPUART_PRESCALER_DIV128\n  *         @arg @ref LL_LPUART_PRESCALER_DIV256\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));\n}\n#endif\n\n/**\n  * @brief  Set the length of the stop bits\n  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength\n  * @param  LPUARTx LPUART Instance\n  * @param  StopBits This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_STOPBITS_1\n  *         @arg @ref LL_LPUART_STOPBITS_2\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)\n{\n  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);\n}\n\n/**\n  * @brief  Retrieve the length of the stop bits\n  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_STOPBITS_1\n  *         @arg @ref LL_LPUART_STOPBITS_2\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));\n}\n\n/**\n  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function\n  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function\n  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function\n  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\\n\n  *         CR1          PCE           LL_LPUART_ConfigCharacter\\n\n  *         CR1          M             LL_LPUART_ConfigCharacter\\n\n  *         CR2          STOP          LL_LPUART_ConfigCharacter\n  * @param  LPUARTx LPUART Instance\n  * @param  DataWidth This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_DATAWIDTH_7B\n  *         @arg @ref LL_LPUART_DATAWIDTH_8B\n  *         @arg @ref LL_LPUART_DATAWIDTH_9B\n  * @param  Parity This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_PARITY_NONE\n  *         @arg @ref LL_LPUART_PARITY_EVEN\n  *         @arg @ref LL_LPUART_PARITY_ODD\n  * @param  StopBits This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_STOPBITS_1\n  *         @arg @ref LL_LPUART_STOPBITS_2\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,\n                                               uint32_t StopBits)\n{\n  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);\n  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);\n}\n\n/**\n  * @brief  Configure TX/RX pins swapping setting.\n  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap\n  * @param  LPUARTx LPUART Instance\n  * @param  SwapConfig This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_TXRX_STANDARD\n  *         @arg @ref LL_LPUART_TXRX_SWAPPED\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)\n{\n  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);\n}\n\n/**\n  * @brief  Retrieve TX/RX pins swapping configuration.\n  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_TXRX_STANDARD\n  *         @arg @ref LL_LPUART_TXRX_SWAPPED\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));\n}\n\n/**\n  * @brief  Configure RX pin active level logic\n  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel\n  * @param  LPUARTx LPUART Instance\n  * @param  PinInvMethod This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD\n  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)\n{\n  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);\n}\n\n/**\n  * @brief  Retrieve RX pin active level logic configuration\n  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD\n  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));\n}\n\n/**\n  * @brief  Configure TX pin active level logic\n  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel\n  * @param  LPUARTx LPUART Instance\n  * @param  PinInvMethod This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD\n  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)\n{\n  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);\n}\n\n/**\n  * @brief  Retrieve TX pin active level logic configuration\n  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD\n  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));\n}\n\n/**\n  * @brief  Configure Binary data logic.\n  *\n  * @note   Allow to define how Logical data from the data register are send/received :\n  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)\n  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic\n  * @param  LPUARTx LPUART Instance\n  * @param  DataLogic This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE\n  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)\n{\n  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);\n}\n\n/**\n  * @brief  Retrieve Binary data configuration\n  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE\n  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));\n}\n\n/**\n  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)\n  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.\n  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.\n  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder\n  * @param  LPUARTx LPUART Instance\n  * @param  BitOrder This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST\n  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)\n{\n  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);\n}\n\n/**\n  * @brief  Return transfer bit order (either Less or Most Significant Bit First)\n  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.\n  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.\n  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST\n  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));\n}\n\n/**\n  * @brief  Set Address of the LPUART node.\n  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,\n  *         for wake up with address mark detection.\n  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.\n  *         (b7-b4 should be set to 0)\n  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.\n  *         (This is used in multiprocessor communication during Mute mode or Stop mode,\n  *         for wake up with 7-bit address mark detection.\n  *         The MSB of the character sent by the transmitter should be equal to 1.\n  *         It may also be used for character detection during normal reception,\n  *         Mute mode inactive (for example, end of block detection in ModBus protocol).\n  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]\n  *         value and CMF flag is set on match)\n  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\\n\n  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress\n  * @param  LPUARTx LPUART Instance\n  * @param  AddressLen This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B\n  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B\n  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)\n{\n  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,\n             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));\n}\n\n/**\n  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.\n  * @note   If 4-bit Address Detection is selected in ADDM7,\n  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)\n  *         If 7-bit Address Detection is selected in ADDM7,\n  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)\n  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress\n  * @param  LPUARTx LPUART Instance\n  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);\n}\n\n/**\n  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)\n  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B\n  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));\n}\n\n/**\n  * @brief  Enable RTS HW Flow Control\n  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);\n}\n\n/**\n  * @brief  Disable RTS HW Flow Control\n  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);\n}\n\n/**\n  * @brief  Enable CTS HW Flow Control\n  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);\n}\n\n/**\n  * @brief  Disable CTS HW Flow Control\n  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);\n}\n\n/**\n  * @brief  Configure HW Flow Control mode (both CTS and RTS)\n  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\\n\n  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl\n  * @param  LPUARTx LPUART Instance\n  * @param  HardwareFlowControl This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_HWCONTROL_NONE\n  *         @arg @ref LL_LPUART_HWCONTROL_RTS\n  *         @arg @ref LL_LPUART_HWCONTROL_CTS\n  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)\n{\n  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);\n}\n\n/**\n  * @brief  Return HW Flow Control configuration (both CTS and RTS)\n  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\\n\n  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_HWCONTROL_NONE\n  *         @arg @ref LL_LPUART_HWCONTROL_RTS\n  *         @arg @ref LL_LPUART_HWCONTROL_CTS\n  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));\n}\n\n/**\n  * @brief  Enable Overrun detection\n  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);\n}\n\n/**\n  * @brief  Disable Overrun detection\n  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);\n}\n\n/**\n  * @brief  Indicate if Overrun detection is enabled\n  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);\n}\n\n/**\n  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)\n  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType\n  * @param  LPUARTx LPUART Instance\n  * @param  Type This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS\n  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT\n  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)\n{\n  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);\n}\n\n/**\n  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)\n  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS\n  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT\n  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));\n}\n\n/**\n  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.\n  *\n  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)\n  *         according to used Peripheral Clock and expected Baud Rate values\n  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid\n  *         (Baud rate value != 0).\n  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,\n  *         a care should be taken when generating high baud rates using high PeriphClk\n  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].\n  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate\n  * @param  LPUARTx LPUART Instance\n  * @param  PeriphClk Peripheral Clock\n  @if USART_PRESC_PRESCALER\n  * @param  PrescalerValue This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_PRESCALER_DIV1\n  *         @arg @ref LL_LPUART_PRESCALER_DIV2\n  *         @arg @ref LL_LPUART_PRESCALER_DIV4\n  *         @arg @ref LL_LPUART_PRESCALER_DIV6\n  *         @arg @ref LL_LPUART_PRESCALER_DIV8\n  *         @arg @ref LL_LPUART_PRESCALER_DIV10\n  *         @arg @ref LL_LPUART_PRESCALER_DIV12\n  *         @arg @ref LL_LPUART_PRESCALER_DIV16\n  *         @arg @ref LL_LPUART_PRESCALER_DIV32\n  *         @arg @ref LL_LPUART_PRESCALER_DIV64\n  *         @arg @ref LL_LPUART_PRESCALER_DIV128\n  *         @arg @ref LL_LPUART_PRESCALER_DIV256\n  @endif\n  * @param  BaudRate Baud Rate\n  * @retval None\n  */\n#if defined(USART_PRESC_PRESCALER)\n__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate)\n#else\n__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate)\n#endif\n{\n#if defined(USART_PRESC_PRESCALER)\n  LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);\n#else\n  LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);\n#endif\n}\n\n/**\n  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register\n  *         (full BRR content), and to used Peripheral Clock values\n  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.\n  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate\n  * @param  LPUARTx LPUART Instance\n  * @param  PeriphClk Peripheral Clock\n  @if USART_PRESC_PRESCALER\n  * @param  PrescalerValue This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_PRESCALER_DIV1\n  *         @arg @ref LL_LPUART_PRESCALER_DIV2\n  *         @arg @ref LL_LPUART_PRESCALER_DIV4\n  *         @arg @ref LL_LPUART_PRESCALER_DIV6\n  *         @arg @ref LL_LPUART_PRESCALER_DIV8\n  *         @arg @ref LL_LPUART_PRESCALER_DIV10\n  *         @arg @ref LL_LPUART_PRESCALER_DIV12\n  *         @arg @ref LL_LPUART_PRESCALER_DIV16\n  *         @arg @ref LL_LPUART_PRESCALER_DIV32\n  *         @arg @ref LL_LPUART_PRESCALER_DIV64\n  *         @arg @ref LL_LPUART_PRESCALER_DIV128\n  *         @arg @ref LL_LPUART_PRESCALER_DIV256\n  @endif\n  * @retval Baud Rate\n  */\n#if defined(USART_PRESC_PRESCALER)\n__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)\n#else\n__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk)\n#endif\n{\n  register uint32_t lpuartdiv = 0x0U;\n  register uint32_t brrresult = 0x0U;\n#if defined(USART_PRESC_PRESCALER)\n  register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[PrescalerValue]));\n#endif\n\n  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;\n\n  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)\n  {\n#if defined(USART_PRESC_PRESCALER)\n    brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);\n#else\n    brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);\n#endif\n  }\n\n  return (brrresult);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature\n  * @{\n  */\n\n/**\n  * @brief  Enable Single Wire Half-Duplex mode\n  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Disable Single Wire Half-Duplex mode\n  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Indicate if Single Wire Half-Duplex mode is enabled\n  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature\n  * @{\n  */\n\n/**\n  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).\n  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime\n  * @param  LPUARTx LPUART Instance\n  * @param  Time Value between Min_Data=0 and Max_Data=31\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)\n{\n  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);\n}\n\n/**\n  * @brief  Return DEDT (Driver Enable De-Assertion Time)\n  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime\n  * @param  LPUARTx LPUART Instance\n  * @retval Time value expressed on 5 bits ([4:0] bits) : c\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);\n}\n\n/**\n  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).\n  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime\n  * @param  LPUARTx LPUART Instance\n  * @param  Time Value between Min_Data=0 and Max_Data=31\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)\n{\n  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);\n}\n\n/**\n  * @brief  Return DEAT (Driver Enable Assertion Time)\n  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime\n  * @param  LPUARTx LPUART Instance\n  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);\n}\n\n/**\n  * @brief  Enable Driver Enable (DE) Mode\n  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);\n}\n\n/**\n  * @brief  Disable Driver Enable (DE) Mode\n  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);\n}\n\n/**\n  * @brief  Indicate if Driver Enable (DE) Mode is enabled\n  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));\n}\n\n/**\n  * @brief  Select Driver Enable Polarity\n  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity\n  * @param  LPUARTx LPUART Instance\n  * @param  Polarity This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH\n  *         @arg @ref LL_LPUART_DE_POLARITY_LOW\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)\n{\n  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);\n}\n\n/**\n  * @brief  Return Driver Enable Polarity\n  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity\n  * @param  LPUARTx LPUART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH\n  *         @arg @ref LL_LPUART_DE_POLARITY_LOW\n  */\n__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)\n{\n  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Check if the LPUART Parity Error Flag is set or not\n  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));\n}\n\n/**\n  * @brief  Check if the LPUART Framing Error Flag is set or not\n  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));\n}\n\n/**\n  * @brief  Check if the LPUART Noise error detected Flag is set or not\n  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));\n}\n\n/**\n  * @brief  Check if the LPUART OverRun Error Flag is set or not\n  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));\n}\n\n/**\n  * @brief  Check if the LPUART IDLE line detected Flag is set or not\n  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE\n\n/**\n  * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not\n  * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE));\n}\n#else\n\n/**\n  * @brief  Check if the LPUART Read Data Register Not Empty Flag is set or not\n  * @rmtoll ISR          RXNE          LL_LPUART_IsActiveFlag_RXNE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));\n}\n#endif\n\n/**\n  * @brief  Check if the LPUART Transmission Complete Flag is set or not\n  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF\n\n/**\n  * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not\n  * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF));\n}\n#else\n\n/**\n  * @brief  Check if the LPUART Transmit Data Register Empty Flag is set or not\n  * @rmtoll ISR          TXE           LL_LPUART_IsActiveFlag_TXE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));\n}\n#endif\n\n/**\n  * @brief  Check if the LPUART CTS interrupt Flag is set or not\n  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));\n}\n\n/**\n  * @brief  Check if the LPUART CTS Flag is set or not\n  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));\n}\n\n/**\n  * @brief  Check if the LPUART Busy Flag is set or not\n  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));\n}\n\n/**\n  * @brief  Check if the LPUART Character Match Flag is set or not\n  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));\n}\n\n/**\n  * @brief  Check if the LPUART Send Break Flag is set or not\n  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));\n}\n\n/**\n  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not\n  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));\n}\n\n/**\n  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not\n  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));\n}\n\n/**\n  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not\n  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));\n}\n\n/**\n  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not\n  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Check if the LPUART TX FIFO Empty Flag is set or not\n  * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE));\n}\n\n/**\n  * @brief  Check if the LPUART RX FIFO Full Flag is set or not\n  * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF));\n}\n\n/**\n  * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not\n  * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT));\n}\n\n/**\n  * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not\n  * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT));\n}\n#endif\n\n/**\n  * @brief  Clear Parity Error Flag\n  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);\n}\n\n/**\n  * @brief  Clear Framing Error Flag\n  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);\n}\n\n/**\n  * @brief  Clear Noise detected Flag\n  * @rmtoll ICR          NCF           LL_LPUART_ClearFlag_NE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_NCF);\n}\n\n/**\n  * @brief  Clear OverRun Error Flag\n  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);\n}\n\n/**\n  * @brief  Clear IDLE line detected Flag\n  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Clear TX FIFO Empty Flag\n  * @rmtoll ICR          TXFECF        LL_LPUART_ClearFlag_TXFE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);\n}\n#endif\n\n/**\n  * @brief  Clear Transmission Complete Flag\n  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);\n}\n\n/**\n  * @brief  Clear CTS Interrupt Flag\n  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);\n}\n\n/**\n  * @brief  Clear Character Match Flag\n  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);\n}\n\n/**\n  * @brief  Clear Wake Up from stop mode Flag\n  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)\n{\n  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EF_IT_Management IT_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable IDLE Interrupt\n  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE\n\n/**\n  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt\n  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);\n}\n#else\n\n/**\n  * @brief  Enable RX Not Empty Interrupt\n  * @rmtoll CR1          RXNEIE        LL_LPUART_EnableIT_RXNE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);\n}\n#endif\n\n/**\n  * @brief  Enable Transmission Complete Interrupt\n  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF\n\n/**\n  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt\n  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);\n}\n#else\n\n/**\n  * @brief  Enable TX Empty Interrupt\n  * @rmtoll CR1          TXEIE         LL_LPUART_EnableIT_TXE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE);\n}\n#endif\n\n/**\n  * @brief  Enable Parity Error Interrupt\n  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);\n}\n\n/**\n  * @brief  Enable Character Match Interrupt\n  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Enable TX FIFO Empty Interrupt\n  * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);\n}\n\n/**\n  * @brief  Enable RX FIFO Full Interrupt\n  * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);\n}\n#endif\n\n/**\n  * @brief  Enable Error Interrupt\n  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing\n  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).\n  *         - 0: Interrupt is inhibited\n  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.\n  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_EIE);\n}\n\n/**\n  * @brief  Enable CTS Interrupt\n  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);\n}\n\n/**\n  * @brief  Enable Wake Up from Stop Mode Interrupt\n  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Enable TX FIFO Threshold Interrupt\n  * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);\n}\n\n/**\n  * @brief  Enable RX FIFO Threshold Interrupt\n  * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);\n}\n#endif\n\n/**\n  * @brief  Disable IDLE Interrupt\n  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE\n\n/**\n  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt\n  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);\n}\n#else\n\n/**\n  * @brief  Disable RX Not Empty Interrupt\n  * @rmtoll CR1          RXNEIE        LL_LPUART_DisableIT_RXNE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE);\n}\n#endif\n\n/**\n  * @brief  Disable Transmission Complete Interrupt\n  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF\n\n/**\n  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt\n  * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);\n}\n#else\n\n/**\n  * @brief  Disable TX Empty Interrupt\n  * @rmtoll CR1          TXEIE         LL_LPUART_DisableIT_TXE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE);\n}\n#endif\n\n/**\n  * @brief  Disable Parity Error Interrupt\n  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);\n}\n\n/**\n  * @brief  Disable Character Match Interrupt\n  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Disable TX FIFO Empty Interrupt\n  * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);\n}\n\n/**\n  * @brief  Disable RX FIFO Full Interrupt\n  * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);\n}\n#endif\n\n/**\n  * @brief  Disable Error Interrupt\n  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing\n  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).\n  *         - 0: Interrupt is inhibited\n  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.\n  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);\n}\n\n/**\n  * @brief  Disable CTS Interrupt\n  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);\n}\n\n/**\n  * @brief  Disable Wake Up from Stop Mode Interrupt\n  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Disable TX FIFO Threshold Interrupt\n  * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);\n}\n\n/**\n  * @brief  Disable RX FIFO Threshold Interrupt\n  * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);\n}\n#endif\n\n/**\n  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.\n  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE\n\n/**\n  * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE));\n}\n#else\n\n/**\n  * @brief  Check if the LPUART RX Not Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1          RXNEIE        LL_LPUART_IsEnabledIT_RXNE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));\n}\n#endif\n\n/**\n  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.\n  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF\n\n/**\n  * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled\n  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE));\n}\n#else\n\n/**\n  * @brief  Check if the LPUART TX Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1          TXEIE         LL_LPUART_IsEnabledIT_TXE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));\n}\n#endif\n\n/**\n  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.\n  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));\n}\n\n/**\n  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.\n  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));\n}\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled\n  * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE));\n}\n\n/**\n  * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled\n  * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE));\n}\n#endif\n\n/**\n  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.\n  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));\n}\n\n/**\n  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.\n  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));\n}\n\n/**\n  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.\n  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled\n  * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE));\n}\n\n/**\n  * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled\n  * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE));\n}\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable DMA Mode for reception\n  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);\n}\n\n/**\n  * @brief  Disable DMA Mode for reception\n  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);\n}\n\n/**\n  * @brief  Check if DMA Mode is enabled for reception\n  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));\n}\n\n/**\n  * @brief  Enable DMA Mode for transmission\n  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);\n}\n\n/**\n  * @brief  Disable DMA Mode for transmission\n  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);\n}\n\n/**\n  * @brief  Check if DMA Mode is enabled for transmission\n  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));\n}\n\n/**\n  * @brief  Enable DMA Disabling on Reception Error\n  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);\n}\n\n/**\n  * @brief  Disable DMA Disabling on Reception Error\n  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)\n{\n  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);\n}\n\n/**\n  * @brief  Indicate if DMA Disabling on Reception Error is disabled\n  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr\n  * @param  LPUARTx LPUART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)\n{\n  return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));\n}\n\n/**\n  * @brief  Get the LPUART data register address used for DMA transfer\n  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\\n\n  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr\n  * @param  LPUARTx LPUART Instance\n  * @param  Direction This parameter can be one of the following values:\n  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT\n  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE\n  * @retval Address of data register\n  */\n__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)\n{\n  register uint32_t data_reg_addr = 0U;\n\n  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)\n  {\n    /* return address of TDR register */\n    data_reg_addr = (uint32_t) &(LPUARTx->TDR);\n  }\n  else\n  {\n    /* return address of RDR register */\n    data_reg_addr = (uint32_t) &(LPUARTx->RDR);\n  }\n\n  return data_reg_addr;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EF_Data_Management Data_Management\n  * @{\n  */\n\n/**\n  * @brief  Read Receiver Data register (Receive Data value, 8 bits)\n  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8\n  * @param  LPUARTx LPUART Instance\n  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)\n{\n  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));\n}\n\n/**\n  * @brief  Read Receiver Data register (Receive Data value, 9 bits)\n  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9\n  * @param  LPUARTx LPUART Instance\n  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF\n  */\n__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)\n{\n  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));\n}\n\n/**\n  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)\n  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8\n  * @param  LPUARTx LPUART Instance\n  * @param  Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)\n{\n  LPUARTx->TDR = Value;\n}\n\n/**\n  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)\n  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9\n  * @param  LPUARTx LPUART Instance\n  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)\n{\n  LPUARTx->TDR = Value & 0x1FFU;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup LPUART_LL_EF_Execution Execution\n  * @{\n  */\n\n/**\n  * @brief  Request Break sending\n  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ);\n}\n\n/**\n  * @brief  Put LPUART in mute mode and set the RWU flag\n  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ);\n}\n\n/**\n  @if USART_CR1_FIFOEN\n  * @brief  Request a Receive Data and FIFO flush\n  * @note   Allows to discard the received data without reading them, and avoid an overrun\n  *         condition.\n  @else\n  * @brief  Request a Receive Data flush\n  @endif\n  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush\n  * @param  LPUARTx LPUART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)\n{\n  SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ);\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\nErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);\nErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);\nvoid        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* LPUART1 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_LPUART_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_pwr.h\n  * @author  MCD Application Team\n  * @brief   Header file of PWR LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_PWR_H\n#define __STM32L4xx_LL_PWR_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined(PWR)\n\n/** @defgroup PWR_LL PWR\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n\n/* Private macros ------------------------------------------------------------*/\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants\n  * @{\n  */\n\n/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_PWR_WriteReg function\n  * @{\n  */\n#define LL_PWR_SCR_CSBF                    PWR_SCR_CSBF\n#define LL_PWR_SCR_CWUF                    PWR_SCR_CWUF\n#define LL_PWR_SCR_CWUF5                   PWR_SCR_CWUF5\n#define LL_PWR_SCR_CWUF4                   PWR_SCR_CWUF4\n#define LL_PWR_SCR_CWUF3                   PWR_SCR_CWUF3\n#define LL_PWR_SCR_CWUF2                   PWR_SCR_CWUF2\n#define LL_PWR_SCR_CWUF1                   PWR_SCR_CWUF1\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_PWR_ReadReg function\n  * @{\n  */\n#define LL_PWR_SR1_WUFI                    PWR_SR1_WUFI\n#if defined(PWR_SR1_EXT_SMPS_RDY)\n#define LL_PWR_SR1_EXT_SMPS_RDY            PWR_SR1_EXT_SMPS_RDY\n#endif /* PWR_SR1_EXT_SMPS_RDY */\n#define LL_PWR_SR1_SBF                     PWR_SR1_SBF\n#define LL_PWR_SR1_WUF5                    PWR_SR1_WUF5\n#define LL_PWR_SR1_WUF4                    PWR_SR1_WUF4\n#define LL_PWR_SR1_WUF3                    PWR_SR1_WUF3\n#define LL_PWR_SR1_WUF2                    PWR_SR1_WUF2\n#define LL_PWR_SR1_WUF1                    PWR_SR1_WUF1\n#if defined(PWR_SR2_PVMO4)\n#define LL_PWR_SR2_PVMO4                   PWR_SR2_PVMO4\n#endif /* PWR_SR2_PVMO4 */\n#if defined(PWR_SR2_PVMO3)\n#define LL_PWR_SR2_PVMO3                   PWR_SR2_PVMO3\n#endif /* PWR_SR2_PVMO3 */\n#if defined(PWR_SR2_PVMO2)\n#define LL_PWR_SR2_PVMO2                   PWR_SR2_PVMO2\n#endif /* PWR_SR2_PVMO2 */\n#if defined(PWR_SR2_PVMO1)\n#define LL_PWR_SR2_PVMO1                   PWR_SR2_PVMO1\n#endif /* PWR_SR2_PVMO1 */\n#define LL_PWR_SR2_PVDO                    PWR_SR2_PVDO\n#define LL_PWR_SR2_VOSF                    PWR_SR2_VOSF\n#define LL_PWR_SR2_REGLPF                  PWR_SR2_REGLPF\n#define LL_PWR_SR2_REGLPS                  PWR_SR2_REGLPS\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE\n  * @{\n  */\n#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR1_VOS_0)\n#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR1_VOS_1)\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR\n  * @{\n  */\n#define LL_PWR_MODE_STOP0                  (PWR_CR1_LPMS_STOP0)\n#define LL_PWR_MODE_STOP1                  (PWR_CR1_LPMS_STOP1)\n#define LL_PWR_MODE_STOP2                  (PWR_CR1_LPMS_STOP2)\n#define LL_PWR_MODE_STANDBY                (PWR_CR1_LPMS_STANDBY)\n#define LL_PWR_MODE_SHUTDOWN               (PWR_CR1_LPMS_SHUTDOWN)\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring\n  * @{\n  */\n#if defined(PWR_CR2_PVME1)\n#define LL_PWR_PVM_VDDUSB_1_2V             (PWR_CR2_PVME1)     /* Monitoring VDDUSB vs. 1.2V */\n#endif\n#if defined(PWR_CR2_PVME2)\n#define LL_PWR_PVM_VDDIO2_0_9V             (PWR_CR2_PVME2)     /* Monitoring VDDIO2 vs. 0.9V */\n#endif\n#if defined(PWR_CR2_PVME3)\n#define LL_PWR_PVM_VDDA_1_62V              (PWR_CR2_PVME3)     /* Monitoring VDDA vs. 1.62V  */\n#endif\n#if defined(PWR_CR2_PVME4)\n#define LL_PWR_PVM_VDDA_2_2V               (PWR_CR2_PVME4)     /* Monitoring VDDA vs. 2.2V   */\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL\n  * @{\n  */\n#define LL_PWR_PVDLEVEL_0                  (PWR_CR2_PLS_LEV0)  /* VPVD0 around 2.0 V */\n#define LL_PWR_PVDLEVEL_1                  (PWR_CR2_PLS_LEV1)  /* VPVD1 around 2.2 V */\n#define LL_PWR_PVDLEVEL_2                  (PWR_CR2_PLS_LEV2)  /* VPVD2 around 2.4 V */\n#define LL_PWR_PVDLEVEL_3                  (PWR_CR2_PLS_LEV3)  /* VPVD3 around 2.5 V */\n#define LL_PWR_PVDLEVEL_4                  (PWR_CR2_PLS_LEV4)  /* VPVD4 around 2.6 V */\n#define LL_PWR_PVDLEVEL_5                  (PWR_CR2_PLS_LEV5)  /* VPVD5 around 2.8 V */\n#define LL_PWR_PVDLEVEL_6                  (PWR_CR2_PLS_LEV6)  /* VPVD6 around 2.9 V */\n#define LL_PWR_PVDLEVEL_7                  (PWR_CR2_PLS_LEV7)  /* External input analog voltage   (Compare internally to VREFINT) */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_WAKEUP WAKEUP\n  * @{\n  */\n#define LL_PWR_WAKEUP_PIN1                 (PWR_CR3_EWUP1)\n#define LL_PWR_WAKEUP_PIN2                 (PWR_CR3_EWUP2)\n#define LL_PWR_WAKEUP_PIN3                 (PWR_CR3_EWUP3)\n#define LL_PWR_WAKEUP_PIN4                 (PWR_CR3_EWUP4)\n#define LL_PWR_WAKEUP_PIN5                 (PWR_CR3_EWUP5)\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR\n  * @{\n  */\n#define LL_PWR_BATT_CHARG_RESISTOR_5K      (0x00000000U)\n#define LL_PWR_BATT_CHARGRESISTOR_1_5K     (PWR_CR4_VBRS)\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_GPIO GPIO\n  * @{\n  */\n#define LL_PWR_GPIO_A                      ((uint32_t)(&(PWR->PUCRA)))\n#define LL_PWR_GPIO_B                      ((uint32_t)(&(PWR->PUCRB)))\n#define LL_PWR_GPIO_C                      ((uint32_t)(&(PWR->PUCRC)))\n#define LL_PWR_GPIO_D                      ((uint32_t)(&(PWR->PUCRD)))\n#define LL_PWR_GPIO_E                      ((uint32_t)(&(PWR->PUCRE)))\n#if defined(GPIOF)\n#define LL_PWR_GPIO_F                      ((uint32_t)(&(PWR->PUCRF)))\n#endif\n#if defined(GPIOG)\n#define LL_PWR_GPIO_G                      ((uint32_t)(&(PWR->PUCRG)))\n#endif\n#if defined(GPIOH)\n#define LL_PWR_GPIO_H                      ((uint32_t)(&(PWR->PUCRH)))\n#endif\n#if defined(GPIOI)\n#define LL_PWR_GPIO_I                      ((uint32_t)(&(PWR->PUCRI)))\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT\n  * @{\n  */\n#define LL_PWR_GPIO_BIT_0                  (0x00000001U)\n#define LL_PWR_GPIO_BIT_1                  (0x00000002U)\n#define LL_PWR_GPIO_BIT_2                  (0x00000004U)\n#define LL_PWR_GPIO_BIT_3                  (0x00000008U)\n#define LL_PWR_GPIO_BIT_4                  (0x00000010U)\n#define LL_PWR_GPIO_BIT_5                  (0x00000020U)\n#define LL_PWR_GPIO_BIT_6                  (0x00000040U)\n#define LL_PWR_GPIO_BIT_7                  (0x00000080U)\n#define LL_PWR_GPIO_BIT_8                  (0x00000100U)\n#define LL_PWR_GPIO_BIT_9                  (0x00000200U)\n#define LL_PWR_GPIO_BIT_10                 (0x00000400U)\n#define LL_PWR_GPIO_BIT_11                 (0x00000800U)\n#define LL_PWR_GPIO_BIT_12                 (0x00001000U)\n#define LL_PWR_GPIO_BIT_13                 (0x00002000U)\n#define LL_PWR_GPIO_BIT_14                 (0x00004000U)\n#define LL_PWR_GPIO_BIT_15                 (0x00008000U)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros\n  * @{\n  */\n\n/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in PWR register\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in PWR register\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions\n  * @{\n  */\n\n/** @defgroup PWR_LL_EF_Configuration Configuration\n  * @{\n  */\n\n/**\n  * @brief  Switch the regulator from main mode to low-power mode\n  * @rmtoll CR1          LPR           LL_PWR_EnableLowPowerRunMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)\n{\n  SET_BIT(PWR->CR1, PWR_CR1_LPR);\n}\n\n/**\n  * @brief  Switch the regulator from low-power mode to main mode\n  * @rmtoll CR1          LPR           LL_PWR_DisableLowPowerRunMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)\n{\n  CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);\n}\n\n/**\n  * @brief  Switch from run main mode to run low-power mode.\n  * @rmtoll CR1          LPR           LL_PWR_EnterLowPowerRunMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)\n{\n  LL_PWR_EnableLowPowerRunMode();\n}\n\n/**\n  * @brief  Switch from run main mode to low-power mode.\n  * @rmtoll CR1          LPR           LL_PWR_ExitLowPowerRunMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)\n{\n  LL_PWR_DisableLowPowerRunMode();\n}\n\n/**\n  * @brief  Check if the regulator is in low-power mode\n  * @rmtoll CR1          LPR           LL_PWR_IsEnabledLowPowerRunMode\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)\n{\n  return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR));\n}\n\n/**\n  * @brief  Set the main internal regulator output voltage\n  * @note   This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices.\n  * @rmtoll CR1          VOS           LL_PWR_SetRegulVoltageScaling\n  * @param  VoltageScaling This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)\n{\n  MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);\n}\n\n/**\n  * @brief  Get the main internal regulator output voltage\n  * @rmtoll CR1          VOS           LL_PWR_GetRegulVoltageScaling\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1\n  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));\n}\n\n#if defined(PWR_CR5_R1MODE)\n/**\n  * @brief  Enable main regulator voltage range 1 boost mode\n  * @rmtoll CR5          R1MODE        LL_PWR_EnableRange1BoostMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)\n{\n  CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);\n}\n\n/**\n  * @brief  Disable main regulator voltage range 1 boost mode\n  * @rmtoll CR5          R1MODE        LL_PWR_DisableRange1BoostMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)\n{\n  SET_BIT(PWR->CR5, PWR_CR5_R1MODE);\n}\n\n/**\n  * @brief  Check if the main regulator voltage range 1 boost mode is enabled\n  * @rmtoll CR5          R1MODE        LL_PWR_IsEnabledRange1BoostMode\n  * @retval Inverted state of bit (0 or 1).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)\n{\n  return (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == RESET);\n}\n#endif /* PWR_CR5_R1MODE */\n\n/**\n  * @brief  Enable access to the backup domain\n  * @rmtoll CR1          DBP           LL_PWR_EnableBkUpAccess\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)\n{\n  SET_BIT(PWR->CR1, PWR_CR1_DBP);\n}\n\n/**\n  * @brief  Disable access to the backup domain\n  * @rmtoll CR1          DBP           LL_PWR_DisableBkUpAccess\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)\n{\n  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);\n}\n\n/**\n  * @brief  Check if the backup domain is enabled\n  * @rmtoll CR1          DBP           LL_PWR_IsEnabledBkUpAccess\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)\n{\n  return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));\n}\n\n/**\n  * @brief  Set Low-Power mode\n  * @rmtoll CR1          LPMS          LL_PWR_SetPowerMode\n  * @param  LowPowerMode This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_MODE_STOP0\n  *         @arg @ref LL_PWR_MODE_STOP1\n  *         @arg @ref LL_PWR_MODE_STOP2\n  *         @arg @ref LL_PWR_MODE_STANDBY\n  *         @arg @ref LL_PWR_MODE_SHUTDOWN\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)\n{\n  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);\n}\n\n/**\n  * @brief  Get Low-Power mode\n  * @rmtoll CR1          LPMS          LL_PWR_GetPowerMode\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_MODE_STOP0\n  *         @arg @ref LL_PWR_MODE_STOP1\n  *         @arg @ref LL_PWR_MODE_STOP2\n  *         @arg @ref LL_PWR_MODE_STANDBY\n  *         @arg @ref LL_PWR_MODE_SHUTDOWN\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));\n}\n\n#if defined(PWR_CR1_RRSTP)\n/**\n  * @brief  Enable SRAM3 content retention in Stop mode\n  * @rmtoll CR1          RRSTP           LL_PWR_EnableSRAM3Retention\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void)\n{\n  SET_BIT(PWR->CR1, PWR_CR1_RRSTP);\n}\n\n/**\n  * @brief  Disable SRAM3 content retention in Stop mode\n  * @rmtoll CR1          RRSTP           LL_PWR_DisableSRAM3Retention\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void)\n{\n  CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);\n}\n\n/**\n  * @brief  Check if SRAM3 content retention in Stop mode is enabled\n  * @rmtoll CR1          RRSTP           LL_PWR_IsEnabledSRAM3Retention\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void)\n{\n  return (READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP));\n}\n#endif /* PWR_CR1_RRSTP */\n\n#if defined(PWR_CR3_DSIPDEN)\n/**\n  * @brief  Enable pull-down activation on DSI pins\n  * @rmtoll CR3          DSIPDEN           LL_PWR_EnableDSIPinsPDActivation\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void)\n{\n  SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\n}\n\n/**\n  * @brief  Disable pull-down activation on DSI pins\n  * @rmtoll CR3          DSIPDEN           LL_PWR_DisableDSIPinsPDActivation\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void)\n{\n  CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\n}\n\n/**\n  * @brief  Check if pull-down activation on DSI pins is enabled\n  * @rmtoll CR3          DSIPDEN           LL_PWR_IsEnabledDSIPinsPDActivation\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void)\n{\n  return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN));\n}\n#endif /* PWR_CR3_DSIPDEN */\n\n#if defined(PWR_CR2_PVME1)\n/**\n  * @brief  Enable VDDUSB supply\n  * @rmtoll CR2          USV           LL_PWR_EnableVddUSB\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableVddUSB(void)\n{\n  SET_BIT(PWR->CR2, PWR_CR2_USV);\n}\n\n/**\n  * @brief  Disable VDDUSB supply\n  * @rmtoll CR2          USV           LL_PWR_DisableVddUSB\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableVddUSB(void)\n{\n  CLEAR_BIT(PWR->CR2, PWR_CR2_USV);\n}\n\n/**\n  * @brief  Check if VDDUSB supply is enabled\n  * @rmtoll CR2          USV           LL_PWR_IsEnabledVddUSB\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)\n{\n  return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV));\n}\n#endif\n\n#if defined(PWR_CR2_IOSV)\n/**\n  * @brief  Enable VDDIO2 supply\n  * @rmtoll CR2          IOSV          LL_PWR_EnableVddIO2\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableVddIO2(void)\n{\n  SET_BIT(PWR->CR2, PWR_CR2_IOSV);\n}\n\n/**\n  * @brief  Disable VDDIO2 supply\n  * @rmtoll CR2          IOSV          LL_PWR_DisableVddIO2\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableVddIO2(void)\n{\n  CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);\n}\n\n/**\n  * @brief  Check if VDDIO2 supply is enabled\n  * @rmtoll CR2          IOSV          LL_PWR_IsEnabledVddIO2\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)\n{\n  return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV));\n}\n#endif\n\n/**\n  * @brief  Enable the Power Voltage Monitoring on a peripheral\n  * @rmtoll CR2          PVME1         LL_PWR_EnablePVM\\n\n  *         CR2          PVME2         LL_PWR_EnablePVM\\n\n  *         CR2          PVME3         LL_PWR_EnablePVM\\n\n  *         CR2          PVME4         LL_PWR_EnablePVM\n  * @param  PeriphVoltage This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)\n  *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)\n  *         @arg @ref LL_PWR_PVM_VDDA_1_62V\n  *         @arg @ref LL_PWR_PVM_VDDA_2_2V\n  *\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)\n{\n  SET_BIT(PWR->CR2, PeriphVoltage);\n}\n\n/**\n  * @brief  Disable the Power Voltage Monitoring on a peripheral\n  * @rmtoll CR2          PVME1         LL_PWR_DisablePVM\\n\n  *         CR2          PVME2         LL_PWR_DisablePVM\\n\n  *         CR2          PVME3         LL_PWR_DisablePVM\\n\n  *         CR2          PVME4         LL_PWR_DisablePVM\n  * @param  PeriphVoltage This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)\n  *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)\n  *         @arg @ref LL_PWR_PVM_VDDA_1_62V\n  *         @arg @ref LL_PWR_PVM_VDDA_2_2V\n  *\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)\n{\n  CLEAR_BIT(PWR->CR2, PeriphVoltage);\n}\n\n/**\n  * @brief  Check if Power Voltage Monitoring is enabled on a peripheral\n  * @rmtoll CR2          PVME1         LL_PWR_IsEnabledPVM\\n\n  *         CR2          PVME2         LL_PWR_IsEnabledPVM\\n\n  *         CR2          PVME3         LL_PWR_IsEnabledPVM\\n\n  *         CR2          PVME4         LL_PWR_IsEnabledPVM\n  * @param  PeriphVoltage This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)\n  *         @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)\n  *         @arg @ref LL_PWR_PVM_VDDA_1_62V\n  *         @arg @ref LL_PWR_PVM_VDDA_2_2V\n  *\n  *         (*) value not defined in all devices\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)\n{\n  return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage));\n}\n\n/**\n  * @brief  Configure the voltage threshold detected by the Power Voltage Detector\n  * @rmtoll CR2          PLS           LL_PWR_SetPVDLevel\n  * @param  PVDLevel This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_PVDLEVEL_0\n  *         @arg @ref LL_PWR_PVDLEVEL_1\n  *         @arg @ref LL_PWR_PVDLEVEL_2\n  *         @arg @ref LL_PWR_PVDLEVEL_3\n  *         @arg @ref LL_PWR_PVDLEVEL_4\n  *         @arg @ref LL_PWR_PVDLEVEL_5\n  *         @arg @ref LL_PWR_PVDLEVEL_6\n  *         @arg @ref LL_PWR_PVDLEVEL_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)\n{\n  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);\n}\n\n/**\n  * @brief  Get the voltage threshold detection\n  * @rmtoll CR2          PLS           LL_PWR_GetPVDLevel\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_PVDLEVEL_0\n  *         @arg @ref LL_PWR_PVDLEVEL_1\n  *         @arg @ref LL_PWR_PVDLEVEL_2\n  *         @arg @ref LL_PWR_PVDLEVEL_3\n  *         @arg @ref LL_PWR_PVDLEVEL_4\n  *         @arg @ref LL_PWR_PVDLEVEL_5\n  *         @arg @ref LL_PWR_PVDLEVEL_6\n  *         @arg @ref LL_PWR_PVDLEVEL_7\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));\n}\n\n/**\n  * @brief  Enable Power Voltage Detector\n  * @rmtoll CR2          PVDE          LL_PWR_EnablePVD\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnablePVD(void)\n{\n  SET_BIT(PWR->CR2, PWR_CR2_PVDE);\n}\n\n/**\n  * @brief  Disable Power Voltage Detector\n  * @rmtoll CR2          PVDE          LL_PWR_DisablePVD\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisablePVD(void)\n{\n  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);\n}\n\n/**\n  * @brief  Check if Power Voltage Detector is enabled\n  * @rmtoll CR2          PVDE          LL_PWR_IsEnabledPVD\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)\n{\n  return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE));\n}\n\n/**\n  * @brief  Enable Internal Wake-up line\n  * @rmtoll CR3          EIWF          LL_PWR_EnableInternWU\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableInternWU(void)\n{\n  SET_BIT(PWR->CR3, PWR_CR3_EIWF);\n}\n\n/**\n  * @brief  Disable Internal Wake-up line\n  * @rmtoll CR3          EIWF          LL_PWR_DisableInternWU\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableInternWU(void)\n{\n  CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);\n}\n\n/**\n  * @brief  Check if Internal Wake-up line is enabled\n  * @rmtoll CR3          EIWF          LL_PWR_IsEnabledInternWU\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)\n{\n  return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF));\n}\n\n/**\n  * @brief  Enable pull-up and pull-down configuration\n  * @rmtoll CR3          APC           LL_PWR_EnablePUPDCfg\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)\n{\n  SET_BIT(PWR->CR3, PWR_CR3_APC);\n}\n\n/**\n  * @brief  Disable pull-up and pull-down configuration\n  * @rmtoll CR3          APC           LL_PWR_DisablePUPDCfg\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)\n{\n  CLEAR_BIT(PWR->CR3, PWR_CR3_APC);\n}\n\n/**\n  * @brief  Check if pull-up and pull-down configuration is enabled\n  * @rmtoll CR3          APC           LL_PWR_IsEnabledPUPDCfg\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)\n{\n  return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC));\n}\n\n#if defined(PWR_CR3_DSIPDEN)\n/**\n  * @brief  Enable pull-down activation on DSI pins\n  * @rmtoll CR3          DSIPDEN       LL_PWR_EnableDSIPullDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableDSIPullDown(void)\n{\n  SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\n}\n\n/**\n  * @brief  Disable pull-down activation on DSI pins\n  * @rmtoll CR3          DSIPDEN       LL_PWR_DisableDSIPullDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableDSIPullDown(void)\n{\n  CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);\n}\n\n/**\n  * @brief  Check if pull-down activation on DSI pins is enabled\n  * @rmtoll CR3          DSIPDEN       LL_PWR_IsEnabledDSIPullDown\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void)\n{\n  return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN));\n}\n#endif /* PWR_CR3_DSIPDEN */\n\n#if defined(PWR_CR3_EN_ULP)\n/**\n  * @brief  Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes\n  * @rmtoll CR3          EN_ULP       LL_PWR_EnableBORPVD_ULP\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void)\n{\n  SET_BIT(PWR->CR3, PWR_CR3_EN_ULP);\n}\n\n/**\n  * @brief  Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes\n  * @rmtoll CR3          EN_ULP       LL_PWR_DisableBORPVD_ULP\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void)\n{\n  CLEAR_BIT(PWR->CR3, PWR_CR3_EN_ULP);\n}\n\n/**\n  * @brief  Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled\n  * @rmtoll CR3          EN_ULP       LL_PWR_IsEnabledBORPVD_ULP\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void)\n{\n  return (READ_BIT(PWR->CR3, PWR_CR3_EN_ULP) == (PWR_CR3_EN_ULP));\n}\n#endif /* PWR_CR3_EN_ULP */\n\n/**\n  * @brief  Enable SRAM2 content retention in Standby mode\n  * @rmtoll CR3          RRS           LL_PWR_EnableSRAM2Retention\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)\n{\n  SET_BIT(PWR->CR3, PWR_CR3_RRS);\n}\n\n/**\n  * @brief  Disable SRAM2 content retention in Standby mode\n  * @rmtoll CR3          RRS           LL_PWR_DisableSRAM2Retention\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)\n{\n  CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);\n}\n\n/**\n  * @brief  Check if SRAM2 content retention in Standby mode is enabled\n  * @rmtoll CR3          RRS           LL_PWR_IsEnabledSRAM2Retention\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)\n{\n  return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS));\n}\n\n/**\n  * @brief  Enable the WakeUp PINx functionality\n  * @rmtoll CR3          EWUP1         LL_PWR_EnableWakeUpPin\\n\n  *         CR3          EWUP2         LL_PWR_EnableWakeUpPin\\n\n  *         CR3          EWUP3         LL_PWR_EnableWakeUpPin\\n\n  *         CR3          EWUP4         LL_PWR_EnableWakeUpPin\\n\n  *         CR3          EWUP5         LL_PWR_EnableWakeUpPin\\n\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2\n  *         @arg @ref LL_PWR_WAKEUP_PIN3\n  *         @arg @ref LL_PWR_WAKEUP_PIN4\n  *         @arg @ref LL_PWR_WAKEUP_PIN5\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)\n{\n  SET_BIT(PWR->CR3, WakeUpPin);\n}\n\n/**\n  * @brief  Disable the WakeUp PINx functionality\n  * @rmtoll CR3          EWUP1         LL_PWR_DisableWakeUpPin\\n\n  *         CR3          EWUP2         LL_PWR_DisableWakeUpPin\\n\n  *         CR3          EWUP3         LL_PWR_DisableWakeUpPin\\n\n  *         CR3          EWUP4         LL_PWR_DisableWakeUpPin\\n\n  *         CR3          EWUP5         LL_PWR_DisableWakeUpPin\\n\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2\n  *         @arg @ref LL_PWR_WAKEUP_PIN3\n  *         @arg @ref LL_PWR_WAKEUP_PIN4\n  *         @arg @ref LL_PWR_WAKEUP_PIN5\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)\n{\n  CLEAR_BIT(PWR->CR3, WakeUpPin);\n}\n\n/**\n  * @brief  Check if the WakeUp PINx functionality is enabled\n  * @rmtoll CR3          EWUP1         LL_PWR_IsEnabledWakeUpPin\\n\n  *         CR3          EWUP2         LL_PWR_IsEnabledWakeUpPin\\n\n  *         CR3          EWUP3         LL_PWR_IsEnabledWakeUpPin\\n\n  *         CR3          EWUP4         LL_PWR_IsEnabledWakeUpPin\\n\n  *         CR3          EWUP5         LL_PWR_IsEnabledWakeUpPin\\n\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2\n  *         @arg @ref LL_PWR_WAKEUP_PIN3\n  *         @arg @ref LL_PWR_WAKEUP_PIN4\n  *         @arg @ref LL_PWR_WAKEUP_PIN5\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)\n{\n  return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin));\n}\n\n#if defined(PWR_CR4_EXT_SMPS_ON)\n/**\n  * @brief Enable the CFLDO working @ 0.95V\n  * @note  When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the\n  *        internal CFLDO can be reduced to 0.95V.\n  * @rmtoll CR4          EXT_SMPS_ON   LL_PWR_EnableExtSMPS_0V95\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableExtSMPS_0V95(void)\n{\n  SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);\n}\n\n/**\n  * @brief  Disable the CFLDO working @ 0.95V\n  * @note  When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the\n  *        internal CFLDO can be reduced to 0.95V.\n  * @rmtoll CR4          EXT_SMPS_ON   LL_PWR_DisableExtSMPS_0V95\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableExtSMPS_0V95(void)\n{\n  CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);\n}\n\n/**\n  * @brief  Check if CFLDO is working @ 0.95V\n  * @note  When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the\n  *        internal CFLDO can be reduced to 0.95V.\n  * @rmtoll CR4          EXT_SMPS_ON   LL_PWR_IsEnabledExtSMPS_0V95\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS_0V95(void)\n{\n  return (READ_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON) == (PWR_CR4_EXT_SMPS_ON));\n}\n#endif /* PWR_CR4_EXT_SMPS_ON */\n\n/**\n  * @brief  Set the resistor impedance\n  * @rmtoll CR4          VBRS          LL_PWR_SetBattChargResistor\n  * @param  Resistor This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K\n  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)\n{\n  MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);\n}\n\n/**\n  * @brief  Get the resistor impedance\n  * @rmtoll CR4          VBRS          LL_PWR_GetBattChargResistor\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K\n  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K\n  */\n__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)\n{\n  return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));\n}\n\n/**\n  * @brief  Enable battery charging\n  * @rmtoll CR4          VBE           LL_PWR_EnableBatteryCharging\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)\n{\n  SET_BIT(PWR->CR4, PWR_CR4_VBE);\n}\n\n/**\n  * @brief  Disable battery charging\n  * @rmtoll CR4          VBE           LL_PWR_DisableBatteryCharging\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)\n{\n  CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);\n}\n\n/**\n  * @brief  Check if battery charging is enabled\n  * @rmtoll CR4          VBE           LL_PWR_IsEnabledBatteryCharging\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)\n{\n  return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE));\n}\n\n/**\n  * @brief  Set the Wake-Up pin polarity low for the event detection\n  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityLow\\n\n  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityLow\\n\n  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityLow\\n\n  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityLow\\n\n  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityLow\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2\n  *         @arg @ref LL_PWR_WAKEUP_PIN3\n  *         @arg @ref LL_PWR_WAKEUP_PIN4\n  *         @arg @ref LL_PWR_WAKEUP_PIN5\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)\n{\n  SET_BIT(PWR->CR4, WakeUpPin);\n}\n\n/**\n  * @brief  Set the Wake-Up pin polarity high for the event detection\n  * @rmtoll CR4          WP1           LL_PWR_SetWakeUpPinPolarityHigh\\n\n  *         CR4          WP2           LL_PWR_SetWakeUpPinPolarityHigh\\n\n  *         CR4          WP3           LL_PWR_SetWakeUpPinPolarityHigh\\n\n  *         CR4          WP4           LL_PWR_SetWakeUpPinPolarityHigh\\n\n  *         CR4          WP5           LL_PWR_SetWakeUpPinPolarityHigh\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2\n  *         @arg @ref LL_PWR_WAKEUP_PIN3\n  *         @arg @ref LL_PWR_WAKEUP_PIN4\n  *         @arg @ref LL_PWR_WAKEUP_PIN5\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)\n{\n  CLEAR_BIT(PWR->CR4, WakeUpPin);\n}\n\n/**\n  * @brief  Get the Wake-Up pin polarity for the event detection\n  * @rmtoll CR4          WP1           LL_PWR_IsWakeUpPinPolarityLow\\n\n  *         CR4          WP2           LL_PWR_IsWakeUpPinPolarityLow\\n\n  *         CR4          WP3           LL_PWR_IsWakeUpPinPolarityLow\\n\n  *         CR4          WP4           LL_PWR_IsWakeUpPinPolarityLow\\n\n  *         CR4          WP5           LL_PWR_IsWakeUpPinPolarityLow\n  * @param  WakeUpPin This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_WAKEUP_PIN1\n  *         @arg @ref LL_PWR_WAKEUP_PIN2\n  *         @arg @ref LL_PWR_WAKEUP_PIN3\n  *         @arg @ref LL_PWR_WAKEUP_PIN4\n  *         @arg @ref LL_PWR_WAKEUP_PIN5\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)\n{\n  return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin));\n}\n\n/**\n  * @brief  Enable GPIO pull-up state in Standby and Shutdown modes\n  * @rmtoll PUCRA        PU0-15        LL_PWR_EnableGPIOPullUp\\n\n  *         PUCRB        PU0-15        LL_PWR_EnableGPIOPullUp\\n\n  *         PUCRC        PU0-15        LL_PWR_EnableGPIOPullUp\\n\n  *         PUCRD        PU0-15        LL_PWR_EnableGPIOPullUp\\n\n  *         PUCRE        PU0-15        LL_PWR_EnableGPIOPullUp\\n\n  *         PUCRF        PU0-15        LL_PWR_EnableGPIOPullUp\\n\n  *         PUCRG        PU0-15        LL_PWR_EnableGPIOPullUp\\n\n  *         PUCRH        PU0-15        LL_PWR_EnableGPIOPullUp\\n\n  *         PUCRI        PU0-11        LL_PWR_EnableGPIOPullUp\n  * @param  GPIO This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_A\n  *         @arg @ref LL_PWR_GPIO_B\n  *         @arg @ref LL_PWR_GPIO_C\n  *         @arg @ref LL_PWR_GPIO_D\n  *         @arg @ref LL_PWR_GPIO_E\n  *         @arg @ref LL_PWR_GPIO_F (*)\n  *         @arg @ref LL_PWR_GPIO_G (*)\n  *         @arg @ref LL_PWR_GPIO_H\n  *         @arg @ref LL_PWR_GPIO_I (*)\n  *\n  *         (*) value not defined in all devices\n  * @param  GPIONumber This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_BIT_0\n  *         @arg @ref LL_PWR_GPIO_BIT_1\n  *         @arg @ref LL_PWR_GPIO_BIT_2\n  *         @arg @ref LL_PWR_GPIO_BIT_3\n  *         @arg @ref LL_PWR_GPIO_BIT_4\n  *         @arg @ref LL_PWR_GPIO_BIT_5\n  *         @arg @ref LL_PWR_GPIO_BIT_6\n  *         @arg @ref LL_PWR_GPIO_BIT_7\n  *         @arg @ref LL_PWR_GPIO_BIT_8\n  *         @arg @ref LL_PWR_GPIO_BIT_9\n  *         @arg @ref LL_PWR_GPIO_BIT_10\n  *         @arg @ref LL_PWR_GPIO_BIT_11\n  *         @arg @ref LL_PWR_GPIO_BIT_12\n  *         @arg @ref LL_PWR_GPIO_BIT_13\n  *         @arg @ref LL_PWR_GPIO_BIT_14\n  *         @arg @ref LL_PWR_GPIO_BIT_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\n{\n  SET_BIT(*((uint32_t *)GPIO), GPIONumber);\n}\n\n/**\n  * @brief  Disable GPIO pull-up state in Standby and Shutdown modes\n  * @rmtoll PUCRA        PU0-15        LL_PWR_DisableGPIOPullUp\\n\n  *         PUCRB        PU0-15        LL_PWR_DisableGPIOPullUp\\n\n  *         PUCRC        PU0-15        LL_PWR_DisableGPIOPullUp\\n\n  *         PUCRD        PU0-15        LL_PWR_DisableGPIOPullUp\\n\n  *         PUCRE        PU0-15        LL_PWR_DisableGPIOPullUp\\n\n  *         PUCRF        PU0-15        LL_PWR_DisableGPIOPullUp\\n\n  *         PUCRG        PU0-15        LL_PWR_DisableGPIOPullUp\\n\n  *         PUCRH        PU0-15        LL_PWR_DisableGPIOPullUp\\n\n  *         PUCRI        PU0-11        LL_PWR_DisableGPIOPullUp\n  * @param  GPIO This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_A\n  *         @arg @ref LL_PWR_GPIO_B\n  *         @arg @ref LL_PWR_GPIO_C\n  *         @arg @ref LL_PWR_GPIO_D\n  *         @arg @ref LL_PWR_GPIO_E\n  *         @arg @ref LL_PWR_GPIO_F (*)\n  *         @arg @ref LL_PWR_GPIO_G (*)\n  *         @arg @ref LL_PWR_GPIO_H\n  *         @arg @ref LL_PWR_GPIO_I (*)\n  *\n  *         (*) value not defined in all devices\n  * @param  GPIONumber This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_BIT_0\n  *         @arg @ref LL_PWR_GPIO_BIT_1\n  *         @arg @ref LL_PWR_GPIO_BIT_2\n  *         @arg @ref LL_PWR_GPIO_BIT_3\n  *         @arg @ref LL_PWR_GPIO_BIT_4\n  *         @arg @ref LL_PWR_GPIO_BIT_5\n  *         @arg @ref LL_PWR_GPIO_BIT_6\n  *         @arg @ref LL_PWR_GPIO_BIT_7\n  *         @arg @ref LL_PWR_GPIO_BIT_8\n  *         @arg @ref LL_PWR_GPIO_BIT_9\n  *         @arg @ref LL_PWR_GPIO_BIT_10\n  *         @arg @ref LL_PWR_GPIO_BIT_11\n  *         @arg @ref LL_PWR_GPIO_BIT_12\n  *         @arg @ref LL_PWR_GPIO_BIT_13\n  *         @arg @ref LL_PWR_GPIO_BIT_14\n  *         @arg @ref LL_PWR_GPIO_BIT_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\n{\n  CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber);\n}\n\n/**\n  * @brief  Check if GPIO pull-up state is enabled\n  * @rmtoll PUCRA        PU0-15        LL_PWR_IsEnabledGPIOPullUp\\n\n  *         PUCRB        PU0-15        LL_PWR_IsEnabledGPIOPullUp\\n\n  *         PUCRC        PU0-15        LL_PWR_IsEnabledGPIOPullUp\\n\n  *         PUCRD        PU0-15        LL_PWR_IsEnabledGPIOPullUp\\n\n  *         PUCRE        PU0-15        LL_PWR_IsEnabledGPIOPullUp\\n\n  *         PUCRF        PU0-15        LL_PWR_IsEnabledGPIOPullUp\\n\n  *         PUCRG        PU0-15        LL_PWR_IsEnabledGPIOPullUp\\n\n  *         PUCRH        PU0-15        LL_PWR_IsEnabledGPIOPullUp\\n\n  *         PUCRI        PU0-11        LL_PWR_IsEnabledGPIOPullUp\n  * @param  GPIO This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_A\n  *         @arg @ref LL_PWR_GPIO_B\n  *         @arg @ref LL_PWR_GPIO_C\n  *         @arg @ref LL_PWR_GPIO_D\n  *         @arg @ref LL_PWR_GPIO_E\n  *         @arg @ref LL_PWR_GPIO_F (*)\n  *         @arg @ref LL_PWR_GPIO_G (*)\n  *         @arg @ref LL_PWR_GPIO_H\n  *         @arg @ref LL_PWR_GPIO_I (*)\n  *\n  *         (*) value not defined in all devices\n  * @param  GPIONumber This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_BIT_0\n  *         @arg @ref LL_PWR_GPIO_BIT_1\n  *         @arg @ref LL_PWR_GPIO_BIT_2\n  *         @arg @ref LL_PWR_GPIO_BIT_3\n  *         @arg @ref LL_PWR_GPIO_BIT_4\n  *         @arg @ref LL_PWR_GPIO_BIT_5\n  *         @arg @ref LL_PWR_GPIO_BIT_6\n  *         @arg @ref LL_PWR_GPIO_BIT_7\n  *         @arg @ref LL_PWR_GPIO_BIT_8\n  *         @arg @ref LL_PWR_GPIO_BIT_9\n  *         @arg @ref LL_PWR_GPIO_BIT_10\n  *         @arg @ref LL_PWR_GPIO_BIT_11\n  *         @arg @ref LL_PWR_GPIO_BIT_12\n  *         @arg @ref LL_PWR_GPIO_BIT_13\n  *         @arg @ref LL_PWR_GPIO_BIT_14\n  *         @arg @ref LL_PWR_GPIO_BIT_15\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)\n{\n  return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber));\n}\n\n/**\n  * @brief  Enable GPIO pull-down state in Standby and Shutdown modes\n  * @rmtoll PDCRA        PD0-15        LL_PWR_EnableGPIOPullDown\\n\n  *         PDCRB        PD0-15        LL_PWR_EnableGPIOPullDown\\n\n  *         PDCRC        PD0-15        LL_PWR_EnableGPIOPullDown\\n\n  *         PDCRD        PD0-15        LL_PWR_EnableGPIOPullDown\\n\n  *         PDCRE        PD0-15        LL_PWR_EnableGPIOPullDown\\n\n  *         PDCRF        PD0-15        LL_PWR_EnableGPIOPullDown\\n\n  *         PDCRG        PD0-15        LL_PWR_EnableGPIOPullDown\\n\n  *         PDCRH        PD0-15        LL_PWR_EnableGPIOPullDown\\n\n  *         PDCRI        PD0-11        LL_PWR_EnableGPIOPullDown\n  * @param  GPIO This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_A\n  *         @arg @ref LL_PWR_GPIO_B\n  *         @arg @ref LL_PWR_GPIO_C\n  *         @arg @ref LL_PWR_GPIO_D\n  *         @arg @ref LL_PWR_GPIO_E\n  *         @arg @ref LL_PWR_GPIO_F (*)\n  *         @arg @ref LL_PWR_GPIO_G (*)\n  *         @arg @ref LL_PWR_GPIO_H\n  *         @arg @ref LL_PWR_GPIO_I (*)\n  *\n  *         (*) value not defined in all devices\n  * @param  GPIONumber This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_BIT_0\n  *         @arg @ref LL_PWR_GPIO_BIT_1\n  *         @arg @ref LL_PWR_GPIO_BIT_2\n  *         @arg @ref LL_PWR_GPIO_BIT_3\n  *         @arg @ref LL_PWR_GPIO_BIT_4\n  *         @arg @ref LL_PWR_GPIO_BIT_5\n  *         @arg @ref LL_PWR_GPIO_BIT_6\n  *         @arg @ref LL_PWR_GPIO_BIT_7\n  *         @arg @ref LL_PWR_GPIO_BIT_8\n  *         @arg @ref LL_PWR_GPIO_BIT_9\n  *         @arg @ref LL_PWR_GPIO_BIT_10\n  *         @arg @ref LL_PWR_GPIO_BIT_11\n  *         @arg @ref LL_PWR_GPIO_BIT_12\n  *         @arg @ref LL_PWR_GPIO_BIT_13\n  *         @arg @ref LL_PWR_GPIO_BIT_14\n  *         @arg @ref LL_PWR_GPIO_BIT_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\n{\n  register uint32_t temp = (uint32_t)(GPIO) + 4;\n  SET_BIT(*((uint32_t *)(temp)), GPIONumber);\n}\n\n/**\n  * @brief  Disable GPIO pull-down state in Standby and Shutdown modes\n  * @rmtoll PDCRA        PD0-15        LL_PWR_DisableGPIOPullDown\\n\n  *         PDCRB        PD0-15        LL_PWR_DisableGPIOPullDown\\n\n  *         PDCRC        PD0-15        LL_PWR_DisableGPIOPullDown\\n\n  *         PDCRD        PD0-15        LL_PWR_DisableGPIOPullDown\\n\n  *         PDCRE        PD0-15        LL_PWR_DisableGPIOPullDown\\n\n  *         PDCRF        PD0-15        LL_PWR_DisableGPIOPullDown\\n\n  *         PDCRG        PD0-15        LL_PWR_DisableGPIOPullDown\\n\n  *         PDCRH        PD0-15        LL_PWR_DisableGPIOPullDown\\n\n  *         PDCRI        PD0-11        LL_PWR_DisableGPIOPullDown\n  * @param  GPIO This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_A\n  *         @arg @ref LL_PWR_GPIO_B\n  *         @arg @ref LL_PWR_GPIO_C\n  *         @arg @ref LL_PWR_GPIO_D\n  *         @arg @ref LL_PWR_GPIO_E\n  *         @arg @ref LL_PWR_GPIO_F (*)\n  *         @arg @ref LL_PWR_GPIO_G (*)\n  *         @arg @ref LL_PWR_GPIO_H\n  *         @arg @ref LL_PWR_GPIO_I (*)\n  *\n  *         (*) value not defined in all devices\n  * @param  GPIONumber This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_BIT_0\n  *         @arg @ref LL_PWR_GPIO_BIT_1\n  *         @arg @ref LL_PWR_GPIO_BIT_2\n  *         @arg @ref LL_PWR_GPIO_BIT_3\n  *         @arg @ref LL_PWR_GPIO_BIT_4\n  *         @arg @ref LL_PWR_GPIO_BIT_5\n  *         @arg @ref LL_PWR_GPIO_BIT_6\n  *         @arg @ref LL_PWR_GPIO_BIT_7\n  *         @arg @ref LL_PWR_GPIO_BIT_8\n  *         @arg @ref LL_PWR_GPIO_BIT_9\n  *         @arg @ref LL_PWR_GPIO_BIT_10\n  *         @arg @ref LL_PWR_GPIO_BIT_11\n  *         @arg @ref LL_PWR_GPIO_BIT_12\n  *         @arg @ref LL_PWR_GPIO_BIT_13\n  *         @arg @ref LL_PWR_GPIO_BIT_14\n  *         @arg @ref LL_PWR_GPIO_BIT_15\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\n{\n  register uint32_t temp = (uint32_t)(GPIO) + 4;\n  CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber);\n}\n\n/**\n  * @brief  Check if GPIO pull-down state is enabled\n  * @rmtoll PDCRA        PD0-15        LL_PWR_IsEnabledGPIOPullDown\\n\n  *         PDCRB        PD0-15        LL_PWR_IsEnabledGPIOPullDown\\n\n  *         PDCRC        PD0-15        LL_PWR_IsEnabledGPIOPullDown\\n\n  *         PDCRD        PD0-15        LL_PWR_IsEnabledGPIOPullDown\\n\n  *         PDCRE        PD0-15        LL_PWR_IsEnabledGPIOPullDown\\n\n  *         PDCRF        PD0-15        LL_PWR_IsEnabledGPIOPullDown\\n\n  *         PDCRG        PD0-15        LL_PWR_IsEnabledGPIOPullDown\\n\n  *         PDCRH        PD0-15        LL_PWR_IsEnabledGPIOPullDown\\n\n  *         PDCRI        PD0-11        LL_PWR_IsEnabledGPIOPullDown\n  * @param  GPIO This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_A\n  *         @arg @ref LL_PWR_GPIO_B\n  *         @arg @ref LL_PWR_GPIO_C\n  *         @arg @ref LL_PWR_GPIO_D\n  *         @arg @ref LL_PWR_GPIO_E\n  *         @arg @ref LL_PWR_GPIO_F (*)\n  *         @arg @ref LL_PWR_GPIO_G (*)\n  *         @arg @ref LL_PWR_GPIO_H\n  *         @arg @ref LL_PWR_GPIO_I (*)\n  *\n  *         (*) value not defined in all devices\n  * @param  GPIONumber This parameter can be one of the following values:\n  *         @arg @ref LL_PWR_GPIO_BIT_0\n  *         @arg @ref LL_PWR_GPIO_BIT_1\n  *         @arg @ref LL_PWR_GPIO_BIT_2\n  *         @arg @ref LL_PWR_GPIO_BIT_3\n  *         @arg @ref LL_PWR_GPIO_BIT_4\n  *         @arg @ref LL_PWR_GPIO_BIT_5\n  *         @arg @ref LL_PWR_GPIO_BIT_6\n  *         @arg @ref LL_PWR_GPIO_BIT_7\n  *         @arg @ref LL_PWR_GPIO_BIT_8\n  *         @arg @ref LL_PWR_GPIO_BIT_9\n  *         @arg @ref LL_PWR_GPIO_BIT_10\n  *         @arg @ref LL_PWR_GPIO_BIT_11\n  *         @arg @ref LL_PWR_GPIO_BIT_12\n  *         @arg @ref LL_PWR_GPIO_BIT_13\n  *         @arg @ref LL_PWR_GPIO_BIT_14\n  *         @arg @ref LL_PWR_GPIO_BIT_15\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)\n{\n  register uint32_t temp = (uint32_t)(GPIO) + 4;\n  return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Get Internal Wake-up line Flag\n  * @rmtoll SR1          WUFI          LL_PWR_IsActiveFlag_InternWU\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)\n{\n  return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI));\n}\n\n#if defined(PWR_SR1_EXT_SMPS_RDY)\n/**\n  * @brief  Get Ready Flag for switching to external SMPS\n  * @rmtoll SR1          EXT_SMPS_RDY  LL_PWR_IsActiveFlag_ExtSMPSReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ExtSMPSReady(void)\n{\n  return (READ_BIT(PWR->SR1, PWR_SR1_EXT_SMPS_RDY) == (PWR_SR1_EXT_SMPS_RDY));\n}\n#endif /* PWR_SR1_EXT_SMPS_RDY */\n\n/**\n  * @brief  Get Stand-By Flag\n  * @rmtoll SR1          SBF           LL_PWR_IsActiveFlag_SB\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)\n{\n  return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF));\n}\n\n/**\n  * @brief  Get Wake-up Flag 5\n  * @rmtoll SR1          WUF5          LL_PWR_IsActiveFlag_WU5\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)\n{\n  return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5));\n}\n\n/**\n  * @brief  Get Wake-up Flag 4\n  * @rmtoll SR1          WUF4          LL_PWR_IsActiveFlag_WU4\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)\n{\n  return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4));\n}\n\n/**\n  * @brief  Get Wake-up Flag 3\n  * @rmtoll SR1          WUF3          LL_PWR_IsActiveFlag_WU3\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)\n{\n  return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3));\n}\n\n/**\n  * @brief  Get Wake-up Flag 2\n  * @rmtoll SR1          WUF2          LL_PWR_IsActiveFlag_WU2\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)\n{\n  return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2));\n}\n\n/**\n  * @brief  Get Wake-up Flag 1\n  * @rmtoll SR1          WUF1          LL_PWR_IsActiveFlag_WU1\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)\n{\n  return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1));\n}\n\n/**\n  * @brief  Clear Stand-By Flag\n  * @rmtoll SCR          CSBF          LL_PWR_ClearFlag_SB\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)\n{\n  WRITE_REG(PWR->SCR, PWR_SCR_CSBF);\n}\n\n/**\n  * @brief  Clear Wake-up Flags\n  * @rmtoll SCR          CWUF          LL_PWR_ClearFlag_WU\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)\n{\n  WRITE_REG(PWR->SCR, PWR_SCR_CWUF);\n}\n\n/**\n  * @brief  Clear Wake-up Flag 5\n  * @rmtoll SCR          CWUF5         LL_PWR_ClearFlag_WU5\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)\n{\n  WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);\n}\n\n/**\n  * @brief  Clear Wake-up Flag 4\n  * @rmtoll SCR          CWUF4         LL_PWR_ClearFlag_WU4\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)\n{\n  WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);\n}\n\n/**\n  * @brief  Clear Wake-up Flag 3\n  * @rmtoll SCR          CWUF3         LL_PWR_ClearFlag_WU3\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)\n{\n  WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);\n}\n\n/**\n  * @brief  Clear Wake-up Flag 2\n  * @rmtoll SCR          CWUF2         LL_PWR_ClearFlag_WU2\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)\n{\n  WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);\n}\n\n/**\n  * @brief  Clear Wake-up Flag 1\n  * @rmtoll SCR          CWUF1         LL_PWR_ClearFlag_WU1\n  * @retval None\n  */\n__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)\n{\n  WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);\n}\n\n/**\n  * @brief  Indicate whether VDDA voltage is below or above PVM4 threshold\n  * @rmtoll SR2          PVMO4         LL_PWR_IsActiveFlag_PVMO4\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)\n{\n  return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4));\n}\n\n/**\n  * @brief  Indicate whether VDDA voltage is below or above PVM3 threshold\n  * @rmtoll SR2          PVMO3         LL_PWR_IsActiveFlag_PVMO3\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)\n{\n  return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3));\n}\n\n#if defined(PWR_SR2_PVMO2)\n/**\n  * @brief  Indicate whether VDDIO2 voltage is below or above PVM2 threshold\n  * @rmtoll SR2          PVMO2         LL_PWR_IsActiveFlag_PVMO2\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)\n{\n  return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2));\n}\n#endif /* PWR_SR2_PVMO2 */\n\n#if defined(PWR_SR2_PVMO1)\n/**\n  * @brief  Indicate whether VDDUSB voltage is below or above PVM1 threshold\n  * @rmtoll SR2          PVMO1         LL_PWR_IsActiveFlag_PVMO1\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)\n{\n  return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1));\n}\n#endif /* PWR_SR2_PVMO1 */\n\n/**\n  * @brief  Indicate whether VDD voltage is below or above the selected PVD threshold\n  * @rmtoll SR2          PVDO          LL_PWR_IsActiveFlag_PVDO\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)\n{\n  return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO));\n}\n\n/**\n  * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level\n  * @rmtoll SR2          VOSF          LL_PWR_IsActiveFlag_VOS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)\n{\n  return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF));\n}\n\n/**\n  * @brief  Indicate whether the regulator is ready in main mode or is in low-power mode\n  * @note   Take care, return value \"0\" means the regulator is ready. Return value \"1\" means the output voltage range is still changing.\n  * @rmtoll SR2          REGLPF        LL_PWR_IsActiveFlag_REGLPF\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)\n{\n  return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF));\n}\n\n/**\n  * @brief  Indicate whether or not the low-power regulator is ready\n  * @rmtoll SR2          REGLPS        LL_PWR_IsActiveFlag_REGLPS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)\n{\n  return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS));\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup PWR_LL_EF_Init De-initialization function\n  * @{\n  */\nErrorStatus LL_PWR_DeInit(void);\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name\n  * @{\n  */\n/* Old functions name kept for legacy purpose, to be replaced by the          */\n/* current functions name.                                                    */\n#define LL_PWR_IsActiveFlag_VOSF  LL_PWR_IsActiveFlag_VOS\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(PWR) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_PWR_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_rcc.h\n  * @author  MCD Application Team\n  * @brief   Header file of RCC LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_RCC_H\n#define __STM32L4xx_LL_RCC_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @defgroup RCC_LL RCC\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup RCC_LL_Private_Variables RCC Private Variables\n  * @{\n  */\n\n#if defined(RCC_CCIPR2_PLLSAI2DIVR)\nstatic const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16};\n#endif /* RCC_CCIPR2_PLLSAI2DIVR */\n\n/**\n  * @}\n  */\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup RCC_LL_Private_Constants RCC Private Constants\n  * @{\n  */\n/* Defines used to perform offsets*/\n/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */\n#define RCC_OFFSET_CCIPR        0U\n#define RCC_OFFSET_CCIPR2       0x14U\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_Private_Macros RCC Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_Exported_Types RCC Exported Types\n  * @{\n  */\n\n/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure\n  * @{\n  */\n\n/**\n  * @brief  RCC Clocks Frequency Structure\n  */\ntypedef struct\n{\n  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */\n  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */\n  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */\n  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */\n} LL_RCC_ClocksTypeDef;\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants\n  * @{\n  */\n\n/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation\n  * @brief    Defines used to adapt values of different oscillators\n  * @note     These values could be modified in the user environment according to\n  *           HW set-up.\n  * @{\n  */\n#if !defined  (HSE_VALUE)\n#define HSE_VALUE    8000000U   /*!< Value of the HSE oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSI_VALUE)\n#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */\n#endif /* HSI_VALUE */\n\n#if !defined  (LSE_VALUE)\n#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */\n#endif /* LSE_VALUE */\n\n#if !defined  (LSI_VALUE)\n#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */\n#endif /* LSI_VALUE */\n#if defined(RCC_HSI48_SUPPORT)\n\n#if !defined  (HSI48_VALUE)\n#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */\n#endif /* HSI48_VALUE */\n#endif /* RCC_HSI48_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_RCC_WriteReg function\n  * @{\n  */\n#define LL_RCC_CICR_LSIRDYC                RCC_CICR_LSIRDYC     /*!< LSI Ready Interrupt Clear */\n#define LL_RCC_CICR_LSERDYC                RCC_CICR_LSERDYC     /*!< LSE Ready Interrupt Clear */\n#define LL_RCC_CICR_MSIRDYC                RCC_CICR_MSIRDYC     /*!< MSI Ready Interrupt Clear */\n#define LL_RCC_CICR_HSIRDYC                RCC_CICR_HSIRDYC     /*!< HSI Ready Interrupt Clear */\n#define LL_RCC_CICR_HSERDYC                RCC_CICR_HSERDYC     /*!< HSE Ready Interrupt Clear */\n#define LL_RCC_CICR_PLLRDYC                RCC_CICR_PLLRDYC     /*!< PLL Ready Interrupt Clear */\n#if defined(RCC_HSI48_SUPPORT)\n#define LL_RCC_CICR_HSI48RDYC              RCC_CICR_HSI48RDYC   /*!< HSI48 Ready Interrupt Clear */\n#endif /* RCC_HSI48_SUPPORT */\n#if defined(RCC_PLLSAI1_SUPPORT)\n#define LL_RCC_CICR_PLLSAI1RDYC            RCC_CICR_PLLSAI1RDYC /*!< PLLSAI1 Ready Interrupt Clear */\n#endif /* RCC_PLLSAI1_SUPPORT */\n#if defined(RCC_PLLSAI2_SUPPORT)\n#define LL_RCC_CICR_PLLSAI2RDYC            RCC_CICR_PLLSAI2RDYC /*!< PLLSAI2 Ready Interrupt Clear */\n#endif /* RCC_PLLSAI2_SUPPORT */\n#define LL_RCC_CICR_LSECSSC                RCC_CICR_LSECSSC     /*!< LSE Clock Security System Interrupt Clear */\n#define LL_RCC_CICR_CSSC                   RCC_CICR_CSSC        /*!< Clock Security System Interrupt Clear */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_RCC_ReadReg function\n  * @{\n  */\n#define LL_RCC_CIFR_LSIRDYF                RCC_CIFR_LSIRDYF     /*!< LSI Ready Interrupt flag */\n#define LL_RCC_CIFR_LSERDYF                RCC_CIFR_LSERDYF     /*!< LSE Ready Interrupt flag */\n#define LL_RCC_CIFR_MSIRDYF                RCC_CIFR_MSIRDYF     /*!< MSI Ready Interrupt flag */\n#define LL_RCC_CIFR_HSIRDYF                RCC_CIFR_HSIRDYF     /*!< HSI Ready Interrupt flag */\n#define LL_RCC_CIFR_HSERDYF                RCC_CIFR_HSERDYF     /*!< HSE Ready Interrupt flag */\n#define LL_RCC_CIFR_PLLRDYF                RCC_CIFR_PLLRDYF     /*!< PLL Ready Interrupt flag */\n#if defined(RCC_HSI48_SUPPORT)\n#define LL_RCC_CIFR_HSI48RDYF              RCC_CIFR_HSI48RDYF   /*!< HSI48 Ready Interrupt flag */\n#endif /* RCC_HSI48_SUPPORT */\n#if defined(RCC_PLLSAI1_SUPPORT)\n#define LL_RCC_CIFR_PLLSAI1RDYF            RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */\n#endif /* RCC_PLLSAI1_SUPPORT */\n#if defined(RCC_PLLSAI2_SUPPORT)\n#define LL_RCC_CIFR_PLLSAI2RDYF            RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */\n#endif /* RCC_PLLSAI2_SUPPORT */\n#define LL_RCC_CIFR_LSECSSF                RCC_CIFR_LSECSSF     /*!< LSE Clock Security System Interrupt flag */\n#define LL_RCC_CIFR_CSSF                   RCC_CIFR_CSSF        /*!< Clock Security System Interrupt flag */\n#define LL_RCC_CSR_FWRSTF                  RCC_CSR_FWRSTF     /*!< Firewall reset flag */\n#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */\n#define LL_RCC_CSR_OBLRSTF                 RCC_CSR_OBLRSTF    /*!< OBL reset flag */\n#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */\n#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */\n#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */\n#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */\n#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions\n  * @{\n  */\n#define LL_RCC_CIER_LSIRDYIE               RCC_CIER_LSIRDYIE      /*!< LSI Ready Interrupt Enable */\n#define LL_RCC_CIER_LSERDYIE               RCC_CIER_LSERDYIE      /*!< LSE Ready Interrupt Enable */\n#define LL_RCC_CIER_MSIRDYIE               RCC_CIER_MSIRDYIE      /*!< MSI Ready Interrupt Enable */\n#define LL_RCC_CIER_HSIRDYIE               RCC_CIER_HSIRDYIE      /*!< HSI Ready Interrupt Enable */\n#define LL_RCC_CIER_HSERDYIE               RCC_CIER_HSERDYIE      /*!< HSE Ready Interrupt Enable */\n#define LL_RCC_CIER_PLLRDYIE               RCC_CIER_PLLRDYIE      /*!< PLL Ready Interrupt Enable */\n#if defined(RCC_HSI48_SUPPORT)\n#define LL_RCC_CIER_HSI48RDYIE             RCC_CIER_HSI48RDYIE    /*!< HSI48 Ready Interrupt Enable */\n#endif /* RCC_HSI48_SUPPORT */\n#if defined(RCC_PLLSAI1_SUPPORT)\n#define LL_RCC_CIER_PLLSAI1RDYIE           RCC_CIER_PLLSAI1RDYIE  /*!< PLLSAI1 Ready Interrupt Enable */\n#endif /* RCC_PLLSAI2_SUPPORT */\n#if defined(RCC_PLLSAI2_SUPPORT)\n#define LL_RCC_CIER_PLLSAI2RDYIE           RCC_CIER_PLLSAI2RDYIE  /*!< PLLSAI2 Ready Interrupt Enable */\n#endif /* RCC_PLLSAI2_SUPPORT */\n#define LL_RCC_CIER_LSECSSIE               RCC_CIER_LSECSSIE      /*!< LSE CSS Interrupt Enable */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability\n  * @{\n  */\n#define LL_RCC_LSEDRIVE_LOW                0x00000000U             /*!< Xtal mode lower driving capability */\n#define LL_RCC_LSEDRIVE_MEDIUMLOW          RCC_BDCR_LSEDRV_0       /*!< Xtal mode medium low driving capability */\n#define LL_RCC_LSEDRIVE_MEDIUMHIGH         RCC_BDCR_LSEDRV_1       /*!< Xtal mode medium high driving capability */\n#define LL_RCC_LSEDRIVE_HIGH               RCC_BDCR_LSEDRV         /*!< Xtal mode higher driving capability */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_MSIRANGE  MSI clock ranges\n  * @{\n  */\n#define LL_RCC_MSIRANGE_0                  RCC_CR_MSIRANGE_0  /*!< MSI = 100 KHz  */\n#define LL_RCC_MSIRANGE_1                  RCC_CR_MSIRANGE_1  /*!< MSI = 200 KHz  */\n#define LL_RCC_MSIRANGE_2                  RCC_CR_MSIRANGE_2  /*!< MSI = 400 KHz  */\n#define LL_RCC_MSIRANGE_3                  RCC_CR_MSIRANGE_3  /*!< MSI = 800 KHz  */\n#define LL_RCC_MSIRANGE_4                  RCC_CR_MSIRANGE_4  /*!< MSI = 1 MHz    */\n#define LL_RCC_MSIRANGE_5                  RCC_CR_MSIRANGE_5  /*!< MSI = 2 MHz    */\n#define LL_RCC_MSIRANGE_6                  RCC_CR_MSIRANGE_6  /*!< MSI = 4 MHz    */\n#define LL_RCC_MSIRANGE_7                  RCC_CR_MSIRANGE_7  /*!< MSI = 8 MHz    */\n#define LL_RCC_MSIRANGE_8                  RCC_CR_MSIRANGE_8  /*!< MSI = 16 MHz   */\n#define LL_RCC_MSIRANGE_9                  RCC_CR_MSIRANGE_9  /*!< MSI = 24 MHz   */\n#define LL_RCC_MSIRANGE_10                 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz   */\n#define LL_RCC_MSIRANGE_11                 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz   */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_MSISRANGE  MSI range after Standby mode\n  * @{\n  */\n#define LL_RCC_MSISRANGE_4                 RCC_CSR_MSISRANGE_1  /*!< MSI = 1 MHz    */\n#define LL_RCC_MSISRANGE_5                 RCC_CSR_MSISRANGE_2  /*!< MSI = 2 MHz    */\n#define LL_RCC_MSISRANGE_6                 RCC_CSR_MSISRANGE_4  /*!< MSI = 4 MHz    */\n#define LL_RCC_MSISRANGE_7                 RCC_CSR_MSISRANGE_8  /*!< MSI = 8 MHz    */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE  LSCO Selection\n  * @{\n  */\n#define LL_RCC_LSCO_CLKSOURCE_LSI          0x00000000U                 /*!< LSI selection for low speed clock  */\n#define LL_RCC_LSCO_CLKSOURCE_LSE          RCC_BDCR_LSCOSEL      /*!< LSE selection for low speed clock  */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch\n  * @{\n  */\n#define LL_RCC_SYS_CLKSOURCE_MSI           RCC_CFGR_SW_MSI    /*!< MSI selection as system clock */\n#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */\n#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */\n#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status\n  * @{\n  */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI    RCC_CFGR_SWS_MSI   /*!< MSI used as system clock */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */\n#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler\n  * @{\n  */\n#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */\n#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */\n#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */\n#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */\n#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */\n#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */\n#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */\n#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */\n#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)\n  * @{\n  */\n#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */\n#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */\n#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */\n#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */\n#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)\n  * @{\n  */\n#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */\n#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */\n#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */\n#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */\n#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK  Wakeup from Stop and CSS backup clock selection\n  * @{\n  */\n#define LL_RCC_STOP_WAKEUPCLOCK_MSI        0x00000000U             /*!< MSI selection after wake-up from STOP */\n#define LL_RCC_STOP_WAKEUPCLOCK_HSI        RCC_CFGR_STOPWUCK       /*!< HSI selection after wake-up from STOP */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_MCO1SOURCE  MCO1 SOURCE selection\n  * @{\n  */\n#define LL_RCC_MCO1SOURCE_NOCLOCK          0x00000000U                            /*!< MCO output disabled, no clock on MCO */\n#define LL_RCC_MCO1SOURCE_SYSCLK           RCC_CFGR_MCOSEL_0                      /*!< SYSCLK selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_MSI              RCC_CFGR_MCOSEL_1                      /*!< MSI selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_HSI              (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_HSE              RCC_CFGR_MCOSEL_2                      /*!< HSE selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_PLLCLK           (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2)  /*!< Main PLL selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_LSI              (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2)  /*!< LSI selection as MCO1 source */\n#define LL_RCC_MCO1SOURCE_LSE              (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */\n#if defined(RCC_HSI48_SUPPORT)\n#define LL_RCC_MCO1SOURCE_HSI48            RCC_CFGR_MCOSEL_3                      /*!< HSI48 selection as MCO1 source */\n#endif /* RCC_HSI48_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler\n  * @{\n  */\n#define LL_RCC_MCO1_DIV_1                  RCC_CFGR_MCOPRE_DIV1       /*!< MCO not divided */\n#define LL_RCC_MCO1_DIV_2                  RCC_CFGR_MCOPRE_DIV2       /*!< MCO divided by 2 */\n#define LL_RCC_MCO1_DIV_4                  RCC_CFGR_MCOPRE_DIV4       /*!< MCO divided by 4 */\n#define LL_RCC_MCO1_DIV_8                  RCC_CFGR_MCOPRE_DIV8       /*!< MCO divided by 8 */\n#define LL_RCC_MCO1_DIV_16                 RCC_CFGR_MCOPRE_DIV16      /*!< MCO divided by 16 */\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency\n  * @{\n  */\n#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */\n#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/** @defgroup RCC_LL_EC_USART1_CLKSOURCE  Peripheral USART clock source selection\n  * @{\n  */\n#define LL_RCC_USART1_CLKSOURCE_PCLK2      (RCC_CCIPR_USART1SEL << 16U)                           /*!< PCLK2 clock used as USART1 clock source */\n#define LL_RCC_USART1_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */\n#define LL_RCC_USART1_CLKSOURCE_HSI        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */\n#define LL_RCC_USART1_CLKSOURCE_LSE        ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL)   /*!< LSE clock used as USART1 clock source */\n#define LL_RCC_USART2_CLKSOURCE_PCLK1      (RCC_CCIPR_USART2SEL << 16U)                           /*!< PCLK1 clock used as USART2 clock source */\n#define LL_RCC_USART2_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */\n#define LL_RCC_USART2_CLKSOURCE_HSI        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */\n#define LL_RCC_USART2_CLKSOURCE_LSE        ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL)   /*!< LSE clock used as USART2 clock source */\n#if defined(RCC_CCIPR_USART3SEL)\n#define LL_RCC_USART3_CLKSOURCE_PCLK1      (RCC_CCIPR_USART3SEL << 16U)                           /*!< PCLK1 clock used as USART3 clock source */\n#define LL_RCC_USART3_CLKSOURCE_SYSCLK     ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */\n#define LL_RCC_USART3_CLKSOURCE_HSI        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */\n#define LL_RCC_USART3_CLKSOURCE_LSE        ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL)   /*!< LSE clock used as USART3 clock source */\n#endif /* RCC_CCIPR_USART3SEL */\n/**\n  * @}\n  */\n\n#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)\n/** @defgroup RCC_LL_EC_UART4_CLKSOURCE  Peripheral UART clock source selection\n  * @{\n  */\n#if defined(RCC_CCIPR_UART4SEL)\n#define LL_RCC_UART4_CLKSOURCE_PCLK1       (RCC_CCIPR_UART4SEL << 16U)                           /*!< PCLK1 clock used as UART4 clock source */\n#define LL_RCC_UART4_CLKSOURCE_SYSCLK      ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0)  /*!< SYSCLK clock used as UART4 clock source */\n#define LL_RCC_UART4_CLKSOURCE_HSI         ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1)  /*!< HSI clock used as UART4 clock source */\n#define LL_RCC_UART4_CLKSOURCE_LSE         ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL)    /*!< LSE clock used as UART4 clock source */\n#endif /* RCC_CCIPR_UART4SEL */\n#if defined(RCC_CCIPR_UART5SEL)\n#define LL_RCC_UART5_CLKSOURCE_PCLK1       (RCC_CCIPR_UART5SEL << 16U)                           /*!< PCLK1 clock used as UART5 clock source */\n#define LL_RCC_UART5_CLKSOURCE_SYSCLK      ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0)  /*!< SYSCLK clock used as UART5 clock source */\n#define LL_RCC_UART5_CLKSOURCE_HSI         ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1)  /*!< HSI clock used as UART5 clock source */\n#define LL_RCC_UART5_CLKSOURCE_LSE         ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL)    /*!< LSE clock used as UART5 clock source */\n#endif /* RCC_CCIPR_UART5SEL */\n/**\n  * @}\n  */\n#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */\n\n/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE  Peripheral LPUART clock source selection\n  * @{\n  */\n#define LL_RCC_LPUART1_CLKSOURCE_PCLK1     0x00000000U                     /*!< PCLK1 clock used as LPUART1 clock source */\n#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK    RCC_CCIPR_LPUART1SEL_0          /*!< SYSCLK clock used as LPUART1 clock source */\n#define LL_RCC_LPUART1_CLKSOURCE_HSI       RCC_CCIPR_LPUART1SEL_1          /*!< HSI clock used as LPUART1 clock source */\n#define LL_RCC_LPUART1_CLKSOURCE_LSE       RCC_CCIPR_LPUART1SEL            /*!< LSE clock used as LPUART1 clock source */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE  Peripheral I2C clock source selection\n  * @{\n  */\n#define LL_RCC_I2C1_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U))                                                  /*!< PCLK1 clock used as I2C1 clock source */\n#define LL_RCC_I2C1_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */\n#define LL_RCC_I2C1_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */\n#if defined(RCC_CCIPR_I2C2SEL)\n#define LL_RCC_I2C2_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U))                                                  /*!< PCLK1 clock used as I2C2 clock source */\n#define LL_RCC_I2C2_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */\n#define LL_RCC_I2C2_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */\n#endif /* RCC_CCIPR_I2C2SEL */\n#define LL_RCC_I2C3_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U))                                                  /*!< PCLK1 clock used as I2C3 clock source */\n#define LL_RCC_I2C3_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */\n#define LL_RCC_I2C3_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */\n#if defined(RCC_CCIPR2_I2C4SEL)\n#define LL_RCC_I2C4_CLKSOURCE_PCLK1        ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U))                                                    /*!< PCLK1 clock used as I2C4 clock source */\n#define LL_RCC_I2C4_CLKSOURCE_SYSCLK       ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */\n#define LL_RCC_I2C4_CLKSOURCE_HSI          ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */\n#endif /* RCC_CCIPR2_I2C4SEL */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection\n  * @{\n  */\n#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1      RCC_CCIPR_LPTIM1SEL                                    /*!< PCLK1 clock used as LPTIM1 clock source */\n#define LL_RCC_LPTIM1_CLKSOURCE_LSI        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI clock used as LPTIM1 clock source */\n#define LL_RCC_LPTIM1_CLKSOURCE_HSI        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI clock used as LPTIM1 clock source */\n#define LL_RCC_LPTIM1_CLKSOURCE_LSE        (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U))   /*!< LSE clock used as LPTIM1 clock source */\n#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1      RCC_CCIPR_LPTIM2SEL                                    /*!< PCLK1 clock used as LPTIM2 clock source */\n#define LL_RCC_LPTIM2_CLKSOURCE_LSI        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI clock used as LPTIM2 clock source */\n#define LL_RCC_LPTIM2_CLKSOURCE_HSI        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI clock used as LPTIM2 clock source */\n#define LL_RCC_LPTIM2_CLKSOURCE_LSE        (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U))   /*!< LSE clock used as LPTIM2 clock source */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE  Peripheral SAI clock source selection\n  * @{\n  */\n#if defined(RCC_CCIPR2_SAI1SEL)\n#define LL_RCC_SAI1_CLKSOURCE_PLL          (RCC_CCIPR2_SAI1SEL << 16U)                          /*!< PLL clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1      ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLLSAI1 clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2      ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLLSAI2 clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_HSI          ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PIN          ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0))  /*!< External input clock used as SAI1 clock source */\n#elif defined(RCC_CCIPR_SAI1SEL)\n#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1      RCC_CCIPR_SAI1SEL                                    /*!< PLLSAI1 clock used as SAI1 clock source */\n#if defined(RCC_PLLSAI2_SUPPORT)\n#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2      (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_0 >> 16U))   /*!< PLLSAI2 clock used as SAI1 clock source */\n#endif /* RCC_PLLSAI2_SUPPORT */\n#define LL_RCC_SAI1_CLKSOURCE_PLL          (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL_1 >> 16U))   /*!< PLL clock used as SAI1 clock source */\n#define LL_RCC_SAI1_CLKSOURCE_PIN          (RCC_CCIPR_SAI1SEL | (RCC_CCIPR_SAI1SEL >> 16U))     /*!< External input clock used as SAI1 clock source */\n#endif /* RCC_CCIPR2_SAI1SEL */\n\n#if defined(RCC_CCIPR2_SAI2SEL)\n#define LL_RCC_SAI2_CLKSOURCE_PLL          (RCC_CCIPR2_SAI2SEL << 16U)                          /*!< PLL clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1      ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLLSAI1 clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2      ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLLSAI2 clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_HSI          ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PIN          ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0))  /*!< External input clock used as SAI2 clock source */\n#elif defined(RCC_CCIPR_SAI2SEL)\n#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1      RCC_CCIPR_SAI2SEL                                    /*!< PLLSAI1 clock used as SAI2 clock source */\n#if defined(RCC_PLLSAI2_SUPPORT)\n#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2      (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_0 >> 16U))   /*!< PLLSAI2 clock used as SAI2 clock source */\n#endif /* RCC_PLLSAI2_SUPPORT */\n#define LL_RCC_SAI2_CLKSOURCE_PLL          (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL_1 >> 16U))   /*!< PLL clock used as SAI2 clock source */\n#define LL_RCC_SAI2_CLKSOURCE_PIN          (RCC_CCIPR_SAI2SEL | (RCC_CCIPR_SAI2SEL >> 16U))     /*!< External input clock used as SAI2 clock source */\n#endif /* RCC_CCIPR2_SAI2SEL */\n/**\n  * @}\n  */\n\n#if defined(RCC_CCIPR2_SDMMCSEL)\n/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE  Peripheral SDMMC kernel clock source selection\n  * @{\n  */\n#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK  0x00000000U          /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */\n#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL    RCC_CCIPR2_SDMMCSEL  /*!< PLLSAI3CLK clock used as SDMMC1 clock source */\n/**\n  * @}\n  */\n#endif /* RCC_CCIPR2_SDMMCSEL */\n\n#if defined(SDMMC1)\n/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE  Peripheral SDMMC clock source selection\n  * @{\n  */\n#if defined(RCC_HSI48_SUPPORT)\n#define LL_RCC_SDMMC1_CLKSOURCE_HSI48      0x00000000U          /*!< HSI48 clock used as SDMMC1 clock source */\n#else\n#define LL_RCC_SDMMC1_CLKSOURCE_NONE       0x00000000U          /*!< No clock used as SDMMC1 clock source */\n#endif\n#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1    RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source */\n#define LL_RCC_SDMMC1_CLKSOURCE_PLL        RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as SDMMC1 clock source */\n#define LL_RCC_SDMMC1_CLKSOURCE_MSI        RCC_CCIPR_CLK48SEL   /*!< MSI clock used as SDMMC1 clock source */\n/**\n  * @}\n  */\n#endif /* SDMMC1 */\n\n/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection\n  * @{\n  */\n#if defined(RCC_HSI48_SUPPORT)\n#define LL_RCC_RNG_CLKSOURCE_HSI48         0x00000000U          /*!< HSI48 clock used as RNG clock source */\n#else\n#define LL_RCC_RNG_CLKSOURCE_NONE          0x00000000U          /*!< No clock used as RNG clock source */\n#endif\n#define LL_RCC_RNG_CLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as RNG clock source */\n#define LL_RCC_RNG_CLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */\n#define LL_RCC_RNG_CLKSOURCE_MSI           RCC_CCIPR_CLK48SEL   /*!< MSI clock used as RNG clock source */\n/**\n  * @}\n  */\n\n#if defined(USB_OTG_FS) || defined(USB)\n/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection\n  * @{\n  */\n#if defined(RCC_HSI48_SUPPORT)\n#define LL_RCC_USB_CLKSOURCE_HSI48         0x00000000U          /*!< HSI48 clock used as USB clock source */\n#else\n#define LL_RCC_USB_CLKSOURCE_NONE          0x00000000U          /*!< No clock used as USB clock source */\n#endif\n#define LL_RCC_USB_CLKSOURCE_PLLSAI1       RCC_CCIPR_CLK48SEL_0 /*!< PLLSAI1 clock used as USB clock source */\n#define LL_RCC_USB_CLKSOURCE_PLL           RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */\n#define LL_RCC_USB_CLKSOURCE_MSI           RCC_CCIPR_CLK48SEL   /*!< MSI clock used as USB clock source */\n/**\n  * @}\n  */\n\n#endif /* USB_OTG_FS || USB */\n\n/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection\n  * @{\n  */\n#define LL_RCC_ADC_CLKSOURCE_NONE          0x00000000U          /*!< No clock used as ADC clock source */\n#if defined(RCC_PLLSAI1_SUPPORT)\n#define LL_RCC_ADC_CLKSOURCE_PLLSAI1       RCC_CCIPR_ADCSEL_0   /*!< PLLSAI1 clock used as ADC clock source */\n#endif /* RCC_PLLSAI1_SUPPORT */\n#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)\n#define LL_RCC_ADC_CLKSOURCE_PLLSAI2       RCC_CCIPR_ADCSEL_1   /*!< PLLSAI2 clock used as ADC clock source */\n#endif /* RCC_PLLSAI2_SUPPORT */\n#if defined(RCC_CCIPR_ADCSEL)\n#define LL_RCC_ADC_CLKSOURCE_SYSCLK        RCC_CCIPR_ADCSEL     /*!< SYSCLK clock used as ADC clock source */\n#else\n#define LL_RCC_ADC_CLKSOURCE_SYSCLK        0x30000000U          /*!< SYSCLK clock used as ADC clock source */\n#endif\n/**\n  * @}\n  */\n\n#if defined(SWPMI1)\n/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE  Peripheral SWPMI1 clock source selection\n  * @{\n  */\n#define LL_RCC_SWPMI1_CLKSOURCE_PCLK1      0x00000000U          /*!< PCLK1 used as SWPMI1 clock source */\n#define LL_RCC_SWPMI1_CLKSOURCE_HSI        RCC_CCIPR_SWPMI1SEL  /*!< HSI used as SWPMI1 clock source */\n/**\n  * @}\n  */\n#endif /* SWPMI1 */\n\n#if defined(DFSDM1_Channel0)\n#if defined(RCC_CCIPR2_ADFSDM1SEL)\n/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM1 Audio clock source selection\n  * @{\n  */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U             /*!< SAI1 clock used as DFSDM1 Audio clock */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI  RCC_CCIPR2_ADFSDM1SEL_0 /*!< HSI clock used as DFSDM1 Audio clock */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI  RCC_CCIPR2_ADFSDM1SEL_1 /*!< MSI clock used as DFSDM1 Audio clock */\n/**\n  * @}\n  */\n#endif /* RCC_CCIPR2_ADFSDM1SEL */\n\n/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM1 clock source selection\n  * @{\n  */\n#if defined(RCC_CCIPR2_DFSDM1SEL)\n#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2      0x00000000U          /*!< PCLK2 used as DFSDM1 clock source */\n#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK     RCC_CCIPR2_DFSDM1SEL /*!< SYSCLK used as DFSDM1 clock source */\n#else\n#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2      0x00000000U          /*!< PCLK2 used as DFSDM1 clock source */\n#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK     RCC_CCIPR_DFSDM1SEL  /*!< SYSCLK used as DFSDM1 clock source */\n#endif /* RCC_CCIPR2_DFSDM1SEL */\n/**\n  * @}\n  */\n#endif /* DFSDM1_Channel0 */\n\n#if defined(DSI)\n/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection\n  * @{\n  */\n#define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U           /*!< DSI-PHY clock used as DSI byte lane clock source */\n#define LL_RCC_DSI_CLKSOURCE_PLL          RCC_CCIPR2_DSISEL     /*!< PLL clock used as DSI byte lane clock source */\n/**\n  * @}\n  */\n#endif /* DSI */\n\n#if defined(LTDC)\n/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE  Peripheral LTDC clock source selection\n  * @{\n  */\n#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2  0x00000000U              /*!< PLLSAI2DIVR divided by 2 used as LTDC clock source */\n#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4  RCC_CCIPR2_PLLSAI2DIVR_0 /*!< PLLSAI2DIVR divided by 4 used as LTDC clock source */\n#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8  RCC_CCIPR2_PLLSAI2DIVR_1 /*!< PLLSAI2DIVR divided by 8 used as LTDC clock source */\n#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR   /*!< PLLSAI2DIVR divided by 16 used as LTDC clock source */\n/**\n  * @}\n  */\n#endif /* LTDC */\n\n#if defined(OCTOSPI1)\n/** @defgroup RCC_LL_EC_OCTOSPI  Peripheral OCTOSPI get clock source\n  * @{\n  */\n#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK    0x00000000U           /*!< SYSCLK used as OctoSPI clock source */\n#define LL_RCC_OCTOSPI_CLKSOURCE_MSI       RCC_CCIPR2_OSPISEL_0  /*!< MSI used as OctoSPI clock source */\n#define LL_RCC_OCTOSPI_CLKSOURCE_PLL       RCC_CCIPR2_OSPISEL_1  /*!< PLL used as OctoSPI clock source */\n/**\n  * @}\n  */\n#endif /* OCTOSPI1 */\n\n/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source\n  * @{\n  */\n#define LL_RCC_USART1_CLKSOURCE            RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */\n#define LL_RCC_USART2_CLKSOURCE            RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */\n#if defined(RCC_CCIPR_USART3SEL)\n#define LL_RCC_USART3_CLKSOURCE            RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */\n#endif /* RCC_CCIPR_USART3SEL */\n/**\n  * @}\n  */\n\n#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)\n/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source\n  * @{\n  */\n#if defined(RCC_CCIPR_UART4SEL)\n#define LL_RCC_UART4_CLKSOURCE             RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */\n#endif /* RCC_CCIPR_UART4SEL */\n#if defined(RCC_CCIPR_UART5SEL)\n#define LL_RCC_UART5_CLKSOURCE             RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */\n#endif /* RCC_CCIPR_UART5SEL */\n/**\n  * @}\n  */\n#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */\n\n/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source\n  * @{\n  */\n#define LL_RCC_LPUART1_CLKSOURCE           RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source\n  * @{\n  */\n#define LL_RCC_I2C1_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */\n#if defined(RCC_CCIPR_I2C2SEL)\n#define LL_RCC_I2C2_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */\n#endif /* RCC_CCIPR_I2C2SEL */\n#define LL_RCC_I2C3_CLKSOURCE              ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */\n#if defined(RCC_CCIPR2_I2C4SEL)\n#define LL_RCC_I2C4_CLKSOURCE              ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */\n#endif /* RCC_CCIPR2_I2C4SEL */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source\n  * @{\n  */\n#define LL_RCC_LPTIM1_CLKSOURCE            RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */\n#define LL_RCC_LPTIM2_CLKSOURCE            RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */\n/**\n  * @}\n  */\n\n#if defined(RCC_CCIPR_SAI1SEL)\n/** @defgroup RCC_LL_EC_SAI1  Peripheral SAI get clock source\n  * @{\n  */\n#if defined(RCC_CCIPR2_SAI1SEL)\n#define LL_RCC_SAI1_CLKSOURCE              RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */\n#else\n#define LL_RCC_SAI1_CLKSOURCE              RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */\n#endif /* RCC_CCIPR2_SAI1SEL */\n#if defined(RCC_CCIPR2_SAI2SEL)\n#define LL_RCC_SAI2_CLKSOURCE              RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */\n#elif defined(RCC_CCIPR_SAI2SEL)\n#define LL_RCC_SAI2_CLKSOURCE              RCC_CCIPR_SAI2SEL /*!< SAI2 Clock source selection */\n#endif /* RCC_CCIPR2_SAI2SEL */\n/**\n  * @}\n  */\n#endif /* RCC_CCIPR_SAI1SEL */\n\n#if defined(RCC_CCIPR2_SDMMCSEL)\n/** @defgroup RCC_LL_EC_SDMMC1_KERNEL  Peripheral SDMMC get kernel clock source\n  * @{\n  */\n#define LL_RCC_SDMMC1_KERNELCLKSOURCE      RCC_CCIPR2_SDMMCSEL /*!< SDMMC1 Kernel Clock source selection */\n/**\n  * @}\n  */\n#endif /* RCC_CCIPR2_SDMMCSEL */\n\n#if defined(SDMMC1)\n/** @defgroup RCC_LL_EC_SDMMC1  Peripheral SDMMC get clock source\n  * @{\n  */\n#define LL_RCC_SDMMC1_CLKSOURCE            RCC_CCIPR_CLK48SEL /*!< SDMMC1 Clock source selection */\n/**\n  * @}\n  */\n#endif /* SDMMC1 */\n\n/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source\n  * @{\n  */\n#define LL_RCC_RNG_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */\n/**\n  * @}\n  */\n\n#if defined(USB_OTG_FS) || defined(USB)\n/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source\n  * @{\n  */\n#define LL_RCC_USB_CLKSOURCE               RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */\n/**\n  * @}\n  */\n#endif /* USB_OTG_FS || USB */\n\n/** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source\n  * @{\n  */\n#if defined(RCC_CCIPR_ADCSEL)\n#define LL_RCC_ADC_CLKSOURCE               RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */\n#else\n#define LL_RCC_ADC_CLKSOURCE               ((uint32_t)0x30000000U) /*!< ADC Clock source selection */\n#endif\n/**\n  * @}\n  */\n\n#if defined(SWPMI1)\n/** @defgroup RCC_LL_EC_SWPMI1  Peripheral SWPMI1 get clock source\n  * @{\n  */\n#define LL_RCC_SWPMI1_CLKSOURCE            RCC_CCIPR_SWPMI1SEL /*!< SWPMI1 Clock source selection */\n/**\n  * @}\n  */\n#endif /* SWPMI1 */\n\n#if defined(DFSDM1_Channel0)\n#if defined(RCC_CCIPR2_ADFSDM1SEL)\n/** @defgroup RCC_LL_EC_DFSDM1_AUDIO  Peripheral DFSDM1 Audio get clock source\n  * @{\n  */\n#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */\n/**\n  * @}\n  */\n\n#endif /* RCC_CCIPR2_ADFSDM1SEL */\n/** @defgroup RCC_LL_EC_DFSDM1  Peripheral DFSDM1 get clock source\n  * @{\n  */\n#if defined(RCC_CCIPR2_DFSDM1SEL)\n#define LL_RCC_DFSDM1_CLKSOURCE            RCC_CCIPR2_DFSDM1SEL /*!< DFSDM1 Clock source selection */\n#else\n#define LL_RCC_DFSDM1_CLKSOURCE            RCC_CCIPR_DFSDM1SEL /*!< DFSDM1 Clock source selection */\n#endif /* RCC_CCIPR2_DFSDM1SEL */\n/**\n  * @}\n  */\n#endif /* DFSDM1_Channel0 */\n\n#if defined(DSI)\n/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source\n  * @{\n  */\n#define LL_RCC_DSI_CLKSOURCE               RCC_CCIPR2_DSISEL      /*!< DSI Clock source selection */\n/**\n  * @}\n  */\n#endif /* DSI */\n\n#if defined(LTDC)\n/** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source\n  * @{\n  */\n#define LL_RCC_LTDC_CLKSOURCE              RCC_CCIPR2_PLLSAI2DIVR /*!< LTDC Clock source selection */\n/**\n  * @}\n  */\n#endif /* LTDC */\n\n#if defined(OCTOSPI1)\n/** @defgroup RCC_LL_EC_OCTOSPI  Peripheral OCTOSPI get clock source\n  * @{\n  */\n#define LL_RCC_OCTOSPI_CLKSOURCE           RCC_CCIPR2_OSPISEL    /*!< OctoSPI Clock source selection */\n/**\n  * @}\n  */\n#endif /* OCTOSPI1 */\n\n\n/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection\n  * @{\n  */\n#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */\n#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32     RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by 32 used as RTC clock */\n/**\n  * @}\n  */\n\n\n/** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLSAI1 and PLLSAI2 entry clock source\n  * @{\n  */\n#define LL_RCC_PLLSOURCE_NONE              0x00000000U             /*!< No clock */\n#define LL_RCC_PLLSOURCE_MSI               RCC_PLLCFGR_PLLSRC_MSI  /*!< MSI clock selected as PLL entry clock source */\n#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */\n#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLM_DIV  PLL division factor\n  * @{\n  */\n#define LL_RCC_PLLM_DIV_1                  0x00000000U                                                    /*!< Main PLL division factor for PLLM input by 1 */\n#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_0)                                           /*!< Main PLL division factor for PLLM input by 2 */\n#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1)                                           /*!< Main PLL division factor for PLLM input by 3 */\n#define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)                      /*!< Main PLL division factor for PLLM input by 4 */\n#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2)                                           /*!< Main PLL division factor for PLLM input by 5 */\n#define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)                      /*!< Main PLL division factor for PLLM input by 6 */\n#define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)                      /*!< Main PLL division factor for PLLM input by 7 */\n#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 8 */\n#if defined(RCC_PLLM_DIV_1_16_SUPPORT)\n#define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3)                                           /*!< Main PLL division factor for PLLM input by 9 */\n#define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)                      /*!< Main PLL division factor for PLLM input by 10 */\n#define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)                      /*!< Main PLL division factor for PLLM input by 11 */\n#define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 12 */\n#define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)                      /*!< Main PLL division factor for PLLM input by 13 */\n#define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 14 */\n#define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 15 */\n#define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 16 */\n#endif /* RCC_PLLM_DIV_1_16_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)\n  * @{\n  */\n#define LL_RCC_PLLR_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLCLK (system clock) by 2 */\n#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_0)   /*!< Main PLL division factor for PLLCLK (system clock) by 4 */\n#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_1)   /*!< Main PLL division factor for PLLCLK (system clock) by 6 */\n#define LL_RCC_PLLR_DIV_8                  (RCC_PLLCFGR_PLLR)     /*!< Main PLL division factor for PLLCLK (system clock) by 8 */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLP_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)\n  * @{\n  */\n#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\n#define LL_RCC_PLLP_DIV_2                  (RCC_PLLCFGR_PLLPDIV_1)                                              /*!< Main PLL division factor for PLLP output by 2 */\n#define LL_RCC_PLLP_DIV_3                  (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 3 */\n#define LL_RCC_PLLP_DIV_4                  (RCC_PLLCFGR_PLLPDIV_2)                                              /*!< Main PLL division factor for PLLP output by 4 */\n#define LL_RCC_PLLP_DIV_5                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 5 */\n#define LL_RCC_PLLP_DIV_6                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 6 */\n#define LL_RCC_PLLP_DIV_7                  (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 7 */\n#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLPDIV_3)                                              /*!< Main PLL division factor for PLLP output by 8 */\n#define LL_RCC_PLLP_DIV_9                  (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 9 */\n#define LL_RCC_PLLP_DIV_10                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 10 */\n#define LL_RCC_PLLP_DIV_11                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 11 */\n#define LL_RCC_PLLP_DIV_12                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 12 */\n#define LL_RCC_PLLP_DIV_13                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 13 */\n#define LL_RCC_PLLP_DIV_14                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 14 */\n#define LL_RCC_PLLP_DIV_15                 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */\n#define LL_RCC_PLLP_DIV_16                 (RCC_PLLCFGR_PLLPDIV_4)                                              /*!< Main PLL division factor for PLLP output by 16 */\n#define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0)                        /*!< Main PLL division factor for PLLP output by 17 */\n#define LL_RCC_PLLP_DIV_18                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1)                        /*!< Main PLL division factor for PLLP output by 18 */\n#define LL_RCC_PLLP_DIV_19                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 19 */\n#define LL_RCC_PLLP_DIV_20                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2)                        /*!< Main PLL division factor for PLLP output by 20 */\n#define LL_RCC_PLLP_DIV_21                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 21 */\n#define LL_RCC_PLLP_DIV_22                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 22 */\n#define LL_RCC_PLLP_DIV_23                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */\n#define LL_RCC_PLLP_DIV_24                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3)                        /*!< Main PLL division factor for PLLP output by 24 */\n#define LL_RCC_PLLP_DIV_25                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0)  /*!< Main PLL division factor for PLLP output by 25 */\n#define LL_RCC_PLLP_DIV_26                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1)  /*!< Main PLL division factor for PLLP output by 26 */\n#define LL_RCC_PLLP_DIV_27                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */\n#define LL_RCC_PLLP_DIV_28                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2)  /*!< Main PLL division factor for PLLP output by 28 */\n#define LL_RCC_PLLP_DIV_29                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */\n#define LL_RCC_PLLP_DIV_30                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */\n#define LL_RCC_PLLP_DIV_31                 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */\n#else\n#define LL_RCC_PLLP_DIV_7                  0x00000000U            /*!< Main PLL division factor for PLLP output by 7 */\n#define LL_RCC_PLLP_DIV_17                 (RCC_PLLCFGR_PLLP)     /*!< Main PLL division factor for PLLP output by 17 */\n#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\n/**\n  * @}\n  */\n#endif /* RCC_PLLP_SUPPORT */\n\n/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)\n  * @{\n  */\n#define LL_RCC_PLLQ_DIV_2                  0x00000000U             /*!< Main PLL division factor for PLLQ output by 2 */\n#define LL_RCC_PLLQ_DIV_4                  (RCC_PLLCFGR_PLLQ_0)    /*!< Main PLL division factor for PLLQ output by 4 */\n#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_1)    /*!< Main PLL division factor for PLLQ output by 6 */\n#define LL_RCC_PLLQ_DIV_8                  (RCC_PLLCFGR_PLLQ)      /*!< Main PLL division factor for PLLQ output by 8 */\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLSAI1M  PLLSAI1 division factor (PLLSAI1M)\n  * @{\n  */\n#define LL_RCC_PLLSAI1M_DIV_1              0x00000000U                                             /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */\n#define LL_RCC_PLLSAI1M_DIV_2              (RCC_PLLSAI1CFGR_PLLSAI1M_0)                            /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */\n#define LL_RCC_PLLSAI1M_DIV_3              (RCC_PLLSAI1CFGR_PLLSAI1M_1)                            /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */\n#define LL_RCC_PLLSAI1M_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */\n#define LL_RCC_PLLSAI1M_DIV_5              (RCC_PLLSAI1CFGR_PLLSAI1M_2)                            /*!< PLLSAI1 division factor for PLLSAI1M input by 5 */\n#define LL_RCC_PLLSAI1M_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 6 */\n#define LL_RCC_PLLSAI1M_DIV_7              (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 7 */\n#define LL_RCC_PLLSAI1M_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 8 */\n#define LL_RCC_PLLSAI1M_DIV_9              (RCC_PLLSAI1CFGR_PLLSAI1M_3)                            /*!< PLLSAI1 division factor for PLLSAI1M input by 9 */\n#define LL_RCC_PLLSAI1M_DIV_10             (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 10 */\n#define LL_RCC_PLLSAI1M_DIV_11             (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 11 */\n#define LL_RCC_PLLSAI1M_DIV_12             (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 12 */\n#define LL_RCC_PLLSAI1M_DIV_13             (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2) /*!< PLLSAI1 division factor for PLLSAI1M input by 13 */\n#define LL_RCC_PLLSAI1M_DIV_14             (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 14 */\n#define LL_RCC_PLLSAI1M_DIV_15             (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 15 */\n#define LL_RCC_PLLSAI1M_DIV_16             (RCC_PLLSAI1CFGR_PLLSAI1M_3|RCC_PLLSAI1CFGR_PLLSAI1M_2|RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 16 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLSAI1Q  PLLSAI1 division factor (PLLSAI1Q)\n  * @{\n  */\n#define LL_RCC_PLLSAI1Q_DIV_2              0x00000000U                  /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */\n#define LL_RCC_PLLSAI1Q_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */\n#define LL_RCC_PLLSAI1Q_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */\n#define LL_RCC_PLLSAI1Q_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1Q)   /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLSAI1P  PLLSAI1 division factor (PLLSAI1P)\n  * @{\n  */\n#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\n#define LL_RCC_PLLSAI1P_DIV_2              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 2 */\n#define LL_RCC_PLLSAI1P_DIV_3              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 3 */\n#define LL_RCC_PLLSAI1P_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 4 */\n#define LL_RCC_PLLSAI1P_DIV_5              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 5 */\n#define LL_RCC_PLLSAI1P_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 6 */\n#define LL_RCC_PLLSAI1P_DIV_7              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */\n#define LL_RCC_PLLSAI1P_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 8 */\n#define LL_RCC_PLLSAI1P_DIV_9              (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 9 */\n#define LL_RCC_PLLSAI1P_DIV_10             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 10 */\n#define LL_RCC_PLLSAI1P_DIV_11             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 1 */\n#define LL_RCC_PLLSAI1P_DIV_12             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 12 */\n#define LL_RCC_PLLSAI1P_DIV_13             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 13 */\n#define LL_RCC_PLLSAI1P_DIV_14             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 14 */\n#define LL_RCC_PLLSAI1P_DIV_15             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 15 */\n#define LL_RCC_PLLSAI1P_DIV_16             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4)                               /*!< PLLSAI1 division factor for PLLSAI1P output by 16 */\n#define LL_RCC_PLLSAI1P_DIV_17             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */\n#define LL_RCC_PLLSAI1P_DIV_18             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 18 */\n#define LL_RCC_PLLSAI1P_DIV_19             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 19 */\n#define LL_RCC_PLLSAI1P_DIV_20             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 20 */\n#define LL_RCC_PLLSAI1P_DIV_21             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division fctor for PLLSAI1P output by 21 */\n#define LL_RCC_PLLSAI1P_DIV_22             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 22 */\n#define LL_RCC_PLLSAI1P_DIV_23             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 23 */\n#define LL_RCC_PLLSAI1P_DIV_24             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /*!< PLLSAI1 division factor for PLLSAI1P output by 24 */\n#define LL_RCC_PLLSAI1P_DIV_25             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 25 */\n#define LL_RCC_PLLSAI1P_DIV_26             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 26 */\n#define LL_RCC_PLLSAI1P_DIV_27             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 27 */\n#define LL_RCC_PLLSAI1P_DIV_28             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /*!< PLLSAI1 division factor for PLLSAI1P output by 28 */\n#define LL_RCC_PLLSAI1P_DIV_29             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 29 */\n#define LL_RCC_PLLSAI1P_DIV_30             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /*!< PLLSAI1 division factor for PLLSAI1P output by 30 */\n#define LL_RCC_PLLSAI1P_DIV_31             (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */\n#else\n#define LL_RCC_PLLSAI1P_DIV_7              0x00000000U                /*!< PLLSAI1 division factor for PLLSAI1P output by 7 */\n#define LL_RCC_PLLSAI1P_DIV_17             (RCC_PLLSAI1CFGR_PLLSAI1P) /*!< PLLSAI1 division factor for PLLSAI1P output by 17 */\n#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLSAI1R  PLLSAI1 division factor (PLLSAI1R)\n  * @{\n  */\n#define LL_RCC_PLLSAI1R_DIV_2              0x00000000U                  /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */\n#define LL_RCC_PLLSAI1R_DIV_4              (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */\n#define LL_RCC_PLLSAI1R_DIV_6              (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */\n#define LL_RCC_PLLSAI1R_DIV_8              (RCC_PLLSAI1CFGR_PLLSAI1R)   /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLSAI2M  PLLSAI1 division factor (PLLSAI2M)\n  * @{\n  */\n#define LL_RCC_PLLSAI2M_DIV_1              0x00000000U                                             /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */\n#define LL_RCC_PLLSAI2M_DIV_2              (RCC_PLLSAI2CFGR_PLLSAI2M_0)                            /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */\n#define LL_RCC_PLLSAI2M_DIV_3              (RCC_PLLSAI2CFGR_PLLSAI2M_1)                            /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */\n#define LL_RCC_PLLSAI2M_DIV_4              (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */\n#define LL_RCC_PLLSAI2M_DIV_5              (RCC_PLLSAI2CFGR_PLLSAI2M_2)                            /*!< PLLSAI2 division factor for PLLSAI2M input by 5 */\n#define LL_RCC_PLLSAI2M_DIV_6              (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 6 */\n#define LL_RCC_PLLSAI2M_DIV_7              (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 7 */\n#define LL_RCC_PLLSAI2M_DIV_8              (RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 8 */\n#define LL_RCC_PLLSAI2M_DIV_9              (RCC_PLLSAI2CFGR_PLLSAI2M_3)                            /*!< PLLSAI2 division factor for PLLSAI2M input by 9 */\n#define LL_RCC_PLLSAI2M_DIV_10             (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 10 */\n#define LL_RCC_PLLSAI2M_DIV_11             (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 11 */\n#define LL_RCC_PLLSAI2M_DIV_12             (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 12 */\n#define LL_RCC_PLLSAI2M_DIV_13             (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2) /*!< PLLSAI2 division factor for PLLSAI2M input by 13 */\n#define LL_RCC_PLLSAI2M_DIV_14             (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 14 */\n#define LL_RCC_PLLSAI2M_DIV_15             (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 15 */\n#define LL_RCC_PLLSAI2M_DIV_16             (RCC_PLLSAI2CFGR_PLLSAI2M_3|RCC_PLLSAI2CFGR_PLLSAI2M_2|RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 16 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\n\n#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\n/** @defgroup RCC_LL_EC_PLLSAI2Q  PLLSAI2 division factor (PLLSAI2Q)\n  * @{\n  */\n#define LL_RCC_PLLSAI2Q_DIV_2              0x00000000U                  /*!< PLLSAI2 division factor for PLLSAI2Q output by 2 */\n#define LL_RCC_PLLSAI2Q_DIV_4              (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /*!< PLLSAI2 division factor for PLLSAI2Q output by 4 */\n#define LL_RCC_PLLSAI2Q_DIV_6              (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /*!< PLLSAI2 division factor for PLLSAI2Q output by 6 */\n#define LL_RCC_PLLSAI2Q_DIV_8              (RCC_PLLSAI2CFGR_PLLSAI2Q)   /*!< PLLSAI2 division factor for PLLSAI2Q output by 8 */\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\n\n/** @defgroup RCC_LL_EC_PLLSAI2P  PLLSAI2 division factor (PLLSAI2P)\n  * @{\n  */\n#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\n#define LL_RCC_PLLSAI2P_DIV_2              (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1)                               /*!< PLLSAI2 division factor for PLLSAI2P output by 2 */\n#define LL_RCC_PLLSAI2P_DIV_3              (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 3 */\n#define LL_RCC_PLLSAI2P_DIV_4              (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2)                               /*!< PLLSAI2 division factor for PLLSAI2P output by 4 */\n#define LL_RCC_PLLSAI2P_DIV_5              (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 5 */\n#define LL_RCC_PLLSAI2P_DIV_6              (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 6 */\n#define LL_RCC_PLLSAI2P_DIV_7              (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */\n#define LL_RCC_PLLSAI2P_DIV_8              (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3)                               /*!< PLLSAI2 division factor for PLLSAI2P output by 8 */\n#define LL_RCC_PLLSAI2P_DIV_9              (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 9 */\n#define LL_RCC_PLLSAI2P_DIV_10             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 10 */\n#define LL_RCC_PLLSAI2P_DIV_11             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 1 */\n#define LL_RCC_PLLSAI2P_DIV_12             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 12 */\n#define LL_RCC_PLLSAI2P_DIV_13             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 13 */\n#define LL_RCC_PLLSAI2P_DIV_14             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 14 */\n#define LL_RCC_PLLSAI2P_DIV_15             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 15 */\n#define LL_RCC_PLLSAI2P_DIV_16             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4)                               /*!< PLLSAI2 division factor for PLLSAI2P output by 16 */\n#define LL_RCC_PLLSAI2P_DIV_17             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */\n#define LL_RCC_PLLSAI2P_DIV_18             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 18 */\n#define LL_RCC_PLLSAI2P_DIV_19             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 19 */\n#define LL_RCC_PLLSAI2P_DIV_20             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 20 */\n#define LL_RCC_PLLSAI2P_DIV_21             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division fctor for PLLSAI2P output by 21 */\n#define LL_RCC_PLLSAI2P_DIV_22             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 22 */\n#define LL_RCC_PLLSAI2P_DIV_23             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 23 */\n#define LL_RCC_PLLSAI2P_DIV_24             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /*!< PLLSAI2 division factor for PLLSAI2P output by 24 */\n#define LL_RCC_PLLSAI2P_DIV_25             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 25 */\n#define LL_RCC_PLLSAI2P_DIV_26             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 26 */\n#define LL_RCC_PLLSAI2P_DIV_27             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 27 */\n#define LL_RCC_PLLSAI2P_DIV_28             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /*!< PLLSAI2 division factor for PLLSAI2P output by 28 */\n#define LL_RCC_PLLSAI2P_DIV_29             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI2 division factor for PLLSAI2P output by 29 */\n#define LL_RCC_PLLSAI2P_DIV_30             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /*!< PLLSAI2 division factor for PLLSAI2P output by 30 */\n#define LL_RCC_PLLSAI2P_DIV_31             (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /*!< PLLSAI1 division factor for PLLSAI1P output by 31 */\n#else\n#define LL_RCC_PLLSAI2P_DIV_7              0x00000000U                /*!< PLLSAI2 division factor for PLLSAI2P output by 7 */\n#define LL_RCC_PLLSAI2P_DIV_17             (RCC_PLLSAI2CFGR_PLLSAI2P) /*!< PLLSAI2 division factor for PLLSAI2P output by 17 */\n#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EC_PLLSAI2R  PLLSAI2 division factor (PLLSAI2R)\n  * @{\n  */\n#define LL_RCC_PLLSAI2R_DIV_2              0x00000000U                  /*!< PLLSAI2 division factor for PLLSAI2R output by 2 */\n#define LL_RCC_PLLSAI2R_DIV_4              (RCC_PLLSAI2CFGR_PLLSAI2R_0) /*!< PLLSAI2 division factor for PLLSAI2R output by 4 */\n#define LL_RCC_PLLSAI2R_DIV_6              (RCC_PLLSAI2CFGR_PLLSAI2R_1) /*!< PLLSAI2 division factor for PLLSAI2R output by 6 */\n#define LL_RCC_PLLSAI2R_DIV_8              (RCC_PLLSAI2CFGR_PLLSAI2R)   /*!< PLLSAI2 division factor for PLLSAI2R output by 8 */\n/**\n  * @}\n  */\n\n#if defined(RCC_CCIPR2_PLLSAI2DIVR)\n/** @defgroup RCC_LL_EC_PLLSAI2DIVR  PLLSAI2DIVR division factor (PLLSAI2DIVR)\n  * @{\n  */\n#define LL_RCC_PLLSAI2DIVR_DIV_2           0x00000000U                     /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 */\n#define LL_RCC_PLLSAI2DIVR_DIV_4           RCC_CCIPR2_PLLSAI2DIVR_0        /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 */\n#define LL_RCC_PLLSAI2DIVR_DIV_8           RCC_CCIPR2_PLLSAI2DIVR_1        /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 */\n#define LL_RCC_PLLSAI2DIVR_DIV_16          (RCC_CCIPR2_PLLSAI2DIVR_1 | RCC_CCIPR2_PLLSAI2DIVR_0) /*!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 */\n/**\n  * @}\n  */\n#endif /* RCC_CCIPR2_PLLSAI2DIVR */\n#endif /* RCC_PLLSAI2_SUPPORT */\n\n/** @defgroup RCC_LL_EC_MSIRANGESEL  MSI clock range selection\n  * @{\n  */\n#define LL_RCC_MSIRANGESEL_STANDBY         0U                  /*!< MSI Range is provided by MSISRANGE */\n#define LL_RCC_MSIRANGESEL_RUN             1U                  /*!< MSI Range is provided by MSIRANGE */\n/**\n  * @}\n  */\n\n#if defined(RCC_CSR_LSIPREDIV)\n/** @defgroup RCC_LL_EC_LSIPREDIV  LSI division factor\n  * @{\n  */\n#define LL_RCC_LSI_PREDIV_1                0x00000000U         /*!< LSI division factor by 1   */\n#define LL_RCC_LSI_PREDIV_128              RCC_CSR_LSIPREDIV   /*!< LSI division factor by 128 */\n/**\n  * @}\n  */\n#endif /* RCC_CSR_LSIPREDIV */\n\n/** Legacy definitions for compatibility purpose\n@cond 0\n*/\n#if defined(DFSDM1_Channel0)\n#define LL_RCC_DFSDM1_CLKSOURCE_PCLK       LL_RCC_DFSDM1_CLKSOURCE_PCLK2\n#define LL_RCC_DFSDM_CLKSOURCE_PCLK        LL_RCC_DFSDM1_CLKSOURCE_PCLK2\n#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK      LL_RCC_DFSDM1_CLKSOURCE_SYSCLK\n#define LL_RCC_DFSDM_CLKSOURCE             LL_RCC_DFSDM1_CLKSOURCE\n#endif /* DFSDM1_Channel0 */\n#if defined(SWPMI1)\n#define LL_RCC_SWPMI1_CLKSOURCE_PCLK       LL_RCC_SWPMI1_CLKSOURCE_PCLK1\n#endif /* SWPMI1 */\n/**\n@endcond\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros\n  * @{\n  */\n\n/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in RCC register\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in RCC register\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies\n  * @{\n  */\n\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency on system domain\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_16 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLN__ Between 8 and 86\n  * @param  __PLLR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_8\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \\\n                   ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_16 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLN__ Between 8 and 86\n  * @param  __PLLP__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_3\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_5\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_7\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  *         @arg @ref LL_RCC_PLLP_DIV_9\n  *         @arg @ref LL_RCC_PLLP_DIV_10\n  *         @arg @ref LL_RCC_PLLP_DIV_11\n  *         @arg @ref LL_RCC_PLLP_DIV_12\n  *         @arg @ref LL_RCC_PLLP_DIV_13\n  *         @arg @ref LL_RCC_PLLP_DIV_14\n  *         @arg @ref LL_RCC_PLLP_DIV_15\n  *         @arg @ref LL_RCC_PLLP_DIV_16\n  *         @arg @ref LL_RCC_PLLP_DIV_17\n  *         @arg @ref LL_RCC_PLLP_DIV_18\n  *         @arg @ref LL_RCC_PLLP_DIV_19\n  *         @arg @ref LL_RCC_PLLP_DIV_20\n  *         @arg @ref LL_RCC_PLLP_DIV_21\n  *         @arg @ref LL_RCC_PLLP_DIV_22\n  *         @arg @ref LL_RCC_PLLP_DIV_23\n  *         @arg @ref LL_RCC_PLLP_DIV_24\n  *         @arg @ref LL_RCC_PLLP_DIV_25\n  *         @arg @ref LL_RCC_PLLP_DIV_26\n  *         @arg @ref LL_RCC_PLLP_DIV_27\n  *         @arg @ref LL_RCC_PLLP_DIV_28\n  *         @arg @ref LL_RCC_PLLP_DIV_29\n  *         @arg @ref LL_RCC_PLLP_DIV_30\n  *         @arg @ref LL_RCC_PLLP_DIV_31\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \\\n                   ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))\n\n#else\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  __PLLN__ Between 8 and 86\n  * @param  __PLLP__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_7\n  *         @arg @ref LL_RCC_PLLP_DIV_17\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \\\n                   (((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))\n\n#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n/**\n  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain\n  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_16 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  __PLLN__ Between 8 and 86\n  * @param  __PLLQ__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \\\n                   ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI1 frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),\n  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLSAI1M__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_16\n  * @param  __PLLSAI1N__ Between 8 and 86\n  * @param  __PLLSAI1P__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_31\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \\\n                   ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \\\n                    ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))\n\n#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI1 frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  __PLLSAI1N__ Between 8 and 86\n  * @param  __PLLSAI1P__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_31\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \\\n                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \\\n                    ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))\n\n#else\n/**\n  * @brief  Helper macro to calculate the PLLSAI1 frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  __PLLSAI1N__ Between 8 and 86\n  * @param  __PLLSAI1P__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \\\n                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \\\n                    (((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))\n\n#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\n\n#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI1 frequency used on 48M domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),\n  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLSAI1M__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_16\n  * @param  __PLLSAI1N__ Between 8 and 86\n  * @param  __PLLSAI1Q__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \\\n                   ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \\\n                    ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))\n\n#else\n/**\n  * @brief  Helper macro to calculate the PLLSAI1 frequency used on 48M domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  __PLLSAI1N__ Between 8 and 86\n  * @param  __PLLSAI1Q__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \\\n                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \\\n                    ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))\n\n#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\n\n#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI1 frequency used on ADC domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),\n  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLSAI1M__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_16\n  * @param  __PLLSAI1N__ Between 8 and 86\n  * @param  __PLLSAI1R__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_8\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \\\n                   ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \\\n                    ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))\n\n#else\n/**\n  * @brief  Helper macro to calculate the PLLSAI1 frequency used on ADC domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  __PLLSAI1N__ Between 8 and 86\n  * @param  __PLLSAI1R__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_8\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \\\n                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \\\n                    ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))\n\n#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\n\n#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI2 frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),\n  *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLSAI2M__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_16\n  * @param  __PLLSAI2N__ Between 8 and 86\n  * @param  __PLLSAI2P__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_31\n  * @retval PLLSAI2 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \\\n                   ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \\\n                    ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))\n\n#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI2 frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  __PLLSAI2N__ Between 8 and 86\n  * @param  __PLLSAI2P__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_31\n  * @retval PLLSAI2 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \\\n                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \\\n                    ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))\n\n#else\n/**\n  * @brief  Helper macro to calculate the PLLSAI2 frequency used for SAI domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  __PLLSAI2N__ Between 8 and 86\n  * @param  __PLLSAI2P__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17\n  * @retval PLLSAI2 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \\\n                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \\\n                    (((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))\n\n#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(LTDC)\n/**\n  * @brief  Helper macro to calculate the PLLSAI2 frequency used for LTDC domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),\n  *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)\n  * @param  __PLLSAI2M__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_16\n  * @param  __PLLSAI2N__ Between 8 and 86\n  * @param  __PLLSAI2R__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_8\n  * @param  __PLLSAI2DIVR__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16\n  * @retval PLLSAI2 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \\\n                   (((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \\\n                    (((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos])))\n#elif defined(RCC_PLLSAI2_SUPPORT)\n/**\n  * @brief  Helper macro to calculate the PLLSAI2 frequency used on ADC domain\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),\n  *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)\n  * @param  __PLLM__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  __PLLSAI2N__ Between 8 and 86\n  * @param  __PLLSAI2R__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_8\n  * @retval PLLSAI2 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \\\n                   ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \\\n                    ((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))\n\n#endif /* LTDC */\n\n#if defined(DSI)\n/**\n  * @brief  Helper macro to calculate the PLLDSICLK frequency used on DSI\n  * @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),\n  *             @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ());\n  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)\n  * @param  __PLLSAI2M__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_16\n  * @param  __PLLSAI2N__ Between 8 and 86\n  * @param  __PLLSAI2Q__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_8\n  * @retval PLL clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \\\n                   ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \\\n                    ((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))\n#endif /* DSI */\n\n\n\n/**\n  * @brief  Helper macro to calculate the HCLK frequency\n  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)\n  * @param  __AHBPRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  * @retval HCLK clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])\n\n/**\n  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)\n  * @param  __HCLKFREQ__ HCLK frequency\n  * @param  __APB1PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  * @retval PCLK1 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])\n\n/**\n  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)\n  * @param  __HCLKFREQ__ HCLK frequency\n  * @param  __APB2PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  * @retval PCLK2 clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])\n\n/**\n  * @brief  Helper macro to calculate the MSI frequency (in Hz)\n  * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()\n  * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,\n  *        __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()\n  *        else by LL_RCC_MSI_GetRange()\n  *        ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n  *              (LL_RCC_MSI_IsEnabledRangeSelect()?\n  *               LL_RCC_MSI_GetRange():\n  *               LL_RCC_MSI_GetRangeAfterStandby()))\n  * @param  __MSISEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MSIRANGESEL_STANDBY\n  *         @arg @ref LL_RCC_MSIRANGESEL_RUN\n  * @param  __MSIRANGE__ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MSIRANGE_0\n  *         @arg @ref LL_RCC_MSIRANGE_1\n  *         @arg @ref LL_RCC_MSIRANGE_2\n  *         @arg @ref LL_RCC_MSIRANGE_3\n  *         @arg @ref LL_RCC_MSIRANGE_4\n  *         @arg @ref LL_RCC_MSIRANGE_5\n  *         @arg @ref LL_RCC_MSIRANGE_6\n  *         @arg @ref LL_RCC_MSIRANGE_7\n  *         @arg @ref LL_RCC_MSIRANGE_8\n  *         @arg @ref LL_RCC_MSIRANGE_9\n  *         @arg @ref LL_RCC_MSIRANGE_10\n  *         @arg @ref LL_RCC_MSIRANGE_11\n  *         @arg @ref LL_RCC_MSISRANGE_4\n  *         @arg @ref LL_RCC_MSISRANGE_5\n  *         @arg @ref LL_RCC_MSISRANGE_6\n  *         @arg @ref LL_RCC_MSISRANGE_7\n  * @retval MSI clock frequency (in Hz)\n  */\n#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__)   (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \\\n                           (MSIRangeTable[(__MSIRANGE__) >> 8U]) : \\\n                           (MSIRangeTable[(__MSIRANGE__) >> 4U]))\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions\n  * @{\n  */\n\n/** @defgroup RCC_LL_EF_HSE HSE\n  * @{\n  */\n\n/**\n  * @brief  Enable the Clock Security System.\n  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_CSSON);\n}\n\n/**\n  * @brief  Enable HSE external oscillator (HSE Bypass)\n  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSEBYP);\n}\n\n/**\n  * @brief  Disable HSE external oscillator (HSE Bypass)\n  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);\n}\n\n/**\n  * @brief  Enable HSE crystal oscillator (HSE ON)\n  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSEON);\n}\n\n/**\n  * @brief  Disable HSE crystal oscillator (HSE ON)\n  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSE_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);\n}\n\n/**\n  * @brief  Check if HSE oscillator Ready\n  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_HSI HSI\n  * @{\n  */\n\n/**\n  * @brief  Enable HSI even in stop mode\n  * @note HSI oscillator is forced ON even in Stop mode\n  * @rmtoll CR           HSIKERON      LL_RCC_HSI_EnableInStopMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSIKERON);\n}\n\n/**\n  * @brief  Disable HSI in stop mode\n  * @rmtoll CR           HSIKERON      LL_RCC_HSI_DisableInStopMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);\n}\n\n/**\n  * @brief  Enable HSI oscillator\n  * @rmtoll CR           HSION         LL_RCC_HSI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSION);\n}\n\n/**\n  * @brief  Disable HSI oscillator\n  * @rmtoll CR           HSION         LL_RCC_HSI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSION);\n}\n\n/**\n  * @brief  Check if HSI clock is ready\n  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));\n}\n\n/**\n  * @brief  Enable HSI Automatic from stop mode\n  * @rmtoll CR           HSIASFS       LL_RCC_HSI_EnableAutoFromStop\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_HSIASFS);\n}\n\n/**\n  * @brief  Disable HSI Automatic from stop mode\n  * @rmtoll CR           HSIASFS       LL_RCC_HSI_DisableAutoFromStop\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);\n}\n/**\n  * @brief  Get HSI Calibration value\n  * @note When HSITRIM is written, HSICAL is updated with the sum of\n  *       HSITRIM and the factory trim value\n  * @rmtoll ICSCR        HSICAL        LL_RCC_HSI_GetCalibration\n  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)\n{\n  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);\n}\n\n/**\n  * @brief  Set HSI Calibration trimming\n  * @note user-programmable trimming value that is added to the HSICAL\n  * @note Default value is 16, which, when added to the HSICAL value,\n  *       should trim the HSI to 16 MHz +/- 1 %\n  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_SetCalibTrimming\n  * @param  Value Between Min_Data = 0 and Max_Data = 31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)\n{\n  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);\n}\n\n/**\n  * @brief  Get HSI Calibration trimming\n  * @rmtoll ICSCR        HSITRIM       LL_RCC_HSI_GetCalibTrimming\n  * @retval Between Min_Data = 0 and Max_Data = 31\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)\n{\n  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);\n}\n\n/**\n  * @}\n  */\n\n#if defined(RCC_HSI48_SUPPORT)\n/** @defgroup RCC_LL_EF_HSI48 HSI48\n  * @{\n  */\n\n/**\n  * @brief  Enable HSI48\n  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI48_Enable(void)\n{\n  SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);\n}\n\n/**\n  * @brief  Disable HSI48\n  * @rmtoll CRRCR          HSI48ON       LL_RCC_HSI48_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_HSI48_Disable(void)\n{\n  CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);\n}\n\n/**\n  * @brief  Check if HSI48 oscillator Ready\n  * @rmtoll CRRCR          HSI48RDY      LL_RCC_HSI48_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)\n{\n  return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));\n}\n\n/**\n  * @brief  Get HSI48 Calibration value\n  * @rmtoll CRRCR          HSI48CAL      LL_RCC_HSI48_GetCalibration\n  * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF\n  */\n__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_HSI48_SUPPORT */\n\n/** @defgroup RCC_LL_EF_LSE LSE\n  * @{\n  */\n\n/**\n  * @brief  Enable  Low Speed External (LSE) crystal.\n  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_Enable(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);\n}\n\n/**\n  * @brief  Disable  Low Speed External (LSE) crystal.\n  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_Disable(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);\n}\n\n/**\n  * @brief  Enable external clock source (LSE bypass).\n  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\n}\n\n/**\n  * @brief  Disable external clock source (LSE bypass).\n  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);\n}\n\n/**\n  * @brief  Set LSE oscillator drive capability\n  * @note The oscillator is in Xtal mode when it is not in bypass mode.\n  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability\n  * @param  LSEDrive This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LSEDRIVE_LOW\n  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW\n  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH\n  *         @arg @ref LL_RCC_LSEDRIVE_HIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)\n{\n  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);\n}\n\n/**\n  * @brief  Get LSE oscillator drive capability\n  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_LSEDRIVE_LOW\n  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW\n  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH\n  *         @arg @ref LL_RCC_LSEDRIVE_HIGH\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)\n{\n  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));\n}\n\n/**\n  * @brief  Enable Clock security system on LSE.\n  * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_EnableCSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);\n}\n\n/**\n  * @brief  Disable Clock security system on LSE.\n  * @note Clock security system can be disabled only after a LSE\n  *       failure detection. In that case it MUST be disabled by software.\n  * @rmtoll BDCR         LSECSSON      LL_RCC_LSE_DisableCSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);\n}\n\n/**\n  * @brief  Check if LSE oscillator Ready\n  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)\n{\n  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));\n}\n\n/**\n  * @brief  Check if CSS on LSE failure Detection\n  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsCSSDetected\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)\n{\n  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));\n}\n\n#if defined(RCC_BDCR_LSESYSDIS)\n/**\n  * @brief  Disable LSE oscillator propagation\n  * @note LSE clock isnt propagated to any peripheral except to RTC which remains clocked  \n  * @rmtoll BDCR         LSESYSDIS     LL_RCC_LSE_DisablePropagation\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);\n}\n\n/**\n  * @brief  Enable LSE oscillator propagation\n  * @rmtoll BDCR         LSESYSDIS     LL_RCC_LSE_EnablePropagation\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);\n}\n\n/**\n  * @brief  Check if LSE oscillator propagation is enabled\n  * @rmtoll BDCR         LSESYSDIS     LL_RCC_LSE_IsLSEPropagationEnabled\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSE_IsLSEPropagationEnabled(void)\n{\n  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS) == 0x0);\n}\n#endif /* RCC_BDCR_LSESYSDIS */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_LSI LSI\n  * @{\n  */\n\n/**\n  * @brief  Enable LSI Oscillator\n  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSI_Enable(void)\n{\n  SET_BIT(RCC->CSR, RCC_CSR_LSION);\n}\n\n/**\n  * @brief  Disable LSI Oscillator\n  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSI_Disable(void)\n{\n  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);\n}\n\n/**\n  * @brief  Check if LSI is Ready\n  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));\n}\n\n#if defined(RCC_CSR_LSIPREDIV)\n/**\n  * @brief  Set LSI division factor\n  * @rmtoll CSR          LSIPREDIV     LL_RCC_LSI_SetPrediv\n  * @param  LSIDIV This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LSI_PREDIV_1\n  *         @arg @ref LL_RCC_LSI_PREDIV_128\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)\n{\n  MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, LSI_PREDIV);\n}\n\n/**\n  * @brief  Get LSI division factor\n  * @rmtoll CSR          LSIPREDIV     LL_RCC_LSI_GetPrediv\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_LSI_PREDIV_1\n  *         @arg @ref LL_RCC_LSI_PREDIV_128\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_LSIPREDIV));\n}\n#endif /* RCC_CSR_LSIPREDIV */\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_MSI MSI\n  * @{\n  */\n\n/**\n  * @brief  Enable MSI oscillator\n  * @rmtoll CR           MSION         LL_RCC_MSI_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MSI_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_MSION);\n}\n\n/**\n  * @brief  Disable MSI oscillator\n  * @rmtoll CR           MSION         LL_RCC_MSI_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MSI_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_MSION);\n}\n\n/**\n  * @brief  Check if MSI oscillator Ready\n  * @rmtoll CR           MSIRDY        LL_RCC_MSI_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));\n}\n\n/**\n  * @brief  Enable MSI PLL-mode (Hardware auto calibration with LSE)\n  * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)\n  *       and ready (LSERDY set by hardware)\n  * @note hardware protection to avoid enabling MSIPLLEN if LSE is not\n  *       ready\n  * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_EnablePLLMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);\n}\n\n/**\n  * @brief  Disable MSI-PLL mode\n  * @note cleared by hardware when LSE is disabled (LSEON = 0) or when\n  *       the Clock Security System on LSE detects a LSE failure\n  * @rmtoll CR           MSIPLLEN      LL_RCC_MSI_DisablePLLMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);\n}\n\n/**\n  * @brief  Enable MSI clock range selection with MSIRANGE register\n  * @note Write 0 has no effect. After a standby or a reset\n  *       MSIRGSEL is at 0 and the MSI range value is provided by\n  *       MSISRANGE\n  * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_EnableRangeSelection\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);\n}\n\n/**\n  * @brief  Check if MSI clock range is selected with MSIRANGE register\n  * @rmtoll CR           MSIRGSEL      LL_RCC_MSI_IsEnabledRangeSelect\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));\n}\n\n/**\n  * @brief  Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.\n  * @rmtoll CR           MSIRANGE      LL_RCC_MSI_SetRange\n  * @param  Range This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MSIRANGE_0\n  *         @arg @ref LL_RCC_MSIRANGE_1\n  *         @arg @ref LL_RCC_MSIRANGE_2\n  *         @arg @ref LL_RCC_MSIRANGE_3\n  *         @arg @ref LL_RCC_MSIRANGE_4\n  *         @arg @ref LL_RCC_MSIRANGE_5\n  *         @arg @ref LL_RCC_MSIRANGE_6\n  *         @arg @ref LL_RCC_MSIRANGE_7\n  *         @arg @ref LL_RCC_MSIRANGE_8\n  *         @arg @ref LL_RCC_MSIRANGE_9\n  *         @arg @ref LL_RCC_MSIRANGE_10\n  *         @arg @ref LL_RCC_MSIRANGE_11\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)\n{\n  MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);\n}\n\n/**\n  * @brief  Get the Internal Multi Speed oscillator (MSI) clock range in run mode.\n  * @rmtoll CR           MSIRANGE      LL_RCC_MSI_GetRange\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_MSIRANGE_0\n  *         @arg @ref LL_RCC_MSIRANGE_1\n  *         @arg @ref LL_RCC_MSIRANGE_2\n  *         @arg @ref LL_RCC_MSIRANGE_3\n  *         @arg @ref LL_RCC_MSIRANGE_4\n  *         @arg @ref LL_RCC_MSIRANGE_5\n  *         @arg @ref LL_RCC_MSIRANGE_6\n  *         @arg @ref LL_RCC_MSIRANGE_7\n  *         @arg @ref LL_RCC_MSIRANGE_8\n  *         @arg @ref LL_RCC_MSIRANGE_9\n  *         @arg @ref LL_RCC_MSIRANGE_10\n  *         @arg @ref LL_RCC_MSIRANGE_11\n  */\n__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));\n}\n\n/**\n  * @brief  Configure MSI range used after standby\n  * @rmtoll CSR          MSISRANGE     LL_RCC_MSI_SetRangeAfterStandby\n  * @param  Range This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MSISRANGE_4\n  *         @arg @ref LL_RCC_MSISRANGE_5\n  *         @arg @ref LL_RCC_MSISRANGE_6\n  *         @arg @ref LL_RCC_MSISRANGE_7\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)\n{\n  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);\n}\n\n/**\n  * @brief  Get MSI range used after standby\n  * @rmtoll CSR          MSISRANGE     LL_RCC_MSI_GetRangeAfterStandby\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_MSISRANGE_4\n  *         @arg @ref LL_RCC_MSISRANGE_5\n  *         @arg @ref LL_RCC_MSISRANGE_6\n  *         @arg @ref LL_RCC_MSISRANGE_7\n  */\n__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));\n}\n\n/**\n  * @brief  Get MSI Calibration value\n  * @note When MSITRIM is written, MSICAL is updated with the sum of\n  *       MSITRIM and the factory trim value\n  * @rmtoll ICSCR        MSICAL        LL_RCC_MSI_GetCalibration\n  * @retval Between Min_Data = 0 and Max_Data = 255\n  */\n__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)\n{\n  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);\n}\n\n/**\n  * @brief  Set MSI Calibration trimming\n  * @note user-programmable trimming value that is added to the MSICAL\n  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_SetCalibTrimming\n  * @param  Value Between Min_Data = 0 and Max_Data = 255\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)\n{\n  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);\n}\n\n/**\n  * @brief  Get MSI Calibration trimming\n  * @rmtoll ICSCR        MSITRIM       LL_RCC_MSI_GetCalibTrimming\n  * @retval Between 0 and 255\n  */\n__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)\n{\n  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_LSCO LSCO\n  * @{\n  */\n\n/**\n  * @brief  Enable Low speed clock\n  * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSCO_Enable(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);\n}\n\n/**\n  * @brief  Disable Low speed clock\n  * @rmtoll BDCR         LSCOEN        LL_RCC_LSCO_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSCO_Disable(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);\n}\n\n/**\n  * @brief  Configure Low speed clock selection\n  * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_SetSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);\n}\n\n/**\n  * @brief  Get Low speed clock selection\n  * @rmtoll BDCR         LSCOSEL       LL_RCC_LSCO_GetSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_System System\n  * @{\n  */\n\n/**\n  * @brief  Configure the system clock source\n  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_MSI\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);\n}\n\n/**\n  * @brief  Get the system clock source\n  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE\n  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));\n}\n\n/**\n  * @brief  Set AHB prescaler\n  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);\n}\n\n/**\n  * @brief  Set APB1 prescaler\n  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);\n}\n\n/**\n  * @brief  Set APB2 prescaler\n  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler\n  * @param  Prescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);\n}\n\n/**\n  * @brief  Get AHB prescaler\n  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SYSCLK_DIV_1\n  *         @arg @ref LL_RCC_SYSCLK_DIV_2\n  *         @arg @ref LL_RCC_SYSCLK_DIV_4\n  *         @arg @ref LL_RCC_SYSCLK_DIV_8\n  *         @arg @ref LL_RCC_SYSCLK_DIV_16\n  *         @arg @ref LL_RCC_SYSCLK_DIV_64\n  *         @arg @ref LL_RCC_SYSCLK_DIV_128\n  *         @arg @ref LL_RCC_SYSCLK_DIV_256\n  *         @arg @ref LL_RCC_SYSCLK_DIV_512\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));\n}\n\n/**\n  * @brief  Get APB1 prescaler\n  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_APB1_DIV_1\n  *         @arg @ref LL_RCC_APB1_DIV_2\n  *         @arg @ref LL_RCC_APB1_DIV_4\n  *         @arg @ref LL_RCC_APB1_DIV_8\n  *         @arg @ref LL_RCC_APB1_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));\n}\n\n/**\n  * @brief  Get APB2 prescaler\n  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_APB2_DIV_1\n  *         @arg @ref LL_RCC_APB2_DIV_2\n  *         @arg @ref LL_RCC_APB2_DIV_4\n  *         @arg @ref LL_RCC_APB2_DIV_8\n  *         @arg @ref LL_RCC_APB2_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));\n}\n\n/**\n  * @brief  Set Clock After Wake-Up From Stop mode\n  * @rmtoll CFGR         STOPWUCK      LL_RCC_SetClkAfterWakeFromStop\n  * @param  Clock This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI\n  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);\n}\n\n/**\n  * @brief  Get Clock After Wake-Up From Stop mode\n  * @rmtoll CFGR         STOPWUCK      LL_RCC_GetClkAfterWakeFromStop\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI\n  *         @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_MCO MCO\n  * @{\n  */\n\n/**\n  * @brief  Configure MCOx\n  * @rmtoll CFGR         MCOSEL        LL_RCC_ConfigMCO\\n\n  *         CFGR         MCOPRE        LL_RCC_ConfigMCO\n  * @param  MCOxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK\n  *         @arg @ref LL_RCC_MCO1SOURCE_SYSCLK\n  *         @arg @ref LL_RCC_MCO1SOURCE_MSI\n  *         @arg @ref LL_RCC_MCO1SOURCE_HSI\n  *         @arg @ref LL_RCC_MCO1SOURCE_HSE\n  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)\n  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK\n  *         @arg @ref LL_RCC_MCO1SOURCE_LSI\n  *         @arg @ref LL_RCC_MCO1SOURCE_LSE\n  *\n  *         (*) value not defined in all devices.\n  * @param  MCOxPrescaler This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_MCO1_DIV_1\n  *         @arg @ref LL_RCC_MCO1_DIV_2\n  *         @arg @ref LL_RCC_MCO1_DIV_4\n  *         @arg @ref LL_RCC_MCO1_DIV_8\n  *         @arg @ref LL_RCC_MCO1_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)\n{\n  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source\n  * @{\n  */\n\n/**\n  * @brief  Configure USARTx clock source\n  * @rmtoll CCIPR        USARTxSEL     LL_RCC_SetUSARTClockSource\n  * @param  USARTxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)\n{\n  MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));\n}\n\n#if defined(UART4) || defined(UART5)\n/**\n  * @brief  Configure UARTx clock source\n  * @rmtoll CCIPR        UARTxSEL      LL_RCC_SetUARTClockSource\n  * @param  UARTxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)\n{\n  MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));\n}\n#endif /* UART4 || UART5 */\n\n/**\n  * @brief  Configure LPUART1x clock source\n  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_SetLPUARTClockSource\n  * @param  LPUARTxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)\n{\n  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);\n}\n\n/**\n  * @brief  Configure I2Cx clock source\n  * @rmtoll CCIPR        I2CxSEL       LL_RCC_SetI2CClockSource\n  * @param  I2CxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)\n  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)\n  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)\n  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)\n  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)\n  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)\n{\n  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));\n  MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));\n}\n\n/**\n  * @brief  Configure LPTIMx clock source\n  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_SetLPTIMClockSource\n  * @param  LPTIMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)\n{\n  MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));\n}\n\n#if defined(RCC_CCIPR_SAI1SEL)\n/**\n  * @brief  Configure SAIx clock source\n  @if STM32L4S9xx\n  * @rmtoll CCIPR2       SAIxSEL       LL_RCC_SetSAIClockSource\n  @else\n  * @rmtoll CCIPR        SAIxSEL       LL_RCC_SetSAIClockSource\n  @endif\n  * @param  SAIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)\n{\n#if defined(RCC_CCIPR2_SAI1SEL)\n  MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));\n#else\n  MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));\n#endif /* RCC_CCIPR2_SAI1SEL */\n}\n#endif /* RCC_CCIPR_SAI1SEL */\n\n#if defined(RCC_CCIPR2_SDMMCSEL)\n/**\n  * @brief  Configure SDMMC1 kernel clock source\n  * @rmtoll CCIPR2       SDMMCSEL      LL_RCC_SetSDMMCKernelClockSource\n  * @param  SDMMCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK\n  *         @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)\n{\n  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);\n}\n#endif /* RCC_CCIPR2_SDMMCSEL */\n\n/**\n  * @brief  Configure SDMMC1 clock source\n  * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetSDMMCClockSource\n  * @param  SDMMCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)\n{\n  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);\n}\n\n/**\n  * @brief  Configure RNG clock source\n  * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetRNGClockSource\n  * @param  RNGxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_MSI\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)\n{\n  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);\n}\n\n#if defined(USB_OTG_FS) || defined(USB)\n/**\n  * @brief  Configure USB clock source\n  * @rmtoll CCIPR        CLK48SEL      LL_RCC_SetUSBClockSource\n  * @param  USBxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)\n{\n  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);\n}\n#endif /* USB_OTG_FS || USB */\n\n#if defined(RCC_CCIPR_ADCSEL)\n/**\n  * @brief  Configure ADC clock source\n  * @rmtoll CCIPR        ADCSEL        LL_RCC_SetADCClockSource\n  * @param  ADCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)\n{\n  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);\n}\n#endif /* RCC_CCIPR_ADCSEL */\n\n#if defined(SWPMI1)\n/**\n  * @brief  Configure SWPMI clock source\n  * @rmtoll CCIPR        SWPMI1SEL     LL_RCC_SetSWPMIClockSource\n  * @param  SWPMIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)\n{\n  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);\n}\n#endif /* SWPMI1 */\n\n#if defined(DFSDM1_Channel0)\n#if defined(RCC_CCIPR2_ADFSDM1SEL)\n/**\n  * @brief  Configure DFSDM Audio clock source\n  * @rmtoll CCIPR2        ADFSDM1SEL        LL_RCC_SetDFSDMAudioClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);\n}\n#endif /* RCC_CCIPR2_ADFSDM1SEL */\n\n/**\n  * @brief  Configure DFSDM Kernel clock source\n  @if STM32L4S9xx\n  * @rmtoll CCIPR2       DFSDM1SEL     LL_RCC_SetDFSDMClockSource\n  @else\n  * @rmtoll CCIPR        DFSDM1SEL     LL_RCC_SetDFSDMClockSource\n  @endif\n  * @param  DFSDMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)\n{\n#if defined(RCC_CCIPR2_DFSDM1SEL)\n  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);\n#else\n  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);\n#endif /* RCC_CCIPR2_DFSDM1SEL */\n}\n#endif /* DFSDM1_Channel0 */\n\n#if defined(DSI)\n/**\n  * @brief  Configure DSI clock source\n  * @rmtoll CCIPR2         DSISEL        LL_RCC_SetDSIClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);\n}\n#endif /* DSI */\n\n#if defined(LTDC)\n/**\n  * @brief  Configure LTDC Clock Source\n  * @rmtoll CCIPR2         PLLSAI2DIVR        LL_RCC_SetLTDCClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16\n  * @retval None\n */\n__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);\n}\n#endif /* LTDC */\n\n#if defined(OCTOSPI1)\n/**\n  * @brief  Configure OCTOSPI clock source\n  * @rmtoll CCIPR2         OSPISEL        LL_RCC_SetOCTOSPIClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI\n  *         @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);\n}\n#endif /* OCTOSPI1 */\n\n/**\n  * @brief  Get USARTx clock source\n  * @rmtoll CCIPR        USARTxSEL     LL_RCC_GetUSARTClockSource\n  * @param  USARTx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));\n}\n\n#if defined(UART4) || defined(UART5)\n/**\n  * @brief  Get UARTx clock source\n  * @rmtoll CCIPR        UARTxSEL      LL_RCC_GetUARTClockSource\n  * @param  UARTx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE_LSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));\n}\n#endif /* UART4 || UART5 */\n\n/**\n  * @brief  Get LPUARTx clock source\n  * @rmtoll CCIPR        LPUART1SEL    LL_RCC_GetLPUARTClockSource\n  * @param  LPUARTx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));\n}\n\n/**\n  * @brief  Get I2Cx clock source\n  * @rmtoll CCIPR        I2CxSEL       LL_RCC_GetI2CClockSource\n  * @param  I2Cx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2C1_CLKSOURCE\n  *         @arg @ref LL_RCC_I2C2_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_I2C3_CLKSOURCE\n  *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)\n  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)\n  *         @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)\n  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)\n  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)\n  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)\n  *\n  *         (*) value not defined in all devices.\n */\n__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)\n{\n  __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));\n  return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));\n}\n\n/**\n  * @brief  Get LPTIMx clock source\n  * @rmtoll CCIPR        LPTIMxSEL     LL_RCC_GetLPTIMClockSource\n  * @param  LPTIMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U | LPTIMx);\n}\n\n#if defined(RCC_CCIPR_SAI1SEL)\n/**\n  * @brief  Get SAIx clock source\n  * @rmtoll CCIPR        SAIxSEL       LL_RCC_GetSAIClockSource\n  * @param  SAIx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)\n{\n#if defined(RCC_CCIPR2_SAI1SEL)\n  return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U));\n#else\n  return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U | SAIx);\n#endif /* RCC_CCIPR2_SAI1SEL */\n}\n#endif /* RCC_CCIPR_SAI1SEL */\n\n#if defined(RCC_CCIPR2_SDMMCSEL)\n/**\n  * @brief  Get SDMMCx kernel clock source\n  * @rmtoll CCIPR2       SDMMCSEL      LL_RCC_GetSDMMCKernelClockSource\n  * @param  SDMMCx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)\n  *         @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));\n}\n#endif /* RCC_CCIPR2_SDMMCSEL */\n\n#if defined(SDMMC1)\n/**\n  * @brief  Get SDMMCx clock source\n  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetSDMMCClockSource\n  * @param  SDMMCx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));\n}\n#endif /* SDMMC1 */\n\n/**\n  * @brief  Get RNGx clock source\n  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetRNGClockSource\n  * @param  RNGx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE_MSI\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));\n}\n\n#if defined(USB_OTG_FS) || defined(USB)\n/**\n  * @brief  Get USBx clock source\n  * @rmtoll CCIPR        CLK48SEL      LL_RCC_GetUSBClockSource\n  * @param  USBx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL\n  *         @arg @ref LL_RCC_USB_CLKSOURCE_MSI\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));\n}\n#endif /* USB_OTG_FS || USB */\n\n/**\n  * @brief  Get ADCx clock source\n  * @rmtoll CCIPR        ADCSEL        LL_RCC_GetADCClockSource\n  * @param  ADCx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE_NONE\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1 (*)\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)\n{\n#if defined(RCC_CCIPR_ADCSEL)\n  return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));\n#else\n  return ((READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) ? LL_RCC_ADC_CLKSOURCE_SYSCLK : LL_RCC_ADC_CLKSOURCE_NONE);\n#endif /* RCC_CCIPR_ADCSEL */\n}\n\n#if defined(SWPMI1)\n/**\n  * @brief  Get SWPMIx clock source\n  * @rmtoll CCIPR        SWPMI1SEL     LL_RCC_GetSWPMIClockSource\n  * @param  SPWMIx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1\n  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));\n}\n#endif /* SWPMI1 */\n\n#if defined(DFSDM1_Channel0)\n#if defined(RCC_CCIPR2_ADFSDM1SEL)\n/**\n  * @brief  Get DFSDM Audio Clock Source\n  * @rmtoll CCIPR2         ADFSDM1SEL        LL_RCC_GetDFSDMAudioClockSource\n  * @param  DFSDMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));\n}\n#endif /* RCC_CCIPR2_ADFSDM1SEL */\n\n/**\n  * @brief  Get DFSDMx Kernel clock source\n  @if STM32L4S9xx\n  * @rmtoll CCIPR2       DFSDM1SEL     LL_RCC_GetDFSDMClockSource\n  @else\n  * @rmtoll CCIPR        DFSDM1SEL     LL_RCC_GetDFSDMClockSource\n  @endif\n  * @param  DFSDMx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)\n{\n#if defined(RCC_CCIPR2_DFSDM1SEL)\n  return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));\n#else\n  return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));\n#endif /* RCC_CCIPR2_DFSDM1SEL */\n}\n#endif /* DFSDM1_Channel0 */\n\n#if defined(DSI)\n/**\n  * @brief  Get DSI Clock Source\n  * @rmtoll CCIPR2         DSISEL        LL_RCC_GetDSIClockSource\n  * @param  DSIx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));\n}\n#endif /* DSI */\n\n#if defined(LTDC)\n/**\n  * @brief  Get LTDC Clock Source\n  * @rmtoll CCIPR2         PLLSAI2DIVR        LL_RCC_GetLTDCClockSource\n  * @param  LTDCx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));\n}\n#endif /* LTDC */\n\n#if defined(OCTOSPI1)\n/**\n  * @brief  Get OCTOSPI clock source\n  * @rmtoll CCIPR2         OSPISEL        LL_RCC_GetOCTOSPIClockSource\n  * @param  OCTOSPIx This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_OCTOSPI_CLKSOURCE\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK\n  *         @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI\n  *         @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));\n}\n#endif /* OCTOSPI1 */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_RTC RTC\n  * @{\n  */\n\n/**\n  * @brief  Set RTC Clock Source\n  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless\n  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is\n  *       set). The BDRST bit can be used to reset them.\n  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)\n{\n  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);\n}\n\n/**\n  * @brief  Get RTC Clock Source\n  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI\n  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32\n  */\n__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));\n}\n\n/**\n  * @brief  Enable RTC\n  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableRTC(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);\n}\n\n/**\n  * @brief  Disable RTC\n  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableRTC(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);\n}\n\n/**\n  * @brief  Check if RTC has been enabled or not\n  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)\n{\n  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));\n}\n\n/**\n  * @brief  Force the Backup domain reset\n  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)\n{\n  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);\n}\n\n/**\n  * @brief  Release the Backup domain reset\n  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)\n{\n  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);\n}\n\n/**\n  * @}\n  */\n\n\n/** @defgroup RCC_LL_EF_PLL PLL\n  * @{\n  */\n\n/**\n  * @brief  Enable PLL\n  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLON);\n}\n\n/**\n  * @brief  Disable PLL\n  * @note Cannot be disabled if the PLL clock is used as the system clock\n  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);\n}\n\n/**\n  * @brief  Check if PLL Ready\n  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));\n}\n\n/**\n  * @brief  Configure PLL used for SYSCLK Domain\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLN/PLLR can be written only when PLL is disabled.\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\\n\n  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_16 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLN Between 8 and 86\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);\n}\n\n#if defined(RCC_PLLP_SUPPORT)\n#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\n/**\n  * @brief  Configure PLL used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLN/PLLP can be written only when PLL is disabled.\n  * @note This  can be selected for SAI1 or SAI2 (*)\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLPDIV       LL_RCC_PLL_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_16 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLN Between 8 and 86\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_3\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_5\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_7\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  *         @arg @ref LL_RCC_PLLP_DIV_9\n  *         @arg @ref LL_RCC_PLLP_DIV_10\n  *         @arg @ref LL_RCC_PLLP_DIV_11\n  *         @arg @ref LL_RCC_PLLP_DIV_12\n  *         @arg @ref LL_RCC_PLLP_DIV_13\n  *         @arg @ref LL_RCC_PLLP_DIV_14\n  *         @arg @ref LL_RCC_PLLP_DIV_15\n  *         @arg @ref LL_RCC_PLLP_DIV_16\n  *         @arg @ref LL_RCC_PLLP_DIV_17\n  *         @arg @ref LL_RCC_PLLP_DIV_18\n  *         @arg @ref LL_RCC_PLLP_DIV_19\n  *         @arg @ref LL_RCC_PLLP_DIV_20\n  *         @arg @ref LL_RCC_PLLP_DIV_21\n  *         @arg @ref LL_RCC_PLLP_DIV_22\n  *         @arg @ref LL_RCC_PLLP_DIV_23\n  *         @arg @ref LL_RCC_PLLP_DIV_24\n  *         @arg @ref LL_RCC_PLLP_DIV_25\n  *         @arg @ref LL_RCC_PLLP_DIV_26\n  *         @arg @ref LL_RCC_PLLP_DIV_27\n  *         @arg @ref LL_RCC_PLLP_DIV_28\n  *         @arg @ref LL_RCC_PLLP_DIV_29\n  *         @arg @ref LL_RCC_PLLP_DIV_30\n  *         @arg @ref LL_RCC_PLLP_DIV_31\n  * @retval None\n  */\n#else\n/**\n  * @brief  Configure PLL used for SAI domain clock\n  * @note   PLL Source and PLLM Divider can be written only when PLL,\n  *         PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note   PLLN/PLLP can be written only when PLL is disabled.\n  * @note   This  can be selected for SAI1 or SAI2 (*)\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  PLLN Between 8 and 86\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_7\n  *         @arg @ref LL_RCC_PLLP_DIV_17\n  * @retval None\n  */\n#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);\n#else\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);\n#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\n}\n#endif /* RCC_PLLP_SUPPORT */\n\n/**\n  * @brief  Configure PLL used for 48Mhz domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLN/PLLQ can be written only when PLL is disabled.\n  * @note This  can be selected for USB, RNG, SDMMC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_16 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @param  PLLN Between 8 and 86\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,\n             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);\n}\n\n/**\n  * @brief  Get Main PLL multiplication factor for VCO\n  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN\n  * @retval Between 8 and 86\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);\n}\n\n#if defined(RCC_PLLP_SUPPORT)\n#if defined(RCC_PLLP_DIV_2_31_SUPPORT)\n/**\n  * @brief  Get Main PLL division factor for PLLP\n  * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)\n  * @rmtoll PLLCFGR      PLLPDIV       LL_RCC_PLL_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_2\n  *         @arg @ref LL_RCC_PLLP_DIV_3\n  *         @arg @ref LL_RCC_PLLP_DIV_4\n  *         @arg @ref LL_RCC_PLLP_DIV_5\n  *         @arg @ref LL_RCC_PLLP_DIV_6\n  *         @arg @ref LL_RCC_PLLP_DIV_7\n  *         @arg @ref LL_RCC_PLLP_DIV_8\n  *         @arg @ref LL_RCC_PLLP_DIV_9\n  *         @arg @ref LL_RCC_PLLP_DIV_10\n  *         @arg @ref LL_RCC_PLLP_DIV_11\n  *         @arg @ref LL_RCC_PLLP_DIV_12\n  *         @arg @ref LL_RCC_PLLP_DIV_13\n  *         @arg @ref LL_RCC_PLLP_DIV_14\n  *         @arg @ref LL_RCC_PLLP_DIV_15\n  *         @arg @ref LL_RCC_PLLP_DIV_16\n  *         @arg @ref LL_RCC_PLLP_DIV_17\n  *         @arg @ref LL_RCC_PLLP_DIV_18\n  *         @arg @ref LL_RCC_PLLP_DIV_19\n  *         @arg @ref LL_RCC_PLLP_DIV_20\n  *         @arg @ref LL_RCC_PLLP_DIV_21\n  *         @arg @ref LL_RCC_PLLP_DIV_22\n  *         @arg @ref LL_RCC_PLLP_DIV_23\n  *         @arg @ref LL_RCC_PLLP_DIV_24\n  *         @arg @ref LL_RCC_PLLP_DIV_25\n  *         @arg @ref LL_RCC_PLLP_DIV_26\n  *         @arg @ref LL_RCC_PLLP_DIV_27\n  *         @arg @ref LL_RCC_PLLP_DIV_28\n  *         @arg @ref LL_RCC_PLLP_DIV_29\n  *         @arg @ref LL_RCC_PLLP_DIV_30\n  *         @arg @ref LL_RCC_PLLP_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));\n}\n#else\n/**\n  * @brief  Get Main PLL division factor for PLLP\n  * @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)\n  * @rmtoll PLLCFGR      PLLP          LL_RCC_PLL_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLP_DIV_7\n  *         @arg @ref LL_RCC_PLLP_DIV_17\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));\n}\n#endif /* RCC_PLLP_DIV_2_31_SUPPORT */\n#endif /* RCC_PLLP_SUPPORT */\n\n/**\n  * @brief  Get Main PLL division factor for PLLQ\n  * @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)\n  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLQ_DIV_2\n  *         @arg @ref LL_RCC_PLLQ_DIV_4\n  *         @arg @ref LL_RCC_PLLQ_DIV_6\n  *         @arg @ref LL_RCC_PLLQ_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));\n}\n\n/**\n  * @brief  Get Main PLL division factor for PLLR\n  * @note Used for PLLCLK (system clock)\n  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLR_DIV_2\n  *         @arg @ref LL_RCC_PLLR_DIV_4\n  *         @arg @ref LL_RCC_PLLR_DIV_6\n  *         @arg @ref LL_RCC_PLLR_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));\n}\n\n/**\n  * @brief  Get the oscillator used as PLL clock source.\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));\n}\n\n/**\n  * @brief  Get Division factor for the main PLL and other PLL\n  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  *         @arg @ref LL_RCC_PLLM_DIV_9 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_10 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_11 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_12 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_13 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_14 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_15 (*)\n  *         @arg @ref LL_RCC_PLLM_DIV_16 (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));\n}\n\n#if defined(RCC_PLLP_SUPPORT)\n/**\n  * @brief  Enable PLL output mapped on SAI domain clock\n  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_EnableDomain_SAI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)\n{\n  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);\n}\n\n/**\n  * @brief  Disable PLL output mapped on SAI domain clock\n  * @note Cannot be disabled if the PLL clock is used as the system\n  *       clock\n  * @note In order to save power, when the PLLCLK  of the PLL is\n  *       not used,  should be 0\n  * @rmtoll PLLCFGR      PLLPEN        LL_RCC_PLL_DisableDomain_SAI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)\n{\n  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);\n}\n#endif /* RCC_PLLP_SUPPORT */\n\n/**\n  * @brief  Enable PLL output mapped on 48MHz domain clock\n  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_EnableDomain_48M\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)\n{\n  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);\n}\n\n/**\n  * @brief  Disable PLL output mapped on 48MHz domain clock\n  * @note Cannot be disabled if the PLL clock is used as the system\n  *       clock\n  * @note In order to save power, when the PLLCLK  of the PLL is\n  *       not used,  should be 0\n  * @rmtoll PLLCFGR      PLLQEN        LL_RCC_PLL_DisableDomain_48M\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)\n{\n  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);\n}\n\n/**\n  * @brief  Enable PLL output mapped on SYSCLK domain\n  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_EnableDomain_SYS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)\n{\n  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);\n}\n\n/**\n  * @brief  Disable PLL output mapped on SYSCLK domain\n  * @note Cannot be disabled if the PLL clock is used as the system\n  *       clock\n  * @note In order to save power, when the PLLCLK  of the PLL is\n  *       not used, Main PLL  should be 0\n  * @rmtoll PLLCFGR      PLLREN        LL_RCC_PLL_DisableDomain_SYS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)\n{\n  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);\n}\n\n/**\n  * @}\n  */\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1\n  * @{\n  */\n\n/**\n  * @brief  Enable PLLSAI1\n  * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);\n}\n\n/**\n  * @brief  Disable PLLSAI1\n  * @rmtoll CR           PLLSAI1ON     LL_RCC_PLLSAI1_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);\n}\n\n/**\n  * @brief  Check if PLLSAI1 Ready\n  * @rmtoll CR           PLLSAI1RDY    LL_RCC_PLLSAI1_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));\n}\n\n#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\n/**\n  * @brief  Configure PLLSAI1 used for 48Mhz domain clock\n  * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.\n  * @note This  can be selected for USB, RNG, SDMMC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_48M\\n\n  *         PLLSAI1CFGR  PLLSAI1M      LL_RCC_PLLSAI1_ConfigDomain_48M\\n\n  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_48M\\n\n  *         PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_16\n  * @param  PLLN Between 8 and 86\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,\n             PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);\n}\n#else\n/**\n  * @brief  Configure PLLSAI1 used for 48Mhz domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.\n  * @note This  can be selected for USB, RNG, SDMMC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_48M\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_48M\\n\n  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_48M\\n\n  *         PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_ConfigDomain_48M\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  PLLN Between 8 and 86\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLQ);\n}\n#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\n\n#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Configure PLLSAI1 used for SAI domain clock\n  * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.\n  * @note This  can be selected for SAI1 or SAI2\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLSAI1CFGR  PLLSAI1M      LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLSAI1CFGR  PLLSAI1PDIV   LL_RCC_PLLSAI1_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_16\n  * @param  PLLN Between 8 and 86\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,\n             PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);\n}\n#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Configure PLLSAI1 used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.\n  * @note This  can be selected for SAI1 or SAI2 (*)\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLSAI1CFGR  PLLSAI1PDIV   LL_RCC_PLLSAI1_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  PLLN Between 8 and 86\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,\n             PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);\n}\n#else\n/**\n  * @brief  Configure PLLSAI1 used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.\n  * @note This  can be selected for SAI1 or SAI2 (*)\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_SAI\\n\n  *         PLLSAI1CFGR  PLLSAI1P      LL_RCC_PLLSAI1_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  PLLN Between 8 and 86\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLP);\n}\n#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */\n\n#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\n/**\n  * @brief  Configure PLLSAI1 used for ADC domain clock\n  * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.\n  * @note This  can be selected for ADC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_ADC\\n\n  *         PLLSAI1CFGR  PLLSAI1M      LL_RCC_PLLSAI1_ConfigDomain_ADC\\n\n  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_ADC\\n\n  *         PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_ConfigDomain_ADC\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_16\n  * @param  PLLN Between 8 and 86\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,\n             PLLM | PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);\n}\n#else\n/**\n  * @brief  Configure PLLSAI1 used for ADC domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLN/PLLR can be written only when PLLSAI1 is disabled.\n  * @note This  can be selected for ADC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI1_ConfigDomain_ADC\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI1_ConfigDomain_ADC\\n\n  *         PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_ConfigDomain_ADC\\n\n  *         PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_ConfigDomain_ADC\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  PLLN Between 8 and 86\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos | PLLR);\n}\n#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\n\n/**\n  * @brief  Get SAI1PLL multiplication factor for VCO\n  * @rmtoll PLLSAI1CFGR  PLLSAI1N      LL_RCC_PLLSAI1_GetN\n  * @retval Between 8 and 86\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);\n}\n\n#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Get SAI1PLL division factor for PLLSAI1P\n  * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).\n  * @rmtoll PLLSAI1CFGR  PLLSAI1PDIV      LL_RCC_PLLSAI1_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));\n}\n#else\n/**\n  * @brief  Get SAI1PLL division factor for PLLSAI1P\n  * @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).\n  * @rmtoll PLLSAI1CFGR  PLLSAI1P      LL_RCC_PLLSAI1_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1P_DIV_17\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));\n}\n#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */\n\n/**\n  * @brief  Get SAI1PLL division factor for PLLSAI1Q\n  * @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)\n  * @rmtoll PLLSAI1CFGR  PLLSAI1Q      LL_RCC_PLLSAI1_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1Q_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));\n}\n\n/**\n  * @brief  Get PLLSAI1 division factor for PLLSAIR\n  * @note Used for PLLADC1CLK (ADC clock)\n  * @rmtoll PLLSAI1CFGR  PLLSAI1R      LL_RCC_PLLSAI1_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1R_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));\n}\n\n#if  defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)\n/**\n  * @brief  Get Division factor for the PLLSAI1\n  * @rmtoll PLLSAI1CFGR  PLLSAI1M      LL_RCC_PLLSAI1_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI1M_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));\n}\n#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */\n\n/**\n  * @brief  Enable PLLSAI1 output mapped on SAI domain clock\n  * @rmtoll PLLSAI1CFGR  PLLSAI1PEN    LL_RCC_PLLSAI1_EnableDomain_SAI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)\n{\n  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);\n}\n\n/**\n  * @brief  Disable PLLSAI1 output mapped on SAI domain clock\n  * @note In order to save power, when  of the PLLSAI1 is\n  *       not used,  should be 0\n  * @rmtoll PLLSAI1CFGR  PLLSAI1PEN    LL_RCC_PLLSAI1_DisableDomain_SAI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)\n{\n  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);\n}\n\n/**\n  * @brief  Enable PLLSAI1 output mapped on 48MHz domain clock\n  * @rmtoll PLLSAI1CFGR  PLLSAI1QEN    LL_RCC_PLLSAI1_EnableDomain_48M\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)\n{\n  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);\n}\n\n/**\n  * @brief  Disable PLLSAI1 output mapped on 48MHz domain clock\n  * @note In order to save power, when  of the PLLSAI1 is\n  *       not used,  should be 0\n  * @rmtoll PLLSAI1CFGR  PLLSAI1QEN    LL_RCC_PLLSAI1_DisableDomain_48M\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)\n{\n  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);\n}\n\n/**\n  * @brief  Enable PLLSAI1 output mapped on ADC domain clock\n  * @rmtoll PLLSAI1CFGR  PLLSAI1REN    LL_RCC_PLLSAI1_EnableDomain_ADC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)\n{\n  SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);\n}\n\n/**\n  * @brief  Disable PLLSAI1 output mapped on ADC domain clock\n  * @note In order to save power, when  of the PLLSAI1 is\n  *       not used, Main PLLSAI1  should be 0\n  * @rmtoll PLLSAI1CFGR  PLLSAI1REN    LL_RCC_PLLSAI1_DisableDomain_ADC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)\n{\n  CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);\n}\n\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2\n  * @{\n  */\n\n/**\n  * @brief  Enable PLLSAI2\n  * @rmtoll CR           PLLSAI2ON     LL_RCC_PLLSAI2_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)\n{\n  SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);\n}\n\n/**\n  * @brief  Disable PLLSAI2\n  * @rmtoll CR           PLLSAI2ON     LL_RCC_PLLSAI2_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)\n{\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);\n}\n\n/**\n  * @brief  Check if PLLSAI2 Ready\n  * @rmtoll CR           PLLSAI2RDY    LL_RCC_PLLSAI2_IsReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)\n{\n  return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));\n}\n\n#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Configure PLLSAI2 used for SAI domain clock\n  * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.\n  * @note This  can be selected for SAI1 or SAI2\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLSAI2CFGR  PLLSAI2M      LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLSAI2CFGR  PLLSAI2PDIV   LL_RCC_PLLSAI2_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_16\n  * @param  PLLN Between 8 and 86\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,\n             PLLM | PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);\n}\n#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Configure PLLSAI2 used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI1 and PLLSAI2 are disabled.\n  * @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.\n  * @note This  can be selected for SAI1 or SAI2\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLSAI2CFGR  PLLSAI2PDIV   LL_RCC_PLLSAI2_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  PLLN Between 8 and 86\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_31\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);\n}\n#else\n/**\n  * @brief  Configure PLLSAI2 used for SAI domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI2 and PLLSAI2 are disabled.\n  * @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.\n  * @note This  can be selected for SAI1 or SAI2\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_SAI\\n\n  *         PLLSAI2CFGR  PLLSAI2P      LL_RCC_PLLSAI2_ConfigDomain_SAI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  PLLN Between 8 and 86\n  * @param  PLLP This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLP);\n}\n#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */\n\n#if defined(DSI)\n/**\n  * @brief  Configure PLLSAI2 used for DSI domain clock\n  * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.\n  * @note This  can be selected for DSI\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_DSI\\n\n  *         PLLSAI2CFGR  PLLSAI2M      LL_RCC_PLLSAI2_ConfigDomain_DSI\\n\n  *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_DSI\\n\n  *         PLLSAI2CFGR  PLLSAI2Q      LL_RCC_PLLSAI2_ConfigDomain_DSI\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_16\n  * @param  PLLN Between 8 and 86\n  * @param  PLLQ This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLQ | PLLM);\n}\n#endif /* DSI */\n\n#if defined(LTDC)\n/**\n  * @brief  Configure PLLSAI2 used for LTDC domain clock\n  * @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.\n  * @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.\n  * @note This  can be selected for LTDC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_LTDC\\n\n  *         PLLSAI2CFGR  PLLSAI2M      LL_RCC_PLLSAI2_ConfigDomain_LTDC\\n\n  *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_LTDC\\n\n  *         PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_ConfigDomain_LTDC\\n\n  *         CCIPR2       PLLSAI2DIVR   LL_RCC_PLLSAI2_ConfigDomain_LTDC\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_16\n  * @param  PLLN Between 8 and 86\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_8\n  * @param  PLLDIVR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);\n  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR | PLLM);\n  MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);\n}\n#else\n/**\n  * @brief  Configure PLLSAI2 used for ADC domain clock\n  * @note PLL Source and PLLM Divider can be written only when PLL,\n  *       PLLSAI2 and PLLSAI2 are disabled.\n  * @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.\n  * @note This  can be selected for ADC\n  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI2_ConfigDomain_ADC\\n\n  *         PLLCFGR      PLLM          LL_RCC_PLLSAI2_ConfigDomain_ADC\\n\n  *         PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_ConfigDomain_ADC\\n\n  *         PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_ConfigDomain_ADC\n  * @param  Source This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSOURCE_NONE\n  *         @arg @ref LL_RCC_PLLSOURCE_MSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSI\n  *         @arg @ref LL_RCC_PLLSOURCE_HSE\n  * @param  PLLM This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLM_DIV_1\n  *         @arg @ref LL_RCC_PLLM_DIV_2\n  *         @arg @ref LL_RCC_PLLM_DIV_3\n  *         @arg @ref LL_RCC_PLLM_DIV_4\n  *         @arg @ref LL_RCC_PLLM_DIV_5\n  *         @arg @ref LL_RCC_PLLM_DIV_6\n  *         @arg @ref LL_RCC_PLLM_DIV_7\n  *         @arg @ref LL_RCC_PLLM_DIV_8\n  * @param  PLLN Between 8 and 86\n  * @param  PLLR This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)\n{\n  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);\n  MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos | PLLR);\n}\n#endif /* LTDC */\n\n/**\n  * @brief  Get SAI2PLL multiplication factor for VCO\n  * @rmtoll PLLSAI2CFGR  PLLSAI2N      LL_RCC_PLLSAI2_GetN\n  * @retval Between 8 and 86\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);\n}\n\n#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)\n/**\n  * @brief  Get SAI2PLL division factor for PLLSAI2P\n  * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).\n  * @rmtoll PLLSAI2CFGR  PLLSAI2PDIV    LL_RCC_PLLSAI2_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_16\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_18\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_19\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_20\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_21\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_22\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_23\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_24\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_25\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_26\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_27\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_28\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_29\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_30\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_31\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));\n}\n#else\n/**\n  * @brief  Get SAI2PLL division factor for PLLSAI2P\n  * @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).\n  * @rmtoll PLLSAI2CFGR  PLLSAI2P      LL_RCC_PLLSAI2_GetP\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2P_DIV_17\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));\n}\n#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */\n\n#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)\n/**\n  * @brief  Get division factor for PLLSAI2Q\n  * @note Used for PLLDSICLK (DSI clock)\n  * @rmtoll PLLSAI2CFGR  PLLSAI2Q      LL_RCC_PLLSAI2_GetQ\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2Q_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));\n}\n#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */\n\n/**\n  * @brief  Get SAI2PLL division factor for PLLSAI2R\n  * @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices\n  * @rmtoll PLLSAI2CFGR  PLLSAI2R      LL_RCC_PLLSAI2_GetR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2R_DIV_8\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));\n}\n\n#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\n/**\n  * @brief  Get Division factor for the PLLSAI2\n  * @rmtoll PLLSAI2CFGR  PLLSAI2M      LL_RCC_PLLSAI2_GetDivider\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_1\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_3\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_5\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_6\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_7\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_9\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_10\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_11\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_12\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_13\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_14\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_15\n  *         @arg @ref LL_RCC_PLLSAI2M_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)\n{\n  return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));\n}\n#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */\n\n#if defined(RCC_CCIPR2_PLLSAI2DIVR)\n/**\n  * @brief  Get PLLSAI2 division factor for PLLSAI2DIVR\n  * @note Used for LTDC domain clock\n  * @rmtoll CCIPR2  PLLSAI2DIVR      LL_RCC_PLLSAI2_GetDIVR\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8\n  *         @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16\n  */\n__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)\n{\n  return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));\n}\n#endif /* RCC_CCIPR2_PLLSAI2DIVR */\n\n/**\n  * @brief  Enable PLLSAI2 output mapped on SAI domain clock\n  * @rmtoll PLLSAI2CFGR  PLLSAI2PEN    LL_RCC_PLLSAI2_EnableDomain_SAI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)\n{\n  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);\n}\n\n/**\n  * @brief  Disable PLLSAI2 output mapped on SAI domain clock\n  * @note In order to save power, when  of the PLLSAI2 is\n  *       not used,  should be 0\n  * @rmtoll PLLSAI2CFGR  PLLSAI2PEN    LL_RCC_PLLSAI2_DisableDomain_SAI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)\n{\n  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);\n}\n\n#if defined(DSI)\n/**\n  * @brief  Enable PLLSAI2 output mapped on DSI domain clock\n  * @rmtoll PLLSAI2CFGR  PLLSAI2QEN    LL_RCC_PLLSAI2_EnableDomain_DSI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)\n{\n  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);\n}\n\n/**\n  * @brief  Disable PLLSAI2 output mapped on DSI domain clock\n  * @note In order to save power, when  of the PLLSAI2 is\n  *       not used, Main PLLSAI2  should be 0\n  * @rmtoll PLLSAI2CFGR  PLLSAI2QEN    LL_RCC_PLLSAI2_DisableDomain_DSI\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)\n{\n  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);\n}\n#endif /* DSI */\n\n#if defined(LTDC)\n/**\n  * @brief  Enable PLLSAI2 output mapped on LTDC domain clock\n  * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_EnableDomain_LTDC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)\n{\n  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);\n}\n\n/**\n  * @brief  Disable PLLSAI2 output mapped on LTDC domain clock\n  * @note In order to save power, when  of the PLLSAI2 is\n  *       not used, Main PLLSAI2  should be 0\n  * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_DisableDomain_LTDC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)\n{\n  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);\n}\n#else\n/**\n  * @brief  Enable PLLSAI2 output mapped on ADC domain clock\n  * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_EnableDomain_ADC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)\n{\n  SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);\n}\n\n/**\n  * @brief  Disable PLLSAI2 output mapped on ADC domain clock\n  * @note In order to save power, when  of the PLLSAI2 is\n  *       not used, Main PLLSAI2  should be 0\n  * @rmtoll PLLSAI2CFGR  PLLSAI2REN    LL_RCC_PLLSAI2_DisableDomain_ADC\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)\n{\n  CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);\n}\n#endif /* LTDC */\n\n/**\n  * @}\n  */\n#endif /* RCC_PLLSAI2_SUPPORT */\n\n\n\n/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management\n  * @{\n  */\n\n/**\n  * @brief  Clear LSI ready interrupt flag\n  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);\n}\n\n/**\n  * @brief  Clear LSE ready interrupt flag\n  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);\n}\n\n/**\n  * @brief  Clear MSI ready interrupt flag\n  * @rmtoll CICR         MSIRDYC       LL_RCC_ClearFlag_MSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);\n}\n\n/**\n  * @brief  Clear HSI ready interrupt flag\n  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);\n}\n\n/**\n  * @brief  Clear HSE ready interrupt flag\n  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);\n}\n\n/**\n  * @brief  Clear PLL ready interrupt flag\n  * @rmtoll CICR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);\n}\n\n#if defined(RCC_HSI48_SUPPORT)\n/**\n  * @brief  Clear HSI48 ready interrupt flag\n  * @rmtoll CICR          HSI48RDYC     LL_RCC_ClearFlag_HSI48RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);\n}\n#endif /* RCC_HSI48_SUPPORT */\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n/**\n  * @brief  Clear PLLSAI1 ready interrupt flag\n  * @rmtoll CICR         PLLSAI1RDYC   LL_RCC_ClearFlag_PLLSAI1RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);\n}\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n/**\n  * @brief  Clear PLLSAI1 ready interrupt flag\n  * @rmtoll CICR         PLLSAI2RDYC   LL_RCC_ClearFlag_PLLSAI2RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);\n}\n#endif /* RCC_PLLSAI2_SUPPORT */\n\n/**\n  * @brief  Clear Clock security system interrupt flag\n  * @rmtoll CICR         CSSC          LL_RCC_ClearFlag_HSECSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_CSSC);\n}\n\n/**\n  * @brief  Clear LSE Clock security system interrupt flag\n  * @rmtoll CICR         LSECSSC       LL_RCC_ClearFlag_LSECSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)\n{\n  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);\n}\n\n/**\n  * @brief  Check if LSI ready interrupt occurred or not\n  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));\n}\n\n/**\n  * @brief  Check if LSE ready interrupt occurred or not\n  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));\n}\n\n/**\n  * @brief  Check if MSI ready interrupt occurred or not\n  * @rmtoll CIFR         MSIRDYF       LL_RCC_IsActiveFlag_MSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));\n}\n\n/**\n  * @brief  Check if HSI ready interrupt occurred or not\n  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));\n}\n\n/**\n  * @brief  Check if HSE ready interrupt occurred or not\n  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));\n}\n\n/**\n  * @brief  Check if PLL ready interrupt occurred or not\n  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));\n}\n\n#if defined(RCC_HSI48_SUPPORT)\n/**\n  * @brief  Check if HSI48 ready interrupt occurred or not\n  * @rmtoll CIR          HSI48RDYF     LL_RCC_IsActiveFlag_HSI48RDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));\n}\n#endif /* RCC_HSI48_SUPPORT */\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n/**\n  * @brief  Check if PLLSAI1 ready interrupt occurred or not\n  * @rmtoll CIFR         PLLSAI1RDYF   LL_RCC_IsActiveFlag_PLLSAI1RDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));\n}\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n/**\n  * @brief  Check if PLLSAI1 ready interrupt occurred or not\n  * @rmtoll CIFR         PLLSAI2RDYF   LL_RCC_IsActiveFlag_PLLSAI2RDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));\n}\n#endif /* RCC_PLLSAI2_SUPPORT */\n\n/**\n  * @brief  Check if Clock security system interrupt occurred or not\n  * @rmtoll CIFR         CSSF          LL_RCC_IsActiveFlag_HSECSS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));\n}\n\n/**\n  * @brief  Check if LSE Clock security system interrupt occurred or not\n  * @rmtoll CIFR         LSECSSF       LL_RCC_IsActiveFlag_LSECSS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)\n{\n  return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));\n}\n\n/**\n  * @brief  Check if RCC flag FW reset is set or not.\n  * @rmtoll CSR          FWRSTF        LL_RCC_IsActiveFlag_FWRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Independent Watchdog reset is set or not.\n  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Low Power reset is set or not.\n  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag is set or not.\n  * @rmtoll CSR          OBLRSTF       LL_RCC_IsActiveFlag_OBLRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Pin reset is set or not.\n  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Software reset is set or not.\n  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag Window Watchdog reset is set or not.\n  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));\n}\n\n/**\n  * @brief  Check if RCC flag BOR reset is set or not.\n  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)\n{\n  return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));\n}\n\n/**\n  * @brief  Set RMVF bit to clear the reset flags.\n  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_ClearResetFlags(void)\n{\n  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_IT_Management IT Management\n  * @{\n  */\n\n/**\n  * @brief  Enable LSI ready interrupt\n  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);\n}\n\n/**\n  * @brief  Enable LSE ready interrupt\n  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);\n}\n\n/**\n  * @brief  Enable MSI ready interrupt\n  * @rmtoll CIER         MSIRDYIE      LL_RCC_EnableIT_MSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);\n}\n\n/**\n  * @brief  Enable HSI ready interrupt\n  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);\n}\n\n/**\n  * @brief  Enable HSE ready interrupt\n  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);\n}\n\n/**\n  * @brief  Enable PLL ready interrupt\n  * @rmtoll CIER         PLLRDYIE      LL_RCC_EnableIT_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);\n}\n\n#if defined(RCC_HSI48_SUPPORT)\n/**\n  * @brief  Enable HSI48 ready interrupt\n  * @rmtoll CIER          HSI48RDYIE    LL_RCC_EnableIT_HSI48RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);\n}\n#endif /* RCC_HSI48_SUPPORT */\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n/**\n  * @brief  Enable PLLSAI1 ready interrupt\n  * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_EnableIT_PLLSAI1RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);\n}\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n/**\n  * @brief  Enable PLLSAI2 ready interrupt\n  * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_EnableIT_PLLSAI2RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);\n}\n#endif /* RCC_PLLSAI2_SUPPORT */\n\n/**\n  * @brief  Enable LSE clock security system interrupt\n  * @rmtoll CIER         LSECSSIE      LL_RCC_EnableIT_LSECSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)\n{\n  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);\n}\n\n/**\n  * @brief  Disable LSI ready interrupt\n  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);\n}\n\n/**\n  * @brief  Disable LSE ready interrupt\n  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);\n}\n\n/**\n  * @brief  Disable MSI ready interrupt\n  * @rmtoll CIER         MSIRDYIE      LL_RCC_DisableIT_MSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);\n}\n\n/**\n  * @brief  Disable HSI ready interrupt\n  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);\n}\n\n/**\n  * @brief  Disable HSE ready interrupt\n  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);\n}\n\n/**\n  * @brief  Disable PLL ready interrupt\n  * @rmtoll CIER         PLLRDYIE      LL_RCC_DisableIT_PLLRDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);\n}\n\n#if defined(RCC_HSI48_SUPPORT)\n/**\n  * @brief  Disable HSI48 ready interrupt\n  * @rmtoll CIER          HSI48RDYIE    LL_RCC_DisableIT_HSI48RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);\n}\n#endif /* RCC_HSI48_SUPPORT */\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n/**\n  * @brief  Disable PLLSAI1 ready interrupt\n  * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_DisableIT_PLLSAI1RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);\n}\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n/**\n  * @brief  Disable PLLSAI2 ready interrupt\n  * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_DisableIT_PLLSAI2RDY\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);\n}\n#endif /* RCC_PLLSAI2_SUPPORT */\n\n/**\n  * @brief  Disable LSE clock security system interrupt\n  * @rmtoll CIER         LSECSSIE      LL_RCC_DisableIT_LSECSS\n  * @retval None\n  */\n__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)\n{\n  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);\n}\n\n/**\n  * @brief  Checks if LSI ready interrupt source is enabled or disabled.\n  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));\n}\n\n/**\n  * @brief  Checks if LSE ready interrupt source is enabled or disabled.\n  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));\n}\n\n/**\n  * @brief  Checks if MSI ready interrupt source is enabled or disabled.\n  * @rmtoll CIER         MSIRDYIE      LL_RCC_IsEnabledIT_MSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));\n}\n\n/**\n  * @brief  Checks if HSI ready interrupt source is enabled or disabled.\n  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));\n}\n\n/**\n  * @brief  Checks if HSE ready interrupt source is enabled or disabled.\n  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));\n}\n\n/**\n  * @brief  Checks if PLL ready interrupt source is enabled or disabled.\n  * @rmtoll CIER         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));\n}\n\n#if defined(RCC_HSI48_SUPPORT)\n/**\n  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.\n  * @rmtoll CIER          HSI48RDYIE    LL_RCC_IsEnabledIT_HSI48RDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));\n}\n#endif /* RCC_HSI48_SUPPORT */\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n/**\n  * @brief  Checks if PLLSAI1 ready interrupt source is enabled or disabled.\n  * @rmtoll CIER         PLLSAI1RDYIE  LL_RCC_IsEnabledIT_PLLSAI1RDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));\n}\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n/**\n  * @brief  Checks if PLLSAI2 ready interrupt source is enabled or disabled.\n  * @rmtoll CIER         PLLSAI2RDYIE  LL_RCC_IsEnabledIT_PLLSAI2RDY\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));\n}\n#endif /* RCC_PLLSAI2_SUPPORT */\n\n/**\n  * @brief  Checks if LSECSS interrupt source is enabled or disabled.\n  * @rmtoll CIER         LSECSSIE      LL_RCC_IsEnabledIT_LSECSS\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)\n{\n  return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup RCC_LL_EF_Init De-initialization function\n  * @{\n  */\nErrorStatus LL_RCC_DeInit(void);\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions\n  * @{\n  */\nvoid        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);\nuint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);\n#if defined(UART4) || defined(UART5)\nuint32_t    LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);\n#endif /* UART4 || UART5 */\nuint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);\nuint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);\nuint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);\n#if defined(SAI1)\nuint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);\n#endif /* SAI1 */\n#if defined(RCC_CCIPR2_SDMMCSEL)\nuint32_t    LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);\n#endif\n#if defined(SDMMC1)\nuint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);\n#endif /* SDMMC1 */\nuint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);\n#if defined(USB_OTG_FS) || defined(USB)\nuint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);\n#endif /* USB_OTG_FS || USB */\nuint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);\n#if defined(SWPMI1)\nuint32_t    LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);\n#endif /* SWPMI1 */\n#if defined(DFSDM1_Channel0)\nuint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);\n#if defined(RCC_CCIPR2_DFSDM1SEL)\nuint32_t    LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);\n#endif /* RCC_CCIPR2_DFSDM1SEL */\n#endif /* DFSDM1_Channel0 */\n#if defined(LTDC)\nuint32_t    LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);\n#endif /* LTDC */\n#if defined(DSI)\nuint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);\n#endif /* DSI */\n#if defined(OCTOSPI1)\nuint32_t    LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);\n#endif /* OCTOSPI1 */\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_RCC_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_system.h\n  * @author  MCD Application Team\n  * @brief   Header file of SYSTEM LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL SYSTEM driver contains a set of generic APIs that can be\n    used by user:\n      (+) Some of the FLASH features need to be handled in the SYSTEM file.\n      (+) Access to DBGCMU registers\n      (+) Access to SYSCFG registers\n      (+) Access to VREFBUF registers\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_SYSTEM_H\n#define __STM32L4xx_LL_SYSTEM_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)\n\n/** @defgroup SYSTEM_LL SYSTEM\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants\n  * @{\n  */\n\n/**\n * @brief Power-down in Run mode Flash key\n */\n#define FLASH_PDKEY1                  0x04152637U /*!< Flash power down key1 */\n#define FLASH_PDKEY2                  0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 \n                                                       to unlock the RUN_PD bit in FLASH_ACR */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants\n  * @{\n  */\n\n/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP\n* @{\n*/\n#define LL_SYSCFG_REMAP_FLASH              0x00000000U                                           /*!< Main Flash memory mapped at 0x00000000              */\n#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */\n#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */\n#if defined(FMC_Bank1_R)\n#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */\n#endif /* FMC_Bank1_R */\n#define LL_SYSCFG_REMAP_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000                 */\n/**\n  * @}\n  */\n\n#if defined(SYSCFG_MEMRMP_FB_MODE)\n/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE\n  * @{\n  */\n#define LL_SYSCFG_BANKMODE_BANK1           0x00000000U               /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) \n                                                                      and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */\n#define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_MEMRMP_FB_MODE     /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) \n                                                                      and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */\n/**\n  * @}\n  */\n\n#endif /* SYSCFG_MEMRMP_FB_MODE */\n/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS\n  * @{\n  */\n#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */\n#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */\n#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)\n#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */\n#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */\n#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)\n#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */\n#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */\n#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */\n#if defined(I2C2)\n#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */\n#endif /* I2C2 */\n#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */\n#if defined(I2C4)\n#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4    SYSCFG_CFGR1_I2C4_FMP     /*!< Enable Fast Mode Plus on I2C4 pins */\n#endif /* I2C4 */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT\n  * @{\n  */\n#define LL_SYSCFG_EXTI_PORTA               0U                        /*!< EXTI PORT A                        */\n#define LL_SYSCFG_EXTI_PORTB               1U                        /*!< EXTI PORT B                        */\n#define LL_SYSCFG_EXTI_PORTC               2U                        /*!< EXTI PORT C                        */\n#define LL_SYSCFG_EXTI_PORTD               3U                        /*!< EXTI PORT D                        */\n#define LL_SYSCFG_EXTI_PORTE               4U                        /*!< EXTI PORT E                        */\n#if defined(GPIOF)\n#define LL_SYSCFG_EXTI_PORTF               5U                        /*!< EXTI PORT F                        */\n#endif /* GPIOF */\n#if defined(GPIOG)\n#define LL_SYSCFG_EXTI_PORTG               6U                        /*!< EXTI PORT G                        */\n#endif /* GPIOG */\n#define LL_SYSCFG_EXTI_PORTH               7U                        /*!< EXTI PORT H                        */\n#if defined(GPIOI)\n#define LL_SYSCFG_EXTI_PORTI               8U                        /*!< EXTI PORT I                        */\n#endif /* GPIOI */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE\n  * @{\n  */\n#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16U | 0U)  /* !< EXTI_POSITION_0  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16U | 0U)  /* !< EXTI_POSITION_4  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16U | 0U)  /* !< EXTI_POSITION_8  | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16U | 0U)  /* !< EXTI_POSITION_12 | EXTICR[0] */\n#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16U | 1U)  /* !< EXTI_POSITION_0  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16U | 1U)  /* !< EXTI_POSITION_4  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16U | 1U)  /* !< EXTI_POSITION_8  | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16U | 1U)  /* !< EXTI_POSITION_12 | EXTICR[1] */\n#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16U | 2U)  /* !< EXTI_POSITION_0  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16U | 2U)  /* !< EXTI_POSITION_4  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16U | 2U)  /* !< EXTI_POSITION_8  | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16U | 2U)  /* !< EXTI_POSITION_12 | EXTICR[2] */\n#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16U | 3U)  /* !< EXTI_POSITION_0  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16U | 3U)  /* !< EXTI_POSITION_4  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16U | 3U)  /* !< EXTI_POSITION_8  | EXTICR[3] */\n#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16U | 3U)  /* !< EXTI_POSITION_12 | EXTICR[3] */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK\n  * @{\n  */\n#define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal \n                                                                   with Break Input of TIM1/8/15/16/17                           */\n#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection \n                                                                   with TIM1/8/15/16/17 Break Input \n                                                                   and also the PVDE and PLS bits of the Power Control Interface */\n#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY    SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal \n                                                                   with Break Input of TIM1/8/15/16/17                           */\n#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4 \n                                                                   with Break Input of TIM1/15/16/17                             */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP\n  * @{\n  */\n#define LL_SYSCFG_SRAM2WRP_PAGE0           SYSCFG_SWPR_PAGE0  /*!< SRAM2 Write protection page 0  */\n#define LL_SYSCFG_SRAM2WRP_PAGE1           SYSCFG_SWPR_PAGE1  /*!< SRAM2 Write protection page 1  */\n#define LL_SYSCFG_SRAM2WRP_PAGE2           SYSCFG_SWPR_PAGE2  /*!< SRAM2 Write protection page 2  */\n#define LL_SYSCFG_SRAM2WRP_PAGE3           SYSCFG_SWPR_PAGE3  /*!< SRAM2 Write protection page 3  */\n#define LL_SYSCFG_SRAM2WRP_PAGE4           SYSCFG_SWPR_PAGE4  /*!< SRAM2 Write protection page 4  */\n#define LL_SYSCFG_SRAM2WRP_PAGE5           SYSCFG_SWPR_PAGE5  /*!< SRAM2 Write protection page 5  */\n#define LL_SYSCFG_SRAM2WRP_PAGE6           SYSCFG_SWPR_PAGE6  /*!< SRAM2 Write protection page 6  */\n#define LL_SYSCFG_SRAM2WRP_PAGE7           SYSCFG_SWPR_PAGE7  /*!< SRAM2 Write protection page 7  */\n#define LL_SYSCFG_SRAM2WRP_PAGE8           SYSCFG_SWPR_PAGE8  /*!< SRAM2 Write protection page 8  */\n#define LL_SYSCFG_SRAM2WRP_PAGE9           SYSCFG_SWPR_PAGE9  /*!< SRAM2 Write protection page 9  */\n#define LL_SYSCFG_SRAM2WRP_PAGE10          SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */\n#define LL_SYSCFG_SRAM2WRP_PAGE11          SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */\n#define LL_SYSCFG_SRAM2WRP_PAGE12          SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */\n#define LL_SYSCFG_SRAM2WRP_PAGE13          SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */\n#define LL_SYSCFG_SRAM2WRP_PAGE14          SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */\n#define LL_SYSCFG_SRAM2WRP_PAGE15          SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */\n#if defined(SYSCFG_SWPR_PAGE31)\n#define LL_SYSCFG_SRAM2WRP_PAGE16          SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */\n#define LL_SYSCFG_SRAM2WRP_PAGE17          SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */\n#define LL_SYSCFG_SRAM2WRP_PAGE18          SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */\n#define LL_SYSCFG_SRAM2WRP_PAGE19          SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */\n#define LL_SYSCFG_SRAM2WRP_PAGE20          SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */\n#define LL_SYSCFG_SRAM2WRP_PAGE21          SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */\n#define LL_SYSCFG_SRAM2WRP_PAGE22          SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */\n#define LL_SYSCFG_SRAM2WRP_PAGE23          SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */\n#define LL_SYSCFG_SRAM2WRP_PAGE24          SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */\n#define LL_SYSCFG_SRAM2WRP_PAGE25          SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */\n#define LL_SYSCFG_SRAM2WRP_PAGE26          SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */\n#define LL_SYSCFG_SRAM2WRP_PAGE27          SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */\n#define LL_SYSCFG_SRAM2WRP_PAGE28          SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */\n#define LL_SYSCFG_SRAM2WRP_PAGE29          SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */\n#define LL_SYSCFG_SRAM2WRP_PAGE30          SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */\n#define LL_SYSCFG_SRAM2WRP_PAGE31          SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */\n#endif /* SYSCFG_SWPR_PAGE31 */\n#if defined(SYSCFG_SWPR2_PAGE63)\n#define LL_SYSCFG_SRAM2WRP_PAGE32          SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */\n#define LL_SYSCFG_SRAM2WRP_PAGE33          SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */\n#define LL_SYSCFG_SRAM2WRP_PAGE34          SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */\n#define LL_SYSCFG_SRAM2WRP_PAGE35          SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */\n#define LL_SYSCFG_SRAM2WRP_PAGE36          SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */\n#define LL_SYSCFG_SRAM2WRP_PAGE37          SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */\n#define LL_SYSCFG_SRAM2WRP_PAGE38          SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */\n#define LL_SYSCFG_SRAM2WRP_PAGE39          SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */\n#define LL_SYSCFG_SRAM2WRP_PAGE40          SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */\n#define LL_SYSCFG_SRAM2WRP_PAGE41          SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */\n#define LL_SYSCFG_SRAM2WRP_PAGE42          SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */\n#define LL_SYSCFG_SRAM2WRP_PAGE43          SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */\n#define LL_SYSCFG_SRAM2WRP_PAGE44          SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */\n#define LL_SYSCFG_SRAM2WRP_PAGE45          SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */\n#define LL_SYSCFG_SRAM2WRP_PAGE46          SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */\n#define LL_SYSCFG_SRAM2WRP_PAGE47          SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */\n#define LL_SYSCFG_SRAM2WRP_PAGE48          SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */\n#define LL_SYSCFG_SRAM2WRP_PAGE49          SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */\n#define LL_SYSCFG_SRAM2WRP_PAGE50          SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */\n#define LL_SYSCFG_SRAM2WRP_PAGE51          SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */\n#define LL_SYSCFG_SRAM2WRP_PAGE52          SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */\n#define LL_SYSCFG_SRAM2WRP_PAGE53          SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */\n#define LL_SYSCFG_SRAM2WRP_PAGE54          SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */\n#define LL_SYSCFG_SRAM2WRP_PAGE55          SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */\n#define LL_SYSCFG_SRAM2WRP_PAGE56          SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */\n#define LL_SYSCFG_SRAM2WRP_PAGE57          SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */\n#define LL_SYSCFG_SRAM2WRP_PAGE58          SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */\n#define LL_SYSCFG_SRAM2WRP_PAGE59          SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */\n#define LL_SYSCFG_SRAM2WRP_PAGE60          SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */\n#define LL_SYSCFG_SRAM2WRP_PAGE61          SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */\n#define LL_SYSCFG_SRAM2WRP_PAGE62          SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */\n#define LL_SYSCFG_SRAM2WRP_PAGE63          SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */\n#endif /* SYSCFG_SWPR2_PAGE63 */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment\n  * @{\n  */\n#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */\n#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */\n#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP\n  * @{\n  */\n#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted*/\n#if defined(TIM3)\n#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR1_DBG_TIM3_STOP   /*!< The counter clock of TIM3 is stopped when the core is halted*/\n#endif /* TIM3 */\n#if defined(TIM4)\n#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR1_DBG_TIM4_STOP   /*!< The counter clock of TIM4 is stopped when the core is halted*/\n#endif /* TIM4 */\n#if defined(TIM5)\n#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR1_DBG_TIM5_STOP   /*!< The counter clock of TIM5 is stopped when the core is halted*/\n#endif /* TIM5 */\n#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR1_DBG_TIM6_STOP   /*!< The counter clock of TIM6 is stopped when the core is halted*/\n#if defined(TIM7)\n#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR1_DBG_TIM7_STOP   /*!< The counter clock of TIM7 is stopped when the core is halted*/\n#endif /* TIM7 */\n#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted*/\n#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted*/\n#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted*/\n#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen*/\n#if defined(I2C2)\n#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR1_DBG_I2C2_STOP   /*!< The I2C2 SMBus timeout is frozen*/\n#endif /* I2C2 */\n#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen*/\n#define LL_DBGMCU_APB1_GRP1_CAN_STOP       DBGMCU_APB1FZR1_DBG_CAN_STOP    /*!< The bxCAN receive registers are frozen*/\n#if defined(CAN2)\n#define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1FZR1_DBG_CAN2_STOP   /*!< The bxCAN2 receive registers are frozen*/\n#endif /* CAN2 */\n#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP\n  * @{\n  */\n#if defined(I2C4)\n#define LL_DBGMCU_APB1_GRP2_I2C4_STOP      DBGMCU_APB1FZR2_DBG_I2C4_STOP   /*!< The I2C4 SMBus timeout is frozen*/\n#endif /* I2C4 */\n#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP    DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/\n/**\n  * @}\n  */\n\n/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP\n  * @{\n  */\n#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ_DBG_TIM1_STOP     /*!< The counter clock of TIM1 is stopped when the core is halted*/\n#if defined(TIM8)\n#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ_DBG_TIM8_STOP     /*!< The counter clock of TIM8 is stopped when the core is halted*/\n#endif /* TIM8 */\n#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ_DBG_TIM15_STOP    /*!< The counter clock of TIM15 is stopped when the core is halted*/\n#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ_DBG_TIM16_STOP    /*!< The counter clock of TIM16 is stopped when the core is halted*/\n#if defined(TIM17)\n#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ_DBG_TIM17_STOP    /*!< The counter clock of TIM17 is stopped when the core is halted*/\n#endif /* TIM17 */\n/**\n  * @}\n  */\n\n#if defined(VREFBUF)\n/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE\n  * @{\n  */\n#define LL_VREFBUF_VOLTAGE_SCALE0          ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */\n#define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */\n/**\n  * @}\n  */\n#endif /* VREFBUF */\n\n/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY\n  * @{\n  */\n#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */\n#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */\n#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */\n#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */\n#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */\n#if defined(FLASH_ACR_LATENCY_5WS)\n#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */\n#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */\n#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */\n#define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */\n#define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */\n#define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS  /*!< FLASH ten wait states */\n#define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS  /*!< FLASH eleven wait states */\n#define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS  /*!< FLASH twelve wait states */\n#define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS  /*!< FLASH thirteen wait states */\n#define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS  /*!< FLASH fourteen wait states */\n#define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS  /*!< FLASH fifteen wait states */\n#endif\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions\n  * @{\n  */\n\n/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG\n  * @{\n  */\n\n/**\n  * @brief  Set memory mapping at address 0x00000000\n  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory\n  * @param  Memory This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_REMAP_FLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SRAM\n  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)\n  *         @arg @ref LL_SYSCFG_REMAP_QUADSPI\n  *\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)\n{\n  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);\n}\n\n/**\n  * @brief  Get memory mapping at address 0x00000000\n  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_REMAP_FLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH\n  *         @arg @ref LL_SYSCFG_REMAP_SRAM\n  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)\n  *         @arg @ref LL_SYSCFG_REMAP_QUADSPI\n  *\n  *         (*) value not defined in all devices\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));\n}\n\n#if defined(SYSCFG_MEMRMP_FB_MODE)\n/**\n  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)\n  * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode\n  * @param  Bank This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)\n{\n  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);\n}\n\n/**\n  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)\n  * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1\n  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));\n}\n#endif /* SYSCFG_MEMRMP_FB_MODE */\n\n/**\n  * @brief  Firewall protection enabled\n  * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_EnableFirewall\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);\n}\n\n/**\n  * @brief  Check if Firewall protection is enabled or not\n  * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_IsEnabledFirewall\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)\n{\n  return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);\n}\n\n/**\n  * @brief  Enable I/O analog switch voltage booster.\n  * @note   When voltage booster is enabled, I/O analog switches are supplied\n  *         by a dedicated voltage booster, from VDD power domain. This is\n  *         the recommended configuration with low VDDA voltage operation.\n  * @note   The I/O analog switch voltage booster is relevant for peripherals\n  *         using I/O in analog input: ADC, COMP, OPAMP.\n  *         However, COMP and OPAMP inputs have a high impedance and\n  *         voltage booster do not impact performance significantly.\n  *         Therefore, the voltage booster is mainly intended for\n  *         usage with ADC.\n  * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)\n{\n  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);\n}\n\n/**\n  * @brief  Disable I/O analog switch voltage booster.\n  * @note   When voltage booster is enabled, I/O analog switches are supplied\n  *         by a dedicated voltage booster, from VDD power domain. This is\n  *         the recommended configuration with low VDDA voltage operation.\n  * @note   The I/O analog switch voltage booster is relevant for peripherals\n  *         using I/O in analog input: ADC, COMP, OPAMP.\n  *         However, COMP and OPAMP inputs have a high impedance and\n  *         voltage booster do not impact performance significantly.\n  *         Therefore, the voltage booster is mainly intended for\n  *         usage with ADC.\n  * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);\n}\n\n/**\n  * @brief  Enable the I2C fast mode plus driving capability.\n  * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\\n\n  *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus\n  * @param  ConfigFastModePlus This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)\n  *\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)\n{\n  SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);\n}\n\n/**\n  * @brief  Disable the I2C fast mode plus driving capability.\n  * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\\n\n  *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus\n  * @param  ConfigFastModePlus This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3\n  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)\n  *\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);\n}\n\n/**\n  * @brief  Enable Floating Point Unit Invalid operation Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)\n{\n  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);\n}\n\n/**\n  * @brief  Enable Floating Point Unit Divide-by-zero Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)\n{\n  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);\n}\n\n/**\n  * @brief  Enable Floating Point Unit Underflow Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)\n{\n  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);\n}\n\n/**\n  * @brief  Enable Floating Point Unit Overflow Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)\n{\n  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);\n}\n\n/**\n  * @brief  Enable Floating Point Unit Input denormal Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)\n{\n  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);\n}\n\n/**\n  * @brief  Enable Floating Point Unit Inexact Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)\n{\n  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);\n}\n\n/**\n  * @brief  Disable Floating Point Unit Invalid operation Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);\n}\n\n/**\n  * @brief  Disable Floating Point Unit Divide-by-zero Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);\n}\n\n/**\n  * @brief  Disable Floating Point Unit Underflow Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);\n}\n\n/**\n  * @brief  Disable Floating Point Unit Overflow Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);\n}\n\n/**\n  * @brief  Disable Floating Point Unit Input denormal Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);\n}\n\n/**\n  * @brief  Disable Floating Point Unit Inexact Interrupt\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)\n{\n  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);\n}\n\n/**\n  * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)\n{\n  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));\n}\n\n/**\n  * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)\n{\n  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));\n}\n\n/**\n  * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)\n{\n  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));\n}\n\n/**\n  * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)\n{\n  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));\n}\n\n/**\n  * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)\n{\n  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));\n}\n\n/**\n  * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.\n  * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)\n{\n  return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));\n}\n\n/**\n  * @brief  Configure source input for the EXTI external interrupt.\n  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\\n\n  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource\n  * @param  Port This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_PORTA\n  *         @arg @ref LL_SYSCFG_EXTI_PORTB\n  *         @arg @ref LL_SYSCFG_EXTI_PORTC\n  *         @arg @ref LL_SYSCFG_EXTI_PORTD\n  *         @arg @ref LL_SYSCFG_EXTI_PORTE\n  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTH\n  *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)\n  *\n  *         (*) value not defined in all devices\n  * @param  Line This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_LINE0\n  *         @arg @ref LL_SYSCFG_EXTI_LINE1\n  *         @arg @ref LL_SYSCFG_EXTI_LINE2\n  *         @arg @ref LL_SYSCFG_EXTI_LINE3\n  *         @arg @ref LL_SYSCFG_EXTI_LINE4\n  *         @arg @ref LL_SYSCFG_EXTI_LINE5\n  *         @arg @ref LL_SYSCFG_EXTI_LINE6\n  *         @arg @ref LL_SYSCFG_EXTI_LINE7\n  *         @arg @ref LL_SYSCFG_EXTI_LINE8\n  *         @arg @ref LL_SYSCFG_EXTI_LINE9\n  *         @arg @ref LL_SYSCFG_EXTI_LINE10\n  *         @arg @ref LL_SYSCFG_EXTI_LINE11\n  *         @arg @ref LL_SYSCFG_EXTI_LINE12\n  *         @arg @ref LL_SYSCFG_EXTI_LINE13\n  *         @arg @ref LL_SYSCFG_EXTI_LINE14\n  *         @arg @ref LL_SYSCFG_EXTI_LINE15\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)\n{\n  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));\n}\n\n/**\n  * @brief  Get the configured defined for specific EXTI Line\n  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\\n\n  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource\n  * @param  Line This parameter can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_LINE0\n  *         @arg @ref LL_SYSCFG_EXTI_LINE1\n  *         @arg @ref LL_SYSCFG_EXTI_LINE2\n  *         @arg @ref LL_SYSCFG_EXTI_LINE3\n  *         @arg @ref LL_SYSCFG_EXTI_LINE4\n  *         @arg @ref LL_SYSCFG_EXTI_LINE5\n  *         @arg @ref LL_SYSCFG_EXTI_LINE6\n  *         @arg @ref LL_SYSCFG_EXTI_LINE7\n  *         @arg @ref LL_SYSCFG_EXTI_LINE8\n  *         @arg @ref LL_SYSCFG_EXTI_LINE9\n  *         @arg @ref LL_SYSCFG_EXTI_LINE10\n  *         @arg @ref LL_SYSCFG_EXTI_LINE11\n  *         @arg @ref LL_SYSCFG_EXTI_LINE12\n  *         @arg @ref LL_SYSCFG_EXTI_LINE13\n  *         @arg @ref LL_SYSCFG_EXTI_LINE14\n  *         @arg @ref LL_SYSCFG_EXTI_LINE15\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_SYSCFG_EXTI_PORTA\n  *         @arg @ref LL_SYSCFG_EXTI_PORTB\n  *         @arg @ref LL_SYSCFG_EXTI_PORTC\n  *         @arg @ref LL_SYSCFG_EXTI_PORTD\n  *         @arg @ref LL_SYSCFG_EXTI_PORTE\n  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)\n  *         @arg @ref LL_SYSCFG_EXTI_PORTH\n  *         @arg @ref LL_SYSCFG_EXTI_PORTI (*)\n  *\n  *         (*) value not defined in all devices\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));\n}\n\n/**\n  * @brief  Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is\n  * automatically cleared at the end of the SRAM2 erase operation.)\n  * @note This bit is write-protected: setting this bit is possible only after the\n  *       correct key sequence is written in the SYSCFG_SKR register as described in \n  *       the Reference Manual.\n  * @rmtoll SYSCFG_SCSR  SRAM2ER       LL_SYSCFG_EnableSRAM2Erase\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)\n{\n  /* Starts a hardware SRAM2 erase operation*/\n  SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);\n}\n\n/**\n  * @brief  Check if SRAM2 erase operation is on going\n  * @rmtoll SYSCFG_SCSR  SRAM2BSY      LL_SYSCFG_IsSRAM2EraseOngoing\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)\n{\n  return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));\n}\n\n/**\n  * @brief  Set connections to TIM1/8/15/16/17 Break inputs\n  * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_SetTIMBreakInputs\\n\n  *         SYSCFG_CFGR2 SPL           LL_SYSCFG_SetTIMBreakInputs\\n\n  *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_SetTIMBreakInputs\\n\n  *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_SetTIMBreakInputs\n  * @param  Break This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_TIMBREAK_ECC\n  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD\n  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY\n  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)\n{\n  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);\n}\n\n/**\n  * @brief  Get connections to TIM1/8/15/16/17 Break inputs\n  * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\\n\n  *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\\n\n  *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\\n\n  *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs\n  * @retval Returned value can be can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_TIMBREAK_ECC\n  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD\n  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY\n  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)\n{\n  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));\n}\n\n/**\n  * @brief  Check if SRAM2 parity error detected\n  * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_IsActiveFlag_SP\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)\n{\n  return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));\n}\n\n/**\n  * @brief  Clear SRAM2 parity error flag\n  * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_ClearFlag_SP\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)\n{\n  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);\n}\n\n/**\n  * @brief  Enable SRAM2 page write protection for Pages in range 0 to 31\n  * @note Write protection is cleared only by a system reset\n  * @rmtoll SYSCFG_SWPR  PxWP         LL_SYSCFG_EnableSRAM2PageWRP_0_31\n  * @param  SRAM2WRP This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)\n  *\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n/* Legacy define */\n#define LL_SYSCFG_EnableSRAM2PageWRP    LL_SYSCFG_EnableSRAM2PageWRP_0_31\n__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_0_31(uint32_t SRAM2WRP)\n{\n  SET_BIT(SYSCFG->SWPR, SRAM2WRP);\n}\n\n#if defined(SYSCFG_SWPR2_PAGE63)\n/**\n  * @brief  Enable SRAM2 page write protection for Pages in range 32 to 63\n  * @note Write protection is cleared only by a system reset\n  * @rmtoll SYSCFG_SWPR2 PxWP          LL_SYSCFG_EnableSRAM2PageWRP_32_63\n  * @param  SRAM2WRP This parameter can be a combination of the following values:\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE32 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE33 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE34 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE35 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE36 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE37 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE38 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE39 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE40 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE41 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE42 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE43 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE44 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE45 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE46 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE47 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE48 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE49 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE50 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE51 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE52 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE53 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE54 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE55 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE56 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE57 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE58 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE59 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE60 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE61 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE62 (*)\n  *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE63 (*)\n  *\n  *         (*) value not defined in all devices\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP_32_63(uint32_t SRAM2WRP)\n{\n  SET_BIT(SYSCFG->SWPR2, SRAM2WRP);\n}\n#endif /* SYSCFG_SWPR2_PAGE63 */\n\n/**\n  * @brief  SRAM2 page write protection lock prior to erase\n  * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_LockSRAM2WRP\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)\n{\n  /* Writing a wrong key reactivates the write protection */\n  WRITE_REG(SYSCFG->SKR, 0x00);\n}\n\n/**\n  * @brief  SRAM2 page write protection unlock prior to erase\n  * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_UnlockSRAM2WRP\n  * @retval None\n  */\n__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)\n{\n  /* unlock the write protection of the SRAM2ER bit */\n  WRITE_REG(SYSCFG->SKR, 0xCA);\n  WRITE_REG(SYSCFG->SKR, 0x53);\n}\n\n/**\n  * @}\n  */\n\n\n/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU\n  * @{\n  */\n\n/**\n  * @brief  Return the device identifier\n  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID\n  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));\n}\n\n/**\n  * @brief  Return the device revision identifier\n  * @note This field indicates the revision of the device.\n  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID\n  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);\n}\n\n/**\n  * @brief  Enable the Debug Module during SLEEP mode\n  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Disable the Debug Module during SLEEP mode\n  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STOP mode\n  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Disable the Debug Module during STOP mode\n  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STANDBY mode\n  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Disable the Debug Module during STANDBY mode\n  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Set Trace pin assignment control\n  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\\n\n  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment\n  * @param  PinAssignment This parameter can be one of the following values:\n  *         @arg @ref LL_DBGMCU_TRACE_NONE\n  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)\n{\n  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);\n}\n\n/**\n  * @brief  Get Trace pin assignment control\n  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\\n\n  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_DBGMCU_TRACE_NONE\n  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2\n  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4\n  */\n__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)\n{\n  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));\n}\n\n/**\n  * @brief  Freeze APB1 peripherals (group1 peripherals)\n  * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)\n{\n  SET_BIT(DBGMCU->APB1FZR1, Periphs);\n}\n\n/**\n  * @brief  Freeze APB1 peripherals (group2 peripherals)\n  * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)\n{\n  SET_BIT(DBGMCU->APB1FZR2, Periphs);\n}\n\n/**\n  * @brief  Unfreeze APB1 peripherals (group1 peripherals)\n  * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)\n{\n  CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);\n}\n\n/**\n  * @brief  Unfreeze APB1 peripherals (group2 peripherals)\n  * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)\n{\n  CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);\n}\n\n/**\n  * @brief  Freeze APB2 peripherals\n  * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)\n{\n  SET_BIT(DBGMCU->APB2FZ, Periphs);\n}\n\n/**\n  * @brief  Unfreeze APB2 peripherals\n  * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n  * @param  Periphs This parameter can be a combination of the following values:\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP\n  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)\n{\n  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);\n}\n\n/**\n  * @}\n  */\n\n#if defined(VREFBUF)\n/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF\n  * @{\n  */\n\n/**\n  * @brief  Enable Internal voltage reference\n  * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable\n  * @retval None\n  */\n__STATIC_INLINE void LL_VREFBUF_Enable(void)\n{\n  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);\n}\n\n/**\n  * @brief  Disable Internal voltage reference\n  * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable\n  * @retval None\n  */\n__STATIC_INLINE void LL_VREFBUF_Disable(void)\n{\n  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);\n}\n\n/**\n  * @brief  Enable high impedance (VREF+pin is high impedance)\n  * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ\n  * @retval None\n  */\n__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)\n{\n  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);\n}\n\n/**\n  * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)\n  * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ\n  * @retval None\n  */\n__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)\n{\n  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);\n}\n\n/**\n  * @brief  Set the Voltage reference scale\n  * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling\n  * @param  Scale This parameter can be one of the following values:\n  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0\n  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1\n  * @retval None\n  */\n__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)\n{\n  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);\n}\n\n/**\n  * @brief  Get the Voltage reference scale\n  * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0\n  *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1\n  */\n__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)\n{\n  return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));\n}\n\n/**\n  * @brief  Check if Voltage reference buffer is ready\n  * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)\n{\n  return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));\n}\n\n/**\n  * @brief  Get the trimming code for VREFBUF calibration\n  * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming\n  * @retval Between 0 and 0x3F\n  */\n__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)\n{\n  return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));\n}\n\n/**\n  * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)\n  * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming\n  * @param  Value Between 0 and 0x3F\n  * @retval None\n  */\n__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)\n{\n  WRITE_REG(VREFBUF->CCR, Value);\n}\n\n/**\n  * @}\n  */\n#endif /* VREFBUF */\n\n/** @defgroup SYSTEM_LL_EF_FLASH FLASH\n  * @{\n  */\n\n/**\n  * @brief  Set FLASH Latency\n  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency\n  * @param  Latency This parameter can be one of the following values:\n  *         @arg @ref LL_FLASH_LATENCY_0\n  *         @arg @ref LL_FLASH_LATENCY_1\n  *         @arg @ref LL_FLASH_LATENCY_2\n  *         @arg @ref LL_FLASH_LATENCY_3\n  *         @arg @ref LL_FLASH_LATENCY_4\n  *         @arg @ref LL_FLASH_LATENCY_5 (*)\n  *         @arg @ref LL_FLASH_LATENCY_6 (*)\n  *         @arg @ref LL_FLASH_LATENCY_7 (*)\n  *         @arg @ref LL_FLASH_LATENCY_8 (*)\n  *         @arg @ref LL_FLASH_LATENCY_9 (*)\n  *         @arg @ref LL_FLASH_LATENCY_10 (*)\n  *         @arg @ref LL_FLASH_LATENCY_11 (*)\n  *         @arg @ref LL_FLASH_LATENCY_12 (*)\n  *         @arg @ref LL_FLASH_LATENCY_13 (*)\n  *         @arg @ref LL_FLASH_LATENCY_14 (*)\n  *         @arg @ref LL_FLASH_LATENCY_15 (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)\n{\n  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);\n}\n\n/**\n  * @brief  Get FLASH Latency\n  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_FLASH_LATENCY_0\n  *         @arg @ref LL_FLASH_LATENCY_1\n  *         @arg @ref LL_FLASH_LATENCY_2\n  *         @arg @ref LL_FLASH_LATENCY_3\n  *         @arg @ref LL_FLASH_LATENCY_4\n  *         @arg @ref LL_FLASH_LATENCY_5 (*)\n  *         @arg @ref LL_FLASH_LATENCY_6 (*)\n  *         @arg @ref LL_FLASH_LATENCY_7 (*)\n  *         @arg @ref LL_FLASH_LATENCY_8 (*)\n  *         @arg @ref LL_FLASH_LATENCY_9 (*)\n  *         @arg @ref LL_FLASH_LATENCY_10 (*)\n  *         @arg @ref LL_FLASH_LATENCY_11 (*)\n  *         @arg @ref LL_FLASH_LATENCY_12 (*)\n  *         @arg @ref LL_FLASH_LATENCY_13 (*)\n  *         @arg @ref LL_FLASH_LATENCY_14 (*)\n  *         @arg @ref LL_FLASH_LATENCY_15 (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)\n{\n  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));\n}\n\n/**\n  * @brief  Enable Prefetch\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);\n}\n\n/**\n  * @brief  Disable Prefetch\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);\n}\n\n/**\n  * @brief  Check if Prefetch buffer is enabled\n  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)\n{\n  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));\n}\n\n/**\n  * @brief  Enable Instruction cache\n  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableInstCache(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);\n}\n\n/**\n  * @brief  Disable Instruction cache\n  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableInstCache(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);\n}\n\n/**\n  * @brief  Enable Data cache\n  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableDataCache(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);\n}\n\n/**\n  * @brief  Disable Data cache\n  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableDataCache(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);\n}\n\n/**\n  * @brief  Enable Instruction cache reset\n  * @note  bit can be written only when the instruction cache is disabled\n  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);\n}\n\n/**\n  * @brief  Disable Instruction cache reset\n  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);\n}\n\n/**\n  * @brief  Enable Data cache reset\n  * @note bit can be written only when the data cache is disabled\n  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);\n}\n\n/**\n  * @brief  Disable Data cache reset\n  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);\n}\n\n/**\n  * @brief  Enable Flash Power-down mode during run mode or Low-power run mode\n  * @note Flash memory can be put in power-down mode only when the code is executed\n  *       from RAM\n  * @note Flash must not be accessed when power down is enabled\n  * @note Flash must not be put in power-down while a program or an erase operation\n  *       is on-going\n  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\\n\n  *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\\n\n  *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)\n{\n  /* Following values must be written consecutively to unlock the RUN_PD bit in\n     FLASH_ACR */\n  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);\n  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);\n  SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);\n}\n\n/**\n  * @brief  Disable Flash Power-down mode during run mode or Low-power run mode\n  * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\\n\n  *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\\n\n  *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)\n{\n  /* Following values must be written consecutively to unlock the RUN_PD bit in\n     FLASH_ACR */\n  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);\n  WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);\n}\n\n/**\n  * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode\n  * @note Flash must not be put in power-down while a program or an erase operation\n  *       is on-going\n  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)\n{\n  SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);\n}\n\n/**\n  * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode\n  * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown\n  * @retval None\n  */\n__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)\n{\n  CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_SYSTEM_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_usart.h\n  * @author  MCD Application Team\n  * @brief   Header file of USART LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_USART_H\n#define __STM32L4xx_LL_USART_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)\n\n/** @defgroup USART_LL USART\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n#if defined(USART_PRESC_PRESCALER)\n/** @defgroup USART_LL_Private_Variables USART Private Variables\n  * @{\n  */\n/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */\nstatic const uint16_t USART_PRESCALER_TAB[] =\n{\n  (uint16_t)1,\n  (uint16_t)2,\n  (uint16_t)4,\n  (uint16_t)6,\n  (uint16_t)8,\n  (uint16_t)10,\n  (uint16_t)12,\n  (uint16_t)16,\n  (uint16_t)32,\n  (uint16_t)64,\n  (uint16_t)128,\n  (uint16_t)256\n};\n/**\n  * @}\n  */\n#endif\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup USART_LL_Private_Constants USART Private Constants\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_Private_Macros USART Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_ES_INIT USART Exported Init structures\n  * @{\n  */\n\n/**\n  * @brief LL USART Init Structure definition\n  */\ntypedef struct\n{\n#if defined(USART_PRESC_PRESCALER)\n  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.\n                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/\n\n#endif\n  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/\n\n  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.\n                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/\n\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\n                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/\n\n  uint32_t Parity;                    /*!< Specifies the parity mode.\n                                           This parameter can be a value of @ref USART_LL_EC_PARITY.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/\n\n  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/\n\n  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/\n\n  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.\n                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.\n\n                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/\n\n} LL_USART_InitTypeDef;\n\n/**\n  * @brief LL USART Clock Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.\n                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.\n\n                                           USART HW configuration can be modified afterwards using unitary functions\n                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().\n                                           For more details, refer to description of this function. */\n\n  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.\n                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().\n                                           For more details, refer to description of this function. */\n\n  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.\n                                           This parameter can be a value of @ref USART_LL_EC_PHASE.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().\n                                           For more details, refer to description of this function. */\n\n  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted\n                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.\n                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.\n\n                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().\n                                           For more details, refer to description of this function. */\n\n} LL_USART_ClockInitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup USART_LL_Exported_Constants USART Exported Constants\n  * @{\n  */\n\n/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines\n  * @brief    Flags defines which can be used with LL_USART_WriteReg function\n  * @{\n  */\n#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */\n#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */\n#define LL_USART_ICR_NCF                        USART_ICR_NCF                 /*!< Noise detected flag */\n#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */\n#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */\n#endif\n#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */\n#if defined(USART_TCBGT_SUPPORT)\n#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */\n#endif\n#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */\n#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */\n#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */\n#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */\n#if defined(USART_CR2_SLVEN)\n#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun Clear flag */\n#endif\n#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */\n#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines\n  * @brief    Flags defines which can be used with LL_USART_ReadReg function\n  * @{\n  */\n#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */\n#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */\n#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */\n#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */\n#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */\n#else\n#define LL_USART_ISR_RXNE                       USART_ISR_RXNE                /*!< Read data register not empty flag */\n#endif\n#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/\n#else\n#define LL_USART_ISR_TXE                        USART_ISR_TXE                 /*!< Transmit data register empty flag */\n#endif\n#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */\n#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */\n#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */\n#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */\n#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */\n#if defined(USART_CR2_SLVEN)\n#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */\n#endif\n#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */\n#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */\n#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */\n#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */\n#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */\n#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */\n#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */\n#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */\n#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */\n#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */\n#endif\n#if defined(USART_TCBGT_SUPPORT)\n#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */\n#endif\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */\n#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_IT IT Defines\n  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions\n  * @{\n  */\n#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */\n#else\n#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */\n#endif\n#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */\n#else\n#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */\n#endif\n#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */\n#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */\n#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */\n#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */\n#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */\n#endif\n#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */\n#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */\n#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */\n#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */\n#endif\n#if defined(USART_TCBGT_SUPPORT)\n#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */\n#endif\n#if defined(USART_CR1_FIFOEN)\n#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */\n#endif\n/**\n  * @}\n  */\n\n#if defined(USART_CR1_FIFOEN)\n/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold\n  * @{\n  */\n#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */\n#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */\n#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */\n#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */\n#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */\n#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */\n/**\n  * @}\n  */\n#endif\n\n/** @defgroup USART_LL_EC_DIRECTION Communication Direction\n  * @{\n  */\n#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */\n#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */\n#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */\n#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_PARITY Parity Control\n  * @{\n  */\n#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */\n#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */\n#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_WAKEUP Wakeup\n  * @{\n  */\n#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */\n#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_DATAWIDTH Datawidth\n  * @{\n  */\n#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */\n#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */\n#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling\n  * @{\n  */\n#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */\n#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_EC_CLOCK Clock Signal\n  * @{\n  */\n\n#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */\n#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */\n/**\n  * @}\n  */\n#endif /*USE_FULL_LL_DRIVER*/\n\n/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse\n  * @{\n  */\n#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */\n#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_PHASE Clock Phase\n  * @{\n  */\n#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */\n#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_POLARITY Clock Polarity\n  * @{\n  */\n#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/\n#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */\n/**\n  * @}\n  */\n\n#if defined(USART_PRESC_PRESCALER)\n/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler\n  * @{\n  */\n#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not devided   */\n#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */\n#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */\n#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */\n#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */\n#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */\n#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */\n#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */\n#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */\n#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */\n#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */\n#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */\n/**\n  * @}\n  */\n#endif\n\n/** @defgroup USART_LL_EC_STOPBITS Stop Bits\n  * @{\n  */\n#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */\n#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */\n#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */\n#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap\n  * @{\n  */\n#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */\n#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion\n  * @{\n  */\n#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */\n#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion\n  * @{\n  */\n#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */\n#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion\n  * @{\n  */\n#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */\n#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_BITORDER Bit Order\n  * @{\n  */\n#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */\n#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection\n  * @{\n  */\n#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */\n#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */\n#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */\n#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection\n  * @{\n  */\n#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */\n#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_HWCONTROL Hardware Control\n  * @{\n  */\n#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */\n#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */\n#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */\n#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation\n  * @{\n  */\n#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */\n#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */\n#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power\n  * @{\n  */\n#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */\n#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length\n  * @{\n  */\n#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */\n#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity\n  * @{\n  */\n#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */\n#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data\n  * @{\n  */\n#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */\n#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup USART_LL_Exported_Macros USART Exported Macros\n  * @{\n  */\n\n/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in USART register\n  * @param  __INSTANCE__ USART Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in USART register\n  * @param  __INSTANCE__ USART Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper\n  * @{\n  */\n\n/**\n  * @brief  Compute USARTDIV value according to Peripheral Clock and\n  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)\n  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance\n  @if USART_PRESC_PRESCALER\n  * @param  __PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PRESCALER_DIV1\n  *         @arg @ref LL_USART_PRESCALER_DIV2\n  *         @arg @ref LL_USART_PRESCALER_DIV4\n  *         @arg @ref LL_USART_PRESCALER_DIV6\n  *         @arg @ref LL_USART_PRESCALER_DIV8\n  *         @arg @ref LL_USART_PRESCALER_DIV10\n  *         @arg @ref LL_USART_PRESCALER_DIV12\n  *         @arg @ref LL_USART_PRESCALER_DIV16\n  *         @arg @ref LL_USART_PRESCALER_DIV32\n  *         @arg @ref LL_USART_PRESCALER_DIV64\n  *         @arg @ref LL_USART_PRESCALER_DIV128\n  *         @arg @ref LL_USART_PRESCALER_DIV256\n  * @param  __PRESCALER__ Prescaler value\n  @endif\n  * @param  __BAUDRATE__ Baud rate value to achieve\n  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case\n  */\n#if defined(USART_PRESC_PRESCALER)\n#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))\n#else\n#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))\n#endif\n\n/**\n  * @brief  Compute USARTDIV value according to Peripheral Clock and\n  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)\n  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance\n  @if USART_PRESC_PRESCALER\n  * @param  __PRESCALER__ This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PRESCALER_DIV1\n  *         @arg @ref LL_USART_PRESCALER_DIV2\n  *         @arg @ref LL_USART_PRESCALER_DIV4\n  *         @arg @ref LL_USART_PRESCALER_DIV6\n  *         @arg @ref LL_USART_PRESCALER_DIV8\n  *         @arg @ref LL_USART_PRESCALER_DIV10\n  *         @arg @ref LL_USART_PRESCALER_DIV12\n  *         @arg @ref LL_USART_PRESCALER_DIV16\n  *         @arg @ref LL_USART_PRESCALER_DIV32\n  *         @arg @ref LL_USART_PRESCALER_DIV64\n  *         @arg @ref LL_USART_PRESCALER_DIV128\n  *         @arg @ref LL_USART_PRESCALER_DIV256\n  * @param  __PRESCALER__ Prescaler value\n  @endif\n  * @param  __BAUDRATE__ Baud rate value to achieve\n  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case\n  */\n#if defined(USART_PRESC_PRESCALER)\n#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2))/(__BAUDRATE__))\n#else\n#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))\n#endif\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup USART_LL_Exported_Functions USART Exported Functions\n  * @{\n  */\n\n/** @defgroup USART_LL_EF_Configuration Configuration functions\n  * @{\n  */\n\n/**\n  * @brief  USART Enable\n  * @rmtoll CR1          UE            LL_USART_Enable\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_UE);\n}\n\n/**\n  * @brief  USART Disable (all USART prescalers and outputs are disabled)\n  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,\n  *         and current operations are discarded. The configuration of the USART is kept, but all the status\n  *         flags, in the USARTx_ISR are set to their default values.\n  * @rmtoll CR1          UE            LL_USART_Disable\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);\n}\n\n/**\n  * @brief  Indicate if USART is enabled\n  * @rmtoll CR1          UE            LL_USART_IsEnabled\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  FIFO Mode Enable\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);\n}\n\n/**\n  * @brief  FIFO Mode Disable\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);\n}\n\n/**\n  * @brief  Indicate if FIFO Mode is enabled\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN));\n}\n\n/**\n  * @brief  Configure TX FIFO Threshold\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold\n  * @param  USARTx USART Instance\n  * @param  Threshold This parameter can be one of the following values:\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);\n}\n\n/**\n  * @brief  Return TX FIFO Threshold Configuration\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8\n  */\n__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);\n}\n\n/**\n  * @brief  Configure RX FIFO Threshold\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold\n  * @param  USARTx USART Instance\n  * @param  Threshold This parameter can be one of the following values:\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);\n}\n\n/**\n  * @brief  Return RX FIFO Threshold Configuration\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8\n  */\n__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);\n}\n\n/**\n  * @brief  Configure TX and RX FIFOs Threshold\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\\n\n  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold\n  * @param  USARTx USART Instance\n  * @param  TXThreshold This parameter can be one of the following values:\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8\n  * @param  RXThreshold This parameter can be one of the following values:\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8\n  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos);\n}\n#endif\n\n/**\n  * @brief  USART enabled in STOP Mode.\n  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that\n  *         USART clock selection is HSI or LSE in RCC.\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_UESM);\n}\n\n/**\n  * @brief  USART disabled in STOP Mode.\n  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);\n}\n\n/**\n  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));\n}\n\n/**\n  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)\n  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RE);\n}\n\n/**\n  * @brief  Receiver Disable\n  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);\n}\n\n/**\n  * @brief  Transmitter Enable\n  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TE);\n}\n\n/**\n  * @brief  Transmitter Disable\n  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);\n}\n\n/**\n  * @brief  Configure simultaneously enabled/disabled states\n  *         of Transmitter and Receiver\n  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\\n\n  *         CR1          TE            LL_USART_SetTransferDirection\n  * @param  USARTx USART Instance\n  * @param  TransferDirection This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DIRECTION_NONE\n  *         @arg @ref LL_USART_DIRECTION_RX\n  *         @arg @ref LL_USART_DIRECTION_TX\n  *         @arg @ref LL_USART_DIRECTION_TX_RX\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);\n}\n\n/**\n  * @brief  Return enabled/disabled states of Transmitter and Receiver\n  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\\n\n  *         CR1          TE            LL_USART_GetTransferDirection\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_DIRECTION_NONE\n  *         @arg @ref LL_USART_DIRECTION_RX\n  *         @arg @ref LL_USART_DIRECTION_TX\n  *         @arg @ref LL_USART_DIRECTION_TX_RX\n  */\n__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));\n}\n\n/**\n  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).\n  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.\n  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position\n  *         (9th or 8th bit depending on data width) and parity is checked on the received data.\n  * @rmtoll CR1          PS            LL_USART_SetParity\\n\n  *         CR1          PCE           LL_USART_SetParity\n  * @param  USARTx USART Instance\n  * @param  Parity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);\n}\n\n/**\n  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)\n  * @rmtoll CR1          PS            LL_USART_GetParity\\n\n  *         CR1          PCE           LL_USART_GetParity\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  */\n__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));\n}\n\n/**\n  * @brief  Set Receiver Wake Up method from Mute mode.\n  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod\n  * @param  USARTx USART Instance\n  * @param  Method This parameter can be one of the following values:\n  *         @arg @ref LL_USART_WAKEUP_IDLELINE\n  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);\n}\n\n/**\n  * @brief  Return Receiver Wake Up method from Mute mode\n  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_WAKEUP_IDLELINE\n  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK\n  */\n__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));\n}\n\n/**\n  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)\n  * @rmtoll CR1          M0            LL_USART_SetDataWidth\\n\n  *         CR1          M1            LL_USART_SetDataWidth\n  * @param  USARTx USART Instance\n  * @param  DataWidth This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_7B\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);\n}\n\n/**\n  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)\n  * @rmtoll CR1          M0            LL_USART_GetDataWidth\\n\n  *         CR1          M1            LL_USART_GetDataWidth\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_7B\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  */\n__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));\n}\n\n/**\n  * @brief  Allow switch between Mute Mode and Active mode\n  * @rmtoll CR1          MME           LL_USART_EnableMuteMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_MME);\n}\n\n/**\n  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.\n  * @rmtoll CR1          MME           LL_USART_DisableMuteMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_MME);\n}\n\n/**\n  * @brief  Indicate if switch between Mute Mode and Active mode is allowed\n  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));\n}\n\n/**\n  * @brief  Set Oversampling to 8-bit or 16-bit mode\n  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling\n  * @param  USARTx USART Instance\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);\n}\n\n/**\n  * @brief  Return Oversampling mode\n  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  */\n__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));\n}\n\n/**\n  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput\n  * @param  USARTx USART Instance\n  * @param  LastBitClockPulse This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);\n}\n\n/**\n  * @brief  Retrieve Clock pulse of the last data bit output configuration\n  *         (Last bit Clock pulse output to the SCLK pin or not)\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  */\n__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));\n}\n\n/**\n  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase\n  * @param  USARTx USART Instance\n  * @param  ClockPhase This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);\n}\n\n/**\n  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  */\n__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));\n}\n\n/**\n  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity\n  * @param  USARTx USART Instance\n  * @param  ClockPolarity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);\n}\n\n/**\n  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  */\n__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));\n}\n\n/**\n  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function\n  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function\n  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function\n  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\\n\n  *         CR2          CPOL          LL_USART_ConfigClock\\n\n  *         CR2          LBCL          LL_USART_ConfigClock\n  * @param  USARTx USART Instance\n  * @param  Phase This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PHASE_1EDGE\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  * @param  Polarity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_POLARITY_LOW\n  *         @arg @ref LL_USART_POLARITY_HIGH\n  * @param  LBCPOutput This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT\n  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);\n}\n\n#if defined(USART_PRESC_PRESCALER)\n\n/**\n  * @brief  Configure Clock source prescaler for baudrate generator and oversampling\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler\n  * @param  USARTx USART Instance\n  * @param  PrescalerValue This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PRESCALER_DIV1\n  *         @arg @ref LL_USART_PRESCALER_DIV2\n  *         @arg @ref LL_USART_PRESCALER_DIV4\n  *         @arg @ref LL_USART_PRESCALER_DIV6\n  *         @arg @ref LL_USART_PRESCALER_DIV8\n  *         @arg @ref LL_USART_PRESCALER_DIV10\n  *         @arg @ref LL_USART_PRESCALER_DIV12\n  *         @arg @ref LL_USART_PRESCALER_DIV16\n  *         @arg @ref LL_USART_PRESCALER_DIV32\n  *         @arg @ref LL_USART_PRESCALER_DIV64\n  *         @arg @ref LL_USART_PRESCALER_DIV128\n  *         @arg @ref LL_USART_PRESCALER_DIV256\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)\n{\n  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, PrescalerValue);\n}\n\n/**\n  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_PRESCALER_DIV1\n  *         @arg @ref LL_USART_PRESCALER_DIV2\n  *         @arg @ref LL_USART_PRESCALER_DIV4\n  *         @arg @ref LL_USART_PRESCALER_DIV6\n  *         @arg @ref LL_USART_PRESCALER_DIV8\n  *         @arg @ref LL_USART_PRESCALER_DIV10\n  *         @arg @ref LL_USART_PRESCALER_DIV12\n  *         @arg @ref LL_USART_PRESCALER_DIV16\n  *         @arg @ref LL_USART_PRESCALER_DIV32\n  *         @arg @ref LL_USART_PRESCALER_DIV64\n  *         @arg @ref LL_USART_PRESCALER_DIV128\n  *         @arg @ref LL_USART_PRESCALER_DIV256\n  */\n__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));\n}\n#endif\n\n/**\n  * @brief  Enable Clock output on SCLK pin\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Disable Clock output on SCLK pin\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Indicate if Clock output on SCLK pin is enabled\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));\n}\n\n/**\n  * @brief  Set the length of the stop bits\n  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength\n  * @param  USARTx USART Instance\n  * @param  StopBits This parameter can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);\n}\n\n/**\n  * @brief  Retrieve the length of the stop bits\n  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  */\n__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));\n}\n\n/**\n  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function\n  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function\n  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function\n  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\\n\n  *         CR1          PCE           LL_USART_ConfigCharacter\\n\n  *         CR1          M0            LL_USART_ConfigCharacter\\n\n  *         CR1          M1            LL_USART_ConfigCharacter\\n\n  *         CR2          STOP          LL_USART_ConfigCharacter\n  * @param  USARTx USART Instance\n  * @param  DataWidth This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DATAWIDTH_7B\n  *         @arg @ref LL_USART_DATAWIDTH_8B\n  *         @arg @ref LL_USART_DATAWIDTH_9B\n  * @param  Parity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PARITY_NONE\n  *         @arg @ref LL_USART_PARITY_EVEN\n  *         @arg @ref LL_USART_PARITY_ODD\n  * @param  StopBits This parameter can be one of the following values:\n  *         @arg @ref LL_USART_STOPBITS_0_5\n  *         @arg @ref LL_USART_STOPBITS_1\n  *         @arg @ref LL_USART_STOPBITS_1_5\n  *         @arg @ref LL_USART_STOPBITS_2\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,\n                                              uint32_t StopBits)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);\n  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);\n}\n\n/**\n  * @brief  Configure TX/RX pins swapping setting.\n  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap\n  * @param  USARTx USART Instance\n  * @param  SwapConfig This parameter can be one of the following values:\n  *         @arg @ref LL_USART_TXRX_STANDARD\n  *         @arg @ref LL_USART_TXRX_SWAPPED\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);\n}\n\n/**\n  * @brief  Retrieve TX/RX pins swapping configuration.\n  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_TXRX_STANDARD\n  *         @arg @ref LL_USART_TXRX_SWAPPED\n  */\n__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));\n}\n\n/**\n  * @brief  Configure RX pin active level logic\n  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel\n  * @param  USARTx USART Instance\n  * @param  PinInvMethod This parameter can be one of the following values:\n  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD\n  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);\n}\n\n/**\n  * @brief  Retrieve RX pin active level logic configuration\n  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD\n  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED\n  */\n__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));\n}\n\n/**\n  * @brief  Configure TX pin active level logic\n  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel\n  * @param  USARTx USART Instance\n  * @param  PinInvMethod This parameter can be one of the following values:\n  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD\n  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);\n}\n\n/**\n  * @brief  Retrieve TX pin active level logic configuration\n  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD\n  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED\n  */\n__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));\n}\n\n/**\n  * @brief  Configure Binary data logic.\n  * @note   Allow to define how Logical data from the data register are send/received :\n  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)\n  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic\n  * @param  USARTx USART Instance\n  * @param  DataLogic This parameter can be one of the following values:\n  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE\n  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);\n}\n\n/**\n  * @brief  Retrieve Binary data configuration\n  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE\n  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE\n  */\n__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));\n}\n\n/**\n  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)\n  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.\n  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.\n  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder\n  * @param  USARTx USART Instance\n  * @param  BitOrder This parameter can be one of the following values:\n  *         @arg @ref LL_USART_BITORDER_LSBFIRST\n  *         @arg @ref LL_USART_BITORDER_MSBFIRST\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);\n}\n\n/**\n  * @brief  Return transfer bit order (either Less or Most Significant Bit First)\n  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.\n  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.\n  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_BITORDER_LSBFIRST\n  *         @arg @ref LL_USART_BITORDER_MSBFIRST\n  */\n__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));\n}\n\n/**\n  * @brief  Enable Auto Baud-Rate Detection\n  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not\n  *         Auto Baud Rate detection feature is supported by the USARTx instance.\n  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_ABREN);\n}\n\n/**\n  * @brief  Disable Auto Baud-Rate Detection\n  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not\n  *         Auto Baud Rate detection feature is supported by the USARTx instance.\n  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);\n}\n\n/**\n  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled\n  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not\n  *         Auto Baud Rate detection feature is supported by the USARTx instance.\n  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));\n}\n\n/**\n  * @brief  Set Auto Baud-Rate mode bits\n  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not\n  *         Auto Baud Rate detection feature is supported by the USARTx instance.\n  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode\n  * @param  USARTx USART Instance\n  * @param  AutoBaudRateMode This parameter can be one of the following values:\n  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT\n  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE\n  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME\n  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);\n}\n\n/**\n  * @brief  Return Auto Baud-Rate mode\n  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not\n  *         Auto Baud Rate detection feature is supported by the USARTx instance.\n  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT\n  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE\n  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME\n  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME\n  */\n__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));\n}\n\n/**\n  * @brief  Enable Receiver Timeout\n  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);\n}\n\n/**\n  * @brief  Disable Receiver Timeout\n  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);\n}\n\n/**\n  * @brief  Indicate if Receiver Timeout feature is enabled\n  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));\n}\n\n/**\n  * @brief  Set Address of the USART node.\n  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,\n  *         for wake up with address mark detection.\n  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.\n  *         (b7-b4 should be set to 0)\n  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.\n  *         (This is used in multiprocessor communication during Mute mode or Stop mode,\n  *         for wake up with 7-bit address mark detection.\n  *         The MSB of the character sent by the transmitter should be equal to 1.\n  *         It may also be used for character detection during normal reception,\n  *         Mute mode inactive (for example, end of block detection in ModBus protocol).\n  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]\n  *         value and CMF flag is set on match)\n  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\\n\n  *         CR2          ADDM7         LL_USART_ConfigNodeAddress\n  * @param  USARTx USART Instance\n  * @param  AddressLen This parameter can be one of the following values:\n  *         @arg @ref LL_USART_ADDRESS_DETECT_4B\n  *         @arg @ref LL_USART_ADDRESS_DETECT_7B\n  * @param  NodeAddress 4 or 7 bit Address of the USART node.\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,\n             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));\n}\n\n/**\n  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.\n  * @note   If 4-bit Address Detection is selected in ADDM7,\n  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)\n  *         If 7-bit Address Detection is selected in ADDM7,\n  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)\n  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress\n  * @param  USARTx USART Instance\n  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);\n}\n\n/**\n  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)\n  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_ADDRESS_DETECT_4B\n  *         @arg @ref LL_USART_ADDRESS_DETECT_7B\n  */\n__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));\n}\n\n/**\n  * @brief  Enable RTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_RTSE);\n}\n\n/**\n  * @brief  Disable RTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);\n}\n\n/**\n  * @brief  Enable CTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_CTSE);\n}\n\n/**\n  * @brief  Disable CTS HW Flow Control\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);\n}\n\n/**\n  * @brief  Configure HW Flow Control mode (both CTS and RTS)\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\\n\n  *         CR3          CTSE          LL_USART_SetHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @param  HardwareFlowControl This parameter can be one of the following values:\n  *         @arg @ref LL_USART_HWCONTROL_NONE\n  *         @arg @ref LL_USART_HWCONTROL_RTS\n  *         @arg @ref LL_USART_HWCONTROL_CTS\n  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);\n}\n\n/**\n  * @brief  Return HW Flow Control configuration (both CTS and RTS)\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\\n\n  *         CR3          CTSE          LL_USART_GetHWFlowCtrl\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_HWCONTROL_NONE\n  *         @arg @ref LL_USART_HWCONTROL_RTS\n  *         @arg @ref LL_USART_HWCONTROL_CTS\n  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS\n  */\n__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));\n}\n\n/**\n  * @brief  Enable One bit sampling method\n  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);\n}\n\n/**\n  * @brief  Disable One bit sampling method\n  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);\n}\n\n/**\n  * @brief  Indicate if One bit sampling method is enabled\n  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));\n}\n\n/**\n  * @brief  Enable Overrun detection\n  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);\n}\n\n/**\n  * @brief  Disable Overrun detection\n  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);\n}\n\n/**\n  * @brief  Indicate if Overrun detection is enabled\n  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);\n}\n\n/**\n  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          WUS           LL_USART_SetWKUPType\n  * @param  USARTx USART Instance\n  * @param  Type This parameter can be one of the following values:\n  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS\n  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT\n  *         @arg @ref LL_USART_WAKEUP_ON_RXNE\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);\n}\n\n/**\n  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          WUS           LL_USART_GetWKUPType\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS\n  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT\n  *         @arg @ref LL_USART_WAKEUP_ON_RXNE\n  */\n__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));\n}\n\n/**\n  * @brief  Configure USART BRR register for achieving expected Baud Rate value.\n  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)\n  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values\n  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid\n  *         (Baud rate value != 0)\n  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.\n  * @rmtoll BRR          BRR           LL_USART_SetBaudRate\n  * @param  USARTx USART Instance\n  * @param  PeriphClk Peripheral Clock\n  @if USART_PRESC_PRESCALER\n  * @param  PrescalerValue This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PRESCALER_DIV1\n  *         @arg @ref LL_USART_PRESCALER_DIV2\n  *         @arg @ref LL_USART_PRESCALER_DIV4\n  *         @arg @ref LL_USART_PRESCALER_DIV6\n  *         @arg @ref LL_USART_PRESCALER_DIV8\n  *         @arg @ref LL_USART_PRESCALER_DIV10\n  *         @arg @ref LL_USART_PRESCALER_DIV12\n  *         @arg @ref LL_USART_PRESCALER_DIV16\n  *         @arg @ref LL_USART_PRESCALER_DIV32\n  *         @arg @ref LL_USART_PRESCALER_DIV64\n  *         @arg @ref LL_USART_PRESCALER_DIV128\n  *         @arg @ref LL_USART_PRESCALER_DIV256\n  @endif\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @param  BaudRate Baud Rate\n  * @retval None\n  */\n#if defined(USART_PRESC_PRESCALER)\n__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling,\n                                          uint32_t BaudRate)\n#else\n__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,\n                                          uint32_t BaudRate)\n#endif\n{\n  register uint32_t usartdiv = 0x0U;\n  register uint32_t brrtemp = 0x0U;\n\n  if (OverSampling == LL_USART_OVERSAMPLING_8)\n  {\n#if defined(USART_PRESC_PRESCALER)\n    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, PrescalerValue, BaudRate));\n#else\n    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));\n#endif\n    brrtemp = usartdiv & 0xFFF0U;\n    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);\n    USARTx->BRR = brrtemp;\n  }\n  else\n  {\n#if defined(USART_PRESC_PRESCALER)\n    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, PrescalerValue, BaudRate));\n#else\n    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));\n#endif\n  }\n}\n\n/**\n  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register\n  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values\n  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.\n  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.\n  * @rmtoll BRR          BRR           LL_USART_GetBaudRate\n  * @param  USARTx USART Instance\n  * @param  PeriphClk Peripheral Clock\n  @if USART_PRESC_PRESCALER\n  * @param  PrescalerValue This parameter can be one of the following values:\n  *         @arg @ref LL_USART_PRESCALER_DIV1\n  *         @arg @ref LL_USART_PRESCALER_DIV2\n  *         @arg @ref LL_USART_PRESCALER_DIV4\n  *         @arg @ref LL_USART_PRESCALER_DIV6\n  *         @arg @ref LL_USART_PRESCALER_DIV8\n  *         @arg @ref LL_USART_PRESCALER_DIV10\n  *         @arg @ref LL_USART_PRESCALER_DIV12\n  *         @arg @ref LL_USART_PRESCALER_DIV16\n  *         @arg @ref LL_USART_PRESCALER_DIV32\n  *         @arg @ref LL_USART_PRESCALER_DIV64\n  *         @arg @ref LL_USART_PRESCALER_DIV128\n  *         @arg @ref LL_USART_PRESCALER_DIV256\n  @endif\n  * @param  OverSampling This parameter can be one of the following values:\n  *         @arg @ref LL_USART_OVERSAMPLING_16\n  *         @arg @ref LL_USART_OVERSAMPLING_8\n  * @retval Baud Rate\n  */\n#if defined(USART_PRESC_PRESCALER)\n__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling)\n#else\n__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)\n#endif\n{\n  register uint32_t usartdiv = 0x0U;\n  register uint32_t brrresult = 0x0U;\n#if defined(USART_PRESC_PRESCALER)\n  register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[PrescalerValue]));\n#endif\n\n  usartdiv = USARTx->BRR;\n\n  if (OverSampling == LL_USART_OVERSAMPLING_8)\n  {\n    if ((usartdiv & 0xFFF7U) != 0U)\n    {\n      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;\n#if defined(USART_PRESC_PRESCALER)\n      brrresult = (periphclkpresc * 2U) / usartdiv;\n#else\n      brrresult = (PeriphClk * 2U) / usartdiv;\n#endif\n    }\n  }\n  else\n  {\n    if ((usartdiv & 0xFFFFU) != 0U)\n    {\n#if defined(USART_PRESC_PRESCALER)\n      brrresult = periphclkpresc / usartdiv;\n#else\n      brrresult = PeriphClk / usartdiv;\n#endif\n    }\n  }\n  return (brrresult);\n}\n\n/**\n  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)\n  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout\n  * @param  USARTx USART Instance\n  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)\n{\n  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);\n}\n\n/**\n  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)\n  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout\n  * @param  USARTx USART Instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF\n  */\n__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));\n}\n\n/**\n  * @brief  Set Block Length value in reception\n  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength\n  * @param  USARTx USART Instance\n  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)\n{\n  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);\n}\n\n/**\n  * @brief  Get Block Length value in reception\n  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength\n  * @param  USARTx USART Instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature\n  * @{\n  */\n\n/**\n  * @brief  Enable IrDA mode\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_EnableIrda\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Disable IrDA mode\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_DisableIrda\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Indicate if IrDA mode is enabled\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));\n}\n\n/**\n  * @brief  Configure IrDA Power Mode (Normal or Low Power)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode\n  * @param  USARTx USART Instance\n  * @param  PowerMode This parameter can be one of the following values:\n  *         @arg @ref LL_USART_IRDA_POWER_NORMAL\n  *         @arg @ref LL_USART_IRDA_POWER_LOW\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);\n}\n\n/**\n  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_IRDA_POWER_NORMAL\n  *         @arg @ref LL_USART_PHASE_2EDGE\n  */\n__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));\n}\n\n/**\n  * @brief  Set Irda prescaler value, used for dividing the USART clock source\n  *         to achieve the Irda Low Power frequency (8 bits value)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler\n  * @param  USARTx USART Instance\n  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);\n}\n\n/**\n  * @brief  Return Irda prescaler value, used for dividing the USART clock source\n  *         to achieve the Irda Low Power frequency (8 bits value)\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler\n  * @param  USARTx USART Instance\n  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature\n  * @{\n  */\n\n/**\n  * @brief  Enable Smartcard NACK transmission\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_NACK);\n}\n\n/**\n  * @brief  Disable Smartcard NACK transmission\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);\n}\n\n/**\n  * @brief  Indicate if Smartcard NACK transmission is enabled\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));\n}\n\n/**\n  * @brief  Enable Smartcard mode\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Disable Smartcard mode\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Indicate if Smartcard mode is enabled\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));\n}\n\n/**\n  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.\n  *         In transmission mode, it specifies the number of automatic retransmission retries, before\n  *         generating a transmission error (FE bit set).\n  *         In reception mode, it specifies the number or erroneous reception trials, before generating a\n  *         reception error (RXNE and PE bits set)\n  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount\n  * @param  USARTx USART Instance\n  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);\n}\n\n/**\n  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount\n  * @param  USARTx USART Instance\n  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);\n}\n\n/**\n  * @brief  Set Smartcard prescaler value, used for dividing the USART clock\n  *         source to provide the SMARTCARD Clock (5 bits value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler\n  * @param  USARTx USART Instance\n  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);\n}\n\n/**\n  * @brief  Return Smartcard prescaler value, used for dividing the USART clock\n  *         source to provide the SMARTCARD Clock (5 bits value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler\n  * @param  USARTx USART Instance\n  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));\n}\n\n/**\n  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods\n  *         (GT[7:0] bits : Guard time value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime\n  * @param  USARTx USART Instance\n  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)\n{\n  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);\n}\n\n/**\n  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods\n  *         (GT[7:0] bits : Guard time value)\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime\n  * @param  USARTx USART Instance\n  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)\n  */\n__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature\n  * @{\n  */\n\n/**\n  * @brief  Enable Single Wire Half-Duplex mode\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Disable Single Wire Half-Duplex mode\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Indicate if Single Wire Half-Duplex mode is enabled\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));\n}\n\n/**\n  * @}\n  */\n\n#if defined(USART_CR2_SLVEN)\n\n/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature\n  * @{\n  */\n/**\n  * @brief  Enable SPI Synchronous Slave mode\n  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not\n  *         SPI Slave mode feature is supported by the USARTx instance.\n  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef* USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);\n}\n\n/**\n  * @brief  Disable SPI Synchronous Slave mode\n  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not\n  *         SPI Slave mode feature is supported by the USARTx instance.\n  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef* USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);\n}\n\n/**\n  * @brief  Indicate if  SPI Synchronous Slave mode is enabled\n  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not\n  *         SPI Slave mode feature is supported by the USARTx instance.\n  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef* USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN));\n}\n\n/**\n  * @brief  Enable SPI Slave Selection using NSS input pin\n  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not\n  *         SPI Slave mode feature is supported by the USARTx instance.\n  * @note   SPI Slave Selection depends on NSS input pin\n  *         (The slave is selected when NSS is low and deselected when NSS is high).\n  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef* USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);\n}\n\n/**\n  * @brief  Disable SPI Slave Selection using NSS input pin\n  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not\n  *         SPI Slave mode feature is supported by the USARTx instance.\n  * @note   SPI Slave will be always selected and NSS input pin will be ignored.\n  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef* USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);\n}\n\n/**\n  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin\n  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not\n  *         SPI Slave mode feature is supported by the USARTx instance.\n  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef* USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS));\n}\n\n/**\n  * @}\n  */\n#endif\n\n/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature\n  * @{\n  */\n\n/**\n  * @brief  Set LIN Break Detection Length\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen\n  * @param  USARTx USART Instance\n  * @param  LINBDLength This parameter can be one of the following values:\n  *         @arg @ref LL_USART_LINBREAK_DETECT_10B\n  *         @arg @ref LL_USART_LINBREAK_DETECT_11B\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)\n{\n  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);\n}\n\n/**\n  * @brief  Return LIN Break Detection Length\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_LINBREAK_DETECT_10B\n  *         @arg @ref LL_USART_LINBREAK_DETECT_11B\n  */\n__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));\n}\n\n/**\n  * @brief  Enable LIN mode\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_EnableLIN\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Disable LIN mode\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_DisableLIN\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Indicate if LIN mode is enabled\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature\n  * @{\n  */\n\n/**\n  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime\n  * @param  USARTx USART Instance\n  * @param  Time Value between Min_Data=0 and Max_Data=31\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);\n}\n\n/**\n  * @brief  Return DEDT (Driver Enable De-Assertion Time)\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime\n  * @param  USARTx USART Instance\n  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31\n  */\n__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);\n}\n\n/**\n  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime\n  * @param  USARTx USART Instance\n  * @param  Time Value between Min_Data=0 and Max_Data=31\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)\n{\n  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);\n}\n\n/**\n  * @brief  Return DEAT (Driver Enable Assertion Time)\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime\n  * @param  USARTx USART Instance\n  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31\n  */\n__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);\n}\n\n/**\n  * @brief  Enable Driver Enable (DE) Mode\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR3          DEM           LL_USART_EnableDEMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_DEM);\n}\n\n/**\n  * @brief  Disable Driver Enable (DE) Mode\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR3          DEM           LL_USART_DisableDEMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);\n}\n\n/**\n  * @brief  Indicate if Driver Enable (DE) Mode is enabled\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));\n}\n\n/**\n  * @brief  Select Driver Enable Polarity\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity\n  * @param  USARTx USART Instance\n  * @param  Polarity This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DE_POLARITY_HIGH\n  *         @arg @ref LL_USART_DE_POLARITY_LOW\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)\n{\n  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);\n}\n\n/**\n  * @brief  Return Driver Enable Polarity\n  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not\n  *         Driver Enable feature is supported by the USARTx instance.\n  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity\n  * @param  USARTx USART Instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_USART_DE_POLARITY_HIGH\n  *         @arg @ref LL_USART_DE_POLARITY_LOW\n  */\n__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)\n{\n  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services\n  * @{\n  */\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)\n  * @note   In UART mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  * @note   Other remaining configurations items related to Asynchronous Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\\n\n  *         CR3          SCEN          LL_USART_ConfigAsyncMode\\n\n  *         CR3          IREN          LL_USART_ConfigAsyncMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigAsyncMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)\n{\n  /* In Asynchronous mode, the following bits must be kept cleared:\n  - LINEN, CLKEN bits in the USART_CR2 register,\n  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode\n  * @note   In Synchronous mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also sets the USART in Synchronous mode.\n  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not\n  *         Synchronous mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function\n  * @note   Other remaining configurations items related to Synchronous Mode\n  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigSyncMode\\n\n  *         CR3          SCEN          LL_USART_ConfigSyncMode\\n\n  *         CR3          IREN          LL_USART_ConfigSyncMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigSyncMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)\n{\n  /* In Synchronous mode, the following bits must be kept cleared:\n  - LINEN bit in the USART_CR2 register,\n  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));\n  /* set the UART/USART in Synchronous mode */\n  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in LIN Mode\n  * @note   In LIN mode, the following bits must be kept cleared:\n  *           - STOP and CLKEN bits in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also set the UART/USART in LIN mode.\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function\n  * @note   Other remaining configurations items related to LIN Mode\n  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\\n\n  *         CR2          STOP          LL_USART_ConfigLINMode\\n\n  *         CR2          LINEN         LL_USART_ConfigLINMode\\n\n  *         CR3          IREN          LL_USART_ConfigLINMode\\n\n  *         CR3          SCEN          LL_USART_ConfigLINMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigLINMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)\n{\n  /* In LIN mode, the following bits must be kept cleared:\n  - STOP and CLKEN bits in the USART_CR2 register,\n  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));\n  /* Set the UART/USART in LIN mode */\n  SET_BIT(USARTx->CR2, USART_CR2_LINEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode\n  * @note   In Half Duplex mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *         This function also sets the UART/USART in Half Duplex mode.\n  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not\n  *         Half-Duplex mode is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function\n  * @note   Other remaining configurations items related to Half Duplex Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\\n\n  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)\n{\n  /* In Half Duplex mode, the following bits must be kept cleared:\n  - LINEN and CLKEN bits in the USART_CR2 register,\n  - SCEN and IREN bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));\n  /* set the UART/USART in Half Duplex mode */\n  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode\n  * @note   In Smartcard mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also configures Stop bits to 1.5 bits and\n  *         sets the USART in Smartcard mode (SCEN bit).\n  *         Clock Output is also enabled (CLKEN).\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function\n  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function\n  * @note   Other remaining configurations items related to Smartcard Mode\n  *         (as Baud Rate, Word length, Parity, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\\n\n  *         CR2          STOP          LL_USART_ConfigSmartcardMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\\n\n  *         CR3          SCEN          LL_USART_ConfigSmartcardMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)\n{\n  /* In Smartcard mode, the following bits must be kept cleared:\n  - LINEN bit in the USART_CR2 register,\n  - IREN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));\n  /* Configure Stop bits to 1.5 bits */\n  /* Synchronous mode is activated by default */\n  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));\n  /* set the UART/USART in Smartcard mode */\n  SET_BIT(USARTx->CR3, USART_CR3_SCEN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Irda Mode\n  * @note   In IRDA mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - STOP and CLKEN bits in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  *         This function also sets the UART/USART in IRDA mode (IREN bit).\n  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not\n  *         IrDA feature is supported by the USARTx instance.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function\n  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function\n  * @note   Other remaining configurations items related to Irda Mode\n  *         (as Baud Rate, Word length, Power mode, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\\n\n  *         CR2          STOP          LL_USART_ConfigIrdaMode\\n\n  *         CR3          SCEN          LL_USART_ConfigIrdaMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\\n\n  *         CR3          IREN          LL_USART_ConfigIrdaMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)\n{\n  /* In IRDA mode, the following bits must be kept cleared:\n  - LINEN, STOP and CLKEN bits in the USART_CR2 register,\n  - SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));\n  /* set the UART/USART in IRDA mode */\n  SET_BIT(USARTx->CR3, USART_CR3_IREN);\n}\n\n/**\n  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode\n  *         (several USARTs connected in a network, one of the USARTs can be the master,\n  *         its TX output connected to the RX inputs of the other slaves USARTs).\n  * @note   In MultiProcessor mode, the following bits must be kept cleared:\n  *           - LINEN bit in the USART_CR2 register,\n  *           - CLKEN bit in the USART_CR2 register,\n  *           - SCEN bit in the USART_CR3 register,\n  *           - IREN bit in the USART_CR3 register,\n  *           - HDSEL bit in the USART_CR3 register.\n  * @note   Call of this function is equivalent to following function call sequence :\n  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function\n  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function\n  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function\n  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function\n  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function\n  * @note   Other remaining configurations items related to Multi processor Mode\n  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using\n  *         dedicated functions\n  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\\n\n  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\\n\n  *         CR3          IREN          LL_USART_ConfigMultiProcessMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)\n{\n  /* In Multi Processor mode, the following bits must be kept cleared:\n  - LINEN and CLKEN bits in the USART_CR2 register,\n  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/\n  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management\n  * @{\n  */\n\n/**\n  * @brief  Check if the USART Parity Error Flag is set or not\n  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));\n}\n\n/**\n  * @brief  Check if the USART Framing Error Flag is set or not\n  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));\n}\n\n/**\n  * @brief  Check if the USART Noise error detected Flag is set or not\n  * @rmtoll ISR          NF            LL_USART_IsActiveFlag_NE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));\n}\n\n/**\n  * @brief  Check if the USART OverRun Error Flag is set or not\n  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));\n}\n\n/**\n  * @brief  Check if the USART IDLE line detected Flag is set or not\n  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE\n\n/**\n  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE));\n}\n#else\n\n/**\n  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not\n  * @rmtoll ISR          RXNE          LL_USART_IsActiveFlag_RXNE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));\n}\n#endif\n\n/**\n  * @brief  Check if the USART Transmission Complete Flag is set or not\n  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF\n\n/**\n  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF));\n}\n#else\n\n/**\n  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not\n  * @rmtoll ISR          TXE           LL_USART_IsActiveFlag_TXE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));\n}\n#endif\n\n/**\n  * @brief  Check if the USART LIN Break Detection Flag is set or not\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));\n}\n\n/**\n  * @brief  Check if the USART CTS interrupt Flag is set or not\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));\n}\n\n/**\n  * @brief  Check if the USART CTS Flag is set or not\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));\n}\n\n/**\n  * @brief  Check if the USART Receiver Time Out Flag is set or not\n  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));\n}\n\n/**\n  * @brief  Check if the USART End Of Block Flag is set or not\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));\n}\n\n#if defined(USART_CR2_SLVEN)\n\n/**\n  * @brief  Check if the SPI Slave Underrun error flag is set or not\n  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not\n  *         SPI Slave mode feature is supported by the USARTx instance.\n  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR));\n}\n#endif\n\n/**\n  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not\n  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not\n  *         Auto Baud Rate detection feature is supported by the USARTx instance.\n  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));\n}\n\n/**\n  * @brief  Check if the USART Auto-Baud Rate Flag is set or not\n  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not\n  *         Auto Baud Rate detection feature is supported by the USARTx instance.\n  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));\n}\n\n/**\n  * @brief  Check if the USART Busy Flag is set or not\n  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));\n}\n\n/**\n  * @brief  Check if the USART Character Match Flag is set or not\n  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));\n}\n\n/**\n  * @brief  Check if the USART Send Break Flag is set or not\n  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));\n}\n\n/**\n  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not\n  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));\n}\n\n/**\n  * @brief  Check if the USART Wake Up from stop mode Flag is set or not\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));\n}\n\n/**\n  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not\n  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));\n}\n\n/**\n  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not\n  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Check if the USART TX FIFO Empty Flag is set or not\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE));\n}\n\n/**\n  * @brief  Check if the USART RX FIFO Full Flag is set or not\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF));\n}\n#endif\n\n#if defined(USART_TCBGT_SUPPORT)\n\n/* Function available only on devices supporting Transmit Complete before Guard Time feature */\n/**\n  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not\n  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT));\n}\n#endif\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Check if the USART TX FIFO Threshold Flag is set or not\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT));\n}\n\n/**\n  * @brief  Check if the USART RX FIFO Threshold Flag is set or not\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT));\n}\n#endif\n\n/**\n  * @brief  Clear Parity Error Flag\n  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_PECF);\n}\n\n/**\n  * @brief  Clear Framing Error Flag\n  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_FECF);\n}\n\n/**\n  * @brief  Clear Noise detected Flag\n  * @rmtoll ICR          NCF           LL_USART_ClearFlag_NE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_NCF);\n}\n\n/**\n  * @brief  Clear OverRun Error Flag\n  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);\n}\n\n/**\n  * @brief  Clear IDLE line detected Flag\n  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Clear TX FIFO Empty Flag\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);\n}\n#endif\n\n/**\n  * @brief  Clear Transmission Complete Flag\n  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);\n}\n\n#if defined(USART_TCBGT_SUPPORT)\n\n/* Function available only on devices supporting Transmit Complete before Guard Time feature */\n/**\n  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag\n  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);\n}\n#endif\n\n/**\n  * @brief  Clear LIN Break Detection Flag\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);\n}\n\n/**\n  * @brief  Clear CTS Interrupt Flag\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);\n}\n\n/**\n  * @brief  Clear Receiver Time Out Flag\n  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);\n}\n\n/**\n  * @brief  Clear End Of Block Flag\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);\n}\n\n#if defined(USART_CR2_SLVEN)\n\n/**\n  * @brief  Clear SPI Slave Underrun Flag\n  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not\n  *         SPI Slave mode feature is supported by the USARTx instance.\n  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);\n}\n#endif\n\n/**\n  * @brief  Clear Character Match Flag\n  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);\n}\n\n/**\n  * @brief  Clear Wake Up from stop mode Flag\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)\n{\n  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_IT_Management IT_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable IDLE Interrupt\n  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE\n\n/**\n  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);\n}\n#else\n\n/**\n  * @brief  Enable RX Not Empty Interrupt\n  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);\n}\n#endif\n\n/**\n  * @brief  Enable Transmission Complete Interrupt\n  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TCIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF\n\n/**\n  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);\n}\n#else\n\n/**\n  * @brief  Enable TX Empty Interrupt\n  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TXEIE);\n}\n#endif\n\n/**\n  * @brief  Enable Parity Error Interrupt\n  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_PEIE);\n}\n\n/**\n  * @brief  Enable Character Match Interrupt\n  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_CMIE);\n}\n\n/**\n  * @brief  Enable Receiver Timeout Interrupt\n  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RTOIE);\n}\n\n/**\n  * @brief  Enable End Of Block Interrupt\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_EOBIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Enable TX FIFO Empty Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);\n}\n\n/**\n  * @brief  Enable RX FIFO Full Interrupt\n  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);\n}\n#endif\n\n/**\n  * @brief  Enable LIN Break Detection Interrupt\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);\n}\n\n/**\n  * @brief  Enable Error Interrupt\n  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing\n  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).\n  *           0: Interrupt is inhibited\n  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.\n  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_EIE);\n}\n\n/**\n  * @brief  Enable CTS Interrupt\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);\n}\n\n/**\n  * @brief  Enable Wake Up from Stop Mode Interrupt\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_WUFIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Enable TX FIFO Threshold Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);\n}\n#endif\n\n#if defined(USART_TCBGT_SUPPORT)\n\n/* Function available only on devices supporting Transmit Complete before Guard Time feature */\n/**\n  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);\n}\n#endif\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Enable RX FIFO Threshold Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);\n}\n#endif\n\n/**\n  * @brief  Disable IDLE Interrupt\n  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE\n\n/**\n  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);\n}\n#else\n\n/**\n  * @brief  Disable RX Not Empty Interrupt\n  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);\n}\n#endif\n\n/**\n  * @brief  Disable Transmission Complete Interrupt\n  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF\n\n/**\n  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);\n}\n#else\n\n/**\n  * @brief  Disable TX Empty Interrupt\n  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);\n}\n#endif\n\n/**\n  * @brief  Disable Parity Error Interrupt\n  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);\n}\n\n/**\n  * @brief  Disable Character Match Interrupt\n  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);\n}\n\n/**\n  * @brief  Disable Receiver Timeout Interrupt\n  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);\n}\n\n/**\n  * @brief  Disable End Of Block Interrupt\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Disable TX FIFO Empty Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);\n}\n\n/**\n  * @brief  Disable RX FIFO Full Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);\n}\n#endif\n\n/**\n  * @brief  Disable LIN Break Detection Interrupt\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);\n}\n\n/**\n  * @brief  Disable Error Interrupt\n  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing\n  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).\n  *           0: Interrupt is inhibited\n  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.\n  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);\n}\n\n/**\n  * @brief  Disable CTS Interrupt\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);\n}\n\n/**\n  * @brief  Disable Wake Up from Stop Mode Interrupt\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Disable TX FIFO Threshold Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);\n}\n#endif\n\n#if defined(USART_TCBGT_SUPPORT)\n/* Function available only on devices supporting Transmit Complete before Guard Time feature */\n/**\n  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);\n}\n#endif\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Disable RX FIFO Threshold Interrupt\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);\n}\n#endif\n\n/**\n  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.\n  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE\n\n/**\n  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE));\n}\n#else\n\n/**\n  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));\n}\n#endif\n\n/**\n  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.\n  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/* Legacy define */\n#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF\n\n/**\n  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE));\n}\n#else\n\n/**\n  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.\n  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));\n}\n#endif\n\n/**\n  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.\n  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));\n}\n\n/**\n  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.\n  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));\n}\n\n/**\n  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.\n  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));\n}\n\n/**\n  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE));\n}\n\n/**\n  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE));\n}\n#endif\n\n/**\n  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not\n  *         LIN feature is supported by the USARTx instance.\n  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));\n}\n\n/**\n  * @brief  Check if the USART Error Interrupt is enabled or disabled.\n  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));\n}\n\n/**\n  * @brief  Check if the USART CTS Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not\n  *         Hardware Flow control feature is supported by the USARTx instance.\n  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));\n}\n\n/**\n  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not\n  *         Wake-up from Stop mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));\n}\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE));\n}\n#endif\n\n#if defined(USART_TCBGT_SUPPORT)\n\n/* Function available only on devices supporting Transmit Complete before Guard Time feature */\n/**\n  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE));\n}\n#endif\n\n#if defined(USART_CR1_FIFOEN)\n\n/**\n  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE));\n}\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_DMA_Management DMA_Management\n  * @{\n  */\n\n/**\n  * @brief  Enable DMA Mode for reception\n  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_DMAR);\n}\n\n/**\n  * @brief  Disable DMA Mode for reception\n  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);\n}\n\n/**\n  * @brief  Check if DMA Mode is enabled for reception\n  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));\n}\n\n/**\n  * @brief  Enable DMA Mode for transmission\n  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_DMAT);\n}\n\n/**\n  * @brief  Disable DMA Mode for transmission\n  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);\n}\n\n/**\n  * @brief  Check if DMA Mode is enabled for transmission\n  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));\n}\n\n/**\n  * @brief  Enable DMA Disabling on Reception Error\n  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->CR3, USART_CR3_DDRE);\n}\n\n/**\n  * @brief  Disable DMA Disabling on Reception Error\n  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)\n{\n  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);\n}\n\n/**\n  * @brief  Indicate if DMA Disabling on Reception Error is disabled\n  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr\n  * @param  USARTx USART Instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)\n{\n  return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));\n}\n\n/**\n  * @brief  Get the data register address used for DMA transfer\n  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\\n\n  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr\n  * @param  USARTx USART Instance\n  * @param  Direction This parameter can be one of the following values:\n  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT\n  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE\n  * @retval Address of data register\n  */\n__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)\n{\n  register uint32_t data_reg_addr = 0U;\n\n  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)\n  {\n    /* return address of TDR register */\n    data_reg_addr = (uint32_t) &(USARTx->TDR);\n  }\n  else\n  {\n    /* return address of RDR register */\n    data_reg_addr = (uint32_t) &(USARTx->RDR);\n  }\n\n  return data_reg_addr;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Data_Management Data_Management\n  * @{\n  */\n\n/**\n  * @brief  Read Receiver Data register (Receive Data value, 8 bits)\n  * @rmtoll RDR          RDR           LL_USART_ReceiveData8\n  * @param  USARTx USART Instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)\n{\n  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));\n}\n\n/**\n  * @brief  Read Receiver Data register (Receive Data value, 9 bits)\n  * @rmtoll RDR          RDR           LL_USART_ReceiveData9\n  * @param  USARTx USART Instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF\n  */\n__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)\n{\n  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));\n}\n\n/**\n  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)\n  * @rmtoll TDR          TDR           LL_USART_TransmitData8\n  * @param  USARTx USART Instance\n  * @param  Value between Min_Data=0x00 and Max_Data=0xFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)\n{\n  USARTx->TDR = Value;\n}\n\n/**\n  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)\n  * @rmtoll TDR          TDR           LL_USART_TransmitData9\n  * @param  USARTx USART Instance\n  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)\n{\n  USARTx->TDR = Value & 0x1FFU;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup USART_LL_EF_Execution Execution\n  * @{\n  */\n\n/**\n  * @brief  Request an Automatic Baud Rate measurement on next received data frame\n  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not\n  *         Auto Baud Rate detection feature is supported by the USARTx instance.\n  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);\n}\n\n/**\n  * @brief  Request Break sending\n  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);\n}\n\n/**\n  * @brief  Put USART in mute mode and set the RWU flag\n  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->RQR, USART_RQR_MMRQ);\n}\n\n/**\n  @if USART_CR1_FIFOEN\n  * @brief  Request a Receive Data and FIFO flush\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  * @note   Allows to discard the received data without reading them, and avoid an overrun\n  *         condition.\n  @else\n  * @brief  Request a Receive Data flush\n  @endif\n  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);\n}\n\n/**\n  @if USART_CR1_FIFOEN\n  * @brief  Request a Transmit data and FIFO flush\n  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not\n  *         FIFO mode feature is supported by the USARTx instance.\n  @else\n  * @brief  Request a Transmit data flush\n  @endif\n  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not\n  *         Smartcard feature is supported by the USARTx instance.\n  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush\n  * @param  USARTx USART Instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)\n{\n  SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\nErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);\nErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);\nvoid        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);\nErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);\nvoid        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_USART_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_utils.h\n  * @author  MCD Application Team\n  * @brief   Header file of UTILS LL module.\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The LL UTILS driver contains a set of generic APIs that can be\n    used by user:\n      (+) Device electronic signature\n      (+) Timing functions\n      (+) PLL configuration functions\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_LL_UTILS_H\n#define __STM32L4xx_LL_UTILS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n/** @defgroup UTILS_LL UTILS\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants\n  * @{\n  */\n\n/* Max delay can be used in LL_mDelay */\n#define LL_MAX_DELAY                  0xFFFFFFFFU\n\n/**\n * @brief Unique device ID register base address\n */\n#define UID_BASE_ADDRESS              UID_BASE\n\n/**\n * @brief Flash size data register base address\n */\n#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE\n\n/**\n * @brief Package data register base address\n */\n#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros\n  * @{\n  */\n/**\n  * @}\n  */\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures\n  * @{\n  */\n/**\n  * @brief  UTILS PLL structure definition\n  */\ntypedef struct\n{\n  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.\n                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n\n  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.\n                        This parameter must be a number between Min_Data = 8 and Max_Data = 86\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n\n  uint32_t PLLR;   /*!< Division for the main system clock.\n                        This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV\n\n                        This feature can be modified afterwards using unitary function\n                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */\n} LL_UTILS_PLLInitTypeDef;\n\n/**\n  * @brief  UTILS System, AHB and APB buses clock configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAHBPrescaler(). */\n\n  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAPB1Prescaler(). */\n\n  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\n                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV\n\n                                       This feature can be modified afterwards using unitary function\n                                       @ref LL_RCC_SetAPB2Prescaler(). */\n\n} LL_UTILS_ClkInitTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants\n  * @{\n  */\n\n/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation\n  * @{\n  */\n#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */\n#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE\n  * @{\n  */\n#define LL_UTILS_PACKAGETYPE_LQFP64         0x00000000U /*!< LQFP64 package type                      */\n#define LL_UTILS_PACKAGETYPE_WLCSP64        0x00000001U /*!< WLCSP64 package type                     */\n#define LL_UTILS_PACKAGETYPE_LQFP100        0x00000002U /*!< LQFP100 package type                     */\n#define LL_UTILS_PACKAGETYPE_BGA132         0x00000003U /*!< BGA132 package type                      */\n#define LL_UTILS_PACKAGETYPE_LQFP144_CSP72  0x00000004U /*!< LQFP144, WLCSP81 or WLCSP72 package type */\n#define LL_UTILS_PACKAGETYPE_UFQFPN32       0x00000008U /*!< UFQFPN32 package type                    */\n#define LL_UTILS_PACKAGETYPE_UFQFPN48       0x0000000AU /*!< UFQFPN48 package type                    */\n#define LL_UTILS_PACKAGETYPE_LQFP48         0x0000000BU /*!< LQFP48 package type                      */\n#define LL_UTILS_PACKAGETYPE_WLCSP49        0x0000000CU /*!< WLCSP49 package type                     */\n#define LL_UTILS_PACKAGETYPE_UFBGA64        0x0000000DU /*!< UFBGA64 package type                     */\n#define LL_UTILS_PACKAGETYPE_UFBGA100       0x0000000EU /*!< UFBGA100 package type                    */\n#define LL_UTILS_PACKAGETYPE_UFBGA169       0x00000010U /*!< UFBGA169 package type                    */\n#define LL_UTILS_PACKAGETYPE_LQFP100_DSI    0x00000012U /*!< LQFP100 with DSI package type            */\n#define LL_UTILS_PACKAGETYPE_WLCSP144_DSI   0x00000013U /*!< WLCSP144 with DSI package type           */\n#define LL_UTILS_PACKAGETYPE_UFBGA144_DSI   0x00000013U /*!< UFBGA144 with DSI package type           */\n#define LL_UTILS_PACKAGETYPE_UFBGA169_DSI   0x00000014U /*!< UFBGA169 with DSI package type           */\n#define LL_UTILS_PACKAGETYPE_LQFP144_DSI    0x00000015U /*!< LQFP144 with DSI package type            */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions\n  * @{\n  */\n\n/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE\n  * @{\n  */\n\n/**\n  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word0(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));\n}\n\n/**\n  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word1(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));\n}\n\n/**\n  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)\n  * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]\n  */\n__STATIC_INLINE uint32_t LL_GetUID_Word2(void)\n{\n  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));\n}\n\n/**\n  * @brief  Get Flash memory size\n  * @note   This bitfield indicates the size of the device Flash memory expressed in\n  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.\n  * @retval FLASH_SIZE[15:0]: Flash memory size\n  */\n__STATIC_INLINE uint32_t LL_GetFlashSize(void)\n{\n  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));\n}\n\n/**\n  * @brief  Get Package type\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_BGA132 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_DSI (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_DSI (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_DSI (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_DSI (*)\n  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_DSI (*)\n  *\n  *         (*) value not defined in all devices.\n  */\n__STATIC_INLINE uint32_t LL_GetPackageType(void)\n{\n  return (uint8_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_LL_EF_DELAY DELAY\n  * @{\n  */\n\n/**\n  * @brief  This function configures the Cortex-M SysTick source of the time base.\n  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)\n  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick \n  *         configuration by calling this function, for a delay use rather osDelay RTOS service.\n  * @param  Ticks Number of ticks\n  * @retval None\n  */\n__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)\n{\n  /* Configure the SysTick to have interrupt in 1ms time base */\n  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */\n  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */\n}\n\nvoid        LL_Init1msTick(uint32_t HCLKFrequency);\nvoid        LL_mDelay(uint32_t Delay);\n\n/**\n  * @}\n  */\n\n/** @defgroup UTILS_EF_SYSTEM SYSTEM\n  * @{\n  */\n\nvoid        LL_SetSystemCoreClock(uint32_t HCLKFrequency);\nErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,\n                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\nErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,\n                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\nErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,\n                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_LL_UTILS_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_dma.c\n  * @author  MCD Application Team\n  * @brief   DMA LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx_ll_dma.h\"\n#include \"stm32l4xx_ll_bus.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (DMA1) || defined (DMA2)\n\n/** @defgroup DMA_LL DMA\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup DMA_LL_Private_Macros\n  * @{\n  */\n#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \\\n                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \\\n                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))\n\n#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \\\n                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))\n\n#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \\\n                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))\n\n#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \\\n                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))\n\n#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \\\n                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \\\n                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))\n\n#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \\\n                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \\\n                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))\n\n#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)\n\n#if defined(DMAMUX1)\n#define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= 93U)\n#else\n#define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      (((__VALUE__) == LL_DMA_REQUEST_0)  || \\\n                                                 ((__VALUE__) == LL_DMA_REQUEST_1)  || \\\n                                                 ((__VALUE__) == LL_DMA_REQUEST_2)  || \\\n                                                 ((__VALUE__) == LL_DMA_REQUEST_3)  || \\\n                                                 ((__VALUE__) == LL_DMA_REQUEST_4)  || \\\n                                                 ((__VALUE__) == LL_DMA_REQUEST_5)  || \\\n                                                 ((__VALUE__) == LL_DMA_REQUEST_6)  || \\\n                                                 ((__VALUE__) == LL_DMA_REQUEST_7))\n#endif /* DMAMUX1 */\n\n#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \\\n                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \\\n                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \\\n                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))\n\n#if defined (DMA2)\n#if defined (DMA2_Channel6) && defined (DMA2_Channel7)\n#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \\\n                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \\\n                                                         (((INSTANCE) == DMA2) && \\\n                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))))\n#else\n#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \\\n                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_5) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_6) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_7))) || \\\n                                                         (((INSTANCE) == DMA2) && \\\n                                                         (((CHANNEL) == LL_DMA_CHANNEL_1) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_2) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_3) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_4) || \\\n                                                          ((CHANNEL) == LL_DMA_CHANNEL_5))))\n#endif\n#else\n#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \\\n                                                            (((CHANNEL) == LL_DMA_CHANNEL_1)|| \\\n                                                            ((CHANNEL) == LL_DMA_CHANNEL_2) || \\\n                                                            ((CHANNEL) == LL_DMA_CHANNEL_3) || \\\n                                                            ((CHANNEL) == LL_DMA_CHANNEL_4) || \\\n                                                            ((CHANNEL) == LL_DMA_CHANNEL_5) || \\\n                                                            ((CHANNEL) == LL_DMA_CHANNEL_6) || \\\n                                                            ((CHANNEL) == LL_DMA_CHANNEL_7))))\n#endif\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup DMA_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup DMA_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize the DMA registers to their default reset values.\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  *         @arg @ref LL_DMA_CHANNEL_ALL\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: DMA registers are de-initialized\n  *          - ERROR: DMA registers are not de-initialized\n  */\nuint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)\n{\n  DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;\n  ErrorStatus status = SUCCESS;\n\n  /* Check the DMA Instance DMAx and Channel parameters*/\n  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));\n\n  if (Channel == LL_DMA_CHANNEL_ALL)\n  {\n    if (DMAx == DMA1)\n    {\n      /* Force reset of DMA clock */\n      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);\n\n      /* Release reset of DMA clock */\n      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);\n    }\n#if defined(DMA2)\n    else if (DMAx == DMA2)\n    {\n      /* Force reset of DMA clock */\n      LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);\n\n      /* Release reset of DMA clock */\n      LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);\n    }\n#endif\n    else\n    {\n      status = ERROR;\n    }\n  }\n  else\n  {\n    tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));\n\n    /* Disable the selected DMAx_Channely */\n    CLEAR_BIT(tmp->CCR, DMA_CCR_EN);\n\n    /* Reset DMAx_Channely control register */\n    LL_DMA_WriteReg(tmp, CCR, 0U);\n\n    /* Reset DMAx_Channely remaining bytes register */\n    LL_DMA_WriteReg(tmp, CNDTR, 0U);\n\n    /* Reset DMAx_Channely peripheral address register */\n    LL_DMA_WriteReg(tmp, CPAR, 0U);\n\n    /* Reset DMAx_Channely memory address register */\n    LL_DMA_WriteReg(tmp, CMAR, 0U);\n\n#if defined(DMAMUX1)\n    /* Reset Request register field for DMAx Channel */\n    LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQUEST_MEM2MEM);\n#else\n    /* Reset Request register field for DMAx Channel */\n    LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0);\n#endif /* DMAMUX1 */\n\n    if (Channel == LL_DMA_CHANNEL_1)\n    {\n      /* Reset interrupt pending bits for DMAx Channel1 */\n      LL_DMA_ClearFlag_GI1(DMAx);\n    }\n    else if (Channel == LL_DMA_CHANNEL_2)\n    {\n      /* Reset interrupt pending bits for DMAx Channel2 */\n      LL_DMA_ClearFlag_GI2(DMAx);\n    }\n    else if (Channel == LL_DMA_CHANNEL_3)\n    {\n      /* Reset interrupt pending bits for DMAx Channel3 */\n      LL_DMA_ClearFlag_GI3(DMAx);\n    }\n    else if (Channel == LL_DMA_CHANNEL_4)\n    {\n      /* Reset interrupt pending bits for DMAx Channel4 */\n      LL_DMA_ClearFlag_GI4(DMAx);\n    }\n    else if (Channel == LL_DMA_CHANNEL_5)\n    {\n      /* Reset interrupt pending bits for DMAx Channel5 */\n      LL_DMA_ClearFlag_GI5(DMAx);\n    }\n\n    else if (Channel == LL_DMA_CHANNEL_6)\n    {\n      /* Reset interrupt pending bits for DMAx Channel6 */\n      LL_DMA_ClearFlag_GI6(DMAx);\n    }\n    else if (Channel == LL_DMA_CHANNEL_7)\n    {\n      /* Reset interrupt pending bits for DMAx Channel7 */\n      LL_DMA_ClearFlag_GI7(DMAx);\n    }\n    else\n    {\n      status = ERROR;\n    }\n  }\n\n  return status;\n}\n\n/**\n  * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.\n  * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :\n  *         @arg @ref __LL_DMA_GET_INSTANCE\n  *         @arg @ref __LL_DMA_GET_CHANNEL\n  * @param  DMAx DMAx Instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_DMA_CHANNEL_1\n  *         @arg @ref LL_DMA_CHANNEL_2\n  *         @arg @ref LL_DMA_CHANNEL_3\n  *         @arg @ref LL_DMA_CHANNEL_4\n  *         @arg @ref LL_DMA_CHANNEL_5\n  *         @arg @ref LL_DMA_CHANNEL_6\n  *         @arg @ref LL_DMA_CHANNEL_7\n  * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: DMA registers are initialized\n  *          - ERROR: Not applicable\n  */\nuint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)\n{\n  /* Check the DMA Instance DMAx and Channel parameters*/\n  assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));\n\n  /* Check the DMA parameters from DMA_InitStruct */\n  assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));\n  assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));\n  assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));\n  assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));\n  assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));\n  assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));\n  assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));\n  assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));\n  assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));\n\n  /*---------------------------- DMAx CCR Configuration ------------------------\n   * Configure DMAx_Channely: data transfer direction, data transfer mode,\n   *                          peripheral and memory increment mode,\n   *                          data size alignment and  priority level with parameters :\n   * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits\n   * - Mode:           DMA_CCR_CIRC bit\n   * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit\n   * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit\n   * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits\n   * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits\n   * - Priority:               DMA_CCR_PL[1:0] bits\n   */\n  LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \\\n                        DMA_InitStruct->Mode                   | \\\n                        DMA_InitStruct->PeriphOrM2MSrcIncMode  | \\\n                        DMA_InitStruct->MemoryOrM2MDstIncMode  | \\\n                        DMA_InitStruct->PeriphOrM2MSrcDataSize | \\\n                        DMA_InitStruct->MemoryOrM2MDstDataSize | \\\n                        DMA_InitStruct->Priority);\n\n  /*-------------------------- DMAx CMAR Configuration -------------------------\n   * Configure the memory or destination base address with parameter :\n   * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits\n   */\n  LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);\n\n  /*-------------------------- DMAx CPAR Configuration -------------------------\n   * Configure the peripheral or source base address with parameter :\n   * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits\n   */\n  LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);\n\n  /*--------------------------- DMAx CNDTR Configuration -----------------------\n   * Configure the peripheral base address with parameter :\n   * - NbData: DMA_CNDTR_NDT[15:0] bits\n   */\n  LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);\n\n#if defined(DMAMUX1)\n  /*--------------------------- DMAMUXx CCR Configuration ----------------------\n   * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :\n   * - PeriphRequest: DMA_CxCR[7:0] bits\n   */\n  LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);\n#else\n  /*--------------------------- DMAx CSELR Configuration -----------------------\n   * Configure the DMA request for DMA instance on Channel x with parameter :\n   * - PeriphRequest: DMA_CSELR[31:0] bits\n   */\n  LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);\n#endif /* DMAMUX1 */\n\n  return SUCCESS;\n}\n\n/**\n  * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.\n  * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.\n  * @retval None\n  */\nvoid LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)\n{\n  /* Set DMA_InitStruct fields to default values */\n  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;\n  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;\n  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;\n  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;\n  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;\n  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;\n  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;\n  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;\n  DMA_InitStruct->NbData                 = 0x00000000U;\n#if defined(DMAMUX1)\n  DMA_InitStruct->PeriphRequest          = LL_DMAMUX_REQUEST_MEM2MEM;\n#else\n  DMA_InitStruct->PeriphRequest          = LL_DMA_REQUEST_0;\n#endif /* DMAMUX1 */\n  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* DMA1 || DMA2 */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_exti.c\n  * @author  MCD Application Team\n  * @brief   EXTI LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx_ll_exti.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (EXTI)\n\n/** @defgroup EXTI_LL EXTI\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup EXTI_LL_Private_Macros\n  * @{\n  */\n\n#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)\n#define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)\n\n#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \\\n                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \\\n                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))\n\n\n#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \\\n                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \\\n                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \\\n                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))\n\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup EXTI_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup EXTI_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize the EXTI registers to their default reset values.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: EXTI registers are de-initialized\n  *          - ERROR: not applicable\n  */\nuint32_t LL_EXTI_DeInit(void)\n{\n  /* Interrupt mask register set to default reset values */\n  LL_EXTI_WriteReg(IMR1,   0xFF820000U);\n  /* Event mask register set to default reset values */\n  LL_EXTI_WriteReg(EMR1,   0x00000000U);\n  /* Rising Trigger selection register set to default reset values */\n  LL_EXTI_WriteReg(RTSR1,  0x00000000U);\n  /* Falling Trigger selection register set to default reset values */\n  LL_EXTI_WriteReg(FTSR1,  0x00000000U);\n  /* Software interrupt event register set to default reset values */\n  LL_EXTI_WriteReg(SWIER1, 0x00000000U);\n  /* Pending register clear */\n  LL_EXTI_WriteReg(PR1,    0x007DFFFFU);\n\n  /* Interrupt mask register 2 set to default reset values */\n#if defined(LL_EXTI_LINE_40)\n  LL_EXTI_WriteReg(IMR2,        0x00000187U);\n#else\n  LL_EXTI_WriteReg(IMR2,        0x00000087U);\n#endif\n  /* Event mask register 2 set to default reset values */\n  LL_EXTI_WriteReg(EMR2,        0x00000000U);\n  /* Rising Trigger selection register 2 set to default reset values */\n  LL_EXTI_WriteReg(RTSR2,       0x00000000U);\n  /* Falling Trigger selection register 2 set to default reset values */\n  LL_EXTI_WriteReg(FTSR2,       0x00000000U);\n  /* Software interrupt event register 2 set to default reset values */\n  LL_EXTI_WriteReg(SWIER2,      0x00000000U);\n  /* Pending register 2 clear */\n  LL_EXTI_WriteReg(PR2,         0x00000078U);\n\n  return SUCCESS;\n}\n\n/**\n  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.\n  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: EXTI registers are initialized\n  *          - ERROR: not applicable\n  */\nuint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  /* Check the parameters */\n  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));\n  assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));\n  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));\n  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));\n\n  /* ENABLE LineCommand */\n  if (EXTI_InitStruct->LineCommand != DISABLE)\n  {\n    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));\n\n    /* Configure EXTI Lines in range from 0 to 31 */\n    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)\n    {\n      switch (EXTI_InitStruct->Mode)\n      {\n        case LL_EXTI_MODE_IT:\n          /* First Disable Event on provided Lines */\n          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);\n          /* Then Enable IT on provided Lines */\n          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);\n          break;\n        case LL_EXTI_MODE_EVENT:\n          /* First Disable IT on provided Lines */\n          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);\n          /* Then Enable Event on provided Lines */\n          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);\n          break;\n        case LL_EXTI_MODE_IT_EVENT:\n          /* Directly Enable IT & Event on provided Lines */\n          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);\n          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);\n          break;\n        default:\n          status = ERROR;\n          break;\n      }\n      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)\n      {\n        switch (EXTI_InitStruct->Trigger)\n        {\n          case LL_EXTI_TRIGGER_RISING:\n            /* First Disable Falling Trigger on provided Lines */\n            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            /* Then Enable Rising Trigger on provided Lines */\n            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            break;\n          case LL_EXTI_TRIGGER_FALLING:\n            /* First Disable Rising Trigger on provided Lines */\n            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            /* Then Enable Falling Trigger on provided Lines */\n            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            break;\n          case LL_EXTI_TRIGGER_RISING_FALLING:\n            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);\n            break;\n          default:\n            status = ERROR;\n            break;\n        }\n      }\n    }\n    /* Configure EXTI Lines in range from 32 to 63 */\n    if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)\n    {\n      switch (EXTI_InitStruct->Mode)\n      {\n        case LL_EXTI_MODE_IT:\n          /* First Disable Event on provided Lines */\n          LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);\n          /* Then Enable IT on provided Lines */\n          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);\n          break;\n        case LL_EXTI_MODE_EVENT:\n          /* First Disable IT on provided Lines */\n          LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);\n          /* Then Enable Event on provided Lines */\n          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);\n          break;\n        case LL_EXTI_MODE_IT_EVENT:\n          /* Directly Enable IT & Event on provided Lines */\n          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);\n          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);\n          break;\n        default:\n          status = ERROR;\n          break;\n      }\n      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)\n      {\n        switch (EXTI_InitStruct->Trigger)\n        {\n          case LL_EXTI_TRIGGER_RISING:\n            /* First Disable Falling Trigger on provided Lines */\n            LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);\n            /* Then Enable IT on provided Lines */\n            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);\n            break;\n          case LL_EXTI_TRIGGER_FALLING:\n            /* First Disable Rising Trigger on provided Lines */\n            LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);\n            /* Then Enable Falling Trigger on provided Lines */\n            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);\n            break;\n          case LL_EXTI_TRIGGER_RISING_FALLING:\n            LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);\n            LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);\n            break;\n          default:\n            status = ERROR;\n            break;\n        }\n      }\n    }\n  }\n  /* DISABLE LineCommand */\n  else\n  {\n    /* De-configure EXTI Lines in range from 0 to 31 */\n    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);\n    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);\n    /* De-configure EXTI Lines in range from 32 to 63 */\n    LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);\n    LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);\n  }\n  return status;\n}\n\n/**\n  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.\n  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.\n  * @retval None\n  */\nvoid LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)\n{\n  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;\n  EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;\n  EXTI_InitStruct->LineCommand    = DISABLE;\n  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;\n  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (EXTI) */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_gpio.c\n  * @author  MCD Application Team\n  * @brief   GPIO LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx_ll_gpio.h\"\n#include \"stm32l4xx_ll_bus.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI)\n\n/** @addtogroup GPIO_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup GPIO_LL_Private_Macros\n  * @{\n  */\n#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))\n\n#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\\\n                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\\\n                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\\\n                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))\n\n#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\\\n                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))\n\n#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\\\n                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\\\n                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\\\n                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))\n\n#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\\\n                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\\\n                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))\n\n#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_10 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_11 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_12 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_13 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_14 )   ||\\\n                                            ((__VALUE__) == LL_GPIO_AF_15 ))\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup GPIO_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup GPIO_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize GPIO registers (Registers restored to their default values).\n  * @param  GPIOx GPIO Port\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: GPIO registers are de-initialized\n  *          - ERROR:   Wrong GPIO Port\n  */\nErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\n\n  /* Force and Release reset on clock of GPIOx Port */\n  if (GPIOx == GPIOA)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA);\n  }\n  else if (GPIOx == GPIOB)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB);\n  }\n  else if (GPIOx == GPIOC)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC);\n  }\n#if defined(GPIOD)\n  else if (GPIOx == GPIOD)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD);\n  }\n#endif /* GPIOD */\n#if defined(GPIOE)\n  else if (GPIOx == GPIOE)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE);\n  }\n#endif /* GPIOE */\n#if defined(GPIOF)\n  else if (GPIOx == GPIOF)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF);\n  }\n#endif /* GPIOF */\n#if defined(GPIOG)\n  else if (GPIOx == GPIOG)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG);\n  }\n#endif /* GPIOG */\n#if defined(GPIOH)\n  else if (GPIOx == GPIOH)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH);\n  }\n#endif /* GPIOH */\n#if defined(GPIOI)\n  else if (GPIOx == GPIOI)\n  {\n    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOI);\n    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI);\n  }\n#endif /* GPIOI */\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.\n  * @param  GPIOx GPIO Port\n  * @param  GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure\n  *         that contains the configuration information for the specified GPIO peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content\n  *          - ERROR:   Not applicable\n  */\nErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)\n{\n  uint32_t pinpos     = 0x00000000U;\n  uint32_t currentpin = 0x00000000U;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\n  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));\n  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));\n  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));\n\n  /* ------------------------- Configure the port pins ---------------- */\n  /* Initialize  pinpos on first pin set */\n  pinpos = POSITION_VAL(GPIO_InitStruct->Pin);\n\n  /* Configure the port pins */\n  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)\n  {\n    /* Get current io position */\n    currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);\n\n    if (currentpin)\n    {\n      /* Pin Mode configuration */\n      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);\n\n      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))\n      {\n        /* Check Speed mode parameters */\n        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));\n\n        /* Speed mode configuration */\n        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);\n      }\n\n      /* Pull-up Pull down resistor configuration*/\n      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);\n\n      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)\n      {\n        /* Check Alternate parameter */\n        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));\n\n        /* Speed mode configuration */\n        if (POSITION_VAL(currentpin) < 0x00000008U)\n        {\n          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);\n        }\n        else\n        {\n          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);\n        }\n      }\n    }\n    pinpos++;\n  }\n\n  if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))\n  {\n    /* Check Output mode parameters */\n    assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));\n\n    /* Output mode configuration*/\n    LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);\n\n  }\n  return (SUCCESS);\n}\n\n/**\n  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.\n  * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure\n  *                          whose fields will be set to default values.\n  * @retval None\n  */\n\nvoid LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)\n{\n  /* Reset GPIO init structure parameters values */\n  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;\n  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;\n  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;\n  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;\n  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;\n  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_lpuart.c\n  * @author  MCD Application Team\n  * @brief   LPUART LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx_ll_lpuart.h\"\n#include \"stm32l4xx_ll_rcc.h\"\n#include \"stm32l4xx_ll_bus.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (LPUART1)\n\n/** @addtogroup LPUART_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @addtogroup LPUART_LL_Private_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup LPUART_LL_Private_Macros\n  * @{\n  */\n\n/* Check of parameters for configuration of LPUART registers                  */\n\n#if defined(USART_PRESC_PRESCALER)\n#define IS_LL_LPUART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \\\n                                        || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))\n\n#endif\n/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */\n/*              value :                                                       */\n/*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */\n/*                - LPUART_BRR register value should be >= 0x300              */\n/*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */\n/*              Baudrate specified by the user should belong to [8, 26000000].*/\n#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 26000000U) && ((__BAUDRATE__) >= 8U))\n\n/* __VALUE__ BRR content must be greater than or equal to 0x300. */\n#define IS_LL_LPUART_BRR(__VALUE__) ((__VALUE__) >= 0x300U)\n\n#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \\\n                                        || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \\\n                                        || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \\\n                                        || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))\n\n#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \\\n                                     || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \\\n                                     || ((__VALUE__) == LL_LPUART_PARITY_ODD))\n\n#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \\\n                                        || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \\\n                                        || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))\n\n#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \\\n                                       || ((__VALUE__) == LL_LPUART_STOPBITS_2))\n\n#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \\\n                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \\\n                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \\\n                                       || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))\n\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup LPUART_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup LPUART_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize LPUART registers (Registers restored to their default values).\n  * @param  LPUARTx LPUART Instance\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: LPUART registers are de-initialized\n  *          - ERROR: not applicable\n  */\nErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check the parameters */\n  assert_param(IS_LPUART_INSTANCE(LPUARTx));\n\n  if (LPUARTx == LPUART1)\n  {\n    /* Force reset of LPUART peripheral */\n    LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1);\n\n    /* Release reset of LPUART peripheral */\n    LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1);\n  }\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief  Initialize LPUART registers according to the specified\n  *         parameters in LPUART_InitStruct.\n  * @note   As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0),\n  *         LPUART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.\n  * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).\n  * @param  LPUARTx LPUART Instance\n  * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure\n  *         that contains the configuration information for the specified LPUART peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content\n  *          - ERROR: Problem occurred during LPUART Registers initialization\n  */\nErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)\n{\n  ErrorStatus status = ERROR;\n  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check the parameters */\n  assert_param(IS_LPUART_INSTANCE(LPUARTx));\n#if defined(USART_PRESC_PRESCALER)\n  assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue));\n#endif\n  assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));\n  assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));\n  assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));\n  assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));\n  assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));\n  assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));\n\n  /* LPUART needs to be in disabled state, in order to be able to configure some bits in\n     CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */\n  if (LL_LPUART_IsEnabled(LPUARTx) == 0U)\n  {\n    /*---------------------------- LPUART CR1 Configuration -----------------------\n     * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:\n     * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value\n     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value\n     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value\n     */\n    MODIFY_REG(LPUARTx->CR1,\n               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),\n               (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));\n\n    /*---------------------------- LPUART CR2 Configuration -----------------------\n     * Configure LPUARTx CR2 (Stop bits) with parameters:\n     * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.\n     */\n    LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);\n\n    /*---------------------------- LPUART CR3 Configuration -----------------------\n     * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:\n     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value.\n     */\n    LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);\n\n    /*---------------------------- LPUART BRR Configuration -----------------------\n     * Retrieve Clock frequency used for LPUART Peripheral\n     */\n    periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);\n\n    /* Configure the LPUART Baud Rate :\n#if defined(USART_PRESC_PRESCALER)\n       - prescaler value is required\n#endif\n       - valid baud rate value (different from 0) is required\n       - Peripheral clock as returned by RCC service, should be valid (different from 0).\n    */\n    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)\n        && (LPUART_InitStruct->BaudRate != 0U))\n    {\n      status = SUCCESS;\n      LL_LPUART_SetBaudRate(LPUARTx,\n                            periphclk,\n#if defined(USART_PRESC_PRESCALER)\n                            LPUART_InitStruct->PrescalerValue,\n#endif\n                            LPUART_InitStruct->BaudRate);\n\n      /* Check BRR is greater than or equal to 0x300 */\n      assert_param(IS_LL_LPUART_BRR(LPUARTx->BRR));\n    }\n#if defined(USART_PRESC_PRESCALER)\n\n    /*---------------------------- LPUART PRESC Configuration -----------------------\n     * Configure LPUARTx PRESC (Prescaler) with parameters:\n     * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value.\n     */\n    LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue);\n#endif\n  }\n\n  return (status);\n}\n\n/**\n  * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.\n  * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure\n  *                          whose fields will be set to default values.\n  * @retval None\n  */\n\nvoid LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)\n{\n  /* Set LPUART_InitStruct fields to default values */\n#if defined(USART_PRESC_PRESCALER)\n  LPUART_InitStruct->PrescalerValue      = LL_LPUART_PRESCALER_DIV1;\n#endif\n  LPUART_InitStruct->BaudRate            = 9600U;\n  LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;\n  LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;\n  LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;\n  LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;\n  LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined (LPUART1) */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_pwr.c\n  * @author  MCD Application Team\n  * @brief   PWR LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx_ll_pwr.h\"\n#include \"stm32l4xx_ll_bus.h\"\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined(PWR)\n\n/** @defgroup PWR_LL PWR\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup PWR_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup PWR_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize the PWR registers to their default reset values.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: PWR registers are de-initialized\n  *          - ERROR: not applicable\n  */\nErrorStatus LL_PWR_DeInit(void)\n{\n  /* Force reset of PWR clock */\n  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);\n\n  /* Release reset of PWR clock */\n  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);\n\n  return SUCCESS;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* defined(PWR) */\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_rcc.c\n  * @author  MCD Application Team\n  * @brief   RCC LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx_ll_rcc.h\"\n#ifdef  USE_FULL_ASSERT\n  #include \"stm32_assert.h\"\n#else\n  #define assert_param(expr) ((void)0U)\n#endif\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined(RCC)\n\n/** @addtogroup RCC_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup RCC_LL_Private_Macros\n  * @{\n  */\n#if   defined(RCC_CCIPR_USART3SEL)\n#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))\n#else\n#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))\n\n#endif /* RCC_CCIPR_USART3SEL */\n#if defined(RCC_CCIPR_UART4SEL) && defined(RCC_CCIPR_UART5SEL)\n#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \\\n                                             || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))\n#elif defined(RCC_CCIPR_UART4SEL)\n#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)\n#elif defined(RCC_CCIPR_UART5SEL)\n#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)\n#endif /* RCC_CCIPR_UART4SEL && RCC_CCIPR_UART5SEL*/\n\n#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))\n\n#if defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL)\n#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))\n\n#elif !defined(RCC_CCIPR_I2C2SEL)&&defined(RCC_CCIPR_I2C3SEL)\n#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))\n\n#else\n#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)     ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)\n\n#endif /* RCC_CCIPR_I2C2SEL && RCC_CCIPR_I2C3SEL */\n#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE))\n\n#if defined(RCC_CCIPR_SAI2SEL)\n#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \\\n                                            || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))\n#elif defined(RCC_CCIPR_SAI1SEL)\n#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)\n#endif /* RCC_CCIPR_SAI2SEL */\n\n#if defined(RCC_CCIPR2_SDMMCSEL)\n#define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE))\n#endif /* RCC_CCIPR2_SDMMCSEL */\n\n#if defined(SDMMC1)\n#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE))\n#endif /* SDMMC1 */\n\n#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))\n\n#if defined(USB_OTG_FS) || defined(USB)\n#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))\n#endif /* USB_OTG_FS || USB */\n\n#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))\n\n#if defined(SWPMI1)\n#define IS_LL_RCC_SWPMI_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_SWPMI1_CLKSOURCE))\n#endif /* SWPMI1 */\n\n#if   defined(DFSDM1_Channel0)\n#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))\n#if defined(RCC_CCIPR2_DFSDM1SEL)\n#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))\n#endif /* RCC_CCIPR2_DFSDM1SEL */\n#endif /* DFSDM1_Channel0 */\n\n#if defined(DSI)\n#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))\n#endif /* DSI */\n\n#if defined(LTDC)\n#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))\n#endif /* LTDC */\n\n#if defined(OCTOSPI1)\n#define IS_LL_RCC_OCTOSPI_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_OCTOSPI_CLKSOURCE))\n#endif /* OCTOSPI */\n\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n/** @defgroup RCC_LL_Private_Functions RCC Private functions\n  * @{\n  */\nuint32_t RCC_GetSystemClockFreq(void);\nuint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);\nuint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);\nuint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);\nuint32_t RCC_PLL_GetFreqDomain_SYS(void);\nuint32_t RCC_PLL_GetFreqDomain_SAI(void);\nuint32_t RCC_PLL_GetFreqDomain_48M(void);\n#if defined(RCC_PLLSAI1_SUPPORT)\nuint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);\nuint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);\nuint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);\n#endif /* RCC_PLLSAI1_SUPPORT */\n#if defined(RCC_PLLSAI2_SUPPORT)\nuint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void);\n#if defined(LTDC)\nuint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void);\n#else\nuint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void);\n#endif /* LTDC */\n#if defined(DSI)\nuint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void);\n#endif /* DSI */\n#endif /*RCC_PLLSAI2_SUPPORT*/\n/**\n  * @}\n  */\n\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup RCC_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup RCC_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  Reset the RCC clock configuration to the default reset state.\n  * @note   The default reset state of the clock configuration is given below:\n  *         - MSI  ON and used as system clock source\n  *         - HSE, HSI, PLL and PLLSAIxSource OFF\n  *         - AHB, APB1 and APB2 prescaler set to 1.\n  *         - CSS, MCO OFF\n  *         - All interrupts disabled\n  * @note   This function doesn't modify the configuration of the\n  *         - Peripheral clocks\n  *         - LSI, LSE and RTC clocks\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: RCC registers are de-initialized\n  *          - ERROR: not applicable\n  */\nErrorStatus LL_RCC_DeInit(void)\n{\n  uint32_t vl_mask = 0U;\n\n  /* Set MSION bit */\n  LL_RCC_MSI_Enable();\n\n  /* Insure MSIRDY bit is set before writing default MSIRANGE value */\n  while (LL_RCC_MSI_IsReady() == 0U)\n  {\n    __NOP();\n  }\n\n  /* Set MSIRANGE default value */\n  LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);\n  /* Set MSITRIM bits to the reset value*/\n  LL_RCC_MSI_SetCalibTrimming(0);\n\n  /* Set HSITRIM bits to the reset value*/\n  LL_RCC_HSI_SetCalibTrimming(0x10U);\n\n  /* Reset CFGR register */\n  LL_RCC_WriteReg(CFGR, 0x00000000U);\n\n  vl_mask = 0xFFFFFFFFU;\n\n  /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLSYSON bits */\n  CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIASFS | RCC_CR_HSIKERON  | RCC_CR_HSEON |\n  RCC_CR_PLLON));\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n  /* Reset PLLSAI1ON bit */\n  CLEAR_BIT(vl_mask, RCC_CR_PLLSAI1ON);\n#endif /*RCC_PLLSAI1_SUPPORT*/\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n  /* Reset PLLSAI2ON bit */\n  CLEAR_BIT(vl_mask, RCC_CR_PLLSAI2ON);\n#endif /*RCC_PLLSAI2_SUPPORT*/\n\n  /* Write new mask in CR register */\n  LL_RCC_WriteReg(CR, vl_mask);\n\n  /* Reset PLLCFGR register */\n  LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n  /* Reset PLLSAI1CFGR register */\n  LL_RCC_WriteReg(PLLSAI1CFGR, 16U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos);\n#endif /*RCC_PLLSAI1_SUPPORT*/\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n  /* Reset PLLSAI2CFGR register */\n  LL_RCC_WriteReg(PLLSAI2CFGR, 16U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos);\n#endif /*RCC_PLLSAI2_SUPPORT*/\n\n  /* Reset HSEBYP bit */\n  LL_RCC_HSE_DisableBypass();\n\n  /* Disable all interrupts */\n  LL_RCC_WriteReg(CIER, 0x00000000U);\n\n  return SUCCESS;\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup RCC_LL_EF_Get_Freq\n  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks\n  *         and different peripheral clocks available on the device.\n  * @note   If SYSCLK source is MSI, function returns values based on MSI_VALUE(*)\n  * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)\n  * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)\n  * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)\n  *         or HSI_VALUE(**) or MSI_VALUE(*) multiplied/divided by the PLL factors.\n  * @note   (*) MSI_VALUE is a constant defined in this file (default value\n  *             4 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.\n  * @note   (**) HSI_VALUE is a constant defined in this file (default value\n  *              16 MHz) but the real value may vary depending on the variations\n  *              in voltage and temperature.\n  * @note   (***) HSE_VALUE is a constant defined in this file (default value\n  *               8 MHz), user has to ensure that HSE_VALUE is same as the real\n  *               frequency of the crystal used. Otherwise, this function may\n  *               have wrong result.\n  * @note   The result of this function could be incorrect when using fractional\n  *         value for HSE crystal.\n  * @note   This function can be used by the user application to compute the\n  *         baud-rate for the communication peripherals or configure other parameters.\n  * @{\n  */\n\n/**\n  * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks\n  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function\n  *         must be called to update structure fields. Otherwise, any\n  *         configuration based on this function will be incorrect.\n  * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies\n  * @retval None\n  */\nvoid LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)\n{\n  /* Get SYSCLK frequency */\n  RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();\n\n  /* HCLK clock frequency */\n  RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);\n\n  /* PCLK1 clock frequency */\n  RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);\n\n  /* PCLK2 clock frequency */\n  RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);\n}\n\n/**\n  * @brief  Return USARTx clock frequency\n  * @param  USARTxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USART1_CLKSOURCE\n  *         @arg @ref LL_RCC_USART2_CLKSOURCE\n  *         @arg @ref LL_RCC_USART3_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval USART clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready\n  */\nuint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)\n{\n  uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));\n\n  if (USARTxSource == LL_RCC_USART1_CLKSOURCE)\n  {\n    /* USART1CLK clock frequency */\n    switch (LL_RCC_GetUSARTClockSource(USARTxSource))\n    {\n      case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */\n        usart_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          usart_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */\n        if (LL_RCC_LSE_IsReady())\n        {\n          usart_frequency = LSE_VALUE;\n        }\n        break;\n\n      case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */\n      default:\n        usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n  else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)\n  {\n    /* USART2CLK clock frequency */\n    switch (LL_RCC_GetUSARTClockSource(USARTxSource))\n    {\n      case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */\n        usart_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          usart_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */\n        if (LL_RCC_LSE_IsReady())\n        {\n          usart_frequency = LSE_VALUE;\n        }\n        break;\n\n      case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */\n      default:\n        usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n  else\n  {\n#if defined(RCC_CCIPR_USART3SEL)\n    if (USARTxSource == LL_RCC_USART3_CLKSOURCE)\n    {\n      /* USART3CLK clock frequency */\n      switch (LL_RCC_GetUSARTClockSource(USARTxSource))\n      {\n        case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */\n          usart_frequency = RCC_GetSystemClockFreq();\n          break;\n\n        case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */\n          if (LL_RCC_HSI_IsReady())\n          {\n            usart_frequency = HSI_VALUE;\n          }\n          break;\n\n        case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */\n          if (LL_RCC_LSE_IsReady())\n          {\n            usart_frequency = LSE_VALUE;\n          }\n          break;\n\n        case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */\n        default:\n          usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n          break;\n      }\n    }\n#endif /* RCC_CCIPR_USART3SEL */\n  }\n  return usart_frequency;\n}\n\n#if defined(RCC_CCIPR_UART4SEL) || defined(RCC_CCIPR_UART5SEL)\n/**\n  * @brief  Return UARTx clock frequency\n  * @param  UARTxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_UART4_CLKSOURCE\n  *         @arg @ref LL_RCC_UART5_CLKSOURCE\n  * @retval UART clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready\n  */\nuint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)\n{\n  uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));\n\n#if defined(RCC_CCIPR_UART4SEL)\n  if (UARTxSource == LL_RCC_UART4_CLKSOURCE)\n  {\n    /* UART4CLK clock frequency */\n    switch (LL_RCC_GetUARTClockSource(UARTxSource))\n    {\n      case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */\n        uart_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_UART4_CLKSOURCE_HSI:    /* UART4 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          uart_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_UART4_CLKSOURCE_LSE:    /* UART4 Clock is LSE Osc. */\n        if (LL_RCC_LSE_IsReady())\n        {\n          uart_frequency = LSE_VALUE;\n        }\n        break;\n\n      case LL_RCC_UART4_CLKSOURCE_PCLK1:  /* UART4 Clock is PCLK1 */\n      default:\n        uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n#endif /* RCC_CCIPR_UART4SEL */\n\n#if defined(RCC_CCIPR_UART5SEL)\n  if (UARTxSource == LL_RCC_UART5_CLKSOURCE)\n  {\n    /* UART5CLK clock frequency */\n    switch (LL_RCC_GetUARTClockSource(UARTxSource))\n    {\n      case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */\n        uart_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_UART5_CLKSOURCE_HSI:    /* UART5 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          uart_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_UART5_CLKSOURCE_LSE:    /* UART5 Clock is LSE Osc. */\n        if (LL_RCC_LSE_IsReady())\n        {\n          uart_frequency = LSE_VALUE;\n        }\n        break;\n\n      case LL_RCC_UART5_CLKSOURCE_PCLK1:  /* UART5 Clock is PCLK1 */\n      default:\n        uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n#endif /* RCC_CCIPR_UART5SEL */\n\n  return uart_frequency;\n}\n#endif /* RCC_CCIPR_UART4SEL || RCC_CCIPR_UART5SEL */\n\n/**\n  * @brief  Return I2Cx clock frequency\n  * @param  I2CxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_I2C1_CLKSOURCE\n  *         @arg @ref LL_RCC_I2C2_CLKSOURCE (*)\n  *         @arg @ref LL_RCC_I2C3_CLKSOURCE\n  *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval I2C clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready\n  */\nuint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)\n{\n  uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));\n\n  if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)\n  {\n    /* I2C1 CLK clock frequency */\n    switch (LL_RCC_GetI2CClockSource(I2CxSource))\n    {\n      case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */\n        i2c_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          i2c_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */\n      default:\n        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n#if defined(RCC_CCIPR_I2C2SEL)\n  else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)\n  {\n    /* I2C2 CLK clock frequency */\n    switch (LL_RCC_GetI2CClockSource(I2CxSource))\n    {\n      case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */\n        i2c_frequency = RCC_GetSystemClockFreq();\n        break;\n\n      case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          i2c_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */\n      default:\n        i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n#endif /*RCC_CCIPR_I2C2SEL*/\n  else\n  {\n    if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)\n    {\n      /* I2C3 CLK clock frequency */\n      switch (LL_RCC_GetI2CClockSource(I2CxSource))\n      {\n        case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */\n          i2c_frequency = RCC_GetSystemClockFreq();\n          break;\n\n        case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */\n          if (LL_RCC_HSI_IsReady())\n          {\n            i2c_frequency = HSI_VALUE;\n          }\n          break;\n\n        case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */\n        default:\n          i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n          break;\n      }\n    }\n#if defined(RCC_CCIPR2_I2C4SEL)\n    else\n    {\n      if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)\n      {\n        /* I2C4 CLK clock frequency */\n        switch (LL_RCC_GetI2CClockSource(I2CxSource))\n        {\n          case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */\n            i2c_frequency = RCC_GetSystemClockFreq();\n            break;\n\n          case LL_RCC_I2C4_CLKSOURCE_HSI:    /* I2C4 Clock is HSI Osc. */\n            if (LL_RCC_HSI_IsReady())\n            {\n              i2c_frequency = HSI_VALUE;\n            }\n            break;\n\n          case LL_RCC_I2C4_CLKSOURCE_PCLK1:  /* I2C4 Clock is PCLK1 */\n          default:\n            i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n            break;\n        }\n      }\n    }\n#endif /*RCC_CCIPR2_I2C4SEL*/\n  }\n\n  return i2c_frequency;\n}\n\n\n/**\n  * @brief  Return LPUARTx clock frequency\n  * @param  LPUARTxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE\n  * @retval LPUART clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready\n  */\nuint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)\n{\n  uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));\n\n  /* LPUART1CLK clock frequency */\n  switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))\n  {\n    case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */\n      lpuart_frequency = RCC_GetSystemClockFreq();\n      break;\n\n    case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */\n      if (LL_RCC_HSI_IsReady())\n      {\n        lpuart_frequency = HSI_VALUE;\n      }\n      break;\n\n    case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */\n      if (LL_RCC_LSE_IsReady())\n      {\n        lpuart_frequency = LSE_VALUE;\n      }\n      break;\n\n    case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */\n    default:\n      lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n      break;\n  }\n\n  return lpuart_frequency;\n}\n\n/**\n  * @brief  Return LPTIMx clock frequency\n  * @param  LPTIMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE\n  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE\n  * @retval LPTIM clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready\n  */\nuint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)\n{\n  uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));\n\n  if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)\n  {\n    /* LPTIM1CLK clock frequency */\n    switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))\n    {\n      case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */\n        if (LL_RCC_LSI_IsReady())\n        {\n          lptim_frequency = LSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */\n        if (LL_RCC_HSI_IsReady())\n        {\n          lptim_frequency = HSI_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */\n        if (LL_RCC_LSE_IsReady())\n        {\n          lptim_frequency = LSE_VALUE;\n        }\n        break;\n\n      case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */\n      default:\n        lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n        break;\n    }\n  }\n  else\n  {\n    if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE)\n    {\n      /* LPTIM2CLK clock frequency */\n      switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))\n      {\n        case LL_RCC_LPTIM2_CLKSOURCE_LSI:    /* LPTIM2 Clock is LSI Osc. */\n          if (LL_RCC_LSI_IsReady())\n          {\n            lptim_frequency = LSI_VALUE;\n          }\n          break;\n\n        case LL_RCC_LPTIM2_CLKSOURCE_HSI:    /* LPTIM2 Clock is HSI Osc. */\n          if (LL_RCC_HSI_IsReady())\n          {\n            lptim_frequency = HSI_VALUE;\n          }\n          break;\n\n        case LL_RCC_LPTIM2_CLKSOURCE_LSE:    /* LPTIM2 Clock is LSE Osc. */\n          if (LL_RCC_LSE_IsReady())\n          {\n            lptim_frequency = LSE_VALUE;\n          }\n          break;\n\n        case LL_RCC_LPTIM2_CLKSOURCE_PCLK1:  /* LPTIM2 Clock is PCLK1 */\n        default:\n          lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n          break;\n      }\n    }\n  }\n\n  return lptim_frequency;\n}\n\n#if defined(RCC_CCIPR_SAI1SEL)\n/**\n  * @brief  Return SAIx clock frequency\n  * @param  SAIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SAI1_CLKSOURCE\n  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)\n  *\n  *         (*) value not defined in all devices.\n  * @retval SAI clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used\n  */\nuint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)\n{\n  uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));\n\n  if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)\n  {\n    /* SAI1CLK clock frequency */\n    switch (LL_RCC_GetSAIClockSource(SAIxSource))\n    {\n      case LL_RCC_SAI1_CLKSOURCE_PLLSAI1:    /* PLLSAI1 clock used as SAI1 clock source */\n        if (LL_RCC_PLLSAI1_IsReady())\n        {\n          sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();\n        }\n        break;\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n      case LL_RCC_SAI1_CLKSOURCE_PLLSAI2:    /* PLLSAI2 clock used as SAI1 clock source */\n        if (LL_RCC_PLLSAI2_IsReady())\n        {\n          sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();\n        }\n        break;\n\n#endif /* RCC_PLLSAI2_SUPPORT */\n      case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */\n        if (LL_RCC_PLL_IsReady())\n        {\n          sai_frequency = RCC_PLL_GetFreqDomain_SAI();\n        }\n        break;\n\n      case LL_RCC_SAI1_CLKSOURCE_PIN:        /* External input clock used as SAI1 clock source */\n      default:\n        sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n        break;\n    }\n  }\n  else\n  {\n#if defined(RCC_CCIPR_SAI2SEL)\n    if (SAIxSource == LL_RCC_SAI2_CLKSOURCE)\n    {\n      /* SAI2CLK clock frequency */\n      switch (LL_RCC_GetSAIClockSource(SAIxSource))\n      {\n        case LL_RCC_SAI2_CLKSOURCE_PLLSAI1:  /* PLLSAI1 clock used as SAI2 clock source */\n          if (LL_RCC_PLLSAI1_IsReady())\n          {\n            sai_frequency = RCC_PLLSAI1_GetFreqDomain_SAI();\n          }\n          break;\n\n  #if defined(RCC_PLLSAI2_SUPPORT)\n        case LL_RCC_SAI2_CLKSOURCE_PLLSAI2:  /* PLLSAI2 clock used as SAI2 clock source */\n          if (LL_RCC_PLLSAI2_IsReady())\n          {\n            sai_frequency = RCC_PLLSAI2_GetFreqDomain_SAI();\n          }\n          break;\n\n  #endif /* RCC_PLLSAI2_SUPPORT */\n        case LL_RCC_SAI2_CLKSOURCE_PLL:      /* PLL clock used as SAI2 clock source */\n          if (LL_RCC_PLL_IsReady())\n          {\n            sai_frequency = RCC_PLL_GetFreqDomain_SAI();\n          }\n          break;\n\n        case LL_RCC_SAI2_CLKSOURCE_PIN:      /* External input clock used as SAI2 clock source */\n        default:\n          sai_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n          break;\n      }\n    }\n#endif /* RCC_CCIPR_SAI2SEL */\n  }\n\n  return sai_frequency;\n}\n#endif /* RCC_CCIPR_SAI1SEL */\n\n#if defined(RCC_CCIPR2_SDMMCSEL)\n/**\n  * @brief  Return SDMMCx kernel clock frequency\n  * @param  SDMMCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE\n  * @retval SDMMC clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected\n  */\nuint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource)\n{\n  uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SDMMC_KERNELCLKSOURCE(SDMMCxSource));\n\n  /* SDMMC1CLK kernel clock frequency */\n  switch (LL_RCC_GetSDMMCKernelClockSource(SDMMCxSource))\n  {\n    case LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK:      /* 48MHz clock from internal multiplexor used as SDMMC1 clock source */\n      sdmmc_frequency = LL_RCC_GetSDMMCClockFreq(LL_RCC_SDMMC1_CLKSOURCE);\n      break;\n\n    case LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL:        /* PLLSAI3CLK clock used as SDMMC1 clock source */\n      if (LL_RCC_PLL_IsReady())\n      {\n        sdmmc_frequency = RCC_PLL_GetFreqDomain_SAI();\n      }\n      break;\n\n    default:\n      sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n      break;\n  }\n\n  return sdmmc_frequency;\n}\n#endif\n\n#if defined(SDMMC1)\n/**\n  * @brief  Return SDMMCx clock frequency\n  * @param  SDMMCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SDMMC1_CLKSOURCE\n  * @retval SDMMC clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected\n  */\nuint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)\n{\n  uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));\n\n  /* SDMMC1CLK clock frequency */\n  switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))\n  {\n#if  defined(LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1)\n    case LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1:    /* PLLSAI1 clock used as SDMMC1 clock source */\n      if (LL_RCC_PLLSAI1_IsReady())\n      {\n        sdmmc_frequency = RCC_PLLSAI1_GetFreqDomain_48M();\n      }\n      break;\n#endif\n\n    case LL_RCC_SDMMC1_CLKSOURCE_PLL:        /* PLL clock used as SDMMC1 clock source */\n      if (LL_RCC_PLL_IsReady())\n      {\n        sdmmc_frequency = RCC_PLL_GetFreqDomain_48M();\n      }\n      break;\n\n#if  defined(LL_RCC_SDMMC1_CLKSOURCE_MSI)\n    case LL_RCC_SDMMC1_CLKSOURCE_MSI:        /* MSI clock used as SDMMC1 clock source */\n      if (LL_RCC_MSI_IsReady())\n      {\n        sdmmc_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      }\n      break;\n#endif\n\n#if defined(RCC_HSI48_SUPPORT)\n    case LL_RCC_SDMMC1_CLKSOURCE_HSI48:      /* HSI48 used as SDMMC1 clock source */\n      if (LL_RCC_HSI48_IsReady())\n      {\n        sdmmc_frequency = HSI48_VALUE;\n      }\n      break;\n#else\n    case LL_RCC_SDMMC1_CLKSOURCE_NONE:       /* No clock used as SDMMC1 clock source */\n#endif\n    default:\n      sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n      break;\n  }\n\n  return sdmmc_frequency;\n}\n#endif /* SDMMC1 */\n\n/**\n  * @brief  Return RNGx clock frequency\n  * @param  RNGxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_RNG_CLKSOURCE\n  * @retval RNG clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected\n  */\nuint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)\n{\n  uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));\n\n  /* RNGCLK clock frequency */\n  switch (LL_RCC_GetRNGClockSource(RNGxSource))\n  {\n#if defined(RCC_PLLSAI1_SUPPORT)\n    case LL_RCC_RNG_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as RNG clock source */\n      if (LL_RCC_PLLSAI1_IsReady())\n      {\n        rng_frequency = RCC_PLLSAI1_GetFreqDomain_48M();\n      }\n      break;\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n    case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */\n      if (LL_RCC_PLL_IsReady())\n      {\n        rng_frequency = RCC_PLL_GetFreqDomain_48M();\n      }\n      break;\n\n    case LL_RCC_RNG_CLKSOURCE_MSI:           /* MSI clock used as RNG clock source */\n      if (LL_RCC_MSI_IsReady())\n      {\n        rng_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      }\n      break;\n\n\n#if defined(RCC_HSI48_SUPPORT)\n    case LL_RCC_RNG_CLKSOURCE_HSI48:      /* HSI48 used as SDMMC1 clock source */\n      if (LL_RCC_HSI48_IsReady())\n      {\n        rng_frequency = HSI48_VALUE;\n      }\n      break;\n#else\n    case LL_RCC_RNG_CLKSOURCE_NONE:       /* No clock used as SDMMC1 clock source */\n#endif\n    default:\n      rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n      break;\n\n  }\n\n  return rng_frequency;\n}\n\n\n#if   defined(USB_OTG_FS)||defined(USB)\n/**\n  * @brief  Return USBx clock frequency\n  * @param  USBxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_USB_CLKSOURCE\n  * @retval USB clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected\n  */\nuint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)\n{\n  uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));\n\n  /* USBCLK clock frequency */\n  switch (LL_RCC_GetUSBClockSource(USBxSource))\n  {\n#if defined(RCC_PLLSAI1_SUPPORT)\n    case LL_RCC_USB_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as USB clock source */\n      if (LL_RCC_PLLSAI1_IsReady())\n      {\n        usb_frequency = RCC_PLLSAI1_GetFreqDomain_48M();\n      }\n      break;\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n    case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */\n      if (LL_RCC_PLL_IsReady())\n      {\n        usb_frequency = RCC_PLL_GetFreqDomain_48M();\n      }\n      break;\n\n    case LL_RCC_USB_CLKSOURCE_MSI:           /* MSI clock used as USB clock source */\n      if (LL_RCC_MSI_IsReady())\n      {\n        usb_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      }\n      break;\n\n#if defined(RCC_HSI48_SUPPORT)\n    case LL_RCC_USB_CLKSOURCE_HSI48:      /* HSI48 used as USB clock source */\n      if (LL_RCC_HSI48_IsReady())\n      {\n        usb_frequency = HSI48_VALUE;\n      }\n      break;\n#else\n    case LL_RCC_USB_CLKSOURCE_NONE:       /* No clock used as USB clock source */\n#endif\n    default:\n      usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n      break;\n  }\n\n  return usb_frequency;\n}\n#endif /* USB_OTG_FS || USB */\n\n/**\n  * @brief  Return ADCx clock frequency\n  * @param  ADCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_ADC_CLKSOURCE\n  * @retval ADC clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI) or PLL is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected\n  */\nuint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)\n{\n  uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));\n\n  /* ADCCLK clock frequency */\n  switch (LL_RCC_GetADCClockSource(ADCxSource))\n  {\n#if defined(RCC_PLLSAI1_SUPPORT)\n    case LL_RCC_ADC_CLKSOURCE_PLLSAI1:       /* PLLSAI1 clock used as ADC clock source */\n      if (LL_RCC_PLLSAI1_IsReady())\n      {\n        adc_frequency = RCC_PLLSAI1_GetFreqDomain_ADC();\n      }\n      break;\n\n#if defined(RCC_PLLSAI2_SUPPORT) && defined(LL_RCC_ADC_CLKSOURCE_PLLSAI2)\n    case LL_RCC_ADC_CLKSOURCE_PLLSAI2:       /* PLLSAI2 clock used as ADC clock source */\n      if (LL_RCC_PLLSAI2_IsReady())\n      {\n         adc_frequency = RCC_PLLSAI2_GetFreqDomain_ADC();\n      }\n      break;\n#endif /* RCC_PLLSAI2_SUPPORT && LL_RCC_ADC_CLKSOURCE_PLLSAI2 */\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n    case LL_RCC_ADC_CLKSOURCE_SYSCLK:        /* SYSCLK clock used as ADC clock source */\n      adc_frequency = RCC_GetSystemClockFreq();\n      break;\n    case LL_RCC_ADC_CLKSOURCE_NONE:          /* No clock used as ADC clock source */\n    default:\n      adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n      break;\n  }\n\n  return adc_frequency;\n}\n\n#if defined(SWPMI1)\n/**\n  * @brief  Return SWPMIx clock frequency\n  * @param  SWPMIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_SWPMI1_CLKSOURCE\n  * @retval SWPMI clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready\n  */\nuint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource)\n{\n  uint32_t swpmi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_SWPMI_CLKSOURCE(SWPMIxSource));\n\n  /* SWPMI1CLK clock frequency */\n  switch (LL_RCC_GetSWPMIClockSource(SWPMIxSource))\n  {\n    case LL_RCC_SWPMI1_CLKSOURCE_HSI:        /* SWPMI1 Clock is HSI Osc. */\n      if (LL_RCC_HSI_IsReady())\n      {\n        swpmi_frequency = HSI_VALUE;\n      }\n      break;\n\n    case LL_RCC_SWPMI1_CLKSOURCE_PCLK1:      /* SWPMI1 Clock is PCLK1 */\n    default:\n      swpmi_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n      break;\n  }\n\n  return swpmi_frequency;\n}\n#endif /* SWPMI1 */\n\n#if defined(DFSDM1_Channel0)\n/**\n  * @brief  Return DFSDMx clock frequency\n  * @param  DFSDMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE\n  * @retval DFSDM clock frequency (in Hz)\n  */\nuint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)\n{\n  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));\n\n  /* DFSDM1CLK clock frequency */\n  switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))\n  {\n    case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK:     /* DFSDM1 Clock is SYSCLK */\n      dfsdm_frequency = RCC_GetSystemClockFreq();\n      break;\n\n    case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:      /* DFSDM1 Clock is PCLK2 */\n    default:\n      dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));\n      break;\n  }\n\n  return dfsdm_frequency;\n}\n\n#if defined(RCC_CCIPR2_DFSDM1SEL)\n/**\n  * @brief  Return DFSDMx Audio clock frequency\n  * @param  DFSDMxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE\n  * @retval DFSDM clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  */\nuint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)\n{\n  uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));\n\n  /* DFSDM1CLK clock frequency */\n  switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))\n  {\n    case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1:     /* SAI1 clock used as DFSDM1 audio clock */\n      dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE);\n      break;\n\n    case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI:      /* MSI clock used as DFSDM1 audio clock */\n      if (LL_RCC_MSI_IsReady())\n      {\n        dfsdm_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      }\n      break;\n\n    case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI:      /* HSI clock used as DFSDM1 audio clock */\n    default:\n      if (LL_RCC_HSI_IsReady())\n      {\n        dfsdm_frequency = HSI_VALUE;\n      }\n      break;\n  }\n\n  return dfsdm_frequency;\n}\n#endif /* RCC_CCIPR2_DFSDM1SEL */\n#endif /* DFSDM1_Channel0 */\n\n#if defined(DSI)\n/**\n  * @brief  Return DSI clock frequency\n  * @param  DSIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_DSI_CLKSOURCE\n  * @retval DSI clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used\n  */\nuint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)\n{\n  uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));\n\n  /* DSICLK clock frequency */\n  switch (LL_RCC_GetDSIClockSource(DSIxSource))\n  {\n    case LL_RCC_DSI_CLKSOURCE_PLL:     /* DSI Clock is PLLSAI2 Osc. */\n      if (LL_RCC_PLLSAI2_IsReady())\n      {\n        dsi_frequency = RCC_PLLSAI2_GetFreqDomain_DSI();\n      }\n      break;\n\n    case LL_RCC_DSI_CLKSOURCE_PHY:    /* DSI Clock is DSI physical clock. */\n    default:\n      dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;\n      break;\n  }\n\n  return dsi_frequency;\n}\n#endif /* DSI */\n\n#if defined(LTDC)\n/**\n  * @brief  Return LTDC clock frequency\n  * @param  LTDCxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_LTDC_CLKSOURCE\n  * @retval LTDC clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready\n  */\nuint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)\n{\n  uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));\n\n  if (LL_RCC_PLLSAI2_IsReady())\n  {\n     ltdc_frequency = RCC_PLLSAI2_GetFreqDomain_LTDC();\n  }\n\n  return ltdc_frequency;\n}\n#endif /* LTDC */\n\n#if defined(OCTOSPI1)\n/**\n  * @brief  Return OCTOSPI clock frequency\n  * @param  OCTOSPIxSource This parameter can be one of the following values:\n  *         @arg @ref LL_RCC_OCTOSPI_CLKSOURCE\n  * @retval OCTOSPI clock frequency (in Hz)\n  *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready\n  */\nuint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource)\n{\n  uint32_t octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check parameter */\n  assert_param(IS_LL_RCC_OCTOSPI_CLKSOURCE(OCTOSPIxSource));\n\n  /* OCTOSPI clock frequency */\n  switch (LL_RCC_GetOCTOSPIClockSource(OCTOSPIxSource))\n  {\n    case LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK:   /* OCTOSPI clock is SYSCLK */\n      octospi_frequency = RCC_GetSystemClockFreq();\n      break;\n\n    case LL_RCC_OCTOSPI_CLKSOURCE_MSI:      /* MSI clock used as OCTOSPI clock */\n      if (LL_RCC_MSI_IsReady())\n      {\n        octospi_frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                     (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                      LL_RCC_MSI_GetRange() :\n                                      LL_RCC_MSI_GetRangeAfterStandby()));\n      }\n      break;\n\n    case LL_RCC_OCTOSPI_CLKSOURCE_PLL:      /* PLL clock used as OCTOSPI source */\n      if (LL_RCC_PLL_IsReady())\n      {\n        octospi_frequency = RCC_PLL_GetFreqDomain_48M();\n      }\n      break;\n\n    default:\n      octospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;\n      break;\n  }\n\n  return octospi_frequency;\n}\n#endif /* OCTOSPI1 */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup RCC_LL_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Return SYSTEM clock frequency\n  * @retval SYSTEM clock frequency (in Hz)\n  */\nuint32_t RCC_GetSystemClockFreq(void)\n{\n  uint32_t frequency = 0U;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  switch (LL_RCC_GetSysClkSource())\n  {\n    case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */\n      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */\n      frequency = HSI_VALUE;\n      break;\n\n    case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */\n      frequency = HSE_VALUE;\n      break;\n\n    case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */\n      frequency = RCC_PLL_GetFreqDomain_SYS();\n      break;\n\n    default:\n      frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n\n  return frequency;\n}\n\n/**\n  * @brief  Return HCLK clock frequency\n  * @param  SYSCLK_Frequency SYSCLK clock frequency\n  * @retval HCLK clock frequency (in Hz)\n  */\nuint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)\n{\n  /* HCLK clock frequency */\n  return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());\n}\n\n/**\n  * @brief  Return PCLK1 clock frequency\n  * @param  HCLK_Frequency HCLK clock frequency\n  * @retval PCLK1 clock frequency (in Hz)\n  */\nuint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)\n{\n  /* PCLK1 clock frequency */\n  return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());\n}\n\n/**\n  * @brief  Return PCLK2 clock frequency\n  * @param  HCLK_Frequency HCLK clock frequency\n  * @retval PCLK2 clock frequency (in Hz)\n  */\nuint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)\n{\n  /* PCLK2 clock frequency */\n  return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());\n}\n\n/**\n  * @brief  Return PLL clock frequency used for system domain\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_SYS(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN\n     SYSCLK = PLL_VCO / PLLR\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());\n}\n\n#if defined(SAI1)\n/**\n  * @brief  Return PLL clock frequency used for SAI domain\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_SAI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE / PLLM) * PLLN\n     SAI Domain clock = PLL_VCO / PLLP\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());\n}\n#endif /* SAI1 */\n\n/**\n  * @brief  Return PLL clock frequency used for 48 MHz domain\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLL_GetFreqDomain_48M(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN\n     48M Domain clock = PLL_VCO / PLLQ\n  */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLL clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n  return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());\n}\n#if defined(DSI)\n/**\n  * @brief  Return PLL clock frequency used for DSI clock\n  * @retval PLL clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI2_GetFreqDomain_DSI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */\n  /* DSICLK = PLLSAI2_VCO / PLLSAI2R */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n\n  return __LL_RCC_CALC_PLLSAI2_DSI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),\n                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());\n}\n#endif /* DSI */\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n/**\n  * @brief  Return PLLSAI1 clock frequency used for SAI domain\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\n  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */\n#else\n  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */\n#endif\n  /* SAI Domain clock  = PLLSAI1_VCO / PLLSAI1P */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI1_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetP());\n}\n\n/**\n  * @brief  Return PLLSAI1 clock frequency used for 48Mhz domain\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\n  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */\n#else\n  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */\n#endif\n  /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1Q */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());\n}\n\n/**\n  * @brief  Return PLLSAI1 clock frequency used for ADC domain\n  * @retval PLLSAI1 clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\n  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI1M) * PLLSAI1N */\n#else\n  /* PLLSAI1_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI1N */\n#endif\n  /* 48M Domain clock  = PLLSAI1_VCO / PLLSAI1R */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI1 clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI1 clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI1 clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI1_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetR());\n}\n#endif /* RCC_PLLSAI1_SUPPORT */\n\n#if defined(RCC_PLLSAI2_SUPPORT)\n/**\n  * @brief  Return PLLSAI2 clock frequency used for SAI domain\n  * @retval PLLSAI2 clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n#if  defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\n  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */\n#else\n  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */\n#endif\n  /* SAI Domain clock  = PLLSAI2_VCO / PLLSAI2P */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)\n  return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),\n                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());\n#else\n  return __LL_RCC_CALC_PLLSAI2_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetP());\n#endif\n}\n\n#if  defined(LTDC)\n/**\n  * @brief  Return PLLSAI2 clock frequency used for LTDC domain\n  * @retval PLLSAI2 clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI2_GetFreqDomain_LTDC(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLSAI2M) * PLLSAI2N */\n  /* LTDC Domain clock  = (PLLSAI2_VCO / PLLSAI2R) / PLLSAI2DIVR */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n\n  return __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI2_GetDivider(),\n                                         LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR(), LL_RCC_PLLSAI2_GetDIVR());\n}\n\n#else\n\n  /**\n  * @brief  Return PLLSAI2 clock frequency used for ADC domain\n  * @retval PLLSAI2 clock frequency (in Hz)\n  */\nuint32_t RCC_PLLSAI2_GetFreqDomain_ADC(void)\n{\n  uint32_t pllinputfreq = 0U, pllsource = 0U;\n\n  /* PLLSAI2_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLSAI2N */\n  /* 48M Domain clock  = PLLSAI2_VCO / PLLSAI2R */\n  pllsource = LL_RCC_PLL_GetMainSource();\n\n  switch (pllsource)\n  {\n    case LL_RCC_PLLSOURCE_MSI:  /* MSI used as PLLSAI2 clock source */\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n\n    case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLLSAI2 clock source */\n      pllinputfreq = HSI_VALUE;\n      break;\n\n    case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLLSAI2 clock source */\n      pllinputfreq = HSE_VALUE;\n      break;\n\n    default:\n      pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),\n                                    (LL_RCC_MSI_IsEnabledRangeSelect() ?\n                                     LL_RCC_MSI_GetRange() :\n                                     LL_RCC_MSI_GetRangeAfterStandby()));\n      break;\n  }\n  return __LL_RCC_CALC_PLLSAI2_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),\n                                        LL_RCC_PLLSAI2_GetN(), LL_RCC_PLLSAI2_GetR());\n}\n#endif /* LTDC */\n\n#endif /*RCC_PLLSAI2_SUPPORT*/\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* defined(RCC) */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_usart.c\n  * @author  MCD Application Team\n  * @brief   USART LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx_ll_usart.h\"\n#include \"stm32l4xx_ll_rcc.h\"\n#include \"stm32l4xx_ll_bus.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)\n\n/** @addtogroup USART_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @addtogroup USART_LL_Private_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup USART_LL_Private_Macros\n  * @{\n  */\n\n#if defined(USART_PRESC_PRESCALER)\n#define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \\\n                                        || ((__VALUE__) == LL_USART_PRESCALER_DIV256))\n\n#endif\n/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available\n *              divided by the smallest oversampling used on the USART (i.e. 8)    */\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 15000000U)\n#else\n#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)\n#endif\n\n/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */\n#define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \\\n                                    && ((__VALUE__) <= 0x0000FFFFU))\n\n#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_RX) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_TX) \\\n                                       || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))\n\n#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \\\n                                    || ((__VALUE__) == LL_USART_PARITY_EVEN) \\\n                                    || ((__VALUE__) == LL_USART_PARITY_ODD))\n\n#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \\\n                                       || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \\\n                                       || ((__VALUE__) == LL_USART_DATAWIDTH_9B))\n\n#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \\\n                                          || ((__VALUE__) == LL_USART_OVERSAMPLING_8))\n\n#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \\\n                                              || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))\n\n#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \\\n                                        || ((__VALUE__) == LL_USART_PHASE_2EDGE))\n\n#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \\\n                                           || ((__VALUE__) == LL_USART_POLARITY_HIGH))\n\n#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \\\n                                         || ((__VALUE__) == LL_USART_CLOCK_ENABLE))\n\n#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_1) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_1_5) \\\n                                      || ((__VALUE__) == LL_USART_STOPBITS_2))\n\n#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \\\n                                       || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))\n\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup USART_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup USART_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize USART registers (Registers restored to their default values).\n  * @param  USARTx USART Instance\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers are de-initialized\n  *          - ERROR: USART registers are not de-initialized\n  */\nErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n\n  if (USARTx == USART1)\n  {\n    /* Force reset of USART clock */\n    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);\n\n    /* Release reset of USART clock */\n    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);\n  }\n  else if (USARTx == USART2)\n  {\n    /* Force reset of USART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);\n\n    /* Release reset of USART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);\n  }\n#if defined(USART3)\n  else if (USARTx == USART3)\n  {\n    /* Force reset of USART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);\n\n    /* Release reset of USART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);\n  }\n#endif /* USART3 */\n#if defined(UART4)\n  else if (USARTx == UART4)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);\n  }\n#endif /* UART4 */\n#if defined(UART5)\n  else if (USARTx == UART5)\n  {\n    /* Force reset of UART clock */\n    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);\n\n    /* Release reset of UART clock */\n    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);\n  }\n#endif /* UART5 */\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief  Initialize USART registers according to the specified\n  *         parameters in USART_InitStruct.\n  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),\n  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.\n  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).\n  * @param  USARTx USART Instance\n  * @param  USART_InitStruct: pointer to a LL_USART_InitTypeDef structure\n  *         that contains the configuration information for the specified USART peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content\n  *          - ERROR: Problem occurred during USART Registers initialization\n  */\nErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)\n{\n  ErrorStatus status = ERROR;\n  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;\n\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n#if defined(USART_PRESC_PRESCALER)\n  assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));\n#endif\n  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));\n  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));\n  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));\n  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));\n  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));\n  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));\n  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));\n\n  /* USART needs to be in disabled state, in order to be able to configure some bits in\n     CRx registers */\n  if (LL_USART_IsEnabled(USARTx) == 0U)\n  {\n    /*---------------------------- USART CR1 Configuration ---------------------\n     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:\n     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value\n     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value\n     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value\n     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.\n     */\n    MODIFY_REG(USARTx->CR1,\n               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |\n                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),\n               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |\n                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));\n\n    /*---------------------------- USART CR2 Configuration ---------------------\n     * Configure USARTx CR2 (Stop bits) with parameters:\n     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.\n     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().\n     */\n    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);\n\n    /*---------------------------- USART CR3 Configuration ---------------------\n     * Configure USARTx CR3 (Hardware Flow Control) with parameters:\n     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.\n     */\n    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);\n\n    /*---------------------------- USART BRR Configuration ---------------------\n     * Retrieve Clock frequency used for USART Peripheral\n     */\n    if (USARTx == USART1)\n    {\n      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);\n    }\n    else if (USARTx == USART2)\n    {\n      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);\n    }\n#if defined(USART3)\n    else if (USARTx == USART3)\n    {\n      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);\n    }\n#endif /* USART3 */\n#if defined(UART4)\n    else if (USARTx == UART4)\n    {\n      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);\n    }\n#endif /* UART4 */\n#if defined(UART5)\n    else if (USARTx == UART5)\n    {\n      periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);\n    }\n#endif /* UART5 */\n    else\n    {\n      /* Nothing to do, as error code is already assigned to ERROR value */\n    }\n\n    /* Configure the USART Baud Rate :\n#if defined(USART_PRESC_PRESCALER)\n       - prescaler value is required\n#endif\n       - valid baud rate value (different from 0) is required\n       - Peripheral clock as returned by RCC service, should be valid (different from 0).\n    */\n    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)\n        && (USART_InitStruct->BaudRate != 0U))\n    {\n      status = SUCCESS;\n      LL_USART_SetBaudRate(USARTx,\n                           periphclk,\n#if defined(USART_PRESC_PRESCALER)\n                           USART_InitStruct->PrescalerValue,\n#endif\n                           USART_InitStruct->OverSampling,\n                           USART_InitStruct->BaudRate);\n\n      /* Check BRR is greater than or equal to 16d */\n      assert_param(IS_LL_USART_BRR(USARTx->BRR));\n    }\n\n#if defined(USART_PRESC_PRESCALER)\n    /*---------------------------- USART PRESC Configuration -----------------------\n     * Configure USARTx PRESC (Prescaler) with parameters:\n     * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.\n     */\n    LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);\n#endif\n  }\n  /* Endif (=> USART not in Disabled state => return ERROR) */\n\n  return (status);\n}\n\n/**\n  * @brief Set each @ref LL_USART_InitTypeDef field to default value.\n  * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure\n  *                          whose fields will be set to default values.\n  * @retval None\n  */\n\nvoid LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)\n{\n  /* Set USART_InitStruct fields to default values */\n#if defined(USART_PRESC_PRESCALER)\n  USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;\n#endif\n  USART_InitStruct->BaudRate            = 9600U;\n  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;\n  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;\n  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;\n  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;\n  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;\n  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;\n}\n\n/**\n  * @brief  Initialize USART Clock related settings according to the\n  *         specified parameters in the USART_ClockInitStruct.\n  * @note   As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),\n  *         USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.\n  * @param  USARTx USART Instance\n  * @param  USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure\n  *         that contains the Clock configuration information for the specified USART peripheral.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content\n  *          - ERROR: Problem occurred during USART Registers initialization\n  */\nErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check USART Instance and Clock signal output parameters */\n  assert_param(IS_UART_INSTANCE(USARTx));\n  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));\n\n  /* USART needs to be in disabled state, in order to be able to configure some bits in\n     CRx registers */\n  if (LL_USART_IsEnabled(USARTx) == 0U)\n  {\n    /*---------------------------- USART CR2 Configuration -----------------------*/\n    /* If Clock signal has to be output */\n    if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)\n    {\n      /* Deactivate Clock signal delivery :\n       * - Disable Clock Output:        USART_CR2_CLKEN cleared\n       */\n      LL_USART_DisableSCLKOutput(USARTx);\n    }\n    else\n    {\n      /* Ensure USART instance is USART capable */\n      assert_param(IS_USART_INSTANCE(USARTx));\n\n      /* Check clock related parameters */\n      assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));\n      assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));\n      assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));\n\n      /*---------------------------- USART CR2 Configuration -----------------------\n       * Configure USARTx CR2 (Clock signal related bits) with parameters:\n       * - Enable Clock Output:         USART_CR2_CLKEN set\n       * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value\n       * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value\n       * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.\n       */\n      MODIFY_REG(USARTx->CR2,\n                 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,\n                 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |\n                 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);\n    }\n  }\n  /* Else (USART not in Disabled state => return ERROR */\n  else\n  {\n    status = ERROR;\n  }\n\n  return (status);\n}\n\n/**\n  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.\n  * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure\n  *                               whose fields will be set to default values.\n  * @retval None\n  */\nvoid LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)\n{\n  /* Set LL_USART_ClockInitStruct fields with default values */\n  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;\n  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n\n"
  },
  {
    "path": "examples/lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_ll_utils.c\n  * @author  MCD Application Team\n  * @brief   UTILS LL module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx_ll_utils.h\"\n#include \"stm32l4xx_ll_rcc.h\"\n#include \"stm32l4xx_ll_system.h\"\n#include \"stm32l4xx_ll_pwr.h\"\n#ifdef  USE_FULL_ASSERT\n#include \"stm32_assert.h\"\n#else\n#define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n/** @addtogroup STM32L4xx_LL_Driver\n  * @{\n  */\n\n/** @addtogroup UTILS_LL\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Private_Constants\n  * @{\n  */\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n#define UTILS_MAX_FREQUENCY_SCALE1  120000000U       /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define UTILS_MAX_FREQUENCY_SCALE2   26000000U       /*!< Maximum frequency for system clock at power scale2, in Hz */\n#else\n#define UTILS_MAX_FREQUENCY_SCALE1   80000000U       /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define UTILS_MAX_FREQUENCY_SCALE2   26000000U       /*!< Maximum frequency for system clock at power scale2, in Hz */\n#endif\n\n/* Defines used for PLL range */\n#define UTILS_PLLVCO_INPUT_MIN        4000000U       /*!< Frequency min for PLLVCO input, in Hz   */\n#define UTILS_PLLVCO_INPUT_MAX       16000000U       /*!< Frequency max for PLLVCO input, in Hz   */\n#define UTILS_PLLVCO_OUTPUT_MIN      64000000U       /*!< Frequency min for PLLVCO output, in Hz  */\n#define UTILS_PLLVCO_OUTPUT_MAX     344000000U       /*!< Frequency max for PLLVCO output, in Hz  */\n\n/* Defines used for HSE range */\n#define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */\n#define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */\n\n/* Defines used for FLASH latency according to HCLK Frequency */\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n#define UTILS_SCALE1_LATENCY1_FREQ   20000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */\n#define UTILS_SCALE1_LATENCY2_FREQ   40000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */\n#define UTILS_SCALE1_LATENCY3_FREQ   60000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */\n#define UTILS_SCALE1_LATENCY4_FREQ   80000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */\n#define UTILS_SCALE1_LATENCY5_FREQ  100000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */\n#define UTILS_SCALE2_LATENCY1_FREQ    8000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */\n#define UTILS_SCALE2_LATENCY2_FREQ   16000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */\n#else\n#define UTILS_SCALE1_LATENCY1_FREQ   16000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */\n#define UTILS_SCALE1_LATENCY2_FREQ   32000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */\n#define UTILS_SCALE1_LATENCY3_FREQ   48000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */\n#define UTILS_SCALE1_LATENCY4_FREQ   64000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */\n#define UTILS_SCALE2_LATENCY1_FREQ    6000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */\n#define UTILS_SCALE2_LATENCY2_FREQ   12000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */\n#define UTILS_SCALE2_LATENCY3_FREQ   18000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */\n#endif\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Private_Macros\n  * @{\n  */\n#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \\\n                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))\n\n#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \\\n                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))\n\n#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_2) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_4) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_8) \\\n                                      || ((__VALUE__) == LL_RCC_APB2_DIV_16))\n\n#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \\\n                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8))\n\n#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))\n\n#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \\\n                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \\\n                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \\\n                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_8))\n\n#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))\n\n#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))\n\n#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \\\n                                             ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))\n\n#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \\\n                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))\n\n#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))\n/**\n  * @}\n  */\n/* Private function prototypes -----------------------------------------------*/\n/** @defgroup UTILS_LL_Private_Functions UTILS Private functions\n  * @{\n  */\nstatic uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,\n                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);\nstatic ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);\nstatic ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);\nstatic ErrorStatus UTILS_PLL_IsBusy(void);\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup UTILS_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup UTILS_LL_EF_DELAY\n  * @{\n  */\n\n/**\n  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.\n  * @note   When a RTOS is used, it is recommended to avoid changing the Systick\n  *         configuration by calling this function, for a delay use rather osDelay RTOS service.\n  * @param  HCLKFrequency HCLK frequency in Hz\n  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq\n  * @retval None\n  */\nvoid LL_Init1msTick(uint32_t HCLKFrequency)\n{\n  /* Use frequency provided in argument */\n  LL_InitTick(HCLKFrequency, 1000U);\n}\n\n/**\n  * @brief  This function provides accurate delay (in milliseconds) based\n  *         on SysTick counter flag\n  * @note   When a RTOS is used, it is recommended to avoid using blocking delay\n  *         and use rather osDelay service.\n  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which\n  *         will configure Systick to 1ms\n  * @param  Delay specifies the delay time length, in milliseconds.\n  * @retval None\n  */\nvoid LL_mDelay(uint32_t Delay)\n{\n  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */\n  /* Add this code to indicate that local variable is not used */\n  ((void)tmp);\n\n  /* Add a period to guaranty minimum wait */\n  if(Delay < LL_MAX_DELAY)\n  {\n    Delay++;\n  }\n\n  while (Delay)\n  {\n    if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)\n    {\n      Delay--;\n    }\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup UTILS_EF_SYSTEM\n  *  @brief    System Configuration functions\n  *\n  @verbatim\n ===============================================================================\n           ##### System Configuration functions #####\n ===============================================================================\n    [..]\n         System, AHB and APB buses clocks configuration\n\n         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is \n             120000000 Hz for STM32L4Rx/STM32L4Sx devices and 80000000 Hz for others.\n  @endverbatim\n  @internal\n             Depending on the device voltage range, the maximum frequency should be\n             adapted accordingly:\n\n             (++) Table 1. HCLK clock frequency for STM32L4Rx/STM32L4Sx devices\n             (++) +--------------------------------------------------------+\n             (++) | Latency         |     HCLK clock frequency (MHz)       |\n             (++) |                 |--------------------------------------|\n             (++) |                 |  voltage range 1  | voltage range 2  |\n             (++) |                 |       1.2 V       |     1.0 V        |\n             (++) |-----------------|-------------------|------------------|\n             (++) |0WS(1 CPU cycles)|   0 < HCLK <= 20  |  0 < HCLK <= 8   |\n             (++) |-----------------|-------------------|------------------|\n             (++) |1WS(2 CPU cycles)|  20 < HCLK <= 40  |  8 < HCLK <= 16  |\n             (++) |-----------------|-------------------|------------------|\n             (++) |2WS(3 CPU cycles)|  40 < HCLK <= 60  | 16 < HCLK <= 26  |\n             (++) |-----------------|-------------------|------------------|\n             (++) |3WS(4 CPU cycles)|  60 < HCLK <= 80  | 16 < HCLK <= 26  |\n             (++) |-----------------|-------------------|------------------|\n             (++) |4WS(5 CPU cycles)|  80 < HCLK <= 100 | 16 < HCLK <= 26  |\n             (++) |-----------------|-------------------|------------------|\n             (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26  |\n             (++) +--------------------------------------------------------+\n\n             (++) Table 2. HCLK clock frequency for other STM32L4 devices\n             (++) +-------------------------------------------------------+\n             (++) | Latency         |    HCLK clock frequency (MHz)       |\n             (++) |                 |-------------------------------------|\n             (++) |                 | voltage range 1  | voltage range 2  |\n             (++) |                 |      1.2 V       |     1.0 V        |\n             (++) |-----------------|------------------|------------------|\n             (++) |0WS(1 CPU cycles)|  0 < HCLK <= 16  |  0 < HCLK <= 6   |\n             (++) |-----------------|------------------|------------------|\n             (++) |1WS(2 CPU cycles)| 16 < HCLK <= 32  |  6 < HCLK <= 12  |\n             (++) |-----------------|------------------|------------------|\n             (++) |2WS(3 CPU cycles)| 32 < HCLK <= 48  | 12 < HCLK <= 18  |\n             (++) |-----------------|------------------|------------------|\n             (++) |3WS(4 CPU cycles)| 48 < HCLK <= 64  | 18 < HCLK <= 26  |\n             (++) |-----------------|------------------|------------------|\n             (++) |4WS(5 CPU cycles)| 64 < HCLK <= 80  | 18 < HCLK <= 26  |\n             (++) +-------------------------------------------------------+\n\n  @endinternal\n  * @{\n  */\n\n/**\n  * @brief  This function sets directly SystemCoreClock CMSIS variable.\n  * @note   Variable can be calculated also through SystemCoreClockUpdate function.\n  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)\n  * @retval None\n  */\nvoid LL_SetSystemCoreClock(uint32_t HCLKFrequency)\n{\n  /* HCLK clock frequency */\n  SystemCoreClock = HCLKFrequency;\n}\n\n/**\n  * @brief  This function configures system clock with MSI as clock source of the PLL\n  * @note   The application needs to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.\n  * @note   Function is based on the following formula:\n  *         - PLL output frequency = (((MSI frequency / PLLM) * PLLN) / PLLR)\n  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = MSI frequency / PLLM)\n  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)\n  *         - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Max frequency configuration done\n  *          - ERROR: Max frequency configuration not done\n  */\nErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,\n                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t pllfreq = 0U, msi_range = 0U;\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n  uint32_t hpre = 0U;\n#endif\n\n  /* Check if one of the PLL is enabled */\n  if(UTILS_PLL_IsBusy() == SUCCESS)\n  {\n    /* Get the current MSI range */\n    if(LL_RCC_MSI_IsEnabledRangeSelect())\n    {\n      msi_range =  LL_RCC_MSI_GetRange();\n      switch (msi_range)\n      {\n        case LL_RCC_MSIRANGE_0:     /* MSI = 100 KHz  */\n        case LL_RCC_MSIRANGE_1:     /* MSI = 200 KHz  */\n        case LL_RCC_MSIRANGE_2:     /* MSI = 400 KHz  */\n        case LL_RCC_MSIRANGE_3:     /* MSI = 800 KHz  */\n        case LL_RCC_MSIRANGE_4:     /* MSI = 1 MHz    */\n        case LL_RCC_MSIRANGE_5:     /* MSI = 2 MHz    */\n          /* PLLVCO input frequency can not in the range from 4 to 16 MHz*/\n          status = ERROR;\n          break;\n\n        case LL_RCC_MSIRANGE_6:     /* MSI = 4 MHz    */\n        case LL_RCC_MSIRANGE_7:     /* MSI = 8 MHz    */\n        case LL_RCC_MSIRANGE_8:     /* MSI = 16 MHz   */\n        case LL_RCC_MSIRANGE_9:     /* MSI = 24 MHz   */\n        case LL_RCC_MSIRANGE_10:    /* MSI = 32 MHz   */\n        case LL_RCC_MSIRANGE_11:    /* MSI = 48 MHz   */\n        default:\n          break;\n      }\n    }\n    else\n    {\n      msi_range = LL_RCC_MSI_GetRangeAfterStandby();\n      switch (msi_range)\n      {\n        case LL_RCC_MSISRANGE_4:    /* MSI = 1 MHz    */\n        case LL_RCC_MSISRANGE_5:    /* MSI = 2 MHz    */\n          /* PLLVCO input frequency is not in the range from 4 to 16 MHz*/\n          status = ERROR;\n          break;\n\n        case LL_RCC_MSISRANGE_7:    /* MSI = 8 MHz    */\n        case LL_RCC_MSISRANGE_6:    /* MSI = 4 MHz    */\n        default:\n          break;\n      }\n    }\n\n    /* Main PLL configuration and activation */\n    if(status != ERROR)\n    {\n      /* Calculate the new PLL output frequency */\n      pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range),\n                                            UTILS_PLLInitStruct);\n\n      /* Enable MSI if not enabled */\n      if(LL_RCC_MSI_IsReady() != 1U)\n      {\n        LL_RCC_MSI_Enable();\n        while ((LL_RCC_MSI_IsReady() != 1U))\n        {\n          /* Wait for MSI ready */\n        }\n      }\n\n      /* Configure PLL */\n      LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,\n                                  UTILS_PLLInitStruct->PLLR);\n\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n      /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */\n      if(pllfreq > 80000000U)\n      {\n        hpre = UTILS_ClkInitStruct->AHBCLKDivider;\n        if(hpre == LL_RCC_SYSCLK_DIV_1)\n        {\n          UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;\n        }\n      }\n#endif\n      /* Enable PLL and switch system clock to PLL */\n      status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);\n\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n      /* Apply definitive AHB prescaler value if necessary */\n      if((status == SUCCESS) && (hpre != 0U))\n      {\n        UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;\n        LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);\n      }\n#endif\n    }\n  }\n  else\n  {\n    /* Current PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL\n  * @note   The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.\n  * @note   Function is based on the following formula:\n  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)\n  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)\n  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)\n  *         - PLLR: ensure that max frequency at 120000000 Hz is reach (PLLVCO_output / PLLR)\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Max frequency configuration done\n  *          - ERROR: Max frequency configuration not done\n  */\nErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,\n                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t pllfreq = 0U;\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n  uint32_t hpre = 0U;\n#endif\n\n  /* Check if one of the PLL is enabled */\n  if(UTILS_PLL_IsBusy() == SUCCESS)\n  {\n    /* Calculate the new PLL output frequency */\n    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);\n\n    /* Enable HSI if not enabled */\n    if(LL_RCC_HSI_IsReady() != 1U)\n    {\n      LL_RCC_HSI_Enable();\n      while (LL_RCC_HSI_IsReady() != 1U)\n      {\n        /* Wait for HSI ready */\n      }\n    }\n\n    /* Configure PLL */\n    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,\n                                UTILS_PLLInitStruct->PLLR);\n\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n    /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */\n    if(pllfreq > 80000000U)\n    {\n      hpre = UTILS_ClkInitStruct->AHBCLKDivider;\n      if(hpre == LL_RCC_SYSCLK_DIV_1)\n      {\n        UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;\n      }\n    }\n#endif\n    /* Enable PLL and switch system clock to PLL */\n    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);\n\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n    /* Apply definitive AHB prescaler value if necessary */\n    if((status == SUCCESS) && (hpre != 0U))\n    {\n      UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;\n      LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);\n    }\n#endif\n  }\n  else\n  {\n    /* Current PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @brief  This function configures system clock with HSE as clock source of the PLL\n  * @note   The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled.\n  * @note   Function is based on the following formula:\n  *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)\n  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)\n  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)\n  *         - PLLR: ensure that max frequency at 120000000 Hz is reached (PLLVCO_output / PLLR)\n  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000\n  * @param  HSEBypass This parameter can be one of the following values:\n  *         @arg @ref LL_UTILS_HSEBYPASS_ON\n  *         @arg @ref LL_UTILS_HSEBYPASS_OFF\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Max frequency configuration done\n  *          - ERROR: Max frequency configuration not done\n  */\nErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,\n                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t pllfreq = 0U;\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n  uint32_t hpre = 0U;\n#endif\n\n  /* Check the parameters */\n  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));\n  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));\n\n  /* Check if one of the PLL is enabled */\n  if(UTILS_PLL_IsBusy() == SUCCESS)\n  {\n    /* Calculate the new PLL output frequency */\n    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);\n\n    /* Enable HSE if not enabled */\n    if(LL_RCC_HSE_IsReady() != 1U)\n    {\n      /* Check if need to enable HSE bypass feature or not */\n      if(HSEBypass == LL_UTILS_HSEBYPASS_ON)\n      {\n        LL_RCC_HSE_EnableBypass();\n      }\n      else\n      {\n        LL_RCC_HSE_DisableBypass();\n      }\n\n      /* Enable HSE */\n      LL_RCC_HSE_Enable();\n      while (LL_RCC_HSE_IsReady() != 1U)\n      {\n        /* Wait for HSE ready */\n      }\n    }\n\n    /* Configure PLL */\n    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,\n                                UTILS_PLLInitStruct->PLLR);\n\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n    /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */\n    if(pllfreq > 80000000U)\n    {\n      hpre = UTILS_ClkInitStruct->AHBCLKDivider;\n      if(hpre == LL_RCC_SYSCLK_DIV_1)\n      {\n        UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;\n      }\n    }\n#endif\n    /* Enable PLL and switch system clock to PLL */\n    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);\n\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n    /* Apply definitive AHB prescaler value if necessary */\n    if((status == SUCCESS) && (hpre != 0U))\n    {\n      UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;\n      LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);\n    }\n#endif\n  }\n  else\n  {\n    /* Current PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup UTILS_LL_Private_Functions\n  * @{\n  */\n/**\n  * @brief  Update number of Flash wait states in line with new frequency and current\n            voltage range.\n  * @param  HCLK_Frequency  HCLK frequency\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: Latency has been modified\n  *          - ERROR: Latency cannot be modified\n  */\nstatic ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)\n{\n  ErrorStatus status = SUCCESS;\n\n  uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */\n\n  /* Frequency cannot be equal to 0 */\n  if(HCLK_Frequency == 0U)\n  {\n    status = ERROR;\n  }\n  else\n  {\n    if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)\n    {\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n      if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)\n      {\n        /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */\n        latency = LL_FLASH_LATENCY_5;\n      }\n      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)\n      {\n        /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */\n        latency = LL_FLASH_LATENCY_4;\n      }\n      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)\n      {\n        /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */\n        latency = LL_FLASH_LATENCY_3;\n      }\n      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)\n      {\n        /* 40 < HCLK <= 20 => 2WS (3 CPU cycles) */\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)\n        {\n          /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */\n          latency = LL_FLASH_LATENCY_1;\n        }\n        /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */\n      }\n#else\n      if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)\n      {\n        /* 64 < HCLK <= 80 => 4WS (5 CPU cycles) */\n        latency = LL_FLASH_LATENCY_4;\n      }\n      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)\n      {\n        /* 48 < HCLK <= 64 => 3WS (4 CPU cycles) */\n        latency = LL_FLASH_LATENCY_3;\n      }\n      else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)\n      {\n        /* 32 < HCLK <= 48 => 2WS (3 CPU cycles) */\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)\n        {\n          /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */\n          latency = LL_FLASH_LATENCY_1;\n        }\n        /* else HCLK_Frequency <= 16MHz default LL_FLASH_LATENCY_0 0WS */\n      }\n#endif\n    }\n    else /* SCALE2 */\n    {\n#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n      if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)\n      {\n        /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)\n        {\n          /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */\n          latency = LL_FLASH_LATENCY_1;\n        }\n        /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */\n      }\n#else\n      if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)\n      {\n        /* 18 < HCLK <= 26 => 3WS (4 CPU cycles) */\n        latency = LL_FLASH_LATENCY_3;\n      }\n      else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)\n      {\n        /* 12 < HCLK <= 18 => 2WS (3 CPU cycles) */\n        latency = LL_FLASH_LATENCY_2;\n      }\n      else\n      {\n        if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)\n        {\n          /* 6 < HCLK <= 12 => 1WS (2 CPU cycles) */\n          latency = LL_FLASH_LATENCY_1;\n        }\n        /* else HCLK_Frequency <= 6MHz default LL_FLASH_LATENCY_0 0WS */\n      }\n#endif\n    }\n\n    LL_FLASH_SetLatency(latency);\n\n    /* Check that the new number of wait states is taken into account to access the Flash\n       memory by reading the FLASH_ACR register */\n    if(LL_FLASH_GetLatency() != latency)\n    {\n      status = ERROR;\n    }\n  }\n  return status;\n}\n\n/**\n  * @brief  Function to check that PLL can be modified\n  * @param  PLL_InputFrequency  PLL input frequency (in Hz)\n  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains\n  *                             the configuration information for the PLL.\n  * @retval PLL output frequency (in Hz)\n  */\nstatic uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)\n{\n  uint32_t pllfreq = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));\n  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));\n  assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));\n\n  /* Check different PLL parameters according to RM                          */\n  /*  - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz.   */\n  pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1));\n  assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));\n\n  /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/\n  pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));\n  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));\n\n  /*  - PLLR: ensure that max frequency at 120000000 Hz is reached                   */\n  pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1) * 2);\n  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));\n\n  return pllfreq;\n}\n\n/**\n  * @brief  Function to check that PLL can be modified\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: PLL modification can be done\n  *          - ERROR: PLL is busy\n  */\nstatic ErrorStatus UTILS_PLL_IsBusy(void)\n{\n  ErrorStatus status = SUCCESS;\n\n  /* Check if PLL is busy*/\n  if(LL_RCC_PLL_IsReady() != 0U)\n  {\n    /* PLL configuration cannot be modified */\n    status = ERROR;\n  }\n\n#if defined(RCC_PLLSAI1_SUPPORT)\n  /* Check if PLLSAI1 is busy*/\n  if(LL_RCC_PLLSAI1_IsReady() != 0U)\n  {\n    /* PLLSAI1 configuration cannot be modified */\n    status = ERROR;\n  }\n#endif /*RCC_PLLSAI1_SUPPORT*/\n#if defined(RCC_PLLSAI2_SUPPORT)\n\n  /* Check if PLLSAI2 is busy*/\n  if(LL_RCC_PLLSAI2_IsReady() != 0U)\n  {\n    /* PLLSAI2 configuration cannot be modified */\n    status = ERROR;\n  }\n#endif /*RCC_PLLSAI2_SUPPORT*/\n\n  return status;\n}\n\n/**\n  * @brief  Function to enable PLL and switch system clock to PLL\n  * @param  SYSCLK_Frequency SYSCLK frequency\n  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains\n  *                             the configuration information for the BUS prescalers.\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: No problem to switch system to PLL\n  *          - ERROR: Problem to switch system to PLL\n  */\nstatic ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  uint32_t hclk_frequency = 0U;\n\n  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));\n  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));\n  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));\n\n  /* Calculate HCLK frequency */\n  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);\n\n  /* Increasing the number of wait states because of higher CPU frequency */\n  if(SystemCoreClock < hclk_frequency)\n  {\n    /* Set FLASH latency to highest latency */\n    status = UTILS_SetFlashLatency(hclk_frequency);\n  }\n\n  /* Update system clock configuration */\n  if(status == SUCCESS)\n  {\n    /* Enable PLL */\n    LL_RCC_PLL_Enable();\n    LL_RCC_PLL_EnableDomain_SYS();\n    while (LL_RCC_PLL_IsReady() != 1U)\n    {\n      /* Wait for PLL ready */\n    }\n\n    /* Sysclk activation on the main PLL */\n    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);\n    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);\n    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)\n    {\n      /* Wait for system clock switch to PLL */\n    }\n\n    /* Set APB1 & APB2 prescaler*/\n    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);\n    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);\n  }\n    \n  /* Decreasing the number of wait states because of lower CPU frequency */\n  if(SystemCoreClock > hclk_frequency)\n  {\n    /* Set FLASH latency to lowest latency */\n    status = UTILS_SetFlashLatency(hclk_frequency);\n  }\n\n  /* Update SystemCoreClock variable */\n  if(status == SUCCESS)\n  {\n    LL_SetSystemCoreClock(hclk_frequency);\n  }\n\n  return status;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/posix/README.md",
    "content": ""
  },
  {
    "path": "examples/posix/sntp_rtos/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.10)\n\nproject(lwesp_sntp_rtos)\n\nset(C_SOURCES\n    \"../../../snippets/sntp.c\"\n    \"../../../snippets/station_manager.c\"\n    \"../../../snippets/utils.c\"\n    \"../../../lwesp/src/lwesp/lwesp_ap.c\"\n    \"../../../lwesp/src/lwesp/lwesp_buff.c\"\n    \"../../../lwesp/src/lwesp/lwesp_conn.c\"\n    \"../../../lwesp/src/lwesp/lwesp_debug.c\"\n    \"../../../lwesp/src/lwesp/lwesp_dns.c\"\n    \"../../../lwesp/src/lwesp/lwesp_evt.c\"\n    \"../../../lwesp/src/lwesp/lwesp_input.c\"\n    \"../../../lwesp/src/lwesp/lwesp_int.c\"\n    \"../../../lwesp/src/lwesp/lwesp_mem.c\"\n    \"../../../lwesp/src/lwesp/lwesp_parser.c\"\n    \"../../../lwesp/src/lwesp/lwesp_pbuf.c\"\n    \"../../../lwesp/src/lwesp/lwesp_sntp.c\"\n    \"../../../lwesp/src/lwesp/lwesp_sta.c\"\n    \"../../../lwesp/src/lwesp/lwesp_threads.c\"\n    \"../../../lwesp/src/lwesp/lwesp_timeout.c\"\n    \"../../../lwesp/src/lwesp/lwesp_unicode.c\"\n    \"../../../lwesp/src/lwesp/lwesp_wps.c\"\n    \"../../../lwesp/src/lwesp/lwesp_utils.c\"\n    \"../../../lwesp/src/lwesp/lwesp.c\"\n    \"../../../lwesp/src/system/lwesp_ll_posix.c\"\n    \"../../../lwesp/src/system/lwesp_mem_posix.c\"\n    \"../../../lwesp/src/system/lwesp_sys_posix.c\"\n    \"main.c\"\n)\n\nset(C_INCLUDES\n    \".\"\n    \"../../../lwesp/src/include/system/port/posix\"\n    \"../../../lwesp/src/include\"\n    \"../../../snippets/include\"\n)\n\nset(C_LIBRARIES\n    \"pthread\"\n)\n\nset(CMAKE_EXE_LINKER_FLAGS \"${CMAKE_EXE_LINKER_FLAGS} -pthread\")\n\nadd_executable(${PROJECT_NAME} ${C_SOURCES})\ntarget_include_directories(${PROJECT_NAME} PRIVATE ${C_INCLUDES})\ntarget_link_libraries(${PROJECT_NAME} PRIVATE ${C_LIBRARIES})\n"
  },
  {
    "path": "examples/posix/sntp_rtos/README.md",
    "content": ""
  },
  {
    "path": "examples/posix/sntp_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          imi415 <imi415.public@gmail.com>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#define LWESP_CFG_SNTP                        1\n\n#define LWESP_CFG_MEM_CUSTOM                  1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/posix/sntp_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using POSIX implementation with USB-TTL or native serial device,\n * check lwesp_ll_posix.c implementation and choose your serial port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"sntp.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /* Start SNTP */\n    sntp_gettime();\n\n    /* Do not stop execution */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/.vscode/c_cpp_properties.json",
    "content": "{\n    \"version\": 4,\n    \"configurations\": [\n        {\n            /* \n             * ms-vscode.cmake-tools plugin should be installed.\n             * \n             * It provides data for C/C++ plugin,\n             * such as include paths, browse paths, defines, etc.\n             */\n            \"name\": \"STM32\",\n            \"configurationProvider\": \"ms-vscode.cmake-tools\",\n            \"intelliSenseMode\": \"${default}\"\n        }\n    ]\n}\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/.vscode/extensions.json",
    "content": "{\n    \"recommendations\": [\n        \"ms-vscode.cpptools\",\n        \"ms-vscode.cmake-tools\",\n        \"marus25.cortex-debug\",\n        \"twxs.cmake\",\n        \"dan-c-underwood.arm\",\n        \"zixuanwang.linkerscript\"\n    ]\n}"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/.vscode/launch.json",
    "content": "{\n    // Use IntelliSense to learn about possible attributes.\n    // Hover to view descriptions of existing attributes.\n    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387\n    \"version\": \"0.2.0\",\n    \"configurations\": [\n        {\n            \"name\": \"Debug Microcontroller - ST-Link\",\n            \"cwd\": \"${workspaceFolder}\",\n            \"type\": \"cortex-debug\",\n            \"executable\": \"${command:cmake.launchTargetPath}\", //or fixed file path: build/stm32h735g-dk-led.elf\n            \"request\": \"launch\",                //Use \"attach\" to connect to target w/o elf download\n            \"servertype\": \"stlink\",\n            \"device\": \"\",                       //MCU used, ex. \"STM32H735IG\"\n            \"interface\": \"swd\",\n            \"serialNumber\": \"\",                 //Set ST-Link ID if you use multiple at the same time\n            \"runToMain\": true,\n            \"svdFile\": \"path/to/file.svd\",      //Path to SVD file to see registers\n            \"v1\": false,\n            \"showDevDebugOutput\": \"both\",\n\n            /* Will get automatically detected if STM32CubeIDE is installed to default directory\n               or it can be manually provided if necessary.. */\n            //\"serverpath\": \"c:\\\\ST\\\\STM32CubeIDE_1.7.0\\\\STM32CubeIDE\\\\plugins\\\\com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.win32_2.0.100.202109301221\\\\tools\\\\bin\\\\ST-LINK_gdbserver.exe\",\n            //\"armToolchainPath\": \"c:\\\\ST\\\\STM32CubeIDE_1.7.0\\\\STM32CubeIDE\\\\plugins\\\\com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_2.0.0.202105311346\\\\tools\\\\bin\",\n            //\"stm32cubeprogrammer\": \"c:\\\\Program Files\\\\STMicroelectronics\\\\STM32Cube\\\\STM32CubeProgrammer\\\\bin\",\n\n            /* If you use external loader, add additional arguments */\n            //\"serverArgs\": [\"--extload\", \"path/to/ext/loader.stldr\"],\n        }\n    ]\n}"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/.vscode/tasks.json",
    "content": "{\n\t\"version\": \"2.0.0\",\n\t\"tasks\": [\n        {\n            \"type\": \"cppbuild\",\n            \"label\": \"Build project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"-j\", \"8\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": [\"$gcc\"],\n            \"group\": {\n                \"kind\": \"build\",\n                \"isDefault\": true\n            }\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Re-build project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"--clean-first\", \"-v\", \"-j\", \"8\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": [\"$gcc\"],\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Clean project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"--target\", \"clean\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"CubeProg: Flash project (SWD)\",\n            \"command\": \"STM32_Programmer_CLI\",\n            \"args\": [\n                \"--connect\",\n                \"port=swd\",\n                \"--download\", \"${command:cmake.launchTargetPath}\",\n                \"-hardRst\"\n            ],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"CubeProg: Flash project with defined serial number (SWD) - you must set serial number first\",\n            \"command\": \"STM32_Programmer_CLI\",\n            \"args\": [\n                \"--connect\",\n                \"port=swd\",\n                \"sn=<yourserialnumber>\",\n                \"--download\", \"${command:cmake.launchTargetPath}\",\n                \"-hardRst\"\n            ],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"CubeProg: List all available communication interfaces\",\n            \"command\": \"STM32_Programmer_CLI\",\n            \"args\": [\n                \"--list\",\n            ],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n    ]\n}\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.22)\n\n#\n# Core project settings\n#\nset(PROJ_PATH                       ${CMAKE_CURRENT_SOURCE_DIR})\nproject(lwesp_stm32f429zi_nucleo_mqtt_client_api_rtos)\nenable_language(C CXX ASM)\nmessage(\"Build type: \"              ${CMAKE_BUILD_TYPE})\n\n# Setup compiler settings\nset(CMAKE_C_STANDARD                11)\nset(CMAKE_C_STANDARD_REQUIRED       ON)\nset(CMAKE_C_EXTENSIONS              ON)\nset(CMAKE_CXX_STANDARD              20)\nset(CMAKE_CXX_STANDARD_REQUIRED     ON)\nset(CMAKE_CXX_EXTENSIONS            ON)\n\n#\n# Core MCU flags, CPU, instruction set and FPU setup\n#\nset(CPU_PARAMETERS\n    -mthumb\n    # Other parameters\n    # -mcpu, -mfloat, -mfloat-abi, ...\n    -mcpu=cortex-m4\n    -mfpu=fpv4-sp-d16\n    -mfloat-abi=hard\n)\n\n# Set linker script\nset(linker_script_SRC               ${PROJ_PATH}/STM32CubeIDE/Debug_STM32F429ZI_FLASH.ld)\nset(EXECUTABLE                      ${CMAKE_PROJECT_NAME})\n\n#\n# Source files\n#\nset(src_freertos_SRCS \n    ${PROJ_PATH}/../../lib/FreeRTOS/CMSIS_RTOS_V2/cmsis_os2.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/croutine.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/event_groups.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/portable/MemMang/heap_4.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/list.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/portable/GCC/ARM_CM4F/port.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/queue.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/tasks.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/timers.c)\n\nset(src_stm32f4xx_hal_driver_SRCS \n    ${PROJ_PATH}/../../lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_dma.c\n    ${PROJ_PATH}/../../lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_exti.c\n    ${PROJ_PATH}/../../lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_gpio.c\n    ${PROJ_PATH}/../../lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_pwr.c\n    ${PROJ_PATH}/../../lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c\n    ${PROJ_PATH}/../../lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c\n    ${PROJ_PATH}/../../lib/st/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c)\n\nset(src_user_SRCS \n    ${PROJ_PATH}/src/main.c\n    ${PROJ_PATH}/src/stm32f4xx_it.c\n    ${PROJ_PATH}/src/syscalls.c\n    ${PROJ_PATH}/src/system_stm32f4xx.c)\n\nset(src_lwesp_SRCS \n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_ap.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_buff.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_conn.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_debug.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_dns.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_evt.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_input.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_int.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_mem.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_parser.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_pbuf.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_server.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_sntp.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_sta.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_threads.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_timeout.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_unicode.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_utils.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_wps.c)\n\nset(src_lwesp_api_SRCS \n    ${PROJ_PATH}/../../../lwesp/src/api/lwesp_netconn.c)\n\nset(src_lwesp_apps_SRCS \n    ${PROJ_PATH}/../../../lwesp/src/apps/mqtt/lwesp_mqtt_client.c\n    ${PROJ_PATH}/../../../lwesp/src/apps/mqtt/lwesp_mqtt_client_api.c\n    ${PROJ_PATH}/../../../lwesp/src/apps/mqtt/lwesp_mqtt_client_evt.c)\n\nset(src_lwesp_ll_SRCS \n    ${PROJ_PATH}/../../../lwesp/src/system/lwesp_ll_stm32f429zi_nucleo.c\n    ${PROJ_PATH}/../../../lwesp/src/system/lwesp_sys_cmsis_os.c)\n\nset(src_lwesp_snippets_SRCS \n    ${PROJ_PATH}/../../../snippets/examples_common_lwesp_callback_func.c\n    ${PROJ_PATH}/../../../snippets/mqtt_client_api_cayenne.c\n    ${PROJ_PATH}/../../../snippets/station_manager.c\n    ${PROJ_PATH}/../../../snippets/utils.c)\n\nset(src_startup_SRCS \n    ${PROJ_PATH}/STM32CubeIDE/startup/startup_stm32f429xx.s)\n\n#\n# Include directories\n#\nset(include_c_DIRS\n    ${PROJ_PATH}/inc\n    ${PROJ_PATH}/../../../snippets/include\n    ${PROJ_PATH}/../../../lwesp/src/include\n    ${PROJ_PATH}/../../../lwesp/src/include/system/port/cmsis_os\n    ${PROJ_PATH}/../../lib/st/CMSIS/Include\n    ${PROJ_PATH}/../../lib/st/STM32F4xx_HAL_Driver/Inc\n    ${PROJ_PATH}/../../lib/st/CMSIS/Device/ST/STM32F4xx/Include\n    ${PROJ_PATH}/../../lib/FreeRTOS/include\n    ${PROJ_PATH}/../../lib/FreeRTOS/CMSIS_RTOS_V2\n    ${PROJ_PATH}/../../lib/FreeRTOS/portable/GCC/ARM_CM4F\n)\nset(include_cxx_DIRS\n    \n)\nset(include_asm_DIRS\n    \n)\n\n#\n# Symbols definition\n#\nset(symbols_c_SYMB\n    \"__weak=__attribute__((weak))\"\n    \"HSE_VALUE=8000000\"\n    \"__packed=__attribute__((__packed__))\"\n    \"STM32F429xx\"\n    \"USE_FULL_LL_DRIVER\"\n)\nset(symbols_cxx_SYMB\n    \"STM32F10X_MD\"\n    \"USE_STDPERIPH_DRIVER\"\n)\nset(symbols_asm_SYMB\n    \n)\n\n#\n# Link directories setup\n# Must be before executable is added\n#\nset(link_DIRS\n    \n)\nlink_directories(${EXECUTABLE} ${link_DIRS})\n\n#\n# Executable files\n#\nadd_executable(${EXECUTABLE} \n    ${src_freertos_SRCS}\n    ${src_stm32f4xx_hal_driver_SRCS}\n    ${src_user_SRCS}\n    ${src_lwesp_SRCS}\n    ${src_lwesp_api_SRCS}\n    ${src_lwesp_apps_SRCS}\n    ${src_lwesp_ll_SRCS}\n    ${src_lwesp_snippets_SRCS}\n    ${src_startup_SRCS})\n\n#\n# Add linked libraries for linker\n#\nset(link_LIBS\n    \n)\ntarget_link_libraries(${EXECUTABLE} ${link_LIBS})\n\n#\n# Project symbols\n#\ntarget_compile_definitions(${EXECUTABLE} PRIVATE\n    # Language specific only\n    $<$<COMPILE_LANGUAGE:C>: ${symbols_c_SYMB}>\n    $<$<COMPILE_LANGUAGE:CXX>: ${symbols_cxx_SYMB}>\n    $<$<COMPILE_LANGUAGE:ASM>: ${symbols_asm_SYMB}>\n\n    # Configuration specific\n    $<$<CONFIG:Debug>:\n        DEBUG\n    >\n    $<$<CONFIG:Release>: >\n)\n\n#\n# Add include paths for each of the compiler\n#\ntarget_include_directories(${EXECUTABLE} PRIVATE\n    # Language specific only\n    $<$<COMPILE_LANGUAGE:C>: ${include_c_DIRS}>\n    $<$<COMPILE_LANGUAGE:CXX>: ${include_cxx_DIRS}>\n    $<$<COMPILE_LANGUAGE:ASM>: ${include_asm_DIRS}>\n\n    # Configuration specific\n    $<$<CONFIG:Debug>: >\n    $<$<CONFIG:Release>: >\n)\n\n# Compiler and linker options\ntarget_compile_options(${EXECUTABLE} PRIVATE\n    ${CPU_PARAMETERS}\n    -Wall\n    -Wextra\n    -Wpedantic\n    -Wno-unused-parameter\n    $<$<COMPILE_LANGUAGE:C>:\n\n    >\n    $<$<COMPILE_LANGUAGE:CXX>:\n        #-Wno-volatile\n        #-Wold-style-cast\n        #-Wuseless-cast\n        #-Wsuggest-override\n    >\n    $<$<COMPILE_LANGUAGE:ASM>:\n        -x assembler-with-cpp\n        -MMD\n        -MP\n    >\n    $<$<CONFIG:Debug>:\n        -Og -g3 -ggdb\n    >\n    $<$<CONFIG:Release>:\n        -Og -g0\n    >\n)\n\n# Setup linker parameters\ntarget_link_options(${EXECUTABLE} PRIVATE\n    -T${linker_script_SRC}\n    ${CPU_PARAMETERS}\n    -Wl,-Map=${CMAKE_PROJECT_NAME}.map\n    -u _printf_float              # STDIO float formatting support (remove if not used)\n    --specs=nosys.specs\n    -Wl,--start-group\n    -lc\n    -lm\n    -lstdc++\n    -lsupc++\n    -Wl,--end-group\n    -Wl,--print-memory-usage\n)\n\n# Execute post-build to print size\nadd_custom_command(TARGET ${EXECUTABLE} POST_BUILD\n    COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${EXECUTABLE}>\n)\n\n# Convert output to hex and binary\nadd_custom_command(TARGET ${EXECUTABLE} POST_BUILD\n    COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${EXECUTABLE}> ${EXECUTABLE}.hex\n)\n\n# Convert to bin file -> add conditional check?\nadd_custom_command(TARGET ${EXECUTABLE} POST_BUILD\n    COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:${EXECUTABLE}> ${EXECUTABLE}.bin\n)\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/CMakePresets.json",
    "content": "{\n    \"version\": 3,\n    \"configurePresets\": [\n        {\n            \"name\": \"default\",\n            \"hidden\": true,\n            \"generator\": \"Ninja\",\n            \"binaryDir\": \"${sourceDir}/build/${presetName}\",\n            \"toolchainFile\": \"${sourceDir}/cmake/gcc-arm-none-eabi.cmake\",\n            \"cacheVariables\": {\n                \"CMAKE_EXPORT_COMPILE_COMMANDS\": \"ON\"\n            }\n        },\n        {\n            \"name\": \"Debug\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"CMAKE_BUILD_TYPE\": \"Debug\"\n            }\n        },\n        {\n            \"name\": \"RelWithDebInfo\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"CMAKE_BUILD_TYPE\": \"RelWithDebInfo\"\n            }\n        },\n        {\n            \"name\": \"Release\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"CMAKE_BUILD_TYPE\": \"Release\"\n            }\n        },\n        {\n            \"name\": \"MinSizeRel\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"CMAKE_BUILD_TYPE\": \"MinSizeRel\"\n            }\n        }\n    ]\n}"
  },
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    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/STM32CubeIDE/Debug_STM32F429ZI_FLASH.ld",
    "content": "/*\n******************************************************************************\nFile:     Debug_STM32F429ZI_FLASH.ld\nInfo:     Generated by Atollic TrueSTUDIO(R) 9.2.0   2019-02-21\n\nAbstract: Linker script for STM32F429ZI device\n          Set heap size, stack size, stack location, memory areas and \n          sections according to application requirements. \n\nThe MIT License (MIT)\nCopyright (c) 2018 STMicroelectronics\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n\n******************************************************************************\n*/\n\n/* Entry Point */\nENTRY(Reset_Handler)\n\n/* Highest address of the user mode stack */\n_estack = 0x20030000;    /* end of 192K RAM */\n\n/* Generate a link error if heap and stack don't fit into RAM */\n_Min_Heap_Size = 0;      /* required amount of heap  */\n_Min_Stack_Size = 0x400; /* required amount of stack */\n\n/* Specify the memory areas */\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 2048K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 192K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n  CCMRAM (rw)     : ORIGIN = 0x10000000, LENGTH = 64K\n}\n\n/* Define output sections */\nSECTIONS\n{\n  /* The startup code goes first into FLASH */\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) /* Startup code */\n    . = ALIGN(4);\n  } >FLASH\n\n  /* The program code and other data goes into FLASH */\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           /* .text sections (code) */\n    *(.text*)          /* .text* sections (code) */\n    *(.glue_7)         /* glue arm to thumb code */\n    *(.glue_7t)        /* glue thumb to arm code */\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        /* define a global symbols at end of code */\n  } >FLASH\n\n  /* Constant data goes into FLASH */\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  /* used by the startup to initialize data */\n  _sidata = LOADADDR(.data);\n\n  /* Initialized data sections goes into RAM, load LMA copy after code */\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        /* create a global symbol at data start */\n    *(.data)           /* .data sections */\n    *(.data*)          /* .data* sections */\n\n    . = ALIGN(4);\n    _edata = .;        /* define a global symbol at data end */\n  } >RAM AT> FLASH\n  \n  _siccmram = LOADADDR(.ccmram);\n\n  /* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section, \n  * the startup code needs to be modified to copy the init-values.  \n  */\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       /* create a global symbol at ccmram start */\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       /* create a global symbol at ccmram end */\n  } >CCMRAM AT> FLASH\n\n  /* Uninitialized data section */\n  . = ALIGN(4);\n  .bss :\n  {\n    /* This is used by the startup in order to initialize the .bss secion */\n    _sbss = .;         /* define a global symbol at bss start */\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         /* define a global symbol at bss end */\n    __bss_end__ = _ebss;\n  } >RAM\n\n  /* User_heap_stack section, used to check that there is enough RAM left */\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  /* MEMORY_bank1 section, code must be located here explicitly            */\n  /* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); */\n  .memory_b1_text :\n  {\n    *(.mb1text)        /* .mb1text sections (code) */\n    *(.mb1text*)       /* .mb1text* sections (code)  */\n    *(.mb1rodata)      /* read-only data (constants) */\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  /* Remove information from the standard libraries */\n  /DISCARD/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/STM32CubeIDE/startup/startup_stm32f429xx.s",
    "content": "/**\n  ******************************************************************************\n  * @file      startup_stm32f429xx.s\n  * @author    MCD Application Team\n  * @version   V2.6.1\n  * @date      14-February-2017 \n  * @brief     STM32F429xx Devices vector table for GCC based toolchains. \n  *            This module performs:\n  *                - Set the initial SP\n  *                - Set the initial PC == Reset_Handler,\n  *                - Set the vector table entries with the exceptions ISR address\n  *                - Branches to main in the C library (which eventually\n  *                  calls main()).\n  *            After Reset the Cortex-M4 processor is in Thread mode,\n  *            priority is Privileged, and the Stack is set to Main.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n    \n  .syntax unified\n  .cpu cortex-m4\n  .fpu softvfp\n  .thumb\n\n.global  g_pfnVectors\n.global  Default_Handler\n\n/* start address for the initialization values of the .data section. \ndefined in linker script */\n.word  _sidata\n/* start address for the .data section. defined in linker script */  \n.word  _sdata\n/* end address for the .data section. defined in linker script */\n.word  _edata\n/* start address for the .bss section. defined in linker script */\n.word  _sbss\n/* end address for the .bss section. defined in linker script */\n.word  _ebss\n/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\n\n/**\n * @brief  This is the code that gets called when the processor first\n *          starts execution following a reset event. Only the absolutely\n *          necessary set is performed, after which the application\n *          supplied main() routine is called. \n * @param  None\n * @retval : None\n*/\n\n    .section  .text.Reset_Handler\n  .weak  Reset_Handler\n  .type  Reset_Handler, %function\nReset_Handler: \n  ldr   sp, =_estack       /* set stack pointer */\n \n/* Copy the data segment initializers from flash to SRAM */  \n  movs  r1, #0\n  b  LoopCopyDataInit\n\nCopyDataInit:\n  ldr  r3, =_sidata\n  ldr  r3, [r3, r1]\n  str  r3, [r0, r1]\n  adds  r1, r1, #4\n    \nLoopCopyDataInit:\n  ldr  r0, =_sdata\n  ldr  r3, =_edata\n  adds  r2, r0, r1\n  cmp  r2, r3\n  bcc  CopyDataInit\n  ldr  r2, =_sbss\n  b  LoopFillZerobss\n/* Zero fill the bss segment. */  \nFillZerobss:\n  movs  r3, #0\n  str  r3, [r2], #4\n    \nLoopFillZerobss:\n  ldr  r3, = _ebss\n  cmp  r2, r3\n  bcc  FillZerobss\n\n/* Call the clock system intitialization function.*/\n  bl  SystemInit   \n/* Call static constructors */\n    bl __libc_init_array\n/* Call the application's entry point.*/\n  bl  main\n  bx  lr    \n.size  Reset_Handler, .-Reset_Handler\n\n/**\n * @brief  This is the code that gets called when the processor receives an \n *         unexpected interrupt.  This simply enters an infinite loop, preserving\n *         the system state for examination by a debugger.\n * @param  None     \n * @retval None       \n*/\n    .section  .text.Default_Handler,\"ax\",%progbits\nDefault_Handler:\nInfinite_Loop:\n  b  Infinite_Loop\n  .size  Default_Handler, .-Default_Handler\n/******************************************************************************\n*\n* The minimal vector table for a Cortex M3. Note that the proper constructs\n* must be placed on this to ensure that it ends up at physical address\n* 0x0000.0000.\n* \n*******************************************************************************/\n   .section  .isr_vector,\"a\",%progbits\n  .type  g_pfnVectors, %object\n  .size  g_pfnVectors, .-g_pfnVectors\n   \ng_pfnVectors:\n  .word  _estack\n  .word  Reset_Handler\n\n  .word  NMI_Handler\n  .word  HardFault_Handler\n  .word  MemManage_Handler\n  .word  BusFault_Handler\n  .word  UsageFault_Handler\n  .word  0\n  .word  0\n  .word  0\n  .word  0\n  .word  SVC_Handler\n  .word  DebugMon_Handler\n  .word  0\n  .word  PendSV_Handler\n  .word  SysTick_Handler\n  \n  /* External Interrupts */\n  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        \n  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        \n  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            \n  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      \n  .word     FLASH_IRQHandler                  /* FLASH                        */                                          \n  .word     RCC_IRQHandler                    /* RCC                          */                                            \n  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        \n  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          \n  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          \n  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          \n  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          \n  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  \n  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   \n  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   \n  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   \n  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   \n  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   \n  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   \n  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   \n  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         \n  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          \n  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          \n  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          \n  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          \n  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         \n  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         \n  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */\n  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          \n  .word     TIM2_IRQHandler                   /* TIM2                         */                   \n  .word     TIM3_IRQHandler                   /* TIM3                         */                   \n  .word     TIM4_IRQHandler                   /* TIM4                         */                   \n  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          \n  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          \n  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          \n  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            \n  .word     SPI1_IRQHandler                   /* SPI1                         */                   \n  .word     SPI2_IRQHandler                   /* SPI2                         */                   \n  .word     USART1_IRQHandler                 /* USART1                       */                   \n  .word     USART2_IRQHandler                 /* USART2                       */                   \n  .word     USART3_IRQHandler                 /* USART3                       */                   \n  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          \n  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 \n  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       \n  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         \n  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         \n  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */\n  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          \n  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          \n  .word     FMC_IRQHandler                    /* FMC                         */                   \n  .word     SDIO_IRQHandler                   /* SDIO                         */                   \n  .word     TIM5_IRQHandler                   /* TIM5                         */                   \n  .word     SPI3_IRQHandler                   /* SPI3                         */                   \n  .word     UART4_IRQHandler                  /* UART4                        */                   \n  .word     UART5_IRQHandler                  /* UART5                        */                   \n  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   \n  .word     TIM7_IRQHandler                   /* TIM7                         */\n  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   \n  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   \n  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   \n  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   \n  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   \n  .word     ETH_IRQHandler                    /* Ethernet                     */                   \n  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     \n  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          \n  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          \n  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          \n  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          \n  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   \n  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   \n  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   \n  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   \n  .word     USART6_IRQHandler                 /* USART6                       */                    \n  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          \n  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          \n  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   \n  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   \n  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         \n  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   \n  .word     DCMI_IRQHandler                   /* DCMI                         */                   \n  .word     0                                 /* Reserved                     */                   \n  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */\n  .word     FPU_IRQHandler                    /* FPU                          */\n  .word     UART7_IRQHandler                  /* UART7                        */      \n  .word     UART8_IRQHandler                  /* UART8                        */\n  .word     SPI4_IRQHandler                   /* SPI4                         */\n  .word     SPI5_IRQHandler                   /* SPI5 \t\t\t\t\t\t  */\n  .word     SPI6_IRQHandler                   /* SPI6\t\t\t\t\t\t  */\n  .word     SAI1_IRQHandler                   /* SAI1\t\t\t\t\t\t  */\n  .word     LTDC_IRQHandler                   /* LTDC_IRQHandler\t\t\t  */\n  .word     LTDC_ER_IRQHandler                /* LTDC_ER_IRQHandler\t\t\t  */\n  .word     DMA2D_IRQHandler                  /* DMA2D                        */\n  \n/*******************************************************************************\n*\n* Provide weak aliases for each Exception handler to the Default_Handler. \n* As they are weak aliases, any function with the same name will override \n* this definition.\n* \n*******************************************************************************/\n   .weak      NMI_Handler\n   .thumb_set NMI_Handler,Default_Handler\n  \n   .weak      HardFault_Handler\n   .thumb_set HardFault_Handler,Default_Handler\n  \n   .weak      MemManage_Handler\n   .thumb_set MemManage_Handler,Default_Handler\n  \n   .weak      BusFault_Handler\n   .thumb_set BusFault_Handler,Default_Handler\n\n   .weak      UsageFault_Handler\n   .thumb_set UsageFault_Handler,Default_Handler\n\n   .weak      SVC_Handler\n   .thumb_set SVC_Handler,Default_Handler\n\n   .weak      DebugMon_Handler\n   .thumb_set DebugMon_Handler,Default_Handler\n\n   .weak      PendSV_Handler\n   .thumb_set PendSV_Handler,Default_Handler\n\n   .weak      SysTick_Handler\n   .thumb_set SysTick_Handler,Default_Handler              \n  \n   .weak      WWDG_IRQHandler                   \n   .thumb_set WWDG_IRQHandler,Default_Handler      \n                  \n   .weak      PVD_IRQHandler      \n   .thumb_set PVD_IRQHandler,Default_Handler\n               \n   .weak      TAMP_STAMP_IRQHandler            \n   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\n            \n   .weak      RTC_WKUP_IRQHandler                  \n   .thumb_set RTC_WKUP_IRQHandler,Default_Handler\n            \n   .weak      FLASH_IRQHandler         \n   .thumb_set FLASH_IRQHandler,Default_Handler\n                  \n   .weak      RCC_IRQHandler      \n   .thumb_set RCC_IRQHandler,Default_Handler\n                  \n   .weak      EXTI0_IRQHandler         \n   .thumb_set EXTI0_IRQHandler,Default_Handler\n                  \n   .weak      EXTI1_IRQHandler         \n   .thumb_set EXTI1_IRQHandler,Default_Handler\n                     \n   .weak      EXTI2_IRQHandler         \n   .thumb_set EXTI2_IRQHandler,Default_Handler \n                 \n   .weak      EXTI3_IRQHandler         \n   .thumb_set EXTI3_IRQHandler,Default_Handler\n                        \n   .weak      EXTI4_IRQHandler         \n   .thumb_set EXTI4_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream0_IRQHandler               \n   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\n         \n   .weak      DMA1_Stream1_IRQHandler               \n   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream2_IRQHandler               \n   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream3_IRQHandler               \n   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler \n                 \n   .weak      DMA1_Stream4_IRQHandler              \n   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream5_IRQHandler               \n   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream6_IRQHandler               \n   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\n                  \n   .weak      ADC_IRQHandler      \n   .thumb_set ADC_IRQHandler,Default_Handler\n               \n   .weak      CAN1_TX_IRQHandler   \n   .thumb_set CAN1_TX_IRQHandler,Default_Handler\n            \n   .weak      CAN1_RX0_IRQHandler                  \n   .thumb_set CAN1_RX0_IRQHandler,Default_Handler\n                           \n   .weak      CAN1_RX1_IRQHandler                  \n   .thumb_set CAN1_RX1_IRQHandler,Default_Handler\n            \n   .weak      CAN1_SCE_IRQHandler                  \n   .thumb_set CAN1_SCE_IRQHandler,Default_Handler\n            \n   .weak      EXTI9_5_IRQHandler   \n   .thumb_set EXTI9_5_IRQHandler,Default_Handler\n            \n   .weak      TIM1_BRK_TIM9_IRQHandler            \n   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\n            \n   .weak      TIM1_UP_TIM10_IRQHandler            \n   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\n\n   .weak      TIM1_TRG_COM_TIM11_IRQHandler      \n   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\n      \n   .weak      TIM1_CC_IRQHandler   \n   .thumb_set TIM1_CC_IRQHandler,Default_Handler\n                  \n   .weak      TIM2_IRQHandler            \n   .thumb_set TIM2_IRQHandler,Default_Handler\n                  \n   .weak      TIM3_IRQHandler            \n   .thumb_set TIM3_IRQHandler,Default_Handler\n                  \n   .weak      TIM4_IRQHandler            \n   .thumb_set TIM4_IRQHandler,Default_Handler\n                  \n   .weak      I2C1_EV_IRQHandler   \n   .thumb_set I2C1_EV_IRQHandler,Default_Handler\n                     \n   .weak      I2C1_ER_IRQHandler   \n   .thumb_set I2C1_ER_IRQHandler,Default_Handler\n                     \n   .weak      I2C2_EV_IRQHandler   \n   .thumb_set I2C2_EV_IRQHandler,Default_Handler\n                  \n   .weak      I2C2_ER_IRQHandler   \n   .thumb_set I2C2_ER_IRQHandler,Default_Handler\n                           \n   .weak      SPI1_IRQHandler            \n   .thumb_set SPI1_IRQHandler,Default_Handler\n                        \n   .weak      SPI2_IRQHandler            \n   .thumb_set SPI2_IRQHandler,Default_Handler\n                  \n   .weak      USART1_IRQHandler      \n   .thumb_set USART1_IRQHandler,Default_Handler\n                     \n   .weak      USART2_IRQHandler      \n   .thumb_set USART2_IRQHandler,Default_Handler\n                     \n   .weak      USART3_IRQHandler      \n   .thumb_set USART3_IRQHandler,Default_Handler\n                  \n   .weak      EXTI15_10_IRQHandler               \n   .thumb_set EXTI15_10_IRQHandler,Default_Handler\n               \n   .weak      RTC_Alarm_IRQHandler               \n   .thumb_set RTC_Alarm_IRQHandler,Default_Handler\n            \n   .weak      OTG_FS_WKUP_IRQHandler         \n   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\n            \n   .weak      TIM8_BRK_TIM12_IRQHandler         \n   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\n         \n   .weak      TIM8_UP_TIM13_IRQHandler            \n   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\n         \n   .weak      TIM8_TRG_COM_TIM14_IRQHandler      \n   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\n      \n   .weak      TIM8_CC_IRQHandler   \n   .thumb_set TIM8_CC_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream7_IRQHandler               \n   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\n                     \n   .weak      FMC_IRQHandler            \n   .thumb_set FMC_IRQHandler,Default_Handler\n                     \n   .weak      SDIO_IRQHandler            \n   .thumb_set SDIO_IRQHandler,Default_Handler\n                     \n   .weak      TIM5_IRQHandler            \n   .thumb_set TIM5_IRQHandler,Default_Handler\n                     \n   .weak      SPI3_IRQHandler            \n   .thumb_set SPI3_IRQHandler,Default_Handler\n                     \n   .weak      UART4_IRQHandler         \n   .thumb_set UART4_IRQHandler,Default_Handler\n                  \n   .weak      UART5_IRQHandler         \n   .thumb_set UART5_IRQHandler,Default_Handler\n                  \n   .weak      TIM6_DAC_IRQHandler                  \n   .thumb_set TIM6_DAC_IRQHandler,Default_Handler\n               \n   .weak      TIM7_IRQHandler            \n   .thumb_set TIM7_IRQHandler,Default_Handler\n         \n   .weak      DMA2_Stream0_IRQHandler               \n   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\n               \n   .weak      DMA2_Stream1_IRQHandler               \n   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\n                  \n   .weak      DMA2_Stream2_IRQHandler               \n   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\n            \n   .weak      DMA2_Stream3_IRQHandler               \n   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\n            \n   .weak      DMA2_Stream4_IRQHandler               \n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\n   \n   .weak      ETH_IRQHandler               \n   .thumb_set ETH_IRQHandler,Default_Handler\n\n   .weak      ETH_WKUP_IRQHandler               \n   .thumb_set ETH_WKUP_IRQHandler,Default_Handler\n\n   .weak      CAN2_TX_IRQHandler   \n   .thumb_set CAN2_TX_IRQHandler,Default_Handler\n                           \n   .weak      CAN2_RX0_IRQHandler                  \n   .thumb_set CAN2_RX0_IRQHandler,Default_Handler\n                           \n   .weak      CAN2_RX1_IRQHandler                  \n   .thumb_set CAN2_RX1_IRQHandler,Default_Handler\n                           \n   .weak      CAN2_SCE_IRQHandler                  \n   .thumb_set CAN2_SCE_IRQHandler,Default_Handler\n                           \n   .weak      OTG_FS_IRQHandler      \n   .thumb_set OTG_FS_IRQHandler,Default_Handler\n                     \n   .weak      DMA2_Stream5_IRQHandler               \n   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\n                  \n   .weak      DMA2_Stream6_IRQHandler               \n   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\n                  \n   .weak      DMA2_Stream7_IRQHandler               \n   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\n                  \n   .weak      USART6_IRQHandler      \n   .thumb_set USART6_IRQHandler,Default_Handler\n                        \n   .weak      I2C3_EV_IRQHandler   \n   .thumb_set I2C3_EV_IRQHandler,Default_Handler\n                        \n   .weak      I2C3_ER_IRQHandler   \n   .thumb_set I2C3_ER_IRQHandler,Default_Handler\n                        \n   .weak      OTG_HS_EP1_OUT_IRQHandler         \n   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\n               \n   .weak      OTG_HS_EP1_IN_IRQHandler            \n   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\n               \n   .weak      OTG_HS_WKUP_IRQHandler         \n   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\n            \n   .weak      OTG_HS_IRQHandler      \n   .thumb_set OTG_HS_IRQHandler,Default_Handler\n                  \n   .weak      DCMI_IRQHandler            \n   .thumb_set DCMI_IRQHandler,Default_Handler\n                                   \n   .weak      HASH_RNG_IRQHandler                  \n   .thumb_set HASH_RNG_IRQHandler,Default_Handler   \n\n   .weak      FPU_IRQHandler                  \n   .thumb_set FPU_IRQHandler,Default_Handler  \n\n   .weak      UART7_IRQHandler            \n   .thumb_set UART7_IRQHandler,Default_Handler\n\n   .weak      UART8_IRQHandler            \n   .thumb_set UART8_IRQHandler,Default_Handler\n\n   .weak      SPI4_IRQHandler            \n   .thumb_set SPI4_IRQHandler,Default_Handler\n\n   .weak      SPI5_IRQHandler            \n   .thumb_set SPI5_IRQHandler,Default_Handler\n\n   .weak      SPI6_IRQHandler            \n   .thumb_set SPI6_IRQHandler,Default_Handler\n\n   .weak      SAI1_IRQHandler            \n   .thumb_set SAI1_IRQHandler,Default_Handler\n\n   .weak      LTDC_IRQHandler            \n   .thumb_set LTDC_IRQHandler,Default_Handler\n\n   .weak      LTDC_ER_IRQHandler            \n   .thumb_set LTDC_ER_IRQHandler,Default_Handler\n\n   .weak      DMA2D_IRQHandler            \n   .thumb_set DMA2D_IRQHandler,Default_Handler\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\t\t\n \n   \n   \n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/cmake/gcc-arm-none-eabi.cmake",
    "content": "set(CMAKE_SYSTEM_NAME               Generic)\nset(CMAKE_SYSTEM_PROCESSOR          arm)\n\n# Some default GCC settings\n# arm-none-eabi- must be part of path environment\nset(TOOLCHAIN_PREFIX                arm-none-eabi-)\nset(FLAGS                           \"-fdata-sections -ffunction-sections -Wl,--gc-sections\")\nset(CPP_FLAGS                       \"${FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics\")\n\nset(CMAKE_C_FLAGS                   ${FLAGS})\nset(CMAKE_CXX_FLAGS                 ${CPP_FLAGS})\n\nset(CMAKE_C_COMPILER                ${TOOLCHAIN_PREFIX}gcc)\nset(CMAKE_ASM_COMPILER              ${CMAKE_C_COMPILER})\nset(CMAKE_CXX_COMPILER              ${TOOLCHAIN_PREFIX}g++)\nset(CMAKE_OBJCOPY                   ${TOOLCHAIN_PREFIX}objcopy)\nset(CMAKE_SIZE                      ${TOOLCHAIN_PREFIX}size)\n\nset(CMAKE_EXECUTABLE_SUFFIX_ASM     \".elf\")\nset(CMAKE_EXECUTABLE_SUFFIX_C       \".elf\")\nset(CMAKE_EXECUTABLE_SUFFIX_CXX     \".elf\")\n\nset(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/inc/FreeRTOSConfig.h",
    "content": "/*\n    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\n    All rights reserved\n\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\n\n    This file is part of the FreeRTOS distribution.\n\n    FreeRTOS is free software; you can redistribute it and/or modify it under\n    the terms of the GNU General Public License (version 2) as published by the\n    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\n\n    ***************************************************************************\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\n    >>!   obliged to provide the source code for proprietary components     !<<\n    >>!   outside of the FreeRTOS kernel.                                   !<<\n    ***************************************************************************\n\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\n    link: http://www.freertos.org/a00114.html\n\n    ***************************************************************************\n     *                                                                       *\n     *    FreeRTOS provides completely free yet professionally developed,    *\n     *    robust, strictly quality controlled, supported, and cross          *\n     *    platform software that is more than just the market leader, it     *\n     *    is the industry's de facto standard.                               *\n     *                                                                       *\n     *    Help yourself get started quickly while simultaneously helping     *\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\n     *    tutorial book, reference manual, or both:                          *\n     *    http://www.FreeRTOS.org/Documentation                              *\n     *                                                                       *\n    ***************************************************************************\n\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\n    defined configASSERT()?\n\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\n    embedded software for free we request you assist our global community by\n    participating in the support forum.\n\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\n    be as productive as possible as early as possible.  Now you can receive\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\n    Ltd, and the world's leading authority on the world's leading RTOS.\n\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\n\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\n\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\n    licenses offer ticketed support, indemnification and commercial middleware.\n\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\n    engineered and independently SIL3 certified version for use in safety and\n    mission critical applications that require provable dependability.\n\n    1 tab == 4 spaces!\n*/\n\n\n#ifndef FREERTOS_CONFIG_H\n#define FREERTOS_CONFIG_H\n\n/*-----------------------------------------------------------\n * Application specific definitions.\n *\n * These definitions should be adjusted for your particular hardware and\n * application requirements.\n *\n * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\n * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\n *\n * See http://www.freertos.org/a00110.html.\n *----------------------------------------------------------*/\n\n/* Ensure stdint is only used by the compiler, and not the assembler. */\n#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)\n #include <stdint.h>\n extern uint32_t SystemCoreClock;\n#endif\n\n#define configUSE_PREEMPTION                1\n#define configUSE_IDLE_HOOK                 0\n#define configUSE_TICK_HOOK                 0\n#define configCPU_CLOCK_HZ                  (SystemCoreClock)\n#define configTICK_RATE_HZ                  ((TickType_t)1000)\n#define configMAX_PRIORITIES                (7)\n#define configMINIMAL_STACK_SIZE            ((uint16_t)128)\n#define configTOTAL_HEAP_SIZE               ((size_t)(15 * 1024))\n#define configMAX_TASK_NAME_LEN             (16)\n#define configUSE_TRACE_FACILITY            1\n#define configUSE_16_BIT_TICKS              0\n#define configIDLE_SHOULD_YIELD             1\n#define configUSE_MUTEXES                   1\n#define configQUEUE_REGISTRY_SIZE           8\n#define configCHECK_FOR_STACK_OVERFLOW      0\n#define configUSE_RECURSIVE_MUTEXES         1\n#define configUSE_MALLOC_FAILED_HOOK        0\n#define configUSE_APPLICATION_TASK_TAG      0\n#define configUSE_COUNTING_SEMAPHORES       1\n#define configGENERATE_RUN_TIME_STATS       0\n#define configSUPPORT_STATIC_ALLOCATION     1\n\n/* Co-routine definitions. */\n#define configUSE_CO_ROUTINES               0\n#define configMAX_CO_ROUTINE_PRIORITIES     2\n\n/* Software timer definitions. */\n#define configUSE_TIMERS                    0\n#define configTIMER_TASK_PRIORITY           2\n#define configTIMER_QUEUE_LENGTH            10\n#define configTIMER_TASK_STACK_DEPTH        (configMINIMAL_STACK_SIZE * 2)\n\n/* Set the following definitions to 1 to include the API function, or zero\nto exclude the API function. */\n#define INCLUDE_vTaskPrioritySet            1\n#define INCLUDE_uxTaskPriorityGet           1\n#define INCLUDE_vTaskDelete                 1\n#define INCLUDE_vTaskCleanUpResources       0\n#define INCLUDE_vTaskSuspend                1\n#define INCLUDE_vTaskDelayUntil             0\n#define INCLUDE_vTaskDelay                  1\n#define INCLUDE_xTaskGetSchedulerState      1\n\n/* Cortex-M specific definitions. */\n#ifdef __NVIC_PRIO_BITS\n /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\n #define configPRIO_BITS                    __NVIC_PRIO_BITS\n#else\n #define configPRIO_BITS                    4        /* 15 priority levels */\n#endif\n\n/* The lowest interrupt priority that can be used in a call to a \"set priority\"\nfunction. */\n#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY             0x0F\n\n/* The highest interrupt priority that can be used by any interrupt service\nroutine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL\nINTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\nPRIORITY THAN THIS! (higher priorities are lower numeric values. */\n#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY        0x05\n\n/* Interrupt priorities used by the kernel port layer itself.  These are generic\nto all Cortex-M ports, and do not rely on any particular library functions. */\n#define configKERNEL_INTERRUPT_PRIORITY                     ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\n/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\nSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\n#define configMAX_SYSCALL_INTERRUPT_PRIORITY                ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\n \n/* Normal assert() semantics without relying on the provision of an assert.h\nheader file. */\n#define configASSERT( x )                                   if ((x) == 0) { taskDISABLE_INTERRUPTS(); for (;;) {} }\n \n/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\n   standard names. */\n#define vPortSVCHandler                                     SVC_Handler\n#define xPortPendSVHandler                                  PendSV_Handler\n\n/* IMPORTANT: This define MUST be commented when used with STM32Cube firmware, \n              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */\n/* #define xPortSysTickHandler SysTick_Handler */\n\n#endif /* FREERTOS_CONFIG_H */\n\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/inc/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#define LWESP_CFG_NETCONN                     1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/inc/main.h",
    "content": "/**\n * \\file            main.h\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef __MAIN_H\n#define __MAIN_H\n\n#include \"stm32f4xx.h\"\n#include \"stm32f4xx_ll_rcc.h\"\n#include \"stm32f4xx_ll_bus.h\"\n#include \"stm32f4xx_ll_system.h\"\n#include \"stm32f4xx_ll_exti.h\"\n#include \"stm32f4xx_ll_cortex.h\"\n#include \"stm32f4xx_ll_utils.h\"\n#include \"stm32f4xx_ll_pwr.h\"\n#include \"stm32f4xx_ll_dma.h\"\n#include \"stm32f4xx_ll_usart.h\"\n#include \"stm32f4xx_ll_gpio.h\"\n#include <stdio.h>\n\n#ifndef NVIC_PRIORITYGROUP_0\n#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,\n                                                                 4 bits for subpriority */\n#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,\n                                                                 3 bits for subpriority */\n#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,\n                                                                 2 bits for subpriority */\n#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,\n                                                                 1 bit  for subpriority */\n#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,\n                                                                 0 bit  for subpriority */\n#endif\n\n/* ########################## Assert Selection ############################## */\n/**\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the\n  *        HAL drivers code\n  */\n/* #define USE_FULL_ASSERT    1U */\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\nvoid _Error_Handler(char *, int);\n\n#define Error_Handler() _Error_Handler(__FILE__, __LINE__)\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __MAIN_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/inc/stm32_assert.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32_assert.h\n  * @brief   STM32 assert file.\n  ******************************************************************************\n   ** This notice applies to any and all portions of this file\n  * that are not between comment pairs USER CODE BEGIN and\n  * USER CODE END. Other portions of this file, whether \n  * inserted by the user or by software development tools\n  * are owned by their respective copyright owners.\n  *\n  * COPYRIGHT(c) 2018 STMicroelectronics\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32_ASSERT_H\n#define __STM32_ASSERT_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Includes ------------------------------------------------------------------*/\n/* Exported macro ------------------------------------------------------------*/\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  The assert_param macro is used for function's parameters check.\n  * @param  expr: If expr is false, it calls assert_failed function\n  *         which reports the name of the source file and the source\n  *         line number of the call that failed.\n  *         If expr is true, it returns no value.\n  * @retval None\n  */\n  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\n/* Exported functions ------------------------------------------------------- */\n  void assert_failed(uint8_t* file, uint32_t line);\n#else\n  #define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32_ASSERT_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/inc/stm32f4xx_hal_conf.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_conf_template.h\n  * @author  MCD Application Team\n  * @brief   HAL configuration template file. \n  *          This file should be copied to the application folder and renamed\n  *          to stm32f4xx_hal_conf.h.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_CONF_H\n#define __STM32F4xx_HAL_CONF_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/* ########################## Module Selection ############################## */\n/**\n  * @brief This is the list of modules to be used in the HAL driver \n  */\n#define HAL_MODULE_ENABLED  \n#define HAL_ADC_MODULE_ENABLED\n#define HAL_CAN_MODULE_ENABLED\n/* #define HAL_CAN_LEGACY_MODULE_ENABLED */\n#define HAL_CRC_MODULE_ENABLED\n#define HAL_CEC_MODULE_ENABLED\n#define HAL_CRYP_MODULE_ENABLED\n#define HAL_DAC_MODULE_ENABLED\n#define HAL_DCMI_MODULE_ENABLED\n#define HAL_DMA_MODULE_ENABLED\n#define HAL_DMA2D_MODULE_ENABLED\n#define HAL_ETH_MODULE_ENABLED\n#define HAL_FLASH_MODULE_ENABLED\n#define HAL_NAND_MODULE_ENABLED\n#define HAL_NOR_MODULE_ENABLED\n#define HAL_PCCARD_MODULE_ENABLED\n#define HAL_SRAM_MODULE_ENABLED\n#define HAL_SDRAM_MODULE_ENABLED\n#define HAL_HASH_MODULE_ENABLED\n#define HAL_GPIO_MODULE_ENABLED\n#define HAL_I2C_MODULE_ENABLED\n#define HAL_I2S_MODULE_ENABLED\n#define HAL_IWDG_MODULE_ENABLED\n#define HAL_LTDC_MODULE_ENABLED\n#define HAL_DSI_MODULE_ENABLED\n#define HAL_PWR_MODULE_ENABLED\n#define HAL_QSPI_MODULE_ENABLED\n#define HAL_RCC_MODULE_ENABLED\n#define HAL_RNG_MODULE_ENABLED\n#define HAL_RTC_MODULE_ENABLED\n#define HAL_SAI_MODULE_ENABLED\n#define HAL_SD_MODULE_ENABLED\n#define HAL_SPI_MODULE_ENABLED\n#define HAL_TIM_MODULE_ENABLED\n#define HAL_UART_MODULE_ENABLED\n#define HAL_USART_MODULE_ENABLED\n#define HAL_IRDA_MODULE_ENABLED\n#define HAL_SMARTCARD_MODULE_ENABLED\n#define HAL_WWDG_MODULE_ENABLED\n#define HAL_CORTEX_MODULE_ENABLED\n#define HAL_PCD_MODULE_ENABLED\n#define HAL_HCD_MODULE_ENABLED\n#define HAL_FMPI2C_MODULE_ENABLED\n#define HAL_SPDIFRX_MODULE_ENABLED\n#define HAL_DFSDM_MODULE_ENABLED\n#define HAL_LPTIM_MODULE_ENABLED\n#define HAL_MMC_MODULE_ENABLED\n\n/* ########################## HSE/HSI Values adaptation ##################### */\n/**\n  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSE is used as system clock source, directly or through the PLL).  \n  */\n#if !defined  (HSE_VALUE) \n  #define HSE_VALUE              8000000U /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSE_STARTUP_TIMEOUT)\n  #define HSE_STARTUP_TIMEOUT    100U      /*!< Time out for HSE start up, in ms */\n#endif /* HSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief Internal High Speed oscillator (HSI) value.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSI is used as system clock source, directly or through the PLL). \n  */\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE              16000000U /*!< Value of the Internal oscillator in Hz */\n#endif /* HSI_VALUE */\n\n/**\n  * @brief Internal Low Speed oscillator (LSI) value.\n  */\n#if !defined  (LSI_VALUE) \n #define LSI_VALUE               32000U    /*!< LSI Typical Value in Hz */\n#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz\n                                                The real value may vary depending on the variations\n                                                in voltage and temperature. */\n/**\n  * @brief External Low Speed oscillator (LSE) value.\n  */\n#if !defined  (LSE_VALUE)\n #define LSE_VALUE               32768U    /*!< Value of the External Low Speed oscillator in Hz */\n#endif /* LSE_VALUE */\n\n#if !defined  (LSE_STARTUP_TIMEOUT)\n  #define LSE_STARTUP_TIMEOUT    5000U     /*!< Time out for LSE start up, in ms */\n#endif /* LSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief External clock source for I2S peripheral\n  *        This value is used by the I2S HAL module to compute the I2S clock source \n  *        frequency, this source is inserted directly through I2S_CKIN pad. \n  */\n#if !defined  (EXTERNAL_CLOCK_VALUE)\n  #define EXTERNAL_CLOCK_VALUE     12288000U /*!< Value of the External oscillator in Hz*/\n#endif /* EXTERNAL_CLOCK_VALUE */\n\n/* Tip: To avoid modifying this file each time you need to use different HSE,\n   ===  you can define the HSE value in your toolchain compiler preprocessor. */\n\n/* ########################### System Configuration ######################### */\n/**\n  * @brief This is the HAL system configuration section\n  */     \n#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */\n#define  TICK_INT_PRIORITY            0x0FU /*!< tick interrupt priority */\n#define  USE_RTOS                     0U\n#define  PREFETCH_ENABLE              1U\n#define  INSTRUCTION_CACHE_ENABLE     1U\n#define  DATA_CACHE_ENABLE            1U\n\n/* ########################## Assert Selection ############################## */\n/**\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the \n  *        HAL drivers code\n  */\n/* #define USE_FULL_ASSERT    1U */\n\n/* ################## Ethernet peripheral configuration ##################### */\n\n/* Section 1 : Ethernet peripheral configuration */\n\n/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\n#define MAC_ADDR0   2U\n#define MAC_ADDR1   0U\n#define MAC_ADDR2   0U\n#define MAC_ADDR3   0U\n#define MAC_ADDR4   0U\n#define MAC_ADDR5   0U\n\n/* Definition of the Ethernet driver buffers size and count */   \n#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */\n#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */\n#define ETH_RXBUFNB                    4U                  /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */\n#define ETH_TXBUFNB                    4U                  /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */\n\n/* Section 2: PHY configuration section */\n\n/* DP83848 PHY Address*/ \n#define DP83848_PHY_ADDRESS             0x01U\n/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ \n#define PHY_RESET_DELAY                 0x000000FFU\n/* PHY Configuration delay */\n#define PHY_CONFIG_DELAY                0x00000FFFU\n\n#define PHY_READ_TO                     0x0000FFFFU\n#define PHY_WRITE_TO                    0x0000FFFFU\n\n/* Section 3: Common PHY Registers */\n\n#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */\n#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */\n \n#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */\n#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */\n#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */\n#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */\n#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */\n#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */\n#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */\n#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */\n#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */\n#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */\n\n#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */\n#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */\n#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */\n  \n/* Section 4: Extended PHY Registers */\n\n#define PHY_SR                          ((uint16_t)0x0010)  /*!< PHY status register Offset                      */\n#define PHY_MICR                        ((uint16_t)0x0011)  /*!< MII Interrupt Control Register                  */\n#define PHY_MISR                        ((uint16_t)0x0012)  /*!< MII Interrupt Status and Misc. Control Register */\n \n#define PHY_LINK_STATUS                 ((uint16_t)0x0001)  /*!< PHY Link mask                                   */\n#define PHY_SPEED_STATUS                ((uint16_t)0x0002)  /*!< PHY Speed mask                                  */\n#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004)  /*!< PHY Duplex mask                                 */\n\n#define PHY_MICR_INT_EN                 ((uint16_t)0x0002)  /*!< PHY Enable interrupts                           */\n#define PHY_MICR_INT_OE                 ((uint16_t)0x0001)  /*!< PHY Enable output interrupt events              */\n\n#define PHY_MISR_LINK_INT_EN            ((uint16_t)0x0020)  /*!< Enable Interrupt on change of link status       */\n#define PHY_LINK_INTERRUPT              ((uint16_t)0x2000)  /*!< PHY link status interrupt mask                  */\n\n/* ################## SPI peripheral configuration ########################## */\n\n/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\n* Activated: CRC code is present inside driver\n* Deactivated: CRC code cleaned from driver\n*/\n\n#define USE_SPI_CRC                     1U\n\n/* Includes ------------------------------------------------------------------*/\n/**\n  * @brief Include module's header file \n  */\n\n#ifdef HAL_RCC_MODULE_ENABLED\n  #include \"stm32f4xx_hal_rcc.h\"\n#endif /* HAL_RCC_MODULE_ENABLED */\n\n#ifdef HAL_GPIO_MODULE_ENABLED\n  #include \"stm32f4xx_hal_gpio.h\"\n#endif /* HAL_GPIO_MODULE_ENABLED */\n\n#ifdef HAL_DMA_MODULE_ENABLED\n  #include \"stm32f4xx_hal_dma.h\"\n#endif /* HAL_DMA_MODULE_ENABLED */\n   \n#ifdef HAL_CORTEX_MODULE_ENABLED\n  #include \"stm32f4xx_hal_cortex.h\"\n#endif /* HAL_CORTEX_MODULE_ENABLED */\n\n#ifdef HAL_ADC_MODULE_ENABLED\n  #include \"stm32f4xx_hal_adc.h\"\n#endif /* HAL_ADC_MODULE_ENABLED */\n\n#ifdef HAL_CAN_MODULE_ENABLED\n  #include \"stm32f4xx_hal_can.h\"\n#endif /* HAL_CAN_MODULE_ENABLED */\n\n#ifdef HAL_CAN_LEGACY_MODULE_ENABLED\n  #include \"stm32f4xx_hal_can_legacy.h\"\n#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */\n\n#ifdef HAL_CRC_MODULE_ENABLED\n  #include \"stm32f4xx_hal_crc.h\"\n#endif /* HAL_CRC_MODULE_ENABLED */\n\n#ifdef HAL_CRYP_MODULE_ENABLED\n  #include \"stm32f4xx_hal_cryp.h\" \n#endif /* HAL_CRYP_MODULE_ENABLED */\n\n#ifdef HAL_DMA2D_MODULE_ENABLED\n  #include \"stm32f4xx_hal_dma2d.h\"\n#endif /* HAL_DMA2D_MODULE_ENABLED */\n\n#ifdef HAL_DAC_MODULE_ENABLED\n  #include \"stm32f4xx_hal_dac.h\"\n#endif /* HAL_DAC_MODULE_ENABLED */\n\n#ifdef HAL_DCMI_MODULE_ENABLED\n  #include \"stm32f4xx_hal_dcmi.h\"\n#endif /* HAL_DCMI_MODULE_ENABLED */\n\n#ifdef HAL_ETH_MODULE_ENABLED\n  #include \"stm32f4xx_hal_eth.h\"\n#endif /* HAL_ETH_MODULE_ENABLED */\n\n#ifdef HAL_FLASH_MODULE_ENABLED\n  #include \"stm32f4xx_hal_flash.h\"\n#endif /* HAL_FLASH_MODULE_ENABLED */\n \n#ifdef HAL_SRAM_MODULE_ENABLED\n  #include \"stm32f4xx_hal_sram.h\"\n#endif /* HAL_SRAM_MODULE_ENABLED */\n\n#ifdef HAL_NOR_MODULE_ENABLED\n  #include \"stm32f4xx_hal_nor.h\"\n#endif /* HAL_NOR_MODULE_ENABLED */\n\n#ifdef HAL_NAND_MODULE_ENABLED\n  #include \"stm32f4xx_hal_nand.h\"\n#endif /* HAL_NAND_MODULE_ENABLED */\n\n#ifdef HAL_PCCARD_MODULE_ENABLED\n  #include \"stm32f4xx_hal_pccard.h\"\n#endif /* HAL_PCCARD_MODULE_ENABLED */ \n  \n#ifdef HAL_SDRAM_MODULE_ENABLED\n  #include \"stm32f4xx_hal_sdram.h\"\n#endif /* HAL_SDRAM_MODULE_ENABLED */\n\n#ifdef HAL_HASH_MODULE_ENABLED\n #include \"stm32f4xx_hal_hash.h\"\n#endif /* HAL_HASH_MODULE_ENABLED */\n\n#ifdef HAL_I2C_MODULE_ENABLED\n #include \"stm32f4xx_hal_i2c.h\"\n#endif /* HAL_I2C_MODULE_ENABLED */\n\n#ifdef HAL_I2S_MODULE_ENABLED\n #include \"stm32f4xx_hal_i2s.h\"\n#endif /* HAL_I2S_MODULE_ENABLED */\n\n#ifdef HAL_IWDG_MODULE_ENABLED\n #include \"stm32f4xx_hal_iwdg.h\"\n#endif /* HAL_IWDG_MODULE_ENABLED */\n\n#ifdef HAL_LTDC_MODULE_ENABLED\n #include \"stm32f4xx_hal_ltdc.h\"\n#endif /* HAL_LTDC_MODULE_ENABLED */\n\n#ifdef HAL_PWR_MODULE_ENABLED\n #include \"stm32f4xx_hal_pwr.h\"\n#endif /* HAL_PWR_MODULE_ENABLED */\n\n#ifdef HAL_RNG_MODULE_ENABLED\n #include \"stm32f4xx_hal_rng.h\"\n#endif /* HAL_RNG_MODULE_ENABLED */\n\n#ifdef HAL_RTC_MODULE_ENABLED\n #include \"stm32f4xx_hal_rtc.h\"\n#endif /* HAL_RTC_MODULE_ENABLED */\n\n#ifdef HAL_SAI_MODULE_ENABLED\n #include \"stm32f4xx_hal_sai.h\"\n#endif /* HAL_SAI_MODULE_ENABLED */\n\n#ifdef HAL_SD_MODULE_ENABLED\n #include \"stm32f4xx_hal_sd.h\"\n#endif /* HAL_SD_MODULE_ENABLED */\n\n#ifdef HAL_SPI_MODULE_ENABLED\n #include \"stm32f4xx_hal_spi.h\"\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n#ifdef HAL_TIM_MODULE_ENABLED\n #include \"stm32f4xx_hal_tim.h\"\n#endif /* HAL_TIM_MODULE_ENABLED */\n\n#ifdef HAL_UART_MODULE_ENABLED\n #include \"stm32f4xx_hal_uart.h\"\n#endif /* HAL_UART_MODULE_ENABLED */\n\n#ifdef HAL_USART_MODULE_ENABLED\n #include \"stm32f4xx_hal_usart.h\"\n#endif /* HAL_USART_MODULE_ENABLED */\n\n#ifdef HAL_IRDA_MODULE_ENABLED\n #include \"stm32f4xx_hal_irda.h\"\n#endif /* HAL_IRDA_MODULE_ENABLED */\n\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\n #include \"stm32f4xx_hal_smartcard.h\"\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\n\n#ifdef HAL_WWDG_MODULE_ENABLED\n #include \"stm32f4xx_hal_wwdg.h\"\n#endif /* HAL_WWDG_MODULE_ENABLED */\n\n#ifdef HAL_PCD_MODULE_ENABLED\n #include \"stm32f4xx_hal_pcd.h\"\n#endif /* HAL_PCD_MODULE_ENABLED */\n\n#ifdef HAL_HCD_MODULE_ENABLED\n #include \"stm32f4xx_hal_hcd.h\"\n#endif /* HAL_HCD_MODULE_ENABLED */\n   \n#ifdef HAL_DSI_MODULE_ENABLED\n #include \"stm32f4xx_hal_dsi.h\"\n#endif /* HAL_DSI_MODULE_ENABLED */\n\n#ifdef HAL_QSPI_MODULE_ENABLED\n #include \"stm32f4xx_hal_qspi.h\"\n#endif /* HAL_QSPI_MODULE_ENABLED */\n\n#ifdef HAL_CEC_MODULE_ENABLED\n #include \"stm32f4xx_hal_cec.h\"\n#endif /* HAL_CEC_MODULE_ENABLED */\n\n#ifdef HAL_FMPI2C_MODULE_ENABLED\n #include \"stm32f4xx_hal_fmpi2c.h\"\n#endif /* HAL_FMPI2C_MODULE_ENABLED */\n\n#ifdef HAL_SPDIFRX_MODULE_ENABLED\n #include \"stm32f4xx_hal_spdifrx.h\"\n#endif /* HAL_SPDIFRX_MODULE_ENABLED */\n\n#ifdef HAL_DFSDM_MODULE_ENABLED\n #include \"stm32f4xx_hal_dfsdm.h\"\n#endif /* HAL_DFSDM_MODULE_ENABLED */\n\n#ifdef HAL_LPTIM_MODULE_ENABLED\n #include \"stm32f4xx_hal_lptim.h\"\n#endif /* HAL_LPTIM_MODULE_ENABLED */\n\n#ifdef HAL_MMC_MODULE_ENABLED\n #include \"stm32f4xx_hal_mmc.h\"\n#endif /* HAL_MMC_MODULE_ENABLED */\n\n/* Exported macro ------------------------------------------------------------*/\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  The assert_param macro is used for function's parameters check.\n  * @param  expr If expr is false, it calls assert_failed function\n  *         which reports the name of the source file and the source\n  *         line number of the call that failed. \n  *         If expr is true, it returns no value.\n  * @retval None\n  */\n  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\n/* Exported functions ------------------------------------------------------- */\n  void assert_failed(uint8_t* file, uint32_t line);\n#else\n  #define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_CONF_H */\n \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/inc/stm32f4xx_it.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f7xx_it.h\n  * @brief   This file contains the headers of the interrupt handlers.\n  ******************************************************************************\n  *\n  * COPYRIGHT(c) 2018 STMicroelectronics\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F7xx_IT_H\n#define __STM32F7xx_IT_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions ------------------------------------------------------- */\n\nvoid NMI_Handler(void);\nvoid HardFault_Handler(void);\nvoid MemManage_Handler(void);\nvoid BusFault_Handler(void);\nvoid UsageFault_Handler(void);\nvoid SVC_Handler(void);\nvoid DebugMon_Handler(void);\nvoid PendSV_Handler(void);\nvoid SysTick_Handler(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F7xx_IT_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/src/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#include \"main.h\"\n#include \"cmsis_os.h\"\n\n#include \"examples_common_lwesp_callback_func.h\"\n#include \"lwesp/lwesp.h\"\n#include \"mqtt_client_api.h\"\n#include \"station_manager.h\"\n\nstatic void LL_Init(void);\nvoid SystemClock_Config(void);\nstatic void USART_Printf_Init(void);\n\nstatic void init_thread(void* arg);\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    LL_Init();            /* Reset of all peripherals, initializes the Flash interface and the Systick. */\n    SystemClock_Config(); /* Configure the system clock */\n    USART_Printf_Init();  /* Init USART for printf */\n\n    printf(\"Application running on STM32F429ZI-Nucleo!\\r\\n\");\n\n    /* Initialize, create first thread and start kernel */\n    osKernelInitialize();\n    const osThreadAttr_t attr = {.stack_size = 512};\n    osThreadNew(init_thread, NULL, &attr);\n    osKernelStart();\n\n    while (1) {}\n}\n\n/**\n * \\brief           Initialization thread\n * \\param[in]       arg: Thread argument\n */\nstatic void\ninit_thread(void* arg) {\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /* Create a MQTT API thread */\n    lwesp_sys_thread_create(NULL, \"netconn_client\", (lwesp_sys_thread_fn)lwesp_mqtt_client_api_thread, NULL,\n                            LWESP_SYS_THREAD_SS, LWESP_SYS_THREAD_PRIO);\n    osThreadExit();\n}\n\n/**\n * \\brief           Low-Layer initialization\n */\nstatic void\nLL_Init(void) {\n    NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\n    NVIC_SetPriority(MemoryManagement_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(BusFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(UsageFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(SVCall_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(DebugMonitor_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));\n}\n\n/**\n * \\brief           System clock configuration\n */\nvoid\nSystemClock_Config(void) {\n    /* Configure flash latency */\n    LL_FLASH_SetLatency(LL_FLASH_LATENCY_5);\n    if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_5) {\n        while (1) {}\n    }\n\n    /* Set voltage scaling */\n    LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);\n    LL_PWR_DisableOverDriveMode();\n\n    /* Enable HSE */\n    LL_RCC_HSE_EnableBypass();\n    LL_RCC_HSE_Enable();\n    while (LL_RCC_HSE_IsReady() != 1) {}\n\n    /* Configure PLL */\n    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_4, 168, LL_RCC_PLLP_DIV_2);\n    LL_RCC_PLL_Enable();\n    while (LL_RCC_PLL_IsReady() != 1) {}\n\n    /* Set prescalers */\n    LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);\n    LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_4);\n    LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);\n\n    /* Configure system clock */\n    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);\n    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}\n\n    /* Configure systick */\n    LL_Init1msTick(168000000);\n    LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);\n    LL_SYSTICK_EnableIT();\n    LL_SetSystemCoreClock(168000000);\n}\n\n/**\n * \\brief           Init USART1 for printf output\n */\nstatic void\nUSART_Printf_Init(void) {\n    LL_USART_InitTypeDef USART_InitStruct = {0};\n    LL_GPIO_InitTypeDef GPIO_InitStruct = {0};\n\n    /* Peripheral clock enable */\n    LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3);\n    LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD);\n\n    /*\n     * USART3 GPIO Configuration\n     *\n     * PD8   ------> USART3_TX\n     * PD9   ------> USART3_RX\n     */\n    GPIO_InitStruct.Pin = LL_GPIO_PIN_8 | LL_GPIO_PIN_9;\n    GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;\n    GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;\n    GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;\n    GPIO_InitStruct.Alternate = LL_GPIO_AF_7;\n    LL_GPIO_Init(GPIOD, &GPIO_InitStruct);\n\n    USART_InitStruct.BaudRate = 921600;\n    USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;\n    USART_InitStruct.StopBits = LL_USART_STOPBITS_1;\n    USART_InitStruct.Parity = LL_USART_PARITY_NONE;\n    USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;\n    USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;\n    USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;\n    LL_USART_Init(USART3, &USART_InitStruct);\n    LL_USART_ConfigAsyncMode(USART3);\n    LL_USART_Enable(USART3);\n}\n\n/**\n * \\brief           Printf character handler\n * \\param[in]       ch: Character to send\n * \\param[in]       f: File pointer\n * \\return          Written character\n */\n#ifdef __GNUC__\nint\n__io_putchar(int ch) {\n#else\nint\nfputc(int ch, FILE* fil) {\n#endif\n    LL_USART_TransmitData8(USART3, (uint8_t)ch);\n    while (!LL_USART_IsActiveFlag_TXE(USART3)) {}\n    return ch;\n}\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/src/stm32f4xx_it.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_it.c\n  * @brief   Interrupt Service Routines.\n  ******************************************************************************\n  *\n  * COPYRIGHT(c) 2018 STMicroelectronics\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n#include \"stm32f4xx_it.h\"\n\n#include \"cmsis_os.h\"\n\n/******************************************************************************/\n/*            Cortex-M4 Processor Interruption and Exception Handlers         */ \n/******************************************************************************/\n\n/**\n * \\brief           This function handles Non maskable interrupt.\n */\nvoid NMI_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Hard fault interrupt.\n */\nvoid\nHardFault_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Mem manage interrupt.\n */\nvoid\nMemManage_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Bus fault interrupt.\n */\nvoid\nBusFault_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Usage fault interrupt.\n */\nvoid\nUsageFault_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Debug monitor interrupt.\n */\nvoid\nDebugMon_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Systick interrupt.\n */\nvoid\nSysTick_Handler(void) {\n    extern void xPortSysTickHandler(void);\n    xPortSysTickHandler();\n}\n\n/******************************************************************************/\n/* STM32F4xx Peripheral Interrupt Handlers                                    */\n/* Add here the Interrupt Handlers for the used peripherals.                  */\n/* For the available peripheral interrupt handler names,                      */\n/* please refer to the startup file (startup_stm32f4xx.s).                    */\n/******************************************************************************/\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/src/syscalls.c",
    "content": "/* Support files for GNU libc.  Files in the system namespace go here.\n   Files in the C namespace (ie those that do not start with an\n   underscore) go in .c.  */\n\n#include <_ansi.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/fcntl.h>\n#include <stdio.h>\n#include <string.h>\n#include <time.h>\n#include <sys/time.h>\n#include <sys/times.h>\n#include <errno.h>\n#include <reent.h>\n#include <unistd.h>\n#include <sys/wait.h>\n\n#define FreeRTOS\n#define MAX_STACK_SIZE 0x2000\n\nextern int __io_putchar(int ch) __attribute__((weak));\nextern int __io_getchar(void) __attribute__((weak));\n\n#ifndef FreeRTOS\n  register char * stack_ptr asm(\"sp\");\n#endif\n\ncaddr_t _sbrk(int incr)\n{\n\textern char end asm(\"end\");\n\tstatic char *heap_end;\n\tchar *prev_heap_end,*min_stack_ptr;\n\n\tif (heap_end == 0)\n\t\theap_end = &end;\n\n\tprev_heap_end = heap_end;\n\n#ifdef FreeRTOS\n\t/* Use the NVIC offset register to locate the main stack pointer. */\n\tmin_stack_ptr = (char*)(*(unsigned int *)*(unsigned int *)0xE000ED08);\n\t/* Locate the STACK bottom address */\n\tmin_stack_ptr -= MAX_STACK_SIZE;\n\n\tif (heap_end + incr > min_stack_ptr)\n#else\n\tif (heap_end + incr > stack_ptr)\n#endif\n\t{\n//\t\twrite(1, \"Heap and stack collision\\n\", 25);\n//\t\tabort();\n\t\terrno = ENOMEM;\n\t\treturn (caddr_t) -1;\n\t}\n\n\theap_end += incr;\n\n\treturn (caddr_t) prev_heap_end;\n}\n\n/*\n * _gettimeofday primitive (Stub function)\n * */\nint _gettimeofday (struct timeval * tp, struct timezone * tzp)\n{\n  /* Return fixed data for the timezone.  */\n  if (tzp)\n    {\n      tzp->tz_minuteswest = 0;\n      tzp->tz_dsttime = 0;\n    }\n\n  return 0;\n}\nvoid initialise_monitor_handles()\n{\n}\n\nint _getpid(void)\n{\n\treturn 1;\n}\n\nint _kill(int pid, int sig)\n{\n\terrno = EINVAL;\n\treturn -1;\n}\n\nvoid _exit (int status)\n{\n\t_kill(status, -1);\n\twhile (1) {}\n}\n\nint _write(int file, char *ptr, int len)\n{\n    int DataIdx;\n\n    for (DataIdx = 0; DataIdx < len; DataIdx++) {\n        __io_putchar( *ptr++ );\n    }\n    return len;\n}\n\nint _close(int file)\n{\n\treturn -1;\n}\n\nint _fstat(int file, struct stat *st)\n{\n\tst->st_mode = S_IFCHR;\n\treturn 0;\n}\n\nint _isatty(int file)\n{\n\treturn 1;\n}\n\nint _lseek(int file, int ptr, int dir)\n{\n\treturn 0;\n}\n\nint _read(int file, char *ptr, int len)\n{\n\tint DataIdx;\n\n\tfor (DataIdx = 0; DataIdx < len; DataIdx++)\n\t{\n\t  *ptr++ = __io_getchar();\n\t}\n\n   return len;\n}\n\nint _open(char *path, int flags, ...)\n{\n\t/* Pretend like we always fail */\n\treturn -1;\n}\n\nint _wait(int *status)\n{\n\terrno = ECHILD;\n\treturn -1;\n}\n\nint _unlink(char *name)\n{\n\terrno = ENOENT;\n\treturn -1;\n}\n\nint _times(struct tms *buf)\n{\n\treturn -1;\n}\n\nint _stat(char *file, struct stat *st)\n{\n\tst->st_mode = S_IFCHR;\n\treturn 0;\n}\n\nint _link(char *old, char *new)\n{\n\terrno = EMLINK;\n\treturn -1;\n}\n\nint _fork(void)\n{\n\terrno = EAGAIN;\n\treturn -1;\n}\n\nint _execve(char *name, char **argv, char **env)\n{\n\terrno = ENOMEM;\n\treturn -1;\n}\n"
  },
  {
    "path": "examples/stm32/mqtt_client_api_rtos_stm32f429zi_nucleo/src/system_stm32f4xx.c",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f4xx.c\n  * @author  MCD Application Team\n  * @version V2.6.1\n  * @date    14-February-2017\n  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\n  *\n  *   This file provides two functions and one global variable to be called from \n  *   user application:\n  *      - SystemInit(): This function is called at startup just after reset and \n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32f4xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\n  *                                  by the user application to setup the SysTick \n  *                                  timer or configure other parameters.\n  *                                     \n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx_system\n  * @{\n  */  \n  \n/** @addtogroup STM32F4xx_System_Private_Includes\n  * @{\n  */\n\n\n#include \"stm32f4xx.h\"\n\n#if !defined  (HSE_VALUE) \n  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Defines\n  * @{\n  */\n\n/************************* Miscellaneous Configuration ************************/\n/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\\\n || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\n/* #define DATA_IN_ExtSRAM */\n#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\\\n          STM32F412Zx || STM32F412Vx */\n \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/* #define DATA_IN_ExtSDRAM */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\\\n          STM32F479xx */\n\n/*!< Uncomment the following line if you need to relocate your vector Table in\n     Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. \n                                   This value must be a multiple of 0x200. */\n/******************************************************************************/\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Variables\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nuint32_t SystemCoreClock = 16000000;\nconst uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\nconst uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\n  * @{\n  */\n\n#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\n  static void SystemInit_ExtMemCtl(void); \n#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system\n  *         Initialize the FPU setting, vector table location and External memory \n  *         configuration.\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit(void)\n{\n  /* FPU settings ------------------------------------------------------------*/\n  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\n    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */\n  #endif\n  /* Reset the RCC clock configuration to the default reset state ------------*/\n  /* Set HSION bit */\n  RCC->CR |= (uint32_t)0x00000001;\n\n  /* Reset CFGR register */\n  RCC->CFGR = 0x00000000;\n\n  /* Reset HSEON, CSSON and PLLON bits */\n  RCC->CR &= (uint32_t)0xFEF6FFFF;\n\n  /* Reset PLLCFGR register */\n  RCC->PLLCFGR = 0x24003010;\n\n  /* Reset HSEBYP bit */\n  RCC->CR &= (uint32_t)0xFFFBFFFF;\n\n  /* Disable all interrupts */\n  RCC->CIR = 0x00000000;\n\n#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\n  SystemInit_ExtMemCtl(); \n#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\n\n  /* Configure the Vector Table location add offset address ------------------*/\n#ifdef VECT_TAB_SRAM\n  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#else\n  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\n#endif\n}\n\n/**\n   * @brief  Update SystemCoreClock variable according to Clock Register Values.\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *           \n  * @note   Each time the core clock (HCLK) changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.         \n  *     \n  * @note   - The system frequency computed by this function is not the real \n  *           frequency in the chip. It is calculated based on the predefined \n  *           constant and the selected clock source:\n  *             \n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\n  *                                              \n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\n  *                          \n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \n  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.\n  *         \n  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value\n  *             16 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.   \n  *    \n  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value\n  *              depends on the application requirements), user has to ensure that HSE_VALUE\n  *              is same as the real frequency of the crystal used. Otherwise, this function\n  *              may have wrong result.\n  *                \n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  *     \n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate(void)\n{\n  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\n  \n  /* Get SYSCLK source -------------------------------------------------------*/\n  tmp = RCC->CFGR & RCC_CFGR_SWS;\n\n  switch (tmp)\n  {\n    case 0x00:  /* HSI used as system clock source */\n      SystemCoreClock = HSI_VALUE;\n      break;\n    case 0x04:  /* HSE used as system clock source */\n      SystemCoreClock = HSE_VALUE;\n      break;\n    case 0x08:  /* PLL used as system clock source */\n\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\n         SYSCLK = PLL_VCO / PLL_P\n         */    \n      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\n      \n      if (pllsource != 0)\n      {\n        /* HSE used as PLL clock source */\n        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\n      }\n      else\n      {\n        /* HSI used as PLL clock source */\n        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\n      }\n\n      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\n      SystemCoreClock = pllvco/pllp;\n      break;\n    default:\n      SystemCoreClock = HSI_VALUE;\n      break;\n  }\n  /* Compute HCLK frequency --------------------------------------------------*/\n  /* Get HCLK prescaler */\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\n  /* HCLK frequency */\n  SystemCoreClock >>= tmp;\n}\n\n#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief  Setup the external memory controller.\n  *         Called in startup_stm32f4xx.s before jump to main.\n  *         This function configures the external memories (SRAM/SDRAM)\n  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit_ExtMemCtl(void)\n{\n  __IO uint32_t tmp = 0x00;\n\n  register uint32_t tmpreg = 0, timeout = 0xFFFF;\n  register __IO uint32_t index;\n\n  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */\n  RCC->AHB1ENR |= 0x000001F8;\n\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\n  \n  /* Connect PDx pins to FMC Alternate function */\n  GPIOD->AFR[0]  = 0x00CCC0CC;\n  GPIOD->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PDx pins in Alternate function mode */  \n  GPIOD->MODER   = 0xAAAA0A8A;\n  /* Configure PDx pins speed to 100 MHz */  \n  GPIOD->OSPEEDR = 0xFFFF0FCF;\n  /* Configure PDx pins Output type to push-pull */  \n  GPIOD->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PDx pins */ \n  GPIOD->PUPDR   = 0x00000000;\n\n  /* Connect PEx pins to FMC Alternate function */\n  GPIOE->AFR[0]  = 0xC00CC0CC;\n  GPIOE->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PEx pins in Alternate function mode */ \n  GPIOE->MODER   = 0xAAAA828A;\n  /* Configure PEx pins speed to 100 MHz */ \n  GPIOE->OSPEEDR = 0xFFFFC3CF;\n  /* Configure PEx pins Output type to push-pull */  \n  GPIOE->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PEx pins */ \n  GPIOE->PUPDR   = 0x00000000;\n  \n  /* Connect PFx pins to FMC Alternate function */\n  GPIOF->AFR[0]  = 0xCCCCCCCC;\n  GPIOF->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PFx pins in Alternate function mode */   \n  GPIOF->MODER   = 0xAA800AAA;\n  /* Configure PFx pins speed to 50 MHz */ \n  GPIOF->OSPEEDR = 0xAA800AAA;\n  /* Configure PFx pins Output type to push-pull */  \n  GPIOF->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PFx pins */ \n  GPIOF->PUPDR   = 0x00000000;\n\n  /* Connect PGx pins to FMC Alternate function */\n  GPIOG->AFR[0]  = 0xCCCCCCCC;\n  GPIOG->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PGx pins in Alternate function mode */ \n  GPIOG->MODER   = 0xAAAAAAAA;\n  /* Configure PGx pins speed to 50 MHz */ \n  GPIOG->OSPEEDR = 0xAAAAAAAA;\n  /* Configure PGx pins Output type to push-pull */  \n  GPIOG->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PGx pins */ \n  GPIOG->PUPDR   = 0x00000000;\n  \n  /* Connect PHx pins to FMC Alternate function */\n  GPIOH->AFR[0]  = 0x00C0CC00;\n  GPIOH->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PHx pins in Alternate function mode */ \n  GPIOH->MODER   = 0xAAAA08A0;\n  /* Configure PHx pins speed to 50 MHz */ \n  GPIOH->OSPEEDR = 0xAAAA08A0;\n  /* Configure PHx pins Output type to push-pull */  \n  GPIOH->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PHx pins */ \n  GPIOH->PUPDR   = 0x00000000;\n  \n  /* Connect PIx pins to FMC Alternate function */\n  GPIOI->AFR[0]  = 0xCCCCCCCC;\n  GPIOI->AFR[1]  = 0x00000CC0;\n  /* Configure PIx pins in Alternate function mode */ \n  GPIOI->MODER   = 0x0028AAAA;\n  /* Configure PIx pins speed to 50 MHz */ \n  GPIOI->OSPEEDR = 0x0028AAAA;\n  /* Configure PIx pins Output type to push-pull */  \n  GPIOI->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PIx pins */ \n  GPIOI->PUPDR   = 0x00000000;\n  \n/*-- FMC Configuration -------------------------------------------------------*/\n  /* Enable the FMC interface clock */\n  RCC->AHB3ENR |= 0x00000001;\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\n\n  FMC_Bank5_6->SDCR[0] = 0x000019E4;\n  FMC_Bank5_6->SDTR[0] = 0x01115351;      \n  \n  /* SDRAM initialization sequence */\n  /* Clock enable command */\n  FMC_Bank5_6->SDCMR = 0x00000011; \n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n\n  /* Delay */\n  for (index = 0; index<1000; index++);\n  \n  /* PALL command */\n  FMC_Bank5_6->SDCMR = 0x00000012;           \n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n  \n  /* Auto refresh command */\n  FMC_Bank5_6->SDCMR = 0x00000073;\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n \n  /* MRD register program */\n  FMC_Bank5_6->SDCMR = 0x00046014;\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  } \n  \n  /* Set refresh count */\n  tmpreg = FMC_Bank5_6->SDRTR;\n  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));\n  \n  /* Disable write protection */\n  tmpreg = FMC_Bank5_6->SDCR[0]; \n  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\n  /* Configure and enable Bank1_SRAM2 */\n  FMC_Bank1->BTCR[2]  = 0x00001011;\n  FMC_Bank1->BTCR[3]  = 0x00000201;\n  FMC_Bank1E->BWTR[2] = 0x0fffffff;\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ \n#if defined(STM32F469xx) || defined(STM32F479xx)\n  /* Configure and enable Bank1_SRAM2 */\n  FMC_Bank1->BTCR[2]  = 0x00001091;\n  FMC_Bank1->BTCR[3]  = 0x00110212;\n  FMC_Bank1E->BWTR[2] = 0x0fffffff;\n#endif /* STM32F469xx || STM32F479xx */\n\n  (void)(tmp); \n}\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\n/**\n  * @brief  Setup the external memory controller.\n  *         Called in startup_stm32f4xx.s before jump to main.\n  *         This function configures the external memories (SRAM/SDRAM)\n  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit_ExtMemCtl(void)\n{\n  __IO uint32_t tmp = 0x00;\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#if defined (DATA_IN_ExtSDRAM)\n  register uint32_t tmpreg = 0, timeout = 0xFFFF;\n  register __IO uint32_t index;\n\n#if defined(STM32F446xx)\n  /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface\n      clock */\n  RCC->AHB1ENR |= 0x0000007D;\n#else\n  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface \n      clock */\n  RCC->AHB1ENR |= 0x000001F8;\n#endif /* STM32F446xx */  \n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\n  \n#if defined(STM32F446xx)\n  /* Connect PAx pins to FMC Alternate function */\n  GPIOA->AFR[0]  |= 0xC0000000;\n  GPIOA->AFR[1]  |= 0x00000000;\n  /* Configure PDx pins in Alternate function mode */\n  GPIOA->MODER   |= 0x00008000;\n  /* Configure PDx pins speed to 50 MHz */\n  GPIOA->OSPEEDR |= 0x00008000;\n  /* Configure PDx pins Output type to push-pull */\n  GPIOA->OTYPER  |= 0x00000000;\n  /* No pull-up, pull-down for PDx pins */\n  GPIOA->PUPDR   |= 0x00000000;\n\n  /* Connect PCx pins to FMC Alternate function */\n  GPIOC->AFR[0]  |= 0x00CC0000;\n  GPIOC->AFR[1]  |= 0x00000000;\n  /* Configure PDx pins in Alternate function mode */\n  GPIOC->MODER   |= 0x00000A00;\n  /* Configure PDx pins speed to 50 MHz */\n  GPIOC->OSPEEDR |= 0x00000A00;\n  /* Configure PDx pins Output type to push-pull */\n  GPIOC->OTYPER  |= 0x00000000;\n  /* No pull-up, pull-down for PDx pins */\n  GPIOC->PUPDR   |= 0x00000000;\n#endif /* STM32F446xx */\n\n  /* Connect PDx pins to FMC Alternate function */\n  GPIOD->AFR[0]  = 0x000000CC;\n  GPIOD->AFR[1]  = 0xCC000CCC;\n  /* Configure PDx pins in Alternate function mode */  \n  GPIOD->MODER   = 0xA02A000A;\n  /* Configure PDx pins speed to 50 MHz */  \n  GPIOD->OSPEEDR = 0xA02A000A;\n  /* Configure PDx pins Output type to push-pull */  \n  GPIOD->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PDx pins */ \n  GPIOD->PUPDR   = 0x00000000;\n\n  /* Connect PEx pins to FMC Alternate function */\n  GPIOE->AFR[0]  = 0xC00000CC;\n  GPIOE->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PEx pins in Alternate function mode */ \n  GPIOE->MODER   = 0xAAAA800A;\n  /* Configure PEx pins speed to 50 MHz */ \n  GPIOE->OSPEEDR = 0xAAAA800A;\n  /* Configure PEx pins Output type to push-pull */  \n  GPIOE->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PEx pins */ \n  GPIOE->PUPDR   = 0x00000000;\n\n  /* Connect PFx pins to FMC Alternate function */\n  GPIOF->AFR[0]  = 0xCCCCCCCC;\n  GPIOF->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PFx pins in Alternate function mode */   \n  GPIOF->MODER   = 0xAA800AAA;\n  /* Configure PFx pins speed to 50 MHz */ \n  GPIOF->OSPEEDR = 0xAA800AAA;\n  /* Configure PFx pins Output type to push-pull */  \n  GPIOF->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PFx pins */ \n  GPIOF->PUPDR   = 0x00000000;\n\n  /* Connect PGx pins to FMC Alternate function */\n  GPIOG->AFR[0]  = 0xCCCCCCCC;\n  GPIOG->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PGx pins in Alternate function mode */ \n  GPIOG->MODER   = 0xAAAAAAAA;\n  /* Configure PGx pins speed to 50 MHz */ \n  GPIOG->OSPEEDR = 0xAAAAAAAA;\n  /* Configure PGx pins Output type to push-pull */  \n  GPIOG->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PGx pins */ \n  GPIOG->PUPDR   = 0x00000000;\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F469xx) || defined(STM32F479xx)  \n  /* Connect PHx pins to FMC Alternate function */\n  GPIOH->AFR[0]  = 0x00C0CC00;\n  GPIOH->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PHx pins in Alternate function mode */ \n  GPIOH->MODER   = 0xAAAA08A0;\n  /* Configure PHx pins speed to 50 MHz */ \n  GPIOH->OSPEEDR = 0xAAAA08A0;\n  /* Configure PHx pins Output type to push-pull */  \n  GPIOH->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PHx pins */ \n  GPIOH->PUPDR   = 0x00000000;\n  \n  /* Connect PIx pins to FMC Alternate function */\n  GPIOI->AFR[0]  = 0xCCCCCCCC;\n  GPIOI->AFR[1]  = 0x00000CC0;\n  /* Configure PIx pins in Alternate function mode */ \n  GPIOI->MODER   = 0x0028AAAA;\n  /* Configure PIx pins speed to 50 MHz */ \n  GPIOI->OSPEEDR = 0x0028AAAA;\n  /* Configure PIx pins Output type to push-pull */  \n  GPIOI->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PIx pins */ \n  GPIOI->PUPDR   = 0x00000000;\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n  \n/*-- FMC Configuration -------------------------------------------------------*/\n  /* Enable the FMC interface clock */\n  RCC->AHB3ENR |= 0x00000001;\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\n\n  /* Configure and enable SDRAM bank1 */\n#if defined(STM32F446xx)\n  FMC_Bank5_6->SDCR[0] = 0x00001954;\n#else  \n  FMC_Bank5_6->SDCR[0] = 0x000019E4;\n#endif /* STM32F446xx */\n  FMC_Bank5_6->SDTR[0] = 0x01115351;      \n  \n  /* SDRAM initialization sequence */\n  /* Clock enable command */\n  FMC_Bank5_6->SDCMR = 0x00000011; \n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n\n  /* Delay */\n  for (index = 0; index<1000; index++);\n  \n  /* PALL command */\n  FMC_Bank5_6->SDCMR = 0x00000012;           \n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n  \n  /* Auto refresh command */\n#if defined(STM32F446xx)\n  FMC_Bank5_6->SDCMR = 0x000000F3;\n#else  \n  FMC_Bank5_6->SDCMR = 0x00000073;\n#endif /* STM32F446xx */\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n \n  /* MRD register program */\n#if defined(STM32F446xx)\n  FMC_Bank5_6->SDCMR = 0x00044014;\n#else  \n  FMC_Bank5_6->SDCMR = 0x00046014;\n#endif /* STM32F446xx */\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  } \n  \n  /* Set refresh count */\n  tmpreg = FMC_Bank5_6->SDRTR;\n#if defined(STM32F446xx)\n  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));\n#else    \n  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));\n#endif /* STM32F446xx */\n  \n  /* Disable write protection */\n  tmpreg = FMC_Bank5_6->SDCR[0]; \n  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);\n#endif /* DATA_IN_ExtSDRAM */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\\\n || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\n\n#if defined(DATA_IN_ExtSRAM)\n/*-- GPIOs Configuration -----------------------------------------------------*/\n   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\n  RCC->AHB1ENR   |= 0x00000078;\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\n  \n  /* Connect PDx pins to FMC Alternate function */\n  GPIOD->AFR[0]  = 0x00CCC0CC;\n  GPIOD->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PDx pins in Alternate function mode */  \n  GPIOD->MODER   = 0xAAAA0A8A;\n  /* Configure PDx pins speed to 100 MHz */  \n  GPIOD->OSPEEDR = 0xFFFF0FCF;\n  /* Configure PDx pins Output type to push-pull */  \n  GPIOD->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PDx pins */ \n  GPIOD->PUPDR   = 0x00000000;\n\n  /* Connect PEx pins to FMC Alternate function */\n  GPIOE->AFR[0]  = 0xC00CC0CC;\n  GPIOE->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PEx pins in Alternate function mode */ \n  GPIOE->MODER   = 0xAAAA828A;\n  /* Configure PEx pins speed to 100 MHz */ \n  GPIOE->OSPEEDR = 0xFFFFC3CF;\n  /* Configure PEx pins Output type to push-pull */  \n  GPIOE->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PEx pins */ \n  GPIOE->PUPDR   = 0x00000000;\n\n  /* Connect PFx pins to FMC Alternate function */\n  GPIOF->AFR[0]  = 0x00CCCCCC;\n  GPIOF->AFR[1]  = 0xCCCC0000;\n  /* Configure PFx pins in Alternate function mode */   \n  GPIOF->MODER   = 0xAA000AAA;\n  /* Configure PFx pins speed to 100 MHz */ \n  GPIOF->OSPEEDR = 0xFF000FFF;\n  /* Configure PFx pins Output type to push-pull */  \n  GPIOF->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PFx pins */ \n  GPIOF->PUPDR   = 0x00000000;\n\n  /* Connect PGx pins to FMC Alternate function */\n  GPIOG->AFR[0]  = 0x00CCCCCC;\n  GPIOG->AFR[1]  = 0x000000C0;\n  /* Configure PGx pins in Alternate function mode */ \n  GPIOG->MODER   = 0x00085AAA;\n  /* Configure PGx pins speed to 100 MHz */ \n  GPIOG->OSPEEDR = 0x000CAFFF;\n  /* Configure PGx pins Output type to push-pull */  \n  GPIOG->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PGx pins */ \n  GPIOG->PUPDR   = 0x00000000;\n  \n/*-- FMC/FSMC Configuration --------------------------------------------------*/\n  /* Enable the FMC/FSMC interface clock */\n  RCC->AHB3ENR         |= 0x00000001;\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\n  /* Configure and enable Bank1_SRAM2 */\n  FMC_Bank1->BTCR[2]  = 0x00001011;\n  FMC_Bank1->BTCR[3]  = 0x00000201;\n  FMC_Bank1E->BWTR[2] = 0x0fffffff;\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ \n#if defined(STM32F469xx) || defined(STM32F479xx)\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\n  /* Configure and enable Bank1_SRAM2 */\n  FMC_Bank1->BTCR[2]  = 0x00001091;\n  FMC_Bank1->BTCR[3]  = 0x00110212;\n  FMC_Bank1E->BWTR[2] = 0x0fffffff;\n#endif /* STM32F469xx || STM32F479xx */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\\\n   || defined(STM32F412Zx) || defined(STM32F412Vx)\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\n  /* Configure and enable Bank1_SRAM2 */\n  FSMC_Bank1->BTCR[2]  = 0x00001011;\n  FSMC_Bank1->BTCR[3]  = 0x00000201;\n  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */\n\n#endif /* DATA_IN_ExtSRAM */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\\\n          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ \n  (void)(tmp); \n}\n#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
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    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/.vscode/c_cpp_properties.json",
    "content": "{\n    \"version\": 4,\n    \"configurations\": [\n        {\n            /* \n             * ms-vscode.cmake-tools plugin should be installed.\n             * \n             * It provides data for C/C++ plugin,\n             * such as include paths, browse paths, defines, etc.\n             */\n            \"name\": \"STM32\",\n            \"configurationProvider\": \"ms-vscode.cmake-tools\",\n            \"intelliSenseMode\": \"${default}\"\n        }\n    ]\n}\n"
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    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/.vscode/extensions.json",
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    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/.vscode/launch.json",
    "content": "{\n    // Use IntelliSense to learn about possible attributes.\n    // Hover to view descriptions of existing attributes.\n    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387\n    \"version\": \"0.2.0\",\n    \"configurations\": [\n        {\n            \"name\": \"Debug Microcontroller - ST-Link\",\n            \"cwd\": \"${workspaceFolder}\",\n            \"type\": \"cortex-debug\",\n            \"executable\": \"${command:cmake.launchTargetPath}\", //or fixed file path: build/stm32h735g-dk-led.elf\n            \"request\": \"launch\",                //Use \"attach\" to connect to target w/o elf download\n            \"servertype\": \"stlink\",\n            \"device\": \"\",                       //MCU used, ex. \"STM32H735IG\"\n            \"interface\": \"swd\",\n            \"serialNumber\": \"\",                 //Set ST-Link ID if you use multiple at the same time\n            \"runToMain\": true,\n            \"svdFile\": \"path/to/file.svd\",      //Path to SVD file to see registers\n            \"v1\": false,\n            \"showDevDebugOutput\": \"both\",\n\n            /* Will get automatically detected if STM32CubeIDE is installed to default directory\n               or it can be manually provided if necessary.. */\n            //\"serverpath\": \"c:\\\\ST\\\\STM32CubeIDE_1.7.0\\\\STM32CubeIDE\\\\plugins\\\\com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.win32_2.0.100.202109301221\\\\tools\\\\bin\\\\ST-LINK_gdbserver.exe\",\n            //\"armToolchainPath\": \"c:\\\\ST\\\\STM32CubeIDE_1.7.0\\\\STM32CubeIDE\\\\plugins\\\\com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.win32_2.0.0.202105311346\\\\tools\\\\bin\",\n            //\"stm32cubeprogrammer\": \"c:\\\\Program Files\\\\STMicroelectronics\\\\STM32Cube\\\\STM32CubeProgrammer\\\\bin\",\n\n            /* If you use external loader, add additional arguments */\n            //\"serverArgs\": [\"--extload\", \"path/to/ext/loader.stldr\"],\n        }\n    ]\n}"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/.vscode/tasks.json",
    "content": "{\n\t\"version\": \"2.0.0\",\n\t\"tasks\": [\n        {\n            \"type\": \"cppbuild\",\n            \"label\": \"Build project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"-j\", \"8\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": [\"$gcc\"],\n            \"group\": {\n                \"kind\": \"build\",\n                \"isDefault\": true\n            }\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Re-build project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"--clean-first\", \"-v\", \"-j\", \"8\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": [\"$gcc\"],\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Clean project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"--target\", \"clean\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"CubeProg: Flash project (SWD)\",\n            \"command\": \"STM32_Programmer_CLI\",\n            \"args\": [\n                \"--connect\",\n                \"port=swd\",\n                \"--download\", \"${command:cmake.launchTargetPath}\",\n                \"-hardRst\"\n            ],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"CubeProg: Flash project with defined serial number (SWD) - you must set serial number first\",\n            \"command\": \"STM32_Programmer_CLI\",\n            \"args\": [\n                \"--connect\",\n                \"port=swd\",\n                \"sn=<yourserialnumber>\",\n                \"--download\", \"${command:cmake.launchTargetPath}\",\n                \"-hardRst\"\n            ],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"CubeProg: List all available communication interfaces\",\n            \"command\": \"STM32_Programmer_CLI\",\n            \"args\": [\n                \"--list\",\n            ],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n    ]\n}\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.22)\n\n#\n# Core project settings\n#\nset(PROJ_PATH                       ${CMAKE_CURRENT_SOURCE_DIR})\nproject(lwesp_stm32l496g_discovery_netconn_client_rtos)\nenable_language(C CXX ASM)\nmessage(\"Build type: \"              ${CMAKE_BUILD_TYPE})\n\n# Setup compiler settings\nset(CMAKE_C_STANDARD                11)\nset(CMAKE_C_STANDARD_REQUIRED       ON)\nset(CMAKE_C_EXTENSIONS              ON)\nset(CMAKE_CXX_STANDARD              20)\nset(CMAKE_CXX_STANDARD_REQUIRED     ON)\nset(CMAKE_CXX_EXTENSIONS            ON)\n\n#\n# Core MCU flags, CPU, instruction set and FPU setup\n#\nset(CPU_PARAMETERS\n    -mthumb\n    # Other parameters\n    # -mcpu, -mfloat, -mfloat-abi, ...\n    -mcpu=cortex-m4\n    -mfpu=fpv4-sp-d16\n    -mfloat-abi=hard\n)\n\n# Set linker script\nset(linker_script_SRC               ${PROJ_PATH}/STM32CubeIDE/Debug_STM32L496AG_FLASH.ld)\nset(EXECUTABLE                      ${CMAKE_PROJECT_NAME})\n\n#\n# Source files\n#\nset(src_freertos_SRCS \n    ${PROJ_PATH}/../../lib/FreeRTOS/CMSIS_RTOS_V2/cmsis_os2.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/croutine.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/event_groups.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/portable/MemMang/heap_4.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/list.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/portable/GCC/ARM_CM4F/port.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/queue.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/tasks.c\n    ${PROJ_PATH}/../../lib/FreeRTOS/timers.c)\n\nset(src_stm32l4xx_hal_drivers_SRCS \n    ${PROJ_PATH}/../../lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c\n    ${PROJ_PATH}/../../lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c\n    ${PROJ_PATH}/../../lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c\n    ${PROJ_PATH}/../../lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c\n    ${PROJ_PATH}/../../lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c\n    ${PROJ_PATH}/../../lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c\n    ${PROJ_PATH}/../../lib/st/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c)\n\nset(src_user_SRCS \n    ${PROJ_PATH}/src/main.c\n    ${PROJ_PATH}/src/stm32l4xx_it.c\n    ${PROJ_PATH}/src/syscalls.c\n    ${PROJ_PATH}/src/system_stm32l4xx.c)\n\nset(src_lwesp_SRCS \n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_ap.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_buff.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_conn.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_debug.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_dns.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_evt.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_input.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_int.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_mem.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_parser.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_pbuf.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_server.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_sntp.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_sta.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_threads.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_timeout.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_unicode.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_utils.c\n    ${PROJ_PATH}/../../../lwesp/src/lwesp/lwesp_wps.c)\n\nset(src_lwesp_api_SRCS \n    ${PROJ_PATH}/../../../lwesp/src/api/lwesp_netconn.c)\n\nset(src_lwesp_ll_SRCS \n    ${PROJ_PATH}/../../../lwesp/src/system/lwesp_ll_stm32l496g_discovery.c\n    ${PROJ_PATH}/../../../lwesp/src/system/lwesp_sys_cmsis_os.c)\n\nset(src_lwesp_snippets_SRCS \n    ${PROJ_PATH}/../../../snippets/examples_common_lwesp_callback_func.c\n    ${PROJ_PATH}/../../../snippets/netconn_client.c\n    ${PROJ_PATH}/../../../snippets/station_manager.c\n    ${PROJ_PATH}/../../../snippets/utils.c)\n\nset(src_startup_SRCS \n    ${PROJ_PATH}/STM32CubeIDE/startup/startup_stm32l496xx.s)\n\n#\n# Include directories\n#\nset(include_c_DIRS\n    ${PROJ_PATH}/inc\n    ${PROJ_PATH}/../../../snippets/include\n    ${PROJ_PATH}/../../../lwesp/src/include\n    ${PROJ_PATH}/../../../lwesp/src/include/system/port/cmsis_os\n    ${PROJ_PATH}/../../lib/st/CMSIS/Include\n    ${PROJ_PATH}/../../lib/st/STM32L4xx_HAL_Driver/Inc\n    ${PROJ_PATH}/../../lib/st/CMSIS/Device/ST/STM32L4xx/Include\n    ${PROJ_PATH}/../../lib/FreeRTOS/include\n    ${PROJ_PATH}/../../lib/FreeRTOS/CMSIS_RTOS_V2\n    ${PROJ_PATH}/../../lib/FreeRTOS/portable/GCC/ARM_CM4F\n)\nset(include_cxx_DIRS\n    \n)\nset(include_asm_DIRS\n    \n)\n\n#\n# Symbols definition\n#\nset(symbols_c_SYMB\n    \"__weak=__attribute__((weak))\"\n    \"__packed=__attribute__((__packed__))\"\n    \"USE_FULL_LL_DRIVER\"\n    \"STM32L496xx\"\n)\nset(symbols_cxx_SYMB\n    \"STM32F10X_MD\"\n    \"USE_STDPERIPH_DRIVER\"\n)\nset(symbols_asm_SYMB\n    \n)\n\n#\n# Link directories setup\n# Must be before executable is added\n#\nset(link_DIRS\n    \n)\nlink_directories(${EXECUTABLE} ${link_DIRS})\n\n#\n# Executable files\n#\nadd_executable(${EXECUTABLE} \n    ${src_freertos_SRCS}\n    ${src_stm32l4xx_hal_drivers_SRCS}\n    ${src_user_SRCS}\n    ${src_lwesp_SRCS}\n    ${src_lwesp_api_SRCS}\n    ${src_lwesp_ll_SRCS}\n    ${src_lwesp_snippets_SRCS}\n    ${src_startup_SRCS})\n\n#\n# Add linked libraries for linker\n#\nset(link_LIBS\n    \n)\ntarget_link_libraries(${EXECUTABLE} ${link_LIBS})\n\n#\n# Project symbols\n#\ntarget_compile_definitions(${EXECUTABLE} PRIVATE\n    # Language specific only\n    $<$<COMPILE_LANGUAGE:C>: ${symbols_c_SYMB}>\n    $<$<COMPILE_LANGUAGE:CXX>: ${symbols_cxx_SYMB}>\n    $<$<COMPILE_LANGUAGE:ASM>: ${symbols_asm_SYMB}>\n\n    # Configuration specific\n    $<$<CONFIG:Debug>:\n        DEBUG\n    >\n    $<$<CONFIG:Release>: >\n)\n\n#\n# Add include paths for each of the compiler\n#\ntarget_include_directories(${EXECUTABLE} PRIVATE\n    # Language specific only\n    $<$<COMPILE_LANGUAGE:C>: ${include_c_DIRS}>\n    $<$<COMPILE_LANGUAGE:CXX>: ${include_cxx_DIRS}>\n    $<$<COMPILE_LANGUAGE:ASM>: ${include_asm_DIRS}>\n\n    # Configuration specific\n    $<$<CONFIG:Debug>: >\n    $<$<CONFIG:Release>: >\n)\n\n# Compiler and linker options\ntarget_compile_options(${EXECUTABLE} PRIVATE\n    ${CPU_PARAMETERS}\n    -Wall\n    -Wextra\n    -Wpedantic\n    -Wno-unused-parameter\n    $<$<COMPILE_LANGUAGE:C>:\n\n    >\n    $<$<COMPILE_LANGUAGE:CXX>:\n        #-Wno-volatile\n        #-Wold-style-cast\n        #-Wuseless-cast\n        #-Wsuggest-override\n    >\n    $<$<COMPILE_LANGUAGE:ASM>:\n        -x assembler-with-cpp\n        -MMD\n        -MP\n    >\n    $<$<CONFIG:Debug>:\n        -Og -g3 -ggdb\n    >\n    $<$<CONFIG:Release>:\n        -Og -g0\n    >\n)\n\n# Setup linker parameters\ntarget_link_options(${EXECUTABLE} PRIVATE\n    -T${linker_script_SRC}\n    ${CPU_PARAMETERS}\n    -Wl,-Map=${CMAKE_PROJECT_NAME}.map\n    -u _printf_float              # STDIO float formatting support (remove if not used)\n    --specs=nosys.specs\n    -Wl,--start-group\n    -lc\n    -lm\n    -lstdc++\n    -lsupc++\n    -Wl,--end-group\n    -Wl,--print-memory-usage\n)\n\n# Execute post-build to print size\nadd_custom_command(TARGET ${EXECUTABLE} POST_BUILD\n    COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${EXECUTABLE}>\n)\n\n# Convert output to hex and binary\nadd_custom_command(TARGET ${EXECUTABLE} POST_BUILD\n    COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${EXECUTABLE}> ${EXECUTABLE}.hex\n)\n\n# Convert to bin file -> add conditional check?\nadd_custom_command(TARGET ${EXECUTABLE} POST_BUILD\n    COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:${EXECUTABLE}> ${EXECUTABLE}.bin\n)\n"
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    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/STM32CubeIDE/Debug_STM32L496AG_FLASH.ld",
    "content": "/*\n******************************************************************************\nFile:     Debug_STM32L496AG_FLASH.ld\nInfo:     Generated by Atollic TrueSTUDIO(R) 9.0.0   2018-04-12\n\nAbstract: Linker script for STM32L496AG device\n          Set heap size, stack size, stack location, memory areas and \n          sections according to application requirements. \n\nThe MIT License (MIT)\nCopyright (c) 2018 STMicroelectronics\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in all\ncopies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\nSOFTWARE.\n\n******************************************************************************\n*/\n\n/* Entry Point */\nENTRY(Reset_Handler)\n\n/* Highest address of the user mode stack */\n_estack = 0x20040000;    /* end of 256K RAM */\n\n/* Generate a link error if heap and stack don't fit into RAM */\n_Min_Heap_Size = 0;      /* required amount of heap  */\n_Min_Stack_Size = 0x400; /* required amount of stack */\n\n/* Specify the memory areas */\nMEMORY\n{\n  FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K\n  RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 256K\n  RAM2 (rw)       : ORIGIN = 0x10000000, LENGTH = 64K\n  MEMORY_B1 (rx)  : ORIGIN = 0x60000000, LENGTH = 0K\n}\n\n/* Define output sections */\nSECTIONS\n{\n  /* The startup code goes first into FLASH */\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) /* Startup code */\n    . = ALIGN(4);\n  } >FLASH\n\n  /* The program code and other data goes into FLASH */\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           /* .text sections (code) */\n    *(.text*)          /* .text* sections (code) */\n    *(.glue_7)         /* glue arm to thumb code */\n    *(.glue_7t)        /* glue thumb to arm code */\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        /* define a global symbols at end of code */\n  } >FLASH\n\n  /* Constant data goes into FLASH */\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  /* used by the startup to initialize data */\n  _sidata = LOADADDR(.data);\n\n  /* Initialized data sections goes into RAM, load LMA copy after code */\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        /* create a global symbol at data start */\n    *(.data)           /* .data sections */\n    *(.data*)          /* .data* sections */\n\n    . = ALIGN(4);\n    _edata = .;        /* define a global symbol at data end */\n  } >RAM AT> FLASH\n  \n  _siram2 = LOADADDR(.ram2);\n\n  /* RAM2 section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section, \n  * the startup code needs to be modified to copy the init-values.  \n  */\n  .ram2 :\n  {\n    . = ALIGN(4);\n    _sram2 = .;       /* create a global symbol at ram2 start */\n    *(.ram2)\n    *(.ram2*)\n    \n    . = ALIGN(4);\n    _eram2 = .;       /* create a global symbol at ram2 end */\n  } >RAM2 AT> FLASH\n\n  /* Uninitialized data section */\n  . = ALIGN(4);\n  .bss :\n  {\n    /* This is used by the startup in order to initialize the .bss secion */\n    _sbss = .;         /* define a global symbol at bss start */\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         /* define a global symbol at bss end */\n    __bss_end__ = _ebss;\n  } >RAM\n\n  /* User_heap_stack section, used to check that there is enough RAM left */\n  ._user_heap_stack :\n  {\n    . = ALIGN(4);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(4);\n  } >RAM\n\n  /* MEMORY_bank1 section, code must be located here explicitly            */\n  /* Example: extern int foo(void) __attribute__ ((section (\".mb1text\"))); */\n  .memory_b1_text :\n  {\n    *(.mb1text)        /* .mb1text sections (code) */\n    *(.mb1text*)       /* .mb1text* sections (code)  */\n    *(.mb1rodata)      /* read-only data (constants) */\n    *(.mb1rodata*)\n  } >MEMORY_B1\n\n  /* Remove information from the standard libraries */\n  /DISCARD/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n"
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  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/STM32CubeIDE/startup/startup_stm32l496xx.s",
    "content": "/**\n  ******************************************************************************\n  * @file      startup_stm32l496xx.s\n  * @author    MCD Application Team\n  * @brief     STM32L496xx devices vector table GCC toolchain.\n  *            This module performs:\n  *                - Set the initial SP\n  *                - Set the initial PC == Reset_Handler,\n  *                - Set the vector table entries with the exceptions ISR address,\n  *                - Configure the clock system  \n  *                - Branches to main in the C library (which eventually\n  *                  calls main()).\n  *            After Reset the Cortex-M4 processor is in Thread mode,\n  *            priority is Privileged, and the Stack is set to Main.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n  .syntax unified\n\t.cpu cortex-m4\n\t.fpu softvfp\n\t.thumb\n\n.global\tg_pfnVectors\n.global\tDefault_Handler\n\n/* start address for the initialization values of the .data section.\ndefined in linker script */\n.word\t_sidata\n/* start address for the .data section. defined in linker script */\n.word\t_sdata\n/* end address for the .data section. defined in linker script */\n.word\t_edata\n/* start address for the .bss section. defined in linker script */\n.word\t_sbss\n/* end address for the .bss section. defined in linker script */\n.word\t_ebss\n\n.equ  BootRAM,        0xF1E0F85F\n/**\n * @brief  This is the code that gets called when the processor first\n *          starts execution following a reset event. Only the absolutely\n *          necessary set is performed, after which the application\n *          supplied main() routine is called.\n * @param  None\n * @retval : None\n*/\n\n    .section\t.text.Reset_Handler\n\t.weak\tReset_Handler\n\t.type\tReset_Handler, %function\nReset_Handler:\n  ldr   sp, =_estack    /* Atollic update: set stack pointer */\n\n/* Copy the data segment initializers from flash to SRAM */\n  movs\tr1, #0\n  b\tLoopCopyDataInit\n\nCopyDataInit:\n\tldr\tr3, =_sidata\n\tldr\tr3, [r3, r1]\n\tstr\tr3, [r0, r1]\n\tadds\tr1, r1, #4\n\nLoopCopyDataInit:\n\tldr\tr0, =_sdata\n\tldr\tr3, =_edata\n\tadds\tr2, r0, r1\n\tcmp\tr2, r3\n\tbcc\tCopyDataInit\n\tldr\tr2, =_sbss\n\tb\tLoopFillZerobss\n/* Zero fill the bss segment. */\nFillZerobss:\n\tmovs\tr3, #0\n\tstr\tr3, [r2], #4\n\nLoopFillZerobss:\n\tldr\tr3, = _ebss\n\tcmp\tr2, r3\n\tbcc\tFillZerobss\n\n/* Call the clock system intitialization function.*/\n    bl  SystemInit\n/* Call static constructors */\n    bl __libc_init_array\n/* Call the application's entry point.*/\n\tbl\tmain\n\nLoopForever:\n    b LoopForever\n    \n.size\tReset_Handler, .-Reset_Handler\n\n/**\n * @brief  This is the code that gets called when the processor receives an\n *         unexpected interrupt.  This simply enters an infinite loop, preserving\n *         the system state for examination by a debugger.\n *\n * @param  None\n * @retval : None\n*/\n    .section\t.text.Default_Handler,\"ax\",%progbits\nDefault_Handler:\nInfinite_Loop:\n\tb\tInfinite_Loop\n\t.size\tDefault_Handler, .-Default_Handler\n/******************************************************************************\n*\n* The minimal vector table for a Cortex-M4.  Note that the proper constructs\n* must be placed on this to ensure that it ends up at physical address\n* 0x0000.0000.\n*\n******************************************************************************/\n \t.section\t.isr_vector,\"a\",%progbits\n\t.type\tg_pfnVectors, %object\n\t.size\tg_pfnVectors, .-g_pfnVectors\n\n\ng_pfnVectors:\n\t.word\t_estack\n\t.word\tReset_Handler\n\t.word\tNMI_Handler\n\t.word\tHardFault_Handler\n\t.word\tMemManage_Handler\n\t.word\tBusFault_Handler\n\t.word\tUsageFault_Handler\n\t.word\t0\n\t.word\t0\n\t.word\t0\n\t.word\t0\n\t.word\tSVC_Handler\n\t.word\tDebugMon_Handler\n\t.word\t0\n\t.word\tPendSV_Handler\n\t.word\tSysTick_Handler\n\t.word\tWWDG_IRQHandler\n\t.word\tPVD_PVM_IRQHandler\n\t.word\tTAMP_STAMP_IRQHandler\n\t.word\tRTC_WKUP_IRQHandler\n\t.word\tFLASH_IRQHandler\n\t.word\tRCC_IRQHandler\n\t.word\tEXTI0_IRQHandler\n\t.word\tEXTI1_IRQHandler\n\t.word\tEXTI2_IRQHandler\n\t.word\tEXTI3_IRQHandler\n\t.word\tEXTI4_IRQHandler\n\t.word\tDMA1_Channel1_IRQHandler\n\t.word\tDMA1_Channel2_IRQHandler\n\t.word\tDMA1_Channel3_IRQHandler\n\t.word\tDMA1_Channel4_IRQHandler\n\t.word\tDMA1_Channel5_IRQHandler\n\t.word\tDMA1_Channel6_IRQHandler\n\t.word\tDMA1_Channel7_IRQHandler\n\t.word\tADC1_2_IRQHandler\n\t.word\tCAN1_TX_IRQHandler\n\t.word\tCAN1_RX0_IRQHandler\n\t.word\tCAN1_RX1_IRQHandler\n\t.word\tCAN1_SCE_IRQHandler\n\t.word\tEXTI9_5_IRQHandler\n\t.word\tTIM1_BRK_TIM15_IRQHandler\n\t.word\tTIM1_UP_TIM16_IRQHandler\n\t.word\tTIM1_TRG_COM_TIM17_IRQHandler\n\t.word\tTIM1_CC_IRQHandler\n\t.word\tTIM2_IRQHandler\n\t.word\tTIM3_IRQHandler\n\t.word\tTIM4_IRQHandler\n\t.word\tI2C1_EV_IRQHandler\n\t.word\tI2C1_ER_IRQHandler\n\t.word\tI2C2_EV_IRQHandler\n\t.word\tI2C2_ER_IRQHandler\n\t.word\tSPI1_IRQHandler\n\t.word\tSPI2_IRQHandler\n\t.word\tUSART1_IRQHandler\n\t.word\tUSART2_IRQHandler\n\t.word\tUSART3_IRQHandler\n\t.word\tEXTI15_10_IRQHandler\n\t.word\tRTC_Alarm_IRQHandler\n\t.word\tDFSDM1_FLT3_IRQHandler\n\t.word\tTIM8_BRK_IRQHandler\n\t.word\tTIM8_UP_IRQHandler\n\t.word\tTIM8_TRG_COM_IRQHandler\n\t.word\tTIM8_CC_IRQHandler\n\t.word\tADC3_IRQHandler\n\t.word\tFMC_IRQHandler\n\t.word\tSDMMC1_IRQHandler\n\t.word\tTIM5_IRQHandler\n\t.word\tSPI3_IRQHandler\n\t.word\tUART4_IRQHandler\n\t.word\tUART5_IRQHandler\n\t.word\tTIM6_DAC_IRQHandler\n\t.word\tTIM7_IRQHandler\n\t.word\tDMA2_Channel1_IRQHandler\n\t.word\tDMA2_Channel2_IRQHandler\n\t.word\tDMA2_Channel3_IRQHandler\n\t.word\tDMA2_Channel4_IRQHandler\n\t.word\tDMA2_Channel5_IRQHandler\n\t.word\tDFSDM1_FLT0_IRQHandler\n\t.word\tDFSDM1_FLT1_IRQHandler\n\t.word\tDFSDM1_FLT2_IRQHandler\n\t.word\tCOMP_IRQHandler\n\t.word\tLPTIM1_IRQHandler\n\t.word\tLPTIM2_IRQHandler\n\t.word\tOTG_FS_IRQHandler\n\t.word\tDMA2_Channel6_IRQHandler\n\t.word\tDMA2_Channel7_IRQHandler\n\t.word\tLPUART1_IRQHandler\n\t.word\tQUADSPI_IRQHandler\n\t.word\tI2C3_EV_IRQHandler\n\t.word\tI2C3_ER_IRQHandler\n\t.word\tSAI1_IRQHandler\n\t.word\tSAI2_IRQHandler\n\t.word\tSWPMI1_IRQHandler\n\t.word\tTSC_IRQHandler\n\t.word\tLCD_IRQHandler\n\t.word 0\n\t.word\tRNG_IRQHandler\n\t.word\tFPU_IRQHandler\n\t.word\tCRS_IRQHandler\n\t.word\tI2C4_EV_IRQHandler\n\t.word\tI2C4_ER_IRQHandler\n\t.word\tDCMI_IRQHandler\n\t.word\tCAN2_TX_IRQHandler\n\t.word\tCAN2_RX0_IRQHandler\n\t.word\tCAN2_RX1_IRQHandler\n\t.word\tCAN2_SCE_IRQHandler\n\t.word\tDMA2D_IRQHandler  \n\n\n/*******************************************************************************\n*\n* Provide weak aliases for each Exception handler to the Default_Handler.\n* As they are weak aliases, any function with the same name will override\n* this definition.\n*\n*******************************************************************************/\n\n  .weak\tNMI_Handler\n\t.thumb_set NMI_Handler,Default_Handler\n\n  .weak\tHardFault_Handler\n\t.thumb_set HardFault_Handler,Default_Handler\n\n  .weak\tMemManage_Handler\n\t.thumb_set MemManage_Handler,Default_Handler\n\n  .weak\tBusFault_Handler\n\t.thumb_set BusFault_Handler,Default_Handler\n\n\t.weak\tUsageFault_Handler\n\t.thumb_set UsageFault_Handler,Default_Handler\n\n\t.weak\tSVC_Handler\n\t.thumb_set SVC_Handler,Default_Handler\n\n\t.weak\tDebugMon_Handler\n\t.thumb_set DebugMon_Handler,Default_Handler\n\n\t.weak\tPendSV_Handler\n\t.thumb_set PendSV_Handler,Default_Handler\n\n\t.weak\tSysTick_Handler\n\t.thumb_set SysTick_Handler,Default_Handler\n\n\t.weak\tWWDG_IRQHandler\n\t.thumb_set WWDG_IRQHandler,Default_Handler\n\n\t.weak\tPVD_PVM_IRQHandler\n\t.thumb_set PVD_PVM_IRQHandler,Default_Handler\n\n\t.weak\tTAMP_STAMP_IRQHandler\n\t.thumb_set TAMP_STAMP_IRQHandler,Default_Handler\n\n\t.weak\tRTC_WKUP_IRQHandler\n\t.thumb_set RTC_WKUP_IRQHandler,Default_Handler\n\n\t.weak\tFLASH_IRQHandler\n\t.thumb_set FLASH_IRQHandler,Default_Handler\n\n\t.weak\tRCC_IRQHandler\n\t.thumb_set RCC_IRQHandler,Default_Handler\n\n\t.weak\tEXTI0_IRQHandler\n\t.thumb_set EXTI0_IRQHandler,Default_Handler\n\n\t.weak\tEXTI1_IRQHandler\n\t.thumb_set EXTI1_IRQHandler,Default_Handler\n\n\t.weak\tEXTI2_IRQHandler\n\t.thumb_set EXTI2_IRQHandler,Default_Handler\n\n\t.weak\tEXTI3_IRQHandler\n\t.thumb_set EXTI3_IRQHandler,Default_Handler\n\n\t.weak\tEXTI4_IRQHandler\n\t.thumb_set EXTI4_IRQHandler,Default_Handler\n\n\t.weak\tDMA1_Channel1_IRQHandler\n\t.thumb_set DMA1_Channel1_IRQHandler,Default_Handler\n\n\t.weak\tDMA1_Channel2_IRQHandler\n\t.thumb_set DMA1_Channel2_IRQHandler,Default_Handler\n\n\t.weak\tDMA1_Channel3_IRQHandler\n\t.thumb_set DMA1_Channel3_IRQHandler,Default_Handler\n\n\t.weak\tDMA1_Channel4_IRQHandler\n\t.thumb_set DMA1_Channel4_IRQHandler,Default_Handler\n\n\t.weak\tDMA1_Channel5_IRQHandler\n\t.thumb_set DMA1_Channel5_IRQHandler,Default_Handler\n\n\t.weak\tDMA1_Channel6_IRQHandler\n\t.thumb_set DMA1_Channel6_IRQHandler,Default_Handler\n\n\t.weak\tDMA1_Channel7_IRQHandler\n\t.thumb_set DMA1_Channel7_IRQHandler,Default_Handler\n\n\t.weak\tADC1_2_IRQHandler\n\t.thumb_set ADC1_2_IRQHandler,Default_Handler\n\n\t.weak\tCAN1_TX_IRQHandler\n\t.thumb_set CAN1_TX_IRQHandler,Default_Handler\n\n\t.weak\tCAN1_RX0_IRQHandler\n\t.thumb_set CAN1_RX0_IRQHandler,Default_Handler\n\n\t.weak\tCAN1_RX1_IRQHandler\n\t.thumb_set CAN1_RX1_IRQHandler,Default_Handler\n\n\t.weak\tCAN1_SCE_IRQHandler\n\t.thumb_set CAN1_SCE_IRQHandler,Default_Handler\n\n\t.weak\tEXTI9_5_IRQHandler\n\t.thumb_set EXTI9_5_IRQHandler,Default_Handler\n\n\t.weak\tTIM1_BRK_TIM15_IRQHandler\n\t.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler\n\n\t.weak\tTIM1_UP_TIM16_IRQHandler\n\t.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler\n\n\t.weak\tTIM1_TRG_COM_TIM17_IRQHandler\n\t.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler\n\n\t.weak\tTIM1_CC_IRQHandler\n\t.thumb_set TIM1_CC_IRQHandler,Default_Handler\n\n\t.weak\tTIM2_IRQHandler\n\t.thumb_set TIM2_IRQHandler,Default_Handler\n\n\t.weak\tTIM3_IRQHandler\n\t.thumb_set TIM3_IRQHandler,Default_Handler\n\n\t.weak\tTIM4_IRQHandler\n\t.thumb_set TIM4_IRQHandler,Default_Handler\n\n\t.weak\tI2C1_EV_IRQHandler\n\t.thumb_set I2C1_EV_IRQHandler,Default_Handler\n\n\t.weak\tI2C1_ER_IRQHandler\n\t.thumb_set I2C1_ER_IRQHandler,Default_Handler\n\n\t.weak\tI2C2_EV_IRQHandler\n\t.thumb_set I2C2_EV_IRQHandler,Default_Handler\n\n\t.weak\tI2C2_ER_IRQHandler\n\t.thumb_set I2C2_ER_IRQHandler,Default_Handler\n\n\t.weak\tSPI1_IRQHandler\n\t.thumb_set SPI1_IRQHandler,Default_Handler\n\n\t.weak\tSPI2_IRQHandler\n\t.thumb_set SPI2_IRQHandler,Default_Handler\n\n\t.weak\tUSART1_IRQHandler\n\t.thumb_set USART1_IRQHandler,Default_Handler\n\n\t.weak\tUSART2_IRQHandler\n\t.thumb_set USART2_IRQHandler,Default_Handler\n\n\t.weak\tUSART3_IRQHandler\n\t.thumb_set USART3_IRQHandler,Default_Handler\n\n\t.weak\tEXTI15_10_IRQHandler\n\t.thumb_set EXTI15_10_IRQHandler,Default_Handler\n\n\t.weak\tRTC_Alarm_IRQHandler\n\t.thumb_set RTC_Alarm_IRQHandler,Default_Handler\n\n\t.weak\tDFSDM1_FLT3_IRQHandler\n\t.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler\n\n\t.weak\tTIM8_BRK_IRQHandler\n\t.thumb_set TIM8_BRK_IRQHandler,Default_Handler\n\n\t.weak\tTIM8_UP_IRQHandler\n\t.thumb_set TIM8_UP_IRQHandler,Default_Handler\n\n\t.weak\tTIM8_TRG_COM_IRQHandler\n\t.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler\n\n\t.weak\tTIM8_CC_IRQHandler\n\t.thumb_set TIM8_CC_IRQHandler,Default_Handler\n\n\t.weak\tADC3_IRQHandler\n\t.thumb_set ADC3_IRQHandler,Default_Handler\n\n\t.weak\tFMC_IRQHandler\n\t.thumb_set FMC_IRQHandler,Default_Handler\n\n\t.weak\tSDMMC1_IRQHandler\n\t.thumb_set SDMMC1_IRQHandler,Default_Handler\n\n\t.weak\tTIM5_IRQHandler\n\t.thumb_set TIM5_IRQHandler,Default_Handler\n\n\t.weak\tSPI3_IRQHandler\n\t.thumb_set SPI3_IRQHandler,Default_Handler\n\n\t.weak\tUART4_IRQHandler\n\t.thumb_set UART4_IRQHandler,Default_Handler\n\n\t.weak\tUART5_IRQHandler\n\t.thumb_set UART5_IRQHandler,Default_Handler\n\n\t.weak\tTIM6_DAC_IRQHandler\n\t.thumb_set TIM6_DAC_IRQHandler,Default_Handler\n\n\t.weak\tTIM7_IRQHandler\n\t.thumb_set TIM7_IRQHandler,Default_Handler\n\n\t.weak\tDMA2_Channel1_IRQHandler\n\t.thumb_set DMA2_Channel1_IRQHandler,Default_Handler\n\n\t.weak\tDMA2_Channel2_IRQHandler\n\t.thumb_set DMA2_Channel2_IRQHandler,Default_Handler\n\n\t.weak\tDMA2_Channel3_IRQHandler\n\t.thumb_set DMA2_Channel3_IRQHandler,Default_Handler\n\n\t.weak\tDMA2_Channel4_IRQHandler\n\t.thumb_set DMA2_Channel4_IRQHandler,Default_Handler\n\n\t.weak\tDMA2_Channel5_IRQHandler\n\t.thumb_set DMA2_Channel5_IRQHandler,Default_Handler\n\n\t.weak\tDFSDM1_FLT0_IRQHandler\n\t.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler\t\n\t\n\t.weak\tDFSDM1_FLT1_IRQHandler\n\t.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler\t\n\t\n\t.weak\tDFSDM1_FLT2_IRQHandler\n\t.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler\t\n\t\n\t.weak\tCOMP_IRQHandler\n\t.thumb_set COMP_IRQHandler,Default_Handler\n\t\n\t.weak\tLPTIM1_IRQHandler\n\t.thumb_set LPTIM1_IRQHandler,Default_Handler\n\t\n\t.weak\tLPTIM2_IRQHandler\n\t.thumb_set LPTIM2_IRQHandler,Default_Handler\t\n\t\n\t.weak\tOTG_FS_IRQHandler\n\t.thumb_set OTG_FS_IRQHandler,Default_Handler\t\n\t\n\t.weak\tDMA2_Channel6_IRQHandler\n\t.thumb_set DMA2_Channel6_IRQHandler,Default_Handler\t\n\t\n\t.weak\tDMA2_Channel7_IRQHandler\n\t.thumb_set DMA2_Channel7_IRQHandler,Default_Handler\t\n\t\n\t.weak\tLPUART1_IRQHandler\n\t.thumb_set LPUART1_IRQHandler,Default_Handler\t\n\t\n\t.weak\tQUADSPI_IRQHandler\n\t.thumb_set QUADSPI_IRQHandler,Default_Handler\t\n\t\n\t.weak\tI2C3_EV_IRQHandler\n\t.thumb_set I2C3_EV_IRQHandler,Default_Handler\t\n\t\n\t.weak\tI2C3_ER_IRQHandler\n\t.thumb_set I2C3_ER_IRQHandler,Default_Handler\t\n\t\n\t.weak\tSAI1_IRQHandler\n\t.thumb_set SAI1_IRQHandler,Default_Handler\n\t\n\t.weak\tSAI2_IRQHandler\n\t.thumb_set SAI2_IRQHandler,Default_Handler\n\t\n\t.weak\tSWPMI1_IRQHandler\n\t.thumb_set SWPMI1_IRQHandler,Default_Handler\n\t\n\t.weak\tTSC_IRQHandler\n\t.thumb_set TSC_IRQHandler,Default_Handler\n\t\n\t.weak\tLCD_IRQHandler\n\t.thumb_set LCD_IRQHandler,Default_Handler\n\t\n\t.weak\tRNG_IRQHandler\n\t.thumb_set RNG_IRQHandler,Default_Handler\n\t\n\t.weak\tFPU_IRQHandler\n\t.thumb_set FPU_IRQHandler,Default_Handler\n\t\n\t.weak\tCRS_IRQHandler\n\t.thumb_set CRS_IRQHandler,Default_Handler\t\n\t\n\t.weak\tI2C4_EV_IRQHandler\n\t.thumb_set I2C4_EV_IRQHandler,Default_Handler\n\t\n\t.weak\tI2C4_ER_IRQHandler\n\t.thumb_set I2C4_ER_IRQHandler,Default_Handler\n\t\n\t.weak\tDCMI_IRQHandler\n\t.thumb_set DCMI_IRQHandler,Default_Handler\n\t\n\t.weak\tCAN2_TX_IRQHandler\n\t.thumb_set CAN2_TX_IRQHandler,Default_Handler\n\t\n\t.weak\tCAN2_RX0_IRQHandler\n\t.thumb_set CAN2_RX0_IRQHandler,Default_Handler\n\t\n\t.weak\tCAN2_RX1_IRQHandler\n\t.thumb_set CAN2_RX1_IRQHandler,Default_Handler\n\t\n\t.weak\tCAN2_SCE_IRQHandler\n\t.thumb_set CAN2_SCE_IRQHandler,Default_Handler \n\t\n\t.weak\tDMA2D_IRQHandler\n\t.thumb_set FPU_IRQHandler,Default_Handler    \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/cmake/gcc-arm-none-eabi.cmake",
    "content": "set(CMAKE_SYSTEM_NAME               Generic)\nset(CMAKE_SYSTEM_PROCESSOR          arm)\n\n# Some default GCC settings\n# arm-none-eabi- must be part of path environment\nset(TOOLCHAIN_PREFIX                arm-none-eabi-)\nset(FLAGS                           \"-fdata-sections -ffunction-sections -Wl,--gc-sections\")\nset(CPP_FLAGS                       \"${FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics\")\n\nset(CMAKE_C_FLAGS                   ${FLAGS})\nset(CMAKE_CXX_FLAGS                 ${CPP_FLAGS})\n\nset(CMAKE_C_COMPILER                ${TOOLCHAIN_PREFIX}gcc)\nset(CMAKE_ASM_COMPILER              ${CMAKE_C_COMPILER})\nset(CMAKE_CXX_COMPILER              ${TOOLCHAIN_PREFIX}g++)\nset(CMAKE_OBJCOPY                   ${TOOLCHAIN_PREFIX}objcopy)\nset(CMAKE_SIZE                      ${TOOLCHAIN_PREFIX}size)\n\nset(CMAKE_EXECUTABLE_SUFFIX_ASM     \".elf\")\nset(CMAKE_EXECUTABLE_SUFFIX_C       \".elf\")\nset(CMAKE_EXECUTABLE_SUFFIX_CXX     \".elf\")\n\nset(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/inc/FreeRTOSConfig.h",
    "content": "/*\n    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\n    All rights reserved\n\n    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\n\n    This file is part of the FreeRTOS distribution.\n\n    FreeRTOS is free software; you can redistribute it and/or modify it under\n    the terms of the GNU General Public License (version 2) as published by the\n    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\n\n    ***************************************************************************\n    >>!   NOTE: The modification to the GPL is included to allow you to     !<<\n    >>!   distribute a combined work that includes FreeRTOS without being   !<<\n    >>!   obliged to provide the source code for proprietary components     !<<\n    >>!   outside of the FreeRTOS kernel.                                   !<<\n    ***************************************************************************\n\n    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\n    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\n    FOR A PARTICULAR PURPOSE.  Full license text is available on the following\n    link: http://www.freertos.org/a00114.html\n\n    ***************************************************************************\n     *                                                                       *\n     *    FreeRTOS provides completely free yet professionally developed,    *\n     *    robust, strictly quality controlled, supported, and cross          *\n     *    platform software that is more than just the market leader, it     *\n     *    is the industry's de facto standard.                               *\n     *                                                                       *\n     *    Help yourself get started quickly while simultaneously helping     *\n     *    to support the FreeRTOS project by purchasing a FreeRTOS           *\n     *    tutorial book, reference manual, or both:                          *\n     *    http://www.FreeRTOS.org/Documentation                              *\n     *                                                                       *\n    ***************************************************************************\n\n    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\n    the FAQ page \"My application does not run, what could be wrong?\".  Have you\n    defined configASSERT()?\n\n    http://www.FreeRTOS.org/support - In return for receiving this top quality\n    embedded software for free we request you assist our global community by\n    participating in the support forum.\n\n    http://www.FreeRTOS.org/training - Investing in training allows your team to\n    be as productive as possible as early as possible.  Now you can receive\n    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\n    Ltd, and the world's leading authority on the world's leading RTOS.\n\n    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\n    including FreeRTOS+Trace - an indispensable productivity tool, a DOS\n    compatible FAT file system, and our tiny thread aware UDP/IP stack.\n\n    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\n    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\n\n    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\n    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\n    licenses offer ticketed support, indemnification and commercial middleware.\n\n    http://www.SafeRTOS.com - High Integrity Systems also provide a safety\n    engineered and independently SIL3 certified version for use in safety and\n    mission critical applications that require provable dependability.\n\n    1 tab == 4 spaces!\n*/\n\n\n#ifndef FREERTOS_CONFIG_H\n#define FREERTOS_CONFIG_H\n\n/*-----------------------------------------------------------\n * Application specific definitions.\n *\n * These definitions should be adjusted for your particular hardware and\n * application requirements.\n *\n * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\n * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\n *\n * See http://www.freertos.org/a00110.html.\n *----------------------------------------------------------*/\n\n/* Ensure stdint is only used by the compiler, and not the assembler. */\n#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)\n #include <stdint.h>\n extern uint32_t SystemCoreClock;\n#endif\n\n#define configUSE_PREEMPTION                1\n#define configUSE_IDLE_HOOK                 0\n#define configUSE_TICK_HOOK                 0\n#define configCPU_CLOCK_HZ                  (SystemCoreClock)\n#define configTICK_RATE_HZ                  ((TickType_t)1000)\n#define configMAX_PRIORITIES                (7)\n#define configMINIMAL_STACK_SIZE            ((uint16_t)128)\n#define configTOTAL_HEAP_SIZE               ((size_t)(15 * 1024))\n#define configMAX_TASK_NAME_LEN             (16)\n#define configUSE_TRACE_FACILITY            1\n#define configUSE_16_BIT_TICKS              0\n#define configIDLE_SHOULD_YIELD             1\n#define configUSE_MUTEXES                   1\n#define configQUEUE_REGISTRY_SIZE           8\n#define configCHECK_FOR_STACK_OVERFLOW      0\n#define configUSE_RECURSIVE_MUTEXES         1\n#define configUSE_MALLOC_FAILED_HOOK        0\n#define configUSE_APPLICATION_TASK_TAG      0\n#define configUSE_COUNTING_SEMAPHORES       1\n#define configGENERATE_RUN_TIME_STATS       0\n#define configSUPPORT_STATIC_ALLOCATION     1\n\n/* Co-routine definitions. */\n#define configUSE_CO_ROUTINES               0\n#define configMAX_CO_ROUTINE_PRIORITIES     2\n\n/* Software timer definitions. */\n#define configUSE_TIMERS                    0\n#define configTIMER_TASK_PRIORITY           2\n#define configTIMER_QUEUE_LENGTH            10\n#define configTIMER_TASK_STACK_DEPTH        (configMINIMAL_STACK_SIZE * 2)\n\n/* Set the following definitions to 1 to include the API function, or zero\nto exclude the API function. */\n#define INCLUDE_vTaskPrioritySet            1\n#define INCLUDE_uxTaskPriorityGet           1\n#define INCLUDE_vTaskDelete                 1\n#define INCLUDE_vTaskCleanUpResources       0\n#define INCLUDE_vTaskSuspend                1\n#define INCLUDE_vTaskDelayUntil             0\n#define INCLUDE_vTaskDelay                  1\n#define INCLUDE_xTaskGetSchedulerState      1\n\n/* Cortex-M specific definitions. */\n#ifdef __NVIC_PRIO_BITS\n /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\n #define configPRIO_BITS                    __NVIC_PRIO_BITS\n#else\n #define configPRIO_BITS                    4        /* 15 priority levels */\n#endif\n\n/* The lowest interrupt priority that can be used in a call to a \"set priority\"\nfunction. */\n#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY             0x0F\n\n/* The highest interrupt priority that can be used by any interrupt service\nroutine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL\nINTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\nPRIORITY THAN THIS! (higher priorities are lower numeric values. */\n#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY        0x05\n\n/* Interrupt priorities used by the kernel port layer itself.  These are generic\nto all Cortex-M ports, and do not rely on any particular library functions. */\n#define configKERNEL_INTERRUPT_PRIORITY                     ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\n/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\nSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\n#define configMAX_SYSCALL_INTERRUPT_PRIORITY                ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\n \n/* Normal assert() semantics without relying on the provision of an assert.h\nheader file. */\n#define configASSERT( x )                                   if ((x) == 0) { taskDISABLE_INTERRUPTS(); for (;;) {} }\n \n/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\n   standard names. */\n#define vPortSVCHandler                                     SVC_Handler\n#define xPortPendSVHandler                                  PendSV_Handler\n\n/* IMPORTANT: This define MUST be commented when used with STM32Cube firmware, \n              to prevent overwriting SysTick_Handler defined within STM32Cube HAL */\n/* #define xPortSysTickHandler SysTick_Handler */\n\n#endif /* FREERTOS_CONFIG_H */\n\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/inc/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#define LWESP_CFG_NETCONN                     1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/inc/main.h",
    "content": "/**\n * \\file            main.h\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef __MAIN_H\n#define __MAIN_H\n\n#include \"stm32l4xx_ll_rcc.h\"\n#include \"stm32l4xx_ll_bus.h\"\n#include \"stm32l4xx_ll_system.h\"\n#include \"stm32l4xx_ll_exti.h\"\n#include \"stm32l4xx_ll_cortex.h\"\n#include \"stm32l4xx_ll_utils.h\"\n#include \"stm32l4xx_ll_pwr.h\"\n#include \"stm32l4xx_ll_dma.h\"\n#include \"stm32l4xx_ll_usart.h\"\n#include \"stm32l4xx.h\"\n#include \"stm32l4xx_ll_gpio.h\"\n#include <stdio.h>\n\n#ifndef NVIC_PRIORITYGROUP_0\n#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,\n                                                                 4 bits for subpriority */\n#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,\n                                                                 3 bits for subpriority */\n#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,\n                                                                 2 bits for subpriority */\n#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,\n                                                                 1 bit  for subpriority */\n#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,\n                                                                 0 bit  for subpriority */\n#endif\n\n/* ########################## Assert Selection ############################## */\n/**\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the\n  *        HAL drivers code\n  */\n/* #define USE_FULL_ASSERT    1U */\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\nvoid _Error_Handler(char *, int);\n\n#define Error_Handler() _Error_Handler(__FILE__, __LINE__)\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __MAIN_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/inc/stm32_assert.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32_assert.h\n  * @brief   STM32 assert file.\n  ******************************************************************************\n   ** This notice applies to any and all portions of this file\n  * that are not between comment pairs USER CODE BEGIN and\n  * USER CODE END. Other portions of this file, whether \n  * inserted by the user or by software development tools\n  * are owned by their respective copyright owners.\n  *\n  * COPYRIGHT(c) 2018 STMicroelectronics\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32_ASSERT_H\n#define __STM32_ASSERT_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Includes ------------------------------------------------------------------*/\n/* Exported macro ------------------------------------------------------------*/\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  The assert_param macro is used for function's parameters check.\n  * @param  expr: If expr is false, it calls assert_failed function\n  *         which reports the name of the source file and the source\n  *         line number of the call that failed.\n  *         If expr is true, it returns no value.\n  * @retval None\n  */\n  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\n/* Exported functions ------------------------------------------------------- */\n  void assert_failed(uint8_t* file, uint32_t line);\n#else\n  #define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32_ASSERT_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/inc/stm32l4xx_hal_conf.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32l4xx_hal_conf.h\n  * @author  MCD Application Team\n  * @brief   HAL configuration template file.\n  *          This file should be copied to the application folder and renamed\n  *          to stm32l4xx_hal_conf.h.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32L4xx_HAL_CONF_H\n#define __STM32L4xx_HAL_CONF_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/* ########################## Module Selection ############################## */\n/**\n  * @brief This is the list of modules to be used in the HAL driver\n  */\n#define HAL_MODULE_ENABLED\n#define HAL_ADC_MODULE_ENABLED\n#define HAL_CAN_MODULE_ENABLED\n#define HAL_COMP_MODULE_ENABLED\n#define HAL_CORTEX_MODULE_ENABLED\n#define HAL_CRC_MODULE_ENABLED\n#define HAL_CRYP_MODULE_ENABLED\n#define HAL_DAC_MODULE_ENABLED\n#define HAL_DCMI_MODULE_ENABLED\n#define HAL_DFSDM_MODULE_ENABLED\n#define HAL_DMA_MODULE_ENABLED\n#define HAL_DMA2D_MODULE_ENABLED\n#define HAL_DSI_MODULE_ENABLED\n#define HAL_FIREWALL_MODULE_ENABLED\n#define HAL_FLASH_MODULE_ENABLED\n#define HAL_GFXMMU_MODULE_ENABLED\n#define HAL_HASH_MODULE_ENABLED\n#define HAL_HCD_MODULE_ENABLED\n#define HAL_NAND_MODULE_ENABLED\n#define HAL_NOR_MODULE_ENABLED\n#define HAL_SRAM_MODULE_ENABLED\n#define HAL_GPIO_MODULE_ENABLED\n#define HAL_I2C_MODULE_ENABLED\n#define HAL_IRDA_MODULE_ENABLED\n#define HAL_IWDG_MODULE_ENABLED\n#define HAL_LCD_MODULE_ENABLED\n#define HAL_LPTIM_MODULE_ENABLED\n#define HAL_LTDC_MODULE_ENABLED\n#define HAL_OPAMP_MODULE_ENABLED\n#define HAL_OSPI_MODULE_ENABLED\n#define HAL_PCD_MODULE_ENABLED\n#define HAL_PWR_MODULE_ENABLED\n#define HAL_QSPI_MODULE_ENABLED\n#define HAL_RCC_MODULE_ENABLED\n#define HAL_RNG_MODULE_ENABLED\n#define HAL_RTC_MODULE_ENABLED\n#define HAL_SAI_MODULE_ENABLED\n#define HAL_SD_MODULE_ENABLED\n#define HAL_SMARTCARD_MODULE_ENABLED\n#define HAL_SMBUS_MODULE_ENABLED\n#define HAL_SPI_MODULE_ENABLED\n#define HAL_SWPMI_MODULE_ENABLED\n#define HAL_TIM_MODULE_ENABLED\n#define HAL_TSC_MODULE_ENABLED\n#define HAL_UART_MODULE_ENABLED\n#define HAL_USART_MODULE_ENABLED\n#define HAL_WWDG_MODULE_ENABLED\n\n\n/* ########################## Oscillator Values adaptation ####################*/\n/**\n  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSE is used as system clock source, directly or through the PLL).\n  */\n#if !defined  (HSE_VALUE)\n  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSE_STARTUP_TIMEOUT)\n  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */\n#endif /* HSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief Internal Multiple Speed oscillator (MSI) default value.\n  *        This value is the default MSI range value after Reset.\n  */\n#if !defined  (MSI_VALUE)\n  #define MSI_VALUE    ((uint32_t)4000000U) /*!< Value of the Internal oscillator in Hz*/\n#endif /* MSI_VALUE */\n\n/**\n  * @brief Internal High Speed oscillator (HSI) value.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSI is used as system clock source, directly or through the PLL).\n  */\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n  * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.\n  *        This internal oscillator is mainly dedicated to provide a high precision clock to\n  *        the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.\n  *        When the CRS is not used, the HSI48 RC oscillator runs on it default frequency\n  *        which is subject to manufacturing process variations.\n  */\n#if !defined  (HSI48_VALUE) \n  #define HSI48_VALUE   ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.\n                                               The real value my vary depending on manufacturing process variations.*/\n#endif /* HSI48_VALUE */\n\n/**\n  * @brief Internal Low Speed oscillator (LSI) value.\n  */\n#if !defined  (LSI_VALUE) \n  #define LSI_VALUE  ((uint32_t)32000U)      /*!< LSI Typical Value in Hz*/\n#endif /* LSI_VALUE */                       /*!< Value of the Internal Low Speed oscillator in Hz\n                                              The real value may vary depending on the variations\n                                              in voltage and temperature.*/\n/**\n  * @brief External Low Speed oscillator (LSE) value.\n  *        This value is used by the UART, RTC HAL module to compute the system frequency\n  */\n#if !defined  (LSE_VALUE)\n  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/\n#endif /* LSE_VALUE */\n\n#if !defined  (LSE_STARTUP_TIMEOUT)\n  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)  /*!< Time out for LSE start up, in ms */\n#endif /* HSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief External clock source for SAI1 peripheral\n  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source \n  *        frequency.\n  */\n#if !defined  (EXTERNAL_SAI1_CLOCK_VALUE)\n  #define EXTERNAL_SAI1_CLOCK_VALUE    ((uint32_t)48000U) /*!< Value of the SAI1 External clock source in Hz*/\n#endif /* EXTERNAL_SAI1_CLOCK_VALUE */\n\n/**\n  * @brief External clock source for SAI2 peripheral\n  *        This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source \n  *        frequency.\n  */\n#if !defined  (EXTERNAL_SAI2_CLOCK_VALUE)\n  #define EXTERNAL_SAI2_CLOCK_VALUE    ((uint32_t)48000U) /*!< Value of the SAI2 External clock source in Hz*/\n#endif /* EXTERNAL_SAI2_CLOCK_VALUE */\n\n/* Tip: To avoid modifying this file each time you need to use different HSE,\n   ===  you can define the HSE value in your toolchain compiler preprocessor. */\n\n/* ########################### System Configuration ######################### */\n/**\n  * @brief This is the HAL system configuration section\n  */\n#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */\n#define  TICK_INT_PRIORITY            ((uint32_t)0x0FU) /*!< tick interrupt priority */\n#define  USE_RTOS                     0U\n#define  PREFETCH_ENABLE              0U\n#define  INSTRUCTION_CACHE_ENABLE     1U\n#define  DATA_CACHE_ENABLE            1U\n\n/* ########################## Assert Selection ############################## */\n/**\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the\n  *        HAL drivers code\n  */\n/* #define USE_FULL_ASSERT               1U */\n\n/* ################## SPI peripheral configuration ########################## */\n\n/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\n * Activated: CRC code is present inside driver\n * Deactivated: CRC code cleaned from driver\n */\n\n#define USE_SPI_CRC                   1U\n\n/* Includes ------------------------------------------------------------------*/\n/**\n  * @brief Include module's header file\n  */\n\n#ifdef HAL_RCC_MODULE_ENABLED\n  #include \"stm32l4xx_hal_rcc.h\"\n#endif /* HAL_RCC_MODULE_ENABLED */\n\n#ifdef HAL_GPIO_MODULE_ENABLED\n  #include \"stm32l4xx_hal_gpio.h\"\n#endif /* HAL_GPIO_MODULE_ENABLED */\n\n#ifdef HAL_DMA_MODULE_ENABLED\n  #include \"stm32l4xx_hal_dma.h\"\n#endif /* HAL_DMA_MODULE_ENABLED */\n\n#ifdef HAL_DFSDM_MODULE_ENABLED\n  #include \"stm32l4xx_hal_dfsdm.h\"\n#endif /* HAL_DFSDM_MODULE_ENABLED */\n\n#ifdef HAL_CORTEX_MODULE_ENABLED\n  #include \"stm32l4xx_hal_cortex.h\"\n#endif /* HAL_CORTEX_MODULE_ENABLED */\n\n#ifdef HAL_ADC_MODULE_ENABLED\n  #include \"stm32l4xx_hal_adc.h\"\n#endif /* HAL_ADC_MODULE_ENABLED */\n\n#ifdef HAL_CAN_MODULE_ENABLED\n  #include \"stm32l4xx_hal_can.h\"\n#endif /* HAL_CAN_MODULE_ENABLED */\n\n#ifdef HAL_COMP_MODULE_ENABLED\n  #include \"stm32l4xx_hal_comp.h\"\n#endif /* HAL_COMP_MODULE_ENABLED */\n\n#ifdef HAL_CRC_MODULE_ENABLED\n  #include \"stm32l4xx_hal_crc.h\"\n#endif /* HAL_CRC_MODULE_ENABLED */\n\n#ifdef HAL_CRYP_MODULE_ENABLED\n  #include \"stm32l4xx_hal_cryp.h\"\n#endif /* HAL_CRYP_MODULE_ENABLED */\n\n#ifdef HAL_DAC_MODULE_ENABLED\n  #include \"stm32l4xx_hal_dac.h\"\n#endif /* HAL_DAC_MODULE_ENABLED */\n\n#ifdef HAL_DCMI_MODULE_ENABLED\n  #include \"stm32l4xx_hal_dcmi.h\"\n#endif /* HAL_DCMI_MODULE_ENABLED */\n\n#ifdef HAL_DMA2D_MODULE_ENABLED\n  #include \"stm32l4xx_hal_dma2d.h\"\n#endif /* HAL_DMA2D_MODULE_ENABLED */\n\n#ifdef HAL_DSI_MODULE_ENABLED\n  #include \"stm32l4xx_hal_dsi.h\"\n#endif /* HAL_DSI_MODULE_ENABLED */\n\n#ifdef HAL_FIREWALL_MODULE_ENABLED\n  #include \"stm32l4xx_hal_firewall.h\"\n#endif /* HAL_FIREWALL_MODULE_ENABLED */\n\n#ifdef HAL_FLASH_MODULE_ENABLED\n  #include \"stm32l4xx_hal_flash.h\"\n#endif /* HAL_FLASH_MODULE_ENABLED */\n\n#ifdef HAL_HASH_MODULE_ENABLED\n  #include \"stm32l4xx_hal_hash.h\"\n#endif /* HAL_HASH_MODULE_ENABLED */\n\n#ifdef HAL_SRAM_MODULE_ENABLED\n  #include \"stm32l4xx_hal_sram.h\"\n#endif /* HAL_SRAM_MODULE_ENABLED */\n\n#ifdef HAL_NOR_MODULE_ENABLED\n  #include \"stm32l4xx_hal_nor.h\"\n#endif /* HAL_NOR_MODULE_ENABLED */\n\n#ifdef HAL_NAND_MODULE_ENABLED\n  #include \"stm32l4xx_hal_nand.h\"\n#endif /* HAL_NAND_MODULE_ENABLED */\n\n#ifdef HAL_I2C_MODULE_ENABLED\n  #include \"stm32l4xx_hal_i2c.h\"\n#endif /* HAL_I2C_MODULE_ENABLED */\n\n#ifdef HAL_IWDG_MODULE_ENABLED\n  #include \"stm32l4xx_hal_iwdg.h\"\n#endif /* HAL_IWDG_MODULE_ENABLED */\n\n#ifdef HAL_LCD_MODULE_ENABLED\n  #include \"stm32l4xx_hal_lcd.h\"\n#endif /* HAL_LCD_MODULE_ENABLED */\n\n#ifdef HAL_LPTIM_MODULE_ENABLED\n  #include \"stm32l4xx_hal_lptim.h\"\n#endif /* HAL_LPTIM_MODULE_ENABLED */\n\n#ifdef HAL_LTDC_MODULE_ENABLED\n  #include \"stm32l4xx_hal_ltdc.h\"\n#endif /* HAL_LTDC_MODULE_ENABLED */\n\n#ifdef HAL_OPAMP_MODULE_ENABLED\n  #include \"stm32l4xx_hal_opamp.h\"\n#endif /* HAL_OPAMP_MODULE_ENABLED */\n\n#ifdef HAL_OSPI_MODULE_ENABLED\n  #include \"stm32l4xx_hal_ospi.h\"\n#endif /* HAL_OSPI_MODULE_ENABLED */\n\n#ifdef HAL_PWR_MODULE_ENABLED\n  #include \"stm32l4xx_hal_pwr.h\"\n#endif /* HAL_PWR_MODULE_ENABLED */\n\n#ifdef HAL_QSPI_MODULE_ENABLED\n  #include \"stm32l4xx_hal_qspi.h\"\n#endif /* HAL_QSPI_MODULE_ENABLED */\n\n#ifdef HAL_RNG_MODULE_ENABLED\n  #include \"stm32l4xx_hal_rng.h\"\n#endif /* HAL_RNG_MODULE_ENABLED */\n\n#ifdef HAL_RTC_MODULE_ENABLED\n  #include \"stm32l4xx_hal_rtc.h\"\n#endif /* HAL_RTC_MODULE_ENABLED */\n\n#ifdef HAL_SAI_MODULE_ENABLED\n  #include \"stm32l4xx_hal_sai.h\"\n#endif /* HAL_SAI_MODULE_ENABLED */\n\n#ifdef HAL_SD_MODULE_ENABLED\n  #include \"stm32l4xx_hal_sd.h\"\n#endif /* HAL_SD_MODULE_ENABLED */\n\n#ifdef HAL_SMBUS_MODULE_ENABLED\n  #include \"stm32l4xx_hal_smbus.h\"\n#endif /* HAL_SMBUS_MODULE_ENABLED */\n\n#ifdef HAL_SPI_MODULE_ENABLED\n  #include \"stm32l4xx_hal_spi.h\"\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n#ifdef HAL_SWPMI_MODULE_ENABLED\n  #include \"stm32l4xx_hal_swpmi.h\"\n#endif /* HAL_SWPMI_MODULE_ENABLED */\n\n#ifdef HAL_TIM_MODULE_ENABLED\n  #include \"stm32l4xx_hal_tim.h\"\n#endif /* HAL_TIM_MODULE_ENABLED */\n\n#ifdef HAL_TSC_MODULE_ENABLED\n  #include \"stm32l4xx_hal_tsc.h\"\n#endif /* HAL_TSC_MODULE_ENABLED */\n\n#ifdef HAL_UART_MODULE_ENABLED\n  #include \"stm32l4xx_hal_uart.h\"\n#endif /* HAL_UART_MODULE_ENABLED */\n\n#ifdef HAL_USART_MODULE_ENABLED\n  #include \"stm32l4xx_hal_usart.h\"\n#endif /* HAL_USART_MODULE_ENABLED */\n\n#ifdef HAL_IRDA_MODULE_ENABLED\n  #include \"stm32l4xx_hal_irda.h\"\n#endif /* HAL_IRDA_MODULE_ENABLED */\n\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\n  #include \"stm32l4xx_hal_smartcard.h\"\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\n\n#ifdef HAL_WWDG_MODULE_ENABLED\n  #include \"stm32l4xx_hal_wwdg.h\"\n#endif /* HAL_WWDG_MODULE_ENABLED */\n\n#ifdef HAL_PCD_MODULE_ENABLED\n  #include \"stm32l4xx_hal_pcd.h\"\n#endif /* HAL_PCD_MODULE_ENABLED */\n\n#ifdef HAL_HCD_MODULE_ENABLED\n  #include \"stm32l4xx_hal_hcd.h\"\n#endif /* HAL_HCD_MODULE_ENABLED */\n\n#ifdef HAL_GFXMMU_MODULE_ENABLED\n  #include \"stm32l4xx_hal_gfxmmu.h\"\n#endif /* HAL_GFXMMU_MODULE_ENABLED */\n\n/* Exported macro ------------------------------------------------------------*/\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  The assert_param macro is used for function's parameters check.\n  * @param  expr: If expr is false, it calls assert_failed function\n  *         which reports the name of the source file and the source\n  *         line number of the call that failed.\n  *         If expr is true, it returns no value.\n  * @retval None\n  */\n  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))\n/* Exported functions ------------------------------------------------------- */\n  void assert_failed(char *file, uint32_t line);\n#else\n  #define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32L4xx_HAL_CONF_H */\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/inc/stm32l4xx_it.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f7xx_it.h\n  * @brief   This file contains the headers of the interrupt handlers.\n  ******************************************************************************\n  *\n  * COPYRIGHT(c) 2018 STMicroelectronics\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F7xx_IT_H\n#define __STM32F7xx_IT_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions ------------------------------------------------------- */\n\nvoid NMI_Handler(void);\nvoid HardFault_Handler(void);\nvoid MemManage_Handler(void);\nvoid BusFault_Handler(void);\nvoid UsageFault_Handler(void);\nvoid SVC_Handler(void);\nvoid DebugMon_Handler(void);\nvoid PendSV_Handler(void);\nvoid SysTick_Handler(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F7xx_IT_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/src/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#include \"main.h\"\n#include \"cmsis_os.h\"\n\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"netconn_client.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\nstatic void LL_Init(void);\nvoid SystemClock_Config(void);\nstatic void USART_Printf_Init(void);\n\nstatic void init_thread(void* arg);\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    LL_Init();                                  /* Reset of all peripherals, initializes the Flash interface and the Systick. */\n    SystemClock_Config();                       /* Configure the system clock */\n    USART_Printf_Init();                        /* Init USART for printf */\n\n    printf(\"Application running on STM32L496G-Discovery!\\r\\n\");\n\n    /* Initialize, create first thread and start kernel */\n    osKernelInitialize();\n    const osThreadAttr_t attr = {\n            .stack_size = 512\n    };\n    osThreadNew(init_thread, NULL, &attr);\n    osKernelStart();\n\n    while (1) {}\n}\n\n/**\n * \\brief           Initialization thread\n * \\param[in]       arg: Thread argument\n */\nstatic void\ninit_thread(void* arg) {\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Continuously try to connect to WIFI network\n     * but only in case device is not already connected\n     */\n    while (1) {\n        if (!lwesp_sta_is_joined()) {\n            /*\n             * Connect to access point.\n             *\n             * Try unlimited time until access point accepts us.\n             * Check for station_manager.c to define preferred access points ESP should connect to\n             */\n            station_manager_connect_to_preferred_access_point(1);\n        }\n        osDelay(1000);\n    }\n}\n\n/**\n * \\brief           Low-Layer initialization\n */\nstatic void\nLL_Init(void) {\n    LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);\n    LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);\n\n    NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\n    NVIC_SetPriority(MemoryManagement_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(BusFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(UsageFault_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(SVCall_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(DebugMonitor_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));\n    NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));\n}\n\n/**\n * \\brief           System clock configuration\n */\nvoid\nSystemClock_Config(void) {\n    /* Configure flash latency */\n    LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);\n    if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) {\n        while (1) {}\n    }\n\n    /* Set voltage scaling */\n    LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);\n\n    /* Enable MSI */\n    LL_RCC_MSI_Enable();\n    while (LL_RCC_MSI_IsReady() != 1) {}\n    LL_RCC_MSI_EnableRangeSelection();\n    LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_6);\n    LL_RCC_MSI_SetCalibTrimming(0);\n\n    /* Configure PLL */\n    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_MSI, LL_RCC_PLLM_DIV_1, 40, LL_RCC_PLLR_DIV_2);\n    LL_RCC_PLL_EnableDomain_SYS();\n    LL_RCC_PLL_Enable();\n    while (LL_RCC_PLL_IsReady() != 1) {}\n\n    /* Configure system clock to PLL */\n    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);\n    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}\n\n    /* Set prescalers */\n    LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);\n    LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);\n    LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);\n\n    /* SysTick_IRQn interrupt configuration */\n    LL_Init1msTick(80000000);\n    LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);\n    LL_SetSystemCoreClock(80000000);\n    NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));\n    LL_SYSTICK_EnableIT();\n}\n\n/**\n * \\brief           Init USART2 for printf output\n */\nstatic void\nUSART_Printf_Init(void) {\n    LL_USART_InitTypeDef USART_InitStruct;\n    LL_GPIO_InitTypeDef GPIO_InitStruct;\n\n    /* Peripheral clock enable */\n    LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);\n    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);\n    LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);\n\n    /*\n     * USART2 GPIO Configuration\n     *\n     * PA2  ------> USART2_TX\n     * PD6  ------> USART2_RX\n     */\n    GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;\n    GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;\n    GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;\n    GPIO_InitStruct.Alternate = LL_GPIO_AF_7;\n\n    GPIO_InitStruct.Pin = LL_GPIO_PIN_2;\n    LL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = LL_GPIO_PIN_6;\n    LL_GPIO_Init(GPIOD, &GPIO_InitStruct);\n\n    USART_InitStruct.BaudRate = 921600;\n    USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;\n    USART_InitStruct.StopBits = LL_USART_STOPBITS_1;\n    USART_InitStruct.Parity = LL_USART_PARITY_NONE;\n    USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;\n    USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;\n    USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;\n    LL_USART_Init(USART2, &USART_InitStruct);\n\n    LL_USART_ConfigAsyncMode(USART2);           /* Configure USART in async mode */\n    LL_USART_Enable(USART2);                    /* Enable USART */\n}\n\n/**\n * \\brief           Printf character handler\n * \\param[in]       ch: Character to send\n * \\param[in]       f: File pointer\n * \\return          Written character\n */\n#ifdef __GNUC__\nint __io_putchar(int ch) {\n#else\nint fputc(int ch, FILE* fil) {\n#endif\n    LL_USART_TransmitData8(USART2, (uint8_t)ch);\n    while (!LL_USART_IsActiveFlag_TXE(USART2)) {}\n    return ch;\n}\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/src/stm32l4xx_it.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f7xx_it.c\n  * @brief   Interrupt Service Routines.\n  ******************************************************************************\n  *\n  * COPYRIGHT(c) 2018 STMicroelectronics\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32l4xx.h\"\n#include \"stm32l4xx_it.h\"\n\n#include \"cmsis_os.h\"\n\n/******************************************************************************/\n/*            Cortex-M4 Processor Interruption and Exception Handlers         */ \n/******************************************************************************/\n\n/**\n * \\brief           This function handles Non maskable interrupt.\n */\nvoid NMI_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Hard fault interrupt.\n */\nvoid\nHardFault_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Mem manage interrupt.\n */\nvoid\nMemManage_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Bus fault interrupt.\n */\nvoid\nBusFault_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Usage fault interrupt.\n */\nvoid\nUsageFault_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Debug monitor interrupt.\n */\nvoid\nDebugMon_Handler(void) {\n    while (1) {\n        \n    }\n}\n\n/**\n * \\brief           This function handles Systick interrupt.\n */\nvoid\nSysTick_Handler(void) {\n    extern void xPortSysTickHandler(void);\n    xPortSysTickHandler();\n}\n\n/******************************************************************************/\n/* STM32L4xx Peripheral Interrupt Handlers                                    */\n/* Add here the Interrupt Handlers for the used peripherals.                  */\n/* For the available peripheral interrupt handler names,                      */\n/* please refer to the startup file (startup_stm32l4xx.s).                    */\n/******************************************************************************/\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/src/syscalls.c",
    "content": "/* Support files for GNU libc.  Files in the system namespace go here.\n   Files in the C namespace (ie those that do not start with an\n   underscore) go in .c.  */\n\n#include <_ansi.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/fcntl.h>\n#include <stdio.h>\n#include <string.h>\n#include <time.h>\n#include <sys/time.h>\n#include <sys/times.h>\n#include <errno.h>\n#include <reent.h>\n#include <unistd.h>\n#include <sys/wait.h>\n\n#define FreeRTOS\n#define MAX_STACK_SIZE 0x2000\n\nextern int __io_putchar(int ch) __attribute__((weak));\nextern int __io_getchar(void) __attribute__((weak));\n\n#ifndef FreeRTOS\n  register char * stack_ptr asm(\"sp\");\n#endif\n\ncaddr_t _sbrk(int incr)\n{\n\textern char end asm(\"end\");\n\tstatic char *heap_end;\n\tchar *prev_heap_end,*min_stack_ptr;\n\n\tif (heap_end == 0)\n\t\theap_end = &end;\n\n\tprev_heap_end = heap_end;\n\n#ifdef FreeRTOS\n\t/* Use the NVIC offset register to locate the main stack pointer. */\n\tmin_stack_ptr = (char*)(*(unsigned int *)*(unsigned int *)0xE000ED08);\n\t/* Locate the STACK bottom address */\n\tmin_stack_ptr -= MAX_STACK_SIZE;\n\n\tif (heap_end + incr > min_stack_ptr)\n#else\n\tif (heap_end + incr > stack_ptr)\n#endif\n\t{\n//\t\twrite(1, \"Heap and stack collision\\n\", 25);\n//\t\tabort();\n\t\terrno = ENOMEM;\n\t\treturn (caddr_t) -1;\n\t}\n\n\theap_end += incr;\n\n\treturn (caddr_t) prev_heap_end;\n}\n\n/*\n * _gettimeofday primitive (Stub function)\n * */\nint _gettimeofday (struct timeval * tp, struct timezone * tzp)\n{\n  /* Return fixed data for the timezone.  */\n  if (tzp)\n    {\n      tzp->tz_minuteswest = 0;\n      tzp->tz_dsttime = 0;\n    }\n\n  return 0;\n}\nvoid initialise_monitor_handles()\n{\n}\n\nint _getpid(void)\n{\n\treturn 1;\n}\n\nint _kill(int pid, int sig)\n{\n\terrno = EINVAL;\n\treturn -1;\n}\n\nvoid _exit (int status)\n{\n\t_kill(status, -1);\n\twhile (1) {}\n}\n\nint _write(int file, char *ptr, int len)\n{\n    int DataIdx;\n\n    for (DataIdx = 0; DataIdx < len; DataIdx++) {\n        __io_putchar( *ptr++ );\n    }\n    return len;\n}\n\nint _close(int file)\n{\n\treturn -1;\n}\n\nint _fstat(int file, struct stat *st)\n{\n\tst->st_mode = S_IFCHR;\n\treturn 0;\n}\n\nint _isatty(int file)\n{\n\treturn 1;\n}\n\nint _lseek(int file, int ptr, int dir)\n{\n\treturn 0;\n}\n\nint _read(int file, char *ptr, int len)\n{\n\tint DataIdx;\n\n\tfor (DataIdx = 0; DataIdx < len; DataIdx++)\n\t{\n\t  *ptr++ = __io_getchar();\n\t}\n\n   return len;\n}\n\nint _open(char *path, int flags, ...)\n{\n\t/* Pretend like we always fail */\n\treturn -1;\n}\n\nint _wait(int *status)\n{\n\terrno = ECHILD;\n\treturn -1;\n}\n\nint _unlink(char *name)\n{\n\terrno = ENOENT;\n\treturn -1;\n}\n\nint _times(struct tms *buf)\n{\n\treturn -1;\n}\n\nint _stat(char *file, struct stat *st)\n{\n\tst->st_mode = S_IFCHR;\n\treturn 0;\n}\n\nint _link(char *old, char *new)\n{\n\terrno = EMLINK;\n\treturn -1;\n}\n\nint _fork(void)\n{\n\terrno = EAGAIN;\n\treturn -1;\n}\n\nint _execve(char *name, char **argv, char **env)\n{\n\terrno = ENOMEM;\n\treturn -1;\n}\n"
  },
  {
    "path": "examples/stm32/netconn_client_rtos_stm32l496g_discovery/src/system_stm32l4xx.c",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32l4xx.c\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File\n  *\n  *   This file provides two functions and one global variable to be called from\n  *   user application:\n  *      - SystemInit(): This function is called at startup just after reset and\n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32l4xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\n  *                                  by the user application to setup the SysTick\n  *                                  timer or configure other parameters.\n  *\n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  *   After each device reset the MSI (4 MHz) is used as system clock source.\n  *   Then SystemInit() function is called, in \"startup_stm32l4xx.s\" file, to\n  *   configure the system clock before to branch to main program.\n  *\n  *   This file configures the system clock as follows:\n  *=============================================================================\n  *-----------------------------------------------------------------------------\n  *        System Clock source                    | MSI\n  *-----------------------------------------------------------------------------\n  *        SYSCLK(Hz)                             | 4000000\n  *-----------------------------------------------------------------------------\n  *        HCLK(Hz)                               | 4000000\n  *-----------------------------------------------------------------------------\n  *        AHB Prescaler                          | 1\n  *-----------------------------------------------------------------------------\n  *        APB1 Prescaler                         | 1\n  *-----------------------------------------------------------------------------\n  *        APB2 Prescaler                         | 1\n  *-----------------------------------------------------------------------------\n  *        PLL_M                                  | 1\n  *-----------------------------------------------------------------------------\n  *        PLL_N                                  | 8\n  *-----------------------------------------------------------------------------\n  *        PLL_P                                  | 7\n  *-----------------------------------------------------------------------------\n  *        PLL_Q                                  | 2\n  *-----------------------------------------------------------------------------\n  *        PLL_R                                  | 2\n  *-----------------------------------------------------------------------------\n  *        PLLSAI1_P                              | NA\n  *-----------------------------------------------------------------------------\n  *        PLLSAI1_Q                              | NA\n  *-----------------------------------------------------------------------------\n  *        PLLSAI1_R                              | NA\n  *-----------------------------------------------------------------------------\n  *        PLLSAI2_P                              | NA\n  *-----------------------------------------------------------------------------\n  *        PLLSAI2_Q                              | NA\n  *-----------------------------------------------------------------------------\n  *        PLLSAI2_R                              | NA\n  *-----------------------------------------------------------------------------\n  *        Require 48MHz for USB OTG FS,          | Disabled\n  *        SDIO and RNG clock                     |\n  *-----------------------------------------------------------------------------\n  *=============================================================================\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32l4xx_system\n  * @{\n  */\n\n/** @addtogroup STM32L4xx_System_Private_Includes\n  * @{\n  */\n\n#include \"stm32l4xx.h\"\n\n#if !defined  (HSE_VALUE)\n  #define HSE_VALUE    8000000U  /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (MSI_VALUE)\n  #define MSI_VALUE    4000000U  /*!< Value of the Internal oscillator in Hz*/\n#endif /* MSI_VALUE */\n\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    16000000U /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Private_Defines\n  * @{\n  */\n\n/************************* Miscellaneous Configuration ************************/\n/*!< Uncomment the following line if you need to relocate your vector Table in\n     Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.\n                                   This value must be a multiple of 0x200. */\n/******************************************************************************/\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Private_Variables\n  * @{\n  */\n  /* The SystemCoreClock variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\n  uint32_t SystemCoreClock = 4000000U;\n\n  const uint8_t  AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};\n  const uint8_t  APBPrescTable[8] =  {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};\n  const uint32_t MSIRangeTable[12] = {100000U,   200000U,   400000U,   800000U,  1000000U,  2000000U, \\\n                                      4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32L4xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system.\n  * @param  None\n  * @retval None\n  */\n\nvoid SystemInit(void)\n{\n  /* FPU settings ------------------------------------------------------------*/\n  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\n    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */\n  #endif\n\n  /* Reset the RCC clock configuration to the default reset state ------------*/\n  /* Set MSION bit */\n  RCC->CR |= RCC_CR_MSION;\n\n  /* Reset CFGR register */\n  RCC->CFGR = 0x00000000U;\n\n  /* Reset HSEON, CSSON , HSION, and PLLON bits */\n  RCC->CR &= 0xEAF6FFFFU;\n\n  /* Reset PLLCFGR register */\n  RCC->PLLCFGR = 0x00001000U;\n\n  /* Reset HSEBYP bit */\n  RCC->CR &= 0xFFFBFFFFU;\n\n  /* Disable all interrupts */\n  RCC->CIER = 0x00000000U;\n\n  /* Configure the Vector Table location add offset address ------------------*/\n#ifdef VECT_TAB_SRAM\n  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#else\n  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\n#endif\n}\n\n/**\n  * @brief  Update SystemCoreClock variable according to Clock Register Values.\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *\n  * @note   Each time the core clock (HCLK) changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.\n  *\n  * @note   - The system frequency computed by this function is not the real\n  *           frequency in the chip. It is calculated based on the predefined\n  *           constant and the selected clock source:\n  *\n  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)\n  *\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)\n  *\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)\n  *\n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)\n  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.\n  *\n  *         (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value\n  *             4 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.\n  *\n  *         (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value\n  *              16 MHz) but the real value may vary depending on the variations\n  *              in voltage and temperature.\n  *\n  *         (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value\n  *              8 MHz), user has to ensure that HSE_VALUE is same as the real\n  *              frequency of the crystal used. Otherwise, this function may\n  *              have wrong result.\n  *\n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  *\n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate(void)\n{\n  uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U;\n\n  /* Get MSI Range frequency--------------------------------------------------*/\n  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)\n  { /* MSISRANGE from RCC_CSR applies */\n    msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;\n  }\n  else\n  { /* MSIRANGE from RCC_CR applies */\n    msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;\n  }\n  /*MSI frequency range in HZ*/\n  msirange = MSIRangeTable[msirange];\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  switch (RCC->CFGR & RCC_CFGR_SWS)\n  {\n    case 0x00:  /* MSI used as system clock source */\n      SystemCoreClock = msirange;\n      break;\n\n    case 0x04:  /* HSI used as system clock source */\n      SystemCoreClock = HSI_VALUE;\n      break;\n\n    case 0x08:  /* HSE used as system clock source */\n      SystemCoreClock = HSE_VALUE;\n      break;\n\n    case 0x0C:  /* PLL used as system clock  source */\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN\n         SYSCLK = PLL_VCO / PLLR\n         */\n      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\n      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;\n\n      switch (pllsource)\n      {\n        case 0x02:  /* HSI used as PLL clock source */\n          pllvco = (HSI_VALUE / pllm);\n          break;\n\n        case 0x03:  /* HSE used as PLL clock source */\n          pllvco = (HSE_VALUE / pllm);\n          break;\n\n        default:    /* MSI used as PLL clock source */\n          pllvco = (msirange / pllm);\n          break;\n      }\n      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);\n      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;\n      SystemCoreClock = pllvco/pllr;\n      break;\n\n    default:\n      SystemCoreClock = msirange;\n      break;\n  }\n  /* Compute HCLK clock frequency --------------------------------------------*/\n  /* Get HCLK prescaler */\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];\n  /* HCLK clock frequency */\n  SystemCoreClock >>= tmp;\n}\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "examples/win32/.vscode/c_cpp_properties.json",
    "content": "{\n    \"version\": 4,\n    \"configurations\": [\n        {\n            /*\n             * Full configuration is provided by CMake plugin for vscode,\n             * that shall be installed by user\n             */\n            \"name\": \"Win32\",\n            \"intelliSenseMode\": \"${default}\",\n            \"configurationProvider\": \"ms-vscode.cmake-tools\"\n        }\n    ]\n}"
  },
  {
    "path": "examples/win32/.vscode/extensions.json",
    "content": "{\n    \"recommendations\": [\n        \"ms-vscode.cpptools\",\n        \"ms-vscode.cmake-tools\",\n        \"twxs.cmake\",\n    ]\n}"
  },
  {
    "path": "examples/win32/.vscode/launch.json",
    "content": "{\n    // Use IntelliSense to learn about possible attributes.\n    // Hover to view descriptions of existing attributes.\n    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387\n    \"version\": \"0.2.0\",\n    \"configurations\": [\n        {\n            \"name\": \"(Windows) Launch\",\n            \"type\": \"cppdbg\",\n            \"request\": \"launch\",\n            \"program\": \"${command:cmake.launchTargetPath}\",\n            \"miDebuggerPath\": \"c:\\\\msys64\\\\mingw64\\\\bin\\\\gdb.exe\",\n            \"args\": [],\n            \"stopAtEntry\": false,\n            \"cwd\": \"${fileDirname}\",\n            \"environment\": []\n        }\n    ]\n}"
  },
  {
    "path": "examples/win32/.vscode/settings.json",
    "content": "{\n    \"files.associations\": {\n        \"lwevt_types.h\": \"c\",\n        \"lwevt_type.h\": \"c\",\n        \"lwevt.h\": \"c\",\n        \"string.h\": \"c\",\n        \"lwevt_opt.h\": \"c\",\n        \"cli.h\": \"c\",\n        \"windows.h\": \"c\",\n        \"lwesp_private.h\": \"c\"\n    },\n    \"esbonio.sphinx.confDir\": \"\"\n}"
  },
  {
    "path": "examples/win32/.vscode/tasks.json",
    "content": "{\n\t\"version\": \"2.0.0\",\n\t\"tasks\": [\n        {\n            \"type\": \"cppbuild\",\n            \"label\": \"Build project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"-j\", \"8\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": [\"$gcc\"],\n            \"group\": {\n                \"kind\": \"build\",\n                \"isDefault\": true\n            }\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Re-build project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"--clean-first\", \"-v\", \"-j\", \"8\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": [\"$gcc\"],\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Clean project\",\n            \"command\": \"cmake\",\n            \"args\": [\"--build\", \"${command:cmake.buildDirectory}\", \"--target\", \"clean\"],\n            \"options\": {\n                \"cwd\": \"${workspaceFolder}\"\n            },\n            \"problemMatcher\": []\n        },\n        {\n            \"type\": \"shell\",\n            \"label\": \"Run application\",\n            \"command\": \"${command:cmake.launchTargetPath}\",\n            \"args\": [],\n            \"problemMatcher\": [],\n        }\n    ]\n}"
  },
  {
    "path": "examples/win32/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.22)\n\n# Setup project\nproject(${PROJECT_NAME})\nadd_executable(${PROJECT_NAME})\nmessage(\"Project name: ${PROJECT_NAME}\")\n\n# Add source files\ntarget_sources(${PROJECT_NAME} PUBLIC\n    ${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}/main.c\n\n    # Port\n    ${CMAKE_CURRENT_LIST_DIR}/../../lwesp/src/system/lwesp_sys_win32.c\n    ${CMAKE_CURRENT_LIST_DIR}/../../lwesp/src/system/lwesp_ll_win32.c\n\n    # Snippets\n    ${CMAKE_CURRENT_LIST_DIR}/../../snippets/utils.c\n    ${CMAKE_CURRENT_LIST_DIR}/../../snippets/station_manager.c\n    ${CMAKE_CURRENT_LIST_DIR}/../../snippets/examples_common_lwesp_callback_func.c\n)\n\n# Add include paths\ntarget_include_directories(${PROJECT_NAME} PUBLIC\n    ${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}/\n\n    # Port\n    ${CMAKE_CURRENT_LIST_DIR}/../../lwesp/src/include/system/port/win32\n\n    # Snippets\n    ${CMAKE_CURRENT_LIST_DIR}/../../snippets/include\n)\n\n# Compilation definition information\ntarget_compile_definitions(${PROJECT_NAME} PUBLIC\n    WIN32\n    _DEBUG\n    CONSOLE\n)\n\n# Compiler options\ntarget_compile_options(${PROJECT_NAME} PRIVATE\n    -Wall\n    -Wextra\n    -Wpedantic\n)\n\n# Add subdir with lwesp and link to the project\nadd_subdirectory(\"../../lwesp\" lwesp)\ntarget_link_libraries(${PROJECT_NAME} lwesp)\n\n# Project specific sources and libs\nif (${PROJECT_NAME} STREQUAL \"client_rtos\")\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../snippets/client.c)\nendif()\nif (${PROJECT_NAME} STREQUAL \"dns_rtos\")\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../snippets/dns.c)\nendif()\nif (${PROJECT_NAME} STREQUAL \"mqtt_client_api_rtos\")\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../lwesp/src/apps/mqtt/lwesp_mqtt_client.c)\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../lwesp/src/apps/mqtt/lwesp_mqtt_client_api.c)\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../snippets/mqtt_client.c)\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../snippets/mqtt_client_api.c)\ntarget_link_libraries(${PROJECT_NAME}   lwesp_api)\nendif()\nif (${PROJECT_NAME} STREQUAL \"mqtt_client_rtos\")\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../lwesp/src/apps/mqtt/lwesp_mqtt_client.c)\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../lwesp/src/apps/mqtt/lwesp_mqtt_client_api.c)\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../snippets/mqtt_client.c)\nendif()\nif (${PROJECT_NAME} STREQUAL \"netconn_client_rtos\")\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../snippets/netconn_client.c)\ntarget_link_libraries(${PROJECT_NAME}   lwesp_api)\nendif()\nif (${PROJECT_NAME} STREQUAL \"netconn_server_rtos\")\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../snippets/netconn_server.c)\ntarget_link_libraries(${PROJECT_NAME}   lwesp_api)\nendif()\nif (${PROJECT_NAME} STREQUAL \"sntp_rtos\")\ntarget_sources(${PROJECT_NAME} PUBLIC   ${CMAKE_CURRENT_LIST_DIR}/../../snippets/sntp.c)\nendif()\n"
  },
  {
    "path": "examples/win32/CMakePresets.json",
    "content": "{\n    \"version\": 3,\n    \"configurePresets\": [\n        {\n            \"name\": \"default\",\n            \"hidden\": true,\n            \"generator\": \"Ninja\",\n            \"binaryDir\": \"${sourceDir}/build/${presetName}\",\n            \"toolchainFile\": \"${sourceDir}/../../cmake/i686-w64-mingw32-gcc.cmake\",\n            \"cacheVariables\": {\n                \"CMAKE_BUILD_TYPE\": \"Debug\",\n                \"CMAKE_EXPORT_COMPILE_COMMANDS\": \"ON\"\n            }\n        },\n        {\n            \"name\": \"access_point_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"access_point_rtos\"\n            }\n        },\n        {\n            \"name\": \"client_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"client_rtos\"\n            }\n        },\n        {\n            \"name\": \"dns_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"dns_rtos\"\n            }\n        },\n        {\n            \"name\": \"mqtt_client_api_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"mqtt_client_api_rtos\"\n            }\n        },\n        {\n            \"name\": \"mqtt_client_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"mqtt_client_rtos\"\n            }\n        },\n        {\n            \"name\": \"netconn_client_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"netconn_client_rtos\"\n            }\n        },\n        {\n            \"name\": \"netconn_server_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"netconn_server_rtos\"\n            }\n        },\n        {\n            \"name\": \"server_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"server_rtos\"\n            }\n        },\n        {\n            \"name\": \"sntp_rtos\",\n            \"inherits\": \"default\",\n            \"cacheVariables\": {\n                \"PROJECT_NAME\": \"sntp_rtos\"\n            }\n        }\n    ],\n\n    \"buildPresets\": [\n        {\n            \"name\": \"access_point_rtos\",\n            \"configurePreset\": \"access_point_rtos\"\n        },\n        {\n            \"name\": \"client_rtos\",\n            \"configurePreset\": \"client_rtos\"\n        },\n        {\n            \"name\": \"dns_rtos\",\n            \"configurePreset\": \"dns_rtos\"\n        },\n        {\n            \"name\": \"mqtt_client_api_rtos\",\n            \"configurePreset\": \"mqtt_client_api_rtos\"\n        },\n        {\n            \"name\": \"mqtt_client_rtos\",\n            \"configurePreset\": \"mqtt_client_rtos\"\n        },\n        {\n            \"name\": \"netconn_client_rtos\",\n            \"configurePreset\": \"netconn_client_rtos\"\n        },\n        {\n            \"name\": \"netconn_server_rtos\",\n            \"configurePreset\": \"netconn_server_rtos\"\n        },\n        {\n            \"name\": \"server_rtos\",\n            \"configurePreset\": \"server_rtos\"\n        },\n        {\n            \"name\": \"sntp_rtos\",\n            \"configurePreset\": \"sntp_rtos\"\n        }\n    ]\n}"
  },
  {
    "path": "examples/win32/README.md",
    "content": "# WIN32 examples\n\nExamples are provided as CMake sources.\nTo run then, you can use VSCode or CMake directly.\n\n```\ncmake --preset <example_preset_from_CMakePresets.json_file>\ncmake --build --preset <example_preset_from_CMakePresets.json_file>\n```\n"
  },
  {
    "path": "examples/win32/access_point_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/access_point_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"utils.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/* Callback function for example related events */\nstatic lwespr_t lwesp_callback_func(lwesp_evt_t* evt);\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    lwespr_t res;\n\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n    lwesp_evt_register(lwesp_callback_func);\n\n    /* Enable access point only mode */\n    if ((res = lwesp_set_wifi_mode(LWESP_MODE_AP, NULL, NULL, 1)) == lwespOK) {\n        printf(\"ESP set to access-point-only mode\\r\\n\");\n    } else {\n        printf(\"Problems setting ESP to access-point-only mode: %d\\r\\n\", (int)res);\n    }\n\n    /* Configure access point */\n    res = lwesp_ap_set_config(\"LWESP_AccessPoint\", \"ap_password\", 13, LWESP_ECN_WPA2_PSK, 5, 0, NULL, NULL, 1);\n    if (res == lwespOK) {\n        printf(\"Access point configured!\\r\\n\");\n    } else {\n        printf(\"Cannot configure access point!\\r\\n\");\n    }\n\n    /* The rest is handled in event function */\n\n    /*\n     * Do not stop program here.\n     * New threads were created for ESP processing\n     */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n\n/**\n * \\brief           Event callback function for ESP stack\n * \\param[in]       evt: Event information with data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nlwesp_callback_func(lwesp_evt_t* evt) {\n    switch (lwesp_evt_get_type(evt)) {\n        case LWESP_EVT_AP_CONNECTED_STA: {\n            lwesp_mac_t* mac = lwesp_evt_ap_connected_sta_get_mac(evt);\n            utils_print_mac(\"New station connected to access point with MAC address: \", mac, \"\\r\\n\");\n            break;\n        }\n        case LWESP_EVT_AP_IP_STA: {\n            lwesp_mac_t* mac = lwesp_evt_ap_ip_sta_get_mac(evt);\n            lwesp_ip_t* ip = lwesp_evt_ap_ip_sta_get_ip(evt);\n\n            utils_print_ip(\"IP \", ip, \" assigned to station with MAC address: \");\n            utils_print_mac(NULL, mac, \"\\r\\n\");\n            break;\n        }\n        case LWESP_EVT_AP_DISCONNECTED_STA: {\n            lwesp_mac_t* mac = lwesp_evt_ap_disconnected_sta_get_mac(evt);\n            utils_print_mac(\"Station disconnected from access point with MAC address: \", mac, \"\\r\\n\");\n            break;\n        }\n        default: break;\n    }\n    return lwespOK;\n}\n"
  },
  {
    "path": "examples/win32/build_all_examples.py",
    "content": "import os\nimport re\n\n# Get presets from the path\n# Use cmake command line to list actual presets visible to cmake\ndef get_presets():\n\tpresets = []\n\tresp = os.popen(\"cmake --list-presets\").read().strip()\n\tfor line in resp.split(\"\\n\"):\n\t\tl = line.strip()\n\t\tr = re.findall(\"\\\"(.*)\\\"\", l)\n\t\tif r:\n\t\t\tpresets.append(r[0])\n\treturn presets\n\n# Main execution\nif __name__ == '__main__':\t\n\t# Get all presets\n\tfailed = []\n\tpresets = get_presets()\n\tfor preset in presets:\n\t\tprint(\"-------------------------------\")\n\t\tprint(\"Configuring preset \" + preset)\n\t\tprint(\"-------------------------------\")\n\t\tret = os.system(\"cmake --preset \" + preset)\n\t\tif ret != 0:\n\t\t\tprint(\"!!!! Command failed !!!! with result code: \" + str(ret))\n\t\t\tfailed.append(preset)\n\t\tprint(\"Return: \" + str(ret))\n\t\tprint(\"-------------------------------\")\n\t\tprint(\"Building preset \" + preset)\n\t\tprint(\"-------------------------------\")\n\t\tret = os.system(\"cmake --build --preset \" + preset)\n\t\tif ret != 0:\n\t\t\tprint(\"!!!! Command failed !!!! with result code: \" + str(ret))\n\t\t\tfailed.append(preset)\n\t\tprint(\"Return: \" + str(ret))\n\t\tprint(\"-------------------------------\")\n\tprint(\"Failed presets:\")\n\tfor p in failed:\n\t\tprint(p)\n\tprint(\"-------------------------------\")"
  },
  {
    "path": "examples/win32/client_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/client_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"netconn_client.h\"\n#include \"client.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /* Start client connections */\n    client_connect();\n\n    /*\n     * Do not stop program here as we still need to wait\n     * for commands to be processed\n     */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "examples/win32/dns_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#define LWESP_CFG_DNS                         1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/dns_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"dns.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /* Start DNS request */\n    dns_start();\n\n    /* Do not stop execution */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "examples/win32/mqtt_client_api_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/mqtt_client_api_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"mqtt_client_api.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /* Start MQTT API thread */\n    lwesp_sys_thread_create(NULL, \"mqtt_client_api\", (lwesp_sys_thread_fn)lwesp_mqtt_client_api_thread, NULL, LWESP_SYS_THREAD_SS, LWESP_SYS_THREAD_PRIO);\n\n    /*\n     * Do not stop program here.\n     * New threads were created for ESP processing\n     */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "examples/win32/mqtt_client_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#define LWESP_CFG_PING                        1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/mqtt_client_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"mqtt_client.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /* Start a new thread for MQTT client */\n    lwesp_sys_thread_create(NULL, \"mqtt_client\", (lwesp_sys_thread_fn)mqtt_client_thread, NULL, LWESP_SYS_THREAD_SS, LWESP_SYS_THREAD_PRIO);\n\n    while (1) {\n        lwesp_delay(1000);\n    }\n}\n"
  },
  {
    "path": "examples/win32/netconn_client_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#define LWESP_CFG_NETCONN                     1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/netconn_client_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"netconn_client.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /*\n     * Start netconn client processing in separate thread\n     *\n     * Use netconn_client_thread function as thread entry point\n     */\n    lwesp_sys_thread_create(NULL, \"netconn_client\", (lwesp_sys_thread_fn)netconn_client_thread, NULL, 0, 0);\n\n    /*\n     * Do not stop program here.\n     * New threads were created for ESP processing\n     */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "examples/win32/netconn_server_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#define LWESP_CFG_NETCONN                     1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/netconn_server_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"netconn_server.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /*\n     * Start netconn server processing in separate thread\n     *\n     * Use netconn_server_thread function as thread entry point\n     */\n    lwesp_sys_thread_create(NULL, \"netconn_client\", (lwesp_sys_thread_fn)netconn_server_thread, NULL, 0, 0);\n\n    /*\n     * Do not stop program here.\n     * New threads were created for ESP processing\n     */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "examples/win32/server_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/server_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"netconn_client.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/* Callback for server operations */\nstatic lwespr_t lwesp_server_callback_func(lwesp_evt_t* evt);\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /* Start server on port 80 */\n    lwesp_set_server(1, 80, LWESP_CFG_MAX_CONNS, 0, lwesp_server_callback_func, NULL, NULL, 1);\n\n    /*\n     * Do not stop program here as we still need to wait\n     * for commands to be processed\n     */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n\n/**\n * \\brief           Callback function for server connection events\n * \\param[in]       evt: Event information with data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nlwesp_server_callback_func(lwesp_evt_t* evt) {\n    lwesp_conn_p conn;\n\n    conn = lwesp_conn_get_from_evt(evt);          /* Get connection handle from event */\n    switch (lwesp_evt_get_type(evt)) {\n        case LWESP_EVT_CONN_ACTIVE: {             /* Connection just active */\n            printf(\"Connection %d active as server!\\r\\n\", (int)lwesp_conn_getnum(conn));\n            break;\n        }\n        case LWESP_EVT_CONN_RECV: {               /* Connection data received */\n            lwesp_pbuf_p p;\n            p = lwesp_evt_conn_recv_get_buff(evt);/* Get received buffer */\n            if (p != NULL) {\n                printf(\"Server connection %d data received with %d bytes\\r\\n\",\n                    (int)lwesp_conn_getnum(conn), (int)lwesp_pbuf_length(p, 1));\n            }\n            lwesp_conn_close(conn, 0);            /* Close connection */\n            break;\n        }\n        case LWESP_EVT_CONN_CLOSE: {              /* Connection closed */\n            printf(\"Server connection %d closed!\\r\\n\", (int)lwesp_conn_getnum(conn));\n            break;\n        }\n        default: break;\n    }\n    return lwespOK;\n}\n"
  },
  {
    "path": "examples/win32/sntp_rtos/lwesp_opts.h",
    "content": "/**\n * \\file            lwesp_opts.h\n * \\brief           ESP application options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.0-dev\n */\n#ifndef LWESP_HDR_OPTS_H\n#define LWESP_HDR_OPTS_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n#define LWESP_CFG_AT_ECHO                     1\n#define LWESP_CFG_INPUT_USE_PROCESS           1\n\n#define LWESP_CFG_SNTP                        1\n\n#endif /* LWESP_HDR_OPTS_H */\n"
  },
  {
    "path": "examples/win32/sntp_rtos/main.c",
    "content": "/**\n * \\file            main.c\n * \\brief           Main file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Before you start using WIN32 implementation with USB and VCP,\n * check lwesp_ll_win32.c implementation and choose your COM port!\n */\n#include \"lwesp/lwesp.h\"\n#include \"station_manager.h\"\n#include \"sntp.h\"\n#include \"examples_common_lwesp_callback_func.h\"\n\n/**\n * \\brief           Program entry point\n */\nint\nmain(void) {\n    printf(\"Starting ESP application!\\r\\n\");\n\n    /* Initialize ESP with common callback for all examples */\n    printf(\"Initializing LwESP\\r\\n\");\n    if (lwesp_init(examples_common_lwesp_callback_func, 1) != lwespOK) {\n        printf(\"Cannot initialize LwESP!\\r\\n\");\n    } else {\n        printf(\"LwESP initialized!\\r\\n\");\n    }\n\n    /*\n     * Connect to access point.\n     *\n     * Try unlimited time until access point accepts us.\n     * Check for station_manager.c to define preferred access points ESP should connect to\n     */\n    station_manager_connect_to_preferred_access_point(1);\n\n    /* Start SNTP */\n    sntp_gettime();\n\n    /* Do not stop execution */\n    while (1) {\n        lwesp_delay(1000);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "library.json",
    "content": "{\n\t\"name\": \"LwESP\",\n\t\"version\": \"1.1.2-dev\",\n\t\"description\": \"Lightweight Espressif ESP32 and ESP8266 AT commands parser for embedded systems\",\n\t\"keywords\": \"lwesp, lightweiight, ESP32, ESP8266, AT, AT Commands\",\n\t\"repository\": {\n\t\t\"type\": \"git\",\n\t\t\"url\": \"https://github.com/MaJerle/lwesp.git\"\n\t},\n\t\"authors\": [\n\t\t{\n\t\t  \t\"name\": \"Tilen Majerle\",\n\t\t  \t\"email\": \"tilen@majerle.eu\",\n\t\t  \t\"url\": \"https://majerle.eu\"\n\t\t}\n\t],\n\t\"license\": \"MIT\",\n\t\"homepage\": \"https://github.com/MaJerle/lwesp\",\n\t\"dependencies\": {\n\n\t},\n\t\"frameworks\": \"*\",\n\t\"platforms\": \"*\",\n\t\"export\": {\n\t\t\"exclude\": [\n\t\t\t\".github\",\n\t\t\t\"dev\",\n\t\t\t\"docs\",\n\t\t\t\"**/.vs\",\n\t\t\t\"**/Debug\",\n\t\t\t\"build\",\n\t\t\t\"**/build\",\n\t\t\t\"esp_at_binaries\"\n\t\t]\n\t}\n}"
  },
  {
    "path": "lwesp/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.22)\n\ninclude(${CMAKE_CURRENT_LIST_DIR}/library.cmake)"
  },
  {
    "path": "lwesp/library.cmake",
    "content": "#\n# LIB_PREFIX: LWESP\n#\n# This file provides set of variables for end user\n# and also generates one (or more) libraries, that can be added to the project using target_link_libraries(...)\n#\n# Before this file is included to the root CMakeLists file (using include() function), user can set some variables:\n#\n# LWESP_SYS_PORT: If defined, it will include port source file from the library, and include the necessary header file.\n# LWESP_OPTS_FILE: If defined, it is the path to the user options file. If not defined, one will be generated for you automatically\n# LWESP_COMPILE_OPTIONS: If defined, it provide compiler options for generated library.\n# LWESP_COMPILE_DEFINITIONS: If defined, it provides \"-D\" definitions to the library build\n#\n\n# Custom include directory\nset(LWESP_CUSTOM_INC_DIR ${CMAKE_CURRENT_BINARY_DIR}/lib_inc)\n\n# Library core sources\nset(lwesp_core_SRCS\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_ap.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_ble.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_bt.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_buff.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_cli.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_conn.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_debug.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_dhcp.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_dns.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_evt.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_flash.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_hostname.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_input.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_int.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_mdns.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_mem.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_parser.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_pbuf.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_ping.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_server.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_smart.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_sntp.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_sta.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_threads.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_timeout.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_unicode.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_utils.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_webserver.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_wps.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp.c\n)\n\n# API sources\nset(lwesp_api_SRCS\n    ${CMAKE_CURRENT_LIST_DIR}/src/api/lwesp_netconn.c\n)\n\n# HTTP server\nset(lwesp_httpsrv_SRCS\n    ${CMAKE_CURRENT_LIST_DIR}/src/apps/http_server/lwesp_http_server.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/apps/http_server/lwesp_http_server_fs.c\n)\n\n# MQTT\nset(lwesp_mqtt_SRCS\n    ${CMAKE_CURRENT_LIST_DIR}/src/apps/mqtt/lwesp_mqtt_client.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/apps/mqtt/lwesp_mqtt_client_api.c\n)\n\n# CLI\nset(lwesp_cli_SRCS\n    ${CMAKE_CURRENT_LIST_DIR}/src/lwesp/lwesp_cli.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/cli/cli.c\n    ${CMAKE_CURRENT_LIST_DIR}/src/cli/cli_input.c\n)\n\n# All apps source files\nset(lwesp_allapps_SRCS\n    ${lwesp_mqtt_SRCS}\n    ${lwesp_httpsrv_SRCS}\n    ${lwesp_cli_SRCS}\n)\n\n# Setup include directories\nset(lwesp_include_DIRS\n    ${CMAKE_CURRENT_LIST_DIR}/src/include\n    ${LWESP_CUSTOM_INC_DIR}\n)\n\n# Add system port to core if user defined\nif(DEFINED LWESP_SYS_PORT)\n    set(lwesp_core_SRCS ${lwesp_core_SRCS} ${CMAKE_CURRENT_LIST_DIR}/src/system/lwesp_sys_${LWESP_SYS_PORT}.c)\n    set(lwesp_include_DIRS ${lwesp_include_DIRS} ${CMAKE_CURRENT_LIST_DIR}/src/include/system/port/${LWESP_SYS_PORT})\nendif()\n\n# Register core library to the system\nadd_library(lwesp)\ntarget_sources(lwesp PRIVATE ${lwesp_core_SRCS})\ntarget_include_directories(lwesp PUBLIC ${lwesp_include_DIRS})\ntarget_compile_options(lwesp PRIVATE ${LWESP_COMPILE_OPTIONS})\ntarget_compile_definitions(lwesp PRIVATE ${LWESP_COMPILE_DEFINITIONS})\n\n# Register API to the system\nadd_library(lwesp_api)\ntarget_sources(lwesp_api PRIVATE ${lwesp_api_SRCS})\ntarget_include_directories(lwesp_api PUBLIC ${lwesp_include_DIRS})\ntarget_compile_options(lwesp_api PRIVATE ${LWESP_COMPILE_OPTIONS})\ntarget_compile_definitions(lwesp_api PRIVATE ${LWESP_COMPILE_DEFINITIONS})\ntarget_link_directories(lwesp_api PUBLIC lwesp)\n\n# Register apps to the system\nadd_library(lwesp_apps)\ntarget_sources(lwesp_apps PRIVATE ${lwesp_allapps_SRCS})\ntarget_include_directories(lwesp_apps PUBLIC ${lwesp_include_DIRS})\ntarget_compile_options(lwesp_apps PRIVATE ${LWESP_COMPILE_OPTIONS})\ntarget_compile_definitions(lwesp_apps PRIVATE ${LWESP_COMPILE_DEFINITIONS})\ntarget_link_directories(lwesp_apps PUBLIC lwesp)\n\n# Create config file if user didn't provide one info himself\nif(NOT LWESP_OPTS_FILE)\n    message(STATUS \"Using default lwesp_opts.h file\")\n    set(LWESP_OPTS_FILE ${CMAKE_CURRENT_LIST_DIR}/src/include/lwesp/lwesp_opts_template.h)\nelse()\n    message(STATUS \"Using custom lwesp_opts.h file from ${LWESP_OPTS_FILE}\")\nendif()\n\nconfigure_file(${LWESP_OPTS_FILE} ${LWESP_CUSTOM_INC_DIR}/lwesp_opts.h COPYONLY)\n"
  },
  {
    "path": "lwesp/src/api/lwesp_netconn.c",
    "content": "/**\n * \\file            lwesp_netconn.c\n * \\brief           API functions for sequential calls\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_netconn.h\"\n#include \"lwesp/lwesp_conn.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_NETCONN || __DOXYGEN__\n\n/* Check conditions */\n#if LWESP_CFG_NETCONN_RECEIVE_QUEUE_LEN < 2\n#error \"LWESP_CFG_NETCONN_RECEIVE_QUEUE_LEN must be greater or equal to 2\"\n#endif /* LWESP_CFG_NETCONN_RECEIVE_QUEUE_LEN < 2 */\n\n#if LWESP_CFG_NETCONN_ACCEPT_QUEUE_LEN < 2\n#error \"LWESP_CFG_NETCONN_ACCEPT_QUEUE_LEN must be greater or equal to 2\"\n#endif /* LWESP_CFG_NETCONN_ACCEPT_QUEUE_LEN < 2 */\n\n/* Check for IP status */\n#if LWESP_CFG_IPV6\n#define NETCONN_IS_TCP(nc) ((nc)->type == LWESP_NETCONN_TYPE_TCP || (nc)->type == LWESP_NETCONN_TYPE_TCPV6)\n#define NETCONN_IS_SSL(nc) ((nc)->type == LWESP_NETCONN_TYPE_SSL || (nc)->type == LWESP_NETCONN_TYPE_SSLV6)\n#define NETCONN_IS_UDP(nc) ((nc)->type == LWESP_NETCONN_TYPE_UDP || (nc)->type == LWESP_NETCONN_TYPE_UDPV6)\n#else\n#define NETCONN_IS_TCP(nc) ((nc)->type == LWESP_NETCONN_TYPE_TCP)\n#define NETCONN_IS_SSL(nc) ((nc)->type == LWESP_NETCONN_TYPE_SSL)\n#define NETCONN_IS_UDP(nc) ((nc)->type == LWESP_NETCONN_TYPE_UDP)\n#endif /* LWESP_CFG_IPV6 */\n\n/**\n * \\brief           Sequential API structure\n */\ntypedef struct lwesp_netconn {\n    struct lwesp_netconn* next; /*!< Linked list entry */\n\n    lwesp_netconn_type_t type;  /*!< Netconn type */\n    lwesp_port_t listen_port;   /*!< Port on which we are listening */\n\n    size_t rcv_packets;         /*!< Number of received packets so far on this connection */\n    lwesp_conn_p conn;          /*!< Pointer to actual connection */\n    uint16_t conn_val_id; /*!< Connection validation ID that changes between every connection active/closed operation */\n\n    lwesp_sys_mbox_t mbox_accept;  /*!< List of active connections waiting to be processed */\n    lwesp_sys_mbox_t mbox_receive; /*!< Message queue for receive mbox */\n    size_t mbox_receive_entries;   /*!< Number of entries written to receive mbox */\n\n    lwesp_linbuff_t buff;          /*!< Linear buffer structure */\n\n    uint16_t conn_timeout;         /*!< Connection timeout in units of seconds when\n                                                    netconn is in server (listen) mode.\n                                                    Connection will be automatically closed if there is no\n                                                    data exchange in time. Set to `0` when timeout feature is disabled. */\n\n#if LWESP_CFG_NETCONN_RECEIVE_TIMEOUT || __DOXYGEN__\n    uint32_t rcv_timeout; /*!< Receive timeout in unit of milliseconds */\n#endif\n} lwesp_netconn_t;\n\nstatic uint8_t recv_closed = 0xFF, recv_not_present = 0xFF;\nstatic lwesp_netconn_t* listen_api;   /*!< Main connection in listening mode */\nstatic lwesp_netconn_t* netconn_list; /*!< Linked list of netconn entries */\n\n/**\n * \\brief           Flush all mboxes and clear possible used memories\n * \\param[in]       nc: Pointer to netconn to flush\n * \\param[in]       protect: Set to 1 to protect against multi-thread access\n */\nstatic void\nflush_mboxes(lwesp_netconn_t* nc, uint8_t protect) {\n    lwesp_pbuf_p pbuf;\n    lwesp_netconn_t* new_nc;\n    if (protect) {\n        lwesp_core_lock();\n    }\n    if (lwesp_sys_mbox_isvalid(&nc->mbox_receive)) {\n        while (lwesp_sys_mbox_getnow(&nc->mbox_receive, (void**)&pbuf)) {\n            if (nc->mbox_receive_entries > 0) {\n                --nc->mbox_receive_entries;\n            }\n            if (pbuf != NULL && (uint8_t*)pbuf != (uint8_t*)&recv_closed) {\n                LWESP_DEBUGF(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING,\n                             \"[LWESP NETCONN] flush mboxes. Clearing pbuf 0x%p\\r\\n\", (void*)pbuf);\n                lwesp_pbuf_free_s(&pbuf); /* Free received data buffers */\n            }\n        }\n        lwesp_sys_mbox_delete(&nc->mbox_receive);  /* Delete message queue */\n        lwesp_sys_mbox_invalid(&nc->mbox_receive); /* Invalid handle */\n    }\n    if (lwesp_sys_mbox_isvalid(&nc->mbox_accept)) {\n        while (lwesp_sys_mbox_getnow(&nc->mbox_accept, (void**)&new_nc)) {\n            if (new_nc != NULL && (uint8_t*)new_nc != (uint8_t*)&recv_closed\n                && (uint8_t*)new_nc != (uint8_t*)&recv_not_present) {\n                lwesp_netconn_close(new_nc); /* Close netconn connection */\n            }\n        }\n        lwesp_sys_mbox_delete(&nc->mbox_accept);  /* Delete message queue */\n        lwesp_sys_mbox_invalid(&nc->mbox_accept); /* Invalid handle */\n    }\n    if (protect) {\n        lwesp_core_unlock();\n    }\n}\n\n/**\n * \\brief           Callback function for every server connection\n * \\param[in]       evt: Pointer to callback structure\n * \\return          Member of \\ref lwespr_t enumeration\n */\nstatic lwespr_t\nnetconn_evt(lwesp_evt_t* evt) {\n    lwesp_conn_p conn;\n    lwesp_netconn_t* nc = NULL;\n    uint8_t close = 0;\n\n    conn = lwesp_conn_get_from_evt(evt); /* Get connection from event */\n    switch (lwesp_evt_get_type(evt)) {\n        /*\n         * A new connection has been active\n         * and should be handled by netconn API\n         */\n        case LWESP_EVT_CONN_ACTIVE: {               /* A new connection active is active */\n            if (lwesp_conn_is_client(conn)) {       /* Was connection started by us? */\n                nc = lwesp_conn_get_arg(conn);      /* Argument should be already set */\n                if (nc != NULL) {\n                    nc->conn = conn;                /* Save actual connection */\n                    nc->conn_val_id = conn->val_id; /* Get value ID */\n                } else {\n                    close = 1;                      /* Close this connection, invalid netconn */\n                }\n\n                /* Is the connection server type and we have known listening API? */\n            } else if (lwesp_conn_is_server(conn) && listen_api != NULL) {\n                /*\n                 * Create a new netconn structure\n                 * and set it as connection argument.\n                 */\n                nc = lwesp_netconn_new(LWESP_NETCONN_TYPE_TCP); /* Create new API */\n                LWESP_DEBUGW(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING, nc == NULL,\n                             \"[LWESP NETCONN] Cannot create new structure for incoming server connection!\\r\\n\");\n\n                if (nc != NULL) {\n                    nc->conn = conn;              /* Set connection handle */\n                    nc->conn_val_id = conn->val_id;\n                    lwesp_conn_set_arg(conn, nc); /* Set argument for connection */\n\n                    /*\n                     * In case there is no listening connection,\n                     * simply close the connection\n                     */\n                    if (!lwesp_sys_mbox_isvalid(&listen_api->mbox_accept)\n                        || !lwesp_sys_mbox_putnow(&listen_api->mbox_accept, nc)) {\n                        LWESP_DEBUGF(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING,\n                                     \"[LWESP NETCONN] Accept MBOX is invalid or it cannot insert new nc!\\r\\n\");\n                        close = 1;\n                    }\n                } else {\n                    close = 1;\n                }\n            } else {\n                LWESP_DEBUGW(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING, listen_api == NULL,\n                             \"[LWESP NETCONN] Closing connection as there is no listening API in netconn!\\r\\n\");\n                close = 1; /* Close the connection at this point */\n            }\n\n            /* Decide if some events want to close the connection */\n            if (close) {\n                if (nc != NULL) {\n                    lwesp_conn_set_arg(conn, NULL); /* Reset argument */\n                    lwesp_netconn_delete(nc);       /* Free memory for API */\n                }\n                lwesp_conn_close(conn, 0);          /* Close the connection */\n                close = 0;\n            }\n            break;\n        }\n\n        /*\n         * We have a new data received which\n         * should have netconn structure as argument\n         */\n        case LWESP_EVT_CONN_RECV: {\n            lwesp_pbuf_p pbuf;\n\n            nc = lwesp_conn_get_arg(conn);            /* Get API from connection */\n            pbuf = lwesp_evt_conn_recv_get_buff(evt); /* Get received buff */\n\n#if !LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n            lwesp_conn_recved(conn, pbuf); /* Notify stack about received data */\n#endif                                     /* !LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n\n            lwesp_pbuf_ref(pbuf);          /* Increase reference counter */\n            LWESP_DEBUGW(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE, nc == NULL,\n                         \"[LWESP NETCONN] Data receive -> netconn is NULL!\\r\\n\");\n            LWESP_DEBUGW(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE, nc->conn_val_id != conn->val_id,\n                         \"[LWESP NETCONN] Connection validation ID does not match connection val_id!\\r\\n\");\n            LWESP_DEBUGW(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE, !lwesp_sys_mbox_isvalid(&nc->mbox_receive),\n                         \"[LWESP NETCONN] Receive mbox is not valid!\\r\\n\");\n            if (nc == NULL || nc->conn_val_id != conn->val_id || !lwesp_sys_mbox_isvalid(&nc->mbox_receive)\n                || !lwesp_sys_mbox_putnow(&nc->mbox_receive, pbuf)) {\n                LWESP_DEBUGF(LWESP_CFG_DBG_NETCONN,\n                             \"[LWESP NETCONN] Could not put receive packet. Ignoring more data for receive!\\r\\n\");\n                lwesp_pbuf_free_s(&pbuf); /* Free pbuf */\n                return lwespOKIGNOREMORE; /* Return OK to free the memory and ignore further data */\n            }\n            ++nc->mbox_receive_entries;   /* Increase number of packets in receive mbox */\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n            /* Check against 1 less to still allow potential close event to be written to queue */\n            if (nc->mbox_receive_entries >= (LWESP_CFG_NETCONN_RECEIVE_QUEUE_LEN - 1)) {\n                conn->status.f.receive_blocked = 1; /* Block reading more data */\n            }\n#endif                                              /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n\n            ++nc->rcv_packets;                      /* Increase number of packets received */\n            LWESP_DEBUGF(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE,\n                         \"[LWESP NETCONN] Received pbuf contains %d bytes. Handle written to receive mbox\\r\\n\",\n                         (int)lwesp_pbuf_length(pbuf, 0));\n            break;\n        }\n\n        /* Connection was just closed */\n        case LWESP_EVT_CONN_CLOSE: {\n            nc = lwesp_conn_get_arg(conn); /* Get API from connection */\n\n            /*\n             * In case we have a netconn available,\n             * simply write pointer to received variable to indicate closed state\n             */\n            if (nc != NULL && nc->conn_val_id == conn->val_id && lwesp_sys_mbox_isvalid(&nc->mbox_receive)) {\n                if (lwesp_sys_mbox_putnow(&nc->mbox_receive, (void*)&recv_closed)) {\n                    ++nc->mbox_receive_entries;\n                }\n            }\n            break;\n        }\n        default: return lwespERR;\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Global event callback function\n * \\param[in]       evt: Callback information and data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nlwesp_evt(lwesp_evt_t* evt) {\n    switch (lwesp_evt_get_type(evt)) {\n        case LWESP_EVT_WIFI_DISCONNECTED: { /* Wifi disconnected event */\n            if (listen_api != NULL) {       /* Check if listen API active */\n                lwesp_sys_mbox_putnow(&listen_api->mbox_accept, &recv_closed);\n            }\n            break;\n        }\n        case LWESP_EVT_DEVICE_PRESENT: {                            /* Device present event */\n            if (listen_api != NULL && !lwesp_device_is_present()) { /* Check if device present */\n                lwesp_sys_mbox_putnow(&listen_api->mbox_accept, &recv_not_present);\n            }\n        }\n        default: break;\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Create new netconn connection\n * \\param[in]       type: Netconn connection type\n * \\return          New netconn connection on success, `NULL` otherwise\n */\nlwesp_netconn_p\nlwesp_netconn_new(lwesp_netconn_type_t type) {\n    lwesp_netconn_t* a;\n    static uint8_t first = 1;\n\n    /* Register only once! */\n    lwesp_core_lock();\n    if (first) {\n        first = 0;\n        lwesp_evt_register(lwesp_evt); /* Register global event function */\n    }\n    lwesp_core_unlock();\n    a = lwesp_mem_calloc(1, sizeof(*a)); /* Allocate memory for core object */\n    if (a != NULL) {\n        a->type = type;                  /* Save netconn type */\n        a->conn_timeout = 0;             /* Default connection timeout */\n        if (!lwesp_sys_mbox_create(&a->mbox_accept, LWESP_CFG_NETCONN_ACCEPT_QUEUE_LEN)) {\n            LWESP_DEBUGF(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_DANGER,\n                         \"[LWESP NETCONN] Cannot create accept MBOX\\r\\n\");\n            goto free_ret;\n        }\n        if (!lwesp_sys_mbox_create(&a->mbox_receive, LWESP_CFG_NETCONN_RECEIVE_QUEUE_LEN)) {\n            LWESP_DEBUGF(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_DANGER,\n                         \"[LWESP NETCONN] Cannot create receive MBOX\\r\\n\");\n            goto free_ret;\n        }\n        lwesp_core_lock();\n        a->next = netconn_list; /* Add it to beginning of the list */\n        netconn_list = a;\n        lwesp_core_unlock();\n    }\n    return a;\nfree_ret:\n    if (lwesp_sys_mbox_isvalid(&a->mbox_accept)) {\n        lwesp_sys_mbox_delete(&a->mbox_accept);\n        lwesp_sys_mbox_invalid(&a->mbox_accept);\n    }\n    if (lwesp_sys_mbox_isvalid(&a->mbox_receive)) {\n        lwesp_sys_mbox_delete(&a->mbox_receive);\n        lwesp_sys_mbox_invalid(&a->mbox_receive);\n    }\n    if (a != NULL) {\n        lwesp_mem_free_s((void**)&a);\n    }\n    return NULL;\n}\n\n/**\n * \\brief           Delete netconn connection\n * \\param[in]       nc: Netconn handle\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_delete(lwesp_netconn_p nc) {\n    LWESP_ASSERT(nc != NULL);\n\n    lwesp_core_lock();\n    if (nc->conn != NULL) {\n        /* No NC for any incoming connections or anything else... */\n        lwesp_conn_set_arg(nc->conn, NULL);\n    }\n    flush_mboxes(nc, 0); /* Clear mboxes */\n\n    /* Stop listening on netconn */\n    if (nc == listen_api) {\n        listen_api = NULL;\n        lwesp_core_unlock();\n        lwesp_set_server(0, nc->listen_port, 0, 0, NULL, NULL, NULL, 1);\n        lwesp_core_lock();\n    }\n\n    /* Remove netconn from linkedlist */\n    if (nc == netconn_list) {\n        netconn_list = netconn_list->next; /* Remove first from linked list */\n    } else if (netconn_list != NULL) {\n        lwesp_netconn_p tmp, prev;\n        /* Find element on the list */\n        for (prev = netconn_list, tmp = netconn_list->next; tmp != NULL; prev = tmp, tmp = tmp->next) {\n            if (nc == tmp) {\n                prev->next = tmp->next; /* Remove tmp from linked list */\n                break;\n            }\n        }\n    }\n    if (nc->conn != NULL) {\n        /*\n         * First delete the connection argument,\n         * then close the connection.\n         */\n        if (lwesp_conn_is_active(nc->conn)) {\n            lwesp_conn_close(nc->conn, 1);\n        }\n        nc->conn = NULL;\n    }\n    lwesp_core_unlock();\n\n    lwesp_mem_free_s((void**)&nc);\n    return lwespOK;\n}\n\n/**\n * \\brief           Connect to server as client\n * \\param[in]       nc: Netconn handle\n * \\param[in]       host: Pointer to host, such as domain name or IP address in string format\n * \\param[in]       port: Target port to use\n * \\return          \\ref lwespOK if successfully connected, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_netconn_connect(lwesp_netconn_p nc, const char* host, lwesp_port_t port) {\n    lwespr_t res;\n\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(host != NULL);\n    LWESP_ASSERT(port > 0);\n\n    /*\n     * Start a new connection as client and:\n     *\n     *  - Set current netconn structure as argument\n     *  - Set netconn callback function for connection management\n     *  - Start connection in blocking mode\n     */\n    res = lwesp_conn_start(NULL, (lwesp_conn_type_t)nc->type, host, port, nc, netconn_evt, 1);\n    return res;\n}\n\n/**\n * \\brief           Connect to server as client, allow keep-alive option\n * \\param[in]       nc: Netconn handle\n * \\param[in]       host: Pointer to host, such as domain name or IP address in string format\n * \\param[in]       port: Target port to use\n * \\param[in]       keep_alive: Keep alive period seconds\n * \\param[in]       local_ip: Local ip in connected command\n * \\param[in]       local_port: Local port address\n * \\param[in]       mode: UDP mode\n * \\return          \\ref lwespOK if successfully connected, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_netconn_connect_ex(lwesp_netconn_p nc, const char* host, lwesp_port_t port, uint16_t keep_alive,\n                         const char* local_ip, lwesp_port_t local_port, uint8_t mode) {\n    lwesp_conn_start_t cs = {0};\n    lwespr_t res;\n\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(host != NULL);\n    LWESP_ASSERT(port > 0);\n\n    /*\n     * Start a new connection as client and:\n     *\n     *  - Set current netconn structure as argument\n     *  - Set netconn callback function for connection management\n     *  - Start connection in blocking mode\n     */\n    cs.type = (lwesp_conn_type_t)nc->type;\n    cs.remote_host = host;\n    cs.remote_port = port;\n    cs.local_ip = local_ip;\n    if (NETCONN_IS_TCP(nc) || NETCONN_IS_SSL(nc)) {\n        cs.ext.tcp_ssl.keep_alive = keep_alive;\n    } else {\n        cs.ext.udp.local_port = local_port;\n        cs.ext.udp.mode = mode;\n    }\n    res = lwesp_conn_startex(NULL, &cs, nc, netconn_evt, 1);\n    return res;\n}\n\n/**\n * \\brief           Bind a connection to specific port, can be only used for server connections\n * \\param[in]       nc: Netconn handle\n * \\param[in]       port: Port used to bind a connection to\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_bind(lwesp_netconn_p nc, lwesp_port_t port) {\n    lwespr_t res = lwespOK;\n\n    LWESP_ASSERT(nc != NULL);\n\n    /*\n     * Protection is not needed as it is expected\n     * that this function is called only from single\n     * thread for single netconn connection,\n     * thus it is considered reentrant\n     */\n\n    nc->listen_port = port;\n\n    return res;\n}\n\n/**\n * \\brief           Set timeout value in units of seconds when connection is in listening mode\n *                  If new connection is accepted, it will be automatically closed after `seconds` elapsed\n *                  without any data exchange.\n * \\note            Call this function before you put connection to listen mode with \\ref lwesp_netconn_listen\n * \\param[in]       nc: Netconn handle used for listen mode\n * \\param[in]       timeout: Time in units of seconds. Set to `0` to disable timeout feature\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_netconn_set_listen_conn_timeout(lwesp_netconn_p nc, uint16_t timeout) {\n    lwespr_t res = lwespOK;\n    LWESP_ASSERT(nc != NULL);\n\n    /*\n     * Protection is not needed as it is expected\n     * that this function is called only from single\n     * thread for single netconn connection,\n     * thus it is reentrant in this case\n     */\n\n    nc->conn_timeout = timeout;\n\n    return res;\n}\n\n/**\n * \\brief           Listen on previously binded connection\n * \\param[in]       nc: Netconn handle used to listen for new connections\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_listen(lwesp_netconn_p nc) {\n    return lwesp_netconn_listen_with_max_conn(nc, LWESP_CFG_MAX_CONNS);\n}\n\n/**\n * \\brief           Listen on previously binded connection with max allowed connections at a time\n * \\param[in]       nc: Netconn handle used to listen for new connections\n * \\param[in]       max_connections: Maximal number of connections server can accept at a time\n *                      This parameter may not be larger than \\ref LWESP_CFG_MAX_CONNS\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_netconn_listen_with_max_conn(lwesp_netconn_p nc, uint16_t max_connections) {\n    lwespr_t res;\n\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(NETCONN_IS_TCP(nc));\n\n    /* Enable server on port and set default netconn callback */\n    if ((res = lwesp_set_server(1, nc->listen_port, LWESP_U16(LWESP_MIN(max_connections, LWESP_CFG_MAX_CONNS)),\n                                nc->conn_timeout, netconn_evt, NULL, NULL, 1))\n        == lwespOK) {\n        lwesp_core_lock();\n        listen_api = nc; /* Set current main API in listening state */\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n/**\n * \\brief           Accept a new connection\n * \\param[in]       nc: Netconn handle used as base connection to accept new clients\n * \\param[out]      client: Pointer to netconn handle to save new connection to\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_accept(lwesp_netconn_p nc, lwesp_netconn_p* client) {\n    lwesp_netconn_t* tmp;\n    uint32_t time;\n\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(client != NULL);\n    LWESP_ASSERT(NETCONN_IS_TCP(nc));\n    LWESP_ASSERT(nc == listen_api);\n\n    *client = NULL;\n    time = lwesp_sys_mbox_get(&nc->mbox_accept, (void**)&tmp, 0);\n    if (time == LWESP_SYS_TIMEOUT) {\n        return lwespTIMEOUT;\n    }\n    if ((uint8_t*)tmp == (uint8_t*)&recv_closed) {\n        lwesp_core_lock();\n        listen_api = NULL;               /* Disable listening at this point */\n        lwesp_core_unlock();\n        return lwespERRWIFINOTCONNECTED; /* Wifi disconnected */\n    } else if ((uint8_t*)tmp == (uint8_t*)&recv_not_present) {\n        lwesp_core_lock();\n        listen_api = NULL;       /* Disable listening at this point */\n        lwesp_core_unlock();\n        return lwespERRNODEVICE; /* Device not present */\n    }\n    *client = tmp;               /* Set new pointer */\n    return lwespOK;              /* We have a new connection */\n}\n\n/**\n * \\brief           Write data to connection output buffers\n * \\note            This function may only be used on TCP or SSL connections\n * \\param[in]       nc: Netconn handle used to write data to\n * \\param[in]       data: Pointer to data to write\n * \\param[in]       btw: Number of bytes to write\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_write(lwesp_netconn_p nc, const void* data, size_t btw) {\n    size_t len, sent;\n    const uint8_t* d = data;\n    lwespr_t res;\n\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(NETCONN_IS_TCP(nc) || NETCONN_IS_SSL(nc));\n    LWESP_ASSERT(lwesp_conn_is_active(nc->conn));\n\n    /*\n     * Several steps are done in write process\n     *\n     * 1. Check if buffer is set and check if there is something to write to it.\n     *    1. In case buffer will be full after copy, send it and free memory.\n     * 2. Check how many bytes we can write directly without need to copy\n     * 3. Try to allocate a new buffer and copy remaining input data to it\n     * 4. In case buffer allocation fails, send data directly (may have impact on speed and effectivenes)\n     */\n\n    /* Step 1 */\n    if (nc->buff.buff != NULL) {                           /* Is there a write buffer ready to accept more data? */\n        len = LWESP_MIN(nc->buff.len - nc->buff.ptr, btw); /* Get number of bytes we can write to buffer */\n        if (len > 0) {\n            LWESP_MEMCPY(&nc->buff.buff[nc->buff.ptr], data, len); /* Copy memory to temporary write buffer */\n            d += len;\n            nc->buff.ptr += len;\n            btw -= len;\n        }\n\n        /* Step 1.1 */\n        if (nc->buff.ptr == nc->buff.len) {\n            res = lwesp_conn_send(nc->conn, nc->buff.buff, nc->buff.len, &sent, 1);\n\n            lwesp_mem_free_s((void**)&nc->buff.buff);\n            if (res != lwespOK) {\n                return res;\n            }\n        } else {\n            return lwespOK; /* Buffer is not full yet */\n        }\n    }\n\n    /* Step 2 */\n    if (btw >= LWESP_CFG_CONN_MAX_DATA_LEN) {\n        size_t rem;\n        rem = btw % LWESP_CFG_CONN_MAX_DATA_LEN;                 /* Get remaining bytes for max data length */\n        res = lwesp_conn_send(nc->conn, d, btw - rem, &sent, 1); /* Write data directly */\n        if (res != lwespOK) {\n            return res;\n        }\n        d += sent;   /* Advance in data pointer */\n        btw -= sent; /* Decrease remaining data to send */\n    }\n\n    if (btw == 0) { /* Sent everything? */\n        return lwespOK;\n    }\n\n    /* Step 3 */\n    if (nc->buff.buff == NULL) {                    /* Check if we should allocate a new buffer */\n        nc->buff.buff = lwesp_mem_malloc(sizeof(*nc->buff.buff) * LWESP_CFG_CONN_MAX_DATA_LEN);\n        nc->buff.len = LWESP_CFG_CONN_MAX_DATA_LEN; /* Save buffer length */\n        nc->buff.ptr = 0;                           /* Save buffer pointer */\n    }\n\n    /* Step 4 */\n    if (nc->buff.buff != NULL) {                              /* Memory available? */\n        LWESP_MEMCPY(&nc->buff.buff[nc->buff.ptr], d, btw);   /* Copy data to buffer */\n        nc->buff.ptr += btw;\n    } else {                                                  /* Still no memory available? */\n        return lwesp_conn_send(nc->conn, data, btw, NULL, 1); /* Simply send directly blocking */\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Extended version of \\ref lwesp_netconn_write with additional\n *                  option to set custom flags.\n * \n * \\note            It is recommended to use this for full features support \n * \n * \\param[in]       nc: Netconn handle used to write data to\n * \\param[in]       data: Pointer to data to write\n * \\param[in]       btw: Number of bytes to write\n * \\param           flags: Bitwise-ORed set of flags for netconn.\n *                      Flags start with \\ref LWESP_NETCONN_FLAG_xxx\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_write_ex(lwesp_netconn_p nc, const void* data, size_t btw, uint16_t flags) {\n    lwespr_t res = lwesp_netconn_write(nc, data, btw);\n    if (res == lwespOK) {\n        if (flags & LWESP_NETCONN_FLAG_FLUSH) {\n            res = lwesp_netconn_flush(nc);\n        }\n    }\n    return res;\n}\n\n/**\n * \\brief           Flush buffered data on netconn TCP/SSL connection\n * \\note            This function may only be used on TCP/SSL connection\n * \\param[in]       nc: Netconn handle to flush data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_flush(lwesp_netconn_p nc) {\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(NETCONN_IS_TCP(nc) || NETCONN_IS_SSL(nc));\n    LWESP_ASSERT(lwesp_conn_is_active(nc->conn));\n\n    /*\n     * In case we have data in write buffer,\n     * flush them out to network\n     */\n    if (nc->buff.buff != NULL) {                                             /* Check remaining data */\n        if (nc->buff.ptr > 0) {                                              /* Do we have data in current buffer? */\n            lwesp_conn_send(nc->conn, nc->buff.buff, nc->buff.ptr, NULL, 1); /* Send data */\n        }\n        lwesp_mem_free_s((void**)&nc->buff.buff);\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Send data on UDP connection to default IP and port\n * \\param[in]       nc: Netconn handle used to send\n * \\param[in]       data: Pointer to data to write\n * \\param[in]       btw: Number of bytes to write\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_send(lwesp_netconn_p nc, const void* data, size_t btw) {\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(nc->type == LWESP_NETCONN_TYPE_UDP);\n    LWESP_ASSERT(lwesp_conn_is_active(nc->conn));\n\n    return lwesp_conn_send(nc->conn, data, btw, NULL, 1);\n}\n\n/**\n * \\brief           Send data on UDP connection to specific IP and port\n * \\note            Use this function in case of UDP type netconn\n * \\param[in]       nc: Netconn handle used to send\n * \\param[in]       ip: Pointer to IP address\n * \\param[in]       port: Port number used to send data\n * \\param[in]       data: Pointer to data to write\n * \\param[in]       btw: Number of bytes to write\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_sendto(lwesp_netconn_p nc, const lwesp_ip_t* ip, lwesp_port_t port, const void* data, size_t btw) {\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(nc->type == LWESP_NETCONN_TYPE_UDP);\n    LWESP_ASSERT(lwesp_conn_is_active(nc->conn));\n\n    return lwesp_conn_sendto(nc->conn, ip, port, data, btw, NULL, 1);\n}\n\n/**\n * \\brief           Receive data from connection\n * \\param[in]       nc: Netconn handle used to receive from\n * \\param[in]       pbuf: Pointer to pointer to save new receive buffer to.\n *                     When function returns, user must check for valid pbuf value `pbuf != NULL`\n * \\return          \\ref lwespOK when new data ready\n * \\return          \\ref lwespCLOSED when connection closed by remote side\n * \\return          \\ref lwespTIMEOUT when receive timeout occurs\n * \\return          Any other member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_netconn_receive(lwesp_netconn_p nc, lwesp_pbuf_p* pbuf) {\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(pbuf != NULL);\n\n    *pbuf = NULL;\n#if LWESP_CFG_NETCONN_RECEIVE_TIMEOUT\n    /*\n     * Wait for new received data for up to specific timeout\n     * or throw error for timeout notification\n     */\n    if (nc->rcv_timeout == LWESP_NETCONN_RECEIVE_NO_WAIT) {\n        if (!lwesp_sys_mbox_getnow(&nc->mbox_receive, (void**)pbuf)) {\n            return lwespTIMEOUT;\n        }\n    } else if (lwesp_sys_mbox_get(&nc->mbox_receive, (void**)pbuf, nc->rcv_timeout) == LWESP_SYS_TIMEOUT) {\n        return lwespTIMEOUT;\n    }\n#else  /* LWESP_CFG_NETCONN_RECEIVE_TIMEOUT */\n    /* Forever wait for new receive packet */\n    lwesp_sys_mbox_get(&nc->mbox_receive, (void**)pbuf, 0);\n#endif /* !LWESP_CFG_NETCONN_RECEIVE_TIMEOUT */\n\n    lwesp_core_lock();\n    if (nc->mbox_receive_entries > 0) {\n        --nc->mbox_receive_entries;\n    }\n    lwesp_core_unlock();\n\n    /* Check if connection closed */\n    if ((uint8_t*)(*pbuf) == (uint8_t*)&recv_closed) {\n        *pbuf = NULL; /* Reset pbuf */\n        LWESP_DEBUGF(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING,\n                     \"[LWESP NETCONN] netcon_receive: Got object handle for close event\\r\\n\");\n        return lwespCLOSED;\n    }\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n    else {\n        lwesp_core_lock();\n        nc->conn->status.f.receive_blocked = 0; /* Resume reading more data */\n        lwesp_conn_recved(nc->conn, *pbuf);     /* Notify stack about received data */\n        lwesp_core_unlock();\n    }\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n    LWESP_DEBUGF(LWESP_CFG_DBG_NETCONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING,\n                 \"[LWESP NETCONN] netcon_receive: Got pbuf object handle at 0x%p. Len/Tot_len: %u/%u\\r\\n\", (void*)*pbuf,\n                 (unsigned)lwesp_pbuf_length(*pbuf, 0), (unsigned)lwesp_pbuf_length(*pbuf, 1));\n    return lwespOK; /* We have data available */\n}\n\n/**\n * \\brief           Close a netconn connection\n * \\param[in]       nc: Netconn handle to close\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_netconn_close(lwesp_netconn_p nc) {\n    lwesp_conn_p conn;\n\n    LWESP_ASSERT(nc != NULL);\n    LWESP_ASSERT(nc->conn != NULL);\n    LWESP_ASSERT(lwesp_conn_is_active(nc->conn));\n\n    lwesp_netconn_flush(nc); /* Flush data and ignore result */\n    conn = nc->conn;\n    nc->conn = NULL;\n\n    lwesp_conn_set_arg(conn, NULL); /* Reset argument */\n    lwesp_conn_close(conn, 1);      /* Close the connection */\n    flush_mboxes(nc, 1);            /* Flush message queues */\n    return lwespOK;\n}\n\n/**\n * \\brief           Get connection number used for netconn\n * \\param[in]       nc: Netconn handle\n * \\return          `-1` on failure, connection number between `0` and \\ref LWESP_CFG_MAX_CONNS otherwise\n */\nint8_t\nlwesp_netconn_get_connnum(lwesp_netconn_p nc) {\n    if (nc != NULL && nc->conn != NULL) {\n        return lwesp_conn_getnum(nc->conn);\n    }\n    return -1;\n}\n\n#if LWESP_CFG_NETCONN_RECEIVE_TIMEOUT || __DOXYGEN__\n\n/**\n * \\brief           Set timeout value for receiving data.\n *\n * When enabled, \\ref lwesp_netconn_receive will only block for up to\n * \\e timeout value and will return if no new data within this time\n *\n * \\param[in]       nc: Netconn handle\n * \\param[in]       timeout: Timeout in units of milliseconds.\n *                      Set to `0` to disable timeout feature. Function blocks until data receive or connection closed\n *                      Set to `> 0` to set maximum milliseconds to wait before timeout\n *                      Set to \\ref LWESP_NETCONN_RECEIVE_NO_WAIT to enable non-blocking receive\n */\nvoid\nlwesp_netconn_set_receive_timeout(lwesp_netconn_p nc, uint32_t timeout) {\n    nc->rcv_timeout = timeout;\n}\n\n/**\n * \\brief           Get netconn receive timeout value\n * \\param[in]       nc: Netconn handle\n * \\return          Timeout in units of milliseconds.\n *                  If value is `0`, timeout is disabled (wait forever)\n */\nuint32_t\nlwesp_netconn_get_receive_timeout(lwesp_netconn_p nc) {\n    return nc->rcv_timeout;\n}\n\n#endif /* LWESP_CFG_NETCONN_RECEIVE_TIMEOUT || __DOXYGEN__ */\n\n/**\n * \\brief           Get netconn connection handle\n * \\param[in]       nc: Netconn handle\n * \\return          ESP connection handle\n */\nlwesp_conn_p\nlwesp_netconn_get_conn(lwesp_netconn_p nc) {\n    return nc->conn;\n}\n\n/**\n * \\brief           Get netconn connection type\n * \\param[in]       nc: Netconn handle\n * \\return          ESP connection type\n */\nlwesp_netconn_type_t\nlwesp_netconn_get_type(lwesp_netconn_p nc) {\n    return nc->type;\n}\n\n#endif /* LWESP_CFG_NETCONN || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/apps/http_server/lwesp_http_server.c",
    "content": "/**\n * \\file            lwesp_http_server.c\n * \\brief           HTTP server based on callback API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include <ctype.h>\n#include \"lwesp/apps/lwesp_http_server.h\"\n#include \"lwesp/lwesp_mem.h\"\n\n#define LWESP_CFG_DBG_SERVER_TRACE         (LWESP_CFG_DBG_SERVER | LWESP_DBG_TYPE_TRACE)\n#define LWESP_CFG_DBG_SERVER_TRACE_WARNING (LWESP_CFG_DBG_SERVER | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING)\n#define LWESP_CFG_DBG_SERVER_TRACE_DANGER  (LWESP_CFG_DBG_SERVER | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_DANGER)\n\n/* Function prototypes, declarations in lwesp_http_server_fs.c file */\nuint8_t http_fs_data_open_file(const http_init_t* hi, http_fs_file_t* file, const char* path);\nuint32_t http_fs_data_read_file(const http_init_t* hi, http_fs_file_t* file, void** buff, size_t btr, size_t* br);\nvoid http_fs_data_close_file(const http_init_t* hi, http_fs_file_t* file);\n\n/** Number of opened files in system */\nuint16_t http_fs_opened_files_cnt;\n\n#define CRLF \"\\r\\n\"\n\nstatic char http_uri[HTTP_MAX_URI_LEN + 1];\nstatic http_param_t http_params[HTTP_MAX_PARAMS];\n\n/* HTTP init structure with user settings */\nstatic const http_init_t* hi;\n\n#if HTTP_USE_METHOD_NOTALLOWED_RESP\n/**\n * \\brief           Default output for method not allowed response\n */\nstatic const char http_data_method_not_allowed[] =\n    \"\"\n    \"HTTP/1.1 405 Method Not Allowed\" CRLF \"Server: \" HTTP_SERVER_NAME CRLF \"Allow: GET\"\n#if HTTP_SUPPORT_POST\n    \", POST\"\n#endif /* HTTP_SUPPORT_POST */\n    CRLF CRLF \"\";\n#endif /* HTTP_USE_METHOD_NOTALLOWED_RESP */\n\n#if HTTP_DYNAMIC_HEADERS\n/**\n * \\brief           Intexes for \\ref http_dynstrs array\n */\ntypedef enum {\n    /* Response code */\n    HTTP_HDR_200,\n    HTTP_HDR_400,\n    HTTP_HDR_404,\n\n    /* Server response code */\n    HTTP_HDR_SERVER,\n\n    /* Content type strings */\n    HTTP_HDR_HTML,\n    HTTP_HDR_PNG,\n    HTTP_HDR_JPG,\n    HTTP_HDR_GIF,\n    HTTP_HDR_CSS,\n    HTTP_HDR_JS,\n    HTTP_HDR_ICO,\n    HTTP_HDR_XML,\n    HTTP_HDR_PLAIN,\n} dynamic_headers_index_t;\n\n/**\n * \\brief           Array of supported response strings\n */\nstatic const char* const http_dynstrs[] = {\n    /* Response code */\n    \"HTTP/1.1 200 OK\" CRLF,\n    \"HTTP/1.1 400 Bad Request\" CRLF,\n    \"HTTP/1.1 404 File Not Found\" CRLF,\n\n    /* Server response code */\n    \"Server: \" HTTP_SERVER_NAME CRLF,\n\n    /* Content type strings */\n    \"Content-type: text/html\" CRLF CRLF,\n    \"Content-type: image/png\" CRLF CRLF,\n    \"Content-type: image/jpeg\" CRLF CRLF,\n    \"Content-type: image/gif\" CRLF CRLF,\n    \"Content-type: text/css\" CRLF CRLF,\n    \"Content-type: text/javascript\" CRLF CRLF,\n    \"Content-type: text/x-icon\" CRLF CRLF,\n    \"Content-type: text/xml\" CRLF CRLF,\n    \"Content-type: text/plain\" CRLF CRLF,\n};\n\n/**\n * \\brief           Header index and file suffix pair\n */\ntypedef struct {\n    dynamic_headers_index_t index;\n    const char* ext;\n} dynamic_headers_pair_t;\n\n/**\n * \\brief           Lookup table for file suffix and content type header\n */\nstatic const dynamic_headers_pair_t dynamic_headers_pairs[] = {\n    {HTTP_HDR_HTML, \"html\"}, {HTTP_HDR_HTML, \"htm\"}, {HTTP_HDR_HTML, \"shtml\"}, {HTTP_HDR_HTML, \"shtm\"},\n    {HTTP_HDR_HTML, \"ssi\"},  {HTTP_HDR_PNG, \"png\"},  {HTTP_HDR_JPG, \"jpg\"},    {HTTP_HDR_JPG, \"jpeg\"},\n    {HTTP_HDR_GIF, \"gif\"},   {HTTP_HDR_CSS, \"css\"},  {HTTP_HDR_JS, \"js\"},      {HTTP_HDR_ICO, \"ico\"},\n    {HTTP_HDR_XML, \"xml\"},\n};\n\n#endif /* HTTP_DYNAMIC_HEADERS */\n\n/**\n * \\brief           List of supported file names for index page\n */\nstatic const char* http_index_filenames[] = {\"/index.shtml\",\n                                             \"/index.shtm\"\n                                             \"/index.ssi\",\n                                             \"/index.html\", \"/index.htm\"};\n\n/**\n * \\brief           List of URI suffixes where SSI tags are supported\n */\nstatic const char* http_ssi_suffixes[] = {\".shtml\", \".shtm\", \".ssi\"};\n\n/**\n * \\brief           List of 404 URIs\n */\nstatic const char* http_404_uris[] = {\n    \"/404.shtml\", \"/404.shtm\", \"/404.ssi\", \"/404.html\", \"/404.htm\",\n};\n\n/**\n * \\brief           Compare 2 strings in case insensitive way\n * \\param[in]       a: String a to compare\n * \\param[in]       b: String b to compare\n * \\return          0 if equal, non-zero otherwise\n */\nint\nstrcmpa(const char* a, const char* b) {\n    int d;\n    for (;; ++a, ++b) {\n        d = tolower(*a) - tolower(*b);\n        if (d != 0 || !*a) {\n            return d;\n        }\n    }\n}\n\n/**\n * \\brief           Parse URI from HTTP request and copy it to linear memory location\n * \\param[in]       p: Chain of pbufs from request\n * \\return          \\ref lwespOK if successfully parsed, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nhttp_parse_uri(lwesp_pbuf_p p) {\n    size_t pos_s, pos_e, pos_crlf, uri_len;\n\n    pos_s = lwesp_pbuf_strfind(p, \" \", 0); /* Find first \" \" in request header */\n    if (pos_s == LWESP_SIZET_MAX || (pos_s != 3 && pos_s != 4)) {\n        return lwespERR;\n    }\n    pos_crlf = lwesp_pbuf_strfind(p, CRLF, 0); /* Find CRLF position */\n    if (pos_crlf == LWESP_SIZET_MAX) {\n        return lwespERR;\n    }\n    pos_e = lwesp_pbuf_strfind(p, \" \", pos_s + 1); /* Find second \" \" in request header */\n    if (pos_e == LWESP_SIZET_MAX) {                /* If there is no second \" \" */\n        /*\n         * HTTP 0.9 request is \"GET /\\r\\n\" without\n         * space between request URI and CRLF\n         */\n        pos_e = pos_crlf; /* Use the one from CRLF */\n    }\n\n    uri_len = pos_e - pos_s - 1; /* Get length of uri */\n    if (uri_len > HTTP_MAX_URI_LEN) {\n        return lwespERR;\n    }\n    lwesp_pbuf_copy(p, http_uri, uri_len, pos_s + 1); /* Copy data from pbuf to linear memory */\n    http_uri[uri_len] = 0;                            /* Set terminating 0 */\n\n    return lwespOK;\n}\n\n/**\n * \\brief           Extract parameters from user request URI\n * \\param[in]       params: RAM variable with parameters\n * \\return          Number of parameters extracted\n */\nstatic size_t\nhttp_get_params(char* params) {\n    size_t cnt = 0;\n    char *amp, *eq;\n\n    if (params != NULL) {\n        for (size_t i = 0; params != NULL && i < HTTP_MAX_PARAMS; ++i, ++cnt) {\n            http_params[i].name = params;\n\n            eq = params;\n            amp = strchr(params, '&'); /* Find next & in a sequence */\n            if (amp != NULL) {         /* In case we have it */\n                *amp = 0;              /* Replace it with 0 to end current param */\n                params = ++amp;        /* Go to next one */\n            } else {\n                params = NULL;\n            }\n\n            eq = strchr(eq, '='); /* Find delimiter */\n            if (eq != NULL) {\n                *eq = 0;\n                http_params[i].value = eq + 1;\n            } else {\n                http_params[i].value = NULL;\n            }\n        }\n    }\n    return cnt;\n}\n\n#if HTTP_DYNAMIC_HEADERS\n/**\n * \\brief           Prepare dynamic headers to be sent as response to user\n * \\param[in]       hs: HTTP state\n * \\param[in]       uri: Request URI excluding optional parameters\n */\nstatic void\nprepare_dynamic_headers(http_state_t* hs, const char* uri) {\n    char *ext, *u;\n    size_t i;\n\n    hs->dyn_hdr_idx = 0;\n    hs->dyn_hdr_pos = 0;\n\n    hs->dyn_hdr_strs[1] = http_dynstrs[HTTP_HDR_SERVER]; /* Set server name */\n    if (!hs->rlwesp_file_opened) { /* This should never be the case as 404.html file exists as static */\n        hs->dyn_hdr_strs[0] = http_dynstrs[HTTP_HDR_404];                     /* 404 Not Found */\n        hs->dyn_hdr_strs[HTTP_MAX_HEADERS - 1] = http_dynstrs[HTTP_HDR_HTML]; /* Content type text/html */\n    } else {\n        /*\n         * Try to find CRLFCRLF sequence on static files and remove\n         * the headers if dynamic headers are used\n         */\n        if (hs->rlwesp_file.is_static) {\n            char* crlfcrlf;\n            crlfcrlf = strstr((const char*)hs->rlwesp_file.data, CRLF CRLF);\n            if (crlfcrlf != NULL) { /* Skip header part of file */\n                hs->rlwesp_file.size -=\n                    (const char*)crlfcrlf - (const char*)hs->rlwesp_file.data + 4; /* Decrease file size first! */\n                hs->rlwesp_file.data +=\n                    (const char*)crlfcrlf - (const char*)hs->rlwesp_file.data + 4; /* Advance file pointer */\n            }\n        }\n\n        /*\n         * Process with content-length response header\n         *\n         * In case request does not include SSI parsing,\n         * script has known final content length.\n         *\n         * Include length in header output\n         */\n        hs->dyn_hdr_strs[2] = NULL; /* No content length involved */\n#if HTTP_DYNAMIC_HEADERS_CONTENT_LEN\n        if (!hs->is_ssi) {\n            sprintf(hs->dyn_hdr_cnt_len, \"Content-Length: %d\" CRLF, (int)hs->rlwesp_file.size);\n            hs->dyn_hdr_strs[2] = hs->dyn_hdr_cnt_len;\n        }\n#endif /* HTTP_DYNAMIC_HEADERS_CONTENT_LEN */\n\n        /*\n         * Determine if file is 404 or normal user file.\n         *\n         * 404 file should be in type of \"/404.xxx\" where \"xxx\" includes optional extension\n         */\n        if (strstr(uri, \"/404.\") != NULL) {                   /* Do we have a 404 in file name? */\n            hs->dyn_hdr_strs[0] = http_dynstrs[HTTP_HDR_404]; /* 404 Not found */\n        } else {\n            hs->dyn_hdr_strs[0] = http_dynstrs[HTTP_HDR_200]; /* 200 OK */\n        }\n\n        /*\n         * Try to find content type by inspecting file extensions\n         *\n         * At this point, uri should not include parameters in string as we are searching for actual file\n         *\n         * Step 1: Find file extension\n         * Step 2: Compare file extension with table of known extensions and content types\n         */\n\n        /* Step 1: Find extension of request path */\n        ext = NULL;           /* No extension on beginning */\n        u = strchr(uri, '.'); /* Find first dot in string */\n        while (u != NULL) {\n            ext = u + 1;            /* Set current u as extension but skip dot character */\n            u = strchr(u + 1, '.'); /* Find next dot */\n        }\n\n        /* Step 2: Compare extension against known pairs */\n        i = 0;\n        if (ext != NULL) { /* Do we have an extension? */\n            for (; i < LWESP_ARRAYSIZE(dynamic_headers_pairs); ++i) {\n                if (!strcmpa(ext, dynamic_headers_pairs[i].ext)) {\n                    break;\n                }\n            }\n        }\n\n        /* Finally set the output content type header */\n        if (ext != NULL && i < LWESP_ARRAYSIZE(dynamic_headers_pairs)) {\n            hs->dyn_hdr_strs[HTTP_MAX_HEADERS - 1] =\n                http_dynstrs[dynamic_headers_pairs[i].index]; /* Set response from index directly */\n        } else {\n            hs->dyn_hdr_strs[HTTP_MAX_HEADERS - 1] = http_dynstrs[HTTP_HDR_PLAIN]; /* Plain text, unknown type */\n        }\n    }\n}\n\n/**\n* \\brief           Sends dynamic headers to output before sending actual content\n* \\param[in]       hs: HTTP state\n*/\nstatic void\nsend_dynamic_headers(http_state_t* hs) {\n    size_t to_write, rem_len;\n    if (hs->dyn_hdr_idx >= HTTP_MAX_HEADERS) {\n        return;\n    }\n\n    /* Get available memory in write buffer */\n    lwesp_conn_write(hs->conn, NULL, 0, 0, &hs->conn_mem_available);\n\n    /* Try to write as much data as possible */\n    while (hs->conn_mem_available && hs->dyn_hdr_idx < HTTP_MAX_HEADERS) {\n        if (hs->dyn_hdr_strs[hs->dyn_hdr_idx] == NULL) { /* Check if string is set */\n            hs->dyn_hdr_pos = 0;                         /* Reset header position */\n            ++hs->dyn_hdr_idx;                           /* Go to next string */\n            continue;\n        }\n        rem_len =\n            strlen(&hs->dyn_hdr_strs[hs->dyn_hdr_idx][hs->dyn_hdr_pos]); /* Get remaining length of string to write */\n        to_write =\n            LWESP_MIN(hs->conn_mem_available, rem_len); /* Calculate remaining maximal number of bytes we can write */\n\n        /* Write data to connection output buffer */\n        lwesp_conn_write(hs->conn, &hs->dyn_hdr_strs[hs->dyn_hdr_idx][hs->dyn_hdr_pos], to_write, 0,\n                         &hs->conn_mem_available);\n        hs->written_total += to_write;\n\n        hs->dyn_hdr_pos += to_write; /* Advance for written position */\n        if (to_write == rem_len) {   /* Did we write everything? */\n            hs->dyn_hdr_pos = 0;     /* Reset output variable position */\n            ++hs->dyn_hdr_idx;       /* Increase header index string */\n        }\n    }\n    /*\n     * Flush data to output\n     *\n     * TODO: Do not flush it now and try to write more data together with user output?\n     */\n    //lwesp_conn_write(hs->conn, NULL, 0, 1, &hs->conn_mem_available);  /* Flush data to output */\n}\n#endif\n\n/**\n * \\brief           Get file from uri in format /folder/file?param1=value1&...\n * \\param[in]       hs: HTTP state\n * \\param[in]       uri: Input URI to get file for\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nhttp_get_file_from_uri(http_state_t* hs, const char* uri) {\n    size_t uri_len;\n\n    LWESP_MEMSET(&hs->rlwesp_file, 0x00, sizeof(hs->rlwesp_file));\n    uri_len = strlen(uri);                                 /* Get URI total length */\n    if ((uri_len == 1 && uri[0] == '/') ||                 /* Index file only requested */\n        (uri_len > 1 && uri[0] == '/' && uri[1] == '?')) { /* Index file + parameters */\n        size_t i;\n        /*\n         * Scan index files and check if there is one from user\n         * available to return as main file\n         */\n        for (i = 0; i < LWESP_ARRAYSIZE(http_index_filenames); ++i) {\n            hs->rlwesp_file_opened = http_fs_data_open_file(\n                hi, &hs->rlwesp_file, http_index_filenames[i]); /* Give me a file with desired path */\n            if (hs->rlwesp_file_opened) {                       /* Do we have a file? */\n                uri = http_index_filenames[i];                  /* Set new URI for next of this func */\n                break;\n            }\n        }\n    }\n\n    /*\n     * We still don't have a file,\n     * maybe there was a request for specific file and possible parameters\n     */\n    if (!hs->rlwesp_file_opened) {\n        char* req_params;\n        size_t params_len;\n        req_params = strchr(uri, '?'); /* Search for params delimiter */\n        if (req_params\n            != NULL) {         /* We found parameters? They should not exists in static strings or we may have buf! */\n            req_params[0] = 0; /* Reset everything at this point */\n            ++req_params;      /* Skip NULL part and go to next one */\n        }\n\n        params_len = http_get_params(req_params); /* Get request params from request */\n        if (hi != NULL && hi->cgi != NULL) {      /* Check if any user specific controls to process */\n            for (size_t i = 0; i < hi->cgi_count; ++i) {\n                if (!strcmp(hi->cgi[i].uri, uri)) {\n                    uri = hi->cgi[i].fn(http_params, params_len);\n                    break;\n                }\n            }\n        }\n        hs->rlwesp_file_opened = http_fs_data_open_file(hi, &hs->rlwesp_file, uri); /* Give me a new file now */\n    }\n\n    /*\n     * We still don't have a file!\n     * Try with 404 error page if available by user\n     */\n    if (!hs->rlwesp_file_opened) {\n        for (size_t i = 0; i < LWESP_ARRAYSIZE(http_404_uris); ++i) {\n            uri = http_404_uris[i];\n            hs->rlwesp_file_opened = http_fs_data_open_file(hi, &hs->rlwesp_file, uri); /* Get 404 error page */\n            if (hs->rlwesp_file_opened) {\n                break;\n            }\n        }\n    }\n\n    /*\n     * Check if SSI should be supported on this file\n     */\n    hs->is_ssi = 0; /* By default no SSI is supported */\n    if (hs->rlwesp_file_opened) {\n        size_t uri_len, suffix_len;\n        const char* suffix;\n\n        uri_len = strlen(uri); /* Get length of URI */\n        for (size_t i = 0; i < LWESP_ARRAYSIZE(http_ssi_suffixes); ++i) {\n            suffix = http_ssi_suffixes[i]; /* Get suffix */\n            suffix_len = strlen(suffix);   /* Get length of suffix */\n\n            if (suffix_len < uri_len && !strcmpa(suffix, &uri[uri_len - suffix_len])) {\n                hs->is_ssi = 1; /* We have a SSI tag */\n                break;\n            }\n        }\n    }\n\n#if HTTP_DYNAMIC_HEADERS\n    /*\n     * Process with dynamic headers response only\n     * if file is opened for response.\n     *\n     * If file is not opened, send default 404 resp or close connection\n     */\n    prepare_dynamic_headers(hs, uri);\n#endif /* HTTP_DYNAMIC_HEADERS */\n\n    return hs->rlwesp_file_opened;\n}\n\n#if HTTP_SUPPORT_POST\n/**\n * \\brief           Send the received pbuf to user space\n * \\param[in]       hs: HTTP state context\n * \\param[in]       pbuf: Pbuf with received data\n * \\param[in]       offset: Offset in pbuf where to start reading the buffer\n */\nstatic void\nhttp_post_send_to_user(http_state_t* hs, lwesp_pbuf_p pbuf, size_t offset) {\n    lwesp_pbuf_p new_pbuf;\n\n    if (hi == NULL || hi->post_data_fn == NULL) {\n        return;\n    }\n\n    new_pbuf = lwesp_pbuf_skip(pbuf, offset, &offset); /* Skip pbufs and create this one */\n    if (new_pbuf != NULL) {\n        lwesp_pbuf_advance(new_pbuf, offset); /* Advance pbuf for remaining bytes */\n\n        hi->post_data_fn(hs, new_pbuf); /* Notify user with data */\n    }\n}\n#endif /* HTTP_SUPPORT_POST */\n\n/**\n * \\brief           Read next part of response file\n * \\param[in]       hs: HTTP state\n */\nstatic uint32_t\nread_rlwesp_file(http_state_t* hs) {\n    uint32_t len = 0;\n\n    if (!hs->rlwesp_file_opened) { /* File should be opened at this point! */\n        return 0;\n    }\n\n    hs->buff_ptr = 0; /* Reset buffer pointer at this point */\n\n    /* Is our memory set for some reason? */\n    if (hs->buff != NULL) {                      /* Do we have already something in our buffer? */\n        if (!hs->rlwesp_file.is_static) {        /* If file is not static... */\n            lwesp_mem_free_s((void**)&hs->buff); /* ...free the memory... */\n        }\n        hs->buff = NULL; /* ...and reset pointer */\n    }\n\n    /*\n     * Is buffer set to NULL?\n     * In this case set a pointer to static memory in case of static file or\n     * allocate memory for dynamic file and read it\n     */\n    if (hs->buff == NULL) { /* Do we have a buffer empty? */\n        len = http_fs_data_read_file(hi, &hs->rlwesp_file, NULL, 0,\n                                     NULL); /* Get number of remaining bytes to read in file */\n        if (len > 0) { /* Is there anything to read? On static files, this should be valid only once */\n            if (hs->rlwesp_file.is_static) { /* On static files... */\n                len = http_fs_data_read_file(hi, &hs->rlwesp_file, (void**)&hs->buff, len,\n                                             NULL); /* ...simply set file pointer */\n                hs->buff_len = len;                 /* Set buffer length */\n                if (len == 0) {                     /* Empty read? */\n                    hs->buff = NULL;                /* Reset buffer */\n                }\n            } else {\n                if (len > LWESP_CFG_CONN_MAX_DATA_LEN) { /* Limit to maximal length */\n                    len = LWESP_CFG_CONN_MAX_DATA_LEN;\n                }\n                hs->buff_ptr = 0; /* Reset read pointer */\n                do {\n                    hs->buff_len = len;\n                    hs->buff = (const void*)lwesp_mem_malloc(sizeof(*hs->buff) * hs->buff_len);\n                    if (hs->buff != NULL) { /* Is memory ready? */\n                        /* Read file directly and stop everything */\n                        if (!http_fs_data_read_file(hi, &hs->rlwesp_file, (void**)&hs->buff, hs->buff_len, NULL)) {\n                            lwesp_mem_free_s((void**)&hs->buff);\n                        }\n                        break;\n                    }\n                } while ((len >>= 1) > 64);\n            }\n        }\n    }\n\n    return hs->buff != NULL; /* Do we have our memory ready? */\n}\n\n/**\n * \\brief           Send response using SSI processing\n * \\param[in]       hs: HTTP state\n */\nstatic void\nsend_response_ssi(http_state_t* hs) {\n    uint8_t reset = 0;\n    uint8_t ch;\n\n    LWESP_DEBUGF(LWESP_CFG_DBG_SERVER_TRACE, \"[HTTP SERVER] processing with SSI\\r\\n\");\n\n    /* First get available memory in output buffer */\n    lwesp_conn_write(hs->conn, NULL, 0, 0,\n                     &hs->conn_mem_available); /* Get available memory and/or create a new buffer if possible */\n\n    /*\n     * Check if we have to send temporary buffer,\n     * because of wrong TAG format set by user\n     */\n    if (hs->ssi_tag_buff_written < hs->ssi_tag_buff_ptr) { /* Do we have to send something from SSI buffer? */\n        size_t len;\n        len = LWESP_MIN(hs->ssi_tag_buff_ptr - hs->ssi_tag_buff_written, hs->conn_mem_available);\n        if (len > 0) { /* More data to send? */\n            lwesp_conn_write(hs->conn, &hs->ssi_tag_buff[hs->ssi_tag_buff_written], len, 0, &hs->conn_mem_available);\n            hs->written_total += len;        /* Increase total number of written elements */\n            hs->ssi_tag_buff_written += len; /* Increase total number of written SSI buffer */\n\n            if (hs->ssi_tag_buff_written == hs->ssi_tag_buff_ptr) {\n                hs->ssi_tag_buff_ptr = 0; /* Reset pointer */\n            }\n        }\n    }\n\n    /* Are we ready to read more data? */\n    if (hs->buff == NULL || hs->buff_ptr == hs->buff_len) {\n        read_rlwesp_file(hs); /* Read more file at this point */\n    }\n\n    /*\n     * Process remaining SSI tag buffer\n     * Buffer should be ready from response file function call\n     */\n    if (hs->buff != NULL) {\n        while (hs->buff_ptr < hs->buff_len && hs->conn_mem_available) { /* Process entire buffer if possible */\n            ch = hs->buff[hs->buff_ptr];                                /* Get next character */\n            switch (hs->ssi_state) {\n                case HTTP_SSI_STATE_WAIT_BEGIN: {\n                    if (ch == HTTP_SSI_TAG_START[0]) {\n                        hs->ssi_tag_buff[0] = ch;\n                        hs->ssi_tag_buff_ptr = 1;\n                        hs->ssi_state = HTTP_SSI_STATE_BEGIN;\n                    } else {\n                        reset = 1;\n                    }\n                    break;\n                }\n                case HTTP_SSI_STATE_BEGIN: {\n                    if (hs->ssi_tag_buff_ptr < HTTP_SSI_TAG_START_LEN\n                        && ch == HTTP_SSI_TAG_START[hs->ssi_tag_buff_ptr]) {\n                        hs->ssi_tag_buff[hs->ssi_tag_buff_ptr] = ch;\n                        ++hs->ssi_tag_buff_ptr;\n\n                        if (hs->ssi_tag_buff_ptr == HTTP_SSI_TAG_START_LEN) {\n                            hs->ssi_state = HTTP_SSI_STATE_TAG;\n                            hs->ssi_tag_len = 0;\n                        }\n                    } else {\n                        reset = 1;\n                    }\n                    break;\n                }\n                case HTTP_SSI_STATE_TAG: {\n                    if (ch == HTTP_SSI_TAG_END[0]) {\n                        hs->ssi_tag_buff[hs->ssi_tag_buff_ptr++] = ch;\n                        hs->ssi_state = HTTP_SSI_STATE_END;\n                    } else {\n                        if ((hs->ssi_tag_buff_ptr - HTTP_SSI_TAG_START_LEN) < HTTP_SSI_TAG_MAX_LEN) {\n                            hs->ssi_tag_buff[hs->ssi_tag_buff_ptr] = ch;\n                            ++hs->ssi_tag_buff_ptr;\n                            ++hs->ssi_tag_len;\n                        } else {\n                            reset = 1;\n                        }\n                    }\n                    break;\n                }\n                case HTTP_SSI_STATE_END: {\n                    if ((hs->ssi_tag_buff_ptr - HTTP_SSI_TAG_START_LEN - hs->ssi_tag_len) < HTTP_SSI_TAG_END_LEN\n                        && ch == HTTP_SSI_TAG_END[(hs->ssi_tag_buff_ptr - HTTP_SSI_TAG_START_LEN - hs->ssi_tag_len)]) {\n\n                        hs->ssi_tag_buff[hs->ssi_tag_buff_ptr++] = ch;\n\n                        /* Did we reach end of tag and are ready to get replacement from user? */\n                        if (hs->ssi_tag_buff_ptr == (HTTP_SSI_TAG_START_LEN + hs->ssi_tag_len + HTTP_SSI_TAG_END_LEN)) {\n                            hs->ssi_tag_buff[HTTP_SSI_TAG_START_LEN + hs->ssi_tag_len] = 0;\n\n                            hs->ssi_tag_process_more = 0;\n                            if (hi != NULL && hi->ssi_fn != NULL) {\n                                /* Call user function */\n                                hs->ssi_tag_process_more =\n                                    !hi->ssi_fn(hs, &hs->ssi_tag_buff[HTTP_SSI_TAG_START_LEN], hs->ssi_tag_len);\n                            }\n                            hs->ssi_state = HTTP_SSI_STATE_WAIT_BEGIN;\n                            hs->ssi_tag_len = 0;\n                            hs->ssi_tag_buff_ptr = 0; /* Manually reset everything to prevent anything to be sent */\n                        }\n                    } else {\n                        reset = 1;\n                    }\n                    break;\n                }\n                default: break;\n            }\n\n            if (reset) {\n                reset = 0;\n                if (hs->ssi_tag_buff_ptr > 0) { /* Do we have to send something from temporary TAG buffer? */\n                    size_t len;\n\n                    len = LWESP_MIN(hs->ssi_tag_buff_ptr, hs->conn_mem_available);\n                    lwesp_conn_write(hs->conn, hs->ssi_tag_buff, len, 0, &hs->conn_mem_available);\n                    hs->written_total += len;       /* Increase total written length */\n                    hs->ssi_tag_buff_written = len; /* Set length of number of written buffer */\n                    if (len == hs->ssi_tag_buff_ptr) {\n                        hs->ssi_tag_buff_ptr = 0;\n                    }\n                }\n                if (hs->conn_mem_available > 0) { /* Is there memory to write a current byte? */\n                    lwesp_conn_write(hs->conn, &ch, 1, 0, &hs->conn_mem_available);\n                    ++hs->written_total;\n                    ++hs->buff_ptr;\n                }\n                hs->ssi_state = HTTP_SSI_STATE_WAIT_BEGIN;\n            } else {\n                ++hs->buff_ptr;\n            }\n        }\n    }\n    lwesp_conn_write(hs->conn, NULL, 0, 1, &hs->conn_mem_available); /* Flush to output if possible */\n}\n\n/**\n * \\brief           Send more data without SSI tags parsing\n * \\param[in]       hs: HTTP state\n */\nstatic void\nsend_response_no_ssi(http_state_t* hs) {\n    LWESP_DEBUGF(LWESP_CFG_DBG_SERVER_TRACE, \"[HTTP SERVER] processing NO SSI\\r\\n\");\n\n    /* Are we ready to read more? */\n    if (hs->buff == NULL || hs->written_total == hs->sent_total) {\n        read_rlwesp_file(hs); /* Try to read response file */\n    }\n\n    /*\n     * Do we have a file?\n     * Static file should be processed only once at the end\n     * as entire memory can be send at a time\n     */\n    if (hs->buff != NULL) {\n        const uint8_t* b = hs->buff;\n        size_t blen = hs->buff_len;\n\n#if HTTP_DYNAMIC_HEADERS\n        /*\n         * In case we still have remaining memory from dynamic headers write,\n         * try to write more to fill packet to send as much data as possible at single time\n         */\n        if (hs->conn_mem_available > 0) {\n            size_t to_write;\n            to_write = LWESP_MIN(hs->buff_len, hs->conn_mem_available);\n            lwesp_conn_write(hs->conn, b, to_write, 0, &hs->conn_mem_available);\n            hs->written_total += to_write;\n            blen -= to_write;\n            b += to_write;\n        }\n#endif /* HTTP_DYNAMIC_HEADERS */\n\n        if (blen > 0) {\n            if (lwesp_conn_send(hs->conn, b, blen, NULL, 0) == lwespOK) {\n                hs->written_total += blen; /* Set written total length */\n            }\n        }\n    }\n}\n\n/**\n * \\brief           Send response back to connection\n * \\param[in]       hs: HTTP state\n * \\param[in]       ft: Flag indicating function was called first time to send the response\n */\nstatic void\nsend_response(http_state_t* hs, uint8_t ft) {\n    uint8_t close = 0;\n\n    LWESP_UNUSED(ft);\n\n    if (!hs->process_resp || /* Not yet ready to process response? */\n        (hs->written_total > 0\n         && hs->written_total != hs->sent_total)) { /* Did we wrote something but didn't send yet? */\n        return;\n    }\n\n    /*\n     * Do we have a file ready to be send?\n     * At this point it should be opened already if request method is valid\n     */\n    if (hs->rlwesp_file_opened) {\n#if HTTP_DYNAMIC_HEADERS\n        uint8_t send_dyn_head = 0;\n        /*\n         * Before processing actual output, make sure\n         * dynamic headers were sent to client output\n         */\n        if (hs->dyn_hdr_idx < HTTP_MAX_HEADERS) {\n            send_dynamic_headers(hs); /* Send dynamic headers to output */\n            send_dyn_head = 1;\n        }\n        if (hs->dyn_hdr_idx >= HTTP_MAX_HEADERS)\n#endif /* HTTP_DYNAMIC_HEADERS */\n        {\n            /* Process and send more data to output */\n            if (hs->is_ssi) {          /* In case of SSI request, process data using SSI */\n                send_response_ssi(hs); /* Send response using SSI parsing */\n            } else {\n                send_response_no_ssi(hs); /* Send response without SSI parsing */\n            }\n\n            /*\n             * Shall we hare directly close a connection if buff is NULL?\n             * Maybe check first if problem was memory and try next time again\n             *\n             * Currently this is a solution to close the file\n             */\n            if (hs->buff == NULL) { /* Sent everything or problem somehow? */\n                close = 1;\n            }\n        }\n#if HTTP_DYNAMIC_HEADERS\n        /*\n         * If we were sending header data,\n         * force flush, no matter on a fact if response\n         * functions did flush it already.\n         *\n         * Maybe response functions didn't response anything?\n         */\n        if (send_dyn_head) {\n            lwesp_conn_write(hs->conn, NULL, 0, 1, &hs->conn_mem_available);\n        }\n#endif /* HTTP_DYNAMIC_HEADERS */\n    } else {\n#if HTTP_USE_METHOD_NOTALLOWED_RESP\n        if (hs->req_method == HTTP_METHOD_NOTALLOWED) { /* Is request method not allowed? */\n            lwesp_conn_send(hs->conn, http_data_method_not_allowed, sizeof(http_data_method_not_allowed) - 1, NULL, 0);\n            /* Don't set number of bytes written to prevent recursion */\n        } else\n#endif /* HTTP_USE_METHOD_NOT_ALLOWED_RESPONSE */\n        {\n            /*\n             * Since user should include _fs.c file and 404 response is part of it,\n             * we should never enter here. However in case user does\n             * hard modifications, we may enter here.\n             *\n             * Think about \"hard\" 404 response before closing?\n             */\n        }\n        close = 1; /* Close connection, file is not opened */\n    }\n\n    if (close) {\n        lwesp_conn_close(hs->conn, 0); /* Close the connection as no file opened in this case */\n    }\n}\n\n/**\n * \\brief           Server connection callback\n * \\param[in]       evt: Pointer to callback data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nhttp_evt(lwesp_evt_t* evt) {\n    uint8_t close = 0;\n    lwesp_conn_p conn;\n    http_state_t* hs = NULL;\n\n    conn = lwesp_conn_get_from_evt(evt); /* Get connection from event */\n    if (conn != NULL) {\n        hs = lwesp_conn_get_arg(conn); /* Get connection argument */\n    }\n    switch (lwesp_evt_get_type(evt)) {\n        /* A new connection just became active */\n        case LWESP_EVT_CONN_ACTIVE: {\n            LWESP_DEBUGF(LWESP_CFG_DBG_SERVER_TRACE_WARNING, \"[HTTP SERVER] Conn %d active\\r\\n\",\n                         (int)lwesp_conn_getnum(conn));\n            hs = lwesp_mem_calloc(1, sizeof(*hs));\n            if (hs != NULL) {\n                hs->conn = conn;              /* Save connection handle */\n                lwesp_conn_set_arg(conn, hs); /* Set argument for connection */\n            } else {\n                LWESP_DEBUGF(LWESP_CFG_DBG_SERVER_TRACE_WARNING,\n                             \"[HTTP SERVER] Cannot allocate memory for http state\\r\\n\");\n                close = 1; /* No memory, close the connection */\n            }\n            break;\n        }\n\n        /* Data received on connection */\n        case LWESP_EVT_CONN_RECV: {\n            lwesp_pbuf_p p;\n            size_t pos;\n\n            p = lwesp_evt_conn_recv_get_buff(evt); /* Get received buffer */\n            if (hs != NULL) {                      /* Do we have a valid http state? */\n                /*\n                 * Check if we have to receive headers data first\n                 * before we can proceed with everything else\n                 */\n                if (!hs->headers_received) { /* Are we still waiting for headers data? */\n                    if (hs->p == NULL) {\n                        hs->p = p; /* This is a first received packet */\n                    } else {\n                        lwesp_pbuf_cat(hs->p, p); /* Add new packet to the end of linked list of recieved data */\n                    }\n                    lwesp_pbuf_ref(p); /* Increase reference counter */\n\n                    /*\n                     * Check if headers are fully received.\n                     * To know this, search for \"\\r\\n\\r\\n\" sequence in received data\n                     */\n                    if ((pos = lwesp_pbuf_strfind(hs->p, CRLF CRLF, 0)) != LWESP_SIZET_MAX) {\n                        uint8_t http_uri_parsed;\n                        LWESP_DEBUGF(LWESP_CFG_DBG_SERVER_TRACE, \"[HTTP SERVER] HTTP headers received!\\r\\n\");\n                        hs->headers_received = 1; /* Flag received headers */\n\n                        /* Parse the URI, process request and open response file */\n                        http_uri_parsed = http_parse_uri(hs->p) == lwespOK;\n\n#if HTTP_SUPPORT_POST\n                        /* Check for request method used on this connection */\n                        if (!lwesp_pbuf_strcmp(hs->p, \"POST \", 0)) {\n                            size_t data_pos, pbuf_total_len;\n\n                            hs->req_method = HTTP_METHOD_POST; /* Save a new value as POST method */\n\n                            /*\n                             * At this point, all headers are received\n                             * We can start process them into something useful\n                             */\n                            data_pos = pos + 4; /* Ignore 4 bytes of CRLF sequence */\n\n                            /*\n                             * Try to find content length on this request\n                             * search for 2 possible values \"Content-Length\" or \"content-length\" parameters\n                             */\n                            hs->content_length = 0;\n                            if (((pos = lwesp_pbuf_strfind(hs->p, \"Content-Length:\", 0)) != LWESP_SIZET_MAX)\n                                || (pos = lwesp_pbuf_strfind(hs->p, \"content-length:\", 0)) != LWESP_SIZET_MAX) {\n                                uint8_t ch;\n\n                                pos += 15; /* Skip this part */\n                                if (lwesp_pbuf_get_at(hs->p, pos, &ch) && ch == ' ') {\n                                    ++pos;\n                                }\n                                lwesp_pbuf_get_at(hs->p, pos, &ch);\n                                while (ch >= '0' && ch <= '9') {\n                                    hs->content_length = 10 * hs->content_length + (ch - '0');\n                                    ++pos;\n                                    if (!lwesp_pbuf_get_at(hs->p, pos, &ch)) {\n                                        break;\n                                    }\n                                }\n                            }\n\n                            /* Check if we are expecting any data on POST request */\n                            if (hs->content_length > 0) {\n                                /*\n                                 * Call user POST start method here\n                                 * to notify him to prepare himself to receive POST data\n                                 */\n                                if (hi != NULL && hi->post_start_fn != NULL) {\n                                    hi->post_start_fn(hs, http_uri, hs->content_length);\n                                }\n\n                                /*\n                                 * Check if there is anything to send already\n                                 * to user from data part of request\n                                 */\n                                pbuf_total_len =\n                                    lwesp_pbuf_length(hs->p, 1); /* Get total length of current received pbuf */\n                                if ((pbuf_total_len - data_pos) > 0) {\n                                    hs->content_received = pbuf_total_len - data_pos;\n\n                                    /* Send data to user */\n                                    http_post_send_to_user(hs, hs->p, data_pos);\n\n                                    /*\n                                     * Did we receive everything in single packet?\n                                     * Close POST loop at this point and notify user\n                                     */\n                                    if (hs->content_received >= hs->content_length) {\n                                        hs->process_resp = 1; /* Process with response to user */\n                                        if (hi != NULL && hi->post_end_fn != NULL) {\n                                            hi->post_end_fn(hs);\n                                        }\n                                    }\n                                }\n                            } else {\n                                hs->process_resp = 1;\n                            }\n                        } else\n#else  /* HTTP_SUPPORT_POST */\n                        LWESP_UNUSED(pos);\n#endif /* !HTTP_SUPPORT_POST */\n                        {\n                            if (!lwesp_pbuf_strcmp(hs->p, \"GET \", 0)) {\n                                hs->req_method = HTTP_METHOD_GET;\n                                hs->process_resp = 1; /* Process with response to user */\n                            } else {\n                                hs->req_method = HTTP_METHOD_NOTALLOWED;\n                                hs->process_resp = 1;\n                            }\n                        }\n\n                        /*\n                         * If uri was parsed succssfully and if method is allowed,\n                         * then open and prepare file for future response\n                         */\n                        if (http_uri_parsed && hs->req_method != HTTP_METHOD_NOTALLOWED) {\n                            http_get_file_from_uri(hs, http_uri); /* Open file */\n                        }\n                    }\n                } else {\n#if HTTP_SUPPORT_POST\n                    /*\n                     * We are receiving request data now\n                     * as headers are already received\n                     */\n                    if (hs->req_method == HTTP_METHOD_POST) {\n                        /* Did we receive all the data on POST? */\n                        if (hs->content_received < hs->content_length) {\n                            size_t tot_len;\n\n                            tot_len = lwesp_pbuf_length(p, 1); /* Get length of pbuf */\n                            hs->content_received += tot_len;\n\n                            http_post_send_to_user(hs, p, 0); /* Send data directly to user */\n\n                            /* Check if everything received */\n                            if (hs->content_received >= hs->content_length) {\n                                hs->process_resp = 1; /* Process with response to user */\n\n                                /* Stop the response part here! */\n                                if (hi != NULL && hi->post_end_fn) {\n                                    hi->post_end_fn(hs);\n                                }\n                            }\n                        }\n                    } else\n#endif /* HTTP_SUPPORT_POST */\n                    {\n                        /* Protocol violation at this point! */\n                    }\n                }\n\n                /* Do the processing on response */\n                if (hs->process_resp) {\n                    send_response(hs, 1); /* Send the response data */\n                }\n            } else {\n                close = 1;\n            }\n            lwesp_conn_recved(conn, p); /* Notify stack about received data */\n            break;\n        }\n\n        /* Data send event */\n        case LWESP_EVT_CONN_SEND: {\n            size_t len;\n            lwespr_t res;\n            res = lwesp_evt_conn_send_get_result(evt);\n            if (res == lwespOK && hs != NULL) {\n                len = lwesp_evt_conn_send_get_length(evt); /* Get length */\n                LWESP_DEBUGF(LWESP_CFG_DBG_SERVER_TRACE, \"[HTTP SERVER] data sent with %d bytes\\r\\n\", (int)len);\n                hs->sent_total += len; /* Increase number of bytes sent */\n                send_response(hs, 0);  /* Send more data if possible */\n            } else {\n                LWESP_DEBUGW(LWESP_CFG_DBG_SERVER_TRACE_DANGER, res != lwespOK,\n                             \"[HTTP SERVER] data send error. Closing connection..\\r\\n\");\n                close = 1;\n            }\n            break;\n        }\n\n        /* Connection was just closed, either forced by user or by remote side */\n        case LWESP_EVT_CONN_CLOSE: {\n            LWESP_DEBUGF(LWESP_CFG_DBG_SERVER_TRACE, \"[HTTP SERVER] connection closed\\r\\n\");\n            if (hs != NULL) {\n#if HTTP_SUPPORT_POST\n                if (hs->req_method == HTTP_METHOD_POST) {\n                    if (hs->content_received < hs->content_length) {\n                        if (hi != NULL && hi->post_end_fn) {\n                            hi->post_end_fn(hs);\n                        }\n                    }\n                }\n#endif /* HTTP_SUPPORT_POST */\n                if (hs->p != NULL) {\n                    lwesp_pbuf_free_s(&hs->p); /* Free packet buffer */\n                }\n                if (hs->rlwesp_file_opened) { /* Is file opened? */\n                    uint8_t is_static = hs->rlwesp_file.is_static;\n                    http_fs_data_close_file(hi, &hs->rlwesp_file); /* Close file at this point */\n                    if (!is_static && hs->buff != NULL) {\n                        lwesp_mem_free_s((void**)&hs->buff);\n                    }\n                    hs->rlwesp_file_opened = 0; /* File is not opened anymore */\n                }\n                lwesp_mem_free_s((void**)&hs);\n            }\n            break;\n        }\n\n        /* Poll the connection */\n        case LWESP_EVT_CONN_POLL: {\n            if (hs != NULL) {\n                send_response(hs, 0); /* Send more data if possible */\n            } else {\n                close = 1;\n            }\n            break;\n        }\n        default: break;\n    }\n\n    if (close) {                   /* Do we have to close a connection? */\n        lwesp_conn_close(conn, 0); /* Close a connection */\n    }\n\n    return lwespOK;\n}\n\n/**\n * \\brief           Initialize HTTP server at specific port\n * \\param[in]       init: Initialization structure for server\n * \\param[in]       port: Port for HTTP server, usually 80\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_http_server_init(const http_init_t* init, lwesp_port_t port) {\n    lwespr_t res;\n    if ((res = lwesp_set_server(1, port, LWESP_CFG_MAX_CONNS, 80, http_evt, NULL, NULL, 1)) == lwespOK) {\n        hi = init;\n    }\n    return res;\n}\n\n/**\n * \\brief           Write data directly to connection from callback\n * \\note            This function may only be called from SSI callback function for HTTP server\n * \\param[in]       hs: HTTP state\n * \\param[in]       data: Data to write\n * \\param[in]       len: Length of bytes to write\n * \\return          Number of bytes written\n */\nsize_t\nlwesp_http_server_write(http_state_t* hs, const void* data, size_t len) {\n    lwesp_conn_write(hs->conn, data, len, 0, &hs->conn_mem_available);\n    hs->written_total += len; /* Increase total length */\n    return len;\n}\n"
  },
  {
    "path": "lwesp/src/apps/http_server/lwesp_http_server_fs.c",
    "content": "/**\n * \\file            lwesp_http_server_fs.c\n * \\brief           HTTP server file system wrapper\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/apps/lwesp_http_server.h\"\n#include \"lwesp/lwesp_mem.h\"\n\n/* Number of opened files in system */\nextern uint16_t http_fs_opened_files_cnt;\n\n#if HTTP_USE_DEFAULT_STATIC_FILES\n/**\n * \\brief           Default index.html file including response headers\n */\nstatic const uint8_t responseData[] =\n    \"\"\n    \"HTTP/1.1 200 OK\\r\\n\"\n    \"Server: \" HTTP_SERVER_NAME \"\\r\\n\"\n    \"Content-Type: text/html\\r\\n\"\n    \"\\r\\n\"\n    \"<html>\\n\"\n    \"   <head>\\n\"\n    \"       <title><!--#title--></title>\\n\"\n    \"       <meta http-equiv=\\\"Refresh\\\" content=\\\"1\\\" />\\n\"\n    \"       <script src=\\\"https://ajax.googleapis.com/ajax/libs/jquery/3.2.1/jquery.min.js\\\"></script>\\n\"\n    \"       <script src=\\\"/js/js.js\\\" type=\\\"text/javascript\\\"></script>\\n\"\n    \"       <link rel=\\\"stylesheet\\\" \"\n    \"href=\\\"https://maxcdn.bootstrapcdn.com/bootstrap/4.0.0-beta.2/css/bootstrap.min.css\\\" \"\n    \"integrity=\\\"sha384-PsH8R72JQ3SOdhVi3uxftmaW6Vc51MKb0q5P2rRUpPvrszuE4W1povHYgTpBfshb\\\" crossorigin=\\\"anonymous\\\" \"\n    \"/>\\n\"\n    \"       <link rel=\\\"stylesheet\\\" type=\\\"text/css\\\" href=\\\"/css/style.css\\\" />\\n\"\n    \"   </head>\\n\"\n    \"   <body>\\n\"\n    \"       <div class=\\\"container\\\">\\n\"\n    \"           <h1>Welcome to web server hosted by ESP8266 Wi-Fi module!</h1>\\n\"\n    \"       </div>\\n\"\n    \"       <div id=\\\"maindiv\\\"></div>\"\n    \"       <footer>\\n\"\n    \"           <div class=\\\"container\\\">\\n\"\n    \"               Copyright &copy; 2017. All rights reserved. Webserver is hosted on ESP8266.\\n\"\n    \"           </div>\\n\"\n    \"       </footer>\\n\"\n    \"   </body>\\n\"\n    \"</html>\\n\";\n\n/**\n * \\brief           Default CSS response besides bootstrap response\n */\nstatic const uint8_t responseData_css[] =\n    \"\"\n    \"HTTP/1.1 200 OK\\r\\n\"\n    \"Server: \" HTTP_SERVER_NAME \"\\r\\n\"\n    \"Content-Type: text/css\\r\\n\"\n    \"\\r\\n\"\n    \"html, body { margin: 0; padding: 0; color: blue; font-family: Arial, Tahoma; }\\r\\n\"\n    \"h1 { font-size: 22px; }\\n\"\n    \"footer .container { width: 1000px; padding: 6px 3px; border: 1px solid #000000; font-size: 11px; }\\n\"\n    \"footer { position: fixed; bottom: 0; width: 100%; background: brown; color: #DDDDDD; }\\n\"\n    \"\";\n\n/**\n * \\brief           Default static javascript file\n *\n *                  Script will write a paragraph using jQuery to main div\n */\nstatic const uint8_t responseData_js1[] =\n    \"\"\n    \"HTTP/1.1 200 OK\\r\\n\"\n    \"Server: \" HTTP_SERVER_NAME \"\\r\\n\"\n    \"Content-Type: text/javascript\\r\\n\"\n    \"\\r\\n\"\n    \"jQuery(document).ready(function() {\\n\"\n    \"   jQuery(\\\"#maindiv\\\").append(\\\"<p>This paragraphs was written using jQuery</p>\\\");\\n\"\n    \"})\\n\";\n#endif /* HTTP_USE_DEFAULT_STATIC_FILES */\n\n/**\n * \\brief           Default 404 file\n */\nstatic const uint8_t responseData_404[] = \"\"\n                                          \"HTTP/1.1 404 Not Found\\r\\n\"\n                                          \"Server: \" HTTP_SERVER_NAME \"\\r\\n\"\n                                          \"Content-Type: text/html\\r\\n\"\n                                          \"\\r\\n\"\n                                          \"<html><body><h1>404 Page not found!</h1></body></html>\\n\";\n\n/**\n * \\brief           List of dummy files for output on user request\n */\nconst http_fs_file_table_t http_fs_static_files[] = {\n#if HTTP_USE_DEFAULT_STATIC_FILES\n    {\"/index.html\", responseData, sizeof(responseData) - 1},\n    {\"/index.shtml\", responseData, sizeof(responseData) - 1},\n    {\"/css/style.css\", responseData_css, sizeof(responseData_css) - 1},\n    {\"/js/js.js\", responseData_js1, sizeof(responseData_js1) - 1},\n#endif /* HTTP_USE_DEFAULT_STATIC_FILES */\n    {\"/404.html\", responseData_404, sizeof(responseData_404) - 1},\n};\n\n/**\n * \\brief           Open file from file system\n * \\param[in]       hi: HTTP init structure\n * \\param[in]       file: Pointer to file structure\n * \\param[in]       path: File path to open\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nhttp_fs_data_open_file(const http_init_t* hi, http_fs_file_t* file, const char* path) {\n    uint8_t i, res;\n\n    file->fptr = 0;\n    if (hi != NULL && hi->fs_open != NULL) {              /* Is user defined file system ready? */\n        file->rem_open_files = &http_fs_opened_files_cnt; /* Set pointer to opened files */\n        res = hi->fs_open(file, path);                    /* Try to read file from user file system */\n        if (res) {\n            ++http_fs_opened_files_cnt; /* Increase number of opened files */\n\n            file->is_static = 0; /* File is not static */\n            return 1;            /* File is opened! */\n        }\n    }\n\n    /*\n     * Try to open static file if available\n     */\n    for (i = 0; i < LWESP_ARRAYSIZE(http_fs_static_files); ++i) {\n        if (path != NULL && !strcmp(http_fs_static_files[i].path, path)) {\n            LWESP_MEMSET(file, 0x00, sizeof(*file));\n\n            file->size = http_fs_static_files[i].size;\n            file->data = (uint8_t*)http_fs_static_files[i].data;\n            file->is_static = 1; /* Set to 0 for testing purposes */\n            return 1;\n        }\n    }\n    return 0;\n}\n\n/**\n * \\brief           Read part of file or check if we have more data to read\n * \\param[in]       hi: HTTP init structure\n * \\param[in]       file: File handle\n * \\param[in]       buff: Pointer to buffer to save read data\n * \\param[in]       btr: Number of bytes to read and write to buffer\n * \\param[out]      br: Pointer to save number of bytes read to buffer\n * \\return          Number of bytes read or number of remaining bytes ready to be read\n */\nuint32_t\nhttp_fs_data_read_file(const http_init_t* hi, http_fs_file_t* file, void** buff, size_t btr, size_t* br) {\n    uint32_t len;\n\n    len = file->size - file->fptr;                      /* Calculate remaining length */\n    if (buff == NULL) {                                 /* If there is no buffer */\n        if (file->is_static) {                          /* Check static file */\n            return len;                                 /* Simply return difference */\n        } else if (hi != NULL && hi->fs_read != NULL) { /* Check for read function */\n            return hi->fs_read(file, NULL, 0);          /* Call a function for dynamic file check */\n        }\n        return 0; /* No bytes to read */\n    }\n\n    len = LWESP_MIN(btr, len);                  /* Get number of bytes we can read */\n    if (file->is_static) {                      /* Is file static? */\n        *buff = (void*)&file->data[file->fptr]; /* Set a new address pointer only */\n    } else if (hi != NULL && hi->fs_read != NULL) {\n        len = hi->fs_read(file, *buff, len); /* Read and return number of bytes read */\n    } else {\n        return 0;\n    }\n    file->fptr += len; /* Incrase current file pointer */\n    if (br != NULL) {\n        *br = len;\n    }\n    return len;\n}\n\n/**\n * \\brief           Close file handle\n * \\param[in]       hi: HTTP init structure\n * \\param[in]       file: Pointer to file handle to close\n */\nvoid\nhttp_fs_data_close_file(const http_init_t* hi, http_fs_file_t* file) {\n    if (!file->is_static && hi != NULL && hi->fs_close != NULL) {\n        if (hi->fs_close(file)) {       /* Close file handle */\n            --http_fs_opened_files_cnt; /* Decrease number of files opened */\n        }\n    }\n}\n"
  },
  {
    "path": "lwesp/src/apps/http_server/lwesp_http_server_fs_fat.c",
    "content": "/**\n * \\file            lwesp_http_server_fs_fat.c\n * \\brief           FATFS library implementation for HTTP server file system\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/apps/lwesp_http_server.h\"\n#include \"lwesp/apps/lwesp_http_server_fs.h\"\n#include \"lwesp/lwesp_mem.h\"\n\n#if !__DOXYGEN__\n\n#include \"ff.h\" /* Include FATFS file system file */\n\n/* File system object handle */\nstatic FATFS fs;\n\n/* File path */\nstatic char fs_path[128];\n\n/**\n * \\brief           Open a file of specific path\n * \\param[in]       file: File structure to fill if file is successfully open\n * \\param[in]       path: File path to open in format \"/js/scripts.js\" or \"/index.html\"\n * \\return          1 on success, 0 otherwise\n */\nuint8_t\nhttp_fs_open(http_fs_file_t* file, const char* path) {\n    FIL* fil;\n\n    /* Do we have to mount our file system? */\n    if (!*file->rem_open_files) {\n        if (f_mount(&fs, \"SD:\", 1) != FR_OK) {\n            return 0;\n        }\n    }\n\n    /* Format file path in \"www\" directory of root directory */\n    sprintf(fs_path, \"SD:www%s\", path);\n\n    /* Allocate memory for FATFS file structure */\n    fil = lwesp_mem_malloc(sizeof(*fil));\n    if (fil == NULL) {\n        return 0;\n    }\n\n    /*\n     * Try to open file in read mode and\n     * set required parameters for file length\n     */\n    if (f_open(fil, fs_path, FA_READ) == FR_OK) {\n        file->arg = fil;          /* Set user file argument to FATFS file structure */\n        file->size = f_size(fil); /* Set file length, most important part */\n        return 1;\n    }\n\n    lwesp_mem_free(fil); /* We failed, free memory */\n    return 0;\n}\n\n/**\n * \\brief           Read a file content\n * \\param[in]       file: File handle to read\n * \\param[out]      buff: Buffer to read data to. When set to NULL, function should return remaining available data to read\n * \\param[in]       btr: Number of bytes to read. Has no meaning when buff = NULL\n * \\return          Number of bytes read or number of bytes available to read\n */\nuint32_t\nhttp_fs_read(http_fs_file_t* file, void* buff, size_t btr) {\n    FIL* fil;\n    UINT br;\n\n    fil = file->arg;   /* Get file argument */\n    if (fil == NULL) { /* Check if argument is valid */\n        return 0;\n    }\n\n    /*\n     * When buffer is NULL, return available\n     * length we can read in the next step\n     */\n    if (buff == NULL) {\n        return f_size(fil) - f_tell(fil);\n    }\n\n    /*\n     * Read the file and return read length\n     */\n    br = 0;\n    if (f_read(fil, buff, btr, &br) == FR_OK) {\n        return br;\n    }\n    return 0;\n}\n\n/**\n * \\brief           Close a file handle\n * \\param[in]       file: File handle\n * \\return          1 on success, 0 otherwise\n */\nuint8_t\nhttp_fs_close(http_fs_file_t* file) {\n    FIL* fil;\n\n    fil = file->arg;   /* Get file argument */\n    if (fil == NULL) { /* Check if argument is valid */\n        return 0;\n    }\n\n    f_close(fil); /* Close file */\n\n    /*\n     * At this step, check if we are last opened file\n     * and unmount system if necessary\n     */\n    if (*file->rem_open_files == 1) {\n        f_mount(NULL, \"SD:\", 1);\n    }\n    lwesp_mem_free(fil); /* Free user argument */\n\n    return 1; /* Close was successful */\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/apps/http_server/lwesp_http_server_fs_win32.c",
    "content": "/**\n * \\file            lwesp_http_server_fs_win32.c\n * \\brief           WIN32 file system implementation\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/apps/lwesp_http_server.h\"\n#include \"lwesp/apps/lwesp_http_server_fs.h\"\n#include \"lwesp/lwesp_mem.h\"\n\nstatic char fs_path[256];\n\n/**\n * \\brief           Open a file of specific path\n * \\param[in]       file: File structure to fill if file is successfully open\n * \\param[in]       path: File path to open in format \"/js/scripts.js\" or \"/index.html\"\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nhttp_fs_open(http_fs_file_t* file, const char* path) {\n    FILE* fil;\n\n    /* Format file path in \"www\" directory of root directory */\n    sprintf(fs_path, \"../../../www%s\", path);\n\n    /* Try to open file on disk as read and binary mode */\n    if (!fopen_s(&fil, fs_path, \"rb\")) {\n        file->arg = fil;\n        fseek(fil, 0, SEEK_END);\n        file->size = ftell(fil);\n        fseek(fil, 0, SEEK_SET);\n        return 1;\n    }\n    return 0;\n}\n\n/**\n * \\brief           Read a file content\n * \\param[in]       file: File handle to read\n * \\param[out]      buff: Buffer to read data to. When set to NULL, function should return remaining available data to read\n * \\param[in]       btr: Number of bytes to read. Has no meaning when buff = NULL\n * \\return          Number of bytes read or number of bytes available to read\n */\nuint32_t\nhttp_fs_read(http_fs_file_t* file, void* buff, size_t btr) {\n    FILE* fil;\n    uint32_t br;\n\n    fil = file->arg;   /* Get file argument */\n    if (fil == NULL) { /* Check if argument is valid */\n        return 0;\n    }\n\n    /*\n     * When buffer is NULL, return available\n     * length we can read in the next step\n     */\n    if (buff == NULL) {\n        uint32_t s, e;\n        s = ftell(fil);          /* Get current position */\n        fseek(fil, 0, SEEK_END); /* Go to the end */\n        e = ftell(fil);          /* Get end position */\n        fseek(fil, s, SEEK_SET); /* Set back to current position */\n        return e - s;            /* Return difference in positions */\n    }\n\n    /* Read the file and return read length */\n    br = (uint32_t)fread(buff, 1, btr, fil);\n    return br;\n}\n\n/**\n * \\brief           Close a file handle\n * \\param[in]       file: File handle\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nhttp_fs_close(http_fs_file_t* file) {\n    FILE* fil;\n\n    fil = file->arg;   /* Get file argument */\n    if (fil == NULL) { /* Check if argument is valid */\n        return 0;\n    }\n\n    fclose(fil); /* Close file */\n\n    /*\n     * At this step, check if we are last opened file\n     * and unmount system if necessary\n     */\n    if (*file->rem_open_files == 1) {}\n    return 1; /* Close was successful */\n}\n"
  },
  {
    "path": "lwesp/src/apps/mqtt/lwesp_mqtt_client.c",
    "content": "/**\n * \\file            lwesp_mqtt_client.c\n * \\brief           MQTT client\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/apps/lwesp_mqtt_client.h\"\n#include \"lwesp/lwesp.h\"\n\n/**\n * \\brief           MQTT client connection\n */\ntypedef struct lwesp_mqtt_client {\n    lwesp_conn_p conn;                    /*!< Active used connection for MQTT */\n    const lwesp_mqtt_client_info_t* info; /*!< Connection info */\n    lwesp_mqtt_state_t conn_state;        /*!< MQTT connection state */\n\n    uint32_t poll_time; /*!< Poll time, increased every 500ms */\n\n    lwesp_mqtt_evt_t evt;     /*!< MQTT event callback */\n    lwesp_mqtt_evt_fn evt_fn; /*!< Event callback function */\n\n    lwesp_buff_t tx_buff; /*!< Buffer for raw output data to transmit */\n\n    uint8_t is_sending;     /*!< Flag if we are sending data currently */\n    uint32_t sent_total;    /*!< Total number of bytes sent so far on connection */\n    uint32_t written_total; /*!< Total number of bytes written into send buffer and queued for send */\n\n    uint16_t last_packet_id; /*!< Packet ID used on last packet */\n\n    lwesp_mqtt_request_t requests[LWESP_CFG_MQTT_MAX_REQUESTS]; /*!< List of requests */\n\n    uint8_t* rx_buff;   /*!< Raw RX buffer */\n    size_t rx_buff_len; /*!< Length of raw RX buffer */\n\n    uint8_t parser_state;     /*!< Incoming data parser state */\n    uint8_t msg_hdr_byte;     /*!< Incoming message header byte */\n    uint32_t msg_rem_len;     /*!< Remaining length value of current message */\n    uint8_t msg_rem_len_mult; /*!< Multiplier for remaining length */\n    uint32_t msg_curr_pos;    /*!< Current buffer write pointer */\n\n    void* arg; /*!< User argument */\n} lwesp_mqtt_client_t;\n\n/* Tracing debug message */\n#define LWESP_CFG_DBG_MQTT_TRACE         (LWESP_CFG_DBG_MQTT | LWESP_DBG_TYPE_TRACE)\n#define LWESP_CFG_DBG_MQTT_STATE         (LWESP_CFG_DBG_MQTT | LWESP_DBG_TYPE_STATE)\n#define LWESP_CFG_DBG_MQTT_TRACE_WARNING (LWESP_CFG_DBG_MQTT | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING)\n\nstatic lwespr_t prv_mqtt_conn_cb(lwesp_evt_t* evt);\nstatic void prv_send_data(lwesp_mqtt_client_p client);\n\n/**\n * \\brief           List of MQTT message types\n */\ntypedef enum {\n    MQTT_MSG_TYPE_CONNECT = 0x01,     /*!< Client requests a connection to a server */\n    MQTT_MSG_TYPE_CONNACK = 0x02,     /*!< Acknowledge connection request */\n    MQTT_MSG_TYPE_PUBLISH = 0x03,     /*!< Publish message */\n    MQTT_MSG_TYPE_PUBACK = 0x04,      /*!< Publish acknowledgement */\n    MQTT_MSG_TYPE_PUBREC = 0x05,      /*!< Publish received */\n    MQTT_MSG_TYPE_PUBREL = 0x06,      /*!< Publish release */\n    MQTT_MSG_TYPE_PUBCOMP = 0x07,     /*!< Publish complete */\n    MQTT_MSG_TYPE_SUBSCRIBE = 0x08,   /*!< Subscribe to topics */\n    MQTT_MSG_TYPE_SUBACK = 0x09,      /*!< Subscribe acknowledgement */\n    MQTT_MSG_TYPE_UNSUBSCRIBE = 0x0A, /*!< Unsubscribe from topics */\n    MQTT_MSG_TYPE_UNSUBACK = 0x0B,    /*!< Unsubscribe acknowledgement */\n    MQTT_MSG_TYPE_PINGREQ = 0x0C,     /*!< Ping request */\n    MQTT_MSG_TYPE_PINGRESP = 0x0D,    /*!< Ping response */\n    MQTT_MSG_TYPE_DISCONNECT = 0x0E,  /*!< Disconnect notification */\n} mqtt_msg_type_t;\n\n/* List of flags for CONNECT message type */\n#define MQTT_FLAG_CONNECT_USERNAME      0x80 /*!< Packet contains username */\n#define MQTT_FLAG_CONNECT_PASSWORD      0x40 /*!< Packet contains password */\n#define MQTT_FLAG_CONNECT_WILL_RETAIN   0x20 /*!< Will retain is enabled */\n#define MQTT_FLAG_CONNECT_WILL          0x04 /*!< Packet contains will topic and will message */\n#define MQTT_FLAG_CONNECT_CLEAN_SESSION 0x02 /*!< Start with clean session of this client */\n\n/* Parser states */\n#define MQTT_PARSER_STATE_INIT          0x00 /*!< MQTT parser in initialized state */\n#define MQTT_PARSER_STATE_CALC_REM_LEN  0x01 /*!< MQTT parser in calculating remaining length state */\n#define MQTT_PARSER_STATE_READ_REM      0x02 /*!< MQTT parser in reading remaining bytes state */\n\n/* Get packet type from incoming byte */\n#define MQTT_RCV_GET_PACKET_TYPE(d)     ((mqtt_msg_type_t)(((d) >> 0x04) & 0x0F))\n#define MQTT_RCV_GET_PACKET_QOS(d)      ((lwesp_mqtt_qos_t)(((d) >> 0x01) & 0x03))\n#define MQTT_RCV_GET_PACKET_DUP(d)      (((d) >> 0x03) & 0x01)\n#define MQTT_RCV_GET_PACKET_RETAIN(d)   (((d)&0x01))\n\n/* Requests status */\n#define MQTT_REQUEST_FLAG_IN_USE        0x01 /*!< Request object is allocated and in use */\n#define MQTT_REQUEST_FLAG_PENDING       0x02 /*!< Request object is pending waiting for response from server */\n#define MQTT_REQUEST_FLAG_SUBSCRIBE     0x04 /*!< Request object has subscribe type */\n#define MQTT_REQUEST_FLAG_UNSUBSCRIBE   0x08 /*!< Request object has unsubscribe type */\n\n#if LWESP_CFG_DBG\n\n/**\n * \\brief           Convert message type into readable string for debug purpose\n * \\param[in]       msg_type: MQTT message type\n * \\return          Message type in readable string format\n */\nstatic const char*\nprv_mqtt_msg_type_to_str(mqtt_msg_type_t msg_type) {\n    static const char* strings[] = {\"UNKNOWN\",     \"CONNECT\",  \"CONNACK\", \"PUBLISH\",   \"PUBACK\",\n                                    \"PUBREC\",      \"PUBREL\",   \"PUBCOMP\", \"SUBSCRIBE\", \"SUBACK\",\n                                    \"UNSUBSCRIBE\", \"UNSUBACK\", \"PINGREQ\", \"PINGRESP\",  \"DISCONNECT\"};\n    return strings[(uint8_t)msg_type];\n}\n\n#endif /* LWESP_CFG_DBG */\n\n/**\n * \\brief           Default event callback function\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: MQTT event\n */\nstatic void\nprv_mqtt_evt_fn_default(lwesp_mqtt_client_p client, lwesp_mqtt_evt_t* evt) {\n    LWESP_UNUSED(client);\n    LWESP_UNUSED(evt);\n}\n\n/**\n * \\brief           Create new message ID\n * \\param[in]       client: MQTT client\n * \\return          New packet ID\n */\nstatic uint16_t\nprv_create_packet_id(lwesp_mqtt_client_p client) {\n    if (++client->last_packet_id == 0) {\n        client->last_packet_id = 1;\n    }\n    return client->last_packet_id;\n}\n\n/******************************************************************************************************/\n/******************************************************************************************************/\n/* MQTT requests helper function                                                                      */\n/******************************************************************************************************/\n/******************************************************************************************************/\n\n/**\n * \\brief           Create and return new request object\n * \\param[in]       client: MQTT client\n * \\param[in]       packet_id: Packet ID for QoS `1` or `2`\n * \\param[in]       arg: User optional argument for identifying packets\n * \\return          Pointer to new request ready to use or `NULL` if no available memory\n */\nstatic lwesp_mqtt_request_t*\nprv_request_create(lwesp_mqtt_client_p client, uint16_t packet_id, void* arg) {\n    lwesp_mqtt_request_t* request;\n    uint16_t i;\n\n    /* Try to find a new request which does not have IN_USE flag set */\n    for (request = NULL, i = 0; i < LWESP_CFG_MQTT_MAX_REQUESTS; ++i) {\n        if (!(client->requests[i].status & MQTT_REQUEST_FLAG_IN_USE)) {\n            request = &client->requests[i]; /* We have empty request */\n            break;\n        }\n    }\n    if (request != NULL) {\n        request->packet_id = packet_id;             /* Set request packet ID */\n        request->arg = arg;                         /* Set user argument */\n        request->status = MQTT_REQUEST_FLAG_IN_USE; /* Reset everything at this point */\n    }\n    return request;\n}\n\n/**\n * \\brief           Delete request object and make it free\n * \\param[in]       client: MQTT client\n * \\param[in]       request: Request object to delete\n */\nstatic void\nprv_request_delete(lwesp_mqtt_client_p client, lwesp_mqtt_request_t* request) {\n    request->status = 0; /* Reset status to make request unused */\n    LWESP_UNUSED(client);\n}\n\n/**\n * \\brief           Set request as pending waiting for server reply\n * \\param[in]       client: MQTT client\n * \\param[in]       request: Request object to delete\n */\nstatic void\nprv_request_set_pending(lwesp_mqtt_client_p client, lwesp_mqtt_request_t* request) {\n    request->timeout_start_time = lwesp_sys_now(); /* Set timeout start time */\n    request->status |= MQTT_REQUEST_FLAG_PENDING;  /* Set pending flag */\n    LWESP_UNUSED(client);\n}\n\n/**\n * \\brief           Get pending request by specific packet ID\n * \\param[in]       client: MQTT client\n * \\param[in]       pkt_id: Packet id to get request for. Use `-1` to get first pending request\n * \\return          Request on success, `NULL` otherwise\n */\nstatic lwesp_mqtt_request_t*\nprv_request_get_pending(lwesp_mqtt_client_p client, int32_t pkt_id) {\n    /* Try to find a new request which does not have IN_USE flag set */\n    for (size_t i = 0; i < LWESP_CFG_MQTT_MAX_REQUESTS; ++i) {\n        if ((client->requests[i].status & MQTT_REQUEST_FLAG_PENDING)\n            && (pkt_id == -1 || client->requests[i].packet_id == (uint16_t)pkt_id)) {\n            return &client->requests[i];\n        }\n    }\n    return NULL;\n}\n\n/**\n * \\brief           Send error callback to user\n * \\param[in]       client: MQTT client\n * \\param[in]       status: Request status\n * \\param[in]       arg: User argument\n */\nstatic void\nprv_request_send_err_callback(lwesp_mqtt_client_p client, uint8_t status, void* arg) {\n    if (status & MQTT_REQUEST_FLAG_SUBSCRIBE) {\n        client->evt.type = LWESP_MQTT_EVT_SUBSCRIBE;\n    } else if (status & MQTT_REQUEST_FLAG_UNSUBSCRIBE) {\n        client->evt.type = LWESP_MQTT_EVT_UNSUBSCRIBE;\n    } else {\n        client->evt.type = LWESP_MQTT_EVT_PUBLISH;\n    }\n\n    if (client->evt.type == LWESP_MQTT_EVT_PUBLISH) {\n        client->evt.evt.publish.arg = arg;\n        client->evt.evt.publish.res = lwespERR;\n    } else {\n        client->evt.evt.sub_unsub_scribed.arg = arg;\n        client->evt.evt.sub_unsub_scribed.res = lwespERR;\n    }\n    client->evt_fn(client, &client->evt);\n}\n\n/******************************************************************************************************/\n/******************************************************************************************************/\n/* MQTT buffer helper functions                                                                       */\n/******************************************************************************************************/\n/******************************************************************************************************/\n\n/**\n * \\brief           Write a fixed header part of MQTT packet to output buffer\n * \\param[in]       client: MQTT client\n * \\param[in]       type: MQTT Message type\n * \\param[in]       dup: Duplicate status when same packet is sent again\n * \\param[in]       qos: Quality of service value\n * \\param[in]       retain: Retain value\n * \\param[in]       rem_len: Remaining packet length, excluding variable length part\n */\nstatic void\nprv_write_fixed_header(lwesp_mqtt_client_p client, mqtt_msg_type_t type, uint8_t dup, lwesp_mqtt_qos_t qos,\n                       uint8_t retain, uint16_t rem_len) {\n    uint8_t b;\n\n    /*\n     * Fixed header flags according to:\n     * http://docs.oasis-open.org/mqtt/mqtt/v3.1.1/os/mqtt-v3.1.1-os.html#_Toc398718020\n     */\n    b = LWESP_U8(type) << 0x04;\n    switch (type) {\n        case MQTT_MSG_TYPE_PUBLISH:\n            b |= LWESP_U8(!!dup) << 0x03 | (LWESP_U8(qos & 0x03)) << 0x01 | LWESP_U8(!!retain);\n            break;\n        case MQTT_MSG_TYPE_PUBREL:\n        case MQTT_MSG_TYPE_SUBSCRIBE:\n        case MQTT_MSG_TYPE_UNSUBSCRIBE: b |= LWESP_U8(LWESP_MQTT_QOS_AT_LEAST_ONCE) << 0x01; break;\n        default: break;\n    }\n    lwesp_buff_write(&client->tx_buff, &b, 1); /* Write start of packet parameters */\n\n    LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] Writing packet type %s to output buffer\\r\\n\",\n                 prv_mqtt_msg_type_to_str(type));\n\n    do { /* Encode length, we must write a len byte even if 0 */\n        /*\n         * Length is encoded LSB first up to 127 (0x7F) long,\n         * where bit 7 indicates we have more data in queue for length parameter\n         */\n        b = LWESP_U8((rem_len & 0x7F) | (rem_len > 0x7F ? 0x80 : 0));\n        lwesp_buff_write(&client->tx_buff, &b, 1); /* Write single byte */\n        rem_len >>= 7;                             /* Go to next 127 bytes */\n    } while (rem_len > 0);\n}\n\n/**\n * \\brief           Write 8-bit value to output buffer\n * \\param[in]       client: MQTT client\n * \\param[in]       num: Number to write\n */\nstatic void\nprv_write_u8(lwesp_mqtt_client_p client, uint8_t num) {\n    lwesp_buff_write(&client->tx_buff, &num, 1); /* Write single byte */\n}\n\n/**\n * \\brief           Write 16-bit value in MSB first format to output buffer\n * \\param[in]       client: MQTT client\n * \\param[in]       num: Number to write\n */\nstatic void\nprv_write_u16(lwesp_mqtt_client_p client, uint16_t num) {\n    prv_write_u8(client, LWESP_U8(num >> 8));   /* Write MSB first... */\n    prv_write_u8(client, LWESP_U8(num & 0xFF)); /* ...followed by LSB */\n}\n\n/**\n * \\brief           Write raw data without length parameter to output buffer\n * \\param[in]       client: MQTT client\n * \\param[in]       data: Data to write\n * \\param[in]       len: Length of data to write\n */\nstatic void\nprv_write_data(lwesp_mqtt_client_p client, const void* data, size_t len) {\n    lwesp_buff_write(&client->tx_buff, data, len); /* Write raw data to buffer */\n}\n\n/**\n * \\brief           Check if output buffer has enough memory to handle\n *                  all bytes required to encode packet to RAW format\n *\n *                  It calculates additional bytes required to encode\n *                  remaining length itself + 1 byte for packet header\n * \\param[in]       client: MQTT client\n * \\param[in]       rem_len: Remaining length of packet\n * \\return          Number of required RAW bytes or `0` if no memory available\n */\nstatic uint16_t\nprv_output_check_enough_memory(lwesp_mqtt_client_p client, uint16_t rem_len) {\n    uint16_t total_len = rem_len + 1; /* Remaining length + first (packet start) byte */\n\n    do { /* Calculate bytes for encoding remaining length itself */\n        ++total_len;\n        rem_len >>= 7; /* Encoded with 7 bits per byte */\n    } while (rem_len > 0);\n\n    return LWESP_U16(lwesp_buff_get_free(&client->tx_buff)) >= total_len ? total_len : 0;\n}\n\n/**\n * \\brief           Write and send acknowledge/record\n * \\param[in]       client: MQTT client\n * \\param[in]       msg_type: Message type to respond\n * \\param[in]       pkt_id: Packet ID to send response for\n * \\param[in]       qos: Quality of service for packet\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nprv_write_ack_rec_rel_resp(lwesp_mqtt_client_p client, mqtt_msg_type_t msg_type, uint16_t pkt_id,\n                           lwesp_mqtt_qos_t qos) {\n    if (prv_output_check_enough_memory(client, 2)) {            /* Check memory for response packet */\n        prv_write_fixed_header(client, msg_type, 0, qos, 0, 2); /* Write fixed header with 2 more bytes for packet id */\n        prv_write_u16(client, pkt_id);                          /* Write packet ID */\n        prv_send_data(client);                                  /* Flush data to output */\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] Response %s written to output memory\\r\\n\",\n                     prv_mqtt_msg_type_to_str(msg_type));\n        return 1;\n    } else {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] No memory to write %s packet\\r\\n\",\n                     prv_mqtt_msg_type_to_str(msg_type));\n    }\n    return 0;\n}\n\n/**\n * \\brief           Write string to output buffer\n * \\param[in]       client: MQTT client\n * \\param[in]       str: String to write to buffer\n * \\param[in]       len: Length of string\n */\nstatic void\nprv_write_string(lwesp_mqtt_client_p client, const char* str, uint16_t len) {\n    prv_write_u16(client, len);                   /* Write string length */\n    lwesp_buff_write(&client->tx_buff, str, len); /* Write string to buffer */\n}\n\n/**\n * \\brief           Send the actual data to the remote\n * \\param[in]       client: MQTT client\n */\nstatic void\nprv_send_data(lwesp_mqtt_client_p client) {\n    size_t len;\n    const void* addr;\n\n    if (client->is_sending) { /* We are currently sending data */\n        return;\n    }\n\n    len = lwesp_buff_get_linear_block_read_length(&client->tx_buff); /* Get length of linear memory */\n    if (len > 0) {                                                   /* Anything to send? */\n        lwespr_t res;\n        addr = lwesp_buff_get_linear_block_read_address(&client->tx_buff); /* Get address of linear memory */\n        if ((res = lwesp_conn_send(client->conn, addr, len, NULL, 0)) == lwespOK) {\n            client->written_total += len; /* Increase number of bytes written to queue */\n            client->is_sending = 1;       /* Remember active sending flag */\n        } else {\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE_WARNING, \"[LWESP MQTT] Cannot send data with error: %d\\r\\n\",\n                         (int)res);\n        }\n    } else {\n        /*\n         * If buffer is empty, reset it to default state (read & write pointers)\n         * This is to make sure everytime function needs to send data,\n         * it can do it in single shot rather than in 2 attempts (when read > write pointer).\n         * Effectively this means faster transmission of MQTT packets and lower latency.\n         */\n        lwesp_buff_reset(&client->tx_buff);\n    }\n}\n\n/**\n * \\brief           Close a MQTT connection with server\n * \\param[in]       client: MQTT client\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nstatic lwespr_t\nprv_mqtt_close(lwesp_mqtt_client_p client) {\n    lwespr_t res = lwespERR;\n\n    if (client->conn_state != LWESP_MQTT_CONN_DISCONNECTED && client->conn_state != LWESP_MQTT_CONN_DISCONNECTING) {\n        res = lwesp_conn_close(client->conn, 0); /* Close the connection in non-blocking mode */\n        if (res == lwespOK) {\n            client->conn_state = LWESP_MQTT_CONN_DISCONNECTING;\n        }\n    }\n    return res;\n}\n\n/**\n * \\brief           Subscribe/Unsubscribe to/from MQTT topic\n * \\param[in]       client: MQTT client\n * \\param[in]       topic: MQTT topic to (un)subscribe\n * \\param[in]       qos: Quality of service, used only on subscribe part\n * \\param[in]       arg: Custom argument\n * \\param[in]       sub: Status set to `1` on subscribe or `0` on unsubscribe\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nprv_sub_unsub(lwesp_mqtt_client_p client, const char* topic, lwesp_mqtt_qos_t qos, void* arg, uint8_t sub) {\n    lwesp_mqtt_request_t* request;\n    uint32_t rem_len;\n    uint16_t len_topic, pkt_id;\n    uint8_t ret = 0;\n\n    LWESP_ASSERT(client != NULL);\n\n    if ((len_topic = LWESP_U16(strlen(topic))) == 0) {\n        return 0;\n    }\n\n    /*\n     * Calculate remaining length of packet\n     *\n     * rem_len = 2 (topic_len) + topic_len + 2 (pkt_id) + qos (if sub)\n     */\n    rem_len = 2 + len_topic + 2 + (sub ? 1 : 0);\n\n    lwesp_core_lock();\n    if (client->conn_state == LWESP_MQTT_CONNECTED\n        && prv_output_check_enough_memory(client, rem_len)) { /* Check if enough memory to write packet data */\n        pkt_id = prv_create_packet_id(client);                /* Create new packet ID */\n        request = prv_request_create(client, pkt_id, arg);    /* Create request for packet */\n\n        LWESP_DEBUGW(LWESP_CFG_DBG_MQTT_TRACE_WARNING, request == NULL, \"[LWESP MQTT] Sub unsub request is NULL\\r\\n\");\n\n        if (request != NULL) { /* Do we have a request */\n            prv_write_fixed_header(client, sub ? MQTT_MSG_TYPE_SUBSCRIBE : MQTT_MSG_TYPE_UNSUBSCRIBE, 0,\n                                   (lwesp_mqtt_qos_t)1, 0, rem_len);\n            prv_write_u16(client, pkt_id);              /* Write packet ID */\n            prv_write_string(client, topic, len_topic); /* Write topic string to packet */\n            if (sub) {                                  /* Send quality of service only on subscribe */\n                prv_write_u8(client, LWESP_MIN(LWESP_U8(qos),\n                                               LWESP_U8(LWESP_MQTT_QOS_EXACTLY_ONCE))); /* Write quality of service */\n            }\n\n            request->status |= sub ? MQTT_REQUEST_FLAG_SUBSCRIBE : MQTT_REQUEST_FLAG_UNSUBSCRIBE;\n            prv_request_set_pending(client, request); /* Set request as pending waiting for server reply */\n            prv_send_data(client);                    /* Try to send data */\n            ret = 1;\n        }\n    }\n    lwesp_core_unlock();\n    return ret;\n}\n\n/**\n * \\brief           Process incoming fully received message\n * \\param[in]       client: MQTT client\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nprv_mqtt_process_incoming_message(lwesp_mqtt_client_p client) {\n    mqtt_msg_type_t msg_type;\n    lwesp_mqtt_qos_t qos;\n    uint16_t pkt_id;\n\n    msg_type = MQTT_RCV_GET_PACKET_TYPE(client->msg_hdr_byte); /* Get packet type from message header byte */\n\n    /* Debug message */\n    LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_STATE, \"[LWESP MQTT] Processing packet type %s\\r\\n\",\n                 prv_mqtt_msg_type_to_str(msg_type));\n\n    /* Check received packet type */\n    switch (msg_type) {\n        case MQTT_MSG_TYPE_CONNACK: {\n            lwesp_mqtt_conn_status_t err = (lwesp_mqtt_conn_status_t)client->rx_buff[1];\n            if (client->conn_state == LWESP_MQTT_CONNECTING) {\n                if (err == LWESP_MQTT_CONN_STATUS_ACCEPTED) {\n                    client->conn_state = LWESP_MQTT_CONNECTED;\n                }\n                LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] CONNACK received with result: %d\\r\\n\", (int)err);\n\n                /* Notify user layer */\n                client->evt.type = LWESP_MQTT_EVT_CONNECT;\n                client->evt.evt.connect.status = err;\n                client->evt_fn(client, &client->evt);\n            } else {\n                /* Protocol violation here */\n                LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE,\n                             \"[LWESP MQTT] Protocol violation. CONNACK received when already connected!\\r\\n\");\n            }\n            break;\n        }\n        case MQTT_MSG_TYPE_PUBLISH: {\n            uint16_t topic_len, data_len;\n            uint8_t *topic, *data, dup, retain;\n\n            qos = MQTT_RCV_GET_PACKET_QOS(client->msg_hdr_byte);       /* Get QoS from received packet */\n            dup = MQTT_RCV_GET_PACKET_DUP(client->msg_hdr_byte);       /* Get duplicate flag */\n            retain = MQTT_RCV_GET_PACKET_RETAIN(client->msg_hdr_byte); /* Get retain flag */\n\n            topic_len = (client->rx_buff[0] << 8) | client->rx_buff[1];\n            topic = &client->rx_buff[2]; /* Start of topic */\n\n            data = topic + topic_len; /* Get data pointer */\n\n            /* Packet ID is only available if quality of service is not 0 */\n            if (qos > 0) {\n                pkt_id = (client->rx_buff[2 + topic_len] << 8) | client->rx_buff[2 + topic_len + 1]; /* Get packet ID */\n                data += 2; /* Increase pointer for 2 bytes */\n            } else {\n                pkt_id = 0; /* No packet ID */\n            }\n            data_len = client->msg_rem_len - (data - client->rx_buff); /* Calculate length of remaining data */\n\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE,\n                         \"[LWESP MQTT] Publish packet received on topic %.*s; QoS: %d; pkt_id: %d; data_len: %d\\r\\n\",\n                         (int)topic_len, (const char*)topic, (int)qos, (int)pkt_id, (int)data_len);\n\n            /*\n             * We have to send respond to command if\n             * Quality of Service is more than 0\n             *\n             * Response type depends on QoS and is\n             * either PUBACK or PUBREC\n             */\n            if (qos > 0) { /* We have to reply on QoS > 0 */\n                mqtt_msg_type_t resp_msg_type = qos == 1 ? MQTT_MSG_TYPE_PUBACK : MQTT_MSG_TYPE_PUBREC;\n                LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] Sending publish resp: %s on pkt_id: %d\\r\\n\",\n                             prv_mqtt_msg_type_to_str(resp_msg_type), (int)pkt_id);\n                prv_write_ack_rec_rel_resp(client, resp_msg_type, pkt_id, qos);\n            }\n\n            /* Notify application layer about received packet */\n            client->evt.type = LWESP_MQTT_EVT_PUBLISH_RECV;\n            client->evt.evt.publish_recv.topic = topic;\n            client->evt.evt.publish_recv.topic_len = topic_len;\n            client->evt.evt.publish_recv.payload = data;\n            client->evt.evt.publish_recv.payload_len = data_len;\n            client->evt.evt.publish_recv.dup = dup;\n            client->evt.evt.publish_recv.qos = qos;\n            client->evt.evt.publish_recv.retain = retain;\n            client->evt_fn(client, &client->evt);\n            break;\n        }\n        case MQTT_MSG_TYPE_PINGRESP: { /* Respond to PINGREQ received */\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] Ping response received\\r\\n\");\n\n            client->evt.type = LWESP_MQTT_EVT_KEEP_ALIVE;\n            client->evt_fn(client, &client->evt);\n            break;\n        }\n        case MQTT_MSG_TYPE_SUBACK:\n        case MQTT_MSG_TYPE_UNSUBACK:\n        case MQTT_MSG_TYPE_PUBREC:\n        case MQTT_MSG_TYPE_PUBREL:\n        case MQTT_MSG_TYPE_PUBACK:\n        case MQTT_MSG_TYPE_PUBCOMP: {\n            pkt_id = client->rx_buff[0] << 8 | client->rx_buff[1]; /* Get packet ID */\n\n            if (msg_type == MQTT_MSG_TYPE_PUBREC) { /* Publish record received from server */\n                prv_write_ack_rec_rel_resp(client, MQTT_MSG_TYPE_PUBREL, pkt_id,\n                                           (lwesp_mqtt_qos_t)1); /* Send back publish release message */\n            } else if (msg_type == MQTT_MSG_TYPE_PUBREL) {       /* Publish release was received */\n                prv_write_ack_rec_rel_resp(client, MQTT_MSG_TYPE_PUBCOMP, pkt_id,\n                                           (lwesp_mqtt_qos_t)0); /* Send back publish complete */\n            } else if (msg_type == MQTT_MSG_TYPE_SUBACK || msg_type == MQTT_MSG_TYPE_UNSUBACK\n                       || msg_type == MQTT_MSG_TYPE_PUBACK || msg_type == MQTT_MSG_TYPE_PUBCOMP) {\n                lwesp_mqtt_request_t* request;\n\n                /*\n                 * We can enter here only if we received final acknowledge\n                 * on request packets we sent first.\n                 *\n                 * At these point we should have a pending request\n                 * waiting for final acknowledge, otherwise there is protocol violation\n                 */\n                if ((request = prv_request_get_pending(client, pkt_id)) != NULL) {\n                    if (msg_type == MQTT_MSG_TYPE_SUBACK || msg_type == MQTT_MSG_TYPE_UNSUBACK) {\n                        client->evt.type =\n                            msg_type == MQTT_MSG_TYPE_SUBACK ? LWESP_MQTT_EVT_SUBSCRIBE : LWESP_MQTT_EVT_UNSUBSCRIBE;\n                        client->evt.evt.sub_unsub_scribed.arg = request->arg;\n                        client->evt.evt.sub_unsub_scribed.res = client->rx_buff[2] < 3 ? lwespOK : lwespERR;\n                        client->evt_fn(client, &client->evt);\n\n                        /*\n                         * Final acknowledge of packet received\n                         * Ack type depends on QoS level being sent to server on request\n                         */\n                    } else if (msg_type == MQTT_MSG_TYPE_PUBCOMP || msg_type == MQTT_MSG_TYPE_PUBACK) {\n                        client->evt.type = LWESP_MQTT_EVT_PUBLISH;\n                        client->evt.evt.publish.arg = request->arg;\n                        client->evt.evt.publish.res = lwespOK;\n                        client->evt_fn(client, &client->evt);\n                    }\n                    prv_request_delete(client, request); /* Delete request object */\n                } else {\n                    /* Protocol violation at this point! */\n                    LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE,\n                                 \"[LWESP MQTT] Protocol violation. Received ACK without sent packet\\r\\n\");\n                }\n            }\n            break;\n        }\n        default: return 0;\n    }\n    return 1;\n}\n\n/**\n * \\brief           Parse incoming buffer data and try to construct clean packet from it\n * \\param[in]       client: MQTT client\n * \\param[in]       pbuf: Received packet buffer with data\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nprv_mqtt_parse_incoming(lwesp_mqtt_client_p client, lwesp_pbuf_p pbuf) {\n    size_t buff_len = 0, buff_offset = 0;\n    uint8_t ch, *d;\n\n    do {\n        buff_offset += buff_len;                                      /* Calculate new offset of buffer */\n        d = lwesp_pbuf_get_linear_addr(pbuf, buff_offset, &buff_len); /* Get address pointer */\n        if (d == NULL) {\n            break;\n        }\n        for (size_t idx = 0; idx < buff_len; ++idx) { /* Process entire linear buffer */\n            ch = d[idx];\n            switch (client->parser_state) {    /* Check parser state */\n                case MQTT_PARSER_STATE_INIT: { /* We are waiting for start byte and packet type */\n                    LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_STATE,\n                                 \"[LWESP MQTT] Parser init state, received first byte of packet 0x%02X\\r\\n\",\n                                 (unsigned)ch);\n\n                    /* Save other info about message */\n                    client->msg_hdr_byte = ch;    /* Save first entry */\n                    client->msg_rem_len = 0;      /* Reset remaining length */\n                    client->msg_rem_len_mult = 0; /* Reset length multiplier */\n                    client->msg_curr_pos = 0;     /* Reset current buffer write pointer */\n\n                    client->parser_state = MQTT_PARSER_STATE_CALC_REM_LEN;\n                    break;\n                }\n                case MQTT_PARSER_STATE_CALC_REM_LEN: { /* Calculate remaining length of packet */\n                    /* Length of packet is LSB first, each consist of up to 7 bits */\n                    client->msg_rem_len |= (ch & 0x7F) << ((size_t)7 * (size_t)client->msg_rem_len_mult);\n                    ++client->msg_rem_len_mult;\n\n                    if (!(ch & 0x80)) { /* Is this last entry? */\n                        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_STATE, \"[LWESP MQTT] Remaining length received: %d bytes\\r\\n\",\n                                     (int)client->msg_rem_len);\n\n                        if (client->msg_rem_len > 0) {\n                            /*\n                             * Check if all data bytes are part of single pbuf.\n                             * this is done by check if current idx position vs length is more than expected data length\n                             * Check must be \"greater as\" due to idx currently pointing to last length byte and not beginning of data\n                             */\n                            if ((buff_len - idx) > client->msg_rem_len) {\n                                void* tmp_ptr = client->rx_buff;\n                                size_t tmp_len = client->rx_buff_len;\n\n                                /* Set new client pointer */\n                                client->rx_buff = &d[idx + 1]; /* Data are one byte after */\n                                client->rx_buff_len = client->msg_rem_len;\n\n                                prv_mqtt_process_incoming_message(client); /* Process new message */\n\n                                /* Reset to previous values */\n                                client->rx_buff = tmp_ptr;\n                                client->rx_buff_len = tmp_len;\n                                client->parser_state = MQTT_PARSER_STATE_INIT;\n\n                                idx +=\n                                    client->msg_rem_len; /* Skip data part only, idx is increased again in for loop */\n                            } else {\n                                client->parser_state = MQTT_PARSER_STATE_READ_REM;\n                            }\n                        } else {\n                            prv_mqtt_process_incoming_message(client);\n                            client->parser_state = MQTT_PARSER_STATE_INIT;\n                        }\n                    }\n                    break;\n                }\n                case MQTT_PARSER_STATE_READ_REM: { /* Read remaining bytes and write to RX buffer */\n                    /* Process only if rx buff length is big enough */\n                    if (client->msg_curr_pos < client->rx_buff_len) {\n                        client->rx_buff[client->msg_curr_pos] = ch; /* Write received character */\n                    }\n                    ++client->msg_curr_pos;\n\n                    /* We reached end of received characters? */\n                    if (client->msg_curr_pos == client->msg_rem_len) {\n                        if (client->msg_curr_pos\n                            <= client->rx_buff_len) { /* Check if it was possible to write all data to rx buffer */\n                            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_STATE,\n                                         \"[LWESP MQTT] Packet parsed and ready for processing\\r\\n\");\n\n                            prv_mqtt_process_incoming_message(client); /* Process incoming packet */\n                        } else {\n                            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE_WARNING,\n                                         \"[LWESP MQTT] Packet too big for rx buffer. Packet discarded\\r\\n\");\n                        }\n                        client->parser_state =\n                            MQTT_PARSER_STATE_INIT; /* Go to initial state and listen for next received packet */\n                    }\n                    break;\n                }\n                default: client->parser_state = MQTT_PARSER_STATE_INIT;\n            }\n        }\n    } while (buff_len > 0);\n    return 0;\n}\n\n/******************************************************************************************************/\n/******************************************************************************************************/\n/* Connection callback functions                                                                      */\n/******************************************************************************************************/\n/******************************************************************************************************/\n\n/**\n * \\brief           Callback when we are connected to MQTT server\n * \\param[in]       client: MQTT client\n */\nstatic void\nprv_mqtt_connected_cb(lwesp_mqtt_client_p client) {\n    uint16_t rem_len, len_id, len_pass = 0, len_user = 0, len_will_topic = 0, len_will_message = 0;\n    uint8_t flags = 0;\n\n    flags |= MQTT_FLAG_CONNECT_CLEAN_SESSION; /* Start as clean session */\n\n    /*\n     * Remaining length consist of fixed header data\n     * variable header and possible data\n     *\n     * Minimum length consists of 2 + \"MQTT\" (4) + protocol_level (1) + flags (1) + keep_alive (2)\n     */\n    rem_len = 10; /* Set remaining length of fixed header */\n\n    len_id = LWESP_U16(strlen(client->info->id)); /* Get client ID length */\n    rem_len += len_id + 2;                        /* Add client ID length including length entries */\n\n    if (client->info->will_topic != NULL && client->info->will_message != NULL) {\n        flags |= MQTT_FLAG_CONNECT_WILL;\n        flags |= LWESP_MIN(LWESP_U8(client->info->will_qos), 2) << 0x03; /* Set qos to flags */\n\n        len_will_topic = LWESP_U16(strlen(client->info->will_topic));\n        len_will_message = LWESP_U16(strlen(client->info->will_message));\n\n        rem_len += len_will_topic + 2;   /* Add will topic parameter */\n        rem_len += len_will_message + 2; /* Add will message parameter */\n    }\n\n    if (client->info->user != NULL) {        /* Check for username */\n        flags |= MQTT_FLAG_CONNECT_USERNAME; /* Username is included */\n\n        len_user = LWESP_U16(strlen(client->info->user)); /* Get username length */\n        rem_len += len_user + 2;                          /* Add username length including length entries */\n    }\n\n    if (client->info->pass != NULL) {        /* Check for password */\n        flags |= MQTT_FLAG_CONNECT_PASSWORD; /* Password is included */\n\n        len_pass = LWESP_U16(strlen(client->info->pass)); /* Get username length */\n        rem_len += len_pass + 2;                          /* Add password length including length entries */\n    }\n\n    if (!prv_output_check_enough_memory(client, rem_len)) { /* Is there enough memory to write everything? */\n        return;\n    }\n\n    /* Write everything to output buffer */\n    prv_write_fixed_header(client, MQTT_MSG_TYPE_CONNECT, 0, (lwesp_mqtt_qos_t)0, 0, rem_len);\n    prv_write_string(client, \"MQTT\", 4);                                    /* Protocol name */\n    prv_write_u8(client, 4);                                                /* Protocol version */\n    prv_write_u8(client, flags);                                            /* Flags for CONNECT message */\n    prv_write_u16(client, client->info->keep_alive);                        /* Keep alive timeout in units of seconds */\n    prv_write_string(client, client->info->id, len_id);                     /* This is client ID string */\n    if (flags & MQTT_FLAG_CONNECT_WILL) {                                   /* Check for will topic */\n        prv_write_string(client, client->info->will_topic, len_will_topic); /* Write topic to packet */\n        prv_write_string(client, client->info->will_message, len_will_message); /* Write message to packet */\n    }\n    if (flags & MQTT_FLAG_CONNECT_USERNAME) {                   /* Check for username */\n        prv_write_string(client, client->info->user, len_user); /* Write username to packet */\n    }\n    if (flags & MQTT_FLAG_CONNECT_PASSWORD) {                   /* Check for password */\n        prv_write_string(client, client->info->pass, len_pass); /* Write password to packet */\n    }\n\n    client->parser_state = MQTT_PARSER_STATE_INIT; /* Reset parser state */\n\n    client->poll_time = 0;                      /* Reset kep alive time */\n    client->conn_state = LWESP_MQTT_CONNECTING; /* MQTT is connecting to server */\n\n    prv_send_data(client); /* Flush and send the actual data */\n}\n\n/**\n * \\brief           Received data callback function\n * \\param[in]       client: MQTT client\n * \\param[in]       pbuf: Received packet buffer with data\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nprv_mqtt_data_recv_cb(lwesp_mqtt_client_p client, lwesp_pbuf_p pbuf) {\n    prv_mqtt_parse_incoming(client, pbuf); /* We need to process incoming data */\n    lwesp_conn_recved(client->conn, pbuf); /* Notify stack about received data */\n    return 1;\n}\n\n/**\n * \\brief           Data sent callback\n * \\param[in]       client: MQTT client\n * \\param[in]       sent_len: Number of bytes sent (or not)\n * \\param[in]       successful: Send status. Set to `1` on success or `0` if send error occurred\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nprv_mqtt_data_sent_cb(lwesp_mqtt_client_p client, size_t sent_len, uint8_t successful) {\n    lwesp_mqtt_request_t* request;\n\n    client->is_sending = 0; /* We are not sending anymore */\n    client->sent_total += sent_len;\n\n    client->poll_time = 0; /* Reset kep alive time */\n\n    /*\n     * In case transmit was not successful,\n     * start procedure to close MQTT connection\n     * and clear all pending requests in closed callback function\n     */\n    if (!successful) {\n        prv_mqtt_close(client);\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE_WARNING,\n                     \"[LWESP MQTT] Failed to send %d bytes. Manually closing down..\\r\\n\", (int)sent_len);\n        return 0;\n    }\n    lwesp_buff_skip(&client->tx_buff, sent_len); /* Skip buffer for actual sent data */\n\n    /*\n     * Check pending publish requests without QoS because there is no confirmation received by server.\n     * Use technique to count number of bytes sent versus expected number of bytes sent before we ack request sent\n     *\n     * Requests without QoS have packet id set to 0\n     */\n    while ((request = prv_request_get_pending(client, 0)) != NULL && client->sent_total >= request->expected_sent_len) {\n        void* arg = request->arg;\n\n        prv_request_delete(client, request); /* Delete request and make space for next command */\n\n        /* Call published callback */\n        client->evt.type = LWESP_MQTT_EVT_PUBLISH;\n        client->evt.evt.publish.arg = arg;\n        client->evt.evt.publish.res = lwespOK;\n        client->evt_fn(client, &client->evt);\n    }\n    prv_send_data(client); /* Try to send more */\n    return 1;\n}\n\n/**\n * \\brief           Poll for client connection\n *                  Called every LWESP_CFG_CONN_POLL_INTERVAL ms when MQTT client TCP connection is established\n * \\param[in]       client: MQTT client\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nprv_mqtt_poll_cb(lwesp_mqtt_client_p client) {\n    ++client->poll_time;\n\n    if (client->conn_state == LWESP_MQTT_CONN_DISCONNECTING) {\n        return 0;\n    }\n\n    /*\n     * Check for keep-alive time if equal or greater than\n     * keep alive time. In that case, send packet\n     * to make sure we are still alive\n     */\n    if (client->info->keep_alive /* Keep alive must be enabled */\n        /* Poll time is in units of LWESP_CFG_CONN_POLL_INTERVAL milliseconds,\n           while keep_alive is in units of seconds */\n        && (client->poll_time * LWESP_CFG_CONN_POLL_INTERVAL) >= (uint32_t)(client->info->keep_alive * 1000)) {\n\n        if (prv_output_check_enough_memory(client, 0)) { /* Check if memory available in output buffer */\n            prv_write_fixed_header(client, MQTT_MSG_TYPE_PINGREQ, 0, (lwesp_mqtt_qos_t)0, 0,\n                                   0); /* Write PINGREQ command to output buffer */\n            prv_send_data(client);     /* Force send data */\n            client->poll_time = 0;     /* Reset polling time */\n\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] Sending PINGREQ packet\\r\\n\");\n        } else {\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE_WARNING, \"[LWESP MQTT] No memory to send PINGREQ packet\\r\\n\");\n        }\n    }\n\n    /* Propagate connection poll event to */\n    client->evt.type = LWESP_MQTT_EVT_CONN_POLL;\n    client->evt_fn(client, &client->evt);\n\n    /*\n     * Process all active packets and\n     * check for timeout if there was no reply from MQTT server\n     */\n    return 1;\n}\n\n/**\n * \\brief           Connection closed callback\n * \\param[in]       client: MQTT client\n * \\param[in]       res: Result of close event\n * \\param[in]       forced: Set to `1` when closed by user\n * \\return          `1` on success, `0` otherwise\n */\nstatic uint8_t\nprv_mqtt_closed_cb(lwesp_mqtt_client_p client, lwespr_t res, uint8_t forced) {\n    lwesp_mqtt_state_t state = client->conn_state;\n    lwesp_mqtt_request_t* request;\n\n    LWESP_UNUSED(res);\n\n    /* Check all requests */\n    while ((request = prv_request_get_pending(client, -1)) != NULL) {\n        prv_request_delete(client, request);                                  /* Delete request */\n        prv_request_send_err_callback(client, request->status, request->arg); /* Send error callback to user */\n    }\n    LWESP_MEMSET(client->requests, 0x00, sizeof(client->requests));\n\n    client->is_sending = client->sent_total = client->written_total = 0;\n    client->parser_state = MQTT_PARSER_STATE_INIT;\n    lwesp_buff_reset(&client->tx_buff); /* Reset TX buffer */\n\n    /*\n     * Call user function only if connection was closed\n     * when we are connected or in disconnecting mode\n     */\n    client->conn_state = LWESP_MQTT_CONN_DISCONNECTED; /* Connection is disconnected, ready to be established again */\n    client->evt.evt.disconnect.is_accepted =\n        state == LWESP_MQTT_CONNECTED || state == LWESP_MQTT_CONN_DISCONNECTING; /* Set connection state */\n    client->evt.type = LWESP_MQTT_EVT_DISCONNECT; /* Connection disconnected from server */\n    client->evt_fn(client, &client->evt);         /* Notify upper layer about closed connection */\n    client->conn = NULL;                          /* Reset connection handle */\n\n    LWESP_UNUSED(forced);\n\n    return 1;\n}\n\n/**\n * \\brief           Connection callback\n * \\param[in]       evt: Callback parameters\n * \\result          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nstatic lwespr_t\nprv_mqtt_conn_cb(lwesp_evt_t* evt) {\n    lwesp_conn_p conn;\n    lwesp_mqtt_client_p client = NULL;\n\n    conn = lwesp_conn_get_from_evt(evt); /* Get connection from event */\n    if (conn != NULL) {\n        client = lwesp_conn_get_arg(conn); /* Get client structure from connection */\n        if (client == NULL) {\n            lwesp_conn_close(conn, 0); /* Force connection close immediately */\n            return lwespERR;\n        }\n    } else if (evt->type != LWESP_EVT_CONN_ERROR) {\n        return lwespERR;\n    }\n\n    /* Check and process events */\n    switch (lwesp_evt_get_type(evt)) {\n        /*\n         * Connection error. Connection to external\n         * server was not successful\n         */\n        case LWESP_EVT_CONN_ERROR: {\n            lwesp_mqtt_client_p client;\n            if ((client = lwesp_evt_conn_error_get_arg(evt)) != NULL) {\n                client->conn_state = LWESP_MQTT_CONN_DISCONNECTED; /* Set back to disconnected state */\n                /* Notify user upper layer */\n                client->evt.type = LWESP_MQTT_EVT_CONNECT;\n                client->evt.evt.connect.status = LWESP_MQTT_CONN_STATUS_TCP_FAILED; /* TCP connection failed */\n                client->evt_fn(client, &client->evt); /* Notify upper layer about closed connection */\n            }\n            break;\n        }\n\n        /* Connection active to MQTT server */\n        case LWESP_EVT_CONN_ACTIVE: {\n            prv_mqtt_connected_cb(client);\n            break;\n        }\n\n        /* A new packet of data received on MQTT client connection */\n        case LWESP_EVT_CONN_RECV: {\n            prv_mqtt_data_recv_cb(client, lwesp_evt_conn_recv_get_buff(evt));\n            break;\n        }\n\n        /* Data send event */\n        case LWESP_EVT_CONN_SEND: {\n            prv_mqtt_data_sent_cb(client, lwesp_evt_conn_send_get_length(evt),\n                                  lwesp_evt_conn_send_get_result(evt) == lwespOK);\n            break;\n        }\n\n        /* Periodic poll for connection */\n        case LWESP_EVT_CONN_POLL: {\n            prv_mqtt_poll_cb(client);\n            break;\n        }\n\n        /* Connection closed */\n        case LWESP_EVT_CONN_CLOSE: {\n            prv_mqtt_closed_cb(client, lwesp_evt_conn_close_get_result(evt) == lwespOK,\n                               lwesp_evt_conn_close_is_forced(evt));\n            break;\n        }\n        default: break;\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Allocate a new MQTT client structure\n * \\param[in]       tx_buff_len: Length of raw data output buffer\n * \\param[in]       rx_buff_len: Length of raw data input buffer\n * \\return          Pointer to new allocated MQTT client structure or `NULL` on failure\n */\nlwesp_mqtt_client_t*\nlwesp_mqtt_client_new(size_t tx_buff_len, size_t rx_buff_len) {\n    lwesp_mqtt_client_p client;\n\n    if ((client = lwesp_mem_calloc(1, sizeof(*client))) != NULL) {\n        client->conn_state = LWESP_MQTT_CONN_DISCONNECTED; /* Set to disconnected mode */\n\n        if (!lwesp_buff_init(&client->tx_buff, tx_buff_len)) {\n            lwesp_mem_free_s((void**)&client);\n        }\n        if (client != NULL) {\n            client->rx_buff_len = rx_buff_len;\n            if ((client->rx_buff = lwesp_mem_malloc(rx_buff_len)) == NULL) {\n                lwesp_buff_free(&client->tx_buff);\n                lwesp_mem_free_s((void**)&client);\n            }\n        }\n    }\n    return client;\n}\n\n/**\n * \\brief           Delete MQTT client structure\n * \\note            MQTT client must be disconnected first\n * \\param[in]       client: MQTT client\n */\nvoid\nlwesp_mqtt_client_delete(lwesp_mqtt_client_p client) {\n    if (client != NULL) {\n        lwesp_mem_free_s((void**)&client->rx_buff);\n        lwesp_buff_free(&client->tx_buff);\n        lwesp_mem_free_s((void**)&client);\n    }\n}\n\n/**\n * \\brief           Connect to MQTT server in non-blocking mode. \n *                  Function returns immediately and does not wait for server to be connected.\n * \\note            After TCP connection is established, CONNECT packet is automatically sent to server.\n *                  Application must rely on events coming to event function, passed at connect stage\n * \\param[in]       client: MQTT client\n * \\param[in]       host: Host address for server\n * \\param[in]       port: Host port number\n * \\param[in]       evt_fn: Callback function for all events on this MQTT client\n * \\param[in]       info: Information structure for connection.\n *                      It is used after connection is successfully established.\n *                      Variable must not be a local or changes will be lost with potential faulty operation\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_mqtt_client_connect(lwesp_mqtt_client_p client, const char* host, lwesp_port_t port, lwesp_mqtt_evt_fn evt_fn,\n                          const lwesp_mqtt_client_info_t* info) {\n    lwespr_t res = lwespERR;\n\n    LWESP_ASSERT(client != NULL);\n    LWESP_ASSERT(host != NULL);\n    LWESP_ASSERT(port > 0);\n    LWESP_ASSERT(info != NULL && info->id != NULL);\n\n    lwesp_core_lock();\n    if (lwesp_sta_is_joined() && client->conn_state == LWESP_MQTT_CONN_DISCONNECTED) {\n        client->info = info; /* Save client info parameters */\n        client->evt_fn = evt_fn != NULL ? evt_fn : prv_mqtt_evt_fn_default;\n\n        /* Start a new connection in non-blocking mode */\n        if ((res = lwesp_conn_start(&client->conn, info->use_ssl ? LWESP_CONN_TYPE_SSL : LWESP_CONN_TYPE_TCP, host,\n                                    port, client, prv_mqtt_conn_cb, 0))\n            == lwespOK) {\n            client->conn_state = LWESP_MQTT_CONN_CONNECTING;\n        }\n    }\n    lwesp_core_unlock();\n    return res;\n}\n\n/**\n * \\brief           Disconnect from MQTT server\n * \\param[in]       client: MQTT client\n * \\return          \\ref lwespOK if request sent to queue or member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_mqtt_client_disconnect(lwesp_mqtt_client_p client) {\n    lwespr_t res = lwespERR;\n\n    lwesp_core_lock();\n    if (client->conn_state != LWESP_MQTT_CONN_DISCONNECTED && client->conn_state != LWESP_MQTT_CONN_DISCONNECTING) {\n        res = prv_mqtt_close(client); /* Close client connection */\n    }\n    lwesp_core_unlock();\n    return res;\n}\n\n/**\n * \\brief           Subscribe to MQTT topic\n * \\param[in]       client: MQTT client\n * \\param[in]       topic: Topic name to subscribe to\n * \\param[in]       qos: Quality of service. This parameter can be a value of \\ref lwesp_mqtt_qos_t\n * \\param[in]       arg: User custom argument used in callback\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_mqtt_client_subscribe(lwesp_mqtt_client_p client, const char* topic, lwesp_mqtt_qos_t qos, void* arg) {\n    return prv_sub_unsub(client, topic, qos, arg, 1) == 1 ? lwespOK : lwespERR; /* Subscribe to topic */\n}\n\n/**\n * \\brief           Unsubscribe from MQTT topic\n * \\param[in]       client: MQTT client\n * \\param[in]       topic: Topic name to unsubscribe from\n * \\param[in]       arg: User custom argument used in callback\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_mqtt_client_unsubscribe(lwesp_mqtt_client_p client, const char* topic, void* arg) {\n    return prv_sub_unsub(client, topic, (lwesp_mqtt_qos_t)0, arg, 0) == 1 ? lwespOK\n                                                                          : lwespERR; /* Unsubscribe from topic */\n}\n\n/**\n * \\brief           Publish a new message on specific topic\n * \\param[in]       client: MQTT client\n * \\param[in]       topic: Topic to send message to\n * \\param[in]       payload: Message data\n * \\param[in]       payload_len: Length of payload data\n * \\param[in]       qos: Quality of service. This parameter can be a value of \\ref lwesp_mqtt_qos_t enumeration\n * \\param[in]       retain: Retian parameter value\n * \\param[in]       arg: User custom argument used in callback\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_mqtt_client_publish(lwesp_mqtt_client_p client, const char* topic, const void* payload, uint16_t payload_len,\n                          lwesp_mqtt_qos_t qos, uint8_t retain, void* arg) {\n    lwespr_t res = lwespOK;\n    lwesp_mqtt_request_t* request = NULL;\n    uint32_t rem_len, raw_len;\n    uint16_t len_topic, pkt_id;\n    uint8_t qos_u8 = LWESP_U8(qos);\n\n    LWESP_ASSERT(client != NULL);\n    if ((len_topic = LWESP_U16(strlen(topic))) == 0) { /* Topic length */\n        return lwespERR;\n    }\n\n    /*\n     * Calculate remaining length of packet\n     *\n     * rem_len = 2 (topic_len) + topic_len + payload_len + 2 (pkt_id, only if qos > 0)\n     */\n    rem_len = 2 + len_topic + (payload != NULL ? payload_len : 0) + (qos_u8 > 0 ? 2 : 0);\n\n    lwesp_core_lock();\n    if (client->conn_state != LWESP_MQTT_CONNECTED) {\n        res = lwespCLOSED;\n    } else if ((raw_len = prv_output_check_enough_memory(client, rem_len)) != 0) {\n        pkt_id = qos_u8 > 0 ? prv_create_packet_id(client) : 0; /* Create new packet ID */\n        /* Create request for packet */\n        if ((request = prv_request_create(client, pkt_id, arg)) != NULL) {\n            /*\n             * Set expected number of bytes we should send before\n             * we can say that this packet was sent.\n             * Used in case QoS is set to 0 where packet notification\n             * is not received by server. In this case, wait\n             * number of bytes sent before notifying user about success\n             */\n            request->expected_sent_len = client->written_total + raw_len;\n\n            prv_write_fixed_header(client, MQTT_MSG_TYPE_PUBLISH, 0,\n                                   (lwesp_mqtt_qos_t)LWESP_MIN(qos_u8, LWESP_U8(LWESP_MQTT_QOS_EXACTLY_ONCE)), retain,\n                                   rem_len);\n            prv_write_string(client, topic, len_topic); /* Write topic string to packet */\n            if (qos_u8) {\n                prv_write_u16(client, pkt_id); /* Write packet ID */\n            }\n            if (payload != NULL && payload_len > 0) {\n                prv_write_data(client, payload, payload_len); /* Write RAW topic payload */\n            }\n            prv_request_set_pending(client, request); /* Set request as pending waiting for server reply */\n            prv_send_data(client);                    /* Try to send data */\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] Pkt publish start. QoS: %d, pkt_id: %d\\r\\n\",\n                         (int)qos_u8, (int)pkt_id);\n        } else {\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] No free request available to publish message\\r\\n\");\n            res = lwespERRMEM;\n        }\n    } else {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_TRACE, \"[LWESP MQTT] Not enough memory to publish message\\r\\n\");\n        res = lwespERRMEM;\n    }\n    lwesp_core_unlock();\n    return res;\n}\n\n/**\n * \\brief           Test if client is connected to server and accepted to MQTT protocol\n * \\note            Function will return error if TCP is connected but MQTT not accepted\n * \\param[in]       client: MQTT client\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_mqtt_client_is_connected(lwesp_mqtt_client_p client) {\n    uint8_t res = lwespERR;\n    if (client != NULL) {\n        lwesp_core_lock();\n        res = LWESP_U8(client->conn_state == LWESP_MQTT_CONNECTED);\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n/**\n * \\brief           Set user argument on client\n * \\param[in]       client: MQTT client handle\n * \\param[in]       arg: User argument\n */\nvoid\nlwesp_mqtt_client_set_arg(lwesp_mqtt_client_p client, void* arg) {\n    if (client != NULL) {\n        lwesp_core_lock();\n        client->arg = arg;\n        lwesp_core_unlock();\n    }\n}\n\n/**\n * \\brief           Get user argument on client\n * \\param[in]       client: MQTT client handle\n * \\return          User argument\n */\nvoid*\nlwesp_mqtt_client_get_arg(lwesp_mqtt_client_p client) {\n    return client != NULL ? client->arg : NULL;\n}\n"
  },
  {
    "path": "lwesp/src/apps/mqtt/lwesp_mqtt_client_api.c",
    "content": "/**\n * \\file            lwesp_mqtt_client_api.c\n * \\brief           MQTT client API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/apps/lwesp_mqtt_client_api.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/* Tracing debug message */\n#define LWESP_CFG_DBG_MQTT_API_TRACE         (LWESP_CFG_DBG_MQTT_API | LWESP_DBG_TYPE_TRACE)\n#define LWESP_CFG_DBG_MQTT_API_STATE         (LWESP_CFG_DBG_MQTT_API | LWESP_DBG_TYPE_STATE)\n#define LWESP_CFG_DBG_MQTT_API_TRACE_WARNING (LWESP_CFG_DBG_MQTT_API | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING)\n#define LWESP_CFG_DBG_MQTT_API_TRACE_SEVERE  (LWESP_CFG_DBG_MQTT_API | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_SEVERE)\n\n/**\n * \\brief           MQTT API client structure\n */\nstruct lwesp_mqtt_client_api {\n    lwesp_mqtt_client_p mc;                /*!< MQTT client handle */\n    lwesp_sys_mbox_t rcv_mbox;             /*!< Received data mbox */\n    lwesp_sys_sem_t sync_sem;              /*!< Synchronization semaphore */\n    lwesp_sys_mutex_t mutex;               /*!< Mutex handle */\n    uint8_t release_sem;                   /*!< Set to `1` to release semaphore */\n    lwesp_mqtt_conn_status_t connect_resp; /*!< Response when connecting to server */\n    lwespr_t sub_pub_resp;                 /*!< Subscribe/Unsubscribe/Publish response */\n} lwesp_mqtt_client_api_t;\n\n/**\n * \\brief           Variable used as pointer for message queue when MQTT connection is closed\n */\nstatic uint8_t mqtt_closed = 0xFF;\n\n/**\n * \\brief           Release user semaphore\n * \\param[in]       client: Client handle\n */\nstatic void\nprv_release_sem(lwesp_mqtt_client_api_p client) {\n    if (client->release_sem) {\n        client->release_sem = 0;\n        lwesp_sys_sem_release(&client->sync_sem);\n    }\n}\n\n/**\n * \\brief           MQTT event callback function\n */\nstatic void\nprv_mqtt_evt(lwesp_mqtt_client_p client, lwesp_mqtt_evt_t* evt) {\n    lwesp_mqtt_client_api_p api_client = lwesp_mqtt_client_get_arg(client);\n    if (api_client == NULL) {\n        return;\n    }\n    switch (lwesp_mqtt_client_evt_get_type(client, evt)) {\n        case LWESP_MQTT_EVT_CONNECT: {\n            lwesp_mqtt_conn_status_t status = lwesp_mqtt_client_evt_connect_get_status(client, evt);\n\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE, \"[MQTT API] Connect event with status: %d\\r\\n\", (int)status);\n\n            api_client->connect_resp = status;\n\n            /*\n             * By MQTT 3.1.1 specification, broker must close connection\n             * if client CONNECT packet was not accepted.\n             *\n             * If client is accepted or connection did not even start,\n             * release semaphore, otherwise wait CLOSED event\n             * and release semaphore from there,\n             * to make sure we are fully ready for next connection\n             */\n            if (status == LWESP_MQTT_CONN_STATUS_TCP_FAILED || status == LWESP_MQTT_CONN_STATUS_ACCEPTED) {\n                prv_release_sem(api_client); /* Release semaphore */\n            }\n            break;\n        }\n        case LWESP_MQTT_EVT_PUBLISH_RECV: {\n            /* Check valid receive mbox */\n            if (!lwesp_sys_mbox_isvalid(&api_client->rcv_mbox)) {\n                break;\n            }\n            lwesp_mqtt_client_api_buf_p buf;\n            size_t size, buf_size, topic_size, payload_size;\n\n            /* Get event data */\n            const char* topic = lwesp_mqtt_client_evt_publish_recv_get_topic(client, evt);\n            size_t topic_len = lwesp_mqtt_client_evt_publish_recv_get_topic_len(client, evt);\n            const uint8_t* payload = lwesp_mqtt_client_evt_publish_recv_get_payload(client, evt);\n            size_t payload_len = lwesp_mqtt_client_evt_publish_recv_get_payload_len(client, evt);\n            lwesp_mqtt_qos_t qos = lwesp_mqtt_client_evt_publish_recv_get_qos(client, evt);\n\n            /* Print debug message */\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE, \"[MQTT API] New publish received on topic %.*s\\r\\n\",\n                         (int)topic_len, topic);\n\n            /* Calculate memory sizes */\n            buf_size = LWESP_MEM_ALIGN(sizeof(*buf));\n            topic_size = LWESP_MEM_ALIGN(sizeof(*topic) * (topic_len + 1));\n            payload_size = LWESP_MEM_ALIGN(sizeof(*payload) * (payload_len + 1));\n\n            size = buf_size + topic_size + payload_size;\n            if ((buf = lwesp_mem_malloc(size)) != NULL) {\n                LWESP_MEMSET(buf, 0x00, size);\n                buf->topic = (void*)((uint8_t*)buf + buf_size);\n                buf->payload = (void*)((uint8_t*)buf + buf_size + topic_size);\n                buf->topic_len = topic_len;\n                buf->payload_len = payload_len;\n                buf->qos = qos;\n\n                /* Copy content to new memory */\n                LWESP_MEMCPY(buf->topic, topic, sizeof(*topic) * topic_len);\n                LWESP_MEMCPY(buf->payload, payload, sizeof(*payload) * payload_len);\n\n                /* Write to receive queue */\n                if (!lwesp_sys_mbox_putnow(&api_client->rcv_mbox, buf)) {\n                    LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_WARNING,\n                                 \"[MQTT API] Cannot put new received MQTT publish to queue\\r\\n\");\n                    lwesp_mem_free_s((void**)&buf);\n                }\n            } else {\n                LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_WARNING,\n                             \"[MQTT API] Cannot allocate memory for packet buffer of size %d bytes\\r\\n\", (int)size);\n            }\n            break;\n        }\n        case LWESP_MQTT_EVT_PUBLISH: {\n            api_client->sub_pub_resp = lwesp_mqtt_client_evt_publish_get_result(client, evt);\n            prv_release_sem(api_client); /* Release semaphore */\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE, \"[MQTT API] Publish event with response: %d\\r\\n\",\n                         (int)api_client->sub_pub_resp);\n            break;\n        }\n        case LWESP_MQTT_EVT_SUBSCRIBE: {\n            api_client->sub_pub_resp = lwesp_mqtt_client_evt_subscribe_get_result(client, evt);\n            prv_release_sem(api_client); /* Release semaphore */\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE, \"[MQTT API] Subscribe event with response: %d\\r\\n\",\n                         (int)api_client->sub_pub_resp);\n            break;\n        }\n        case LWESP_MQTT_EVT_UNSUBSCRIBE: {\n            api_client->sub_pub_resp = lwesp_mqtt_client_evt_unsubscribe_get_result(client, evt);\n            prv_release_sem(api_client); /* Release semaphore */\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE, \"[MQTT API] Unsubscribe event with response: %d\\r\\n\",\n                         (int)api_client->sub_pub_resp);\n            break;\n        }\n        case LWESP_MQTT_EVT_DISCONNECT: {\n            uint8_t is_accepted = lwesp_mqtt_client_evt_disconnect_is_accepted(client, evt);\n            /* Disconnect event happened */\n            //api_client->connect_resp = MQTT_CONN_STATUS_TCP_FAILED;\n\n            /* Print debug message */\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE, \"[MQTT API] Disconnect event\\r\\n\");\n\n            /* Write to receive mbox to wakeup receive thread */\n            if (is_accepted && lwesp_sys_mbox_isvalid(&api_client->rcv_mbox)) {\n                lwesp_sys_mbox_putnow(&api_client->rcv_mbox, &mqtt_closed);\n            }\n            prv_release_sem(api_client); /* Release semaphore */\n            break;\n        }\n        default: break;\n    }\n}\n\n/**\n * \\brief           Create new MQTT client API\n * \\param[in]       tx_buff_len: Maximal TX buffer for maximal packet length\n * \\param[in]       rx_buff_len: Maximal RX buffer\n * \\return          Client handle on success, `NULL` otherwise\n */\nlwesp_mqtt_client_api_p\nlwesp_mqtt_client_api_new(size_t tx_buff_len, size_t rx_buff_len) {\n    lwesp_mqtt_client_api_p client;\n\n    /* Allocate client memory */\n    if ((client = lwesp_mem_calloc(1, LWESP_MEM_ALIGN(sizeof(*client)))) != NULL) {\n        /* Create MQTT raw client structure */\n        if ((client->mc = lwesp_mqtt_client_new(tx_buff_len, rx_buff_len)) != NULL) {\n            /* Create receive mbox queue */\n            if (lwesp_sys_mbox_create(&client->rcv_mbox, LWESP_CFG_MQTT_API_MBOX_SIZE)) {\n                /* Create synchronization semaphore */\n                if (lwesp_sys_sem_create(&client->sync_sem, 1)) {\n                    /* Create mutex */\n                    if (lwesp_sys_mutex_create(&client->mutex)) {\n                        lwesp_mqtt_client_set_arg(client->mc, client); /* Set client to mqtt client argument */\n                        return client;\n                    } else {\n                        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_SEVERE, \"[MQTT API] Cannot allocate mutex\\r\\n\");\n                    }\n                } else {\n                    LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_SEVERE, \"[MQTT API] Cannot allocate sync semaphore\\r\\n\");\n                }\n            } else {\n                LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_SEVERE, \"[MQTT API] Cannot allocate receive queue\\r\\n\");\n            }\n        } else {\n            LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_SEVERE, \"[MQTT API] Cannot allocate MQTT client\\r\\n\");\n        }\n    } else {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_SEVERE, \"[MQTT API] Cannot allocate memory for client\\r\\n\");\n    }\n    lwesp_mqtt_client_api_delete(client);\n    client = NULL;\n    return NULL;\n}\n\n/**\n * \\brief           Delete client from memory\n * \\param[in]       client: MQTT API client handle\n */\nvoid\nlwesp_mqtt_client_api_delete(lwesp_mqtt_client_api_p client) {\n    if (client == NULL) {\n        return;\n    }\n    if (lwesp_sys_sem_isvalid(&client->sync_sem)) {\n        lwesp_sys_sem_delete(&client->sync_sem);\n        lwesp_sys_sem_invalid(&client->sync_sem);\n    }\n    if (lwesp_sys_mutex_isvalid(&client->mutex)) {\n        lwesp_sys_mutex_delete(&client->mutex);\n        lwesp_sys_mutex_invalid(&client->mutex);\n    }\n    if (lwesp_sys_mbox_isvalid(&client->rcv_mbox)) {\n        void* d;\n        while (lwesp_sys_mbox_getnow(&client->rcv_mbox, &d)) {\n            if ((uint8_t*)d != (uint8_t*)&mqtt_closed) {\n                lwesp_mqtt_client_api_buf_free(d);\n            }\n        }\n        lwesp_sys_mbox_delete(&client->rcv_mbox);\n        lwesp_sys_mbox_invalid(&client->rcv_mbox);\n    }\n    if (client->mc != NULL) {\n        lwesp_mqtt_client_delete(client->mc);\n        client->mc = NULL;\n    }\n    lwesp_mem_free_s((void**)&client);\n}\n\n/**\n * \\brief           Connect to MQTT broker\n * \\param[in]       client: MQTT API client handle\n * \\param[in]       host: TCP host\n * \\param[in]       port: TCP port\n * \\param[in]       info: MQTT client info\n * \\return          \\ref LWESP_MQTT_CONN_STATUS_ACCEPTED on success, member of \\ref lwesp_mqtt_conn_status_t otherwise\n */\nlwesp_mqtt_conn_status_t\nlwesp_mqtt_client_api_connect(lwesp_mqtt_client_api_p client, const char* host, lwesp_port_t port,\n                              const lwesp_mqtt_client_info_t* info) {\n    if (client == NULL || host == NULL || !port || info == NULL) {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_WARNING, \"[MQTT API] Invalid parameters in function\\r\\n\");\n        return LWESP_MQTT_CONN_STATUS_TCP_FAILED;\n    }\n\n    lwesp_sys_mutex_lock(&client->mutex);\n    client->connect_resp = LWESP_MQTT_CONN_STATUS_TCP_FAILED;\n    lwesp_sys_sem_wait(&client->sync_sem, 0);\n    client->release_sem = 1;\n    if (lwesp_mqtt_client_connect(client->mc, host, port, prv_mqtt_evt, info) == lwespOK) {\n        lwesp_sys_sem_wait(&client->sync_sem, 0);\n    } else {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_WARNING, \"[MQTT API] Cannot connect to %s\\r\\n\", host);\n    }\n    client->release_sem = 0;\n    lwesp_sys_sem_release(&client->sync_sem);\n    lwesp_sys_mutex_unlock(&client->mutex);\n    return client->connect_resp;\n}\n\n/**\n * \\brief           Close MQTT connection\n * \\param[in]       client: MQTT API client handle\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_mqtt_client_api_close(lwesp_mqtt_client_api_p client) {\n    lwespr_t res = lwespERR;\n\n    LWESP_ASSERT(client != NULL);\n\n    lwesp_sys_mutex_lock(&client->mutex);\n    lwesp_sys_sem_wait(&client->sync_sem, 0);\n    client->release_sem = 1;\n    if (lwesp_mqtt_client_disconnect(client->mc) == lwespOK) {\n        res = lwespOK;\n        lwesp_sys_sem_wait(&client->sync_sem, 0);\n    } else {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_WARNING, \"[MQTT API] Cannot close API connection\\r\\n\");\n    }\n    client->release_sem = 0;\n    lwesp_sys_sem_release(&client->sync_sem);\n    lwesp_sys_mutex_unlock(&client->mutex);\n    return res;\n}\n\n/**\n * \\brief           Subscribe to topic\n * \\param[in]       client: MQTT API client handle\n * \\param[in]       topic: Topic to subscribe on\n * \\param[in]       qos: Quality of service. This parameter can be a value of \\ref lwesp_mqtt_qos_t\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_mqtt_client_api_subscribe(lwesp_mqtt_client_api_p client, const char* topic, lwesp_mqtt_qos_t qos) {\n    lwespr_t res = lwespERR;\n\n    LWESP_ASSERT(client != NULL);\n    LWESP_ASSERT(topic != NULL);\n\n    lwesp_sys_mutex_lock(&client->mutex);\n    lwesp_sys_sem_wait(&client->sync_sem, 0);\n    client->release_sem = 1;\n    if (lwesp_mqtt_client_subscribe(client->mc, topic, qos, NULL) == lwespOK) {\n        lwesp_sys_sem_wait(&client->sync_sem, 0);\n        res = client->sub_pub_resp;\n    } else {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_WARNING, \"[MQTT API] Cannot subscribe to topic %s\\r\\n\", topic);\n    }\n    client->release_sem = 0;\n    lwesp_sys_sem_release(&client->sync_sem);\n    lwesp_sys_mutex_unlock(&client->mutex);\n\n    return res;\n}\n\n/**\n * \\brief           Unsubscribe from topic\n * \\param[in]       client: MQTT API client handle\n * \\param[in]       topic: Topic to unsubscribe from\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_mqtt_client_api_unsubscribe(lwesp_mqtt_client_api_p client, const char* topic) {\n    lwespr_t res = lwespERR;\n\n    LWESP_ASSERT(client != NULL);\n    LWESP_ASSERT(topic != NULL);\n\n    lwesp_sys_mutex_lock(&client->mutex);\n    lwesp_sys_sem_wait(&client->sync_sem, 0);\n    client->release_sem = 1;\n    if (lwesp_mqtt_client_unsubscribe(client->mc, topic, NULL) == lwespOK) {\n        lwesp_sys_sem_wait(&client->sync_sem, 0);\n        res = client->sub_pub_resp;\n    } else {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_WARNING, \"[MQTT API] Cannot unsubscribe from topic %s\\r\\n\", topic);\n    }\n    client->release_sem = 0;\n    lwesp_sys_sem_release(&client->sync_sem);\n    lwesp_sys_mutex_unlock(&client->mutex);\n\n    return res;\n}\n\n/**\n * \\brief           Publish new packet to MQTT network\n * \\param[in]       client: MQTT API client handle\n * \\param[in]       topic: Topic to publish on\n * \\param[in]       data: Data to send\n * \\param[in]       btw: Number of bytes to send for data parameter\n * \\param[in]       qos: Quality of service. This parameter can be a value of \\ref lwesp_mqtt_qos_t\n * \\param[in]       retain: Set to `1` for retain flag, `0` otherwise\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_mqtt_client_api_publish(lwesp_mqtt_client_api_p client, const char* topic, const void* data, size_t btw,\n                              lwesp_mqtt_qos_t qos, uint8_t retain) {\n    lwespr_t res = lwespERR;\n\n    LWESP_ASSERT(client != NULL);\n    LWESP_ASSERT(topic != NULL);\n\n    lwesp_sys_mutex_lock(&client->mutex);\n    lwesp_sys_sem_wait(&client->sync_sem, 0);\n    client->release_sem = 1;\n    if (lwesp_mqtt_client_publish(client->mc, topic, data, LWESP_U16(btw), qos, retain, NULL) == lwespOK) {\n        lwesp_sys_sem_wait(&client->sync_sem, 0);\n        res = client->sub_pub_resp;\n    } else {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE_WARNING, \"[MQTT API] Cannot publish new packet\\r\\n\");\n    }\n    client->release_sem = 0;\n    lwesp_sys_sem_release(&client->sync_sem);\n    lwesp_sys_mutex_unlock(&client->mutex);\n    return res;\n}\n\n/**\n * \\brief           Check if client MQTT connection is active\n * \\param[in]       client: MQTT API client handle\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_mqtt_client_api_is_connected(lwesp_mqtt_client_api_p client) {\n    uint8_t ret;\n\n    if (client == NULL) {\n        return 0;\n    }\n\n    lwesp_sys_mutex_lock(&client->mutex);\n    ret = lwesp_mqtt_client_is_connected(client->mc);\n    lwesp_sys_mutex_unlock(&client->mutex);\n    return ret;\n}\n\n/**\n * \\brief           Receive next packet in specific timeout time\n * \\note            This function can be called from separate thread\n *                      than the rest of API function, which allows you to\n *                      handle receive data separated with custom timeout\n * \\param[in]       client: MQTT API client handle\n * \\param[in]       p: Pointer to output buffer\n * \\param[in]       timeout: Maximal time to wait before function returns timeout\n * \\return          \\ref lwespOK on success, \\ref lwespCLOSED if MQTT is closed, \\ref lwespTIMEOUT on timeout\n */\nlwespr_t\nlwesp_mqtt_client_api_receive(lwesp_mqtt_client_api_p client, lwesp_mqtt_client_api_buf_p* p, uint32_t timeout) {\n    LWESP_ASSERT(client != NULL);\n    LWESP_ASSERT(p != NULL);\n\n    *p = NULL;\n\n    /* Get new entry from mbox */\n    if (timeout == 0) {\n        if (!lwesp_sys_mbox_getnow(&client->rcv_mbox, (void**)p)) {\n            return lwespTIMEOUT;\n        }\n    } else if (lwesp_sys_mbox_get(&client->rcv_mbox, (void**)p, timeout) == LWESP_SYS_TIMEOUT) {\n        return lwespTIMEOUT;\n    }\n\n    /* Check for MQTT closed event */\n    if ((uint8_t*)(*p) == (uint8_t*)&mqtt_closed) {\n        LWESP_DEBUGF(LWESP_CFG_DBG_MQTT_API_TRACE, \"[MQTT API] Closed event received from queue\\r\\n\");\n\n        *p = NULL;\n        return lwespCLOSED;\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Free buffer memory after usage\n * \\param[in]       p: Buffer to free\n */\nvoid\nlwesp_mqtt_client_api_buf_free(lwesp_mqtt_client_api_buf_p p) {\n    lwesp_mem_free_s((void**)&p);\n}\n"
  },
  {
    "path": "lwesp/src/apps/mqtt/lwesp_mqtt_client_evt.c",
    "content": "/**\n * \\file            lwesp_mqtt_client_evt.c\n * \\brief           MQTT client event helper functions\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/apps/lwesp_mqtt_client_evt.h\"\n"
  },
  {
    "path": "lwesp/src/cli/cli.c",
    "content": "/**\n * \\file            cli.c\n * \\brief           Command line interface\n */\n\n/*\n * Copyright (c) 2019 Miha CESNIK\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Miha CESNIK <>\n * Version:         v1.1.2-dev\n */\n#include <stdbool.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <string.h>\n#include \"cli/cli.h\"\n#include \"lwesp/lwesp_private.h\"\n\nstatic cli_commands_t cli_command_table[CLI_MAX_MODULES];\nstatic size_t num_of_modules;\n\nstatic void cli_list(cli_printf cliprintf, int argc, char** argv);\nstatic void cli_help(cli_printf cliprintf, int argc, char** argv);\n\n/**\n * \\brief           List of commands\n */\nstatic const cli_command_t commands[] = {\n    {\"help\", \"Displays helptext for given command\", cli_help},\n    {\"list\", \"Lists available commands\", cli_list},\n};\n\n/**\n * \\brief           Find the CLI command that matches the input string\n * \\param[in]       command: pointer to command string for which we are searching\n * \\return          pointer of the command if we found a match, else NULL\n */\nconst cli_command_t*\ncli_lookup_command(char* command) {\n    uint32_t module_index, command_index;\n    for (module_index = 0; module_index < num_of_modules; ++module_index) {\n        for (command_index = 0; command_index < cli_command_table[module_index].num_of_commands; ++command_index) {\n            if (!strcmp(command, cli_command_table[module_index].commands[command_index].name)) {\n                return &cli_command_table[module_index].commands[command_index];\n            }\n        }\n    }\n    return NULL;\n}\n\n/**\n * \\brief           CLI auto completion function\n * \\param[in]       cliprintf: Pointer to CLI printf function\n * \\param[in]       cmd_buffer: CLI command buffer\n * \\param[in]       cmd_pos: pointer to current courser postion in command buffer\n * \\param[in]       print_options: additional prints in case of double tab\n */\nvoid\ncli_tab_auto_complete(cli_printf cliprintf, char* cmd_buffer, uint32_t* cmd_pos, bool print_options) {\n    const char* matched_command = NULL;\n    uint32_t module_index, command_index;\n    uint32_t num_of_matched_commands = 0;\n    uint32_t common_command_len = 0;\n\n    for (module_index = 0; module_index < num_of_modules; ++module_index) {\n        for (command_index = 0; command_index < cli_command_table[module_index].num_of_commands; ++command_index) {\n            const cli_command_t* command = &cli_command_table[module_index].commands[command_index];\n            if (!strncmp(cmd_buffer, cli_command_table[module_index].commands[command_index].name, *cmd_pos)) {\n                /* Found a new command which matches the string */\n                if (num_of_matched_commands == 0) {\n                    /*\n                     * Save the first match for later tab completion in case\n                     * print_option is true (double tab)\n                     */\n                    matched_command = command->name;\n                    common_command_len = strlen(matched_command);\n                } else {\n                    /*\n                     * More then one match\n                     * in case of print_option we need to print all options\n                     */\n                    if (print_options) {\n                        /*\n                         * Because we want to print help options only when we\n                         * have multiple matches, print also the first one.\n                         */\n                        if (num_of_matched_commands == 1) {\n                            cliprintf(CLI_NL \"%s\" CLI_NL, matched_command);\n                        }\n                        cliprintf(\"%s\" CLI_NL, command->name);\n                    }\n\n                    /*\n                     * Find the common prefix of all the matched commands for\n                     * partial completion\n                     */\n                    uint32_t last_common_command_len = common_command_len;\n                    common_command_len = 0;\n                    while (matched_command[common_command_len] == command->name[common_command_len]\n                           && matched_command[common_command_len] != '\\0' && command->name[common_command_len] != '\\0'\n                           && common_command_len < last_common_command_len) {\n                        ++common_command_len;\n                    }\n                }\n                ++num_of_matched_commands;\n            }\n        }\n    }\n\n    /* Do the full/partial tab completion */\n    if (matched_command != NULL) {\n        strncpy(cmd_buffer, matched_command, common_command_len);\n        *cmd_pos = strlen(cmd_buffer);\n        cmd_buffer[*cmd_pos] = '\\0';\n        cliprintf(\"\\r\" CLI_PROMPT \"%s\", cmd_buffer);\n    }\n}\n\n/**\n * \\brief           Register new CLI commands\n * \\param[in]       commands: Pointer to commands table\n * \\param[in]       num_of_commands: Number of new commands\n * \\return          true when new commands where succesfully added, else false\n */\nbool\ncli_register_commands(const cli_command_t* commands, size_t num_of_commands) {\n    if (num_of_modules >= CLI_MAX_MODULES) {\n        printf(\"Exceeded the maximum number of CLI modules\\n\\r\");\n        return false;\n    }\n\n    /*\n     * Warning: Not threadsafe!\n     * TODO: add mutex that is initialized in init function\n     */\n    cli_command_table[num_of_modules].commands = commands;\n    cli_command_table[num_of_modules].num_of_commands = num_of_commands;\n    ++num_of_modules;\n\n    return true;\n}\n\n/**\n * \\brief           CLI Init function for adding basic CLI commands\n */\nvoid\ncli_init(void) {\n    cli_register_commands(commands, sizeof(commands) / sizeof(commands[0]));\n}\n\n/**\n * \\brief           CLI command for printing help text of specific command\n * \\param[in]       cliprintf: Pointer to CLI printf function\n * \\param[in]       argc: Number fo arguments in argv\n * \\param[in]       argv: Pointer to the commands arguments\n */\nstatic void\ncli_help(cli_printf cliprintf, int argc, char** argv) {\n    const cli_command_t* command;\n\n    if (argc < 2) {\n        cliprintf(\"Error: No function specified (try `list`)\\n\");\n        return;\n    }\n\n    if ((command = cli_lookup_command(argv[1])) == NULL) {\n        cliprintf(\"Error, command `%s` not found\\n\", argv[1]);\n        return;\n    }\n\n    if (command->help != NULL) {\n        cliprintf(\"%s\\n\", command->help);\n    }\n}\n\n/**\n * \\brief           CLI command for listing all available commands\n * \\param[in]       cliprintf: Pointer to CLI printf function\n * \\param[in]       argc: Number fo arguments in argv\n * \\param[in]       argv: Pointer to the commands arguments\n */\nstatic void\ncli_list(cli_printf cliprintf, int argc, char** argv) {\n    uint32_t module_index, command_index;\n\n    LWESP_UNUSED(argc);\n    LWESP_UNUSED(argv);\n\n    cliprintf(\"%-20s%s\" CLI_NL, \"Command\", \"Description\");\n    cliprintf(\"-----------------------------------------------------------\" CLI_NL);\n\n    for (module_index = 0; module_index < num_of_modules; ++module_index) {\n        for (command_index = 0; command_index < cli_command_table[module_index].num_of_commands; ++command_index) {\n            cliprintf(\"%-20s%s\" CLI_NL, cli_command_table[module_index].commands[command_index].name,\n                      cli_command_table[module_index].commands[command_index].help);\n        }\n    }\n}\n"
  },
  {
    "path": "lwesp/src/cli/cli_input.c",
    "content": "/**\n * \\file            cli_input.c\n * \\brief           Command line interface helper funcions for paring input data\n */\n\n/*\n * Copyright (c) 2019 Miha CESNIK\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Miha CESNIK <>\n * Version:         v1.1.2-dev\n */\n\n#include <stdbool.h>\n#include <stdint.h>\n#include <string.h>\n#include \"cli/cli.h\"\n#include \"cli/cli_input.h\"\n#include \"cli/cli_opt.h\"\n\n/* Statically allocate CLI buffer to eliminate overhead of using heap*/\nstatic char cmd_buffer[CLI_MAX_CMD_LENGTH];\nstatic uint32_t cmd_pos;\n\nstatic char cmd_history_buffer[CLI_CMD_HISTORY][CLI_MAX_CMD_LENGTH];\nstatic uint32_t cmd_history_pos;\nstatic uint32_t cmd_history_full;\n\n/**\n * \\brief           Clear the command buffer and reset the position\n */\nstatic void\nclear_cmd_buffer(void) {\n    memset(cmd_buffer, 0x0, sizeof(cmd_buffer));\n    cmd_pos = 0;\n}\n\n/**\n * \\brief           Stores the command to history\n */\nstatic void\nstore_command_to_history(void) {\n    uint32_t hist_count;\n    if (strcmp(cmd_history_buffer[0], cmd_buffer)) {\n        for (hist_count = CLI_CMD_HISTORY - 1; hist_count > 0; --hist_count) {\n            memcpy(cmd_history_buffer[hist_count], cmd_history_buffer[hist_count - 1], CLI_MAX_CMD_LENGTH);\n        }\n        ++cmd_history_full;\n        if (cmd_history_full > CLI_CMD_HISTORY) {\n            cmd_history_full = CLI_CMD_HISTORY;\n        }\n        memcpy(cmd_history_buffer[0], cmd_buffer, CLI_MAX_CMD_LENGTH);\n        cmd_history_buffer[0][CLI_MAX_CMD_LENGTH - 1] = '\\0';\n    }\n}\n\n/**\n * \\brief           Special key sequence check\n *                      ^[3~ : Delete (TODO)\n *                      ^[A  : Up\n *                      ^[B  : Down\n *                      ^[C  : Right\n *                      ^[D  : Left\n *                      ^[1~ : Home (TODO)\n *                      ^OF  : End (TODO)\n * \\param[in]       cliprintf: Pointer to CLI printf function\n * \\param[in]       ch: input char from CLI\n * \\return          true when special key sequence is active, else false\n */\nstatic bool\ncli_special_key_check(cli_printf cliprintf, char ch) {\n    static uint32_t key_sequence;\n    static char last_ch;\n    bool special_key_found = false;\n\n    if (key_sequence == 0 && ch == 27) {\n        special_key_found = true;\n        key_sequence = 1;\n    } else if (key_sequence == 1 && (ch == '[' || ch == 'O')) {\n        special_key_found = true;\n        key_sequence = 2;\n    } else if (key_sequence == 2 && ch >= 'A' && ch <= 'D') {\n        special_key_found = true;\n        key_sequence = 0;\n        switch (ch) {\n            case 'A': /* Up */\n                if (cmd_history_pos < cmd_history_full) {\n                    /* Clear the line */\n                    memset(cmd_buffer, ' ', cmd_pos);\n                    cliprintf(\"\\r%s       \\r\" CLI_PROMPT, cmd_buffer);\n\n                    strcpy(cmd_buffer, cmd_history_buffer[cmd_history_pos]);\n                    cmd_pos = strlen(cmd_buffer);\n                    cliprintf(\"%s\", cmd_buffer);\n\n                    ++cmd_history_pos;\n                } else {\n                    cliprintf(\"\\a\");\n                }\n                break;\n            case 'B': /* Down */\n                if (cmd_history_pos > 0) {\n                    /* Clear the line */\n                    memset(cmd_buffer, ' ', cmd_pos);\n                    cliprintf(\"\\r%s       \\r\" CLI_PROMPT, cmd_buffer);\n\n                    if (--cmd_history_pos != 0) {\n                        strcpy(cmd_buffer, cmd_history_buffer[cmd_history_pos]);\n                        cmd_pos = strlen(cmd_buffer);\n                        cliprintf(\"%s\", cmd_buffer);\n                    } else {\n                        clear_cmd_buffer();\n                    }\n                } else {\n                    cliprintf(\"\\a\");\n                }\n\n                break;\n            case 'C': /* Right */\n                /* TODO not finnished\n                 * need to implement a courser\n                 */\n                if (cmd_pos < strlen(cmd_buffer)) {\n                    ++cmd_pos;\n                    cliprintf(\"\\033[\\1C\");\n                } else {\n                    cliprintf(\"\\a\");\n                }\n                break;\n            case 'D': /* Left */\n                /* TODO not finnished\n                 * need to implement a courser\n                 */\n                if (cmd_pos > 0) {\n                    --cmd_pos;\n                    cliprintf(\"\\033[\\1D\");\n                } else {\n                    cliprintf(\"\\a\");\n                }\n                break;\n        }\n    } else if (key_sequence == 2 && (ch == 'F')) {\n        /* End*/\n        /* TODO: for now just return invalid key */\n        cliprintf(\"\\a\");\n    } else if (key_sequence == 2 && (ch == '1' || ch == '3')) {\n        /* Home or Delete, we need to check one more character */\n        special_key_found = true;\n        key_sequence = 3;\n    } else if (key_sequence == 3) {\n        /* TODO Home and Delete: for now just return invalid key */\n        cliprintf(\"\\a\");\n        special_key_found = true;\n    } else {\n        /* Unknown sequence */\n        key_sequence = 0;\n    }\n\n    /* Store the last character */\n    last_ch = ch;\n\n    (void)last_ch; /* Prevent compiler warnings */\n\n    return special_key_found;\n}\n\n/**\n * \\brief           parse and execute the given command\n * \\param[in]       cliprintf: Pointer to CLI printf function\n * \\param[in]       input: input string to parse\n * \\return          `true` when command is found and parsed, else `false`\n */\nstatic bool\ncli_parse_and_execute_command(cli_printf cliprintf, char* input) {\n    const cli_command_t* command;\n    char* argv[CLI_MAX_NUM_OF_ARGS];\n    uint32_t argc = 0;\n\n    argv[argc] = strtok(input, \" \");\n    while (argv[argc] != NULL) {\n        argv[++argc] = strtok(NULL, \" \");\n    }\n\n    if ((command = cli_lookup_command(argv[0])) == NULL) {\n        cliprintf(\"Unknown command: %s\\n\", argv[0]);\n        return false;\n    } else {\n        command->func(cliprintf, argc, argv);\n    }\n\n    return true;\n}\n\n/**\n * \\brief           parse new characters to the CLI\n * \\param[in]       cliprintf: Pointer to CLI printf function\n * \\param[in]       ch: new character to CLI\n */\nvoid\ncli_in_data(cli_printf cliprintf, char ch) {\n    static char last_ch;\n\n    if (!cli_special_key_check(cliprintf, ch)) {\n        /* Parse the characters only if they are not part of the special key sequence */\n        switch (ch) {\n            /* Backspace */\n            case '\\b':\n            case 127:\n                if (cmd_pos != 0) {\n                    /* TODO not finished\n                     * in case courser is not at the end this doesn't work properly\n                     */\n                    cmd_buffer[--cmd_pos] = '\\0';\n                    cliprintf(\"\\033[\\1D\");\n                    cliprintf(\"\\033[K\");\n                } else {\n                    cliprintf(\"\\a\");\n                }\n                break;\n            /* Tab for autocomplete */\n            case '\\t': cli_tab_auto_complete(cliprintf, cmd_buffer, &cmd_pos, (last_ch == '\\t')); break;\n            /* New line -> new command */\n            case '\\n':\n            case '\\r':\n                cmd_history_pos = 0;\n                if (!strlen(cmd_buffer)) {\n                    clear_cmd_buffer();\n                    cliprintf(CLI_NL CLI_PROMPT);\n                    return;\n                }\n\n                cliprintf(CLI_NL);\n                store_command_to_history();\n                cli_parse_and_execute_command(cliprintf, cmd_buffer);\n\n                clear_cmd_buffer();\n                cliprintf(CLI_NL CLI_PROMPT);\n                break;\n            /* All other chars */\n            default:\n                if (cmd_pos < CLI_MAX_CMD_LENGTH) {\n                    cmd_buffer[cmd_pos++] = ch;\n                } else {\n                    clear_cmd_buffer();\n                    cliprintf(CLI_NL \"\\aERR: Command too long\" CLI_NL CLI_PROMPT);\n                    return;\n                }\n                cliprintf(\"%c\", ch);\n        }\n    }\n\n    /* Store last character for double tab detection */\n    last_ch = ch;\n}\n"
  },
  {
    "path": "lwesp/src/include/cli/cli.h",
    "content": "/**\n * \\file            cli.h\n * \\brief           Command line interface\n */\n\n/*\n * Copyright (c) 2019 Miha CESNIK\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Miha CESNIK <>\n * Version:         v1.1.2-dev\n */\n#ifndef CLI_HDR_H\n#define CLI_HDR_H\n\n#include <stdbool.h>\n#include <stdint.h>\n#include \"cli/cli_opt.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\defgroup        CLI Command line interface\n * \\brief           Command line interface\n * \\{\n *\n * Functions to initialize everything needed for command line interface (CLI).\n */\n\n/**\n * \\brief           Printf handle for CLI\n * \\param[in]       format: string format\n */\ntypedef void cli_printf(const char* format, ...);\n\n/**\n * \\brief           CLI entriy function\n * \\param[in]       cliprintf: Printf handle callback\n * \\param[in]       argc: Number of arguments\n * \\param[in]       argv: Pointer to pointer to arguments\n */\ntypedef void cli_function(cli_printf cliprintf, int argc, char** argv);\n\n/**\n * \\brief           CLI command structure\n */\ntypedef struct {\n    const char* name;   /*!< Command name */\n    const char* help;   /*!< Command help */\n    cli_function* func; /*!< Command function */\n} cli_command_t;\n\n/**\n * \\brief           List of commands\n */\ntypedef struct {\n    const cli_command_t* commands; /*!< Pointer to commands */\n    size_t num_of_commands;        /*!< Total number of commands */\n} cli_commands_t;\n\nconst cli_command_t* cli_lookup_command(char* command);\nvoid cli_tab_auto_complete(cli_printf cliprintf, char* cmd_buffer, uint32_t* cmd_pos, bool print_options);\nbool cli_register_commands(const cli_command_t* commands, size_t num_of_commands);\nvoid cli_init(void);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* CLI_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/cli/cli_input.h",
    "content": "/**\n * \\file            cli_input.h\n * \\brief           Command line interface helper funcions for paring input data\n */\n\n/*\n * Copyright (c) 2019 Miha CESNIK\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Miha CESNIK <>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_CLI_INPUT_HDR_H\n#define LWESP_CLI_INPUT_HDR_H\n\n#include \"cli/cli.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         CLI\n * \\defgroup        CLI_INPUT Input\n * \\brief           Command line interface helper funcions for paring input data\n * \\{\n *\n * Functions to parse incoming data for command line interface (CLI).\n */\n\nvoid cli_in_data(cli_printf cliprintf, char ch);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_CLI_INPUT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/cli/cli_opt.h",
    "content": "/**\n * \\file            cli_opt.h\n * \\brief           Command line interface configuration file\n */\n\n/*\n * Copyright (c) 2019 Miha CESNIK\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Miha CESNIK <>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_CLI_CONFIG_HDR_H\n#define LWESP_CLI_CONFIG_HDR_H\n\n#include \"lwesp/lwesp_opt.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         CLI\n * \\defgroup        CLI_CONFIG Configuration\n * \\brief           Default CLI configuration\n * \\{\n *\n * Configuration for command line interface (CLI).\n */\n\n/**\n * \\brief           CLI promet, printed on every NL\n */\n#ifndef CLI_PROMPT\n#define CLI_PROMPT \"> \"\n#endif\n\n/**\n * \\brief           CLI NL, default is NL and CR\n */\n#ifndef CLI_NL\n#define CLI_NL \"\\r\\n\"\n#endif\n\n/**\n * \\brief           Max CLI command length\n */\n#ifndef CLI_MAX_CMD_LENGTH\n#define CLI_MAX_CMD_LENGTH 256\n#endif\n\n/**\n * \\brief           Max sotred CLI commands to history\n */\n#ifndef CLI_CMD_HISTORY\n#define CLI_CMD_HISTORY 10\n#endif\n\n/**\n * \\brief           Max CLI arguments in a single command\n */\n#ifndef CLI_MAX_NUM_OF_ARGS\n#define CLI_MAX_NUM_OF_ARGS 16\n#endif\n\n/**\n * \\brief           Max modules for CLI\n */\n#ifndef CLI_MAX_MODULES\n#define CLI_MAX_MODULES 16\n#endif\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_CLI_CONFIG_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/apps/lwesp_apps.h",
    "content": "/**\n * \\file            lwesp_apps.h\n * \\brief           Applications main header file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_APPS_HDR_H\n#define LWESP_APPS_HDR_H\n\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\defgroup        LWESP_APPS Applications\n * \\brief           Applications based on ESP stack\n * \\{\n */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_HTTP_SERVER_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/apps/lwesp_http_server.h",
    "content": "/**\n * \\file            lwesp_http_server.h\n * \\brief           HTTP server with callback API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_HTTP_SERVER_HDR_H\n#define LWESP_HTTP_SERVER_HDR_H\n\n#include \"lwesp/apps/lwesp_apps.h\"\n#include \"lwesp/lwesp.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP_APPS\n * \\defgroup        LWESP_APP_HTTP_SERVER HTTP server\n * \\brief           HTTP server based on callback API\n * \\{\n */\n\n/**\n * \\defgroup        LWESP_OPT_APP_HTTP Configuration\n * \\brief           Configuration of HTTP server app\n * \\{\n */\n\n/**\n * \\brief           Server debug default setting\n */\n#ifndef LWESP_CFG_DBG_SERVER\n#define LWESP_CFG_DBG_SERVER LWESP_DBG_OFF\n#endif\n\n#ifndef HTTP_SSI_TAG_START\n#define HTTP_SSI_TAG_START     \"<!--#\" /*!< SSI tag start string */\n#define HTTP_SSI_TAG_START_LEN 5       /*!< SSI tag start length */\n#endif\n\n#ifndef HTTP_SSI_TAG_END\n#define HTTP_SSI_TAG_END     \"-->\" /*!< SSI tag end string */\n#define HTTP_SSI_TAG_END_LEN 3     /*!< SSI tag end length */\n#endif\n\n/**\n * \\brief           Maximal length of tag name excluding start and end parts of tag\n */\n#ifndef HTTP_SSI_TAG_MAX_LEN\n#define HTTP_SSI_TAG_MAX_LEN 10\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for POST request\n */\n#ifndef HTTP_SUPPORT_POST\n#define HTTP_SUPPORT_POST 1\n#endif\n\n/**\n * \\brief           Maximal length of allowed uri length including parameters in format `/uri/sub/path?param=value`\n */\n#ifndef HTTP_MAX_URI_LEN\n#define HTTP_MAX_URI_LEN 256\n#endif\n\n/**\n * \\brief           Maximal number of parameters in URI\n */\n#ifndef HTTP_MAX_PARAMS\n#define HTTP_MAX_PARAMS 16\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` method not allowed response.\n *\n * Response is used in case user makes HTTP request with method\n * which is not on the list of allowed methods. See \\ref http_req_method_t\n *\n * \\note            When disabled, connection will be closed without response\n */\n#ifndef HTTP_USE_METHOD_NOTALLOWED_RESP\n#define HTTP_USE_METHOD_NOTALLOWED_RESP 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `1` default static files\n *\n * To allow fast startup of server development,\n * several static files are included by default:\n *  - /index.html\n *  - /index.shtml\n *  - /js/style.css\n *  - /js/js.js\n */\n#ifndef HTTP_USE_DEFAULT_STATIC_FILES\n#define HTTP_USE_DEFAULT_STATIC_FILES 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` dynamic headers support\n *\n * With dynamic headers enabled, script will try to detect most common\n * file extensions and will try to response with:\n *  - HTTP response code as first line\n *  - Server name as second line\n *  - Content type as third line including end of headers (empty line)\n */\n#ifndef HTTP_DYNAMIC_HEADERS\n#define HTTP_DYNAMIC_HEADERS 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` content length header for response\n *\n * If response has fixed length without SSI tags,\n * dynamic headers will try to include \"Content-Length\" header\n * as part of response message sent to client\n *\n * \\note            In order to use this, \\ref HTTP_DYNAMIC_HEADERS must be enabled\n */\n#ifndef HTTP_DYNAMIC_HEADERS_CONTENT_LEN\n#define HTTP_DYNAMIC_HEADERS_CONTENT_LEN 1\n#endif\n\n/**\n * \\brief           Default server name for `Server: x` response dynamic header\n */\n#ifndef HTTP_SERVER_NAME\n#define HTTP_SERVER_NAME \"ESP8266 AT Lib\"\n#endif\n\n/**\n * \\}\n */\n\n/**\n * \\brief           Maximal number of headers we can control\n */\n#define HTTP_MAX_HEADERS 4\n\nstruct http_state;\nstruct http_fs_file;\n\n/**\n * \\brief           HTTP parameters on http URI in format `?param1=value1&param2=value2&...`\n */\ntypedef struct {\n    const char* name;  /*!< Name of parameter */\n    const char* value; /*!< Parameter value */\n} http_param_t;\n\n/**\n * \\brief           CGI callback function\n * \\param[in]       params: Pointer to list of parameteres and their values\n * \\param[in]       params_len: Number of parameters\n * \\return          Function must return a new URI which is used later\n *                  as response string, such as \"/index.html\" or similar\n */\ntypedef char* (*http_cgi_fn)(http_param_t* params, size_t params_len);\n\n/**\n * \\brief           CGI structure to register handlers on URI paths\n */\ntypedef struct {\n    const char* uri; /*!< URI path for CGI handler */\n    http_cgi_fn fn;  /*!< Callback function to call when we have a CGI match */\n} http_cgi_t;\n\n/**\n * \\brief           Post request started with non-zero content length function prototype\n * \\param[in]       hs: HTTP state\n * \\param[in]       uri: POST request URI\n * \\param[in]       content_length: Total content length (Content-Length HTTP parameter) in units of bytes\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\ntypedef lwespr_t (*http_post_start_fn)(struct http_state* hs, const char* uri, uint32_t content_length);\n\n/**\n * \\brief           Post data received on request function prototype\n * \\note            This function may be called multiple time until content_length from \\ref http_post_start_fn callback is not reached\n * \\param[in]       hs: HTTP state\n * \\param[in]       pbuf: Packet buffer wit reciveed data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\ntypedef lwespr_t (*http_post_data_fn)(struct http_state* hs, lwesp_pbuf_p pbuf);\n\n/**\n * \\brief           End of POST data request function prototype\n * \\param[in]       hs: HTTP state\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\ntypedef lwespr_t (*http_post_end_fn)(struct http_state* hs);\n\n/**\n * \\brief           SSI (Server Side Includes) callback function prototype\n * \\note            User can use server write functions to directly write to connection output\n * \\param[in]       hs: HTTP state\n * \\param[in]       tag_name: Name of TAG to replace with user content\n * \\param[in]       tag_len: Length of TAG\n * \\retval          1: Everything was written on this tag\n * \\retval          0: There are still data to write to output which means\n *                     callback will be called again for user to process all the data\n */\ntypedef size_t (*http_ssi_fn)(struct http_state* hs, const char* tag_name, size_t tag_len);\n\n/**\n * \\brief           File system open file function\n *                  Function is called when user file system (FAT or similar) should be invoked to open a file from specific path\n * \\param[in]       file: Pointer to file where user has to set length of file if opening was successful\n * \\param[in]       path: Path of file to open\n * \\return          1 if file is opened, 0 otherwise\n */\ntypedef uint8_t (*http_fs_open_fn)(struct http_fs_file* file, const char* path);\n\n/**\n * \\brief           File system read file function\n *                  Function may be called for `2` purposes. First is to read data and second to get remaining length of file to read\n * \\param[in]       file: File pointer to read content\n * \\param[in]       buff: Buffer to read data to. When parameter is set to NULL, number of remaining bytes available to read should be returned\n * \\param[in]       btr: Number of bytes to read from file. This parameter has no meaning when buff is NULL\n * \\return          Number of bytes read or number of bytes available to read\n */\ntypedef uint32_t (*http_fs_read_fn)(struct http_fs_file* file, void* buff, size_t btr);\n\n/**\n * \\brief           Close file callback function\n * \\param[in]       file: File to close\n * \\return          `1` on success, `0` otherwise\n */\ntypedef uint8_t (*http_fs_close_fn)(struct http_fs_file* file);\n\n/**\n * \\brief           HTTP server initialization structure\n */\ntypedef struct {\n    /* POST request related functions */\n#if HTTP_SUPPORT_POST || __DOXYGEN__\n    http_post_start_fn post_start_fn; /*!< Callback function for post start */\n    http_post_data_fn post_data_fn;   /*!< Callback functon for post data */\n    http_post_end_fn post_end_fn;     /*!< Callback functon for post end */\n#endif                                /* HTTP_SUPPORT_POST || __DOXYGEN__ */\n\n    /* CGI related */\n    const http_cgi_t* cgi; /*!< Pointer to array of CGI entries. Set to NULL if not used */\n    size_t cgi_count;      /*!< Length of CGI array. Set to 0 if not used */\n\n    /* SSI related */\n    http_ssi_fn ssi_fn; /*!< SSI callback function */\n\n    /* File system related */\n    http_fs_open_fn fs_open;   /*!< Open file function callback */\n    http_fs_read_fn fs_read;   /*!< Read file function callback */\n    http_fs_close_fn fs_close; /*!< Close file function callback */\n} http_init_t;\n\n/**\n * \\brief           Request method type\n */\ntypedef enum {\n    HTTP_METHOD_NOTALLOWED, /*!< HTTP method is not allowed */\n    HTTP_METHOD_GET,        /*!< HTTP request method GET */\n#if HTTP_SUPPORT_POST || __DOXYGEN__\n    HTTP_METHOD_POST, /*!< HTTP request method POST */\n#endif                /* HTTP_SUPPORT_POST || __DOXYGEN__ */\n} http_req_method_t;\n\n/**\n * \\brief           List of SSI TAG parsing states\n */\ntypedef enum {\n    HTTP_SSI_STATE_WAIT_BEGIN = 0x00, /*!< Waiting beginning of tag */\n    HTTP_SSI_STATE_BEGIN = 0x01,      /*!< Beginning detected, parsing it */\n    HTTP_SSI_STATE_TAG = 0x02,        /*!< Parsing TAG value */\n    HTTP_SSI_STATE_END = 0x03,        /*!< Parsing end of TAG */\n} http_ssi_state_t;\n\n/**\n * \\brief           HTTP file system table structure of static files in device memory\n */\ntypedef struct {\n    const char* path; /*!< File path, ex. \"/index.html\" */\n    const void* data; /*!< Pointer to file data */\n    uint32_t size;    /*!< Size of file in units of bytes */\n} http_fs_file_table_t;\n\n/**\n * \\brief           HTTP response file structure\n */\ntypedef struct http_fs_file {\n    const uint8_t* data; /*!< Pointer to data array in case file is static */\n    uint8_t is_static;   /*!< Flag indicating file is static and no dynamic read is required */\n\n    uint32_t size; /*!< Total length of file */\n    uint32_t fptr; /*!< File pointer to indicate next read position */\n\n    const uint16_t* rem_open_files; /*!< Pointer to number of remaining open files.\n                                                        User can use value on this pointer to get number of other opened files */\n    void* arg;                      /*!< User custom argument, may be used for user specific file system object */\n} http_fs_file_t;\n\n/**\n * \\brief           HTTP state structure\n */\ntypedef struct http_state {\n    lwesp_conn_p conn; /*!< Connection handle */\n    lwesp_pbuf_p p;    /*!< Header received pbuf chain */\n\n    size_t conn_mem_available; /*!< Available memory in connection send queue */\n    uint32_t written_total;    /*!< Total number of bytes written into send buffer */\n    uint32_t sent_total;       /*!< Number of bytes we already sent */\n\n    http_req_method_t req_method; /*!< Used request method */\n    uint8_t headers_received;     /*!< Did we fully received a headers? */\n    uint8_t process_resp;         /*!< Process with response flag */\n\n#if HTTP_SUPPORT_POST || __DOXYGEN__\n    uint32_t content_length;   /*!< Total expected content length for request (on POST) (without headers) */\n    uint32_t content_received; /*!< Content length received so far (POST request, without headers) */\n#endif                         /* HTTP_SUPPORT_POST || __DOXYGEN__ */\n\n    http_fs_file_t rlwesp_file; /*!< Response file structure */\n    uint8_t rlwesp_file_opened; /*!< Status if response file is opened and ready */\n    const uint8_t* buff;        /*!< Buffer pointer with data */\n    uint32_t buff_len;          /*!< Total length of buffer */\n    uint32_t buff_ptr;          /*!< Current buffer pointer */\n\n    void* arg; /*!< User optional argument */\n\n#if HTTP_DYNAMIC_HEADERS || __DOXYGEN__\n    const char* dyn_hdr_strs[HTTP_MAX_HEADERS]; /*!< Pointer to constant strings for dynamic header outputs */\n    size_t dyn_hdr_idx;                         /*!< Current header for processing on output */\n    size_t dyn_hdr_pos;                         /*!< Current position in current index for output */\n#if HTTP_DYNAMIC_HEADERS_CONTENT_LEN || __DOXYGEN__\n    char dyn_hdr_cnt_len[30]; /*!< Content length header response: \"Content-Length: 0123456789\\r\\n\" */\n#endif                        /* HTTP_DYNAMIC_HEADERS_CONTENT_LEN || __DOXYGEN__ */\n#endif                        /* HTTP_DYNAMIC_HEADERS || __DOXYGEN__ */\n\n    /* SSI tag parsing */\n    uint8_t is_ssi;             /*!< Flag if current request is SSI enabled */\n    http_ssi_state_t ssi_state; /*!< Current SSI state when parsing SSI tags */\n    char ssi_tag_buff[HTTP_SSI_TAG_START_LEN + HTTP_SSI_TAG_END_LEN + HTTP_SSI_TAG_MAX_LEN\n                      + 1];      /*!< Temporary buffer for SSI tag storing */\n    size_t ssi_tag_buff_ptr;     /*!< Current write pointer */\n    size_t ssi_tag_buff_written; /*!< Number of bytes written so far to output buffer in case tag is not valid */\n    size_t ssi_tag_len;          /*!< Length of SSI tag */\n    size_t ssi_tag_process_more; /*!< Set to `1` when we have to process tag multiple times */\n} http_state_t;\n\n/**\n * \\brief           Write string to HTTP server output\n * \\note            May only be called from SSI callback function\n * \\param[in]       hs: HTTP handle\n * \\param[in]       str: String to write\n * \\return          Number of bytes written to output\n * \\sa              lwesp_http_server_write\n */\n#define lwesp_http_server_write_string(hs, str) lwesp_http_server_write(hs, str, strlen(str))\n\nlwespr_t lwesp_http_server_init(const http_init_t* init, lwesp_port_t port);\nsize_t lwesp_http_server_write(http_state_t* hs, const void* data, size_t len);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_HTTP_SERVER_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/apps/lwesp_http_server_fs.h",
    "content": "/**\n * \\file            lwesp_http_server_fs.h\n * \\brief           Function declaration for file system\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_HTTP_SERVER_FS_HDR_H\n#define LWESP_HTTP_SERVER_FS_HDR_H\n\n#include \"lwesp/apps/lwesp_http_server.h\"\n#include \"lwesp/lwesp.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP_APP_HTTP_SERVER\n * \\defgroup        LWESP_APP_HTTP_SERVER_FS_FAT FAT File System\n * \\brief           FATFS file system implementation for dynamic files\n * \\{\n */\n\nuint8_t http_fs_open(http_fs_file_t* file, const char* path);\nuint32_t http_fs_read(http_fs_file_t* file, void* buff, size_t btr);\nuint8_t http_fs_close(http_fs_file_t* file);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_HTTP_SERVER_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/apps/lwesp_mqtt_client.h",
    "content": "/**\n * \\file            lwesp_mqtt_client.h\n * \\brief           MQTT client\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_APP_MQTT_CLIENT_HDR_H\n#define LWESP_APP_MQTT_CLIENT_HDR_H\n\n#include \"lwesp/apps/lwesp_mqtt_client_evt.h\"\n#include \"lwesp/lwesp_includes.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP_APPS\n * \\defgroup        LWESP_APP_MQTT_CLIENT MQTT client\n * \\brief           MQTT client\n * \\{\n */\n\n/**\n * \\brief           Quality of service enumeration\n */\ntypedef enum {\n    LWESP_MQTT_QOS_AT_MOST_ONCE =\n        0x00, /*!< Delivery is not guaranteed to arrive, but can arrive `up to 1 time` = non-critical packets where losses are allowed */\n    LWESP_MQTT_QOS_AT_LEAST_ONCE =\n        0x01, /*!< Delivery is quaranteed `at least once`, but it may be delivered multiple times with the same content */\n    LWESP_MQTT_QOS_EXACTLY_ONCE =\n        0x02, /*!< Delivery is quaranteed `exactly once` = very critical packets such as billing informations or similar */\n} lwesp_mqtt_qos_t;\n\nstruct lwesp_mqtt_client;\n\n/**\n * \\brief           Pointer to \\ref lwesp_mqtt_client_t structure\n */\ntypedef struct lwesp_mqtt_client* lwesp_mqtt_client_p;\n\n/**\n * \\brief           State of MQTT client\n */\ntypedef enum {\n    LWESP_MQTT_CONN_DISCONNECTED = 0x00, /*!< Connection with server is not established */\n    LWESP_MQTT_CONN_CONNECTING,          /*!< Client is connecting to server */\n    LWESP_MQTT_CONN_DISCONNECTING,       /*!< Client connection is disconnecting from server */\n    LWESP_MQTT_CONNECTING,               /*!< MQTT client is connecting... CONNECT command has been sent to server */\n    LWESP_MQTT_CONNECTED,                /*!< MQTT is fully connected and ready to send data on topics */\n} lwesp_mqtt_state_t;\n\n/**\n * \\brief           MQTT client information structure\n */\ntypedef struct {\n    const char* id; /*!< Client unique identifier. It is required and must be set by user */\n\n    const char* user; /*!< Authentication username. Set to `NULL` if not required */\n    const char* pass; /*!< Authentication password, set to `NULL` if not required */\n\n    uint16_t keep_alive; /*!< Keep-alive parameter in units of seconds.\n                                                    When set to `0`, functionality is disabled (not recommended) */\n\n    const char* will_topic;    /*!< Will topic */\n    const char* will_message;  /*!< Will message */\n    lwesp_mqtt_qos_t will_qos; /*!< Will topic quality of service */\n\n    uint8_t use_ssl; /*!< Connect to server using SSL connection with AT commands */\n} lwesp_mqtt_client_info_t;\n\n/**\n * \\brief           MQTT request object\n */\ntypedef struct {\n    uint8_t status;     /*!< Entry status flag for in use or pending bit */\n    uint16_t packet_id; /*!< Packet ID generated by client on publish */\n\n    void* arg;                  /*!< User defined argument */\n    uint32_t expected_sent_len; /*!< Number of total bytes which must be sent\n                                                    on connection before we can say \"packet was sent\". */\n\n    uint32_t timeout_start_time; /*!< Timeout start time in units of milliseconds */\n} lwesp_mqtt_request_t;\n\n/**\n * \\brief           MQTT event types\n */\ntypedef enum {\n    LWESP_MQTT_EVT_CONNECT,      /*!< MQTT client connect event */\n    LWESP_MQTT_EVT_SUBSCRIBE,    /*!< MQTT client subscribed to specific topic */\n    LWESP_MQTT_EVT_UNSUBSCRIBE,  /*!< MQTT client unsubscribed from specific topic */\n    LWESP_MQTT_EVT_PUBLISH,      /*!< MQTT client publish message to server event.\n                                        \\note   When publishing packet with quality of service \\ref LWESP_MQTT_QOS_AT_MOST_ONCE,\n                                        you may not receive event, even if packet was successfully sent,\n                                        thus do not rely on this event for packet with `qos = LWESP_MQTT_QOS_AT_MOST_ONCE` */\n    LWESP_MQTT_EVT_PUBLISH_RECV, /*!< MQTT client received a publish message from server */\n    LWESP_MQTT_EVT_DISCONNECT,   /*!< MQTT client disconnected from MQTT server */\n    LWESP_MQTT_EVT_KEEP_ALIVE,   /*!< MQTT keep-alive event.\n                                        It gets invoked after client and server exchange successful \"keep-alive message\",\n                                        defined by MQTT protocol */\n    LWESP_MQTT_EVT_CONN_POLL,    /*!< Local ESP connection poll event.\n                                        When connection is active, stack periodically sends polling events to user.\n                                        This event is propagated to user MQTT space */\n} lwesp_mqtt_evt_type_t;\n\n/**\n * \\brief           List of possible results from MQTT server when executing connect command\n */\ntypedef enum {\n    LWESP_MQTT_CONN_STATUS_ACCEPTED = 0x00,                 /*!< Connection accepted and ready to use */\n    LWESP_MQTT_CONN_STATUS_REFUSED_PROTOCOL_VERSION = 0x01, /*!< Connection Refused, unacceptable protocol version */\n    LWESP_MQTT_CONN_STATUS_REFUSED_ID = 0x02,               /*!< Connection refused, identifier rejected  */\n    LWESP_MQTT_CONN_STATUS_REFUSED_SERVER = 0x03,           /*!< Connection refused, server unavailable */\n    LWESP_MQTT_CONN_STATUS_REFUSED_USER_PASS = 0x04,        /*!< Connection refused, bad user name or password */\n    LWESP_MQTT_CONN_STATUS_REFUSED_NOT_AUTHORIZED = 0x05,   /*!< Connection refused, not authorized */\n    LWESP_MQTT_CONN_STATUS_TCP_FAILED = 0x100,              /*!< TCP connection to server was not successful */\n} lwesp_mqtt_conn_status_t;\n\n/**\n * \\brief           MQTT event structure for callback function\n */\ntypedef struct {\n    lwesp_mqtt_evt_type_t type; /*!< Event type */\n\n    union {\n        struct {\n            lwesp_mqtt_conn_status_t status; /*!< Connection status with MQTT */\n        } connect;                           /*!< Event for connecting to server */\n\n        struct {\n            uint8_t is_accepted; /*!< Status if client was accepted to MQTT prior disconnect event */\n        } disconnect;            /*!< Event for disconnecting from server */\n\n        struct {\n            void* arg;       /*!< User argument for callback function */\n            lwespr_t res;    /*!< Response status */\n        } sub_unsub_scribed; /*!< Event for (un)subscribe to/from topics */\n\n        struct {\n            void* arg;    /*!< User argument for callback function */\n            lwespr_t res; /*!< Response status */\n        } publish;        /*!< Published event */\n\n        struct {\n            const uint8_t* topic; /*!< Pointer to topic identifier */\n            size_t topic_len;     /*!< Length of topic */\n            const void* payload;  /*!< Topic payload */\n            size_t payload_len;   /*!< Length of topic payload */\n            uint8_t dup;          /*!< Duplicate flag if message was sent again */\n            lwesp_mqtt_qos_t qos; /*!< Received packet quality of service */\n            uint8_t retain;       /*!< Retain status of the received packet */\n        } publish_recv;           /*!< Publish received event */\n    } evt;                        /*!< Event data parameters */\n} lwesp_mqtt_evt_t;\n\n/**\n * \\brief           MQTT event callback function\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: MQTT event with type and related data\n */\ntypedef void (*lwesp_mqtt_evt_fn)(lwesp_mqtt_client_p client, lwesp_mqtt_evt_t* evt);\n\nlwesp_mqtt_client_p lwesp_mqtt_client_new(size_t tx_buff_len, size_t rx_buff_len);\nvoid lwesp_mqtt_client_delete(lwesp_mqtt_client_p client);\n\nlwespr_t lwesp_mqtt_client_connect(lwesp_mqtt_client_p client, const char* host, lwesp_port_t port,\n                                   lwesp_mqtt_evt_fn evt_fn, const lwesp_mqtt_client_info_t* info);\nlwespr_t lwesp_mqtt_client_disconnect(lwesp_mqtt_client_p client);\nuint8_t lwesp_mqtt_client_is_connected(lwesp_mqtt_client_p client);\n\nlwespr_t lwesp_mqtt_client_subscribe(lwesp_mqtt_client_p client, const char* topic, lwesp_mqtt_qos_t qos, void* arg);\nlwespr_t lwesp_mqtt_client_unsubscribe(lwesp_mqtt_client_p client, const char* topic, void* arg);\n\nlwespr_t lwesp_mqtt_client_publish(lwesp_mqtt_client_p client, const char* topic, const void* payload, uint16_t len,\n                                   lwesp_mqtt_qos_t qos, uint8_t retain, void* arg);\n\nvoid* lwesp_mqtt_client_get_arg(lwesp_mqtt_client_p client);\nvoid lwesp_mqtt_client_set_arg(lwesp_mqtt_client_p client, void* arg);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_APP_MQTT_CLIENT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/apps/lwesp_mqtt_client_api.h",
    "content": "/**\n * \\file            lwesp_mqtt_client_api.h\n * \\brief           MQTT client API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_APP_MQTT_CLIENT_API_HDR_H\n#define LWESP_APP_MQTT_CLIENT_API_HDR_H\n\n#include \"lwesp/apps/lwesp_mqtt_client.h\"\n#include \"lwesp/lwesp.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP_APPS\n * \\defgroup        LWESP_APP_MQTT_CLIENT_API MQTT client API\n * \\brief           Sequential, single thread MQTT client API\n * \\{\n */\n\n/**\n * \\brief           MQTT API client structure\n */\nstruct lwesp_mqtt_client_api;\n\n/**\n * \\brief           MQTT API RX buffer\n */\ntypedef struct lwesp_mqtt_client_api_buf {\n    char* topic;          /*!< Topic data */\n    size_t topic_len;     /*!< Topic length */\n    uint8_t* payload;     /*!< Payload data */\n    size_t payload_len;   /*!< Payload length */\n    lwesp_mqtt_qos_t qos; /*!< Quality of service */\n} lwesp_mqtt_client_api_buf_t;\n\n/**\n * \\brief           Pointer to \\ref lwesp_mqtt_client_api structure\n */\ntypedef struct lwesp_mqtt_client_api* lwesp_mqtt_client_api_p;\n\n/**\n * \\brief           Pointer to \\ref lwesp_mqtt_client_api_buf_t structure\n */\ntypedef struct lwesp_mqtt_client_api_buf* lwesp_mqtt_client_api_buf_p;\n\nlwesp_mqtt_client_api_p lwesp_mqtt_client_api_new(size_t tx_buff_len, size_t rx_buff_len);\nvoid lwesp_mqtt_client_api_delete(lwesp_mqtt_client_api_p client);\nlwesp_mqtt_conn_status_t lwesp_mqtt_client_api_connect(lwesp_mqtt_client_api_p client, const char* host,\n                                                       lwesp_port_t port, const lwesp_mqtt_client_info_t* info);\nlwespr_t lwesp_mqtt_client_api_close(lwesp_mqtt_client_api_p client);\nlwespr_t lwesp_mqtt_client_api_subscribe(lwesp_mqtt_client_api_p client, const char* topic, lwesp_mqtt_qos_t qos);\nlwespr_t lwesp_mqtt_client_api_unsubscribe(lwesp_mqtt_client_api_p client, const char* topic);\nlwespr_t lwesp_mqtt_client_api_publish(lwesp_mqtt_client_api_p client, const char* topic, const void* data, size_t btw,\n                                       lwesp_mqtt_qos_t qos, uint8_t retain);\nuint8_t lwesp_mqtt_client_api_is_connected(lwesp_mqtt_client_api_p client);\nlwespr_t lwesp_mqtt_client_api_receive(lwesp_mqtt_client_api_p client, lwesp_mqtt_client_api_buf_p* p,\n                                       uint32_t timeout);\nvoid lwesp_mqtt_client_api_buf_free(lwesp_mqtt_client_api_buf_p p);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_APP_MQTT_CLIENT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/apps/lwesp_mqtt_client_evt.h",
    "content": "/**\n * \\file            lwesp_mqtt_client_evt.h\n * \\brief           MQTT client event helper functions\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_APP_MQTT_CLIENT_EVT_HDR_H\n#define LWESP_APP_MQTT_CLIENT_EVT_HDR_H\n\n#include \"lwesp/apps/lwesp_mqtt_client.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP_APP_MQTT_CLIENT\n * \\defgroup        LWESP_APP_MQTT_CLIENT_EVT Event helper functions\n * \\brief           Event helper functions\n * \\{\n */\n\n/**\n * \\brief           Get MQTT event type\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          MQTT Event type, value of \\ref lwesp_mqtt_evt_type_t enumeration\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_get_type(client, evt)           ((lwesp_mqtt_evt_type_t)(evt)->type)\n\n/**\n * \\anchor          LWESP_APP_MQTT_CLIENT_EVT_CONNECT\n * \\name            Connect event\n * \\{\n *\n * \\note            Use these functions on \\ref LWESP_MQTT_EVT_CONNECT event\n */\n\n/**\n * \\brief           Get connection status\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          Connection status. Member of \\ref lwesp_mqtt_conn_status_t\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_connect_get_status(client, evt) ((lwesp_mqtt_conn_status_t)(evt)->evt.connect.status)\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_APP_MQTT_CLIENT_EVT_DISCONNECT\n * \\name            Disconnect event\n * \\{\n *\n * \\note            Use these functions on \\ref LWESP_MQTT_EVT_DISCONNECT event\n */\n\n/**\n * \\brief           Check if MQTT client was accepted by server when disconnect event occurred\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          `1` on success, `0` otherwise\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_disconnect_is_accepted(client, evt)                                                      \\\n    ((lwesp_mqtt_conn_status_t)(evt)->evt.disconnect.is_accepted)\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_APP_MQTT_CLIENT_EVT_SUB_UNSUB\n * \\name            Subscribe/unsubscribe event\n * \\{\n *\n * \\note            Use these functions on \\ref LWESP_MQTT_EVT_SUBSCRIBE or \\ref LWESP_MQTT_EVT_UNSUBSCRIBE events\n */\n\n/**\n * \\brief           Get user argument used on \\ref lwesp_mqtt_client_subscribe\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          User argument\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_subscribe_get_argument(client, evt)       ((void*)(evt)->evt.sub_unsub_scribed.arg)\n\n/**\n * \\brief           Get result of subscribe event\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_subscribe_get_result(client, evt)         ((lwespr_t)(evt)->evt.sub_unsub_scribed.res)\n\n/**\n * \\brief           Get user argument used on \\ref lwesp_mqtt_client_unsubscribe\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          User argument\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_unsubscribe_get_argument(client, evt)     ((void*)(evt)->evt.sub_unsub_scribed.arg)\n\n/**\n * \\brief           Get result of unsubscribe event\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_unsubscribe_get_result(client, evt)       ((lwespr_t)(evt)->evt.sub_unsub_scribed.res)\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_APP_MQTT_CLIENT_EVT_PUBLISH_RECV\n * \\name            Publish receive event\n * \\{\n *\n * \\note            Use these functions on \\ref LWESP_MQTT_EVT_PUBLISH_RECV event\n */\n\n/**\n * \\brief           Get topic from received publish packet\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          Topic name\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_publish_recv_get_topic(client, evt)       ((const void*)(evt)->evt.publish_recv.topic)\n\n/**\n * \\brief           Get topic length from received publish packet\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          Topic length\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_publish_recv_get_topic_len(client, evt)   (LWESP_SZ((evt)->evt.publish_recv.topic_len))\n\n/**\n * \\brief           Get payload from received publish packet\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          Packet payload\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_publish_recv_get_payload(client, evt)     ((const void*)(evt)->evt.publish_recv.payload)\n\n/**\n * \\brief           Get payload length from received publish packet\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          Payload length\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_publish_recv_get_payload_len(client, evt) (LWESP_SZ((evt)->evt.publish_recv.payload_len))\n\n/**\n * \\brief           Check if packet is duplicated\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          `1` if duplicated, `0` otherwise\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_publish_recv_is_duplicate(client, evt)    (LWESP_U8((evt)->evt.publish_recv.dup))\n\n/**\n * \\brief           Get received quality of service\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          Member of \\ref lwesp_mqtt_qos_t enumeration\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_publish_recv_get_qos(client, evt)         ((evt)->evt.publish_recv.qos)\n\n/**\n * \\brief           Get received retain\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          `1` if retained, `0` otherwise\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_publish_recv_get_retain(client, evt)      ((evt)->evt.publish_recv.retain)\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_APP_MQTT_CLIENT_EVT_PUBLISH\n * \\name            Publish event\n * \\{\n *\n * \\note            Use these functions on \\ref LWESP_MQTT_EVT_PUBLISH event\n */\n\n/**\n * \\brief           Get user argument used on \\ref lwesp_mqtt_client_publish\n * \\param[in]       client: MQTT client\n * \\param[in]       evt: Event handle\n * \\return          User argument\n * \\hideinitializer\n */\n#define lwesp_mqtt_client_evt_publish_get_argument(client, evt)         ((void*)(evt)->evt.publish.arg)\n\n/**\n* \\brief           Get result of publish event\n* \\param[in]       client: MQTT client\n* \\param[in]       evt: Event handle\n* \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n* \\hideinitializer\n*/\n#define lwesp_mqtt_client_evt_publish_get_result(client, evt)           ((lwespr_t)(evt)->evt.publish.res)\n\n/**\n * \\}\n */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_APP_MQTT_CLIENT_EVT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp.h",
    "content": "/**\n * \\file            lwesp.h\n * \\brief           LwESP\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_HDR_H\n#define LWESP_HDR_H\n\n#include \"lwesp/lwesp_includes.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\defgroup        LWESP Lightweight ESP-AT parser library\n * \\brief           Lightweight ESP-AT parser\n * \\{\n */\n\nlwespr_t lwesp_init(lwesp_evt_fn cb_func, const uint32_t blocking);\nlwespr_t lwesp_reset(const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_reset_with_delay(uint32_t delay, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                                const uint32_t blocking);\n\nlwespr_t lwesp_restore(const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_set_at_baudrate(uint32_t baud, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                               const uint32_t blocking);\nlwespr_t lwesp_set_wifi_mode(lwesp_mode_t mode, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                             const uint32_t blocking);\nlwespr_t lwesp_get_wifi_mode(lwesp_mode_t* mode, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                             const uint32_t blocking);\n\nlwespr_t lwesp_update_sw(const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\n\nlwespr_t lwesp_core_lock(void);\nlwespr_t lwesp_core_unlock(void);\n\nlwespr_t lwesp_device_set_present(uint8_t present, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                                  const uint32_t blocking);\nuint8_t lwesp_device_is_present(void);\n\nuint8_t lwesp_delay(const uint32_t ms);\n\nlwespr_t lwesp_get_current_at_fw_version(lwesp_sw_version_t* const version);\nlwespr_t lwesp_get_min_at_fw_version(lwesp_sw_version_t* const version);\n\n/**\n * \\brief           Set and format major, minor and patch values to firmware version\n * \\param[in]       v: Version output, pointer to \\ref lwesp_sw_version_t structure\n * \\param[in]       version_: Version in 32-bit format\n * \\hideinitializer\n */\n#define lwesp_set_fw_version(v, version_)                                                                              \\\n    do {                                                                                                               \\\n        (v)->version = (version_);                                                                                     \\\n    } while (0)\n\nlwesp_device_t lwesp_device_get_device(void);\nuint8_t lwesp_device_is_device(lwesp_device_t device);\n\n/* Deprecated and will be removed soon */\n#if LWESP_CFG_ESP8266 || __DOXYGEN__\nuint8_t lwesp_device_is_esp8266(void);\n#else\n#define lwesp_device_is_esp8266() ((uint8_t)0)\n#endif /* LWESP_CFG_ESP8266 || __DOXYGEN__ */\n#if LWESP_CFG_ESP32 || __DOXYGEN__\nuint8_t lwesp_device_is_esp32(void);\n#else\n#define lwesp_device_is_esp32() ((uint8_t)0)\n#endif /* LWESP_CFG_ESP32 || __DOXYGEN__ */\n#if LWESP_CFG_ESP32_C3 || __DOXYGEN__\nuint8_t lwesp_device_is_esp32_c3(void);\n#else\n#define lwesp_device_is_esp32_c3() ((uint8_t)0)\n#endif /* LWESP_CFG_ESP32_C3 || __DOXYGEN__ */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_ap.h",
    "content": "/**\n * \\file            lwesp_ap.h\n * \\brief           Access point API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_AP_HDR_H\n#define LWESP_AP_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_AP Access point\n * \\brief           Access point\n * \\{\n *\n * Functions to manage access point (AP) on ESP device.\n *\n * In order to be able to use AP feature, \\ref LWESP_CFG_MODE_ACCESS_POINT must be enabled.\n */\n\nlwespr_t lwesp_ap_getip(lwesp_ip_t* ip, lwesp_ip_t* gw, lwesp_ip_t* nm, const lwesp_api_cmd_evt_fn evt_fn,\n                        void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_ap_setip(const lwesp_ip_t* ip, const lwesp_ip_t* gw, const lwesp_ip_t* nm,\n                        const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_ap_getmac(lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                         const uint32_t blocking);\nlwespr_t lwesp_ap_setmac(const lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                         const uint32_t blocking);\n\nlwespr_t lwesp_ap_get_config(lwesp_ap_conf_t* ap_conf, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                             const uint32_t blocking);\nlwespr_t lwesp_ap_set_config(const char* ssid, const char* pwd, uint8_t ch, lwesp_ecn_t ecn, uint8_t max_sta,\n                             uint8_t hid, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                             const uint32_t blocking);\n\nlwespr_t lwesp_ap_list_sta(lwesp_sta_t* sta, size_t stal, size_t* staf, const lwesp_api_cmd_evt_fn evt_fn,\n                           void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_ap_disconn_sta(const lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                              const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_AP_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_ble.h",
    "content": "/**\n * \\file            lwesp_ble.h\n * \\brief           Bluetooth Low Energy\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_BLE_HDR_H\n#define LWESP_BLE_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_BLE Bluetooth Low Energy\n * \\brief           Bluetooth Low Energy\n * \\{\n *\n * Functions to manage BLE protocol on some of ESP devices (if hardware supports it)\n *\n * \\ref LWESP_CFG_BLE must be enabled to use this feature.\n */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_BLE_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_bt.h",
    "content": "/**\n * \\file            lwesp_ble.h\n * \\brief           Bluetooth Low Energy\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_BT_HDR_H\n#define LWESP_BT_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_BT Bluetooth Classic\n * \\brief           Bluetooth Classic\n * \\{\n *\n * Functions to manage Bluetooth Classic protocol on some of ESP devices (if hardware supports it)\n *\n * \\ref LWESP_CFG_BT must be enabled to use this feature.\n */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_BT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_buff.h",
    "content": "/**\n * \\file            lwesp_buff.h\n * \\brief           Ring buffer manager\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_BUFF_HDR_H\n#define LWESP_BUFF_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_BUFF Ring buffer\n * \\brief           Generic ring buffer\n * \\{\n */\n\n/* --- Buffer unique part starts --- */\n/**\n * \\brief           Buffer function/typedef prefix string\n *\n * It is used to change function names in zero time to easily re-use same library between applications.\n * Use `#define BUF_PREF(x)    my_prefix_ ## x` to change all function names to (for example) `my_prefix_buff_init`\n *\n * \\note            Modification of this macro must be done in header and source file aswell\n */\n#define BUF_PREF(x) lwesp_##x\n/* --- Buffer unique part ends --- */\n\nuint8_t BUF_PREF(buff_init)(BUF_PREF(buff_t) * buff, size_t size);\nvoid BUF_PREF(buff_free)(BUF_PREF(buff_t) * buff);\nvoid BUF_PREF(buff_reset)(BUF_PREF(buff_t) * buff);\n\n/* Read/Write functions */\nsize_t BUF_PREF(buff_write)(BUF_PREF(buff_t) * buff, const void* data, size_t btw);\nsize_t BUF_PREF(buff_read)(BUF_PREF(buff_t) * buff, void* data, size_t btr);\nsize_t BUF_PREF(buff_peek)(BUF_PREF(buff_t) * buff, size_t skip_count, void* data, size_t btp);\n\n/* Buffer size information */\nsize_t BUF_PREF(buff_get_free)(BUF_PREF(buff_t) * buff);\nsize_t BUF_PREF(buff_get_full)(BUF_PREF(buff_t) * buff);\n\n/* Read data block management */\nvoid* BUF_PREF(buff_get_linear_block_read_address)(BUF_PREF(buff_t) * buff);\nsize_t BUF_PREF(buff_get_linear_block_read_length)(BUF_PREF(buff_t) * buff);\nsize_t BUF_PREF(buff_skip)(BUF_PREF(buff_t) * buff, size_t len);\n\n/* Write data block management */\nvoid* BUF_PREF(buff_get_linear_block_write_address)(BUF_PREF(buff_t) * buff);\nsize_t BUF_PREF(buff_get_linear_block_write_length)(BUF_PREF(buff_t) * buff);\nsize_t BUF_PREF(buff_advance)(BUF_PREF(buff_t) * buff, size_t len);\n\n#undef BUF_PREF /* Prefix not needed anymore */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_BUFF_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_cli.h",
    "content": "/**\n * \\file            lwesp_cli.h\n * \\brief           ESP CLI commands\n */\n\n/*\n * Copyright (c) 2019 Miha CESNIK\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Miha CESNIK <>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_CLI_HDR_H\n#define LWESP_CLI_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_CLI Command line interface\n * \\brief           Command line interface\n * \\{\n */\n\nvoid lwesp_cli_register_commands(void);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_CLI_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_conn.h",
    "content": "/**\n * \\file            lwesp_conn.h\n * \\brief           Connection API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_CONN_HDR_H\n#define LWESP_CONN_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_CONN Connection API\n * \\brief           Connection API functions\n * \\{\n */\n\nlwespr_t lwesp_conn_start(lwesp_conn_p* conn, lwesp_conn_type_t type, const char* const remote_host,\n                          lwesp_port_t remote_port, void* const arg, lwesp_evt_fn conn_evt_fn, const uint32_t blocking);\nlwespr_t lwesp_conn_startex(lwesp_conn_p* conn, lwesp_conn_start_t* start_struct, void* const arg,\n                            lwesp_evt_fn conn_evt_fn, const uint32_t blocking);\n\nlwespr_t lwesp_conn_close(lwesp_conn_p conn, const uint32_t blocking);\nlwespr_t lwesp_conn_send(lwesp_conn_p conn, const void* data, size_t btw, size_t* const bw, const uint32_t blocking);\nlwespr_t lwesp_conn_sendto(lwesp_conn_p conn, const lwesp_ip_t* const ip, lwesp_port_t port, const void* data,\n                           size_t btw, size_t* bw, const uint32_t blocking);\nlwespr_t lwesp_conn_set_arg(lwesp_conn_p conn, void* const arg);\nvoid* lwesp_conn_get_arg(lwesp_conn_p conn);\nuint8_t lwesp_conn_is_client(lwesp_conn_p conn);\nuint8_t lwesp_conn_is_server(lwesp_conn_p conn);\nuint8_t lwesp_conn_is_active(lwesp_conn_p conn);\nuint8_t lwesp_conn_is_closed(lwesp_conn_p conn);\nint8_t lwesp_conn_getnum(lwesp_conn_p conn);\nlwespr_t lwesp_conn_set_ssl_buffersize(size_t size, const uint32_t blocking);\nlwespr_t lwesp_get_conns_status(const uint32_t blocking);\nlwesp_conn_p lwesp_conn_get_from_evt(lwesp_evt_t* evt);\nlwespr_t lwesp_conn_write(lwesp_conn_p conn, const void* data, size_t btw, uint8_t flush, size_t* const mem_available);\nlwespr_t lwesp_conn_recved(lwesp_conn_p conn, lwesp_pbuf_p pbuf);\nsize_t lwesp_conn_get_total_recved_count(lwesp_conn_p conn);\n\nuint8_t lwesp_conn_get_remote_ip(lwesp_conn_p conn, lwesp_ip_t* ip);\nlwesp_port_t lwesp_conn_get_remote_port(lwesp_conn_p conn);\nlwesp_port_t lwesp_conn_get_local_port(lwesp_conn_p conn);\nlwespr_t lwesp_conn_ssl_set_config(uint8_t link_id, uint8_t auth_mode, uint8_t pki_number, uint8_t ca_number,\n                                   const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_CONN_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_debug.h",
    "content": "/**\n * \\file            lwesp_debug.h\n * \\brief           Debugging inside ESP stack\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_DEBUG_HDR_H\n#define LWESP_DEBUG_HDR_H\n\n#include <stdint.h>\n#include <string.h>\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_DEBUG Debug support\n * \\brief           Debug support module to track library flow\n * \\{\n */\n\n#if LWESP_CFG_DBG && !defined(LWESP_CFG_DBG_OUT)\n#warning \"LWESP_CFG_DBG_OUT is not defined but debugging is enabled!\"\n#endif\n\n#if (LWESP_CFG_DBG && defined(LWESP_CFG_DBG_OUT)) || __DOXYGEN__\n/**\n * \\brief           Print message to the debug \"window\" if enabled\n * \\param[in]       c: Condition if debug of specific type is enabled\n * \\param[in]       fmt: Formatted string for debug\n * \\param[in]       ...: Variable parameters for formatted string\n */\n#define LWESP_DEBUGF(c, fmt, ...)                                                                                      \\\n    do {                                                                                                               \\\n        if (((c) & (LWESP_DBG_ON)) && ((c) & (LWESP_CFG_DBG_TYPES_ON))                                                 \\\n            && ((c)&LWESP_DBG_LVL_MASK) >= (LWESP_CFG_DBG_LVL_MIN)) {                                                  \\\n            LWESP_CFG_DBG_OUT(fmt, ##__VA_ARGS__);                                                                     \\\n        }                                                                                                              \\\n    } while (0)\n\n/**\n * \\brief           Print message to the debug \"window\" if enabled when specific condition is met\n * \\param[in]       c: Condition if debug of specific type is enabled\n * \\param[in]       cond: Debug only if this condition is true\n * \\param[in]       fmt: Formatted string for debug\n * \\param[in]       ...: Variable parameters for formatted string\n */\n#define LWESP_DEBUGW(c, cond, fmt, ...)                                                                                \\\n    do {                                                                                                               \\\n        if (cond) {                                                                                                    \\\n            LWESP_DEBUGF(c, fmt, ##__VA_ARGS__);                                                                       \\\n        }                                                                                                              \\\n    } while (0)\n#else\n#undef LWESP_CFG_DBG\n#define LWESP_CFG_DBG LWESP_DBG_OFF\n#define LWESP_DEBUGF(c, fmt, ...)\n#define LWESP_DEBUGW(c, cond, fmt, ...)\n#endif /* (LWESP_CFG_DBG && defined(LWESP_CFG_DBG_OUT)) || __DOXYGEN__ */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_DEBUG_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_debug_types.h",
    "content": "/**\n * \\file            lwesp_debug_types.h\n * \\brief           Debugging types\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_DEBUG_TYPES_HDR_H\n#define LWESP_DEBUG_TYPES_HDR_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP_DEBUG\n * \\{\n */\n\n#define LWESP_DBG_ON          0x80 /*!< Indicates debug is enabled */\n#define LWESP_DBG_OFF         0    /*!< Indicates debug is disabled */\n\n/**\n * \\anchor          LWESP_DBG_LVL\n * \\name            Debug levels\n * \\brief           List of debug levels\n * \\{\n */\n\n#define LWESP_DBG_LVL_ALL     0x00 /*!< Print all messages of all types */\n#define LWESP_DBG_LVL_WARNING 0x01 /*!< Print warning and upper messages */\n#define LWESP_DBG_LVL_DANGER  0x02 /*!< Print danger errors */\n#define LWESP_DBG_LVL_SEVERE  0x03 /*!< Print severe problems affecting program flow */\n#define LWESP_DBG_LVL_MASK    0x03 /*!< Mask for getting debug level */\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_DBG_TYPE\n * \\name            Debug types\n * \\brief           List of debug types\n * \\{\n */\n\n#define LWESP_DBG_TYPE_TRACE  0x40 /*!< Debug trace messages for program flow */\n#define LWESP_DBG_TYPE_STATE  0x20 /*!< Debug state messages (such as state machines) */\n#define LWESP_DBG_TYPE_ALL    (LWESP_DBG_TYPE_TRACE | LWESP_DBG_TYPE_STATE) /*!< All debug types */\n\n/**\n * \\}\n */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_DEBUG_TYPES_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_dhcp.h",
    "content": "/**\n * \\file            lwesp_dhcp.h\n * \\brief           DHCP API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_DHCP_HDR_H\n#define LWESP_DHCP_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_DHCP DHCP\n * \\brief           DHCP config\n * \\{\n */\n\nlwespr_t lwesp_dhcp_set_config(uint8_t sta, uint8_t ap, uint8_t en, const lwesp_api_cmd_evt_fn evt_fn,\n                               void* const evt_arg, const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_DHCP_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_dns.h",
    "content": "/**\n * \\file            lwesp_dns.h\n * \\brief           DNS API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_DNS_HDR_H\n#define LWESP_DNS_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_DNS Domain name server\n * \\brief           Domain name server\n * \\{\n */\n\nlwespr_t lwesp_dns_gethostbyname(const char* host, lwesp_ip_t* const ip, const lwesp_api_cmd_evt_fn evt_fn,\n                                 void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_dns_get_config(lwesp_ip_t* s1, lwesp_ip_t* s2, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                              const uint32_t blocking);\nlwespr_t lwesp_dns_set_config(uint8_t en, const char* s1, const char* s2, const lwesp_api_cmd_evt_fn evt_fn,\n                              void* const evt_arg, const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_DNS_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_evt.h",
    "content": "/**\n * \\file            lwesp_evt.h\n * \\brief           Event helper functions\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_EVT_HDR_H\n#define LWESP_EVT_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_EVT Events management\n * \\brief           Event helper functions\n * \\{\n */\n\nlwespr_t lwesp_evt_register(lwesp_evt_fn fn);\nlwespr_t lwesp_evt_unregister(lwesp_evt_fn fn);\nlwesp_evt_type_t lwesp_evt_get_type(lwesp_evt_t* cc);\n\n/**\n * \\anchor          LWESP_EVT_RESET_DETECTED\n * \\name            Reset detected\n * \\brief           Event helper functions for \\ref LWESP_EVT_RESET_DETECTED event\n * \\{\n */\n\nuint8_t lwesp_evt_reset_detected_is_forced(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_RESET\n * \\name            Reset event\n * \\brief           Event helper functions for \\ref LWESP_EVT_RESET event\n * \\{\n */\n\nlwespr_t lwesp_evt_reset_get_result(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_RESTORE\n * \\name            Restore event\n * \\brief           Event helper functions for \\ref LWESP_EVT_RESTORE event\n * \\{\n */\n\nlwespr_t lwesp_evt_restore_get_result(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_AP_IP_STA\n * \\name            Access point or station IP or MAC\n * \\brief           Event helper functions for \\ref LWESP_EVT_AP_IP_STA event\n * \\{\n */\n\nlwesp_mac_t* lwesp_evt_ap_ip_sta_get_mac(lwesp_evt_t* cc);\nlwesp_ip_t* lwesp_evt_ap_ip_sta_get_ip(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_AP_CONNECTED_STA\n * \\name            Connected station to access point\n * \\brief           Event helper functions for \\ref LWESP_EVT_AP_CONNECTED_STA event\n * \\{\n */\n\nlwesp_mac_t* lwesp_evt_ap_connected_sta_get_mac(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_AP_DISCONNECTED_STA\n * \\name            Disconnected station from access point\n * \\brief           Event helper functions for \\ref LWESP_EVT_AP_DISCONNECTED_STA event\n * \\{\n */\n\nlwesp_mac_t* lwesp_evt_ap_disconnected_sta_get_mac(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_CONN_RECV\n * \\name            Connection data received\n * \\brief           Event helper functions for \\ref LWESP_EVT_CONN_RECV event\n * \\{\n */\n\nlwesp_pbuf_p lwesp_evt_conn_recv_get_buff(lwesp_evt_t* cc);\nlwesp_conn_p lwesp_evt_conn_recv_get_conn(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_CONN_SEND\n * \\name            Connection data send\n * \\brief           Event helper functions for \\ref LWESP_EVT_CONN_SEND event\n * \\{\n */\n\nlwesp_conn_p lwesp_evt_conn_send_get_conn(lwesp_evt_t* cc);\nsize_t lwesp_evt_conn_send_get_length(lwesp_evt_t* cc);\nlwespr_t lwesp_evt_conn_send_get_result(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_CONN_ACTIVE\n * \\name            Connection active\n * \\brief           Event helper functions for \\ref LWESP_EVT_CONN_ACTIVE event\n * \\{\n */\n\nlwesp_conn_p lwesp_evt_conn_active_get_conn(lwesp_evt_t* cc);\nuint8_t lwesp_evt_conn_active_is_client(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_CONN_CLOSE\n * \\name            Connection close event\n * \\brief           Event helper functions for \\ref LWESP_EVT_CONN_CLOSE event\n * \\{\n */\n\nlwesp_conn_p lwesp_evt_conn_close_get_conn(lwesp_evt_t* cc);\nuint8_t lwesp_evt_conn_close_is_client(lwesp_evt_t* cc);\nuint8_t lwesp_evt_conn_close_is_forced(lwesp_evt_t* cc);\nlwespr_t lwesp_evt_conn_close_get_result(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_CONN_POLL\n * \\name            Connection poll\n * \\brief           Event helper functions for \\ref LWESP_EVT_CONN_POLL event\n * \\{\n */\n\nlwesp_conn_p lwesp_evt_conn_poll_get_conn(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_CONN_ERROR\n * \\name            Connection error\n * \\brief           Event helper functions for \\ref LWESP_EVT_CONN_ERROR event\n * \\{\n */\n\nlwespr_t lwesp_evt_conn_error_get_error(lwesp_evt_t* cc);\nlwesp_conn_type_t lwesp_evt_conn_error_get_type(lwesp_evt_t* cc);\nconst char* lwesp_evt_conn_error_get_host(lwesp_evt_t* cc);\nlwesp_port_t lwesp_evt_conn_error_get_port(lwesp_evt_t* cc);\nvoid* lwesp_evt_conn_error_get_arg(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_STA_LIST_AP\n * \\name            List access points\n * \\brief           Event helper functions for \\ref LWESP_EVT_STA_LIST_AP event\n * \\{\n */\n\nlwespr_t lwesp_evt_sta_list_ap_get_result(lwesp_evt_t* cc);\nlwesp_ap_t* lwesp_evt_sta_list_ap_get_aps(lwesp_evt_t* cc);\nsize_t lwesp_evt_sta_list_ap_get_length(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_STA_JOIN_AP\n * \\name            Join access point\n * \\brief           Event helper functions for \\ref LWESP_EVT_STA_JOIN_AP event\n * \\{\n */\n\nlwespr_t lwesp_evt_sta_join_ap_get_result(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_STA_INFO_AP\n * \\name            Get access point info\n * \\brief           Event helper functions for \\ref LWESP_EVT_STA_INFO_AP event\n * \\{\n */\n\nlwespr_t lwesp_evt_sta_info_ap_get_result(lwesp_evt_t* cc);\nconst char* lwesp_evt_sta_info_ap_get_ssid(lwesp_evt_t* cc);\nlwesp_mac_t lwesp_evt_sta_info_ap_get_mac(lwesp_evt_t* cc);\nuint8_t lwesp_evt_sta_info_ap_get_channel(lwesp_evt_t* cc);\nint16_t lwesp_evt_sta_info_ap_get_rssi(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_DNS_HOSTBYNAME\n * \\name            Get host address by name\n * \\brief           Event helper functions for \\ref LWESP_EVT_DNS_HOSTBYNAME event\n * \\{\n */\n\nlwespr_t lwesp_evt_dns_hostbyname_get_result(lwesp_evt_t* cc);\nconst char* lwesp_evt_dns_hostbyname_get_host(lwesp_evt_t* cc);\nlwesp_ip_t* lwesp_evt_dns_hostbyname_get_ip(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_PING\n * \\name            Ping\n * \\brief           Event helper functions for \\ref LWESP_EVT_PING event\n * \\{\n */\n\nlwespr_t lwesp_evt_ping_get_result(lwesp_evt_t* cc);\nconst char* lwesp_evt_ping_get_host(lwesp_evt_t* cc);\nuint32_t lwesp_evt_ping_get_time(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_SNTP_TIME\n * \\name            Simple Network Time Protocol\n * \\brief           Event helper functions for \\ref LWESP_EVT_SNTP_TIME event\n * \\{\n */\n\nlwespr_t lwesp_evt_sntp_time_get_result(lwesp_evt_t* cc);\nconst struct tm* lwesp_evt_sntp_time_get_datetime(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_WEBSERVER\n * \\name            Web Server\n * \\brief           Event helper functions for \\ref LWESP_EVT_WEBSERVER event\n * \\{\n */\n\nuint8_t lwesp_evt_webserver_get_status(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_EVT_SERVER\n * \\name            Server\n * \\brief           Event helper functions for \\ref LWESP_EVT_SERVER\n * \\{\n */\n\nlwespr_t lwesp_evt_server_get_result(lwesp_evt_t* cc);\nlwesp_port_t lwesp_evt_server_get_port(lwesp_evt_t* cc);\nuint8_t lwesp_evt_server_is_enable(lwesp_evt_t* cc);\n\n/**\n * \\}\n */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_EVT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_flash.h",
    "content": "/**\n * \\file            lwesp_flash.h\n * \\brief           System flash API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_FLASH_HDR_H\n#define LWESP_FLASH_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_FLASH System flash API\n * \\brief           System flash API\n * \\{\n */\n\nlwespr_t lwesp_flash_erase(lwesp_flash_partition_t partition, uint32_t offset, uint32_t length,\n                           const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_flash_write(lwesp_flash_partition_t partition, uint32_t offset, const void* data, uint32_t length,\n                           const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\n\nlwespr_t lwesp_mfg_erase(lwesp_mfg_namespace_t mfgns, const char* key, uint32_t offset, uint32_t length,\n                         const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_mfg_write(lwesp_mfg_namespace_t mfgns, const char* key, lwesp_mfg_valtype_t valtype, const void* data,\n                         uint32_t length, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                         const uint32_t blocking);\nlwespr_t lwesp_mfg_read(lwesp_mfg_namespace_t mfgns, const char* key, void* data, uint32_t btr, uint32_t offset,\n                        uint32_t* br, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_FLASH_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_flash_partitions.h",
    "content": "/**\n * \\file            lwesp_flash_partitions.h\n * \\brief           List of flash partitions\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n\n/*\n * Define LWESP_FLASH_PARTITION and LWESP_MFG_NAMESPACE before you include the file\n *\n * #define LWESP_FLASH_PARTITION(enum_type, at_string)\n * #define LWESP_MFG_NAMESPACE(enum_type, at_string)\n */\n\n/* Factory related device partitions */\nLWESP_FLASH_PARTITION(MFG_NVS, \"mfg_nvs\")\nLWESP_FLASH_PARTITION(FATFS, \"fatfs\")\n\n/* Default user non-volatile storage sections, part of mfg_nvs */\nLWESP_MFG_NAMESPACE(SERVER_CERT, \"server_cert\")\nLWESP_MFG_NAMESPACE(SERVER_KEY, \"server_key\")\nLWESP_MFG_NAMESPACE(SERVER_CA, \"server_ca\")\nLWESP_MFG_NAMESPACE(CLIENT_CERT, \"client_cert\")\nLWESP_MFG_NAMESPACE(CLIENT_KEY, \"client_key\")\nLWESP_MFG_NAMESPACE(CLIENT_CA, \"client_ca\")\nLWESP_MFG_NAMESPACE(MQTT_CERT, \"mqtt_cert\")\nLWESP_MFG_NAMESPACE(MQTT_KEY, \"mqtt_key\")\nLWESP_MFG_NAMESPACE(MQTT_CA, \"mqtt_ca\")\nLWESP_MFG_NAMESPACE(BLE_DATA, \"ble_data\")\nLWESP_MFG_NAMESPACE(FACTORY_PARAM, \"factory_param\")\n\n#undef LWESP_FLASH_PARTITION\n#undef LWESP_MFG_NAMESPACE"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_hostname.h",
    "content": "/**\n * \\file            lwesp_hostname.h\n * \\brief           Hostname API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_HOSTNAME_HDR_H\n#define LWESP_HOSTNAME_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_HOSTNAME Hostname API\n * \\brief           Hostname API\n * \\{\n */\n\nlwespr_t lwesp_hostname_set(const char* hostname, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                            const uint32_t blocking);\nlwespr_t lwesp_hostname_get(char* hostname, size_t size, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                            const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_HOSTNAME_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_includes.h",
    "content": "/**\n * \\file            lwesp_includes.h\n * \\brief           All main includes\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_INCLUDES_HDR_H\n#define LWESP_INCLUDES_HDR_H\n\n#include \"lwesp/lwesp_opt.h\"\n#include \"lwesp/lwesp_types.h\"\n\n#include \"lwesp/lwesp_buff.h\"\n#include \"lwesp/lwesp_conn.h\"\n#include \"lwesp/lwesp_debug.h\"\n#include \"lwesp/lwesp_evt.h\"\n#include \"lwesp/lwesp_flash.h\"\n#include \"lwesp/lwesp_input.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"lwesp/lwesp_pbuf.h\"\n#include \"lwesp/lwesp_server.h\"\n#include \"lwesp/lwesp_utils.h\"\n#include \"system/lwesp_sys.h\"\n\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n#include \"lwesp/lwesp_sta.h\"\n#endif /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n#include \"lwesp/lwesp_ap.h\"\n#endif /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n#if LWESP_CFG_NETCONN || __DOXYGEN__\n#include \"lwesp/lwesp_netconn.h\"\n#endif /* LWESP_CFG_NETCONN || __DOXYGEN__ */\n#if LWESP_CFG_PING || __DOXYGEN__\n#include \"lwesp/lwesp_ping.h\"\n#endif /* LWESP_CFG_PING || __DOXYGEN__ */\n#if LWESP_CFG_WPS || __DOXYGEN__\n#include \"lwesp/lwesp_wps.h\"\n#endif /* LWESP_CFG_WPS || __DOXYGEN__ */\n#if LWESP_CFG_SNTP || __DOXYGEN__\n#include \"lwesp/lwesp_sntp.h\"\n#endif /* LWESP_CFG_SNTP || __DOXYGEN__ */\n#if LWESP_CFG_HOSTNAME || __DOXYGEN__\n#include \"lwesp/lwesp_hostname.h\"\n#endif /* LWESP_CFG_HOSTNAME || __DOXYGEN__ */\n#if LWESP_CFG_DNS || __DOXYGEN__\n#include \"lwesp/lwesp_dns.h\"\n#endif /* LWESP_CFG_DNS || __DOXYGEN__ */\n#if LWESP_CFG_SMART || __DOXYGEN__\n#include \"lwesp/lwesp_smart.h\"\n#endif /* LWESP_CFG_SMART || __DOXYGEN__ */\n#if LWESP_CFG_BLE || __DOXYGEN__\n#include \"lwesp/lwesp_ble.h\"\n#endif /* LWESP_CFG_BLE || __DOXYGEN__ */\n#if LWESP_CFG_BT || __DOXYGEN__\n#include \"lwesp/lwesp_bt.h\"\n#endif /* LWESP_CFG_BT || __DOXYGEN__ */\n#include \"lwesp/lwesp_dhcp.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_INCLUDES_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_input.h",
    "content": "/**\n * \\file            lwesp_input.h\n * \\brief           Initialization process\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_INPUT_HDR_H\n#define LWESP_INPUT_HDR_H\n\n#include <string.h>\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_INPUT Input processing\n * \\brief           Input function for received data\n * \\{\n */\n\nlwespr_t lwesp_input(const void* data, size_t len);\nlwespr_t lwesp_input_process(const void* data, size_t len);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_INPUT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_int.h",
    "content": "/**\n * \\file            lwesp_int.h\n * \\brief           Internal functions\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_INT_HDR_H\n#define LWESP_INT_HDR_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_INT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_mdns.h",
    "content": "/**\n * \\file            lwesp_mdns.h\n * \\brief           mDNS API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_MDNS_HDR_H\n#define LWESP_MDNS_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_MDNS mDNS API\n * \\brief           mDNS function\n * \\{\n */\n\nlwespr_t lwesp_mdns_set_config(uint8_t en, const char* host, const char* server, lwesp_port_t port,\n                               const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_MDNS_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_mem.h",
    "content": "/**\n * \\file            lwesp_mem.h\n * \\brief           Memory manager\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_MEM_HDR_H\n#define LWESP_MEM_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_MEM Memory manager\n * \\brief           Dynamic memory manager\n * \\{\n */\n\n#if !LWESP_CFG_MEM_CUSTOM || __DOXYGEN__\n\n/**\n * \\brief           Single memory region descriptor\n */\ntypedef struct {\n    void* start_addr; /*!< Start address of region */\n    size_t size;      /*!< Size in units of bytes of region */\n} lwesp_mem_region_t;\n\nuint8_t lwesp_mem_assignmemory(const lwesp_mem_region_t* regions, size_t size);\n\n#endif /* !LWESP_CFG_MEM_CUSTOM || __DOXYGEN__ */\n\nvoid* lwesp_mem_malloc(size_t size);\nvoid* lwesp_mem_realloc(void* ptr, size_t size);\nvoid* lwesp_mem_calloc(size_t num, size_t size);\nvoid lwesp_mem_free(void* ptr);\nuint8_t lwesp_mem_free_s(void** ptr);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_MEM_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_netconn.h",
    "content": "/**\n * \\file            lwesp_netconn.h\n * \\brief           API functions for sequential calls\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_NETCONN_HDR_H\n#define LWESP_NETCONN_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP_API\n * \\defgroup        LWESP_NETCONN Network connection\n * \\brief           Network connection\n * \\{\n */\n\nstruct lwesp_netconn;\n\n/**\n * \\brief           Netconn object structure\n */\ntypedef struct lwesp_netconn* lwesp_netconn_p;\n\n/**\n * \\brief           Receive data with no timeout\n * \\note            Used with \\ref lwesp_netconn_set_receive_timeout function\n */\n#define LWESP_NETCONN_RECEIVE_NO_WAIT 0xFFFFFFFF\n\n/* Immediate flush for TCP write. Used with \\ref lwesp_netconn_write_ex*/\n#define LWESP_NETCONN_FLAG_FLUSH      ((uint16_t)0x0001) /*!< Immediate flush after netconn write */\n\n/**\n * \\brief           Netconn connection type\n */\ntypedef enum {\n    LWESP_NETCONN_TYPE_TCP = LWESP_CONN_TYPE_TCP,     /*!< TCP connection */\n    LWESP_NETCONN_TYPE_SSL = LWESP_CONN_TYPE_SSL,     /*!< SSL connection */\n    LWESP_NETCONN_TYPE_UDP = LWESP_CONN_TYPE_UDP,     /*!< UDP connection */\n#if LWESP_CFG_IPV6 || __DOXYGEN__\n    LWESP_NETCONN_TYPE_TCPV6 = LWESP_CONN_TYPE_TCPV6, /*!< TCP connection over IPv6 */\n    LWESP_NETCONN_TYPE_SSLV6 = LWESP_CONN_TYPE_SSLV6, /*!< SSL connection over IPv6 */\n    LWESP_NETCONN_TYPE_UDPV6 = LWESP_CONN_TYPE_UDPV6, /*!< UDP connection over IPv6 */\n#endif                                                /* LWESP_CFG_IPV6 || __DOXYGEN__ */\n} lwesp_netconn_type_t;\n\nlwesp_netconn_p lwesp_netconn_new(lwesp_netconn_type_t type);\nlwespr_t lwesp_netconn_delete(lwesp_netconn_p nc);\nlwespr_t lwesp_netconn_bind(lwesp_netconn_p nc, lwesp_port_t port);\nlwespr_t lwesp_netconn_connect(lwesp_netconn_p nc, const char* host, lwesp_port_t port);\nlwespr_t lwesp_netconn_receive(lwesp_netconn_p nc, lwesp_pbuf_p* pbuf);\nlwespr_t lwesp_netconn_close(lwesp_netconn_p nc);\nint8_t lwesp_netconn_get_connnum(lwesp_netconn_p nc);\nlwesp_conn_p lwesp_netconn_get_conn(lwesp_netconn_p nc);\nlwesp_netconn_type_t lwesp_netconn_get_type(lwesp_netconn_p nc);\nvoid lwesp_netconn_set_receive_timeout(lwesp_netconn_p nc, uint32_t timeout);\nuint32_t lwesp_netconn_get_receive_timeout(lwesp_netconn_p nc);\n\nlwespr_t lwesp_netconn_connect_ex(lwesp_netconn_p nc, const char* host, lwesp_port_t port, uint16_t keep_alive,\n                                  const char* local_ip, lwesp_port_t local_port, uint8_t mode);\n\n/* TCP only */\nlwespr_t lwesp_netconn_listen(lwesp_netconn_p nc);\nlwespr_t lwesp_netconn_listen_with_max_conn(lwesp_netconn_p nc, uint16_t max_connections);\nlwespr_t lwesp_netconn_set_listen_conn_timeout(lwesp_netconn_p nc, uint16_t timeout);\nlwespr_t lwesp_netconn_accept(lwesp_netconn_p nc, lwesp_netconn_p* client);\nlwespr_t lwesp_netconn_write(lwesp_netconn_p nc, const void* data, size_t btw);\nlwespr_t lwesp_netconn_write_ex(lwesp_netconn_p nc, const void* data, size_t btw, uint16_t flags);\nlwespr_t lwesp_netconn_flush(lwesp_netconn_p nc);\n\n/* UDP only */\nlwespr_t lwesp_netconn_send(lwesp_netconn_p nc, const void* data, size_t btw);\nlwespr_t lwesp_netconn_sendto(lwesp_netconn_p nc, const lwesp_ip_t* ip, lwesp_port_t port, const void* data,\n                              size_t btw);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_NETCONN_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_opt.h",
    "content": "/**\n * \\file            lwesp_opt.h\n * \\brief           ESP-AT options\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_DEFAULT_CONFIG_HDR_H\n#define LWESP_DEFAULT_CONFIG_HDR_H\n\n/* Uncomment to ignore user options (or set macro in compiler flags) */\n/* #define LWESP_IGNORE_USER_OPTS */\n\n/* Include application options */\n#include \"lwesp_debug_types.h\"\n#ifndef LWESP_IGNORE_USER_OPTS\n#include \"lwesp_opts.h\"\n#endif /* LWESP_IGNORE_USER_OPTS */\n\n/**\n * \\defgroup        LWESP_OPT Configuration\n * \\brief           ESP-AT options\n * \\{\n *\n */\n\n/**\n * \\brief           Enables `1` or disables `0` support for ESP8266 AT commands\n *\n */\n#ifndef LWESP_CFG_ESP8266\n#define LWESP_CFG_ESP8266 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for ESP32 AT commands\n *\n */\n#ifndef LWESP_CFG_ESP32\n#define LWESP_CFG_ESP32 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for ESP32-C2 AT commands\n *\n */\n#ifndef LWESP_CFG_ESP32_C2\n#define LWESP_CFG_ESP32_C2 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for ESP32-C3 AT commands\n *\n */\n#ifndef LWESP_CFG_ESP32_C3\n#define LWESP_CFG_ESP32_C3 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for ESP32-C6 AT commands\n *\n */\n#ifndef LWESP_CFG_ESP32_C6\n#define LWESP_CFG_ESP32_C6 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` operating system support for ESP library\n *\n * \\note            Value must be set to `1` in the current revision\n *\n * \\note            Check \\ref LWESP_OPT_OS group for more configuration related to operating system\n *\n */\n#ifndef LWESP_CFG_OS\n#define LWESP_CFG_OS 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` custom memory management functions\n *\n * When set to `1`, \\ref LWESP_MEM block must be provided manually.\n * This includes implementation of functions \\ref lwesp_mem_malloc,\n * \\ref lwesp_mem_calloc, \\ref lwesp_mem_realloc and \\ref lwesp_mem_free\n *\n * \\note            Function declaration follows standard C functions `malloc, calloc, realloc, free`.\n *                  Declaration is available in `lwesp/lwesp_mem.h` file. Include this file to final\n *                  implementation file\n *\n * \\note            When implementing custom memory allocation, it is necessary\n *                  to take care of multiple threads accessing same resource for custom allocator\n */\n#ifndef LWESP_CFG_MEM_CUSTOM\n#define LWESP_CFG_MEM_CUSTOM 0\n#endif\n\n/**\n * \\brief           Memory alignment for dynamic memory allocations\n *\n * \\note            Some CPUs can work faster if memory is aligned, usually to `4` or `8` bytes.\n *                  To speed up this possibilities, you can set memory alignment and library\n *                  will try to allocate memory on aligned boundaries.\n *\n * \\note            Some CPUs such ARM Cortex-M0 dont't support unaligned memory access.\n *\n * \\note            This value must be power of `2`\n */\n#ifndef LWESP_CFG_MEM_ALIGNMENT\n#define LWESP_CFG_MEM_ALIGNMENT 4\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` callback function and custom parameter for API functions\n *\n * When enabled, `2` additional parameters are available in API functions.\n * When command is executed, callback function with its parameter could be called when not set to `NULL`.\n */\n#ifndef LWESP_CFG_USE_API_FUNC_EVT\n#define LWESP_CFG_USE_API_FUNC_EVT 1\n#endif\n\n/**\n * \\brief           Set number of retries for send data command.\n *\n * Sometimes it may happen that `AT+SEND` command fails due to different problems.\n * Trying to send the same data multiple times can raise chances for success.\n */\n#ifndef LWESP_CFG_MAX_SEND_RETRIES\n#define LWESP_CFG_MAX_SEND_RETRIES 3\n#endif\n\n/**\n * \\brief           Default baudrate used for AT port\n *\n * \\note            User may call API function to change to desired baudrate if necessary\n */\n#ifndef LWESP_CFG_AT_PORT_BAUDRATE\n#define LWESP_CFG_AT_PORT_BAUDRATE 115200\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` ESP acting as station\n *\n * \\note            When device is in station mode, it can connect to other access points\n */\n#ifndef LWESP_CFG_MODE_STATION\n#define LWESP_CFG_MODE_STATION 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` ESP acting as access point\n *\n * \\note            When device is in access point mode, it can accept connections from other stations\n */\n#ifndef LWESP_CFG_MODE_ACCESS_POINT\n#define LWESP_CFG_MODE_ACCESS_POINT 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` full data info in \\ref lwesp_ap_t structure.\n *\n * When enabled, advanced information is stored, and as a consequence, structure size is increased.\n * Information such as scan type, min scan time, max scan time, frequency offset, frequency calibration are added\n */\n#ifndef LWESP_CFG_ACCESS_POINT_STRUCT_FULL_FIELDS\n#define LWESP_CFG_ACCESS_POINT_STRUCT_FULL_FIELDS 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` periodic keep-alive events to registered callbacks\n *\n */\n#ifndef LWESP_CFG_KEEP_ALIVE\n#define LWESP_CFG_KEEP_ALIVE 1\n#endif\n\n/**\n * \\brief           Timeout periodic time to trigger keep alive events to registered callbacks\n *\n * Feature must be enabled with \\ref LWESP_CFG_KEEP_ALIVE\n */\n#ifndef LWESP_CFG_KEEP_ALIVE_TIMEOUT\n#define LWESP_CFG_KEEP_ALIVE_TIMEOUT 1000\n#endif\n\n/**\n * \\defgroup        LWESP_OPT_CONN Connection settings\n * \\brief           Connection settings\n * \\{\n */\n\n/**\n * \\brief           Enables `1` or disables `0` support for IPv6\n *\n */\n#ifndef LWESP_CFG_IPV6\n#define LWESP_CFG_IPV6 0\n#endif\n\n/**\n * \\brief           Maximum single buffer size for network receive data on active connection\n *\n * \\note            When ESP sends buffer bigger than maximal, multiple buffers are created.\n *                  Exception is UDP connection type, which can be controlled,\n *                  with option \\ref LWESP_CFG_CONN_ALLOW_FRAGMENTED_UDP_SEND\n */\n#ifndef LWESP_CFG_CONN_MAX_RECV_BUFF_SIZE\n#define LWESP_CFG_CONN_MAX_RECV_BUFF_SIZE 1460\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for fragmented send of UDP packets.\n *\n * When connection type is UDP and packet length longer than maximal transmission unit,\n * it can be split into multiple packets and sent over the network.\n *\n * When this feature is disabled, max length of UDP packet is defined with\n * \\ref LWESP_CFG_CONN_MAX_DATA_LEN option\n */\n#ifndef LWESP_CFG_CONN_ALLOW_FRAGMENTED_UDP_SEND\n#define LWESP_CFG_CONN_ALLOW_FRAGMENTED_UDP_SEND 0\n#endif\n\n/**\n * \\brief           Maximal number of connections AT software can support on ESP device\n *\n * \\note            In case of official ESP-AT software, leave this on default value (`5`)\n */\n#ifndef LWESP_CFG_MAX_CONNS\n#define LWESP_CFG_MAX_CONNS 5\n#endif\n\n/**\n * \\brief           Maximal number of bytes we can send at single command to ESP\n * \\note            Value can not exceed `2048` bytes or no data will be send at all (ESP8266 AT SW limitation)\n *\n * When manual TCP read mode is enabled, this parameter defines number of bytes to be read at a time\n *\n * \\note            This is limitation of ESP AT commands and on systems where RAM\n *                  is not an issue, it should be set to maximal value (`2048`)\n *                  to optimize data transfer speed performance\n */\n#ifndef LWESP_CFG_CONN_MAX_DATA_LEN\n#define LWESP_CFG_CONN_MAX_DATA_LEN 2048\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` manual `TCP` data receive from ESP device\n *\n * Normally ESP automatically sends received TCP data to host device\n * in async mode. When host device is slow or if there is memory constrain,\n * it may happen that processing cannot handle all received data.\n *\n * When feature is enabled, ESP will notify host device about new data\n * available for read and then user may start read process\n *\n * \\note            This feature is only available for `TCP/SSL` connections.\n */\n#ifndef LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n#define LWESP_CFG_CONN_MANUAL_TCP_RECEIVE 1\n#endif\n\n/**\n * \\brief           Minimal buffer in bytes for connection receive allocation.\n * \n *                  Allocation will always start with (up to) \\ref LWESP_CFG_CONN_MAX_DATA_LEN\n *                  and will continue with trial down to this setting up until allocating is successful.\n * \n * \\note            This feature is used together with \\ref LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n */\n#ifndef LWESP_CFG_CONN_MIN_DATA_LEN\n#define LWESP_CFG_CONN_MIN_DATA_LEN 16\n#endif\n\n/**\n * \\brief           Poll interval for connections in units of milliseconds\n *\n * Value indicates interval time to call poll event on active connections.\n *\n * \\note            Single poll interval applies for all connections\n */\n#ifndef LWESP_CFG_CONN_POLL_INTERVAL\n#define LWESP_CFG_CONN_POLL_INTERVAL 500\n#endif\n\n/**\n * \\brief           Enables (`1`) or disabled (`1`) option to start connection event\n *                  if station does not have valid IP address (is not connected to another access point)\n * \n * When enabled, starting a connection as a client can be successful even, if ESP-AT station isn't connected to another access point.\n * This feature is only used if ESP is in access point mode and another station connects to it.\n *  \n * \\note            Value is set to `0` to keep backward compatibility.\n * \n */\n#ifndef LWESP_CFG_CONN_ALLOW_START_STATION_NO_IP\n#define LWESP_CFG_CONN_ALLOW_START_STATION_NO_IP 0\n#endif\n\n/**\n * \\}\n */\n\n/**\n * \\brief           Buffer size for received data waiting to be processed\n * \\note            When server mode is active and a lot of connections are in queue\n *                  this should be set high otherwise your buffer may overflow\n *\n * \\note            Buffer size also depends on TX user driver if it uses DMA or blocking mode.\n *                  In case of DMA (CPU can work other tasks), buffer may be smaller as CPU\n *                  will have more time to process all the incoming bytes\n *\n * \\note            This parameter has no meaning when \\ref LWESP_CFG_INPUT_USE_PROCESS is enabled\n */\n#ifndef LWESP_CFG_RCV_BUFF_SIZE\n#define LWESP_CFG_RCV_BUFF_SIZE 0x400\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` reset sequence after \\ref lwesp_init call\n *\n * \\note            When this functionality is disabled, user must manually call \\ref lwesp_reset to send\n *                  reset sequence to ESP device.\n */\n#ifndef LWESP_CFG_RESET_ON_INIT\n#define LWESP_CFG_RESET_ON_INIT 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` device restore after \\ref lwesp_init call\n *\n * \\note            When this feature is enabled, it will automatically\n *                  restore and clear any settings stored as \\em default in ESP device\n */\n#ifndef LWESP_CFG_RESTORE_ON_INIT\n#define LWESP_CFG_RESTORE_ON_INIT 1\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` reset sequence after \\ref lwesp_device_set_present call\n *\n * \\note            When this functionality is disabled, user must manually call \\ref lwesp_reset to send\n *                  reset sequence to ESP device.\n */\n#ifndef LWESP_CFG_RESET_ON_DEVICE_PRESENT\n#define LWESP_CFG_RESET_ON_DEVICE_PRESENT 1\n#endif\n\n/**\n * \\brief           Default delay (milliseconds unit) before sending first AT command on reset sequence\n *\n */\n#ifndef LWESP_CFG_RESET_DELAY_DEFAULT\n#define LWESP_CFG_RESET_DELAY_DEFAULT 1000\n#endif\n\n/**\n * \\brief           Maximum length of SSID for access point scan\n *\n * \\note            This parameter must include trailling zero\n */\n#ifndef LWESP_CFG_MAX_SSID_LENGTH\n#define LWESP_CFG_MAX_SSID_LENGTH 21\n#endif\n\n/**\n * \\brief           Maximum length of PWD for access point\n *\n * \\note            This parameter must include trailling zero\n */\n#ifndef LWESP_CFG_MAX_PWD_LENGTH\n#define LWESP_CFG_MAX_PWD_LENGTH 65\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` listing all available CMDs during reset/restore operation\n *\n */\n#ifndef LWESP_CFG_LIST_CMD\n#define LWESP_CFG_LIST_CMD 0\n#endif\n\n/**\n * \\defgroup        LWESP_OPT_DBG Debugging\n * \\brief           Debugging configurations\n * \\{\n */\n\n/**\n * \\brief           Set global debug support\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n *\n * \\note            Set to \\ref LWESP_DBG_OFF to globally disable all debugs\n */\n#ifndef LWESP_CFG_DBG\n#define LWESP_CFG_DBG LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Debugging output function\n *\n * Called with format and optional parameters for printf-like debug\n */\n#ifndef LWESP_CFG_DBG_OUT\n#define LWESP_CFG_DBG_OUT(fmt, ...)                                                                                    \\\n    do {                                                                                                               \\\n        extern int printf(const char* format, ...);                                                                    \\\n        printf(fmt, ##__VA_ARGS__);                                                                                    \\\n    } while (0)\n#endif\n\n/**\n * \\brief           Minimal debug level\n *\n * Check \\ref LWESP_DBG_LVL for possible values\n */\n#ifndef LWESP_CFG_DBG_LVL_MIN\n#define LWESP_CFG_DBG_LVL_MIN LWESP_DBG_LVL_ALL\n#endif\n\n/**\n * \\brief           Enabled debug types\n *\n * When debug is globally enabled with \\ref LWESP_CFG_DBG parameter,\n * user must enable debug types such as TRACE or STATE messages.\n *\n * Check \\ref LWESP_DBG_TYPE for possible options. Separate values with `bitwise OR` operator\n */\n#ifndef LWESP_CFG_DBG_TYPES_ON\n#define LWESP_CFG_DBG_TYPES_ON 0\n#endif\n\n/**\n * \\brief           Set debug level for init function\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_INIT\n#define LWESP_CFG_DBG_INIT LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for memory manager\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_MEM\n#define LWESP_CFG_DBG_MEM LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for input module\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_INPUT\n#define LWESP_CFG_DBG_INPUT LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for ESP threads\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_THREAD\n#define LWESP_CFG_DBG_THREAD LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for asserting of input variables\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_ASSERT\n#define LWESP_CFG_DBG_ASSERT LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for incoming data received from device\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_IPD\n#define LWESP_CFG_DBG_IPD LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for netconn sequential API\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_NETCONN\n#define LWESP_CFG_DBG_NETCONN LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for packet buffer manager\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_PBUF\n#define LWESP_CFG_DBG_PBUF LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for connections\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_CONN\n#define LWESP_CFG_DBG_CONN LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for dynamic variable allocations\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_VAR\n#define LWESP_CFG_DBG_VAR LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` echo mode on AT commands\n *                  sent to ESP device.\n *\n * \\note            This mode is useful when debugging ESP communication\n */\n#ifndef LWESP_CFG_AT_ECHO\n#define LWESP_CFG_AT_ECHO 0\n#endif\n\n/**\n * \\}\n */\n\n/**\n * \\defgroup        LWESP_OPT_OS OS configuration\n * \\brief           Operating system dependant configuration\n * \\{\n */\n\n/**\n * \\brief           Set number of message queue entries for procuder thread\n *\n * Message queue is used for storing memory address to command data\n */\n#ifndef LWESP_CFG_THREAD_PRODUCER_MBOX_SIZE\n#define LWESP_CFG_THREAD_PRODUCER_MBOX_SIZE 16\n#endif\n\n/**\n * \\brief           Set number of message queue entries for processing thread\n *\n * Message queue is used to notify processing thread about new received data on AT port\n */\n#ifndef LWESP_CFG_THREAD_PROCESS_MBOX_SIZE\n#define LWESP_CFG_THREAD_PROCESS_MBOX_SIZE 16\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` direct support for processing input data\n *\n * When this mode is enabled, no overhead is included for copying data\n * to receive buffer because bytes are processed directly by \\ref lwesp_input_process function\n *\n * If this mode is not enabled, then user have to send every received byte via \\ref lwesp_input\n * function to the internal buffer for future processing. This may introduce additional overhead\n * with data copy and may decrease library performance\n *\n * \\note            This mode can only be used when \\ref LWESP_CFG_OS is enabled\n *\n * \\note            When using this mode, separate thread must be dedicated only\n *                  for reading data on AT port. It is usually implemented in LL driver\n *\n * \\note            Best case for using this mode is if DMA receive is supported by host device\n */\n#ifndef LWESP_CFG_INPUT_USE_PROCESS\n#define LWESP_CFG_INPUT_USE_PROCESS 0\n#endif\n\n/**\n * \\brief           Producer thread hook, called each time thread wakes-up and does the processing.\n *\n * It can be used to check if thread is alive.\n */\n#ifndef LWESP_THREAD_PRODUCER_HOOK\n#define LWESP_THREAD_PRODUCER_HOOK()\n#endif\n\n/**\n * \\brief           Process thread hook, called each time thread wakes-up and does the processing.\n *\n * It can be used to check if thread is alive.\n */\n#ifndef LWESP_THREAD_PROCESS_HOOK\n#define LWESP_THREAD_PROCESS_HOOK()\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` custom memory byte pool extension for ThreadX port\n *\n * When enabled, user must manually set byte pool at run-time, before \\ref lwesp_init is called\n */\n#ifndef LWESP_CFG_THREADX_CUSTOM_MEM_BYTE_POOL\n#define LWESP_CFG_THREADX_CUSTOM_MEM_BYTE_POOL 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` idle thread extensions feature of ThreadX\n *\n * When enabled, user must manually configure idle thread and setup additional thread handle extension fields.\n * By default ThreadX doesn't support self-thread cleanup when thread memory is dynamically allocated & thread terminated,\n * hence another thread is mandatory to do the cleanup process instead.\n *\n * This configuration does not create idle-thread, rather only sets additional TX_THREAD fields,\n * indicating thread handle and thread stack are dynamically allocated.\n *\n * Have a look at System-ThreadX port for implementation\n */\n#ifndef LWESP_CFG_THREADX_IDLE_THREAD_EXTENSION\n#define LWESP_CFG_THREADX_IDLE_THREAD_EXTENSION 0\n#endif\n\n/**\n * \\}\n */\n\n/**\n * \\defgroup        LWESP_OPT_MODULES Modules\n * \\brief           Configuration of specific modules\n * \\{\n */\n\n/**\n * \\defgroup        LWESP_OPT_MODULES_NETCONN Netconn module\n * \\brief           Configuration of netconn API module\n * \\{\n */\n\n/**\n * \\brief           Enables `1` or disables `0` NETCONN sequential API support for OS systems\n *\n * \\note            To use this feature, OS support is mandatory.\n * \\sa              LWESP_CFG_OS\n */\n#ifndef LWESP_CFG_NETCONN\n#define LWESP_CFG_NETCONN 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` receive timeout feature\n *\n * When this option is enabled, user will get an option\n * to set timeout value for receive data on netconn,\n * before function returns timeout error.\n *\n * \\note            Even if this option is enabled, user must still manually set timeout,\n *                  by default time will be set to 0 which means no timeout.\n */\n#ifndef LWESP_CFG_NETCONN_RECEIVE_TIMEOUT\n#define LWESP_CFG_NETCONN_RECEIVE_TIMEOUT 1\n#endif\n\n/**\n * \\brief           Accept queue length for new client when netconn server is used\n *\n * Defines number of maximal clients waiting in accept queue of server connection\n */\n#ifndef LWESP_CFG_NETCONN_ACCEPT_QUEUE_LEN\n#define LWESP_CFG_NETCONN_ACCEPT_QUEUE_LEN 5\n#endif\n\n/**\n * \\brief           Receive queue length for pbuf entries\n *\n * Defines maximal number of pbuf data packet references for receive\n */\n#ifndef LWESP_CFG_NETCONN_RECEIVE_QUEUE_LEN\n#define LWESP_CFG_NETCONN_RECEIVE_QUEUE_LEN 8\n#endif\n\n/**\n * \\}\n */\n\n/**\n * \\defgroup        LWESP_OPT_MODULES_MQTT MQTT client module\n * \\brief           Configuration of MQTT and MQTT API client modules\n * \\{\n */\n\n/**\n * \\brief           Maximal number of open MQTT requests at a time\n *\n */\n#ifndef LWESP_CFG_MQTT_MAX_REQUESTS\n#define LWESP_CFG_MQTT_MAX_REQUESTS 8\n#endif\n\n/**\n * \\brief           Size of MQTT API message queue for received messages\n *\n */\n#ifndef LWESP_CFG_MQTT_API_MBOX_SIZE\n#define LWESP_CFG_MQTT_API_MBOX_SIZE 8\n#endif\n\n/**\n * \\brief           Set debug level for MQTT client module\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_MQTT\n#define LWESP_CFG_DBG_MQTT LWESP_DBG_OFF\n#endif\n\n/**\n * \\brief           Set debug level for MQTT API client module\n *\n * Possible values are \\ref LWESP_DBG_ON or \\ref LWESP_DBG_OFF\n */\n#ifndef LWESP_CFG_DBG_MQTT_API\n#define LWESP_CFG_DBG_MQTT_API LWESP_DBG_OFF\n#endif\n\n/**\n * \\}\n */\n\n/**\n * \\brief           Enables `1` or disables `0` support for DNS functions\n *\n */\n#ifndef LWESP_CFG_DNS\n#define LWESP_CFG_DNS 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for WPS functions\n *\n */\n#ifndef LWESP_CFG_WPS\n#define LWESP_CFG_WPS 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for SNTP protocol with AT commands\n *\n */\n#ifndef LWESP_CFG_SNTP\n#define LWESP_CFG_SNTP 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` automatic time read from the device when time gets updated\n * \n * Latest version of ESP-AT, starting from `v3.0` supports, when enabled,\n * to receive `+TIME_UPDATED` notification, when ESP device got new time via SNTP protocol.\n * \n * When this option is enabled, command will be send to \n * the ESP device requesting new time for each new `TIME UPDATED` event.\n * \n * \\note            \\ref LWESP_CFG_SNTP shall be enabled and SNTP configured on ESP device\n */\n#ifndef LWESP_CFG_SNTP_AUTO_READ_TIME_ON_UPDATE\n#define LWESP_CFG_SNTP_AUTO_READ_TIME_ON_UPDATE 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for hostname with AT commands\n *\n */\n#ifndef LWESP_CFG_HOSTNAME\n#define LWESP_CFG_HOSTNAME 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for system flash with AT commands\n *\n */\n#ifndef LWESP_CFG_FLASH\n#define LWESP_CFG_FLASH 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for ping functions\n *\n */\n#ifndef LWESP_CFG_PING\n#define LWESP_CFG_PING 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for mDNS\n *\n */\n#ifndef LWESP_CFG_MDNS\n#define LWESP_CFG_MDNS 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for SMART config\n *\n */\n#ifndef LWESP_CFG_SMART\n#define LWESP_CFG_SMART 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for Web Server feature\n *\n */\n#ifndef LWESP_CFG_WEBSERVER\n#define LWESP_CFG_WEBSERVER 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for Bluetooth Low Energy\n * \n * \\note            This feature only works for some of Espressif devices,\n *                  that support AT BLE commands \n */\n#ifndef LWESP_CFG_BLE\n#define LWESP_CFG_BLE 0\n#endif\n\n/**\n * \\brief           Enables `1` or disables `0` support for Bluetooth Classic\n * \n * \\note            This feature only works for some of Espressif devices,\n *                  that support AT BT commands \n */\n#ifndef LWESP_CFG_BT\n#define LWESP_CFG_BT 0\n#endif\n\n/**\n * \\}\n */\n\n/**\n * \\defgroup        LWESP_OPT_BLE Bluetooth Low Energy\n * \\brief           Configuration of Bluetooth Low Energy\n * \\{\n */\n\n/**\n * \\}\n */\n\n/**\n * \\defgroup        LWESP_OPT_BT Bluetooth Classic\n * \\brief           Configuration of Bluetooth Classic\n * \\{\n */\n\n/**\n * \\}\n */\n\n/**\n * \\defgroup        LWESP_OPT_STD_LIB Standard library\n * \\brief           Standard C library configuration\n * \\{\n *\n * Configuration allows you to overwrite default C language function\n * in case of better implementation with hardware (for example DMA for data copy).\n */\n\n/**\n * \\brief           Memory copy function declaration\n *\n * User is able to change the memory function, in case\n * hardware supports copy operation, it may implement its own\n *\n * Function prototype must be similar to:\n *\n * \\code{c}\nvoid *  my_memcpy(void* dst, const void* src, size_t len);\n\\endcode\n *\n * \\param[in]       dst: Destination memory start address\n * \\param[in]       src: Source memory start address\n * \\param[in]       len: Number of bytes to copy\n * \\return          Destination memory start address\n */\n#ifndef LWESP_MEMCPY\n#define LWESP_MEMCPY(dst, src, len) memcpy(dst, src, len)\n#endif\n\n/**\n * \\brief           Memory set function declaration\n *\n * Function prototype must be similar to:\n *\n * \\code{c}\nvoid *  my_memset(void* dst, int b, size_t len);\n\\endcode\n *\n * \\param[in]       dst: Destination memory start address\n * \\param[in]       b: Value (byte) to set in memory\n * \\param[in]       len: Number of bytes to set\n * \\return          Destination memory start address\n */\n#ifndef LWESP_MEMSET\n#define LWESP_MEMSET(dst, b, len) memset(dst, b, len)\n#endif\n\n/**\n * \\}\n */\n\n/**\n * \\defgroup        LWESP_OPT_MIN_AT_VERSIONS Minimum AT versions\n * \\brief           Minimum AT versions needed for Espressif devices to run properly with LwESP\n * \\{\n */\n\n/* Define minimum versions required for each of device */\n/* Format is (major << 24 | minor << 16 | patch << 8)*/\n#define LWESP_MIN_AT_VERSION_ESP8266  (2 << 24 | 2 << 16 | 1 << 8)\n#define LWESP_MIN_AT_VERSION_ESP32    (3 << 24 | 2 << 16 | 0 << 8)\n#define LWESP_MIN_AT_VERSION_ESP32_C2 (3 << 24 | 2 << 16 | 0 << 8)\n#define LWESP_MIN_AT_VERSION_ESP32_C3 (3 << 24 | 2 << 16 | 0 << 8)\n#define LWESP_MIN_AT_VERSION_ESP32_C6 (3 << 24 | 2 << 16 | 0 << 8)\n\n/**\n * \\}\n */\n\n/**\n * \\}\n */\n\n#if !__DOXYGEN__\n\n/* Define group mode value */\n#define LWESP_CFG_MODE_STATION_ACCESS_POINT (LWESP_CFG_MODE_STATION && LWESP_CFG_MODE_ACCESS_POINT)\n\n/* At least one of them must be enabled */\n#if !LWESP_CFG_MODE_STATION && !LWESP_CFG_MODE_ACCESS_POINT\n#error                                                                                                                 \\\n    \"Invalid ESP configuration. LWESP_CFG_MODE_STATION and LWESP_CFG_MODE_ACCESS_POINT cannot be disabled at the same time!\"\n#endif\n\n/* Operating system config */\n#if !LWESP_CFG_OS\n#if LWESP_CFG_INPUT_USE_PROCESS\n#error \"LWESP_CFG_INPUT_USE_PROCESS may only be enabled when OS is used!\"\n#endif /* LWESP_CFG_INPUT_USE_PROCESS */\n#endif /* !LWESP_CFG_OS */\n\n/* Device config */\n#if !LWESP_CFG_ESP8266 && !LWESP_CFG_ESP32 && !LWESP_CFG_ESP32_C3\n#error \"At least one of LWESP_CFG_ESP8266 or LWESP_CFG_ESP32 or LWESP_CFG_ESP32_C3 must be set to 1!\"\n#endif /* !LWESP_CFG_ESP8266 && !LWESP_CFG_ESP32 */\n\n/* WPS config */\n#if LWESP_CFG_WPS && !LWESP_CFG_MODE_STATION\n#error \"WPS function may only be used when station mode is enabled!\"\n#endif /* LWESP_CFG_WPS && !LWESP_CFG_MODE_STATION */\n\n#endif /* !__DOXYGEN__ */\n\n#include \"lwesp/lwesp_debug.h\"\n\n#endif /* LWESP_DEFAULT_CONFIG_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_opts_template.h",
    "content": "/**\n * \\file            lwesp_opts_template.h\n * \\brief           Template config file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_OPTS_HDR_H\n#define LWESP_OPTS_HDR_H\n\n/* Rename this file to \"lwesp_opts.h\" for your application */\n\n/*\n * Open \"include/lwesp/lwesp_opt.h\" and\n * copy & replace here settings you want to change values\n */\n\n#endif /* LWESP_OPTS_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_parser.h",
    "content": "/**\n * \\file            lwesp_parser.h\n * \\brief           Parser of AT responses\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_PARSER_HDR_H\n#define LWESP_PARSER_HDR_H\n\n#include \"lwesp/lwesp_private.h\"\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nint32_t lwespi_parse_number(const char** str);\nuint32_t lwespi_parse_hexnumber(const char** str);\nuint8_t lwespi_parse_string(const char** src, char* dst, size_t dst_len, uint8_t trim);\nuint8_t lwespi_parse_ip(const char** src, lwesp_ip_t* ip);\nlwesp_port_t lwespi_parse_port(const char** str);\nuint8_t lwespi_parse_mac(const char** src, lwesp_mac_t* mac);\n\nlwespr_t lwespi_parse_cipstatus_cipstate(const char* str);\nlwesp_conn_p lwespi_parse_ipd(const char* str);\nlwespr_t lwespi_parse_ciprecvlen(const char* str);\n\nuint8_t lwespi_parse_cwlap(const char* str, lwesp_msg_t* msg);\nuint8_t lwespi_parse_cwjap(const char* str, lwesp_msg_t* msg);\nuint8_t lwespi_parse_cwlif(const char* str, lwesp_msg_t* msg);\nuint8_t lwespi_parse_cipdomain(const char* src, lwesp_msg_t* msg);\nuint8_t lwespi_parse_cipsntptime(const char* str, lwesp_msg_t* msg);\nuint8_t lwespi_parse_cipsntpintv(const char* str, lwesp_msg_t* msg);\nuint8_t lwespi_parse_sntp_cfg(const char* str, lwesp_msg_t* msg);\nuint8_t lwespi_parse_ping_time(const char* str, lwesp_msg_t* msg);\nuint8_t lwespi_parse_hostname(const char* str, lwesp_msg_t* msg);\nuint8_t lwespi_parse_link_conn(const char* str);\n\nuint8_t lwespi_parse_at_sdk_version(const char* str, lwesp_sw_version_t* version_out);\n\nuint8_t lwespi_parse_ap_conn_disconn_sta(const char* str, uint8_t is_conn);\nuint8_t lwespi_parse_ap_ip_sta(const char* str);\nuint8_t lwespi_parse_cwsap(const char* str, lwesp_msg_t* msg);\n\nuint8_t lwespi_parse_cwdhcp(const char* str);\n\nuint8_t lwespi_parse_webserver(const char* str);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_PARSER_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_pbuf.h",
    "content": "/**\n * \\file            lwesp_pbuf.h\n * \\brief           Packet buffer manager\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_PBUF_HDR_H\n#define LWESP_PBUF_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_PBUF Packet buffer\n * \\brief           Packet buffer manager\n * \\{\n */\n\nlwesp_pbuf_p lwesp_pbuf_new(size_t len);\nsize_t lwesp_pbuf_free(lwesp_pbuf_p pbuf);\nsize_t lwesp_pbuf_free_s(lwesp_pbuf_p* pbuf);\nvoid* lwesp_pbuf_data(const lwesp_pbuf_p pbuf);\nsize_t lwesp_pbuf_length(const lwesp_pbuf_p pbuf, uint8_t tot);\nuint8_t lwesp_pbuf_set_length(lwesp_pbuf_p pbuf, size_t new_len);\nlwespr_t lwesp_pbuf_take(lwesp_pbuf_p pbuf, const void* data, size_t len, size_t offset);\nsize_t lwesp_pbuf_copy(lwesp_pbuf_p pbuf, void* data, size_t len, size_t offset);\n\nlwespr_t lwesp_pbuf_cat(lwesp_pbuf_p head, const lwesp_pbuf_p tail);\nlwespr_t lwesp_pbuf_cat_s(lwesp_pbuf_p head, lwesp_pbuf_p* tail);\nlwespr_t lwesp_pbuf_chain(lwesp_pbuf_p head, lwesp_pbuf_p tail);\nlwesp_pbuf_p lwesp_pbuf_unchain(lwesp_pbuf_p head);\nlwespr_t lwesp_pbuf_ref(lwesp_pbuf_p pbuf);\n\nuint8_t lwesp_pbuf_get_at(const lwesp_pbuf_p pbuf, size_t pos, uint8_t* el);\nsize_t lwesp_pbuf_memcmp(const lwesp_pbuf_p pbuf, const void* data, size_t len, size_t offset);\nsize_t lwesp_pbuf_strcmp(const lwesp_pbuf_p pbuf, const char* str, size_t offset);\nsize_t lwesp_pbuf_memfind(const lwesp_pbuf_p pbuf, const void* data, size_t len, size_t off);\nsize_t lwesp_pbuf_strfind(const lwesp_pbuf_p pbuf, const char* str, size_t off);\n\nuint8_t lwesp_pbuf_advance(lwesp_pbuf_p pbuf, int len);\nlwesp_pbuf_p lwesp_pbuf_skip(lwesp_pbuf_p pbuf, size_t offset, size_t* new_offset);\n\nvoid* lwesp_pbuf_get_linear_addr(const lwesp_pbuf_p pbuf, size_t offset, size_t* new_len);\n\nvoid lwesp_pbuf_set_ip(lwesp_pbuf_p pbuf, const lwesp_ip_t* ip, lwesp_port_t port);\n\nvoid lwesp_pbuf_dump(lwesp_pbuf_p p, uint8_t seq);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_PBUF_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_ping.h",
    "content": "/**\n * \\file            lwesp_ping.h\n * \\brief           Ping API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_PING_HDR_H\n#define LWESP_PING_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_PING PING\n * \\brief           Ping server and get response time\n * \\{\n */\n\nlwespr_t lwesp_ping(const char* host, uint32_t* time, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                    const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_PING_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_private.h",
    "content": "/**\n * \\file            lwesp_private.h\n * \\brief           Private structures and enumerations\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_PRIV_HDR_H\n#define LWESP_PRIV_HDR_H\n\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_buff.h\"\n#include \"lwesp/lwesp_debug.h\"\n#include \"lwesp/lwesp_includes.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"lwesp/lwesp_opt.h\"\n#include \"lwesp/lwesp_timeout.h\"\n#include \"lwesp/lwesp_types.h\"\n#include \"lwesp/lwesp_utils.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\addtogroup      LWESP_TYPES\n * \\{\n */\n\n/**\n * \\brief           List of possible messages\n */\ntypedef enum {\n    LWESP_CMD_IDLE = 0, /*!< IDLE mode */\n\n    /* Basic AT commands */\n    LWESP_CMD_RESET,   /*!< Reset device */\n    LWESP_CMD_ATE0,    /*!< Disable ECHO mode on AT commands */\n    LWESP_CMD_ATE1,    /*!< Enable ECHO mode on AT commands */\n    LWESP_CMD_GMR,     /*!< Get AT commands version */\n    LWESP_CMD_CMD,     /*!< List support AT commands */\n    LWESP_CMD_GSLP,    /*!< Set ESP to sleep mode */\n    LWESP_CMD_RESTORE, /*!< Restore ESP internal settings to default values */\n    LWESP_CMD_UART,\n    LWESP_CMD_SLEEP,\n    LWESP_CMD_WAKEUPGPIO,\n    LWESP_CMD_RFPOWER,\n    LWESP_CMD_RFVDD,\n    LWESP_CMD_RFAUTOTRACE,\n    LWESP_CMD_SYSRAM,\n    LWESP_CMD_SYSADC,\n    LWESP_CMD_SYSMSG,\n    LWESP_CMD_SYSLOG,\n\n    /* Raw flash operations */\n    LWESP_CMD_SYSFLASH_WRITE, /*!< Write flash operation */\n    LWESP_CMD_SYSFLASH_READ,  /*!< Read flash operation */\n    LWESP_CMD_SYSFLASH_ERASE, /*!< Erase flash operation */\n    LWESP_CMD_SYSFLASH_GET,   /*!< Get flash partitions */\n\n    /* Manufacturing data */\n    LWESP_CMD_SYSMFG_WRITE, /*!< Write manufacturing NVS data */\n    LWESP_CMD_SYSMFG_READ,  /*!< Read manufacturing NVS data */\n    LWESP_CMD_SYSMFG_ERASE, /*!< Erase manufacturing NVS data */\n    LWESP_CMD_SYSMFG_GET,   /*!< Get manufacturing user partitions */\n\n    /* WiFi based commands */\n    LWESP_CMD_WIFI_CWMODE,         /*!< Set wifi mode */\n    LWESP_CMD_WIFI_CWMODE_GET,     /*!< Get wifi mode */\n    LWESP_CMD_WIFI_CWLAPOPT,       /*!< Configure what is visible on CWLAP response */\n    LWESP_CMD_WIFI_IPV6,           /*!< Configure IPv6 support */\n    LWESP_CMD_WIFI_CWJAP,          /*!< Connect to access point */\n    LWESP_CMD_WIFI_CWRECONNCFG,    /*!< Setup reconnect interval and maximum tries */\n    LWESP_CMD_WIFI_CWJAP_GET,      /*!< Info of the connected access point */\n    LWESP_CMD_WIFI_CWQAP,          /*!< Disconnect from access point */\n    LWESP_CMD_WIFI_CWLAP,          /*!< List available access points */\n    LWESP_CMD_WIFI_CIPSTAMAC_GET,  /*!< Get MAC address of ESP station */\n    LWESP_CMD_WIFI_CIPSTAMAC_SET,  /*!< Set MAC address of ESP station */\n    LWESP_CMD_WIFI_CIPSTA_GET,     /*!< Get IP address of ESP station */\n    LWESP_CMD_WIFI_CIPSTA_SET,     /*!< Set IP address of ESP station */\n    LWESP_CMD_WIFI_CWAUTOCONN,     /*!< Configure auto connection to access point */\n    LWESP_CMD_WIFI_CWDHCP_SET,     /*!< Set DHCP config */\n    LWESP_CMD_WIFI_CWDHCP_GET,     /*!< Get DHCP config */\n    LWESP_CMD_WIFI_CWDHCPS_SET,    /*!< Set DHCP SoftAP IP config */\n    LWESP_CMD_WIFI_CWDHCPS_GET,    /*!< Get DHCP SoftAP IP config */\n    LWESP_CMD_WIFI_CWSAP_GET,      /*!< Get software access point configuration */\n    LWESP_CMD_WIFI_CWSAP_SET,      /*!< Set software access point configuration */\n    LWESP_CMD_WIFI_CIPAPMAC_GET,   /*!< Get MAC address of ESP access point */\n    LWESP_CMD_WIFI_CIPAPMAC_SET,   /*!< Set MAC address of ESP access point */\n    LWESP_CMD_WIFI_CIPAP_GET,      /*!< Get IP address of ESP access point */\n    LWESP_CMD_WIFI_CIPAP_SET,      /*!< Set IP address of ESP access point */\n    LWESP_CMD_WIFI_CWLIF,          /*!< Get connected stations on access point */\n    LWESP_CMD_WIFI_CWQIF,          /*!< Discnnect station from SoftAP */\n    LWESP_CMD_WIFI_WPS,            /*!< Set WPS option */\n    LWESP_CMD_WIFI_MDNS,           /*!< Configure MDNS function */\n    LWESP_CMD_WIFI_CWHOSTNAME_SET, /*!< Set device hostname */\n    LWESP_CMD_WIFI_CWHOSTNAME_GET, /*!< Get device hostname */\n\n    /* TCP/IP related commands */\n    LWESP_CMD_TCPIP_CIPDOMAIN,        /*!< Get IP address from domain name = DNS function */\n    LWESP_CMD_TCPIP_CIPDNS_SET,       /*!< Configure user specific DNS servers */\n    LWESP_CMD_TCPIP_CIPDNS_GET,       /*!< Get DNS configuration */\n    LWESP_CMD_TCPIP_CIPSTATUS,        /*!< Get status of connections (deprecated, used on ESP8266 devices) */\n    LWESP_CMD_TCPIP_CIPSTATE,         /*!< Obtain connection state and information */\n    LWESP_CMD_TCPIP_CIPSTART,         /*!< Start client connection */\n    LWESP_CMD_TCPIP_CIPSEND,          /*!< Send network data */\n    LWESP_CMD_TCPIP_CIPCLOSE,         /*!< Close active connection */\n    LWESP_CMD_TCPIP_CIPSSLSIZE,       /*!< Set SSL buffer size for SSL connection */\n    LWESP_CMD_TCPIP_CIPSSLCCONF,      /*!< Set the SSL configuration */\n    LWESP_CMD_TCPIP_CIFSR,            /*!< Get local IP */\n    LWESP_CMD_TCPIP_CIPMUX,           /*!< Set single or multiple connections */\n    LWESP_CMD_TCPIP_CIPSERVER,        /*!< Enables/Disables server mode */\n    LWESP_CMD_TCPIP_CIPSERVERMAXCONN, /*!< Sets maximal number of connections allowed for server population */\n    LWESP_CMD_TCPIP_CIPMODE,          /*!< Transmission mode, either transparent or normal one */\n    LWESP_CMD_TCPIP_CIPSTO,           /*!< Sets connection timeout */\n    LWESP_CMD_TCPIP_CIPRECVMODE,      /*!< Sets mode for TCP data receive (manual or automatic) */\n    LWESP_CMD_TCPIP_CIPRECVDATA,      /*!< Manually reads TCP data from device */\n    LWESP_CMD_TCPIP_CIPRECVLEN,       /*!< Gets number of available bytes in connection to be read */\n    LWESP_CMD_TCPIP_CIUPDATE,         /*!< Perform self-update */\n    LWESP_CMD_TCPIP_CIPSNTPCFG,       /*!< Configure SNTP servers */\n    LWESP_CMD_TCPIP_CIPSNTPCFG_GET,   /*!< Get SNTP config */\n    LWESP_CMD_TCPIP_CIPSNTPTIME,      /*!< Get current time using SNTP */\n    LWESP_CMD_TCPIP_CIPSNTPINTV,      /*!< Set the SNTP time synchronization interval */\n    LWESP_CMD_TCPIP_CIPSNTPINTV_GET,  /*!< Query the SNTP time synchronization interval */\n    LWESP_CMD_TCPIP_CIPDINFO,         /*!< Configure what data are received on +IPD statement */\n    LWESP_CMD_TCPIP_PING,             /*!< Ping domain */\n    LWESP_CMD_WIFI_SMART_START,       /*!< Start smart config */\n    LWESP_CMD_WIFI_SMART_STOP,        /*!< Stop smart config */\n    LWESP_CMD_WEBSERVER,              /*!< Start or Stop Web Server */\n\n    /* BLE commands, ESP32 only */\n    LWESP_CMD_BLEINIT_GET, /*!< Get BLE status */\n} lwesp_cmd_t;\n\n/**\n * \\brief           Connection structure\n */\ntypedef struct lwesp_conn {\n    lwesp_conn_type_t type;   /*!< Connection type */\n    uint8_t num;              /*!< Connection number */\n    lwesp_ip_t remote_ip;     /*!< Remote IP address */\n    lwesp_port_t remote_port; /*!< Remote port number */\n    lwesp_port_t local_port;  /*!< Local IP address */\n    lwesp_evt_fn evt_func;    /*!< Callback function for connection */\n    void* arg;                /*!< User custom argument */\n\n    uint16_t val_id; /*!< Validation ID number. It is increased each time\n                                    a new connection is established.\n                                    It protects sending data to wrong connection\n                                    in case we have data in send queue,\n                                    and connection was closed and active\n                                    again in between. */\n\n    lwesp_linbuff_t buff; /*!< Linear buffer structure */\n    size_t total_recved;  /*!< Total number of bytes received */\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE || __DOXYGEN__\n    size_t tcp_available_bytes; /*!< Number of bytes in ESP ready to be read on connection.\n                                    This variable always holds last known info from ESP\n                                    device and is not decremented (or incremented) by application */\n#endif                          /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE || __DOXYGEN__ */\n    size_t tcp_not_ack_bytes;   /*!< Number of bytes not acknowledge by application done with processing\n                                    This variable is increased everytime new packet is\n                                    read to be sent to application and decreased\n                                    when application acknowledges it */\n\n    union {\n        struct {\n            uint8_t active        : 1; /*!< Status whether connection is active */\n            uint8_t client        : 1; /*!< Status whether connection is in client mode */\n            uint8_t data_received : 1; /*!< Status whether first data were received on connection */\n            uint8_t in_closing    : 1; /*!< Status if connection is in closing mode.\n                                                    When in closing mode, ignore any possible\n                                                    received data from function */\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE || __DOXYGEN__\n            uint8_t receive_blocked           : 1; /*!< Status whether we should block manual receive for some time */\n            uint8_t receive_is_command_queued : 1; /*!< Status whether manual read command is in the queue already */\n#endif                                             /* #if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE || __DOXYGEN__ */\n        } f;                                       /*!< Connection flags */\n    } status;                                      /*!< Connection status union with flag bits */\n} lwesp_conn_t;\n\n/**\n * \\ingroup         LWESP_PBUF\n * \\brief           Packet buffer structure\n */\ntypedef struct lwesp_pbuf {\n    struct lwesp_pbuf* next; /*!< Next pbuf in chain list */\n    size_t tot_len;          /*!< Total length of pbuf chain */\n    size_t len;              /*!< Length of payload */\n    size_t ref;              /*!< Number of references to this structure */\n    uint8_t* payload;        /*!< Pointer to payload memory */\n    lwesp_ip_t ip;           /*!< Remote address for received IPD data */\n    lwesp_port_t port;       /*!< Remote port for received IPD data */\n} lwesp_pbuf_t;\n\n/**\n * \\brief           Incoming network data read structure\n */\ntypedef struct {\n    uint8_t read;      /*!< Set to 1 when we should process input\n                                                        data as connection data */\n    size_t tot_len;    /*!< Total length of packet */\n    size_t rem_len;    /*!< Remaining bytes to read in current +IPD statement */\n    lwesp_conn_p conn; /*!< Pointer to connection for network data */\n    lwesp_ip_t ip;     /*!< Remote IP address on from IPD data */\n    lwesp_port_t port; /*!< Remote port on IPD data */\n\n    size_t buff_ptr;   /*!< Buffer pointer to save data to.\n                            When set to `NULL` while `read = 1`,\n                            reading should ignore incoming data */\n    lwesp_pbuf_p buff; /*!< Pointer to data buffer used for receiving data */\n} lwesp_ipd_t;\n\n/**\n * \\brief           Message queue structure to share between threads\n */\ntypedef struct lwesp_msg {\n    lwesp_cmd_t cmd_def;               /*!< Default message type received from queue */\n    lwesp_cmd_t cmd;                   /*!< Since some commands can have different\n                                                        subcommands, sub command is used here */\n    uint8_t i;                         /*!< Variable to indicate order number of subcommands */\n    lwesp_sys_sem_t sem;               /*!< Semaphore for the message */\n    uint8_t is_blocking;               /*!< Status if command is blocking */\n    uint32_t block_time;               /*!< Maximal blocking time in units of milliseconds.\n                                                        Use `0` to for non-blocking call */\n    lwespr_t res;                      /*!< Result of message operation */\n    lwespr_t res_err_code;             /*!< Result from \"ERR CODE\" received by AT command execution */\n    lwespr_t (*fn)(struct lwesp_msg*); /*!< Processing callback function to process packet */\n\n#if LWESP_CFG_USE_API_FUNC_EVT\n    lwesp_api_cmd_evt_fn evt_fn; /*!< Command callback API function */\n    void* evt_arg;               /*!< Command callback API callback parameter */\n#endif                           /* LWESP_CFG_USE_API_FUNC_EVT */\n\n    union {\n        struct {\n            uint32_t delay; /*!< Delay in units of milliseconds before executing first RESET command */\n        } reset;            /*!< Reset device */\n\n        struct {\n            uint32_t baudrate; /*!< Baudrate for AT port */\n        } uart;                /*!< UART configuration */\n\n        struct {\n            lwesp_mode_t mode;      /*!< Mode of operation */\n            lwesp_mode_t* mode_get; /*!< Get mode */\n        } wifi_mode;                /*!< When message type \\ref LWESP_CMD_WIFI_CWMODE is used */\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n        struct {\n            const char* name;       /*!< AP name */\n            const char* pass;       /*!< AP password */\n            const lwesp_mac_t* mac; /*!< Specific MAC address to use when connecting to AP */\n            uint8_t error_num;      /*!< Error number on connecting */\n        } sta_join;                 /*!< Message for joining to access point */\n\n        struct {\n            uint16_t interval; /*!< Interval in units of seconds */\n            uint16_t rep_cnt;  /*!< Repetition counter */\n        } sta_reconn_set;      /*!< Reconnect setup */\n\n        struct {\n            uint8_t en; /*!< Status to enable/disable auto join feature */\n        } sta_autojoin; /*!< Message for auto join procedure */\n\n        struct {\n            lwesp_sta_info_ap_t* info; /*!< Information structure */\n        } sta_info_ap;                 /*!< Message for reading the AP information */\n\n        struct {\n            const char* ssid; /*!< Pointer to optional filter SSID name to search */\n            lwesp_ap_t* aps;  /*!< Pointer to array to save access points */\n            size_t apsl;      /*!< Length of input array of access points */\n            size_t apsi;      /*!< Current access point array */\n            size_t* apf;      /*!< Pointer to output variable holding\n                                                        number of access points found */\n        } ap_list;            /*!< List for available access points to connect to */\n#endif                        /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n        struct {\n            const char* ssid; /*!< Name of access point */\n            const char* pwd;  /*!< Password of access point */\n            lwesp_ecn_t ecn;  /*!< Ecryption used */\n            uint8_t ch;       /*!< RF Channel used */\n            uint8_t max_sta;  /*!< Max allowed connected stations */\n            uint8_t hid;      /*!< Configuration if network is hidden or visible */\n        } ap_conf;            /*!< Parameters to configure access point */\n\n        struct {\n            lwesp_ap_conf_t* ap_conf; /*!< AP configuration */\n        } ap_conf_get;                /*!< Get the soft AP configuration */\n\n        struct {\n            lwesp_sta_t* stas; /*!< Pointer to array to save access points */\n            size_t stal;       /*!< Length of input array of access points */\n            size_t stai;       /*!< Current access point array */\n            size_t* staf;      /*!< Pointer to output variable holding number of access points found */\n        } sta_list;            /*!< List for stations connected to SoftAP */\n\n        struct {\n            uint8_t use_mac; /*!< Status if specific MAC is to be used */\n            lwesp_mac_t mac; /*!< MAC address to disconnect from access point */\n        } ap_disconn_sta;    /*!< Disconnect station from access point */\n#endif                       /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n        struct {\n            lwesp_ip_t* ip; /*!< Pointer to IP variable */\n            lwesp_ip_t* gw; /*!< Pointer to gateway variable */\n            lwesp_ip_t* nm; /*!< Pointer to netmask variable */\n#if LWESP_CFG_IPV6\n            lwesp_ip_t* ip6_ll; /*!< Pointer to IPV6 variable local address */\n            lwesp_ip_t* ip6_gl; /*!< Pointer to IPV6 variable global address */\n#endif                          /* LWESP_CFG_IPV6 */\n        } sta_ap_getip;         /*!< Message for reading station or access point IP */\n\n        struct {\n            lwesp_mac_t* mac; /*!< Pointer to MAC variable */\n        } sta_ap_getmac;      /*!< Message for reading station or access point MAC address */\n\n        struct {\n            lwesp_ip_t ip; /*!< IP variable */\n            lwesp_ip_t gw; /*!< Gateway variable */\n            lwesp_ip_t nm; /*!< Netmask variable */\n        } sta_ap_setip;    /*!< Message for setting station or access point IP */\n\n        struct {\n            lwesp_mac_t mac; /*!< Pointer to MAC variable */\n        } sta_ap_setmac;     /*!< Message for setting station or access point MAC address */\n\n        struct {\n            uint8_t sta; /*!< Set station DHCP settings */\n            uint8_t ap;  /*!< Set access point DHCP settings */\n            uint8_t en;  /*!< Enable/disable DHCP settings */\n        } wifi_cwdhcp;   /*!< Set DHCP settings */\n\n#if LWESP_CFG_HOSTNAME || __DOXYGEN__\n        struct {\n            const char* hostname_set; /*!< Hostname set value */\n            char* hostname_get;       /*!< Hostname get value */\n            size_t length;            /*!< Length of buffer when reading hostname */\n        } wifi_hostname;              /*!< Set or get hostname structure */\n#endif                                /* LWESP_CFG_HOSTNAME || __DOXYGEN__ */\n\n        /* Connection based commands */\n        struct {\n            lwesp_conn_t** conn;         /*!< Pointer to pointer to save connection used */\n            const char* remote_host;     /*!< Host to use for connection */\n            lwesp_port_t remote_port;    /*!< Remote port used for connection */\n            lwesp_conn_type_t type;      /*!< Connection type */\n            const char* local_ip;        /*!< Local IP address. Normally set to NULL */\n            uint16_t tcp_ssl_keep_alive; /*!< Keep alive parameter for TCP */\n            uint8_t udp_mode;            /*!< UDP mode */\n            lwesp_port_t udp_local_port; /*!< UDP local port */\n            void* arg;                   /*!< Connection custom argument */\n            lwesp_evt_fn evt_func;       /*!< Callback function to use on connection */\n            uint8_t success;             /*!< Status if connection AT+CIPSTART succedded */\n            uint8_t ssl_auth;            /*!< SSL authentication mode */\n            uint8_t ssl_pki_num;         /*!< SSL PKI number */\n            uint8_t ssl_ca_num;          /*!< SSL CA number */\n        } conn_start;                    /*!< Structure for starting new connection */\n\n        struct {\n            lwesp_conn_t* conn; /*!< Pointer to connection to close */\n            uint16_t val_id;    /*!< Connection current validation ID when command was sent to queue */\n        } conn_close;           /*!< Close connection */\n\n        struct {\n            lwesp_conn_t* conn;          /*!< Pointer to connection to send data */\n            size_t btw;                  /*!< Number of remaining bytes to write */\n            size_t ptr;                  /*!< Current write pointer for data */\n            const uint8_t* data;         /*!< Data to send */\n            size_t sent;                 /*!< Number of bytes sent in last packet */\n            size_t sent_all;             /*!< Number of bytes sent all together */\n            uint8_t tries;               /*!< Number of tries used for last packet */\n            uint8_t wait_send_ok_err;    /*!< Set to 1 when we wait for SEND OK or SEND ERROR */\n            const lwesp_ip_t* remote_ip; /*!< Remote IP address for UDP connection */\n            lwesp_port_t remote_port;    /*!< Remote port address for UDP connection */\n            uint8_t fau;                 /*!< Free after use flag to free memory after data are sent (or not) */\n            size_t* bw;                  /*!< Number of bytes written so far */\n            uint16_t val_id;             /*!< Connection current validation ID when command was sent to queue */\n        } conn_send;                     /*!< Structure to send data on connection */\n\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n        struct {\n            lwesp_conn_t* conn;    /*!< Connection handle */\n            lwesp_pbuf_p buff;     /*!< Buffer handle to write received data to */\n            size_t len;            /*!< Number of bytes to read from device */\n            uint8_t ipd_recv;      /*!< Status indicating `+IPD` has been received during `AT+CIPRECVLEN` command.\n                                                        When this happens, we will repeat the length reading again */\n            uint8_t is_last_check; /*!< When set to `1`, reading has been completed already\n                                    and CIPRECVLEN is read again for new status */\n            uint8_t read;          /*!< Set to 1 when in raw data read mode */\n            size_t tot_len; /*!< Total length expected for this read operation (actual data len received from device) */\n            size_t buff_ptr; /*!< Buffer pointer to save data to (next character) */\n        } conn_recv;         /*!< Structure to manually read TCP data */\n#endif                       /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n\n        /* TCP/IP based commands */\n        struct {\n            uint8_t en;        /*!< Enable/Disable server status */\n            lwesp_port_t port; /*!< Server port number */\n            uint16_t max_conn; /*!< Maximal number of connections available for server */\n            uint16_t timeout;  /*!< Connection timeout */\n            lwesp_evt_fn cb;   /*!< Server default callback function */\n        } tcpip_server;        /*!< Server configuration */\n\n        struct {\n            size_t size; /*!< Size for SSL in uints of bytes */\n        } tcpip_sslsize; /*!< TCP SSL size for SSL connections */\n#if LWESP_CFG_DNS\n        struct {\n            const char* host; /*!< Hostname to resolve IP address for */\n            lwesp_ip_t* ip;   /*!< Pointer to IP address to save result */\n        } dns_getbyhostname;  /*!< DNS function */\n\n        struct {\n            uint8_t en;     /*!< Enable/Disable status */\n            const char* s1; /*!< DNS server 1 */\n            const char* s2; /*!< DNS server 2 */\n        } dns_setconfig;    /*!< Set DNS config */\n\n        struct {\n            uint8_t dnsi;   /*!< DNS server index to get */\n            lwesp_ip_t* s1; /*!< DNS server 1 */\n            lwesp_ip_t* s2; /*!< DNS server 2 */\n        } dns_getconf;      /*!< Get DNS config */\n#endif                      /* LWESP_CFG_DNS */\n#if LWESP_CFG_PING || __DOXYGEN__\n        struct {\n            const char* host;   /*!< Hostname to ping */\n            uint32_t time;      /*!< Time used for ping */\n            uint32_t* time_out; /*!< Pointer to time output variable */\n        } tcpip_ping;           /*!< Pinging structure */\n#endif                          /* LWESP_CFG_PING || __DOXYGEN__ */\n#if LWESP_CFG_SNTP || __DOXYGEN__\n        struct {\n            uint8_t en;     /*!< Status if SNTP is enabled or not */\n            int16_t tz;     /*!< Timezone setup */\n            const char* h1; /*!< Optional server 1 */\n            const char* h2; /*!< Optional server 2 */\n            const char* h3; /*!< Optional server 3 */\n        } tcpip_sntp_cfg;   /*!< SNTP configuration */\n\n        struct {\n            uint8_t* en;      /*!< Status if SNTP is enabled or not */\n            int16_t* tz;      /*!< Timezone setup */\n            char* h1;         /*!< Optional server 1 */\n            char* h2;         /*!< Optional server 2 */\n            char* h3;         /*!< Optional server 3 */\n        } tcpip_sntp_cfg_get; /*!< SNTP configuration read */\n\n        struct {\n            uint32_t interval; /*!< Time in units of seconds */\n        } tcpip_sntp_intv;     /*!< SNTP interval configuration */\n\n        struct {\n            uint32_t* interval; /*!< Pointer to write time to */\n        } tcpip_sntp_intv_get;  /*!< SNTP interval configuration */\n\n        struct {\n            struct tm* dt; /*!< Pointer to datetime structure */\n        } tcpip_sntp_time; /*!< SNTP get time */\n#endif                     /* LWESP_CFG_SNTP || __DOXYGEN__ */\n#if LWESP_CFG_WPS || __DOXYGEN__\n        struct {\n            uint8_t en;          /*!< Status if WPS is enabled or not */\n            lwesp_ecn_t min_ecn; /*!< Minimum ECN level WPS will look for */\n        } wps_cfg;               /*!< WPS configuration */\n#endif                           /* LWESP_CFG_WPS || __DOXYGEN__ */\n#if LWESP_CFG_MDNS || __DOXYGEN__\n        struct {\n            uint8_t en;         /*!< Set to 1 to enable or 0 to disable */\n            const char* host;   /*!< mDNS host name */\n            const char* server; /*!< mDNS server */\n            lwesp_port_t port;  /*!< mDNS server port */\n        } mdns;                 /*!< mDNS configuration */\n#endif                          /* LWESP_CFG_MDNS || __DOXYGEN__ */\n#if LWESP_CFG_WEBSERVER || __DOXYGEN__\n        struct {\n            uint8_t en;        /*!< Enable/Disable web server status */\n            lwesp_port_t port; /*!< Server port number */\n            uint8_t timeout;   /*!< Connection timeout */\n        } web_server;          /*!< Web Server configuration */\n#endif                         /* LWESP_CFG_WEBSERVER || __DOXYGEN__ */\n        struct {\n            uint8_t link_id;   /*!< Link ID of connection to set SSL configuration for */\n            uint8_t auth_mode; /*!< Timezone setup */\n            uint8_t\n                pki_number; /*!< The index of cert and private key, if only one cert and private key, the value should be 0. */\n            uint8_t ca_number; /*!< The index of CA, if only one CA, the value should be 0. */\n        } tcpip_ssl_cfg;       /*!< SSl configuration for connection */\n\n#if LWESP_CFG_FLASH\n        struct {\n            lwesp_flash_partition_t partition; /*!< Partition to perform on */\n            uint32_t offset;                   /*!< Offset from start of partition */\n            uint32_t length;                   /*!< Length of data */\n        } flash_erase;                         /*!< Flash erase */\n\n        struct {\n            lwesp_flash_partition_t partition; /*!< Partition to perform on */\n            uint32_t offset;                   /*!< Offset from start of partition */\n            uint32_t length;                   /*!< Length of data */\n            const void* data;                  /*!< Data pointer to write */\n        } flash_write;                         /*!< Flash write */\n\n        struct {\n            lwesp_mfg_namespace_t namespace; /*!< Partition to perform on */\n            uint32_t offset;                 /*!< Offset from start of namespace */\n            uint32_t length;                 /*!< Length of data */\n        } mfg_erase;                         /*!< Flash erase */\n\n        struct {\n            lwesp_mfg_namespace_t namespace; /*!< Partition to perform on */\n            const char* key;                 /*!< Key to write */\n            lwesp_mfg_valtype_t valtype;     /*!< Value type */\n            uint32_t length;                 /*!< Length of data */\n            const void* data_ptr;            /*!< Data pointer to write. Used for non-primitive types */\n            uint8_t wait_second_ok;          /*!< Set to `1` to wait for second OK */\n\n            union {\n                uint8_t u8;\n                int8_t i8;\n                uint16_t u16;\n                int16_t i16;\n                uint32_t u32;\n                int32_t i32;\n            } data_prim;\n        } mfg_write; /*!< MFG write */\n\n        struct {\n            lwesp_mfg_namespace_t namespace; /*!< Partition to perform on */\n            const char* key;                 /*!< Key to write */\n            lwesp_mfg_valtype_t valtype;     /*!< Value type */\n            uint32_t offset;                 /*!< Offset from start to read data */\n            uint32_t btr;                    /*!< Number of bytes to read */\n            uint32_t* br;                    /*!< Number of bytes read */\n            uint8_t* data_ptr;               /*!< Data pointer to write. Used for non-primitive types */\n            uint8_t read_mode;               /*!< Set to `1` when in data read mode */\n            uint32_t buff_ptr;               /*!< Next write pointer into buffer */\n        } mfg_read;                          /*!< MFG read */\n#endif\n    } msg; /*!< Group of different message contents */\n} lwesp_msg_t;\n\n/**\n * \\brief           IP and MAC structure with netmask and gateway addresses\n */\ntypedef struct {\n    lwesp_ip_t ip; /*!< IP address */\n    lwesp_ip_t gw; /*!< Gateway address */\n    lwesp_ip_t nm; /*!< Netmask address */\n#if LWESP_CFG_IPV6\n    lwesp_ip_t ip6_ll; /*!< Local IPV6 address */\n    lwesp_ip_t ip6_gl; /*!< Global IPV6 address */\n#endif                 /* LWESP_CFG_IPV6 */\n    lwesp_mac_t mac;   /*!< MAC address */\n    uint8_t dhcp;      /*!< Flag indicating DHCP is enabled */\n\n    struct {\n        uint8_t has_ip : 1; /*!< Flag indicating IP is available */\n#if LWESP_CFG_IPV6\n        uint8_t has_ipv6_ll : 1;  /*!< Flag indicating local IPv6 is available */\n        uint8_t has_ipv6_gl : 1;  /*!< Flag indicating global IPv6 is available */\n#endif                            /* LWESP_CFG_IPV6 */\n        uint8_t is_connected : 1; /*!< Flag indicating ESP is connected to wifi */\n    } f;                          /*!< Flags structure */\n} lwesp_ip_mac_t;\n\n/**\n * \\brief           Link connection active info\n */\ntypedef struct {\n    uint8_t failed;           /*!< Status if connection successful */\n    uint8_t num;              /*!< Connection number */\n    uint8_t is_server;        /*!< Status if connection is client or server */\n    lwesp_conn_type_t type;   /*!< Connection type */\n    lwesp_ip_t remote_ip;     /*!< Remote IP address */\n    lwesp_port_t remote_port; /*!< Remote port */\n    lwesp_port_t local_port;  /*!< Local port number */\n} lwesp_link_conn_t;\n\n/**\n * \\brief           Callback function linked list prototype\n */\ntypedef struct lwesp_evt_func {\n    struct lwesp_evt_func* next; /*!< Next function in the list */\n    lwesp_evt_fn fn;             /*!< Function pointer itself */\n} lwesp_evt_func_t;\n\n/**\n * \\brief           ESP modules structure\n */\ntypedef struct {\n    lwesp_device_t device;          /*!< ESP device type */\n    lwesp_sw_version_t version_at;  /*!< Version of AT command software on ESP device */\n    lwesp_sw_version_t version_sdk; /*!< Version of SDK used to build AT software */\n\n    uint32_t\n        active_conns; /*!< Bit field of currently active connections, @todo: In case user has more than 32 connections, single variable is not enough */\n    uint32_t active_conns_last; /*!< The same as previous but status before last check */\n\n    lwesp_link_conn_t link_conn;             /*!< Link connection handle */\n    lwesp_ipd_t ipd;                         /*!< Connection incoming data structure */\n    lwesp_conn_t conns[LWESP_CFG_MAX_CONNS]; /*!< Array of all connection structures */\n\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n    lwesp_ip_mac_t sta; /*!< Station IP and MAC addressed */\n#endif                  /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n    lwesp_ip_mac_t ap; /*!< Access point IP and MAC addressed */\n#endif                 /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n\n#if LWESP_CFG_SNTP_AUTO_READ_TIME_ON_UPDATE || __DOXYGEN__\n    struct tm sntp_dt; /*!< Data & time structure, used for automatic\n                                read request from the module, if feature enabled. */\n#endif                 /* LWESP_CFG_SNTP_AUTO_READ_TIME_ON_UPDATE || __DOXYGEN__ */\n} lwesp_modules_t;\n\n/**\n * \\brief           ESP global structure\n */\ntypedef struct {\n    size_t locked_cnt; /*!< Counter how many times (recursive) stack is currently locked */\n\n    lwesp_sys_sem_t sem_sync;          /*!< Synchronization semaphore between threads */\n    lwesp_sys_mbox_t mbox_producer;    /*!< Producer message queue handle */\n    lwesp_sys_mbox_t mbox_process;     /*!< Consumer message queue handle */\n    lwesp_sys_thread_t thread_produce; /*!< Producer thread handle */\n    lwesp_sys_thread_t thread_process; /*!< Processing thread handle */\n#if !LWESP_CFG_INPUT_USE_PROCESS || __DOXYGEN__\n    lwesp_buff_t buff; /*!< Input processing buffer */\n#endif                 /* !LWESP_CFG_INPUT_USE_PROCESS || __DOXYGEN__ */\n    lwesp_ll_t ll;     /*!< Low level functions */\n\n    lwesp_msg_t* msg; /*!< Pointer to current user message being executed */\n\n    lwesp_evt_t evt;            /*!< Callback processing structure */\n    lwesp_evt_func_t* evt_func; /*!< Callback function linked list */\n    lwesp_evt_fn evt_server;    /*!< Default callback function for server connections */\n\n    lwesp_modules_t m; /*!< All modules. When resetting, reset structure */\n\n    union {\n        struct {\n            uint8_t initialized : 1; /*!< Flag indicating ESP library is initialized */\n            uint8_t dev_present : 1; /*!< Flag indicating if physical device is connected to host device */\n        } f;                         /*!< Flags structure */\n    } status;                        /*!< Status structure */\n\n    uint8_t conn_val_id; /*!< Validation ID increased each time device\n                                                        connects to wifi network or on reset.\n                                                        It is used for connections */\n} lwesp_t;\n\n/**\n * \\brief           Physical device descriptor data\n * \n * This is used for library internal reasons\n */\ntypedef struct {\n    lwesp_device_t device;   /*!< Device identification */\n    const char* gmr_strid_1; /*!< AT+GMR string identification option 1 */\n    const char* gmr_strid_2; /*!< AT+GMR string identification option 2 */\n    uint32_t min_at_version; /*!< Minimum Espressif official AT version for the module */\n} lwesp_esp_device_desc_t;\n\n/**\n * \\}\n */\n\n#if !__DOXYGEN__\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_PRIVATE Internal functions\n * \\brief           Functions, structures and enumerations\n * \\{\n */\n\nextern lwesp_t esp;\n\n#define LWESP_MSG_VAR_DEFINE(name) lwesp_msg_t* name\n#define LWESP_MSG_VAR_ALLOC(name, blocking)                                                                            \\\n    do {                                                                                                               \\\n        (name) = lwesp_mem_malloc(sizeof(*(name)));                                                                    \\\n        LWESP_DEBUGW(LWESP_CFG_DBG_VAR | LWESP_DBG_TYPE_TRACE, (name) != NULL,                                         \\\n                     \"[MSG VAR] Allocated %d bytes at %p\\r\\n\", (int)sizeof(*(name)), (void*)(name));                   \\\n        LWESP_DEBUGW(LWESP_CFG_DBG_VAR | LWESP_DBG_TYPE_TRACE, (name) == NULL,                                         \\\n                     \"[MSG VAR] Error allocating %d bytes\\r\\n\", (int)sizeof(*(name)));                                 \\\n        if ((name) == NULL) {                                                                                          \\\n            return lwespERRMEM;                                                                                        \\\n        }                                                                                                              \\\n        LWESP_MEMSET((name), 0x00, sizeof(*(name)));                                                                   \\\n        (name)->is_blocking = LWESP_U8((blocking) > 0);                                                                \\\n    } while (0)\n#define LWESP_MSG_VAR_REF(name) (*(name))\n#define LWESP_MSG_VAR_FREE(name)                                                                                       \\\n    do {                                                                                                               \\\n        LWESP_DEBUGF(LWESP_CFG_DBG_VAR | LWESP_DBG_TYPE_TRACE, \"[MSG VAR] Free memory: %p\\r\\n\", (void*)(name));        \\\n        if (lwesp_sys_sem_isvalid(&((name)->sem))) {                                                                   \\\n            lwesp_sys_sem_delete(&((name)->sem));                                                                      \\\n            lwesp_sys_sem_invalid(&((name)->sem));                                                                     \\\n        }                                                                                                              \\\n        lwesp_mem_free_s((void**)&(name));                                                                             \\\n    } while (0)\n#if LWESP_CFG_USE_API_FUNC_EVT\n#define LWESP_MSG_VAR_SET_EVT(name, e_fn, e_arg)                                                                       \\\n    do {                                                                                                               \\\n        (name)->evt_fn = (e_fn);                                                                                       \\\n        (name)->evt_arg = (e_arg);                                                                                     \\\n    } while (0)\n#else /* LWESP_CFG_USE_API_FUNC_EVT */\n#define LWESP_MSG_VAR_SET_EVT(name, e_fn, e_arg)                                                                       \\\n    do {                                                                                                               \\\n        LWESP_UNUSED(e_fn);                                                                                            \\\n        LWESP_UNUSED(e_arg);                                                                                           \\\n    } while (0)\n#endif /* !LWESP_CFG_USE_API_FUNC_EVT */\n\n#define LWESP_CHARISNUM(x)    ((x) >= '0' && (x) <= '9')\n#define LWESP_CHARTONUM(x)    ((x) - '0')\n#define LWESP_CHARISHEXNUM(x) (((x) >= '0' && (x) <= '9') || ((x) >= 'a' && (x) <= 'f') || ((x) >= 'A' && (x) <= 'F'))\n#define LWESP_CHARHEXTONUM(x)                                                                                          \\\n    (((x) >= '0' && (x) <= '9')                                                                                        \\\n         ? ((x) - '0')                                                                                                 \\\n         : (((x) >= 'a' && (x) <= 'f') ? ((x) - 'a' + 10) : (((x) >= 'A' && (x) <= 'F') ? ((x) - 'A' + 10) : 0)))\n#define LWESP_ISVALIDASCII(x) (((x) >= 32 && (x) <= 126) || (x) == '\\r' || (x) == '\\n')\n\n#if LWESP_CFG_IPV6\n#define LWESP_RESET_STA_HAS_IP()                                                                                       \\\n    do {                                                                                                               \\\n        esp.m.sta.f.has_ip = 0;                                                                                        \\\n        esp.m.sta.f.has_ipv6_ll = 0;                                                                                   \\\n        esp.m.sta.f.has_ipv6_gl = 0;                                                                                   \\\n    } while (0)\n#else\n#define LWESP_RESET_STA_HAS_IP() esp.m.sta.f.has_ip = 0\n#endif /* LWESP_CFG_IPV6 */\n\n#define CMD_IS_CUR(c)        (esp.msg != NULL && esp.msg->cmd == (c))\n#define CMD_IS_DEF(c)        (esp.msg != NULL && esp.msg->cmd_def == (c))\n#define CMD_GET_CUR()        ((lwesp_cmd_t)(((esp.msg != NULL) ? esp.msg->cmd : LWESP_CMD_IDLE)))\n#define CMD_GET_DEF()        ((lwesp_cmd_t)(((esp.msg != NULL) ? esp.msg->cmd_def : LWESP_CMD_IDLE)))\n\n#define CRLF                 \"\\r\\n\"\n#define CRLF_LEN             2\n\n#define LWESP_PORT2NUM(port) ((uint32_t)(port))\n\n/* Define macros to check if connection is any (either V4 or V6) of the type */\n#if LWESP_CFG_IPV6\n#define CONN_IS_TCP_V4_OR_V6(contype) ((contype) == LWESP_CONN_TYPE_TCP || (contype) == LWESP_CONN_TYPE_TCPV6)\n#define CONN_IS_SSL_V4_OR_V6(contype) ((contype) == LWESP_CONN_TYPE_SSL || (contype) == LWESP_CONN_TYPE_SSLV6)\n#define CONN_IS_UDP_V4_OR_V6(contype) ((contype) == LWESP_CONN_TYPE_UDP || (contype) == LWESP_CONN_TYPE_UDPV6)\n#else\n#define CONN_IS_TCP_V4_OR_V6(contype) ((contype) == LWESP_CONN_TYPE_TCP)\n#define CONN_IS_SSL_V4_OR_V6(contype) ((contype) == LWESP_CONN_TYPE_SSL)\n#define CONN_IS_UDP_V4_OR_V6(contype) ((contype) == LWESP_CONN_TYPE_UDP)\n#endif\n\nconst char* lwespi_dbg_msg_to_string(lwesp_cmd_t cmd);\nlwespr_t lwespi_process(const void* data, size_t len);\nlwespr_t lwespi_process_buffer(void);\nlwespr_t lwespi_initiate_cmd(lwesp_msg_t* msg);\nuint8_t lwespi_is_valid_conn_ptr(lwesp_conn_p conn);\nlwespr_t lwespi_send_cb(lwesp_evt_type_t type);\nlwespr_t lwespi_send_conn_cb(lwesp_conn_t* conn, lwesp_evt_fn cb);\nvoid lwespi_conn_init(void);\nvoid lwespi_conn_start_timeout(lwesp_conn_p conn);\nlwespr_t lwespi_conn_check_available_rx_data(void);\nlwespr_t lwespi_conn_manual_tcp_try_read_data(lwesp_conn_p conn);\nlwespr_t lwespi_send_msg_to_producer_mbox(lwesp_msg_t* msg, lwespr_t (*process_fn)(lwesp_msg_t*),\n                                          uint32_t max_block_time);\nuint32_t lwespi_get_from_mbox_with_timeout_checks(lwesp_sys_mbox_t* b, void** m, uint32_t timeout);\n\nvoid lwespi_reset_everything(uint8_t forced);\nvoid lwespi_process_events_for_timeout_or_error(lwesp_msg_t* msg, lwespr_t err);\n\nlwesp_cmd_t lwespi_get_cipstatus_or_cipstate_cmd(void);\nconst lwesp_esp_device_desc_t* lwespi_get_device_desc_for_device(lwesp_device_t device);\n\n/**\n * \\}\n */\n\n#endif /* !__DOXYGEN__ */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_PRIV_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_server.h",
    "content": "/**\n * \\file            lwesp_ping.h\n * \\brief           Ping API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_SERVER_HDR_H\n#define LWESP_SERVER_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_SERVER SERVER\n * \\brief           Server mode\n * \\{\n */\n\nlwespr_t lwesp_set_server(uint8_t en, lwesp_port_t port, uint16_t max_conn, uint16_t timeout, lwesp_evt_fn cb,\n                          const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_SERVER_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_smart.h",
    "content": "/**\n * \\file            lwesp_smart.h\n * \\brief           Smart API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n * Copyright (c) 2020 Seeed Technology\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_SMART_HDR_H\n#define LWESP_SMART_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_SMART SMART function\n * \\brief           SMART function on ESP device\n * \\{\n */\n\nlwespr_t lwesp_smart_set_config(uint8_t en, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                                const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_SMART_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_sntp.h",
    "content": "/**\n * \\file            lwesp_sntp.h\n * \\brief           SNTP API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_SNTP_HDR_H\n#define LWESP_SNTP_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_SNTP Simple network time protocol\n * \\brief           Simple network time protocol supported by AT commands\n * \\{\n */\n\nlwespr_t lwesp_sntp_set_config(uint8_t en, int16_t tz, const char* h1, const char* h2, const char* h3,\n                               const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_sntp_get_config(uint8_t* en, int16_t* tz, char* h1, char* h2, char* h3,\n                               const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_sntp_set_interval(uint32_t interval, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                                 const uint32_t blocking);\nlwespr_t lwesp_sntp_get_interval(uint32_t* interval, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                                 const uint32_t blocking);\nlwespr_t lwesp_sntp_gettime(struct tm* dt, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                            const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_SNTP_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_sta.h",
    "content": "/**\n * \\file            lwesp_sta.h\n * \\brief           Station API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_STA_HDR_H\n#define LWESP_STA_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_STA Station API\n * \\brief           Station API\n * \\{\n */\n\nlwespr_t lwesp_sta_join(const char* name, const char* pass, const lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn,\n                        void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_sta_quit(const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_sta_autojoin(uint8_t en, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                            const uint32_t blocking);\nlwespr_t lwesp_sta_reconnect_set_config(uint16_t interval, uint16_t rep_cnt, const lwesp_api_cmd_evt_fn evt_fn,\n                                        void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_sta_getip(lwesp_ip_t* ip, lwesp_ip_t* gw, lwesp_ip_t* nm, const lwesp_api_cmd_evt_fn evt_fn,\n                         void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_sta_setip(const lwesp_ip_t* ip, const lwesp_ip_t* gw, const lwesp_ip_t* nm,\n                         const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_sta_getmac(lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                          const uint32_t blocking);\nlwespr_t lwesp_sta_setmac(const lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                          const uint32_t blocking);\nuint8_t lwesp_sta_has_ip(void);\nuint8_t lwesp_sta_is_joined(void);\nlwespr_t lwesp_sta_copy_ip(lwesp_ip_t* ip, lwesp_ip_t* gw, lwesp_ip_t* nm, uint8_t* is_dhcp);\nlwespr_t lwesp_sta_list_ap(const char* ssid, lwesp_ap_t* aps, size_t apsl, size_t* apf,\n                           const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking);\nlwespr_t lwesp_sta_get_ap_info(lwesp_sta_info_ap_t* info, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                               const uint32_t blocking);\nuint8_t lwesp_sta_is_ap_802_11b(lwesp_ap_t* ap);\nuint8_t lwesp_sta_is_ap_802_11g(lwesp_ap_t* ap);\nuint8_t lwesp_sta_is_ap_802_11n(lwesp_ap_t* ap);\n\n#if LWESP_CFG_IPV6 || __DOXYGEN__\nuint8_t lwesp_sta_has_ipv6_local(void);\nuint8_t lwesp_sta_has_ipv6_global(void);\n#else\n#define lwesp_sta_has_ipv6_local()  0\n#define lwesp_sta_has_ipv6_global() 0\n#endif /* LWESP_CFG_IPV6 || __DOXYGEN__ */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_STA_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_threads.h",
    "content": "/**\n * \\file            lwesp_threads.h\n * \\brief           OS threads implementations\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_THREADS_HDR_H\n#define LWESP_THREADS_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid lwesp_thread_produce(void* const arg);\nvoid lwesp_thread_process(void* const arg);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_THREADS_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_timeout.h",
    "content": "/**\n * \\file            lwesp_timeout.h\n * \\brief           Timeout manager\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_TIMEOUT_HDR_H\n#define LWESP_TIMEOUT_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_TIMEOUT Timeout manager\n * \\brief           Timeout manager\n * \\{\n */\n\nlwespr_t lwesp_timeout_add(uint32_t time, lwesp_timeout_fn fn, void* arg);\nlwespr_t lwesp_timeout_remove(lwesp_timeout_fn fn);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_TIMEOUT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_types.h",
    "content": "/**\n * \\file            lwesp_types.h\n * \\brief           List of structures and enumerations for public usage\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_DEFS_HDR_H\n#define LWESP_DEFS_HDR_H\n\n#include <stdint.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <time.h>\n#include \"lwesp/lwesp_opt.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_TYPES Structures and enumerations\n * \\brief           List of core structures and enumerations\n * \\{\n */\n\n/**\n * \\}\n */\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           Result enumeration used across application functions\n */\ntypedef enum {\n    lwespOK = 0,       /*!< Function succeeded */\n    lwespOKIGNOREMORE, /*!< Function succedded, should continue as lwespOK but ignore sending more data. This result is possible on connection data receive callback */\n    lwespERR,          /*!< General error */\n    lwespERRPAR,       /*!< Wrong parameters on function call */\n    lwespERRMEM,       /*!< Memory error occurred */\n    lwespTIMEOUT,      /*!< Timeout occurred on command */\n    lwespCONT,         /*!< There is still some command to be processed in current command */\n    lwespCLOSED,       /*!< Connection just closed */\n    lwespINPROG,       /*!< Operation is in progress */\n\n    lwespERRNOIP,             /*!< Station does not have IP address */\n    lwespERRNOFREECONN,       /*!< There is no free connection available to start */\n    lwespERRCONNTIMEOUT,      /*!< Timeout received when connection to access point */\n    lwespERRPASS,             /*!< Invalid password for access point */\n    lwespERRNOAP,             /*!< No access point found with specific SSID and MAC address */\n    lwespERRCONNFAIL,         /*!< Connection failed to access point */\n    lwespERRWIFINOTCONNECTED, /*!< Wifi not connected to access point */\n    lwespERRNODEVICE,         /*!< Device is not present */\n    lwespERRBLOCKING,         /*!< Blocking mode command is not allowed */\n    lwespERRCMDNOTSUPPORTED,  /*!< Command is not supported error received by device,\n                                or when command is not supported in the stack itself */\n} lwespr_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           List of support ESP devices by firmware\n */\ntypedef enum {\n    LWESP_DEVICE_UNKNOWN = 0x00, /*!< Device is unknown by default */\n    LWESP_DEVICE_ESP8266,        /*!< Device is ESP8266 */\n    LWESP_DEVICE_ESP32,          /*!< Device is ESP32 */\n    LWESP_DEVICE_ESP32_C2,       /*!< Device is ESP32-C2 */\n    LWESP_DEVICE_ESP32_C3,       /*!< Device is ESP32-C3 */\n    LWESP_DEVICE_ESP32_C6,       /*!< Device is ESP32-C6 */\n    LWESP_DEVICE_END,            /*!< End of the list */\n} lwesp_device_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           List of encryptions of access point\n */\ntypedef enum {\n    LWESP_ECN_OPEN = 0x00,            /*!< No encryption on access point */\n    LWESP_ECN_WEP = 0x01,             /*!< WEP (Wired Equivalent Privacy) encryption */\n    LWESP_ECN_WPA_PSK = 0x02,         /*!< WPA (Wifi Protected Access) encryption */\n    LWESP_ECN_WPA2_PSK = 0x03,        /*!< WPA2 (Wifi Protected Access 2) encryption */\n    LWESP_ECN_WPA_WPA2_PSK = 0x04,    /*!< WPA/2 (Wifi Protected Access 1/2) encryption */\n    LWESP_ECN_WPA2_Enterprise = 0x05, /*!< Enterprise encryption. \\note ESP8266 is not able to connect to such device */\n    LWESP_ECN_WPA3_PSK = 0x06,        /*!< WPA3 (Wifi Protected Access 3) encryption */\n    LWESP_ECN_WPA2_WPA3_PSK = 0x07,   /*!< WPA2/3 (Wifi Protected Access 2/3) encryption */\n    LWESP_ECN_WAPI_PSK = 0x08,        /*!< WAPI PSK encryption mode */\n    LWESP_ECN_OWE = 0x08,             /*!< Opportunistic Wifi Encryption for end-to-end encryption */\n    LWESP_ECN_END,                    /*!< Last entry */\n} lwesp_ecn_t;\n\n/**\n * \\brief           Access point cipher modes, used for access point scan data\n */\ntypedef enum {\n    LWESP_AP_CIPHER_NONE = 0x00,         /*!< None value */\n    LWESP_AP_CIPHER_WEP40 = 0x01,        /*!< WEP40 mode */\n    LWESP_AP_CIPHER_WEP104 = 0x02,       /*!< WEB104 */\n    LWESP_AP_CIPHER_TKIP = 0x03,         /*!< TKIP */\n    LWESP_AP_CIPHER_CCMP = 0x04,         /*!< CCMP */\n    LWESP_AP_CIPHER_TKIP_CCMP = 0x05,    /*!< TKIP and CCMP */\n    LWESP_AP_CIPHER_AES_CMAC_128 = 0x06, /*!< AES-CMAC-128 */\n    LWESP_AP_CIPHER_UNKNOWN = 0x07,      /*!< Unknown value */\n    LWESP_AP_CIPHER_END,\n} lwesp_ap_cipher_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           IP type\n */\ntypedef enum {\n    LWESP_IPTYPE_V4 = 0x00, /*!< IP type is V4 */\n    LWESP_IPTYPE_V6         /*!< IP type is V6 */\n} lwesp_iptype_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           IPv4 address structure\n */\ntypedef struct {\n    uint8_t addr[4]; /*!< IP address data */\n} lwesp_ip4_addr_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           IPv6 address structure\n */\ntypedef struct {\n    uint16_t addr[8]; /*!< IP address data */\n} lwesp_ip6_addr_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           IP structure\n */\ntypedef struct {\n    union {\n        lwesp_ip4_addr_t ip4; /*!< IPv4 address */\n#if LWESP_CFG_IPV6 || __DOXYGEN__\n        lwesp_ip6_addr_t ip6; /*!< IPv6 address */\n#endif                        /* LWESP_CFG_IPV6  || __DOXYGEN__ */\n    } addr;                   /*!< Actual IP address */\n\n    lwesp_iptype_t type; /*!< IP type, either V4 or V6 */\n} lwesp_ip_t;\n\n/**\n * \\ingroup         LWESP_UTILITIES\n * \\brief           Set IPv4 address to \\ref lwesp_ip_t variable\n * \\param[in]       ip_str: Pointer to IP structure\n * \\param[in]       i1,i2,i3,i4: IPv4 parts\n */\n#define lwesp_ip_set_ip4(ip_str, i1, i2, i3, i4)                                                                       \\\n    do {                                                                                                               \\\n        (ip_str)->type = LWESP_IPTYPE_V4;                                                                              \\\n        (ip_str)->addr.ip4.addr[0] = (i1);                                                                             \\\n        (ip_str)->addr.ip4.addr[1] = (i2);                                                                             \\\n        (ip_str)->addr.ip4.addr[2] = (i3);                                                                             \\\n        (ip_str)->addr.ip4.addr[3] = (i4);                                                                             \\\n    } while (0)\n\n/**\n * \\ingroup         LWESP_UTILITIES\n * \\brief           Set IPv6 address to \\ref lwesp_ip_t variable\n * \\param[in]       ip_str: Pointer to IP structure\n * \\param[in]       i1,i2,i3,i4,i5,i6,i7,i8: IPv6 parts\n */\n#define lwesp_ip_set_ip6(ip_str, i1, i2, i3, i4, i5, i6, i7, i8)                                                       \\\n    do {                                                                                                               \\\n        (ip_str)->type = LWESP_IPTYPE_V6;                                                                              \\\n        (ip_str)->addr.ip6.addr[0] = (i1);                                                                             \\\n        (ip_str)->addr.ip6.addr[1] = (i2);                                                                             \\\n        (ip_str)->addr.ip6.addr[2] = (i3);                                                                             \\\n        (ip_str)->addr.ip6.addr[3] = (i4);                                                                             \\\n        (ip_str)->addr.ip6.addr[4] = (i5);                                                                             \\\n        (ip_str)->addr.ip6.addr[5] = (i6);                                                                             \\\n        (ip_str)->addr.ip6.addr[6] = (i7);                                                                             \\\n        (ip_str)->addr.ip6.addr[7] = (i8);                                                                             \\\n    } while (0)\n\n/**\n * \\brief           Check if input IP structure holds valid IP address\n * \\param[in]       ip: IP to check for valid address. It can be V4 or V6\n * \\return          `1` if IP valid, `0` otherwise\n */\nstatic inline uint8_t\nlwesp_ip_is_valid(const lwesp_ip_t* ip) {\n    if (ip == NULL) {\n        return 0;\n    }\n\n    /* Check address validity */\n    if ((ip->type == LWESP_IPTYPE_V4 && ip->addr.ip4.addr[0] > 0)\n#if LWESP_CFG_IPV6\n        || (ip->type == LWESP_IPTYPE_V6 && ip->addr.ip6.addr[0] > 0)\n#endif /* LWESP_CF_IPV6 */\n    ) {\n        return 1;\n    }\n    return 0;\n}\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           Port variable\n */\ntypedef uint16_t lwesp_port_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           MAC address\n */\ntypedef struct {\n    uint8_t mac[6]; /*!< MAC address */\n} lwesp_mac_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           SW version handle object.\n * \n * Format is (major << 24 | minor << 16 | patch << 8 | 0)\n */\ntypedef struct {\n    uint32_t version; /*!< Version in single hex format */\n} lwesp_sw_version_t;\n\n/**\n * \\ingroup         LWESP_AP\n * \\brief           Access point data structure\n */\ntypedef struct {\n    lwesp_ecn_t ecn;                      /*!< Encryption mode */\n    char ssid[LWESP_CFG_MAX_SSID_LENGTH]; /*!< Access point name */\n    int16_t rssi;                         /*!< Received signal strength indicator */\n    lwesp_mac_t mac;                      /*!< MAC physical address */\n    uint8_t ch;                           /*!< WiFi channel used on access point */\n\n#if LWESP_CFG_ACCESS_POINT_STRUCT_FULL_FIELDS || __DOXYGEN__\n    uint8_t scan_type;                 /*!< Scan type, 0 = active, 1 = passive */\n    uint16_t scan_time_min;            /*!< Minimum active scan time per channel in units of milliseconds */\n    uint16_t scan_time_max;            /*!< Maximum active scan time per channel in units of milliseconds */\n    int16_t freq_offset;               /*!< Frequency offset */\n    int16_t freq_cal;                  /*!< Frequency calibration */\n    lwesp_ap_cipher_t pairwise_cipher; /*!< Pairwise cipher mode */\n    lwesp_ap_cipher_t group_cipher;    /*!< Group cipher mode */\n#endif                                 /* LWESP_CFG_ACCESS_POINT_STRUCT_FULL_FIELDS || __DOXYGEN__ */\n    uint8_t bgn;                       /*!< Information about 802.11[b|g|n] support */\n    uint8_t wps;                       /*!< Status if WPS function is supported */\n} lwesp_ap_t;\n\n/**\n * \\ingroup         LWESP_AP\n * \\brief           Access point information on which station is connected to\n */\ntypedef struct {\n    char ssid[LWESP_CFG_MAX_SSID_LENGTH]; /*!< Access point name */\n    int16_t rssi;                         /*!< RSSI */\n    lwesp_mac_t mac;                      /*!< MAC address */\n    uint8_t ch;                           /*!< Channel information */\n} lwesp_sta_info_ap_t;\n\n/**\n * \\ingroup         LWESP_AP\n * \\brief           Soft access point data structure\n */\ntypedef struct {\n    char ssid[LWESP_CFG_MAX_SSID_LENGTH]; /*!< Access point name */\n    char pwd[LWESP_CFG_MAX_PWD_LENGTH];   /*!< Access point password/passphrase */\n    uint8_t ch;                           /*!< WiFi channel used on access point */\n    lwesp_ecn_t ecn;                      /*!< Encryption mode */\n    uint8_t max_cons;                     /*!< Maximum number of stations allowed connected to this AP */\n    uint8_t hidden;                       /*!< broadcast the SSID, 0 -- No, 1 -- Yes */\n} lwesp_ap_conf_t;\n\n/**\n * \\ingroup         LWESP_TYPES        \n * \\brief           Simple helper structure for application purpose\n * \n * User can define array of structure objects and set its\n * preferred WIFI options, then trying to iterate through\n * all and connect to first available\n * \n * \\note            This structure is not used by the LwESP library\n */\ntypedef struct {\n    const char* ssid; /*!< SSID to connect to */\n    const char* pass; /*!< Password for SSID */\n} lwesp_sta_ssid_pass_pair_t;\n\n/**\n * \\ingroup         LWESP_STA\n * \\brief           Station data structure\n */\ntypedef struct {\n    lwesp_ip_t ip;   /*!< IP address of connected station */\n    lwesp_mac_t mac; /*!< MAC address of connected station */\n} lwesp_sta_t;\n\n/**\n * \\brief           List of possible flash operations\n * \n * Values assigned to each enum are aligned with AT+SYSFLASH command\n */\ntypedef enum {\n    LWESP_FLASH_OP_ERASE = 0x00, /*!< Erases sector */\n    LWESP_FLASH_OP_WRITE = 0x01, /*!< Writes to sector */\n    LWESP_FLASH_OP_READ = 0x02,  /*!< Reads from sector */\n} lwesp_flash_operation_t;\n\n/**\n * \\brief           List of system flash partitions\n */\ntypedef enum {\n\n#define LWESP_FLASH_PARTITION(key, at_string) LWESP_FLASH_PARTITION_##key,\n#define LWESP_MFG_NAMESPACE(key, at_string)\n#include \"lwesp/lwesp_flash_partitions.h\"\n    LWESP_FLASH_PARTITION_END,\n} lwesp_flash_partition_t;\n\n/**\n * \\brief           List of manufacturing non-volatile memory user partitions\n */\ntypedef enum {\n\n#define LWESP_MFG_NAMESPACE(key, at_string) LWESP_MFG_NAMESPACE_##key,\n#define LWESP_FLASH_PARTITION(key, at_string)\n#include \"lwesp/lwesp_flash_partitions.h\"\n    LWESP_MFG_NAMESPACE_END,\n} lwesp_mfg_namespace_t;\n\n/**\n * \\brief           Manufacturing value types, currently supported\n */\ntypedef enum {\n    LWESP_MFG_VALTYPE_INVAL = 0,\n    LWESP_MFG_VALTYPE_U8 = 1,\n    LWESP_MFG_VALTYPE_I8 = 2,\n    LWESP_MFG_VALTYPE_U16 = 3,\n    LWESP_MFG_VALTYPE_I16 = 4,\n    LWESP_MFG_VALTYPE_U32 = 5,\n    LWESP_MFG_VALTYPE_I32 = 6,\n    LWESP_MFG_VALTYPE_STRING = 7,\n    LWESP_MFG_VALTYPE_BLOB = 8,\n    LWESP_MFG_VALTYPE_END,\n} lwesp_mfg_valtype_t;\n\n/**\n * \\brief           Check if specific value type is primitive type\n * \\param[in]       _valtype_: Value type from \\ref lwesp_mfg_valtype_t enumeration\n */\n#define LWESP_MFG_VALTYPE_IS_PRIM(_valtype_)                                                                           \\\n    ((_valtype_) == LWESP_MFG_VALTYPE_U8 || (_valtype_) == LWESP_MFG_VALTYPE_I8                                        \\\n     || (_valtype_) == LWESP_MFG_VALTYPE_U16 || (_valtype_) == LWESP_MFG_VALTYPE_I16                                   \\\n     || (_valtype_) == LWESP_MFG_VALTYPE_U32 || (_valtype_) == LWESP_MFG_VALTYPE_I32)\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           List of possible WiFi modes\n */\ntypedef enum {\n    LWESP_MODE_NONE = 0, /*!< Wifi RF IP disabled */\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n    LWESP_MODE_STA = 1, /*!< Set WiFi mode to station only */\n#endif                  /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n    LWESP_MODE_AP = 2, /*!< Set WiFi mode to access point only */\n#endif                 /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n#if LWESP_CFG_MODE_STATION_ACCESS_POINT || __DOXYGEN__\n    LWESP_MODE_STA_AP = 3, /*!< Set WiFi mode to station and access point */\n#endif                     /* (LWESP_CFG_MODE_STATION_ACCESS_POINT) || __DOXYGEN__ */\n} lwesp_mode_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           List of possible HTTP methods\n */\ntypedef enum {\n    LWESP_HTTP_METHOD_GET,     /*!< HTTP method GET */\n    LWESP_HTTP_METHOD_HEAD,    /*!< HTTP method HEAD */\n    LWESP_HTTP_METHOD_POST,    /*!< HTTP method POST */\n    LWESP_HTTP_METHOD_PUT,     /*!< HTTP method PUT */\n    LWESP_HTTP_METHOD_DELETE,  /*!< HTTP method DELETE */\n    LWESP_HTTP_METHOD_CONNECT, /*!< HTTP method CONNECT */\n    LWESP_HTTP_METHOD_OPTIONS, /*!< HTTP method OPTIONS */\n    LWESP_HTTP_METHOD_TRACE,   /*!< HTTP method TRACE */\n    LWESP_HTTP_METHOD_PATCH,   /*!< HTTP method PATCH */\n    LWESP_HTTP_METHOD_END,\n} lwesp_http_method_t;\n\n/**\n * \\ingroup         LWESP_CONN\n * \\brief           List of possible connection types\n */\ntypedef enum {\n    LWESP_CONN_TYPE_TCP, /*!< Connection type is TCP */\n    LWESP_CONN_TYPE_UDP, /*!< Connection type is UDP */\n    LWESP_CONN_TYPE_SSL, /*!< Connection type is SSL */\n#if LWESP_CFG_IPV6 || __DOXYGEN__\n    LWESP_CONN_TYPE_TCPV6, /*!< Connection type is TCP over IPv6 */\n    LWESP_CONN_TYPE_UDPV6, /*!< Connection type is UDP over IPv6 */\n    LWESP_CONN_TYPE_SSLV6, /*!< Connection type is SSL over IPv6 */\n#endif                     /* LWESP_CFG_IPV6 || __DOXYGEN__ */\n} lwesp_conn_type_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           API calls blocking or non-blocking type\n */\ntypedef enum {\n    LWESP_NON_BLOCKING = 0, /*!< Blocking call */\n    LWESP_BLOCKING = 1,     /*!< Non-blocking call */\n} lwesp_blocking_t;\n\n/* Forward declarations */\nstruct lwesp_evt;\nstruct lwesp_conn;\nstruct lwesp_pbuf;\n\n/**\n * \\ingroup         LWESP_CONN\n * \\brief           Pointer to \\ref lwesp_conn_t structure\n */\ntypedef struct lwesp_conn* lwesp_conn_p;\n\n/**\n * \\ingroup         LWESP_PBUF\n * \\brief           Pointer to \\ref lwesp_pbuf_t structure\n */\ntypedef struct lwesp_pbuf* lwesp_pbuf_p;\n\n/**\n * \\ingroup         LWESP_EVT\n * \\brief           Event function prototype\n * \\param[in]       evt: Callback event data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\ntypedef lwespr_t (*lwesp_evt_fn)(struct lwesp_evt* evt);\n\n/**\n * \\ingroup         LWESP_EVT\n * \\brief           List of possible callback types received to user\n */\ntypedef enum lwesp_evt_type_t {\n    LWESP_EVT_INIT_FINISH, /*!< Initialization has been finished at this point */\n\n    LWESP_EVT_RESET_DETECTED, /*!< Device reset detected */\n    LWESP_EVT_RESET,          /*!< Device reset operation finished */\n    LWESP_EVT_RESTORE,        /*!< Device restore operation finished */\n\n    LWESP_EVT_CMD_TIMEOUT, /*!< Timeout on command.\n                                                        When application receives this event,\n                                                        it may reset system as there was (maybe) a problem in device */\n\n    LWESP_EVT_DEVICE_PRESENT, /*!< Notification when device present status changes */\n\n    LWESP_EVT_AT_VERSION_NOT_SUPPORTED, /*!< Library does not support firmware version on ESP device. */\n\n    LWESP_EVT_CONN_RECV,   /*!< Connection data received */\n    LWESP_EVT_CONN_SEND,   /*!< Connection data send */\n    LWESP_EVT_CONN_ACTIVE, /*!< Connection just became active */\n    LWESP_EVT_CONN_ERROR,  /*!< Client connection start was not successful */\n    LWESP_EVT_CONN_CLOSE,  /*!< Connection close event. Check status if successful */\n    LWESP_EVT_CONN_POLL,   /*!< Poll for connection if there are any changes */\n\n    LWESP_EVT_SERVER, /*!< Server status changed */\n\n    LWESP_EVT_KEEP_ALIVE, /*!< Generic keep-alive event type, used as periodic timeout.\n                                                    Optionally enabled with \\ref LWESP_CFG_KEEP_ALIVE */\n\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n    LWESP_EVT_WIFI_CONNECTED,    /*!< Station just connected to access point.\n                                                    When received, station may not have yet valid IP hence new connections\n                                                    cannot be started in this mode */\n    LWESP_EVT_WIFI_GOT_IP,       /*!< Station has valid IP.\n                                                    When this event is received to application, ESP has got IP from access point,\n                                                    but no IP has been read from device and at this moment it is still being unknown to application.\n                                                    Stack will proceed with IP read from device and will later send \\ref LWESP_EVT_WIFI_IP_ACQUIRED event.\n\n                                                    Note: When IPv6 is enabled, this event may be called multiple times during single connection to access point,\n                                                    as device may report \"got IP\" several times.\n                                                    Application must take care when starting new conection from this event, not to start it multiple times */\n    LWESP_EVT_WIFI_DISCONNECTED, /*!< Station just disconnected from access point */\n    LWESP_EVT_WIFI_IP_ACQUIRED,  /*!< Station IP address acquired.\n                                                    At this point, valid IP address has been received from device.\n                                                    Application may use \\ref lwesp_sta_copy_ip function to read it */\n\n    LWESP_EVT_STA_LIST_AP, /*!< Station listed APs event */\n    LWESP_EVT_STA_JOIN_AP, /*!< Join to access point */\n    LWESP_EVT_STA_INFO_AP, /*!< Station AP info (name, mac, channel, rssi) */\n#endif                     /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n    LWESP_EVT_AP_CONNECTED_STA,    /*!< New station just connected to ESP's access point */\n    LWESP_EVT_AP_DISCONNECTED_STA, /*!< New station just disconnected from ESP's access point */\n    LWESP_EVT_AP_IP_STA,           /*!< New station just received IP from ESP's access point */\n#endif                             /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n#if LWESP_CFG_DNS || __DOXYGEN__\n    LWESP_EVT_DNS_HOSTBYNAME, /*!< DNS domain service finished */\n#endif                        /* LWESP_CFG_DNS || __DOXYGEN__ */\n#if LWESP_CFG_PING || __DOXYGEN__\n    LWESP_EVT_PING, /*!< PING service finished */\n#endif              /* LWESP_CFG_PING || __DOXYGEN__ */\n#if LWESP_CFG_WEBSERVER || __DOXYGEN__\n    LWESP_EVT_WEBSERVER, /*!< Web server events */\n#endif                   /* LWESP_CFG_WEBSERVER || __DOXYGEN__ */\n#if LWESP_CFG_SNTP || __DOXYGEN__\n    LWESP_EVT_SNTP_TIME_UPDATED, /*!< SNTP core inside ESP device has updated the time.\n                                        \\ref lwesp_sntp_* can be used to actually read the data from device.\n                                        This event is just a notification, but does not contain any data.\n                                        Alternatively, user can enable \\ref LWESP_CFG_SNTP_AUTO_READ_TIME_ON_UPDATE\n                                        to request data automatically when event is received */\n    LWESP_EVT_SNTP_TIME,         /*!< SNTP event with date and time */\n#endif                           /* LWESP_CFG_SNTP || __DOXYGEN__ */\n    LWESP_CFG_END,\n} lwesp_evt_type_t;\n\n/**\n * \\ingroup         LWESP_EVT\n * \\brief           Global callback structure to pass as parameter to callback function\n */\ntypedef struct lwesp_evt {\n    lwesp_evt_type_t type; /*!< Callback type */\n\n    union {\n        struct {\n            uint8_t forced; /*!< Set to `1` if reset forced by user */\n        } reset_detected;   /*!< Reset occurred. Use with \\ref LWESP_EVT_RESET_DETECTED event */\n\n        struct {\n            lwespr_t res; /*!< Reset operation result */\n        } reset;          /*!< Reset sequence finish. Use with \\ref LWESP_EVT_RESET event */\n\n        struct {\n            lwespr_t res; /*!< Restore operation result */\n        } restore;        /*!< Restore sequence finish. Use with \\ref LWESP_EVT_RESTORE event */\n\n        struct {\n            lwesp_conn_p conn; /*!< Connection where data were received */\n            lwesp_pbuf_p buff; /*!< Pointer to received data */\n        } conn_data_recv;      /*!< Network data received. Use with \\ref LWESP_EVT_CONN_RECV event */\n\n        struct {\n            lwesp_conn_p conn; /*!< Connection where data were sent */\n            size_t sent;       /*!< Number of bytes sent on connection */\n            lwespr_t res;      /*!< Send data result */\n        } conn_data_send;      /*!< Data send. Use with \\ref LWESP_EVT_CONN_SEND event */\n\n        struct {\n            const char* host;       /*!< Host to use for connection */\n            lwesp_port_t port;      /*!< Remote port used for connection */\n            lwesp_conn_type_t type; /*!< Connection type */\n            void* arg;              /*!< Connection user argument */\n            lwespr_t err;           /*!< Error value */\n        } conn_error;               /*!< Client connection start error. Use with \\ref LWESP_EVT_CONN_ERROR event */\n\n        struct {\n            lwesp_conn_p conn; /*!< Pointer to connection */\n            uint8_t client;    /*!< Set to 1 if connection is/was client mode */\n            uint8_t forced;    /*!< Set to 1 if connection action was forced\n                                                        when active: 1 = CLIENT, 0 = SERVER\n                                                        when closed, 1 = CMD, 0 = REMOTE */\n            lwespr_t res;      /*!< Result of close event.\n                                                        Set to \\ref lwespOK on success */\n        } conn_active_close;   /*!< Process active and closed statuses at the same time.\n                                                        Use with \\ref LWESP_EVT_CONN_ACTIVE or\n                                                        \\ref LWESP_EVT_CONN_CLOSE events */\n\n        struct {\n            lwesp_conn_p conn; /*!< Set connection pointer */\n        } conn_poll;           /*!< Polling active connection to check for timeouts.\n                                                        Use with \\ref LWESP_EVT_CONN_POLL event */\n\n        struct {\n            lwespr_t res;      /*!< Status of command */\n            uint8_t en;        /*!< Status to enable/disable server */\n            lwesp_port_t port; /*!< Server port number */\n        } server;              /*!< Server change event. Use with \\ref LWESP_EVT_SERVER event */\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n        struct {\n            lwespr_t res;    /*!< Result of command */\n            lwesp_ap_t* aps; /*!< Pointer to access points */\n            size_t len;      /*!< Number of access points found */\n        } sta_list_ap;       /*!< Station list access points. Use with \\ref LWESP_EVT_STA_LIST_AP event */\n\n        struct {\n            lwespr_t res; /*!< Result of command */\n        } sta_join_ap;    /*!< Join to access point. Use with \\ref LWESP_EVT_STA_JOIN_AP event */\n\n        struct {\n            lwesp_sta_info_ap_t* info; /*!< AP info of current station */\n            lwespr_t res;              /*!< Result of command */\n        } sta_info_ap;                 /*!< Current AP informations. Use with \\ref LWESP_EVT_STA_INFO_AP event */\n#endif                                 /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n        struct {\n            lwesp_mac_t* mac;  /*!< Station MAC address */\n        } ap_conn_disconn_sta; /*!< A new station connected or disconnected to\n                                                        ESP's access point. Use with\n                                                        \\ref LWESP_EVT_AP_CONNECTED_STA or\n                                                        \\ref LWESP_EVT_AP_DISCONNECTED_STA events */\n\n        struct {\n            lwesp_mac_t* mac; /*!< Station MAC address */\n            lwesp_ip_t* ip;   /*!< Station IP address */\n        } ap_ip_sta;          /*!< Station got IP address from ESP's access point.\n                                                        Use with \\ref LWESP_EVT_AP_IP_STA event */\n#endif                        /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n#if LWESP_CFG_DNS || __DOXYGEN__\n        struct {\n            lwespr_t res;     /*!< Result of command */\n            const char* host; /*!< Host name for DNS lookup */\n            lwesp_ip_t* ip;   /*!< Pointer to IP result */\n        } dns_hostbyname;     /*!< DNS domain service finished.\n                                                        Use with \\ref LWESP_EVT_DNS_HOSTBYNAME event */\n#endif                        /* LWESP_CFG_DNS || __DOXYGEN__ */\n#if LWESP_CFG_PING || __DOXYGEN__\n        struct {\n            lwespr_t res;     /*!< Result of command */\n            const char* host; /*!< Host name for ping */\n            uint32_t time;    /*!< Time required for ping. Valid only if operation succedded */\n        } ping;               /*!< Ping finished. Use with \\ref LWESP_EVT_PING event */\n#endif                        /* LWESP_CFG_PING || __DOXYGEN__ */\n#if LWESP_CFG_SNTP || __DOXYGEN__\n        struct {\n            lwespr_t res;        /*!< Result of command */\n            const struct tm* dt; /*!< Pointer to datetime structure */\n        } cip_sntp_time;         /*!< SNTP time finished. Use with \\ref LWESP_EVT_SNTP_TIME event */\n#endif                           /* LWESP_CFG_SNTP || __DOXYGEN__ */\n\n#if LWESP_CFG_WEBSERVER || __DOXYGEN__\n        struct {\n            uint8_t code; /*!< Result of command */\n        } ws_status;      /*!< Ping finished. Use with \\ref LWESP_EVT_PING event */\n#endif                    /* LWESP_CFG_WEBSERVER || __DOXYGEN__ */\n    } evt;                /*!< Callback event union */\n} lwesp_evt_t;\n\n#define LWESP_SIZET_MAX ((size_t)(-1)) /*!< Maximal value of size_t variable type */\n\n/**\n * \\ingroup         LWESP_LL\n * \\brief           Function prototype for AT output data\n * \\param[in]       data: Pointer to data to send. This parameter can be set to `NULL`,\n *                      indicating to the low-level that (if used) DMA could be started\n *                      to transmit data to the device\n * \\param[in]       len: Number of bytes to send. This parameter can be set to `0`\n *                      to indicate that internal buffer can be flushed to stream.\n *                      This is implementation defined and feature might be ignored\n * \\return          Number of bytes sent\n */\ntypedef size_t (*lwesp_ll_send_fn)(const void* data, size_t len);\n\n/**\n * \\ingroup         LWESP_LL\n * \\brief           Function prototype for hardware reset of ESP device\n * \\param[in]       state: State indicating reset. When set to `1`, reset must be active (usually pin active low),\n *                      or set to `0` when reset is cleared\n * \\return          `1` on successful action, `0` otherwise\n */\ntypedef uint8_t (*lwesp_ll_reset_fn)(uint8_t state);\n\n/**\n * \\ingroup         LWESP_LL\n * \\brief           Low level user specific functions\n */\ntypedef struct {\n    lwesp_ll_send_fn send_fn;   /*!< Callback function to transmit data */\n    lwesp_ll_reset_fn reset_fn; /*!< Reset callback function */\n\n    struct {\n        uint32_t baudrate; /*!< UART baudrate value */\n    } uart;                /*!< UART communication parameters */\n} lwesp_ll_t;\n\n/**\n * \\ingroup         LWESP_TIMEOUT\n * \\brief           Timeout callback function prototype\n * \\param[in]       arg: Custom user argument\n */\ntypedef void (*lwesp_timeout_fn)(void* arg);\n\n/**\n * \\ingroup         LWESP_TIMEOUT\n * \\brief           Timeout structure\n */\ntypedef struct lwesp_timeout {\n    struct lwesp_timeout* next; /*!< Pointer to next timeout entry */\n    uint32_t time;              /*!< Time difference from previous entry */\n    void* arg;                  /*!< Argument to pass to callback function */\n    lwesp_timeout_fn fn;        /*!< Callback function for timeout */\n} lwesp_timeout_t;\n\n/**\n * \\ingroup         LWESP_BUFF\n * \\brief           Buffer structure\n */\ntypedef struct {\n    uint8_t* buff; /*!< Pointer to buffer data.\n                                                    Buffer is considered initialized when `buff != NULL` */\n    size_t size;   /*!< Size of buffer data. Size of actual buffer is\n                                                        `1` byte less than this value */\n    size_t r;      /*!< Next read pointer. Buffer is considered empty\n                                                        when `r == w` and full when `w == r - 1` */\n    size_t w;      /*!< Next write pointer. Buffer is considered empty\n                                                        when `r == w` and full when `w == r - 1` */\n} lwesp_buff_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           Linear buffer structure\n */\ntypedef struct {\n    uint8_t* buff; /*!< Pointer to buffer data array */\n    size_t len;    /*!< Length of buffer array */\n    size_t ptr;    /*!< Current buffer pointer */\n} lwesp_linbuff_t;\n\n/**\n * \\ingroup         LWESP_TYPES\n * \\brief           Function declaration for API function command event callback function\n * \\param[in]       res: Operation result, member of \\ref lwespr_t enumeration\n * \\param[in]       arg: Custom user argument\n */\ntypedef void (*lwesp_api_cmd_evt_fn)(lwespr_t res, void* arg);\n\n/**\n * \\ingroup         LWESP_CONN\n * \\brief           Connection start structure, used to start the connection in extended mode\n */\ntypedef struct {\n    lwesp_conn_type_t type;   /*!< Connection type */\n    const char* remote_host;  /*!< Host name or IP address in string format */\n    lwesp_port_t remote_port; /*!< Remote server port */\n    const char* local_ip;     /*!< Local IP. Optional parameter, set to NULL if not used (most cases) */\n\n    union {\n        struct {\n            uint16_t keep_alive; /*!< Keep alive parameter for TCP/SSL connection in units of seconds.\n                                        Value can be between `0 - 7200` where `0` means no keep alive */\n#if 0\n            uint8_t auth_mode;   /*!< SSL authentication mode */\n            uint8_t pki_number;  /*!< SSL PKI number */\n            uint8_t ca_number;   /*!< SSL CA number */\n#endif\n        } tcp_ssl; /*!< TCP/SSL specific features */\n\n        struct {\n            lwesp_port_t local_port; /*!< Custom local port for UDP */\n            uint8_t\n                mode; /*!< UDP mode. Set to `0` by default. Check ESP AT commands instruction set for more info when needed */\n        } udp;        /*!< UDP specific features */\n    } ext;            /*!< Extended support union */\n} lwesp_conn_start_t;\n\n/**\n * \\ingroup         LWESP_UNICODE\n * \\brief           Unicode support structure\n */\ntypedef struct {\n    uint8_t ch[4]; /*!< UTF-8 max characters */\n    uint8_t t;     /*!< Total expected length in UTF-8 sequence */\n    uint8_t r;     /*!< Remaining bytes in UTF-8 sequence */\n    lwespr_t res;  /*!< Current result of processing */\n} lwesp_unicode_t;\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_DEFS_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_unicode.h",
    "content": "/**\n * \\file            lwesp_unicode.h\n * \\brief           Unicode support\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_UNICODE_HDR_H\n#define LWESP_UNICODE_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_UNICODE Unicode manager\n * \\brief           Unicode support manager\n * \\{\n */\n\nlwespr_t lwespi_unicode_decode(lwesp_unicode_t* uni, uint8_t ch);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_UNICODE_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_utils.h",
    "content": "/**\n * \\file            lwesp_utils.h\n * \\brief           Utilities\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_UTILS_HDR_H\n#define LWESP_UTILS_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_UTILS Utilities\n * \\brief           Utilities\n * \\{\n */\n\n/**\n * \\brief           Assert an input parameter if in valid range\n * \\note            Since this is a macro, it may only be used on a functions where return status is of type \\ref lwespr_t enumeration\n * \\param[in]       c: Condition to test\n */\n#define LWESP_ASSERT(c)                                                                                                \\\n    do {                                                                                                               \\\n        if (!(c)) {                                                                                                    \\\n            LWESP_DEBUGF(LWESP_CFG_DBG_ASSERT, \"Assert failed in file %s on line %d: %s\\r\\n\", __FILE__, (int)__LINE__, \\\n                         #c);                                                                                          \\\n            return lwespERRPAR;                                                                                        \\\n        }                                                                                                              \\\n    } while (0)\n\n/**\n * \\brief           Assert an input parameter if in valid range, return 0 from function on failure\n * \\note            Since this is a macro, it may only be used on a functions where return status is of type \\ref lwespr_t enumeration\n * \\param[in]       c: Condition to test\n */\n#define LWESP_ASSERT0(c)                                                                                               \\\n    do {                                                                                                               \\\n        if (!(c)) {                                                                                                    \\\n            LWESP_DEBUGF(LWESP_CFG_DBG_ASSERT, \"Assert failed in file %s on line %d: %s\\r\\n\", __FILE__, (int)__LINE__, \\\n                         #c);                                                                                          \\\n            return 0;                                                                                                  \\\n        }                                                                                                              \\\n    } while (0)\n\n/**\n * \\brief           Align `x` value to specific number of bytes, provided by \\ref LWESP_CFG_MEM_ALIGNMENT configuration\n * \\param[in]       x: Input value to align\n * \\return          Input value aligned to specific number of bytes\n * \\hideinitializer\n */\n#define LWESP_MEM_ALIGN(x)                ((x + (LWESP_CFG_MEM_ALIGNMENT - 1)) & ~(LWESP_CFG_MEM_ALIGNMENT - 1))\n\n/**\n * \\brief           Get minimal value between `x` and `y` inputs\n * \\param[in]       x: First input to test\n * \\param[in]       y: Second input to test\n * \\return          Minimal value between `x` and `y` parameters\n * \\hideinitializer\n */\n#define LWESP_MIN(x, y)                   ((x) < (y) ? (x) : (y))\n\n/**\n * \\brief           Get maximal value between `x` and `y` inputs\n * \\param[in]       x: First input to test\n * \\param[in]       y: Second input to test\n * \\return          Maximal value between `x` and `y` parameters\n * \\hideinitializer\n */\n#define LWESP_MAX(x, y)                   ((x) > (y) ? (x) : (y))\n\n/**\n * \\brief           Get size of statically declared array\n * \\param[in]       x: Input array\n * \\return          Number of array elements\n * \\hideinitializer\n */\n#define LWESP_ARRAYSIZE(x)                (sizeof(x) / sizeof((x)[0]))\n\n/**\n * \\brief           Unused argument in a function call\n * \\note            Use this on all parameters in a function which are not used to prevent\n *                  compiler warnings complaining about \"unused variables\"\n * \\param[in]       x: Variable which is not used\n * \\hideinitializer\n */\n#define LWESP_UNUSED(x)                   ((void)(x))\n\n/**\n * \\brief           Get input value casted to `unsigned 32-bit` value\n * \\param[in]       x: Input value\n * \\hideinitializer\n */\n#define LWESP_U32(x)                      ((uint32_t)(x))\n\n/**\n * \\brief           Get input value casted to `unsigned 16-bit` value\n * \\param[in]       x: Input value\n * \\hideinitializer\n */\n#define LWESP_U16(x)                      ((uint16_t)(x))\n\n/**\n * \\brief           Get input value casted to `unsigned 8-bit` value\n * \\param[in]       x: Input value\n * \\hideinitializer\n */\n#define LWESP_U8(x)                       ((uint8_t)(x))\n\n/**\n * \\brief           Get input value casted to `signed 32-bit` value\n * \\param[in]       x: Input value\n * \\hideinitializer\n */\n#define LWESP_I32(x)                      ((int32_t)(x))\n\n/**\n * \\brief           Get input value casted to `signed 16-bit` value\n * \\param[in]       x: Input value\n * \\hideinitializer\n */\n#define LWESP_I16(x)                      ((int16_t)(x))\n\n/**\n * \\brief           Get input value casted to `signed 8-bit` value\n * \\param[in]       x: Input value\n * \\hideinitializer\n */\n#define LWESP_I8(x)                       ((int8_t)(x))\n\n/**\n * \\brief           Get input value casted to `size_t` value\n * \\param[in]       x: Input value\n * \\hideinitializer\n */\n#define LWESP_SZ(x)                       ((size_t)(x))\n\n/**\n * \\brief           Convert `unsigned 32-bit` number to string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_u32_to_str(num, out)        lwesp_u32_to_gen_str(LWESP_U32(num), (out), 0, 0)\n\n/**\n * \\brief           Convert `unsigned 32-bit` number to HEX string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\param[in]       w: Width of output string.\n *                      When number is shorter than width, leading `0` characters will apply\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_u32_to_hex_str(num, out, w) lwesp_u32_to_gen_str(LWESP_U32(num), (out), 1, (w))\n\n/**\n * \\brief           Convert `signed 32-bit` number to string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_i32_to_str(num, out)        lwesp_i32_to_gen_str(LWESP_I32(num), (out))\n\n/**\n * \\brief           Convert `unsigned 16-bit` number to string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_u16_to_str(num, out)        lwesp_u32_to_gen_str(LWESP_U32(LWESP_U16(num)), (out), 0, 0)\n\n/**\n * \\brief           Convert `unsigned 16-bit` number to HEX string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\param[in]       w: Width of output string.\n *                      When number is shorter than width, leading `0` characters will apply.\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_u16_to_hex_str(num, out, w) lwesp_u32_to_gen_str(LWESP_U32(LWESP_U16(num)), (out), 1, (w))\n\n/**\n * \\brief           Convert `signed 16-bit` number to string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_i16_to_str(num, out)        lwesp_i32_to_gen_str(LWESP_I32(LWESP_I16(num)), (out))\n\n/**\n * \\brief           Convert `unsigned 8-bit` number to string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_u8_to_str(num, out)         lwesp_u32_to_gen_str(LWESP_U32(LWESP_U8(num)), (out), 0, 0)\n\n/**\n * \\brief           Convert `unsigned 16-bit` number to HEX string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\param[in]       w: Width of output string.\n *                      When number is shorter than width, leading `0` characters will apply.\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_u8_to_hex_str(num, out, w)  lwesp_u32_to_gen_str(LWESP_U32(LWESP_U8(num)), (out), 1, (w))\n\n/**\n * \\brief           Convert `signed 8-bit` number to string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\return          Pointer to output variable\n * \\hideinitializer\n */\n#define lwesp_i8_to_str(num, out)         lwesp_i32_to_gen_str(LWESP_I32(LWESP_I8(num)), (out))\n\nchar* lwesp_u32_to_gen_str(uint32_t num, char* out, uint8_t is_hex, uint8_t padding);\nchar* lwesp_i32_to_gen_str(int32_t num, char* out);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_UTILITIES_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_webserver.h",
    "content": "/**\n * \\file            lwesp_webserver.h\n * \\brief           Web Server API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Neo Xiong <xiongyu0523@gmail.com>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_WEBSERVER_HDR_H\n#define LWESP_WEBSERVER_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_WEBSERVER Web Server API\n * \\brief           Web Server function\n * \\{\n */\n\nlwespr_t lwesp_set_webserver(uint8_t en, lwesp_port_t port, uint16_t timeout, const lwesp_api_cmd_evt_fn evt_fn,\n                             void* const evt_arg, const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_WEBSERVER_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/lwesp/lwesp_wps.h",
    "content": "/**\n * \\file            lwesp_wps.h\n * \\brief           WPS API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_WPS_HDR_H\n#define LWESP_WPS_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\ingroup         LWESP\n * \\defgroup        LWESP_WPS WPS\n * \\brief           WPS function on ESP device\n * \\{\n */\n\nlwespr_t lwesp_wps_set_config(uint8_t en, lwesp_ecn_t min_ecn, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                              const uint32_t blocking);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_WPS_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/system/lwesp_ll.h",
    "content": "/**\n * \\file            lwesp_ll.h\n * \\brief           Low-level communication implementation\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_LL_HDR_H\n#define LWESP_LL_HDR_H\n\n#include \"lwesp/lwesp_types.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\defgroup        LWESP_LL Low-level functions\n * \\brief           Low-level communication functions\n * \\{\n */\n\n/**\n * \\brief           Callback function called from initialization process\n *\n * \\note            This function may be called multiple times if AT baudrate is changed from application.\n *                  It is important that every configuration except AT baudrate is configured only once!\n *\n * \\note            This function may be called from different threads in ESP stack when using OS.\n *                  When \\ref LWESP_CFG_INPUT_USE_PROCESS is set to `1`, this function may be called from user UART thread.\n *\n * \\param[in,out]   ll: Pointer to \\ref lwesp_ll_t structure to fill data for communication functions\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t lwesp_ll_init(lwesp_ll_t* ll);\n\n/**\n * \\brief           Callback function to de-init low-level communication part\n * \\param[in,out]   ll: Pointer to \\ref lwesp_ll_t structure to fill data for communication functions\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t lwesp_ll_deinit(lwesp_ll_t* ll);\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_LL_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/system/lwesp_sys.h",
    "content": "/**\n * \\file            lwesp_sys.h\n * \\brief           Main system include file which decides later include file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_MAIN_SYS_HDR_H\n#define LWESP_MAIN_SYS_HDR_H\n\n#include <stdint.h>\n#include \"lwesp/lwesp_opt.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\defgroup        LWESP_SYS System functions\n * \\brief           System based function for OS management, timings, etc\n * \\{\n */\n\n/**\n * \\brief           Thread function prototype\n */\ntypedef void (*lwesp_sys_thread_fn)(void*);\n\n#if __DOXYGEN__\n/**\n * \\brief           System mutex type\n *\n * It is used by middleware as base type of mutex.\n */\ntypedef void* lwesp_sys_mutex_t;\n\n/**\n * \\brief           System semaphore type\n *\n * It is used by middleware as base type of mutex.\n */\ntypedef void* lwesp_sys_sem_t;\n\n/**\n * \\brief           System message queue type\n *\n * It is used by middleware as base type of mutex.\n */\ntypedef void* lwesp_sys_mbox_t;\n\n/**\n * \\brief           System thread ID type\n */\ntypedef void* lwesp_sys_thread_t;\n\n/**\n * \\brief           System thread priority type\n *\n * It is used as priority type for system function,\n * to start new threads by middleware.\n */\ntypedef int lwesp_sys_thread_prio_t;\n\n/**\n * \\brief           Mutex invalid value\n *\n * Value assigned to \\ref lwesp_sys_mutex_t type when it is not valid.\n */\n#define LWESP_SYS_MUTEX_NULL  ((lwesp_sys_mutex_t)0)\n\n/**\n * \\brief           Semaphore invalid value\n *\n * Value assigned to \\ref lwesp_sys_sem_t type when it is not valid.\n */\n#define LWESP_SYS_SEM_NULL    ((lwesp_sys_sem_t)0)\n\n/**\n * \\brief           Message box invalid value\n *\n * Value assigned to \\ref lwesp_sys_mbox_t type when it is not valid.\n */\n#define LWESP_SYS_MBOX_NULL   ((lwesp_sys_mbox_t)0)\n\n/**\n * \\brief           OS timeout value\n *\n * Value returned by operating system functions (mutex wait, sem wait, mbox wait)\n * when it returns timeout and does not give valid value to application\n */\n#define LWESP_SYS_TIMEOUT     ((uint32_t)osWaitForever)\n\n/**\n * \\brief           Default thread priority value used by middleware to start built-in threads\n *\n * Threads can well operate with normal (default) priority and do not require\n * any special feature in terms of priority for proper operation.\n */\n#define LWESP_SYS_THREAD_PRIO (osPriorityNormal)\n\n/**\n * \\brief           Stack size in units of bytes for system threads\n *\n * It is used as default stack size for all built-in threads.\n */\n#define LWESP_SYS_THREAD_SS   (1024)\n#else\n/* Include system port file from portable folder */\n#include \"lwesp_sys_port.h\"\n#endif /* __DOXYGEN__ */\n\n/**\n * \\anchor          LWESP_SYS_CORE\n * \\name            Main\n */\n\n/**\n * \\brief           Init system dependant parameters\n *\n * After this function is called,\n * all other system functions must be fully ready.\n *\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_init(void);\n\n/**\n * \\brief           Get current time in units of milliseconds\n * \\return          Current time in units of milliseconds\n */\nuint32_t lwesp_sys_now(void);\n\n/**\n * \\brief           Protect middleware core\n *\n * Stack protection must support recursive mode.\n * This function may be called multiple times,\n * even if access has been granted before.\n *\n * \\note            Most operating systems support recursive mutexes.\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_protect(void);\n\n/**\n * \\brief           Unprotect middleware core\n *\n * This function must follow number of calls of \\ref lwesp_sys_protect\n * and unlock access only when counter reached back zero.\n *\n * \\note            Most operating systems support recursive mutexes.\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_unprotect(void);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_SYS_MUTEX\n * \\name            Mutex\n */\n\n/**\n * \\brief           Create new recursive mutex\n * \\note            Recursive mutex has to be created as it may be locked multiple times before unlocked\n * \\param[out]      p: Pointer to mutex structure to allocate\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mutex_create(lwesp_sys_mutex_t* p);\n\n/**\n * \\brief           Delete recursive mutex from system\n * \\param[in]       p: Pointer to mutex structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mutex_delete(lwesp_sys_mutex_t* p);\n\n/**\n * \\brief           Lock recursive mutex, wait forever to lock\n * \\param[in]       p: Pointer to mutex structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mutex_lock(lwesp_sys_mutex_t* p);\n\n/**\n * \\brief           Unlock recursive mutex\n * \\param[in]       p: Pointer to mutex structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mutex_unlock(lwesp_sys_mutex_t* p);\n\n/**\n * \\brief           Check if mutex structure is valid system\n * \\param[in]       p: Pointer to mutex structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mutex_isvalid(lwesp_sys_mutex_t* p);\n\n/**\n * \\brief           Set recursive mutex structure as invalid\n * \\param[in]       p: Pointer to mutex structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mutex_invalid(lwesp_sys_mutex_t* p);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_SYS_SEM\n * \\name            Semaphores\n */\n\n/**\n * \\brief           Create a new binary semaphore and set initial state\n * \\note            Semaphore may only have `1` token available\n * \\param[out]      p: Pointer to semaphore structure to fill with result\n * \\param[in]       cnt: Count indicating default semaphore state:\n *                     `0`: Take semaphore token immediately\n *                     `1`: Keep token available\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_sem_create(lwesp_sys_sem_t* p, uint8_t cnt);\n\n/**\n * \\brief           Delete binary semaphore\n * \\param[in]       p: Pointer to semaphore structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_sem_delete(lwesp_sys_sem_t* p);\n\n/**\n * \\brief           Wait for semaphore to be available\n * \\param[in]       p: Pointer to semaphore structure\n * \\param[in]       timeout: Timeout to wait in milliseconds. When `0` is applied, wait forever\n * \\return          Number of milliseconds waited for semaphore to become available or\n *                      \\ref LWESP_SYS_TIMEOUT if not available within given time\n */\nuint32_t lwesp_sys_sem_wait(lwesp_sys_sem_t* p, uint32_t timeout);\n\n/**\n * \\brief           Release semaphore\n * \\param[in]       p: Pointer to semaphore structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_sem_release(lwesp_sys_sem_t* p);\n\n/**\n * \\brief           Check if semaphore is valid\n * \\param[in]       p: Pointer to semaphore structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_sem_isvalid(lwesp_sys_sem_t* p);\n\n/**\n * \\brief           Invalid semaphore\n * \\param[in]       p: Pointer to semaphore structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_sem_invalid(lwesp_sys_sem_t* p);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_SYS_MBOX\n * \\name            Message queues\n */\n\n/**\n * \\brief           Create a new message queue with entry type of `void *`\n * \\param[out]      b: Pointer to message queue structure\n * \\param[in]       size: Number of entries for message queue to hold\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mbox_create(lwesp_sys_mbox_t* b, size_t size);\n\n/**\n * \\brief           Delete message queue\n * \\param[in]       b: Pointer to message queue structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mbox_delete(lwesp_sys_mbox_t* b);\n\n/**\n * \\brief           Put a new entry to message queue and wait until memory available\n * \\param[in]       b: Pointer to message queue structure\n * \\param[in]       m: Pointer to entry to insert to message queue\n * \\return          Time in units of milliseconds needed to put a message to queue\n */\nuint32_t lwesp_sys_mbox_put(lwesp_sys_mbox_t* b, void* m);\n\n/**\n * \\brief           Get a new entry from message queue with timeout\n * \\param[in]       b: Pointer to message queue structure\n * \\param[in]       m: Pointer to pointer to result to save value from message queue to\n * \\param[in]       timeout: Maximal timeout to wait for new message. When `0` is applied, wait for unlimited time\n * \\return          Time in units of milliseconds needed to put a message to queue\n *                      or \\ref LWESP_SYS_TIMEOUT if it was not successful\n */\nuint32_t lwesp_sys_mbox_get(lwesp_sys_mbox_t* b, void** m, uint32_t timeout);\n\n/**\n * \\brief           Put a new entry to message queue without timeout (now or fail)\n * \\param[in]       b: Pointer to message queue structure\n * \\param[in]       m: Pointer to message to save to queue\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mbox_putnow(lwesp_sys_mbox_t* b, void* m);\n\n/**\n * \\brief           Get an entry from message queue immediately\n * \\param[in]       b: Pointer to message queue structure\n * \\param[in]       m: Pointer to pointer to result to save value from message queue to\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mbox_getnow(lwesp_sys_mbox_t* b, void** m);\n\n/**\n * \\brief           Check if message queue is valid\n * \\param[in]       b: Pointer to message queue structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mbox_isvalid(lwesp_sys_mbox_t* b);\n\n/**\n * \\brief           Invalid message queue\n * \\param[in]       b: Pointer to message queue structure\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_mbox_invalid(lwesp_sys_mbox_t* b);\n\n/**\n * \\}\n */\n\n/**\n * \\anchor          LWESP_SYS_THREAD\n * \\name            Threads\n */\n\n/**\n * \\brief           Create a new thread\n * \\param[out]      t: Pointer to thread identifier if create was successful.\n *                     It may be set to `NULL`\n * \\param[in]       name: Name of a new thread\n * \\param[in]       thread_func: Thread function to use as thread body\n * \\param[in]       arg: Thread function argument\n * \\param[in]       stack_size: Size of thread stack in uints of bytes. If set to 0, reserve default stack size\n * \\param[in]       prio: Thread priority\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_thread_create(lwesp_sys_thread_t* t, const char* name, lwesp_sys_thread_fn thread_func,\n                                void* const arg, size_t stack_size, lwesp_sys_thread_prio_t prio);\n\n/**\n * \\brief           Terminate thread (shut it down and remove)\n * \\param[in]       t: Pointer to thread handle to terminate.\n *                      If set to `NULL`, terminate current thread (thread from where function is called)\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_thread_terminate(lwesp_sys_thread_t* t);\n\n/**\n * \\brief           Yield current thread\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t lwesp_sys_thread_yield(void);\n\n/**\n * \\}\n */\n\n/**\n * \\}\n */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_MAIN_SYS_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/system/port/cmsis_os/lwesp_sys_port.h",
    "content": "/**\n * \\file            lwesp_sys_port.h\n * \\brief           CMSIS-OS based system file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_SYSTEM_PORT_HDR_H\n#define LWESP_SYSTEM_PORT_HDR_H\n\n#include <stdint.h>\n#include <stdlib.h>\n#include \"cmsis_os.h\"\n#include \"lwesp/lwesp_opt.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#if LWESP_CFG_OS && !__DOXYGEN__\n\ntypedef osMutexId_t lwesp_sys_mutex_t;\ntypedef osSemaphoreId_t lwesp_sys_sem_t;\ntypedef osMessageQueueId_t lwesp_sys_mbox_t;\ntypedef osThreadId_t lwesp_sys_thread_t;\ntypedef osPriority_t lwesp_sys_thread_prio_t;\n\n#define LWESP_SYS_MUTEX_NULL  ((lwesp_sys_mutex_t)0)\n#define LWESP_SYS_SEM_NULL    ((lwesp_sys_sem_t)0)\n#define LWESP_SYS_MBOX_NULL   ((lwesp_sys_mbox_t)0)\n#define LWESP_SYS_TIMEOUT     ((uint32_t)osWaitForever)\n#define LWESP_SYS_THREAD_PRIO (osPriorityNormal)\n#define LWESP_SYS_THREAD_SS   (1536)\n\n#endif /* LWESP_CFG_OS && !__DOXYGEN__ */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_SYSTEM_PORT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/system/port/freertos/lwesp_sys_port.h",
    "content": "/**\n * \\file            lwesp_sys_port.h\n * \\brief           FreeRTOS native port\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Adrian Carpenter (FreeRTOS port)\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_SYSTEM_PORT_HDR_H\n#define LWESP_SYSTEM_PORT_HDR_H\n\n#include <stdint.h>\n#include <stdlib.h>\n#include \"FreeRTOS.h\"\n#include \"lwesp/lwesp_opt.h\"\n#include \"semphr.h\"\n#include \"task.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#if LWESP_CFG_OS && !__DOXYGEN__\n\ntypedef SemaphoreHandle_t lwesp_sys_mutex_t;\ntypedef SemaphoreHandle_t lwesp_sys_sem_t;\ntypedef QueueHandle_t lwesp_sys_mbox_t;\ntypedef TaskHandle_t lwesp_sys_thread_t;\ntypedef UBaseType_t lwesp_sys_thread_prio_t;\n\n#define LWESP_SYS_MUTEX_NULL  ((SemaphoreHandle_t)0)\n#define LWESP_SYS_SEM_NULL    ((SemaphoreHandle_t)0)\n#define LWESP_SYS_MBOX_NULL   ((QueueHandle_t)0)\n#define LWESP_SYS_TIMEOUT     ((TickType_t)portMAX_DELAY)\n#define LWESP_SYS_THREAD_PRIO (configMAX_PRIORITIES - 1)\n#define LWESP_SYS_THREAD_SS   (1024)\n\n#endif /* LWESP_CFG_OS && !__DOXYGEN__ */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_SYSTEM_PORT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/system/port/posix/lwesp_sys_port.h",
    "content": "/**\n * \\file            lwesp_sys_port.h\n * \\brief           POSIX based system file implementation\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          imi415 <imi415.public@gmail.com>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_SYSTEM_PORT_HDR_H\n#define LWESP_SYSTEM_PORT_HDR_H\n\n#include <pthread.h>\n#include <semaphore.h>\n#include <stdint.h>\n#include <stdlib.h>\n#include \"lwesp/lwesp_opt.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#if LWESP_CFG_OS && !__DOXYGEN__\n\ntypedef pthread_mutex_t* lwesp_sys_mutex_t;\ntypedef sem_t* lwesp_sys_sem_t;\ntypedef void* lwesp_sys_mbox_t;\ntypedef pthread_t* lwesp_sys_thread_t;\ntypedef int lwesp_sys_thread_prio_t;\n\n#define LWESP_SYS_MBOX_NULL   (0)\n#define LWESP_SYS_TIMEOUT     (0xFFFFFFFF)\n#define LWESP_SYS_THREAD_PRIO (0)\n#define LWESP_SYS_THREAD_SS   (1024)\n\n#endif /* LWESP_CFG_OS && !__DOXYGEN__ */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_SYSTEM_PORT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/system/port/threadx/lwesp_sys_port.h",
    "content": "/**\n * \\file            lwesp_sys_port.h\n * \\brief           ThreadX native port\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Neo Xiong <xiongyu0523@gmail.com>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_SYSTEM_PORT_HDR_H\n#define LWESP_SYSTEM_PORT_HDR_H\n\n#include <stdint.h>\n#include <stdlib.h>\n#include \"lwesp/lwesp_opt.h\"\n#include \"tx_api.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#if LWESP_CFG_OS && !__DOXYGEN__\n\ntypedef TX_MUTEX lwesp_sys_mutex_t;\ntypedef TX_SEMAPHORE lwesp_sys_sem_t;\ntypedef TX_QUEUE lwesp_sys_mbox_t;\ntypedef TX_THREAD lwesp_sys_thread_t;\ntypedef UINT lwesp_sys_thread_prio_t;\n\n#define LWESP_SYS_TIMEOUT     TX_WAIT_FOREVER\n#define LWESP_SYS_THREAD_PRIO (TX_MAX_PRIORITIES - 1)\n#define LWESP_SYS_THREAD_SS   1024\n\n#endif /* LWESP_CFG_OS && !__DOXYGEN__ */\n\nvoid lwesp_sys_preinit_threadx_set_bytepool_handle(TX_BYTE_POOL* bp);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_SYSTEM_PORT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/include/system/port/win32/lwesp_sys_port.h",
    "content": "/**\n * \\file            lwesp_sys_port.h\n * \\brief           WIN32 based system file implementation\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#ifndef LWESP_SYSTEM_PORT_HDR_H\n#define LWESP_SYSTEM_PORT_HDR_H\n\n#include <stdint.h>\n#include <stdlib.h>\n#include \"lwesp/lwesp_opt.h\"\n#include \"windows.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#if LWESP_CFG_OS && !__DOXYGEN__\n\ntypedef HANDLE lwesp_sys_mutex_t;\ntypedef HANDLE lwesp_sys_sem_t;\ntypedef HANDLE lwesp_sys_mbox_t;\ntypedef HANDLE lwesp_sys_thread_t;\ntypedef int lwesp_sys_thread_prio_t;\n\n#define LWESP_SYS_MBOX_NULL   ((HANDLE)0)\n#define LWESP_SYS_SEM_NULL    ((HANDLE)0)\n#define LWESP_SYS_MUTEX_NULL  ((HANDLE)0)\n#define LWESP_SYS_TIMEOUT     (INFINITE)\n#define LWESP_SYS_THREAD_PRIO (0)\n#define LWESP_SYS_THREAD_SS   (1024)\n\n#endif /* LWESP_CFG_OS && !__DOXYGEN__ */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* LWESP_SYSTEM_PORT_HDR_H */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp.c",
    "content": "/**\n * \\file            lwesp.c\n * \\brief           LwESP core file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_private.h\"\n#include \"lwesp/lwesp_threads.h\"\n#include \"lwesp/lwesp_timeout.h\"\n#include \"system/lwesp_ll.h\"\n\n/* Check for configuration */\n#if LWESP_CFG_OS != 1\n#error LWESP_CFG_OS must be set to 1 in current revision!\n#endif /* LWESP_CFG_OS != 1 */\n\nstatic lwesp_evt_func_t def_evt_link;\n\n/* Global ESP structure */\nlwesp_t esp;\n\n/**\n * \\brief           Default callback function for events\n * \\param[in]       evt: Pointer to callback data structure\n * \\return          Member of \\ref lwespr_t enumeration\n */\nstatic lwespr_t\nprv_def_callback(lwesp_evt_t* evt) {\n    LWESP_UNUSED(evt);\n    return lwespOK;\n}\n\n#if LWESP_CFG_KEEP_ALIVE\n\n/**\n * \\brief           Keep-alive timeout callback function\n * \\param[in]       arg: Custom user argument\n */\nstatic void\nprv_keep_alive_timeout_fn(void* arg) {\n    /* Dispatch keep-alive events */\n    lwespi_send_cb(LWESP_EVT_KEEP_ALIVE);\n\n    /* Start new timeout */\n    lwesp_timeout_add(LWESP_CFG_KEEP_ALIVE_TIMEOUT, prv_keep_alive_timeout_fn, arg);\n}\n\n#endif /* LWESP_CFG_KEEP_ALIVE */\n\n/**\n * \\brief           Init and prepare ESP stack for device operation\n * \\note            Function must be called from operating system thread context.\n *                  It creates necessary threads and waits them to start, thus running operating system is important.\n *                  - When \\ref LWESP_CFG_RESET_ON_INIT is enabled, reset sequence will be sent to device\n *                      otherwise manual call to \\ref lwesp_reset is required to setup device\n *                  - When \\ref LWESP_CFG_RESTORE_ON_INIT is enabled, restore sequence will be sent to device.\n *\n * \\param[in]       evt_func: Global event callback function for all major events\n * \\param[in]       blocking: Status whether command should be blocking or not.\n *                      Used when \\ref LWESP_CFG_RESET_ON_INIT or \\ref LWESP_CFG_RESTORE_ON_INIT are enabled.\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_init(lwesp_evt_fn evt_func, const uint32_t blocking) {\n    lwespr_t res = lwespOK;\n\n    memset(&esp, 0x00, sizeof(esp)); /* Reset structure to all zeros */\n    esp.status.f.initialized = 0;    /* Clear possible init flag */\n    def_evt_link.fn = evt_func != NULL ? evt_func : prv_def_callback;\n    esp.evt_func = &def_evt_link; /* Set callback function */\n    esp.evt_server = NULL;        /* Set default server callback function */\n\n    if (!lwesp_sys_init()) { /* Init low-level system */\n        goto cleanup;\n    }\n\n    if (!lwesp_sys_sem_create(&esp.sem_sync, 1)) { /* Create sync semaphore between threads */\n        LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                     \"[LWESP CORE] Cannot create sync semaphore!\\r\\n\");\n        goto cleanup;\n    }\n\n    /* Create message queues */\n    if (!lwesp_sys_mbox_create(&esp.mbox_producer, LWESP_CFG_THREAD_PRODUCER_MBOX_SIZE)) { /* Producer */\n        LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                     \"[LWESP CORE] Cannot create producer mbox queue!\\r\\n\");\n        goto cleanup;\n    }\n    if (!lwesp_sys_mbox_create(&esp.mbox_process, LWESP_CFG_THREAD_PROCESS_MBOX_SIZE)) { /* Process */\n        LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                     \"[LWESP CORE] Cannot create process mbox queue!\\r\\n\");\n        goto cleanup;\n    }\n\n    /*\n     * Create threads\n     *\n     * Each thread receives handle of semaphore that must be released inside the thread.\n     * This is to make sure threads start immediately after they are created\n     */\n    lwesp_sys_sem_wait(&esp.sem_sync, 0); /* Lock semaphore */\n    if (!lwesp_sys_thread_create(&esp.thread_produce, \"lwesp_produce\", lwesp_thread_produce, &esp.sem_sync,\n                                 LWESP_SYS_THREAD_SS, LWESP_SYS_THREAD_PRIO)) {\n        LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                     \"[LWESP CORE] Cannot create producing thread!\\r\\n\");\n        lwesp_sys_sem_release(&esp.sem_sync); /* Release semaphore and return */\n        goto cleanup;\n    }\n    lwesp_sys_sem_wait(&esp.sem_sync, 0); /* Wait semaphore, should be unlocked in process thread */\n    if (!lwesp_sys_thread_create(&esp.thread_process, \"lwesp_process\", lwesp_thread_process, &esp.sem_sync,\n                                 LWESP_SYS_THREAD_SS, LWESP_SYS_THREAD_PRIO)) {\n        LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                     \"[LWESP CORE] Cannot create processing thread!\\r\\n\");\n        lwesp_sys_thread_terminate(&esp.thread_produce); /* Delete produce thread */\n        lwesp_sys_sem_release(&esp.sem_sync);            /* Release semaphore and return */\n        goto cleanup;\n    }\n    lwesp_sys_sem_wait(&esp.sem_sync, 0); /* Wait semaphore, should be unlocked in produce thread */\n    lwesp_sys_sem_release(&esp.sem_sync); /* Release semaphore manually */\n\n    lwesp_core_lock();\n    esp.ll.uart.baudrate = LWESP_CFG_AT_PORT_BAUDRATE; /* Set default baudrate value */\n    lwesp_ll_init(&esp.ll);                            /* Init low-level communication */\n\n#if !LWESP_CFG_INPUT_USE_PROCESS\n    lwesp_buff_init(&esp.buff, LWESP_CFG_RCV_BUFF_SIZE); /* Init buffer for input data */\n#endif                                                   /* !LWESP_CFG_INPUT_USE_PROCESS */\n\n    esp.status.f.initialized = 1; /* We are initialized now */\n    esp.status.f.dev_present = 1; /* We assume device is present at this point */\n\n    lwespi_send_cb(LWESP_EVT_INIT_FINISH); /* Call user callback function */\n\n    /*\n     * Call reset command and call default\n     * AT commands to prepare basic setup for device\n     */\n    lwespi_conn_init(); /* Init connection module */\n\n#if LWESP_CFG_KEEP_ALIVE\n    /* Register keep-alive events */\n    lwesp_timeout_add(LWESP_CFG_KEEP_ALIVE_TIMEOUT, prv_keep_alive_timeout_fn, NULL);\n#endif /* LWESP_CFG_KEEP_ALIVE */\n\n#if LWESP_CFG_RESTORE_ON_INIT\n    if (esp.status.f.dev_present) { /* In case device exists */\n        lwesp_core_unlock();\n        res = lwesp_restore(NULL, NULL, blocking); /* Restore device */\n        lwesp_core_lock();\n    }\n#endif /* LWESP_CFG_RESTORE_ON_INIT */\n#if LWESP_CFG_RESET_ON_INIT\n    if (esp.status.f.dev_present) {\n        lwesp_core_unlock();\n        res = lwesp_reset_with_delay(LWESP_CFG_RESET_DELAY_DEFAULT, NULL, NULL,\n                                     blocking); /* Send reset sequence with delay */\n        lwesp_core_lock();\n    }\n#endif                      /* LWESP_CFG_RESET_ON_INIT */\n    LWESP_UNUSED(blocking); /* Prevent compiler warnings */\n    lwesp_core_unlock();\n\n    return res;\ncleanup:\n    if (lwesp_sys_mbox_isvalid(&esp.mbox_producer)) {\n        lwesp_sys_mbox_delete(&esp.mbox_producer);\n        lwesp_sys_mbox_invalid(&esp.mbox_producer);\n    }\n    if (lwesp_sys_mbox_isvalid(&esp.mbox_process)) {\n        lwesp_sys_mbox_delete(&esp.mbox_process);\n        lwesp_sys_mbox_invalid(&esp.mbox_process);\n    }\n    if (lwesp_sys_sem_isvalid(&esp.sem_sync)) {\n        lwesp_sys_sem_delete(&esp.sem_sync);\n        lwesp_sys_sem_invalid(&esp.sem_sync);\n    }\n    return lwespERRMEM;\n}\n\n/**\n * \\brief           Execute reset and send default commands\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_reset(const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    return lwesp_reset_with_delay(0, evt_fn, evt_arg, blocking);\n}\n\n/**\n * \\brief           Execute reset and send default commands with delay before first command\n * \\param[in]       delay: Number of milliseconds to wait before initiating first command to device\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_reset_with_delay(uint32_t delay, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                       const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_RESET;\n    LWESP_MSG_VAR_REF(msg).msg.reset.delay = delay;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 5000);\n}\n\n/**\n * \\brief           Execute restore command and set module to default values\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_restore(const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_RESTORE;\n    LWESP_MSG_VAR_REF(msg).cmd = LWESP_CMD_RESET;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 5000);\n}\n\n/**\n * \\brief           Sets WiFi mode to either station only, access point only or both\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\param[in]       mode: Mode of operation. This parameter can be a value of \\ref lwesp_mode_t enumeration\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_set_wifi_mode(lwesp_mode_t mode, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                    const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWMODE;\n    LWESP_MSG_VAR_REF(msg).msg.wifi_mode.mode = mode;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Gets WiFi mode of either station only, access point only or both\n *\n * \\param[in]       mode: point to space of Mode to get. This parameter can be a pointer of \\ref lwesp_mode_t enumeration\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_get_wifi_mode(lwesp_mode_t* mode, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                    const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWMODE_GET;\n    LWESP_MSG_VAR_REF(msg).msg.wifi_mode.mode_get = mode;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Sets baudrate of AT port (usually UART)\n * \\param[in]       baud: Baudrate in units of bits per second\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_set_at_baudrate(uint32_t baud, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_UART;\n    LWESP_MSG_VAR_REF(msg).msg.uart.baudrate = baud;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 2000);\n}\n\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n\n/**\n * \\brief           Update ESP software remotely\n * \\note            ESP must be connected to access point to use this feature\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_update_sw(const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIUPDATE;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 180000);\n}\n\n#endif /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n\n/**\n * \\brief           Lock stack from multi-thread access, enable atomic access to core\n *\n * If lock was `0` prior function call, lock is enabled and increased\n *\n * \\note            Function may be called multiple times to increase locks.\n *                  Application must take care to call \\ref lwesp_core_unlock\n *                  the same amount of time to make sure lock gets back to `0`\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_core_lock(void) {\n    lwesp_sys_protect();\n    ++esp.locked_cnt;\n    return lwespOK;\n}\n\n/**\n * \\brief           Unlock stack for multi-thread access\n *\n * Used in conjunction with \\ref lwesp_core_lock function\n *\n * If lock was non-zero before function call, lock is decreased.\n * When `lock == 0`, protection is disabled and other threads may access to core\n *\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_core_unlock(void) {\n    --esp.locked_cnt;\n    lwesp_sys_unprotect();\n    return lwespOK;\n}\n\n/**\n * \\brief           Notify stack if device is present or not\n *\n * Use this function to notify stack that device is not physically connected\n * and not ready to communicate with host device\n *\n * \\param[in]       present: Flag indicating device is present\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_device_set_present(uint8_t present, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                         const uint32_t blocking) {\n    lwespr_t res = lwespOK;\n    lwesp_core_lock();\n    present = present ? 1 : 0;\n    if (present != esp.status.f.dev_present) {\n        esp.status.f.dev_present = present;\n\n        if (!esp.status.f.dev_present) {\n            /* Manually reset stack to default device state */\n            lwespi_reset_everything(1);\n        } else {\n#if LWESP_CFG_RESET_ON_DEVICE_PRESENT\n            lwesp_core_unlock();\n            res = lwesp_reset_with_delay(LWESP_CFG_RESET_DELAY_DEFAULT, evt_fn, evt_arg, blocking);\n            lwesp_core_lock();\n#endif /* LWESP_CFG_RESET_ON_DEVICE_PRESENT */\n        }\n        lwespi_send_cb(LWESP_EVT_DEVICE_PRESENT); /* Send present event */\n    }\n    lwesp_core_unlock();\n\n    LWESP_UNUSED(evt_fn);\n    LWESP_UNUSED(evt_arg);\n    LWESP_UNUSED(blocking);\n\n    return res;\n}\n\n/**\n * \\brief           Check if device is present\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_device_is_present(void) {\n    uint8_t res;\n    lwesp_core_lock();\n    res = esp.status.f.dev_present;\n    lwesp_core_unlock();\n    return res;\n}\n\n#if LWESP_CFG_ESP8266 || __DOXYGEN__\n\n/**\n * \\brief           Check if modem device is ESP8266\n * \\note            Function is only available if \\ref LWESP_CFG_ESP8266 is enabled, otherwise it is defined as macro and evaluated to `0`\n * \\return          `1` on success, `0` otherwise\n * \\deprecated      Use \\ref lwesp_device_is_device instead\n */\nuint8_t\nlwesp_device_is_esp8266(void) {\n    return lwesp_device_is_device(LWESP_DEVICE_ESP8266);\n}\n\n#endif /* LWESP_CFG_ESP8266 || __DOXYGEN__ */\n\n#if LWESP_CFG_ESP32 || __DOXYGEN__\n\n/**\n * \\brief           Check if modem device is ESP32\n * \\note            Function is only available if \\ref LWESP_CFG_ESP32 is enabled, otherwise it is defined as macro and evaluated to `0`\n * \\return          `1` on success, `0` otherwise\n * \\deprecated      Use \\ref lwesp_device_is_device instead\n */\nuint8_t\nlwesp_device_is_esp32(void) {\n    return lwesp_device_is_device(LWESP_DEVICE_ESP32);\n}\n\n#endif /* LWESP_CFG_ESP32 || __DOXYGEN__ */\n\n#if LWESP_CFG_ESP32_C3 || __DOXYGEN__\n\n/**\n * \\brief           Check if modem device is ESP32-C3\n * \\note            Function is only available if \\ref LWESP_CFG_ESP32_C3 is enabled, otherwise it is defined as macro and evaluated to `0`\n * \\return          `1` on success, `0` otherwise\n * \\deprecated      Use \\ref lwesp_device_is_device instead\n */\nuint8_t\nlwesp_device_is_esp32_c3(void) {\n    return lwesp_device_is_device(LWESP_DEVICE_ESP32_C3);\n}\n\n#endif /* LWESP_CFG_ESP32_C3 || __DOXYGEN__ */\n\n/**\n * \\brief           Get currently connected Espressif device to AT port\n * \\return          Member of \\ref lwesp_device_t enumeration\n */\nlwesp_device_t\nlwesp_device_get_device(void) {\n    lwesp_device_t dev;\n    lwesp_core_lock();\n    dev = esp.m.device;\n    lwesp_core_unlock();\n    return dev;\n}\n\n/**\n * \\brief           Checks if connected device to the AT host is the one\n *                  as requested as parameter check.\n * \n * \\param           device: Device type to check against\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_device_is_device(lwesp_device_t device) {\n    lwesp_device_t dev;\n    lwesp_core_lock();\n    dev = esp.m.device;\n    lwesp_core_unlock();\n    return dev == device;\n}\n\n/**\n * \\brief           Get current AT firmware version of connected Espressif device.\n *                  It copies version from internal buffer to user variable,\n *                  and is valid only if reset/restore operation is successful.\n * \\param[out]      version: Output version variable\n * \\return          `1` on success, `0` otherwise\n */\nlwespr_t\nlwesp_get_current_at_fw_version(lwesp_sw_version_t* const version) {\n    LWESP_ASSERT(version != NULL);\n    lwesp_core_lock();\n    LWESP_MEMCPY(version, &esp.m.version_at, sizeof(*version));\n    lwesp_core_unlock();\n    return lwespOK;\n}\n\n/**\n * \\brief           Get minimal AT version required to run on Espressif device, to be well supported by LwESP library\n *                  and to ensure proper compatibility and correct operation\n * \\param[out]      version: Version output, pointer to \\ref lwesp_sw_version_t structure\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwesp_get_min_at_fw_version(lwesp_sw_version_t* const version) {\n    uint8_t res = lwespOK;\n    const lwesp_esp_device_desc_t* desc;\n    LWESP_ASSERT(version != NULL);\n\n    lwesp_core_lock();\n    desc = lwespi_get_device_desc_for_device(esp.m.device);\n    lwesp_core_unlock();\n\n    /* It returns pointer to const object, so it is OK to unlock earlier */\n    if (desc != NULL) {\n        lwesp_set_fw_version(version, desc->min_at_version);\n    } else {\n        res = lwespERR;\n    }\n    return res;\n}\n\n/**\n * \\brief           Delay for amount of milliseconds\n *\n * Delay is based on operating system semaphores.\n * It locks semaphore and waits for timeout in `ms` time.\n * Based on operating system, thread may be put to \\e blocked list during delay and may improve execution speed\n *\n * \\param[in]       ms: Milliseconds to delay\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_delay(const uint32_t ms) {\n    lwesp_sys_sem_t sem;\n    if (ms == 0) {\n        return 1;\n    }\n    if (lwesp_sys_sem_create(&sem, 0)) {\n        lwesp_sys_sem_wait(&sem, ms);\n        lwesp_sys_sem_release(&sem);\n        lwesp_sys_sem_delete(&sem);\n        return 1;\n    }\n    return 0;\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_ap.c",
    "content": "/**\n * \\file            lwesp_ap.c\n * \\brief           Access point\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_ap.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n\n/**\n * \\brief           Get IP of access point\n * \\param[out]      ip: Pointer to variable to write IP address\n * \\param[out]      gw: Pointer to variable to write gateway address\n * \\param[out]      nm: Pointer to variable to write netmask address\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ap_getip(lwesp_ip_t* ip, lwesp_ip_t* gw, lwesp_ip_t* nm, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n               const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CIPAP_GET;\n    LWESP_MSG_VAR_REF(msg).msg.sta_ap_getip.ip = ip;\n    LWESP_MSG_VAR_REF(msg).msg.sta_ap_getip.gw = gw;\n    LWESP_MSG_VAR_REF(msg).msg.sta_ap_getip.nm = nm;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Set IP of access point\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\param[in]       ip: Pointer to IP address\n * \\param[in]       gw: Pointer to gateway address. Set to `NULL` to use default gateway\n * \\param[in]       nm: Pointer to netmask address. Set to `NULL` to use default netmask\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ap_setip(const lwesp_ip_t* ip, const lwesp_ip_t* gw, const lwesp_ip_t* nm, const lwesp_api_cmd_evt_fn evt_fn,\n               void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(ip != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CIPAP_SET;\n    LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.sta_ap_setip.ip, ip, sizeof(*ip));\n    LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.sta_ap_setip.gw, gw, sizeof(*gw));\n    LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.sta_ap_setip.nm, nm, sizeof(*nm));\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get MAC of access point\n * \\param[out]      mac: Pointer to output variable to save MAC address\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ap_getmac(lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CIPAPMAC_GET;\n    LWESP_MSG_VAR_REF(msg).msg.sta_ap_getmac.mac = mac;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Set MAC of access point\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\param[in]       mac: Pointer to variable with MAC address. Memory of at least 6 bytes is required\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ap_setmac(const lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(mac != NULL);\n    LWESP_ASSERT(!(((uint8_t*)mac)[0] & 0x01));\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CIPAPMAC_SET;\n    LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.sta_ap_setmac.mac, mac, sizeof(*mac));\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Configure access point\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\note            Before you can configure access point, ESP device must be in AP mode. Check \\ref lwesp_set_wifi_mode for more information\n * \\param[in]       ssid: SSID name of access point\n * \\param[in]       pwd: Password for network. Either set it to `NULL` or less than `64` characters\n * \\param[in]       ch: Wifi RF channel\n * \\param[in]       ecn: Encryption type. Valid options are `OPEN`, `WPA_PSK`, `WPA2_PSK` and `WPA_WPA2_PSK`\n * \\param[in]       max_sta: Maximal number of stations access point can accept. Valid between 1 and 10 stations\n * \\param[in]       hid: Set to `1` to hide access point from public access\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ap_set_config(const char* ssid, const char* pwd, uint8_t ch, lwesp_ecn_t ecn, uint8_t max_sta, uint8_t hid,\n                    const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(ssid != NULL);\n    LWESP_ASSERT(pwd == NULL || (pwd != NULL && strlen(pwd) <= 64));\n    LWESP_ASSERT(ecn == LWESP_ECN_OPEN || ecn == LWESP_ECN_WPA_PSK || ecn == LWESP_ECN_WPA2_PSK\n                 || ecn == LWESP_ECN_WPA_WPA2_PSK);\n    LWESP_ASSERT(ch <= 128);\n    LWESP_ASSERT(max_sta > 0 && max_sta <= 10);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWSAP_SET;\n    LWESP_MSG_VAR_REF(msg).msg.ap_conf.ssid = ssid;\n    LWESP_MSG_VAR_REF(msg).msg.ap_conf.pwd = pwd;\n    LWESP_MSG_VAR_REF(msg).msg.ap_conf.ch = ch;\n    LWESP_MSG_VAR_REF(msg).msg.ap_conf.ecn = ecn;\n    LWESP_MSG_VAR_REF(msg).msg.ap_conf.max_sta = max_sta;\n    LWESP_MSG_VAR_REF(msg).msg.ap_conf.hid = hid;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 10000);\n}\n\n/**\n * \\brief           Get configuration of Soft Access Point\n *\n * \\note            Before you can get configuration access point, ESP device must be in AP mode. Check \\ref lwesp_set_wifi_mode for more information\n * \\param[out]      ap_conf: soft access point configuration\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ap_get_config(lwesp_ap_conf_t* ap_conf, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                    const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(ap_conf != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWSAP_GET;\n    LWESP_MSG_VAR_REF(msg).msg.ap_conf_get.ap_conf = ap_conf;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 10000);\n}\n\n/**\n * \\brief           List stations connected to access point\n * \\param[in]       sta: Pointer to array of \\ref lwesp_sta_t structure to fill with stations\n * \\param[in]       stal: Number of array entries of sta parameter\n * \\param[out]      staf: Number of stations connected to access point\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ap_list_sta(lwesp_sta_t* sta, size_t stal, size_t* staf, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                  const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(sta != NULL);\n    LWESP_ASSERT(stal > 0);\n\n    if (staf != NULL) {\n        *staf = 0;\n    }\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWLIF;\n    LWESP_MSG_VAR_REF(msg).msg.sta_list.stas = sta;\n    LWESP_MSG_VAR_REF(msg).msg.sta_list.stal = stal;\n    LWESP_MSG_VAR_REF(msg).msg.sta_list.staf = staf;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Disconnects connected station from SoftAP access point\n * \\param[in]       mac: Device MAC address to disconnect.\n *                      Application may use \\ref lwesp_ap_list_sta to obtain list of connected stations to SoftAP.\n *                      Set to `NULL` to disconnect all stations.\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ap_disconn_sta(const lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                     const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWQIF;\n    LWESP_MSG_VAR_REF(msg).msg.ap_disconn_sta.use_mac = mac != NULL;\n    if (mac != NULL) {\n        LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.ap_disconn_sta.mac, mac, sizeof(*mac));\n    }\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n#endif /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_ble.c",
    "content": "/**\n * \\file            lwesp_ble.c\n * \\brief           Bluetooth Low Energy\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_ble.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_BLE\n#error \"LWESP_CFG_BLE must be disabled in current revision\"\n#endif /* LWESP_CFG_BLE */\n\n#if LWESP_CFG_BLE || __DOXYGEN__\n\n#endif /* LWESP_CFG_BLE || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_bt.c",
    "content": "/**\n * \\file            lwesp_bt.c\n * \\brief           Bluetooth Classic\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_bt.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_BT\n#error \"LWESP_CFG_BT must be disabled in current revision\"\n#endif /* LWESP_CFG_BT */\n\n#if LWESP_CFG_BT || __DOXYGEN__\n\n#endif /* LWESP_CFG_BLE || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_buff.c",
    "content": "/**\n * \\file            lwesp_buff.c\n * \\brief           Ring buffer manager\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_buff.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/* --- Buffer unique part starts --- */\n/* Prefix for all buffer functions and typedefs */\n#define BUF_PREF(x)     lwesp_##x\n/* --- Buffer unique part ends --- */\n\n/* Buffer utility macros */\n#define BUF_MEMSET      LWESP_MEMSET\n#define BUF_MEMCPY      LWESP_MEMCPY\n#define BUF_IS_VALID(b) ((b) != NULL && (b)->buff != NULL && (b)->size > 0)\n#define BUF_MIN(x, y)   ((x) < (y) ? (x) : (y))\n#define BUF_MAX(x, y)   ((x) > (y) ? (x) : (y))\n\n/**\n * \\brief           Initialize buffer\n * \\param[in]       buff: Pointer to buffer structure\n * \\param[in]       size: Size of buffer in units of bytes\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nBUF_PREF(buff_init)(BUF_PREF(buff_t) * buff, size_t size) {\n    if (buff == NULL || size == 0) {\n        return 0;\n    }\n    BUF_MEMSET(buff, 0, sizeof(*buff));\n\n    buff->size = size;                                         /* Set default values */\n    buff->buff = lwesp_mem_malloc(sizeof(*buff->buff) * size); /* Allocate memory for buffer */\n\n    if (buff->buff == NULL) { /* Check allocation */\n        return 0;\n    }\n    return 1; /* Initialized OK */\n}\n\n/**\n * \\brief           Free dynamic allocation if used on memory\n * \\param[in]       buff: Pointer to buffer structure\n */\nvoid\nBUF_PREF(buff_free)(BUF_PREF(buff_t) * buff) {\n    if (BUF_IS_VALID(buff)) {\n        lwesp_mem_free_s((void**)&buff->buff);\n    }\n}\n\n/**\n * \\brief           Write data to buffer\n *                  Copies data from `data` array to buffer and marks buffer as full for maximum `count` number of bytes\n * \\param[in]       buff: Buffer handle\n * \\param[in]       data: Pointer to data to write into buffer\n * \\param[in]       btw: Number of bytes to write\n * \\return          Number of bytes written to buffer.\n *                  When returned value is less than `btw`, there was no enough memory available\n *                  to copy full data array\n */\nsize_t\nBUF_PREF(buff_write)(BUF_PREF(buff_t) * buff, const void* data, size_t btw) {\n    size_t tocopy, free;\n    const uint8_t* d = data;\n\n    if (!BUF_IS_VALID(buff) || btw == 0) {\n        return 0;\n    }\n\n    /* Calculate maximum number of bytes available to write */\n    free = BUF_PREF(buff_get_free)(buff);\n    btw = BUF_MIN(free, btw);\n    if (btw == 0) {\n        return 0;\n    }\n\n    /* Step 1: Write data to linear part of buffer */\n    tocopy = BUF_MIN(buff->size - buff->w, btw);\n    BUF_MEMCPY(&buff->buff[buff->w], d, tocopy);\n    buff->w += tocopy;\n    btw -= tocopy;\n\n    /* Step 2: Write data to beginning of buffer (overflow part) */\n    if (btw > 0) {\n        BUF_MEMCPY(buff->buff, (void*)&d[tocopy], btw);\n        buff->w = btw;\n    }\n\n    if (buff->w >= buff->size) {\n        buff->w = 0;\n    }\n    return tocopy + btw;\n}\n\n/**\n * \\brief           Read data from buffer\n *                  Copies data from buffer to `data` array and marks buffer as free for maximum `btr` number of bytes\n * \\param[in]       buff: Buffer handle\n * \\param[out]      data: Pointer to output memory to copy buffer data to\n * \\param[in]       btr: Number of bytes to read\n * \\return          Number of bytes read and copied to data array\n */\nsize_t\nBUF_PREF(buff_read)(BUF_PREF(buff_t) * buff, void* data, size_t btr) {\n    size_t tocopy, full;\n    uint8_t* d = data;\n\n    if (!BUF_IS_VALID(buff) || btr == 0) {\n        return 0;\n    }\n\n    /* Calculate maximum number of bytes available to read */\n    full = BUF_PREF(buff_get_full)(buff);\n    btr = BUF_MIN(full, btr);\n    if (btr == 0) {\n        return 0;\n    }\n\n    /* Step 1: Read data from linear part of buffer */\n    tocopy = BUF_MIN(buff->size - buff->r, btr);\n    BUF_MEMCPY(d, &buff->buff[buff->r], tocopy);\n    buff->r += tocopy;\n    btr -= tocopy;\n\n    /* Step 2: Read data from beginning of buffer (overflow part) */\n    if (btr > 0) {\n        BUF_MEMCPY(&d[tocopy], buff->buff, btr);\n        buff->r = btr;\n    }\n\n    /* Step 3: Check end of buffer */\n    if (buff->r >= buff->size) {\n        buff->r = 0;\n    }\n    return tocopy + btr;\n}\n\n/**\n * \\brief           Read from buffer without changing read pointer (peek only)\n * \\param[in]       buff: Buffer handle\n * \\param[in]       skip_count: Number of bytes to skip before reading data\n * \\param[out]      data: Pointer to output memory to copy buffer data to\n * \\param[in]       btp: Number of bytes to peek\n * \\return          Number of bytes peeked and written to output array\n */\nsize_t\nBUF_PREF(buff_peek)(BUF_PREF(buff_t) * buff, size_t skip_count, void* data, size_t btp) {\n    size_t full, tocopy, r;\n    uint8_t* d = data;\n\n    if (!BUF_IS_VALID(buff) || btp == 0) {\n        return 0;\n    }\n\n    r = buff->r;\n\n    /* Calculate maximum number of bytes available to read */\n    full = BUF_PREF(buff_get_full)(buff);\n\n    /* Skip beginning of buffer */\n    if (skip_count >= full) {\n        return 0;\n    }\n    r += skip_count;\n    full -= skip_count;\n    if (r >= buff->size) {\n        r -= buff->size;\n    }\n\n    /* Check maximum number of bytes available to read after skip */\n    btp = BUF_MIN(full, btp);\n    if (btp == 0) {\n        return 0;\n    }\n\n    /* Step 1: Read data from linear part of buffer */\n    tocopy = BUF_MIN(buff->size - r, btp);\n    BUF_MEMCPY(d, &buff->buff[r], tocopy);\n    btp -= tocopy;\n\n    /* Step 2: Read data from beginning of buffer (overflow part) */\n    if (btp > 0) {\n        BUF_MEMCPY(&d[tocopy], buff->buff, btp);\n    }\n    return tocopy + btp;\n}\n\n/**\n * \\brief           Get number of bytes in buffer available to write\n * \\param[in]       buff: Buffer handle\n * \\return          Number of free bytes in memory\n */\nsize_t\nBUF_PREF(buff_get_free)(BUF_PREF(buff_t) * buff) {\n    size_t size, w, r;\n\n    if (!BUF_IS_VALID(buff)) {\n        return 0;\n    }\n\n    /* Use temporary values in case they are changed during operations */\n    w = buff->w;\n    r = buff->r;\n    if (w == r) {\n        size = buff->size;\n    } else if (r > w) {\n        size = r - w;\n    } else {\n        size = buff->size - (w - r);\n    }\n\n    /* Buffer free size is always 1 less than actual size */\n    return size - 1;\n}\n\n/**\n * \\brief           Get number of bytes in buffer available to read\n * \\param[in]       buff: Buffer handle\n * \\return          Number of bytes ready to be read\n */\nsize_t\nBUF_PREF(buff_get_full)(BUF_PREF(buff_t) * buff) {\n    size_t w, r, size;\n\n    if (!BUF_IS_VALID(buff)) {\n        return 0;\n    }\n\n    /* Use temporary values in case they are changed during operations */\n    w = buff->w;\n    r = buff->r;\n    if (w == r) {\n        size = 0;\n    } else if (w > r) {\n        size = w - r;\n    } else {\n        size = buff->size - (r - w);\n    }\n    return size;\n}\n\n/**\n * \\brief           Resets buffer to default values. Buffer size is not modified\n * \\param[in]       buff: Buffer handle\n */\nvoid\nBUF_PREF(buff_reset)(BUF_PREF(buff_t) * buff) {\n    if (BUF_IS_VALID(buff)) {\n        buff->w = 0;\n        buff->r = 0;\n    }\n}\n\n/**\n * \\brief           Get linear address for buffer for fast read\n * \\param[in]       buff: Buffer handle\n * \\return          Linear buffer start address\n */\nvoid*\nBUF_PREF(buff_get_linear_block_read_address)(BUF_PREF(buff_t) * buff) {\n    if (!BUF_IS_VALID(buff)) {\n        return NULL;\n    }\n    return &buff->buff[buff->r];\n}\n\n/**\n * \\brief           Get length of linear block address before it overflows for read operation\n * \\param[in]       buff: Buffer handle\n * \\return          Linear buffer size in units of bytes for read operation\n */\nsize_t\nBUF_PREF(buff_get_linear_block_read_length)(BUF_PREF(buff_t) * buff) {\n    size_t w, r, len;\n\n    if (!BUF_IS_VALID(buff)) {\n        return 0;\n    }\n\n    /* Use temporary values in case they are changed during operations */\n    w = buff->w;\n    r = buff->r;\n    if (w > r) {\n        len = w - r;\n    } else if (r > w) {\n        len = buff->size - r;\n    } else {\n        len = 0;\n    }\n    return len;\n}\n\n/**\n * \\brief           Skip (ignore; advance read pointer) buffer data\n *                  Marks data as read in the buffer and increases free memory for up to `len` bytes\n * \\note            Useful at the end of streaming transfer such as DMA\n * \\param[in]       buff: Buffer handle\n * \\param[in]       len: Number of bytes to skip and mark as read\n * \\return          Number of bytes skipped\n */\nsize_t\nBUF_PREF(buff_skip)(BUF_PREF(buff_t) * buff, size_t len) {\n    size_t full;\n\n    if (!BUF_IS_VALID(buff) || len == 0) {\n        return 0;\n    }\n\n    full = BUF_PREF(buff_get_full)(buff); /* Get buffer used length */\n    buff->r += BUF_MIN(len, full);        /* Advance read pointer */\n    if (buff->r >= buff->size) {          /* Subtract possible overflow */\n        buff->r -= buff->size;\n    }\n    return len;\n}\n\n/**\n * \\brief           Get linear address for buffer for fast read\n * \\param[in]       buff: Buffer handle\n * \\return          Linear buffer start address\n */\nvoid*\nBUF_PREF(buff_get_linear_block_write_address)(BUF_PREF(buff_t) * buff) {\n    if (!BUF_IS_VALID(buff)) {\n        return NULL;\n    }\n    return &buff->buff[buff->w];\n}\n\n/**\n * \\brief           Get length of linear block address before it overflows for write operation\n * \\param[in]       buff: Buffer handle\n * \\return          Linear buffer size in units of bytes for write operation\n */\nsize_t\nBUF_PREF(buff_get_linear_block_write_length)(BUF_PREF(buff_t) * buff) {\n    size_t w, r, len;\n\n    if (!BUF_IS_VALID(buff)) {\n        return 0;\n    }\n\n    /* Use temporary values in case they are changed during operations */\n    w = buff->w;\n    r = buff->r;\n    if (w >= r) {\n        len = buff->size - w;\n        /*\n         * When read pointer is 0,\n         * maximal length is one less as if too many bytes\n         * are written, buffer would be considered empty again (r == w)\n         */\n        if (r == 0) {\n            /*\n             * Cannot overflow:\n             * - If r is not 0, statement does not get called\n             * - buff->size cannot be 0 and if r is 0, len is greater 0\n             */\n            --len;\n        }\n    } else {\n        len = r - w - 1;\n    }\n    return len;\n}\n\n/**\n * \\brief           Advance write pointer in the buffer.\n *                  Similar to skip function but modifies write pointer instead of read\n * \\note            Useful when hardware is writing to buffer and application needs to increase number\n *                  of bytes written to buffer by hardware\n * \\param[in]       buff: Buffer handle\n * \\param[in]       len: Number of bytes to advance\n * \\return          Number of bytes advanced for write operation\n */\nsize_t\nBUF_PREF(buff_advance)(BUF_PREF(buff_t) * buff, size_t len) {\n    size_t free;\n\n    if (!BUF_IS_VALID(buff) || len == 0) {\n        return 0;\n    }\n\n    free = BUF_PREF(buff_get_free)(buff); /* Get buffer free length */\n    buff->w += BUF_MIN(len, free);        /* Advance write pointer */\n    if (buff->w >= buff->size) {          /* Subtract possible overflow */\n        buff->w -= buff->size;\n    }\n    return len;\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_cli.c",
    "content": "/**\n * \\file            lwesp_cli.c\n * \\brief           ESP CLI commands\n */\n\n/*\n * Copyright (c) 2019 Miha CESNIK\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Miha CESNIK <>\n * Version:         v1.1.2-dev\n */\n#include <stdbool.h>\n#include <stdint.h>\n#include \"lwesp/lwesp.h\"\n#if LWESP_CFG_MODE_STATION\n#include \"lwesp/lwesp_sta.h\"\n#endif /* LWESP_CFG_MODE_STATION */\n#include \"cli/cli.h\"\n#include \"cli/cli_opt.h\"\n\n#if LWESP_CFG_MODE_STATION\nstatic void cli_station_info(cli_printf cliprintf, int argc, char** argv);\n#endif /* LWESP_CFG_MODE_STATION */\n\nstatic const cli_command_t commands[] = {\n#if LWESP_CFG_MODE_STATION\n    {\"station-info\", \"Get current station info\", cli_station_info},\n#endif /* LWESP_CFG_MODE_STATION */\n};\n\n/**\n * \\brief           CLI Init function for adding basic CLI commands\n */\nvoid\nlwesp_cli_register_commands(void) {\n    cli_register_commands(commands, sizeof(commands) / sizeof(commands[0]));\n}\n\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n\n/**\n * \\brief           CLI command for reading current AP info\n * \\param[in]       cliprintf: Pointer to CLI printf function\n * \\param[in]       argc: Number fo arguments in argv\n * \\param[in]       argv: Pointer to the commands arguments\n */\nstatic void\ncli_station_info(cli_printf cliprintf, int argc, char** argv) {\n    lwespr_t res;\n    lwesp_sta_info_ap_t info;\n\n    res = lwesp_sta_get_ap_info(&info, NULL, NULL, 1);\n    if (res != lwespOK) {\n        cliprintf(\"Error: Failed to read station info (%d)\" CLI_NL, res);\n        return;\n    }\n\n    cliprintf(\"  SSID:    %s\" CLI_NL, info.ssid);\n    cliprintf(\"  MAC:     %02X:%02X:%02X:%02X:%02X\" CLI_NL, info.mac.mac[0], info.mac.mac[1], info.mac.mac[2],\n              info.mac.mac[3], info.mac.mac[4], info.mac.mac[5]);\n    cliprintf(\"  RSSI:    %d\" CLI_NL, info.rssi);\n    cliprintf(\"  Channel: %d\" CLI_NL, info.ch);\n\n    LWESP_UNUSED(argc);\n    LWESP_UNUSED(argv);\n}\n\n#endif /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_conn.c",
    "content": "/**\n * \\file            lwesp_conn.c\n * \\brief           Connection API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_conn.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/**\n * \\brief           Check if connection is closed or in closing state\n * \\param[in]       conn: Connection handle\n * \\hideinitializer\n */\n#define CONN_CHECK_CLOSED_IN_CLOSING(conn)                                                                             \\\n    do {                                                                                                               \\\n        lwespr_t r = lwespOK;                                                                                          \\\n        lwesp_core_lock();                                                                                             \\\n        if (conn->status.f.in_closing || !conn->status.f.active) {                                                     \\\n            r = lwespCLOSED;                                                                                           \\\n        }                                                                                                              \\\n        lwesp_core_unlock();                                                                                           \\\n        if (r != lwespOK) {                                                                                            \\\n            return r;                                                                                                  \\\n        }                                                                                                              \\\n    } while (0)\n\n/**\n * \\brief           Timeout callback for connection\n * \\param[in]       arg: Timeout callback custom argument\n */\nstatic void\nprv_conn_timeout_cb(void* arg) {\n    lwesp_conn_p conn = arg; /* Argument is actual connection */\n\n    if (conn->status.f.active) {            /* Handle only active connections */\n        esp.evt.type = LWESP_EVT_CONN_POLL; /* Poll connection event */\n        esp.evt.evt.conn_poll.conn = conn;  /* Set connection pointer */\n        lwespi_send_conn_cb(conn, NULL);    /* Send connection callback */\n\n        lwespi_conn_start_timeout(conn); /* Schedule new timeout */\n        LWESP_DEBUGF(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, \"[LWESP CONN] Poll event: %p\\r\\n\", (void*)conn);\n    }\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n    lwespi_conn_manual_tcp_try_read_data(conn); /* Try to read data manually */\n#endif                                          /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n}\n\n/**\n * \\brief           Start timeout function for connection\n * \\param[in]       conn: Connection handle as user argument\n */\nvoid\nlwespi_conn_start_timeout(lwesp_conn_p conn) {\n    lwesp_timeout_add(LWESP_CFG_CONN_POLL_INTERVAL, prv_conn_timeout_cb, conn); /* Add connection timeout */\n}\n\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE || __DOXYGEN__\n\n/**\n * \\brief           Callback function when manual TCP receive finishes\n * \\param[in]       res: Result of reading\n * \\param[in]       arg: Custom user argument\n */\nstatic void\nprv_manual_tcp_read_data_evt_fn(lwespr_t res, void* arg) {\n    lwesp_conn_p conn = arg;\n\n    LWESP_UNUSED(res);\n\n    conn->status.f.receive_is_command_queued = 0;\n    lwespi_conn_manual_tcp_try_read_data(conn);\n}\n\n/**\n * \\brief           Manually start data read operation with desired length on specific connection\n * \\param[in]       conn: Connection handle\n * \\param[in]       len: Number of bytes to read\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwespi_conn_manual_tcp_try_read_data(lwesp_conn_p conn) {\n    uint32_t blocking = 0;\n    lwespr_t res = lwespOK;\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(conn != NULL);\n\n    /* Receive must not be blocked and other command must not be in queue to read data */\n    if (conn->status.f.receive_blocked || conn->status.f.receive_is_command_queued) {\n        return lwespINPROG;\n    }\n\n    /* Any available data to process? */\n    if (conn->tcp_available_bytes == 0 || !conn->status.f.active) {\n        return lwespERR;\n    }\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);                                /* Allocate first, will return on failure */\n    LWESP_MSG_VAR_SET_EVT(msg, prv_manual_tcp_read_data_evt_fn, conn); /* Set event callback function */\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPRECVDATA;\n    LWESP_MSG_VAR_REF(msg).cmd = LWESP_CMD_TCPIP_CIPRECVLEN;\n    LWESP_MSG_VAR_REF(msg).msg.conn_recv.len = 0;     /* Filled after RECVLEN received */\n    LWESP_MSG_VAR_REF(msg).msg.conn_recv.buff = NULL; /* Filled after RECVLEN received */\n    LWESP_MSG_VAR_REF(msg).msg.conn_recv.conn = conn;\n\n    /* Try to start command */\n    if ((res = lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 60000)) == lwespOK) {\n        conn->status.f.receive_is_command_queued = 1; /* Command queued */\n    }\n    return res;\n}\n\n/**\n * \\brief           Callback function for checking receive length in manual TCP receive buffer\n * \\param[in]       res: Result of reading\n * \\param[in]       arg: Custom user argument\n */\nstatic void\nprv_check_available_rx_data_evt_fn(lwespr_t res, void* arg) {\n    LWESP_UNUSED(arg);\n    LWESP_UNUSED(res);\n\n    /* Try to read data if possible */\n    for (size_t i = 0; i < LWESP_CFG_MAX_CONNS; ++i) {\n        lwespi_conn_manual_tcp_try_read_data(&esp.m.conns[i]);\n    }\n}\n\n/**\n * \\brief           Manually check for received buffer status for connections\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nlwespi_conn_check_available_rx_data(void) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, 0);                                          /* Allocate first, will return on failure */\n    LWESP_MSG_VAR_SET_EVT(msg, prv_check_available_rx_data_evt_fn, NULL); /* Set event callback function */\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPRECVLEN;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE || __DOXYGEN__ */\n\n/**\n * \\brief           Send data on already active connection of type UDP to specific remote IP and port\n * \\note            In case IP and port values are not set, it will behave as normal send function (suitable for TCP too)\n * \\param[in]       conn: Pointer to connection to send data\n * \\param[in]       ip: Remote IP address for UDP connection\n * \\param[in]       port: Remote port connection\n * \\param[in]       data: Pointer to data to send\n * \\param[in]       btw: Number of bytes to send\n * \\param[out]      bw: Pointer to output variable to save number of sent data when successfully sent\n * \\param[in]       fau: \"Free After Use\" flag. Set to `1` if stack should free the memory after data sent\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nstatic lwespr_t\nprv_conn_send(lwesp_conn_p conn, const lwesp_ip_t* const ip, lwesp_port_t port, const void* data, size_t btw,\n              size_t* const bw, uint8_t fau, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(conn != NULL);\n    LWESP_ASSERT(data != NULL);\n    LWESP_ASSERT(btw > 0);\n\n    CONN_CHECK_CLOSED_IN_CLOSING(conn); /* Check if we can continue */\n\n#if !LWESP_CFG_CONN_ALLOW_FRAGMENTED_UDP_SEND\n    /*\n     * For UDP connections, do not allow fragmented data send.\n     *\n     * Limit up to maximum buffer allowed by ESP\n     */\n    if (CONN_IS_UDP_V4_OR_V6(conn->type)) {\n        LWESP_ASSERT(btw <= LWESP_CFG_CONN_MAX_DATA_LEN);\n    }\n#endif /* !LWESP_CFG_CONN_ALLOW_FRAGMENTED_UDP_SEND */\n\n    if (bw != NULL) {\n        *bw = 0;\n    }\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSEND;\n\n    LWESP_MSG_VAR_REF(msg).msg.conn_send.conn = conn;\n    LWESP_MSG_VAR_REF(msg).msg.conn_send.data = data;\n    LWESP_MSG_VAR_REF(msg).msg.conn_send.btw = btw;\n    LWESP_MSG_VAR_REF(msg).msg.conn_send.bw = bw;\n    LWESP_MSG_VAR_REF(msg).msg.conn_send.remote_ip = ip;\n    LWESP_MSG_VAR_REF(msg).msg.conn_send.remote_port = port;\n    LWESP_MSG_VAR_REF(msg).msg.conn_send.fau = fau;\n    LWESP_MSG_VAR_REF(msg).msg.conn_send.val_id = conn->val_id;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 60000);\n}\n\n/**\n * \\brief           Flush buffer on connection\n * \\param[in]       conn: Connection to flush buffer on\n * \\return          \\ref lwespOK if data flushed and put to queue, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nflush_buff(lwesp_conn_p conn) {\n    lwespr_t res = lwespOK;\n    lwesp_core_lock();\n    if (conn != NULL && conn->buff.buff != NULL) { /* Do we have something ready? */\n        /*\n         * If there is nothing to write or if write was not successful,\n         * simply free the memory and stop execution\n         */\n        if (conn->buff.ptr > 0) { /* Anything to send at the moment? */\n            res = prv_conn_send(conn, NULL, 0, conn->buff.buff, conn->buff.ptr, NULL, 1, 0);\n        } else {\n            res = lwespERR;\n        }\n        if (res != lwespOK) {\n            LWESP_DEBUGF(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, \"[LWESP CONN] Free write buffer: %p\\r\\n\",\n                         (void*)conn->buff.buff);\n            lwesp_mem_free_s((void**)&conn->buff.buff);\n        }\n        conn->buff.buff = NULL;\n    }\n    lwesp_core_unlock();\n    return res;\n}\n\n/**\n * \\brief           Initialize connection module\n */\nvoid\nlwespi_conn_init(void) {}\n\n/**\n * \\brief           Start a new connection of specific type\n * \\param[out]      conn: Pointer to connection handle to set new connection reference in case of successfully connected\n * \\param[in]       type: Connection type. This parameter can be a value of \\ref lwesp_conn_type_t enumeration.\n *                      Do not use this method to start SSL connection.\n *                      Use \\ref lwesp_conn_startex instead\n * \\param[in]       remote_host: Connection host. In case of IP, write it as string, ex. \"192.168.1.1\"\n * \\param[in]       remote_port: Connection port\n * \\param[in]       arg: Pointer to user argument passed to connection if successfully connected\n * \\param[in]       conn_evt_fn: Callback function for this connection\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_start(lwesp_conn_p* conn, lwesp_conn_type_t type, const char* const remote_host, lwesp_port_t remote_port,\n                 void* const arg, lwesp_evt_fn conn_evt_fn, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(remote_host != NULL);\n    LWESP_ASSERT(remote_port > 0);\n    LWESP_ASSERT(conn_evt_fn != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSTART;\n    LWESP_MSG_VAR_REF(msg).cmd = lwespi_get_cipstatus_or_cipstate_cmd();\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.conn = conn;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.type = type;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.remote_host = remote_host;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.remote_port = remote_port;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.evt_func = conn_evt_fn;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.arg = arg;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 60000);\n}\n\n/**\n * \\brief           Start a new connection of specific type in extended mode\n * \\param[out]      conn: Pointer to connection handle to set new connection reference in case of successfully connected\n * \\param[in]       start_struct: Connection information are handled by one giant structure\n * \\param[in]       arg: Pointer to user argument passed to connection if successfully connected\n * \\param[in]       conn_evt_fn: Callback function for this connection\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_startex(lwesp_conn_p* conn, lwesp_conn_start_t* start_struct, void* const arg, lwesp_evt_fn conn_evt_fn,\n                   const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(start_struct != NULL);\n    LWESP_ASSERT(start_struct->remote_host != NULL);\n    LWESP_ASSERT(start_struct->remote_port > 0);\n    LWESP_ASSERT(conn_evt_fn != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSTART;\n    LWESP_MSG_VAR_REF(msg).cmd = lwespi_get_cipstatus_or_cipstate_cmd();\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.conn = conn;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.type = start_struct->type;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.remote_host = start_struct->remote_host;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.remote_port = start_struct->remote_port;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.local_ip = start_struct->local_ip;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.evt_func = conn_evt_fn;\n    LWESP_MSG_VAR_REF(msg).msg.conn_start.arg = arg;\n\n#if 0\n    if (start_struct->type == LWESP_CONN_TYPE_SSL || start_struct->type == LWESP_CONN_TYPE_SSLV6) {\n        LWESP_MSG_VAR_REF(msg).msg.conn_start.ssl_auth = start_struct->ext.tcp_ssl.auth_mode;\n        LWESP_MSG_VAR_REF(msg).msg.conn_start.ssl_ca_num = start_struct->ext.tcp_ssl.ca_number;\n        LWESP_MSG_VAR_REF(msg).msg.conn_start.ssl_pki_num = start_struct->ext.tcp_ssl.pki_number;\n    }\n#endif\n\n    /* Add connection type specific features */\n    if (!CONN_IS_UDP_V4_OR_V6(start_struct->type)) {\n        LWESP_MSG_VAR_REF(msg).msg.conn_start.tcp_ssl_keep_alive = start_struct->ext.tcp_ssl.keep_alive;\n    } else {\n        LWESP_MSG_VAR_REF(msg).msg.conn_start.udp_local_port = start_struct->ext.udp.local_port;\n        LWESP_MSG_VAR_REF(msg).msg.conn_start.udp_mode = start_struct->ext.udp.mode;\n    }\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 60000);\n}\n\n/**\n * \\brief           Close specific or all connections\n * \\param[in]       conn: Connection handle to close. Set to NULL if you want to close all connections.\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_close(lwesp_conn_p conn, const uint32_t blocking) {\n    lwespr_t res;\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(conn != NULL);\n\n    CONN_CHECK_CLOSED_IN_CLOSING(conn); /* Check if we can continue */\n\n    /* Proceed with close event at this point! */\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPCLOSE;\n    LWESP_MSG_VAR_REF(msg).msg.conn_close.conn = conn;\n    LWESP_MSG_VAR_REF(msg).msg.conn_close.val_id = conn->val_id;\n\n    flush_buff(conn); /* First flush buffer */\n    res = lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n    if (res == lwespOK && !blocking) { /* Function succedded in non-blocking mode */\n        lwesp_core_lock();\n        LWESP_DEBUGF(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, \"[LWESP CONN] Connection %d set to closing state\\r\\n\",\n                     (int)conn->num);\n        conn->status.f.in_closing = 1; /* Connection is in closing mode but not yet closed */\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n/**\n * \\brief           Send data on active connection of type UDP to specific remote IP and port\n * \\note            In case IP and port values are not set, it will behave as normal send function (suitable for TCP too)\n * \\param[in]       conn: Connection handle to send data\n * \\param[in]       ip: Remote IP address for UDP connection\n * \\param[in]       port: Remote port connection\n * \\param[in]       data: Pointer to data to send\n * \\param[in]       btw: Number of bytes to send\n * \\param[out]      bw: Pointer to output variable to save number of sent data when successfully sent\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_sendto(lwesp_conn_p conn, const lwesp_ip_t* const ip, lwesp_port_t port, const void* data, size_t btw,\n                  size_t* bw, const uint32_t blocking) {\n    LWESP_ASSERT(conn != NULL);\n\n    flush_buff(conn); /* Flush currently written memory if exists */\n    return prv_conn_send(conn, ip, port, data, btw, bw, 0, blocking);\n}\n\n/**\n * \\brief           Send data on already active connection either as client or server\n * \\param[in]       conn: Connection handle to send data\n * \\param[in]       data: Data to send\n * \\param[in]       btw: Number of bytes to send\n * \\param[out]      bw: Pointer to output variable to save number of sent data when successfully sent.\n *                      Parameter value might not be accurate if you combine \\ref lwesp_conn_write and \\ref lwesp_conn_send functions\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_send(lwesp_conn_p conn, const void* data, size_t btw, size_t* const bw, const uint32_t blocking) {\n    lwespr_t res;\n    const uint8_t* d = data;\n\n    LWESP_ASSERT(conn != NULL);\n    LWESP_ASSERT(data != NULL);\n    LWESP_ASSERT(btw > 0);\n\n    lwesp_core_lock();\n    if (conn->buff.buff != NULL) { /* Check if memory available */\n        size_t to_copy;\n        to_copy = LWESP_MIN(btw, conn->buff.len - conn->buff.ptr);\n        if (to_copy > 0) {\n            LWESP_MEMCPY(&conn->buff.buff[conn->buff.ptr], d, to_copy);\n            conn->buff.ptr += to_copy;\n            d += to_copy;\n            btw -= to_copy;\n        }\n    }\n    lwesp_core_unlock();\n    res = flush_buff(conn); /* Flush currently written memory if exists */\n    if (btw > 0) {          /* Check for remaining data */\n        res = prv_conn_send(conn, NULL, 0, d, btw, bw, 0, blocking);\n    }\n    return res;\n}\n\n/**\n * \\brief           Notify connection about received data which means connection is ready to accept more data\n *\n * Once data reception is confirmed, stack will try to send more data to user.\n *\n * \\note            Since this feature is not supported yet by AT commands, function is only prototype\n *                  and should be used in connection callback when data are received\n *\n * \\note            Function is not thread safe and may only be called from connection event function\n *\n * \\param[in]       conn: Connection handle\n * \\param[in]       pbuf: Packet buffer received on connection\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_recved(lwesp_conn_p conn, lwesp_pbuf_p pbuf) {\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n    size_t len;\n    len = lwesp_pbuf_length(pbuf, 1);     /* Get length of pbuf */\n    if (conn->tcp_not_ack_bytes >= len) { /* Check length of not-acknowledged bytes */\n        conn->tcp_not_ack_bytes -= len;\n    } else {\n        /* Warning here, de-sync happened somewhere! */\n    }\n    lwespi_conn_manual_tcp_try_read_data(conn); /* Try to read more connection data */\n#else\n    LWESP_UNUSED(conn);\n    LWESP_UNUSED(pbuf);\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n    return lwespOK;\n}\n\n/**\n * \\brief           Set argument variable for connection\n * \\param[in]       conn: Connection handle to set argument\n * \\param[in]       arg: Pointer to argument\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n * \\sa              lwesp_conn_get_arg\n */\nlwespr_t\nlwesp_conn_set_arg(lwesp_conn_p conn, void* const arg) {\n    lwesp_core_lock();\n    conn->arg = arg; /* Set argument for connection */\n    lwesp_core_unlock();\n    return lwespOK;\n}\n\n/**\n * \\brief           Get user defined connection argument\n * \\param[in]       conn: Connection handle to get argument\n * \\return          User argument\n * \\sa              lwesp_conn_set_arg\n */\nvoid*\nlwesp_conn_get_arg(lwesp_conn_p conn) {\n    void* arg;\n    lwesp_core_lock();\n    arg = conn->arg; /* Set argument for connection */\n    lwesp_core_unlock();\n    return arg;\n}\n\n/**\n * \\brief           Gets connections status\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_get_conns_status(const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSTATUS;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Check if connection type is client\n * \\param[in]       conn: Pointer to connection to check for status\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_conn_is_client(lwesp_conn_p conn) {\n    uint8_t res = 0;\n    if (conn != NULL && lwespi_is_valid_conn_ptr(conn)) {\n        lwesp_core_lock();\n        res = conn->status.f.active && conn->status.f.client;\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n/**\n * \\brief           Check if connection type is server\n * \\param[in]       conn: Pointer to connection to check for status\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_conn_is_server(lwesp_conn_p conn) {\n    uint8_t res = 0;\n    if (conn != NULL && lwespi_is_valid_conn_ptr(conn)) {\n        lwesp_core_lock();\n        res = conn->status.f.active && !conn->status.f.client;\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n/**\n * \\brief           Check if connection is active\n * \\param[in]       conn: Pointer to connection to check for status\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_conn_is_active(lwesp_conn_p conn) {\n    uint8_t res = 0;\n    if (conn != NULL && lwespi_is_valid_conn_ptr(conn)) {\n        lwesp_core_lock();\n        res = conn->status.f.active;\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n/**\n * \\brief           Check if connection is closed\n * \\param[in]       conn: Pointer to connection to check for status\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_conn_is_closed(lwesp_conn_p conn) {\n    uint8_t res = 0;\n    if (conn != NULL && lwespi_is_valid_conn_ptr(conn)) {\n        lwesp_core_lock();\n        res = !conn->status.f.active;\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n/**\n * \\brief           Get the number from connection\n * \\param[in]       conn: Connection pointer\n * \\return          Connection number in case of success or -1 on failure\n */\nint8_t\nlwesp_conn_getnum(lwesp_conn_p conn) {\n    int8_t res = -1;\n    if (conn != NULL && lwespi_is_valid_conn_ptr(conn)) {\n        /* Protection not needed as every connection has always the same number */\n        res = (int8_t)conn->num; /* Get number */\n    }\n    return res;\n}\n\n/**\n * \\brief           Set internal buffer size for SSL connection on ESP device\n * \\note            Use this function before you start first SSL connection\n * \\param[in]       size: Size of buffer in units of bytes. Valid range is between 2048 and 4096 bytes\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_set_ssl_buffersize(size_t size, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSSLSIZE;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sslsize.size = size;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get connection from connection based event\n * \\param[in]       evt: Event which happened for connection\n * \\return          Connection pointer on success, `NULL` otherwise\n */\nlwesp_conn_p\nlwesp_conn_get_from_evt(lwesp_evt_t* evt) {\n    switch (evt->type) {\n        case LWESP_EVT_CONN_ACTIVE: return lwesp_evt_conn_active_get_conn(evt);\n        case LWESP_EVT_CONN_CLOSE: return lwesp_evt_conn_close_get_conn(evt);\n        case LWESP_EVT_CONN_RECV: return lwesp_evt_conn_recv_get_conn(evt);\n        case LWESP_EVT_CONN_SEND: return lwesp_evt_conn_send_get_conn(evt);\n        case LWESP_EVT_CONN_POLL: return lwesp_evt_conn_poll_get_conn(evt);\n        default: return NULL;\n    }\n}\n\n/**\n * \\brief           Write data to connection buffer and if it is full, send it non-blocking way\n * \\note            This function may only be called from core (connection callbacks)\n * \\param[in]       conn: Connection to write\n * \\param[in]       data: Data to copy to write buffer\n * \\param[in]       btw: Number of bytes to write\n * \\param[in]       flush: Flush flag. Set to `1` if you want to send data immediately after copying\n * \\param[out]      mem_available: Available memory size in current write buffer.\n *                  When the buffer length is reached, current one is sent and a new one is automatically created.\n *                  If function returns \\ref lwespOK and `*mem_available = 0`, there was a problem\n *                  allocating a new buffer for next operation\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_write(lwesp_conn_p conn, const void* data, size_t btw, uint8_t flush, size_t* const mem_available) {\n    size_t len;\n    const uint8_t* d = data;\n\n    LWESP_ASSERT(conn != NULL);\n\n    /*\n     * Steps during write process:\n     *\n     * 1. Check if we have buffer already allocated and\n     *      write data to the tail of the buffer\n     *   1.1. In case buffer is full, send it non-blocking,\n     *      and enable freeing after it is sent\n     * 2. Check how many bytes we can copy as single buffer directly and send\n     * 3. Create last buffer and copy remaining data to it even if no remaining data\n     *      This is useful when calling function with no parameters (len = 0)\n     * 4. Flush (send) current buffer if necessary\n     */\n\n    /* Step 1 */\n    if (conn->buff.buff != NULL) {\n        len = LWESP_MIN(conn->buff.len - conn->buff.ptr, btw);\n        LWESP_MEMCPY(&conn->buff.buff[conn->buff.ptr], d, len);\n\n        d += len;\n        btw -= len;\n        conn->buff.ptr += len;\n\n        /* Step 1.1 */\n        if (conn->buff.ptr == conn->buff.len || flush) {\n            /* Try to send to processing queue in non-blocking way */\n            if (prv_conn_send(conn, NULL, 0, conn->buff.buff, conn->buff.ptr, NULL, 1, 0) != lwespOK) {\n                LWESP_DEBUGF(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, \"[LWESP CONN] Free write buffer: %p\\r\\n\",\n                             conn->buff.buff);\n                lwesp_mem_free_s((void**)&conn->buff.buff);\n            }\n            conn->buff.buff = NULL;\n        }\n    }\n\n    /* Step 2 */\n    while (btw >= LWESP_CFG_CONN_MAX_DATA_LEN) {\n        uint8_t* buff;\n        buff = lwesp_mem_malloc(sizeof(*buff) * LWESP_CFG_CONN_MAX_DATA_LEN);\n        if (buff != NULL) {\n            LWESP_MEMCPY(buff, d, LWESP_CFG_CONN_MAX_DATA_LEN); /* Copy data to buffer */\n            if (prv_conn_send(conn, NULL, 0, buff, LWESP_CFG_CONN_MAX_DATA_LEN, NULL, 1, 0) != lwespOK) {\n                LWESP_DEBUGF(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, \"[LWESP CONN] Free write buffer: %p\\r\\n\",\n                             (void*)buff);\n                lwesp_mem_free_s((void**)&buff);\n                return lwespERRMEM;\n            }\n        } else {\n            return lwespERRMEM;\n        }\n\n        btw -= LWESP_CFG_CONN_MAX_DATA_LEN; /* Decrease remaining length */\n        d += LWESP_CFG_CONN_MAX_DATA_LEN;   /* Advance data pointer */\n    }\n\n    /* Step 3 */\n    if (conn->buff.buff == NULL) {\n        conn->buff.buff = lwesp_mem_malloc(sizeof(*conn->buff.buff) * LWESP_CFG_CONN_MAX_DATA_LEN);\n        conn->buff.len = LWESP_CFG_CONN_MAX_DATA_LEN;\n        conn->buff.ptr = 0;\n\n        LWESP_DEBUGW(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, conn->buff.buff != NULL,\n                     \"[LWESP CONN] New write buffer allocated, addr = %p\\r\\n\", conn->buff.buff);\n        LWESP_DEBUGW(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, conn->buff.buff == NULL,\n                     \"[LWESP CONN] Cannot allocate new write buffer\\r\\n\");\n    }\n    if (btw > 0) {\n        if (conn->buff.buff != NULL) {\n            LWESP_MEMCPY(conn->buff.buff, d, btw); /* Copy data to memory */\n            conn->buff.ptr = btw;\n        } else {\n            return lwespERRMEM;\n        }\n    }\n\n    /* Step 4 */\n    if (flush && conn->buff.buff != NULL) {\n        flush_buff(conn);\n    }\n\n    /* Calculate number of available memory after write operation */\n    if (mem_available != NULL) {\n        if (conn->buff.buff != NULL) {\n            *mem_available = conn->buff.len - conn->buff.ptr;\n        } else {\n            *mem_available = 0;\n        }\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Get total number of bytes ever received on connection and sent to user\n * \\param[in]       conn: Connection handle\n * \\return          Total number of received bytes on connection\n */\nsize_t\nlwesp_conn_get_total_recved_count(lwesp_conn_p conn) {\n    size_t tot = 0;\n\n    if (conn != NULL) {\n        lwesp_core_lock();\n        tot = conn->total_recved; /* Get total received bytes */\n        lwesp_core_unlock();\n    }\n    return tot;\n}\n\n/**\n * \\brief           Get connection remote IP address\n * \\param[in]       conn: Connection handle\n * \\param[out]      ip: Pointer to IP output handle\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_conn_get_remote_ip(lwesp_conn_p conn, lwesp_ip_t* ip) {\n    if (conn != NULL && ip != NULL) {\n        lwesp_core_lock();\n        LWESP_MEMCPY(ip, &conn->remote_ip, sizeof(*ip)); /* Copy data */\n        lwesp_core_unlock();\n        return 1;\n    }\n    return 0;\n}\n\n/**\n * \\brief           Get connection remote port number\n * \\param[in]       conn: Connection handle\n * \\return          Port number on success, `0` otherwise\n */\nlwesp_port_t\nlwesp_conn_get_remote_port(lwesp_conn_p conn) {\n    lwesp_port_t port = 0;\n    if (conn != NULL) {\n        lwesp_core_lock();\n        port = conn->remote_port;\n        lwesp_core_unlock();\n    }\n    return port;\n}\n\n/**\n * \\brief           Get connection local port number\n * \\param[in]       conn: Connection handle\n * \\return          Port number on success, `0` otherwise\n */\nlwesp_port_t\nlwesp_conn_get_local_port(lwesp_conn_p conn) {\n    lwesp_port_t port = 0;\n    if (conn != NULL) {\n        lwesp_core_lock();\n        port = conn->local_port;\n        lwesp_core_unlock();\n    }\n    return port;\n}\n\n/**\n * \\brief           Configure SSL parameters\n * \\param[in]       link_id: ID of the connection (0~max), for multiple connections, if the value is max, it means all connections.\n *                      By default, max is \\ref LWESP_CFG_MAX_CONNS.\n * \\param[in]       auth_mode: Authentication mode\n *                      `0`: no authorization\n *                      `1`: load cert and private key for server authorization\n *                      `2`: load CA for client authorize server cert and private key\n *                      `3`: both authorization\n * \\param[in]       pki_number:  The index of cert and private key, if only one cert and private key, the value should be `0`.\n * \\param[in]       ca_number: The index of CA, if only one CA, the value should be 0.\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_conn_ssl_set_config(uint8_t link_id, uint8_t auth_mode, uint8_t pki_number, uint8_t ca_number,\n                          const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSSLCCONF;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_ssl_cfg.link_id = LWESP_MIN(link_id, LWESP_CFG_MAX_CONNS);\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_ssl_cfg.auth_mode = LWESP_MIN(auth_mode, 3);\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_ssl_cfg.pki_number = pki_number;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_ssl_cfg.ca_number = ca_number;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_debug.c",
    "content": "/**\n * \\file            lwesp_debug.c\n * \\brief           Debugging inside ESP stack\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_debug.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_DBG || __DOXYGEN__\n\nconst char*\nlwespi_dbg_msg_to_string(lwesp_cmd_t cmd) {\n    static char tmp_arr[100];\n    if (cmd) {\n        sprintf(tmp_arr, \"%d\", (int)cmd);\n        return tmp_arr;\n    }\n    return \"\";\n}\n\n#endif /* LWESP_CFG_DBG || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_dhcp.c",
    "content": "/**\n * \\file            lwesp_dhcp.c\n * \\brief           DHCP API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_dhcp.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/**\n * \\brief           Configure DHCP settings for station or access point (or both)\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\param[in]       sta: Set to `1` to affect station DHCP configuration, set to `0` to keep current setup\n * \\param[in]       ap: Set to `1` to affect access point DHCP configuration, set to `0` to keep current setup\n * \\param[in]       en: Set to `1` to enable DHCP, or `0` to disable (static IP)\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_dhcp_set_config(uint8_t sta, uint8_t ap, uint8_t en, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                      const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWDHCP_SET;\n    LWESP_MSG_VAR_REF(msg).msg.wifi_cwdhcp.sta = sta;\n    LWESP_MSG_VAR_REF(msg).msg.wifi_cwdhcp.ap = ap;\n    LWESP_MSG_VAR_REF(msg).msg.wifi_cwdhcp.en = en;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_dns.c",
    "content": "/**\n * \\file            lwesp_dns.c\n * \\brief           DNS API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_dns.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_DNS || __DOXYGEN__\n\n/**\n * \\brief           Get IP address from host name\n * \\param[in]       host: Pointer to host name to get IP for\n * \\param[out]      ip: Pointer to \\ref lwesp_ip_t variable to save IP\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_dns_gethostbyname(const char* host, lwesp_ip_t* const ip, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                        const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(host != NULL);\n    LWESP_ASSERT(ip != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPDOMAIN;\n    LWESP_MSG_VAR_REF(msg).msg.dns_getbyhostname.host = host;\n    LWESP_MSG_VAR_REF(msg).msg.dns_getbyhostname.ip = ip;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 20000);\n}\n\n/**\n * \\brief           Enable or disable custom DNS server configuration\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\param[in]       en: Set to `1` to enable, `0` to disable custom DNS configuration.\n *                  When disabled, default DNS servers are used as proposed by ESP AT commands firmware\n * \\param[in]       s1: First server IP address in string format, set to `NULL` if not used\n * \\param[in]       s2: Second server IP address in string format, set to `NULL` if not used.\n *                  Address `s1` cannot be the same as `s2`\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_dns_set_config(uint8_t en, const char* s1, const char* s2, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                     const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPDNS_SET;\n    LWESP_MSG_VAR_REF(msg).msg.dns_setconfig.en = en;\n    LWESP_MSG_VAR_REF(msg).msg.dns_setconfig.s1 = s1;\n    LWESP_MSG_VAR_REF(msg).msg.dns_setconfig.s2 = s2;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get the DNS server configuration\n *\n * Retrive configuration saved in the NVS area of ESP device.\n *\n * \\param[out]      s1: First server IP address in lwesp_ip_t format, set to 0.0.0.0 if not used\n * \\param[out]      s2: Second server IP address in lwesp_ip_t format, set to to 0.0.0.0 if not used.\n *                  Address `s1` cannot be the same as `s2`\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_dns_get_config(lwesp_ip_t* s1, lwesp_ip_t* s2, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                     const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPDNS_GET;\n    LWESP_MSG_VAR_REF(msg).msg.dns_getconf.s1 = s1;\n    LWESP_MSG_VAR_REF(msg).msg.dns_getconf.s2 = s2;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n#endif /* LWESP_CFG_DNS || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_evt.c",
    "content": "/**\n * \\file            lwesp_evt.c\n * \\brief           Event helper functions\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_evt.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/**\n * \\brief           Register event function for global (non-connection based) events\n * \\param[in]       fn: Callback function to call on specific event\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_evt_register(lwesp_evt_fn fn) {\n    lwespr_t res = lwespOK;\n    lwesp_evt_func_t *func, *new_func;\n\n    LWESP_ASSERT(fn != NULL);\n\n    lwesp_core_lock();\n\n    /* Check if function already exists on list */\n    for (func = esp.evt_func; func != NULL; func = func->next) {\n        if (func->fn == fn) {\n            res = lwespERR;\n            break;\n        }\n    }\n\n    if (res == lwespOK) {\n        new_func = lwesp_mem_malloc(sizeof(*new_func));\n        if (new_func != NULL) {\n            LWESP_MEMSET(new_func, 0x00, sizeof(*new_func));\n            new_func->fn = fn; /* Set function pointer */\n            for (func = esp.evt_func; func != NULL && func->next != NULL; func = func->next) {}\n            if (func != NULL) {\n                func->next = new_func; /* Set new function as next */\n                res = lwespOK;\n            } else {\n                lwesp_mem_free_s((void**)&new_func);\n                res = lwespERRMEM;\n            }\n        } else {\n            res = lwespERRMEM;\n        }\n    }\n    lwesp_core_unlock();\n    return res;\n}\n\n/**\n * \\brief           Unregister callback function for global (non-connection based) events\n * \\note            Function must be first registered using \\ref lwesp_evt_register\n * \\param[in]       fn: Callback function to remove from event list\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_evt_unregister(lwesp_evt_fn fn) {\n    lwesp_evt_func_t *func, *prev;\n\n    LWESP_ASSERT(fn != NULL);\n\n    lwesp_core_lock();\n    for (prev = esp.evt_func, func = esp.evt_func->next; func != NULL; prev = func, func = func->next) {\n        if (func->fn == fn) {\n            prev->next = func->next;\n            lwesp_mem_free_s((void**)&func);\n            break;\n        }\n    }\n    lwesp_core_unlock();\n    return lwespOK;\n}\n\n/**\n * \\brief           Get event type\n * \\param[in]       cc: Event handle\n * \\return          Event type. Member of \\ref lwesp_evt_type_t enumeration\n */\nlwesp_evt_type_t\nlwesp_evt_get_type(lwesp_evt_t* cc) {\n    return cc->type;\n}\n\n/**\n * \\brief           Check if detected reset was forced by user\n * \\param[in]       cc: Event handle\n * \\return          `1` if forced by user, `0` otherwise\n */\nuint8_t\nlwesp_evt_reset_detected_is_forced(lwesp_evt_t* cc) {\n    return LWESP_U8(!!cc->evt.reset_detected.forced);\n}\n\n/**\n * \\brief           Get reset sequence operation status\n * \\param[in]       cc: Event data\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_reset_get_result(lwesp_evt_t* cc) {\n    return cc->evt.reset.res;\n}\n\n/**\n * \\brief           Get restore sequence operation status\n * \\param[in]       cc: Event data\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_restore_get_result(lwesp_evt_t* cc) {\n    return cc->evt.restore.res;\n}\n\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n\n/**\n * \\brief           Get MAC address from station\n * \\param[in]       cc: Event handle\n * \\return          MAC address\n */\nlwesp_mac_t*\nlwesp_evt_ap_ip_sta_get_mac(lwesp_evt_t* cc) {\n    return cc->evt.ap_ip_sta.mac;\n}\n\n/**\n * \\brief           Get IP address from station\n * \\param[in]       cc: Event handle\n * \\return          IP address\n */\nlwesp_ip_t*\nlwesp_evt_ap_ip_sta_get_ip(lwesp_evt_t* cc) {\n    return cc->evt.ap_ip_sta.ip;\n}\n\n/**\n * \\brief           Get MAC address from connected station\n * \\param[in]       cc: Event handle\n * \\return          MAC address\n */\nlwesp_mac_t*\nlwesp_evt_ap_connected_sta_get_mac(lwesp_evt_t* cc) {\n    return cc->evt.ap_conn_disconn_sta.mac;\n}\n\n/**\n * \\brief           Get MAC address from disconnected station\n * \\param[in]       cc: Event handle\n * \\return          MAC address\n */\nlwesp_mac_t*\nlwesp_evt_ap_disconnected_sta_get_mac(lwesp_evt_t* cc) {\n    return cc->evt.ap_conn_disconn_sta.mac;\n}\n\n#endif /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n\n/**\n * \\brief           Get buffer from received data\n * \\param[in]       cc: Event handle\n * \\return          Buffer handle\n */\nlwesp_pbuf_p\nlwesp_evt_conn_recv_get_buff(lwesp_evt_t* cc) {\n    return cc->evt.conn_data_recv.buff;\n}\n\n/**\n * \\brief           Get connection handle for receive\n * \\param[in]       cc: Event handle\n * \\return          Connection handle\n */\nlwesp_conn_p\nlwesp_evt_conn_recv_get_conn(lwesp_evt_t* cc) {\n    return cc->evt.conn_data_recv.conn;\n}\n\n/**\n * \\brief           Get connection handle for data sent event\n * \\param[in]       cc: Event handle\n * \\return          Connection handle\n */\nlwesp_conn_p\nlwesp_evt_conn_send_get_conn(lwesp_evt_t* cc) {\n    return cc->evt.conn_data_send.conn;\n}\n\n/**\n * \\brief           Get number of bytes sent on connection\n * \\param[in]       cc: Event handle\n * \\return          Number of bytes sent\n */\nsize_t\nlwesp_evt_conn_send_get_length(lwesp_evt_t* cc) {\n    return cc->evt.conn_data_send.sent;\n}\n\n/**\n * \\brief           Check if connection send was successful\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_conn_send_get_result(lwesp_evt_t* cc) {\n    return cc->evt.conn_data_send.res;\n}\n\n/**\n * \\brief           Get connection handle\n * \\param[in]       cc: Event handle\n * \\return          Connection handle\n */\nlwesp_conn_p\nlwesp_evt_conn_active_get_conn(lwesp_evt_t* cc) {\n    return cc->evt.conn_active_close.conn;\n}\n\n/**\n * \\brief           Check if new connection is client\n * \\param[in]       cc: Event handle\n * \\return          `1` if client, `0` otherwise\n */\nuint8_t\nlwesp_evt_conn_active_is_client(lwesp_evt_t* cc) {\n    return LWESP_U8(cc->evt.conn_active_close.client > 0);\n}\n\n/**\n * \\brief           Get connection handle\n * \\param[in]       cc: Event handle\n * \\return          Connection handle\n */\nlwesp_conn_p\nlwesp_evt_conn_close_get_conn(lwesp_evt_t* cc) {\n    return cc->evt.conn_active_close.conn;\n}\n\n/**\n * \\brief           Check if just closed connection was client\n * \\param[in]       cc: Event handle\n * \\return          `1` if client, `0` otherwise\n */\nuint8_t\nlwesp_evt_conn_close_is_client(lwesp_evt_t* cc) {\n    return cc->evt.conn_active_close.client;\n}\n\n/**\n * \\brief           Check if connection close even was forced by user\n * \\param[in]       cc: Event handle\n * \\return          `1` if forced, `0` otherwise\n */\nuint8_t\nlwesp_evt_conn_close_is_forced(lwesp_evt_t* cc) {\n    return cc->evt.conn_active_close.forced;\n}\n\n/**\n * \\brief           Get connection close event result\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_conn_close_get_result(lwesp_evt_t* cc) {\n    return cc->evt.conn_active_close.res;\n}\n\n/**\n * \\brief           Get connection handle\n * \\param[in]       cc: Event handle\n * \\return          Connection handle\n */\nlwesp_conn_p\nlwesp_evt_conn_poll_get_conn(lwesp_evt_t* cc) {\n    return cc->evt.conn_poll.conn;\n}\n\n/**\n * \\brief           Get connection error type\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_conn_error_get_error(lwesp_evt_t* cc) {\n    return cc->evt.conn_error.err;\n}\n\n/**\n * \\brief           Get connection type\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwesp_conn_type_t\nlwesp_evt_conn_error_get_type(lwesp_evt_t* cc) {\n    return cc->evt.conn_error.type;\n}\n\n/**\n * \\brief           Get connection host\n * \\param[in]       cc: Event handle\n * \\return          Host name for connection\n */\nconst char*\nlwesp_evt_conn_error_get_host(lwesp_evt_t* cc) {\n    return cc->evt.conn_error.host;\n}\n\n/**\n * \\brief           Get connection port\n * \\param[in]       cc: Event handle\n * \\return          Host port number\n */\nlwesp_port_t\nlwesp_evt_conn_error_get_port(lwesp_evt_t* cc) {\n    return cc->evt.conn_error.port;\n}\n\n/**\n * \\brief           Get user argument\n * \\param[in]       cc: Event handle\n * \\return          User argument\n */\nvoid*\nlwesp_evt_conn_error_get_arg(lwesp_evt_t* cc) {\n    return cc->evt.conn_error.arg;\n}\n\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n\n/**\n * \\brief           Get command success result\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_sta_list_ap_get_result(lwesp_evt_t* cc) {\n    return cc->evt.sta_list_ap.res;\n}\n\n/**\n * \\brief           Get access points\n * \\param[in]       cc: Event handle\n * \\return          Pointer to \\ref lwesp_ap_t with first access point description\n */\nlwesp_ap_t*\nlwesp_evt_sta_list_ap_get_aps(lwesp_evt_t* cc) {\n    return cc->evt.sta_list_ap.aps;\n}\n\n/**\n * \\brief           Get number of access points found\n * \\param[in]       cc: Event handle\n * \\return          Number of access points found\n */\nsize_t\nlwesp_evt_sta_list_ap_get_length(lwesp_evt_t* cc) {\n    return cc->evt.sta_list_ap.len;\n}\n\n/**\n * \\brief           Get command success result\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_sta_join_ap_get_result(lwesp_evt_t* cc) {\n    return cc->evt.sta_join_ap.res;\n}\n\n/**\n * \\brief           Get current AP name\n * \\param[in]       cc: Event handle\n * \\return          AP name\n */\nconst char*\nlwesp_evt_sta_info_ap_get_ssid(lwesp_evt_t* cc) {\n    return cc->evt.sta_info_ap.info->ssid;\n}\n\n/**\n * \\brief           Get current AP MAC address\n * \\param[in]       cc: Event handle\n * \\return          AP MAC address\n */\nlwesp_mac_t\nlwesp_evt_sta_info_ap_get_mac(lwesp_evt_t* cc) {\n    return cc->evt.sta_info_ap.info->mac;\n}\n\n/**\n * \\brief           Get current AP channel\n * \\param[in]       cc: Event handle\n * \\return          AP channel\n */\nuint8_t\nlwesp_evt_sta_info_ap_get_channel(lwesp_evt_t* cc) {\n    return cc->evt.sta_info_ap.info->ch;\n}\n\n/**\n * \\brief           Get current AP rssi\n * \\param[in]       cc: Event handle\n * \\return          AP rssi\n */\nint16_t\nlwesp_evt_sta_info_ap_get_rssi(lwesp_evt_t* cc) {\n    return cc->evt.sta_info_ap.info->rssi;\n}\n\n/**\n * \\brief           Get command result\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_sta_info_ap_get_result(lwesp_evt_t* cc) {\n    return cc->evt.sta_info_ap.res;\n}\n\n#endif /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n\n#if LWESP_CFG_DNS || __DOXYGEN__\n\n/**\n * \\brief           Get resolve result\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_dns_hostbyname_get_result(lwesp_evt_t* cc) {\n    return cc->evt.dns_hostbyname.res;\n}\n\n/**\n * \\brief           Get hostname used to resolve IP address\n * \\param[in]       cc: Event handle\n * \\return          Hostname\n */\nconst char*\nlwesp_evt_dns_hostbyname_get_host(lwesp_evt_t* cc) {\n    return cc->evt.dns_hostbyname.host;\n}\n\n/**\n * \\brief           Get IP address from DNS function\n * \\param[in]       cc: Event handle\n * \\return          IP address\n */\nlwesp_ip_t*\nlwesp_evt_dns_hostbyname_get_ip(lwesp_evt_t* cc) {\n    return cc->evt.dns_hostbyname.ip;\n}\n\n#endif /* LWESP_CFG_DNS || __DOXYGEN__ */\n\n#if LWESP_CFG_PING || __DOXYGEN__\n\n/**\n * \\brief           Get ping status\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_ping_get_result(lwesp_evt_t* cc) {\n    return cc->evt.ping.res;\n}\n\n/**\n * \\brief           Get hostname used to ping\n * \\param[in]       cc: Event handle\n * \\return          Hostname\n */\nconst char*\nlwesp_evt_ping_get_host(lwesp_evt_t* cc) {\n    return cc->evt.ping.host;\n}\n\n/**\n * \\brief           Get time required for ping\n * \\param[in]       cc: Event handle\n * \\return          Ping time\n */\nuint32_t\nlwesp_evt_ping_get_time(lwesp_evt_t* cc) {\n    return cc->evt.ping.time;\n}\n\n#endif /* LWESP_CFG_PING || __DOXYGEN__ */\n\n#if LWESP_CFG_SNTP || __DOXYGEN__\n\n/**\n * \\brief           Get command success result\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_sntp_time_get_result(lwesp_evt_t* cc) {\n    return cc->evt.cip_sntp_time.res;\n}\n\n/**\n * \\brief           Get date time pointer with data\n * \\param[in]       cc: Event handle\n * \\return          pointer to read-only structure with datetime\n */\nconst struct tm*\nlwesp_evt_sntp_time_get_datetime(lwesp_evt_t* cc) {\n    return cc->evt.cip_sntp_time.dt;\n}\n\n#endif /* LWESP_CFG_SNTP || __DOXYGEN__ */\n\n#if LWESP_CFG_WEBSERVER || __DOXYGEN__\n\n/**\n * \\brief           Get web server status\n * \\param[in]       cc: Event handle\n * \\return          Web server status code\n */\nuint8_t\nlwesp_evt_webserver_get_status(lwesp_evt_t* cc) {\n    return cc->evt.ws_status.code;\n}\n\n#endif /* LWESP_CFG_WEBSERVER || __DOXYGEN__ */\n\n/**\n * \\brief           Get server command result\n * \\param[in]       cc: Event handle\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwesp_evt_server_get_result(lwesp_evt_t* cc) {\n    return cc->evt.server.res;\n}\n\n/**\n * \\brief           Get port for server operation\n * \\param[in]       cc: Event handle\n * \\return          Server port\n */\nlwesp_port_t\nlwesp_evt_server_get_port(lwesp_evt_t* cc) {\n    return cc->evt.server.port;\n}\n\n/**\n* \\brief           Check if operation was to enable or disable server\n* \\param[in]       cc: Event handle\n* \\return          `1` if enable, `0` otherwise\n*/\nuint8_t\nlwesp_evt_server_is_enable(lwesp_evt_t* cc) {\n    return cc->evt.server.en;\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_flash.c",
    "content": "/**\n * \\file            lwesp_flash.c\n * \\brief           System flash API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_flash.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_FLASH || __DOXYGEN__\n\n/**\n * \\brief           Erase flash block\n * \\param[in]       partition: Partition to do erase operation on\n * \\param[in]       offset: Offset from start of partition. Must be `4kB` aligned when used.\n *                      Set to `0` to erase full partition\n * \\param[in]       length: Size to erase. Must be `4kB` aligned when used.\n *                      Set to `0` to erase full partition\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_flash_erase(lwesp_flash_partition_t partition, uint32_t offset, uint32_t length,\n                  const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    /* Check alignment if used */\n    LWESP_ASSERT((offset == 0 || (offset & 0x0FFF) == 0) && (length == 0 || (length & 0x0FFF) == 0));\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_SYSFLASH_ERASE;\n    LWESP_MSG_VAR_REF(msg).msg.flash_erase.partition = partition;\n    LWESP_MSG_VAR_REF(msg).msg.flash_erase.offset = offset;\n    LWESP_MSG_VAR_REF(msg).msg.flash_erase.length = length;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 5000);\n}\n\n/**\n * \\brief           Write data to flash partition\n * \\param[in]       partition: Partition to write to\n * \\param[in]       offset: Offset from start of partition to start writing at\n * \\param[in]       data: Actual data to write. Must not be `NULL`\n * \\param[in]       length: Number of bytes to write\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_flash_write(lwesp_flash_partition_t partition, uint32_t offset, const void* data, uint32_t length,\n                  const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(length > 0);\n    LWESP_ASSERT(data != NULL);\n    LWESP_ASSERT(partition < LWESP_FLASH_PARTITION_END);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_SYSFLASH_WRITE;\n    LWESP_MSG_VAR_REF(msg).msg.flash_write.partition = partition;\n    LWESP_MSG_VAR_REF(msg).msg.flash_write.offset = offset;\n    LWESP_MSG_VAR_REF(msg).msg.flash_write.length = length;\n    LWESP_MSG_VAR_REF(msg).msg.flash_write.data = data;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 5000);\n}\n\n/**\n * \\brief           Write key-value pair into user MFG area.\n * \n * \\note            When writing into this section, no need to previously erase the data\n *                  System is smart enough to do this for us, if absolutely necessary\n * \n * \\param[in]       mfgns: User namespace option\n * \\param[in]       key: Key to write\n * \\param[in]       valtype: Value type to follow\n * \\param[in]       data: Pointer to data to write. If value type is primitive type,\n *                      then pointer is copied to the local structure. This means\n *                      even for non-blocking calls, user can safely use local variables for\n *                      data pointers.\n * \\param[in]       length: Length of data to write. It only makes sense for string and binary data types,\n *                      otherwise it is derived from value type parameter and can be set to `0` by user\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_mfg_write(lwesp_mfg_namespace_t mfgns, const char* key, lwesp_mfg_valtype_t valtype, const void* data,\n                uint32_t length, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(mfgns < LWESP_MFG_NAMESPACE_END);\n    LWESP_ASSERT(data != NULL);\n    LWESP_ASSERT(valtype != LWESP_MFG_VALTYPE_INVAL && valtype < LWESP_MFG_VALTYPE_END);\n    switch (valtype) {\n        case LWESP_MFG_VALTYPE_U8:\n        case LWESP_MFG_VALTYPE_I8: length = 1; break;\n        case LWESP_MFG_VALTYPE_U16:\n        case LWESP_MFG_VALTYPE_I16: length = 2; break;\n        case LWESP_MFG_VALTYPE_U32:\n        case LWESP_MFG_VALTYPE_I32: length = 4; break;\n        default: break; /* Length as-is */\n    }\n    LWESP_ASSERT(length > 0);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_SYSMFG_WRITE;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_write.namespace = mfgns;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_write.key = key;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_write.valtype = valtype;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_write.length = length;\n    if (LWESP_MFG_VALTYPE_IS_PRIM(valtype)) {\n        switch (valtype) {\n            case LWESP_MFG_VALTYPE_U8: LWESP_MSG_VAR_REF(msg).msg.mfg_write.data_prim.u8 = *(uint8_t*)data; break;\n            case LWESP_MFG_VALTYPE_I8: LWESP_MSG_VAR_REF(msg).msg.mfg_write.data_prim.i8 = *(int8_t*)data; break;\n            case LWESP_MFG_VALTYPE_U16: LWESP_MSG_VAR_REF(msg).msg.mfg_write.data_prim.u16 = *(uint16_t*)data; break;\n            case LWESP_MFG_VALTYPE_I16: LWESP_MSG_VAR_REF(msg).msg.mfg_write.data_prim.i16 = *(int16_t*)data; break;\n            case LWESP_MFG_VALTYPE_U32: LWESP_MSG_VAR_REF(msg).msg.mfg_write.data_prim.u32 = *(uint32_t*)data; break;\n            case LWESP_MFG_VALTYPE_I32: LWESP_MSG_VAR_REF(msg).msg.mfg_write.data_prim.i32 = *(int32_t*)data; break;\n            default: break; /* Length as-is */\n        }\n    } else {\n        LWESP_MSG_VAR_REF(msg).msg.mfg_write.data_ptr = data;\n    }\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 5000);\n}\n\n/**\n * \\brief           Read key-value pair into user MFG area.\n * \n * \\note            When writing into this section, no need to previously erase the data\n *                  System is smart enough to do this for us, if absolutely necessary\n * \n * \\param[in]       mfgns: User namespace option\n * \\param[in]       key: Key to ead\n * \\param[in]       data: Pointer to data to write received data to\n * \\param[in]       btr: Number of bytes to read\n * \\param[in]       offset: Offset from partition start to read data from\n * \\param[out]      br: Pointer to output variable to write number of bytes read\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_mfg_read(lwesp_mfg_namespace_t mfgns, const char* key, void* data, uint32_t btr, uint32_t offset, uint32_t* br,\n               const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(mfgns < LWESP_MFG_NAMESPACE_END);\n    LWESP_ASSERT(data != NULL);\n    LWESP_ASSERT(btr > 0);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_SYSMFG_READ;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_read.namespace = mfgns;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_read.key = key;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_read.offset = offset;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_read.btr = btr;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_read.br = br;\n    LWESP_MSG_VAR_REF(msg).msg.mfg_read.data_ptr = data;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 5000);\n}\n\n#endif /* LWESP_CFG_FLASH || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_hostname.c",
    "content": "/**\n * \\file            lwesp_hostname.c\n * \\brief           Hostname API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_hostname.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_HOSTNAME || __DOXYGEN__\n\n/**\n * \\brief           Set hostname of WiFi station\n * \\param[in]       hostname: Name of ESP host\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_hostname_set(const char* hostname, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                   const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(hostname != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWHOSTNAME_SET;\n    LWESP_MSG_VAR_REF(msg).msg.wifi_hostname.hostname_set = hostname;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get hostname of WiFi station\n * \\param[in]       hostname: Pointer to output variable holding memory to save hostname\n * \\param[in]       size: Size of buffer for hostname. Size includes memory for `NULL` termination\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_hostname_get(char* hostname, size_t size, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                   const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(hostname != NULL);\n    LWESP_ASSERT(size > 0);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWHOSTNAME_GET;\n    LWESP_MSG_VAR_REF(msg).msg.wifi_hostname.hostname_get = hostname;\n    LWESP_MSG_VAR_REF(msg).msg.wifi_hostname.length = size;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n#endif /* LWESP_CFG_HOSTNAME || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_input.c",
    "content": "/**\n * \\file            lwesp_input.c\n * \\brief           Wrapper for passing input data to stack\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_input.h\"\n#include \"lwesp/lwesp_buff.h\"\n#include \"lwesp/lwesp_private.h\"\n\nstatic uint32_t lwesp_recv_total_len;\nstatic uint32_t lwesp_recv_calls;\n\n#if !LWESP_CFG_INPUT_USE_PROCESS || __DOXYGEN__\n\n/**\n * \\brief           Write data to input buffer\n * \\note            \\ref LWESP_CFG_INPUT_USE_PROCESS must be disabled to use this function\n * \\param[in]       data: Pointer to data to write\n * \\param[in]       len: Number of data elements in units of bytes\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_input(const void* data, size_t len) {\n    if (!esp.status.f.initialized || esp.buff.buff == NULL) {\n        return lwespERR;\n    }\n    lwesp_buff_write(&esp.buff, data, len);         /* Write data to buffer */\n    lwesp_sys_mbox_putnow(&esp.mbox_process, NULL); /* Write empty box, don't care if write fails */\n    lwesp_recv_total_len += len;                    /* Update total number of received bytes */\n    ++lwesp_recv_calls;                             /* Update number of calls */\n    return lwespOK;\n}\n\n#endif /* !LWESP_CFG_INPUT_USE_PROCESS || __DOXYGEN__ */\n\n#if LWESP_CFG_INPUT_USE_PROCESS || __DOXYGEN__\n\n/**\n * \\brief           Process input data directly without writing it to input buffer\n * \\note            This function may only be used when in OS mode,\n *                  where single thread is dedicated for input read of AT receive\n *\n * \\note            \\ref LWESP_CFG_INPUT_USE_PROCESS must be enabled to use this function\n *\n * \\param[in]       data: Pointer to received data to be processed\n * \\param[in]       len: Length of data to process in units of bytes\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_input_process(const void* data, size_t len) {\n    lwespr_t res = lwespOK;\n\n    if (!esp.status.f.initialized) {\n        return lwespERR;\n    }\n\n    lwesp_recv_total_len += len; /* Update total number of received bytes */\n    ++lwesp_recv_calls;          /* Update number of calls */\n\n    if (len > 0) {\n        lwesp_core_lock();\n        res = lwespi_process(data, len); /* Process input data */\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n#endif /* LWESP_CFG_INPUT_USE_PROCESS || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_int.c",
    "content": "/**\n * \\file            lwesp_int.c\n * \\brief           Internal functions\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_int.h\"\n#include \"lwesp/lwesp_parser.h\"\n#include \"lwesp/lwesp_private.h\"\n#include \"lwesp/lwesp_unicode.h\"\n#include \"system/lwesp_ll.h\"\n\n#if !__DOXYGEN__\n/**\n * \\brief           Receive character structure to handle full line terminated with `\\n` character\n */\ntypedef struct {\n    char data[128]; /*!< Received characters */\n    size_t len;     /*!< Length of valid characters */\n} lwesp_recv_t;\n\n/**\n * \\brief           Processing function status data\n */\ntypedef struct {\n    uint8_t is_ok;    /*!< Set to `1` if OK is set from the command processing */\n    uint8_t is_error; /*!< Set to `1` if error is set from the command processing */\n    uint8_t is_ready; /*!< Set to `1` if ready is received from command processing */\n} lwesp_status_flags_t;\n\n/* Receive character macros */\n#define RECV_ADD(ch)                                                                                                   \\\n    do {                                                                                                               \\\n        if (recv_buff.len < (sizeof(recv_buff.data)) - 1) {                                                            \\\n            recv_buff.data[recv_buff.len++] = ch;                                                                      \\\n            recv_buff.data[recv_buff.len] = 0;                                                                         \\\n        }                                                                                                              \\\n    } while (0)\n#define RECV_RESET()                                                                                                   \\\n    do {                                                                                                               \\\n        recv_buff.len = 0;                                                                                             \\\n        recv_buff.data[0] = 0;                                                                                         \\\n    } while (0)\n#define RECV_LEN()                  ((size_t)recv_buff.len)\n#define RECV_IDX(index)             recv_buff.data[index]\n\n/* Send data over AT port */\n#define AT_PORT_SEND_STR(str)       esp.ll.send_fn((const void*)(str), (size_t)strlen(str))\n#define AT_PORT_SEND_CONST_STR(str) esp.ll.send_fn((const void*)(str), (size_t)(sizeof(str) - 1))\n#define AT_PORT_SEND_CHR(str)       esp.ll.send_fn((const void*)(str), (size_t)1)\n#define AT_PORT_SEND_FLUSH()        esp.ll.send_fn(NULL, 0)\n#define AT_PORT_SEND(d, l)          esp.ll.send_fn((const void*)(d), (size_t)(l))\n#define AT_PORT_SEND_WITH_FLUSH(d, l)                                                                                  \\\n    do {                                                                                                               \\\n        AT_PORT_SEND((d), (l));                                                                                        \\\n        AT_PORT_SEND_FLUSH();                                                                                          \\\n    } while (0)\n\n/* Beginning and end of every AT command */\n#define AT_PORT_SEND_BEGIN_AT()                                                                                        \\\n    do {                                                                                                               \\\n        AT_PORT_SEND_CONST_STR(\"AT\");                                                                                  \\\n    } while (0)\n#define AT_PORT_SEND_END_AT()                                                                                          \\\n    do {                                                                                                               \\\n        AT_PORT_SEND(CRLF, CRLF_LEN);                                                                                  \\\n        AT_PORT_SEND_FLUSH();                                                                                          \\\n    } while (0)\n\n/* Send special characters over AT port with condition */\n#define AT_PORT_SEND_QUOTE_COND(q)                                                                                     \\\n    do {                                                                                                               \\\n        if ((q)) {                                                                                                     \\\n            AT_PORT_SEND_CONST_STR(\"\\\"\");                                                                              \\\n        }                                                                                                              \\\n    } while (0)\n#define AT_PORT_SEND_COMMA_COND(c)                                                                                     \\\n    do {                                                                                                               \\\n        if ((c)) {                                                                                                     \\\n            AT_PORT_SEND_CONST_STR(\",\");                                                                               \\\n        }                                                                                                              \\\n    } while (0)\n#define AT_PORT_SEND_EQUAL_COND(e)                                                                                     \\\n    do {                                                                                                               \\\n        if ((e)) {                                                                                                     \\\n            AT_PORT_SEND_CONST_STR(\"=\");                                                                               \\\n        }                                                                                                              \\\n    } while (0)\n#endif /* !__DOXYGEN__ */\n\n#if LWESP_CFG_FLASH\n/* Flash partitions */\nstatic const char* flash_partitions[] = {\n#define LWESP_FLASH_PARTITION(key, at_string) at_string,\n#define LWESP_MFG_NAMESPACE(key, at_string)\n#include \"lwesp/lwesp_flash_partitions.h\"\n};\n/* Manufactiring NVS partitions */\nstatic const char* mfg_namespaces[] = {\n#define LWESP_FLASH_PARTITION(key, at_string)\n#define LWESP_MFG_NAMESPACE(key, at_string) at_string,\n#include \"lwesp/lwesp_flash_partitions.h\"\n};\n#endif /* LWESP_CFG_FLASH */\n\nstatic uint16_t conn_val_id;\nstatic lwesp_recv_t recv_buff;\nstatic lwespr_t lwespi_process_sub_cmd(lwesp_msg_t* msg, lwesp_status_flags_t* stat);\n\n/* List of supported ESP32 devices by this lib, and its corresponding data info */\nstatic const lwesp_esp_device_desc_t esp_device_descriptors[] = {\n#if LWESP_CFG_ESP8266\n    {\n        .device = LWESP_DEVICE_ESP8266,\n        .gmr_strid_1 = \"- ESP8266 -\",\n        .min_at_version = LWESP_MIN_AT_VERSION_ESP8266,\n    },\n#endif /* LWESP_CFG_ESP8266 */\n#if LWESP_CFG_ESP32\n    {\n        .device = LWESP_DEVICE_ESP32,\n        .gmr_strid_1 = \"- ESP32 -\",\n        .gmr_strid_2 = NULL,\n        .min_at_version = LWESP_MIN_AT_VERSION_ESP32,\n    },\n#endif /* LWESP_CFG_ESP32 */\n#if LWESP_CFG_ESP32_C2\n    {\n        .device = LWESP_DEVICE_ESP32_C2,\n        .gmr_strid_1 = \"- ESP32C2 -\",\n        .gmr_strid_2 = \"- ESP32-C2 -\",\n        .min_at_version = LWESP_MIN_AT_VERSION_ESP32_C2,\n    },\n#endif /* LWESP_CFG_ESP32_C2 */\n#if LWESP_CFG_ESP32_C3\n    {\n        .device = LWESP_DEVICE_ESP32_C3,\n        .gmr_strid_1 = \"- ESP32C3 -\",\n        .gmr_strid_2 = \"- ESP32-C3 -\",\n        .min_at_version = LWESP_MIN_AT_VERSION_ESP32_C3,\n    },\n#endif /* LWESP_CFG_ESP32_C3 */\n#if LWESP_CFG_ESP32_C6\n    {\n        .device = LWESP_DEVICE_ESP32_C6,\n        .gmr_strid_1 = \"- ESP32C6 -\",\n        .gmr_strid_2 = \"- ESP32-C6 -\",\n        .min_at_version = LWESP_MIN_AT_VERSION_ESP32_C6,\n    },\n#endif /* LWESP_CFG_ESP32_C6 */\n};\n\n/**\n * \\brief           Free connection send data memory\n * \\param[in]       m: Send data message type\n */\n#define CONN_SEND_DATA_FREE(m)                                                                                         \\\n    do {                                                                                                               \\\n        if ((m) != NULL && (m)->msg.conn_send.fau) {                                                                   \\\n            (m)->msg.conn_send.fau = 0;                                                                                \\\n            if ((m)->msg.conn_send.data != NULL) {                                                                     \\\n                LWESP_DEBUGF(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, \"[LWESP CONN] Free write buffer fau: %p\\r\\n\",  \\\n                             (void*)(m)->msg.conn_send.data);                                                          \\\n                lwesp_mem_free_s((void**)&((m)->msg.conn_send.data));                                                  \\\n            }                                                                                                          \\\n        }                                                                                                              \\\n    } while (0)\n\n/**\n * \\brief           Send connection callback for \"data send\"\n * \\param[in]       m: Connection send message\n * \\param[in]       err: Error of type \\ref lwespr_t\n */\n#define CONN_SEND_DATA_SEND_EVT(m, err)                                                                                \\\n    do {                                                                                                               \\\n        CONN_SEND_DATA_FREE(m);                                                                                        \\\n        esp.evt.type = LWESP_EVT_CONN_SEND;                                                                            \\\n        esp.evt.evt.conn_data_send.res = err;                                                                          \\\n        esp.evt.evt.conn_data_send.conn = (m)->msg.conn_send.conn;                                                     \\\n        esp.evt.evt.conn_data_send.sent = (m)->msg.conn_send.sent_all;                                                 \\\n        lwespi_send_conn_cb((m)->msg.conn_send.conn, NULL);                                                            \\\n    } while (0)\n\n/**\n * \\brief           Send reset sequence event\n * \\param[in]       m: Command message\n * \\param[in]       err: Error of type \\ref lwespr_t\n */\n#define RESET_SEND_EVT(m, err)                                                                                         \\\n    do {                                                                                                               \\\n        esp.evt.evt.reset.res = err;                                                                                   \\\n        lwespi_send_cb(LWESP_EVT_RESET);                                                                               \\\n    } while (0)\n\n/**\n * \\brief           Send restore sequence event\n * \\param[in]       m: Command message\n * \\param[in]       err: Error of type \\ref lwespr_t\n */\n#define RESTORE_SEND_EVT(m, err)                                                                                       \\\n    do {                                                                                                               \\\n        esp.evt.evt.restore.res = err;                                                                                 \\\n        lwespi_send_cb(LWESP_EVT_RESTORE);                                                                             \\\n    } while (0)\n\n/**\n* \\brief           Send ping event to user\n* \\param[in]       m: Command message\n* \\param[in]       err: Error of type \\ref lwespr_t\n*/\n#define PING_SEND_EVT(m, err)                                                                                          \\\n    do {                                                                                                               \\\n        esp.evt.evt.ping.res = err;                                                                                    \\\n        esp.evt.evt.ping.host = (m)->msg.tcpip_ping.host;                                                              \\\n        esp.evt.evt.ping.time = (m)->msg.tcpip_ping.time;                                                              \\\n        lwespi_send_cb(LWESP_EVT_PING);                                                                                \\\n    } while (0)\n\n/**\n * \\brief           Send cipdomain (DNS function) event to user\n * \\param[in]       m: Command message\n * \\param[in]       err: Error of type \\ref lwespr_t\n */\n#define CIPDOMAIN_SEND_EVT(m, err)                                                                                     \\\n    do {                                                                                                               \\\n        esp.evt.evt.dns_hostbyname.res = err;                                                                          \\\n        esp.evt.evt.dns_hostbyname.host = msg->msg.dns_getbyhostname.host;                                             \\\n        esp.evt.evt.dns_hostbyname.ip = msg->msg.dns_getbyhostname.ip;                                                 \\\n        lwespi_send_cb(LWESP_EVT_DNS_HOSTBYNAME);                                                                      \\\n    } while (0)\n\n/**\n * \\brief           Send join AP event to user\n * \\param[in]       m: Command message\n * \\param[in]       err: Error of type \\ref lwespr_t\n */\n#define STA_JOIN_AP_SEND_EVT(m, err)                                                                                   \\\n    do {                                                                                                               \\\n        esp.evt.evt.sta_join_ap.res = err;                                                                             \\\n        lwespi_send_cb(LWESP_EVT_STA_JOIN_AP);                                                                         \\\n    } while (0)\n\n/**\n * \\brief           Send SNTP time event to user\n * \\param[in]       m: Command message\n * \\param[in]       err: Error of type \\ref lwespr_t\n */\n#define SNTP_TIME_SEND_EVT(m, err)                                                                                     \\\n    do {                                                                                                               \\\n        esp.evt.evt.cip_sntp_time.res = err;                                                                           \\\n        esp.evt.evt.cip_sntp_time.dt = (m)->msg.tcpip_sntp_time.dt;                                                    \\\n        lwespi_send_cb(LWESP_EVT_SNTP_TIME);                                                                           \\\n    } while (0)\n\n/**\n * \\brief           Send list AP event to user\n * \\param[in]       m: Command message\n * \\param[in]       err: Error of type \\ref lwespr_t\n */\n#define STA_LIST_AP_SEND_EVT(m, err)                                                                                   \\\n    do {                                                                                                               \\\n        esp.evt.evt.sta_list_ap.res = err;                                                                             \\\n        esp.evt.evt.sta_list_ap.aps = msg->msg.ap_list.aps;                                                            \\\n        esp.evt.evt.sta_list_ap.len = msg->msg.ap_list.apsi;                                                           \\\n        lwespi_send_cb(LWESP_EVT_STA_LIST_AP);                                                                         \\\n    } while (0)\n\n/**\n * \\brief           Send info AP event to user\n * \\param[in]       m: Command message\n * \\param[in]       err: Error of type \\ref lwespr_t\n */\n#define STA_INFO_AP_SEND_EVT(m, err)                                                                                   \\\n    do {                                                                                                               \\\n        esp.evt.evt.sta_info_ap.res = err;                                                                             \\\n        esp.evt.evt.sta_info_ap.info = esp.msg->msg.sta_info_ap.info;                                                  \\\n        lwespi_send_cb(LWESP_EVT_STA_INFO_AP);                                                                         \\\n    } while (0)\n\n/**\n * \\brief           Get command name based on used Espressif device,\n *                  used to obtain current connection status information\n * \\return          Cip status or state command type\n */\nlwesp_cmd_t\nlwespi_get_cipstatus_or_cipstate_cmd(void) {\n    /*\n     * With the current minimum AT versions,\n     * ESP8266 and ESP32 both require to use AT+CIPSTATUS,\n     * to get connection status.\n     *\n     * All other new devices utilize new command AT+CIPSTATE\n     */\n    if (0\n#if LWESP_CFG_ESP8266\n        || esp.m.device == LWESP_DEVICE_ESP8266\n#endif /* LWESP_CFG_ESP8266 */\n#if LWESP_CFG_ESP32\n        || esp.m.device == LWESP_DEVICE_ESP32\n#endif /* LWESP_CFG_ESP32 */\n    ) {\n        return LWESP_CMD_TCPIP_CIPSTATUS;\n    }\n    return LWESP_CMD_TCPIP_CIPSTATE;\n}\n\n/**\n * \\brief           Send IP address to AT port\n * \\param[in]       ip: Pointer to IP address\n * \\param[in]       q: Set to `1` to include start and ending quotes\n * \\param[in]       c: Set to `1` to include comma before string\n */\nvoid\nlwespi_send_ip(const lwesp_ip_t* ip, uint8_t q, uint8_t c) {\n    uint8_t ch = '.', len = 4;\n    char str[LWESP_CFG_IPV6 ? 5 : 4];\n\n    AT_PORT_SEND_COMMA_COND(c); /* Send comma */\n    if (ip == NULL) {\n        return;\n    }\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n#if LWESP_CFG_IPV6\n    if (ip->type == LWESP_IPTYPE_V6) {\n        ch = ':';\n        len = 8;\n    }\n#endif                                  /* LWESP_CFG_IPV6 */\n    for (uint8_t i = 0; i < len; ++i) { /* Process all elements */\n        if (0) {\n#if LWESP_CFG_IPV6\n        } else if (ip->type == LWESP_IPTYPE_V6) {\n            /* Format IPV6 */\n            lwesp_u32_to_gen_str(LWESP_U32(ip->addr.ip6.addr[i]), str, 1, 4);\n#endif /* LWESP_CFG_IPV6 */\n        } else {\n            /* Format IPV4 */\n            lwesp_u8_to_str(ip->addr.ip4.addr[i], str);\n        }\n        AT_PORT_SEND_STR(str);     /* Send str */\n        if (i < (len - 1)) {       /* Check end if characters */\n            AT_PORT_SEND_CHR(&ch); /* Send character */\n        }\n    }\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n}\n\n/**\n * \\brief           Send MAC address to AT port\n * \\param[in]       mac: Pointer to MAC address\n * \\param[in]       q: Set to `1` to include start and ending quotes\n * \\param[in]       c: Set to `1` to include comma before string\n */\nvoid\nlwespi_send_mac(const lwesp_mac_t* mac, uint8_t q, uint8_t c) {\n    const uint8_t ch = ':';\n    char str[3];\n\n    AT_PORT_SEND_COMMA_COND(c); /* Send comma */\n    if (mac == NULL) {\n        return;\n    }\n    AT_PORT_SEND_QUOTE_COND(q);                   /* Send quote */\n    for (uint8_t i = 0; i < 6; ++i) {             /* Process all elements */\n        lwesp_u8_to_hex_str(mac->mac[i], str, 2); /* ... go to HEX format */\n        AT_PORT_SEND_STR(str);                    /* Send str */\n        if (i < (6 - 1)) {                        /* Check end if characters */\n            AT_PORT_SEND_CHR(&ch);                /* Send character */\n        }\n    }\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n}\n\n/**\n * \\brief           Send string to AT port, either plain or escaped\n * \\param[in]       str: Pointer to input string to string\n * \\param[in]       e: Value to indicate string send format, escaped (`1`) or plain (`0`)\n * \\param[in]       q: Value to indicate starting and ending quotes, enabled (`1`) or disabled (`0`)\n * \\param[in]       c: Set to `1` to include comma before string\n */\nvoid\nlwespi_send_string(const char* str, uint8_t e, uint8_t q, uint8_t c) {\n    char special = '\\\\';\n\n    AT_PORT_SEND_COMMA_COND(c); /* Send comma */\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n    if (str != NULL) {\n        if (e) {                                                  /* Do we have to escape string? */\n            while (*str) {                                        /* Go through string */\n                if (*str == ',' || *str == '\"' || *str == '\\\\') { /* Check for special character */\n                    AT_PORT_SEND_CHR(&special);                   /* Send special character */\n                }\n                AT_PORT_SEND_CHR(str); /* Send character */\n                ++str;\n            }\n        } else {\n            AT_PORT_SEND_STR(str); /* Send plain string */\n        }\n    }\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n}\n\n/**\n * \\brief           Send number (decimal) to AT port\n * \\param[in]       num: Number to send to AT port\n * \\param[in]       q: Value to indicate starting and ending quotes, enabled (`1`) or disabled (`0`)\n * \\param[in]       c: Set to `1` to include comma before string\n */\nvoid\nlwespi_send_number(uint32_t num, uint8_t q, uint8_t c) {\n    char str[11];\n\n    lwesp_u32_to_str(num, str); /* Convert digit to decimal string */\n\n    AT_PORT_SEND_COMMA_COND(c); /* Send comma */\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n    AT_PORT_SEND_STR(str);      /* Send string with number */\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n}\n\n/**\n * \\brief           Send port number to AT port\n * \\param[in]       port: Port number to send\n * \\param[in]       q: Value to indicate starting and ending quotes, enabled (`1`) or disabled (`0`)\n * \\param[in]       c: Set to `1` to include comma before string\n */\nvoid\nlwespi_send_port(lwesp_port_t port, uint8_t q, uint8_t c) {\n    char str[6];\n\n    lwesp_u16_to_str(LWESP_PORT2NUM(port), str); /* Convert digit to decimal string */\n\n    AT_PORT_SEND_COMMA_COND(c); /* Send comma */\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n    AT_PORT_SEND_STR(str);      /* Send string with number */\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n}\n\n/**\n * \\brief           Send signed number to AT port\n * \\param[in]       num: Number to send to AT port\n * \\param[in]       q: Value to indicate starting and ending quotes, enabled (`1`) or disabled (`0`)\n * \\param[in]       c: Set to `1` to include comma before string\n */\nvoid\nlwespi_send_signed_number(int32_t num, uint8_t q, uint8_t c) {\n    char str[11];\n\n    lwesp_i32_to_str(num, str); /* Convert digit to decimal string */\n\n    AT_PORT_SEND_COMMA_COND(c); /* Send comma */\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n    AT_PORT_SEND_STR(str);      /* Send string with number */\n    AT_PORT_SEND_QUOTE_COND(q); /* Send quote */\n}\n\n/**\n * \\brief           Reset all connections\n * \\note            Used to notify upper layer stack to close everything and reset the memory if necessary\n * \\param[in]       forced: Flag indicating reset was forced by command\n */\nstatic void\nreset_connections(uint8_t forced) {\n    esp.evt.type = LWESP_EVT_CONN_CLOSE;\n    esp.evt.evt.conn_active_close.forced = forced;\n    esp.evt.evt.conn_active_close.res = lwespOK;\n\n    for (size_t i = 0; i < LWESP_CFG_MAX_CONNS; ++i) { /* Check all connections */\n        if (esp.m.conns[i].status.f.active) {\n            esp.m.conns[i].status.f.active = 0;\n\n            esp.evt.evt.conn_active_close.conn = &esp.m.conns[i];\n            esp.evt.evt.conn_active_close.client = esp.m.conns[i].status.f.client;\n            lwespi_send_conn_cb(&esp.m.conns[i], NULL); /* Send callback function */\n        }\n    }\n}\n\n/**\n * \\brief           Reset everything after reset was detected\n * \\param[in]       forced: Set to `1` if reset forced by user\n */\nvoid\nlwespi_reset_everything(uint8_t forced) {\n    /**\n     * \\todo: Put stack to default state:\n     *          - Close all the connections in memory\n     *          - Clear entire data memory\n     *          - Reset esp structure with IP\n     *          - Start over init procedure\n     */\n\n    /* Step 1: Close all connections in memory */\n    reset_connections(forced);\n\n#if LWESP_CFG_MODE_STATION\n    LWESP_RESET_STA_HAS_IP();\n    if (esp.m.sta.f.is_connected) {\n        lwespi_send_cb(LWESP_EVT_WIFI_DISCONNECTED);\n    }\n    esp.m.sta.f.is_connected = 0;\n#endif /* LWESP_CFG_MODE_STATION */\n\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n    /* Clean receive buffer */\n    if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPRECVDATA) && esp.msg->msg.conn_recv.buff != NULL) {\n        lwesp_pbuf_free_s(&esp.msg->msg.conn_recv.buff);\n    }\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n\n    /* Invalid ESP modules */\n    LWESP_MEMSET(&esp.m, 0x00, sizeof(esp.m));\n\n    /* Set default device */\n    esp.m.device = LWESP_DEVICE_UNKNOWN;\n\n    /* Reset baudrate to default */\n    esp.ll.uart.baudrate = LWESP_CFG_AT_PORT_BAUDRATE;\n    lwesp_ll_init(&esp.ll);\n\n    /* If reset was not forced by user, repeat with manual reset */\n    if (!forced) {\n        lwesp_reset(NULL, NULL, 0);\n    }\n}\n\n/**\n * \\brief           Process callback function to user with specific type\n * \\param[in]       type: Callback event type\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwespi_send_cb(lwesp_evt_type_t type) {\n    esp.evt.type = type; /* Set callback type to process */\n\n    /* Call callback function for all registered functions */\n    for (lwesp_evt_func_t* link = esp.evt_func; link != NULL; link = link->next) {\n        link->fn(&esp.evt);\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Process connection callback\n * \\note            Before calling function, callback structure must be prepared\n * \\param[in]       conn: Pointer to connection to use as callback\n * \\param[in]       evt: Event callback function for connection\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwespi_send_conn_cb(lwesp_conn_t* conn, lwesp_evt_fn evt) {\n    if (conn->status.f.in_closing && esp.evt.type != LWESP_EVT_CONN_CLOSE) { /* Do not continue if in closing mode */\n        /* return lwespOK; */\n    }\n\n    if (evt != NULL) {                                   /* Try with user connection */\n        return evt(&esp.evt);                            /* Call temporary function */\n    } else if (conn != NULL && conn->evt_func != NULL) { /* Connection custom callback? */\n        return conn->evt_func(&esp.evt);                 /* Process callback function */\n    } else if (conn == NULL) {\n        return lwespOK;\n    }\n\n    /*\n     * On normal API operation,\n     * we should never enter to this part of code\n     */\n\n    /*\n     * If connection doesn't have callback function\n     * automatically close the connection?\n     *\n     * Since function call is non-blocking,\n     * it will set active connection to closing mode\n     * and further callback events should not be executed anymore\n     */\n    return lwesp_conn_close(conn, 0);\n}\n\n/**\n * \\brief           Process and send data from device buffer\n * \\return          Member of \\ref lwespr_t enumeration\n */\nstatic lwespr_t\nlwespi_tcpip_process_send_data(void) {\n    lwesp_conn_t* c = esp.msg->msg.conn_send.conn;\n    if (!lwesp_conn_is_active(c) ||                /* Is the connection already closed? */\n        esp.msg->msg.conn_send.val_id != c->val_id /* Did validation ID change after we set parameter? */\n    ) {\n        /* Send event to user about failed send event */\n        CONN_SEND_DATA_SEND_EVT(esp.msg, lwespCLOSED);\n        return lwespERR;\n    }\n\n    /*\n     * Get maximal length of data to transmit in single run\n     *\n     * For UDP packets, fragmentation may not be allowed.\n     * Check for UDP is done before starting command to send data, in LWESP_CONN module\n     */\n    esp.msg->msg.conn_send.sent = LWESP_MIN(esp.msg->msg.conn_send.btw, LWESP_CFG_CONN_MAX_DATA_LEN);\n\n    AT_PORT_SEND_BEGIN_AT();\n    AT_PORT_SEND_CONST_STR(\"+CIPSEND=\");\n    lwespi_send_number(LWESP_U32(c->num), 0, 0);                      /* Send connection number */\n    lwespi_send_number(LWESP_U32(esp.msg->msg.conn_send.sent), 0, 1); /* Send length number */\n\n    /* On UDP connections, IP address and port may be included */\n    if (CONN_IS_UDP_V4_OR_V6(c->type) && esp.msg->msg.conn_send.remote_ip != NULL\n        && esp.msg->msg.conn_send.remote_port) {\n        lwespi_send_ip(esp.msg->msg.conn_send.remote_ip, 1, 1);     /* Send IP address including quotes */\n        lwespi_send_port(esp.msg->msg.conn_send.remote_port, 0, 1); /* Send length number */\n    }\n    AT_PORT_SEND_END_AT();\n    return lwespOK;\n}\n\n/**\n * \\brief           Process data sent and send remaining\n * \\param[in]       sent: Status whether data were sent or not,\n *                      info received from ESP with `SEND OK` or `SEND FAIL`\n * \\return          `1` in case we should stop sending or `0` if we still have data to process\n */\nstatic uint8_t\nlwespi_tcpip_process_data_sent(uint8_t sent) {\n    if (sent) { /* Data were successfully sent */\n        esp.msg->msg.conn_send.sent_all += esp.msg->msg.conn_send.sent;\n        esp.msg->msg.conn_send.btw -= esp.msg->msg.conn_send.sent;\n        esp.msg->msg.conn_send.ptr += esp.msg->msg.conn_send.sent;\n        if (esp.msg->msg.conn_send.bw != NULL) {\n            *esp.msg->msg.conn_send.bw += esp.msg->msg.conn_send.sent;\n        }\n        esp.msg->msg.conn_send.tries = 0;\n    } else {                            /* We were not successful */\n        ++esp.msg->msg.conn_send.tries; /* Increase number of tries */\n        if (esp.msg->msg.conn_send.tries\n            == LWESP_CFG_MAX_SEND_RETRIES) { /* In case we reached max number of retransmissions */\n            return 1;                        /* Return 1 and indicate error */\n        }\n    }\n    if (esp.msg->msg.conn_send.btw > 0) {                  /* Do we still have data to send? */\n        if (lwespi_tcpip_process_send_data() != lwespOK) { /* Check if we can continue */\n            return 1;                                      /* Finish at this point */\n        }\n        return 0; /* We still have data to send */\n    }\n    return 1; /* Everything was sent, we can stop execution */\n}\n\n/**\n * \\brief           Send error event to application layer\n * \\param[in]       msg: Message from user with connection start\n * \\param[in]       error: Value indicating cause of error\n */\nstatic void\nlwespi_send_conn_error_cb(lwesp_msg_t* msg, lwespr_t error) {\n    esp.evt.type = LWESP_EVT_CONN_ERROR; /* Connection error */\n    esp.evt.evt.conn_error.host = esp.msg->msg.conn_start.remote_host;\n    esp.evt.evt.conn_error.port = esp.msg->msg.conn_start.remote_port;\n    esp.evt.evt.conn_error.type = esp.msg->msg.conn_start.type;\n    esp.evt.evt.conn_error.arg = esp.msg->msg.conn_start.arg;\n    esp.evt.evt.conn_error.err = error;\n\n    /* Call callback specified by user on connection startup */\n    esp.msg->msg.conn_start.evt_func(&esp.evt);\n    LWESP_UNUSED(msg);\n}\n\n/**\n * \\brief           Process received string from ESP\n * \\param[in]       rcv: Pointer to \\ref lwesp_recv_t structure with input string\n */\nstatic void\nlwespi_parse_received(lwesp_recv_t* rcv) {\n    lwesp_status_flags_t stat = {0};\n    const char* s;\n\n    /* Try to remove non-parsable strings */\n    if ((rcv->len == 2 && rcv->data[0] == '\\r' && rcv->data[1] == '\\n')\n        /*\n         * Condition below can only be used if AT echo is disabled\n         * otherwise it may happen that message is inserted in between AT command echo, such as:\n         *\n         * AT+CIPCLOSE=0+LINK_CONN:0,2,\"TCP\",1,\"192.168.0.14\",57551,80\\r\\n\\r\\n\n         *\n         * Instead of:\n         * AT+CIPCLOSE=0\\r\\n\n         * +LINK_CONN:0,2,\"TCP\",1,\"192.168.0.14\",57551,80\\r\\n\n         */\n        /* || (rcv->len > 3 && rcv->data[0] == 'A' && rcv->data[1] == 'T' && rcv->data[2] == '+') */) {\n        return;\n    }\n\n    /* Detect most common responses from device */\n    stat.is_ok = !strcmp(rcv->data, \"OK\" CRLF); /* Check if received string is OK */\n    if (!stat.is_ok) {\n        stat.is_error =\n            !strcmp(rcv->data, \"ERROR\" CRLF) || !strcmp(rcv->data, \"FAIL\" CRLF); /* Check if received string is error */\n        if (!stat.is_error) {\n            stat.is_ready = !strcmp(rcv->data, \"ready\" CRLF); /* Check if received string is ready */\n        }\n    }\n\n    /*\n     * In case ready was received, there was a reset on device,\n     * either forced by command or problem on device itself\n     */\n    if (stat.is_ready) {\n        if (CMD_IS_CUR(LWESP_CMD_RESET) || CMD_IS_CUR(LWESP_CMD_RESTORE)) { /* Did we force reset? */\n            esp.evt.evt.reset_detected.forced = 1;\n        } else { /* Reset due unknown error */\n            esp.evt.evt.reset_detected.forced = 0;\n            if (esp.msg != NULL) {\n                stat.is_ok = 0;\n                stat.is_error = 1;\n                stat.is_ready = 0;\n            }\n        }\n        lwespi_reset_everything(esp.evt.evt.reset_detected.forced); /* Put everything to default state */\n        lwespi_send_cb(LWESP_EVT_RESET_DETECTED);                   /* Call user callback function */\n    }\n\n    /* Read and process statements starting with '+' character */\n    if (rcv->data[0] == '+') {\n        if (!strncmp(\"+IPD\", rcv->data, 4)) {             /* Check received network data */\n            lwesp_conn_p c = lwespi_parse_ipd(rcv->data); /* Parse IPD statement and start receiving network data */\n\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n            if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPRECVDATA) && CMD_IS_CUR(LWESP_CMD_TCPIP_CIPRECVLEN)) {\n                esp.msg->msg.conn_recv.ipd_recv = 1; /* Command repeat, try again later */\n            }\n            if (c != NULL) {\n                lwespi_conn_manual_tcp_try_read_data(c);\n            }\n#else\n            LWESP_UNUSED(c);\n            /* TODO: Here we set buffer to send data in non-manual mode */\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n        } else if (!strncmp(\"+CIPRECVLEN\", rcv->data, 11)) {\n            lwespi_parse_ciprecvlen(rcv->data); /* Parse CIPRECVLEN statement */\n#endif                                          /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n#if LWESP_CFG_MODE_ACCESS_POINT\n        } else if (!strncmp(rcv->data, \"+STA_CONNECTED\", 14)) {\n            lwespi_parse_ap_conn_disconn_sta(&rcv->data[15], 1); /* Parse string and send to user layer */\n        } else if (!strncmp(rcv->data, \"+STA_DISCONNECTED\", 17)) {\n            lwespi_parse_ap_conn_disconn_sta(&rcv->data[18], 0); /* Parse string and send to user layer */\n        } else if (!strncmp(rcv->data, \"+DIST_STA_IP\", 12)) {\n            lwespi_parse_ap_ip_sta(&rcv->data[13]); /* Parse string and send to user layer */\n#endif                                              /* LWESP_CFG_MODE_ACCESS_POINT */\n#if LWESP_CFG_SNTP\n        } else if (!strncmp(rcv->data, \"+TIME_UPDATED\", 13)) {\n            lwespi_send_cb(LWESP_EVT_SNTP_TIME_UPDATED);\n#if LWESP_CFG_SNTP_AUTO_READ_TIME_ON_UPDATE\n            lwesp_sntp_gettime(&esp.m.sntp_dt, NULL, NULL, 0);\n#endif /* LWESP_CFG_SNTP_AUTO_READ_TIME_ON_UPDATE */\n#endif /* LWESP_CFG_SNTP */\n#if LWESP_CFG_WEBSERVER\n        } else if (!strncmp(rcv->data, \"+WEBSERVERRSP\", 13)) {\n            lwespi_parse_webserver(&rcv->data[14]); /* Parse string and send to user layer */\n#endif                                              /* LWESP_CFG_WEBSERVER */\n        } else if (esp.msg != NULL) {\n            if (0) {\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPRECVDATA) && !strncmp(\"+CIPRECVDATA\", rcv->data, 12)) {\n                const char* str = &rcv->data[13];\n                uint32_t len;\n\n                /* Check data length */\n                if ((len = lwespi_parse_number(&str)) > 0) {\n                    lwesp_ip_t ip;\n                    lwesp_port_t port;\n\n                    /* Parse remaining information */\n                    lwespi_parse_ip(&str, &ip);\n                    port = lwespi_parse_port(&str);\n\n                    /* Go to read mode */\n                    esp.msg->msg.conn_recv.read = 1;\n                    esp.msg->msg.conn_recv.tot_len = len;\n                    esp.msg->msg.conn_recv.buff_ptr = 0;\n\n                    /*\n                     * Read received data in case of:\n                     *\n                     *  - Connection is active and\n                     *  - Connection is not in closing mode\n                     */\n                    if (esp.msg->msg.conn_recv.conn->status.f.active\n                        && !esp.msg->msg.conn_recv.conn->status.f.in_closing) {\n                        LWESP_DEBUGW(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING,\n                                     esp.msg->msg.conn_recv.buff == NULL,\n                                     \"[LWESP IPD] No buffer allocated for %d byte(s)\\r\\n\", (int)len);\n\n                        /* Update available data */\n                        if (esp.msg->msg.conn_recv.buff != NULL) {\n                            /* Adjust length of buffer for user */\n                            if (lwesp_pbuf_length(esp.msg->msg.conn_recv.buff, 1) > len) {\n                                esp.msg->msg.conn_recv.buff->tot_len = len;\n                                esp.msg->msg.conn_recv.buff->len = len;\n                            }\n                            lwesp_pbuf_set_ip(esp.msg->msg.conn_recv.buff, &ip, port);\n                            if (esp.msg->msg.conn_recv.conn->tcp_available_bytes >= len) {\n                                esp.msg->msg.conn_recv.conn->tcp_available_bytes -= len;\n                            } else {\n                                esp.msg->msg.conn_recv.conn->tcp_available_bytes = 0;\n                                esp.msg->msg.conn_recv.conn->tcp_available_bytes = 0;\n                                LWESP_DEBUGF(\n                                    LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE,\n                                    \"[LWESP IPD] Connection %u, setting tcp_available_bytes to zero. Actual len \"\n                                    \"is less than it was requested to read\\r\\n\",\n                                    (unsigned)esp.msg->msg.conn_recv.conn->num);\n                            }\n                        }\n                    } else {\n                        /* Ignore reading on closed connection */\n                        lwesp_pbuf_free_s(&esp.msg->msg.conn_recv.buff);\n                        LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE,\n                                     \"[LWESP IPD] Connection %u closed or in closing. skipping %u byte(s)\\r\\n\",\n                                     (unsigned)esp.msg->msg.conn_recv.conn->num, (unsigned)len);\n                    }\n                    esp.msg->msg.conn_recv.conn->status.f.data_received = 1; /* We have first received data */\n                } else {\n                    esp.msg->msg.conn_recv.conn->tcp_available_bytes = 0;\n                    LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE,\n                                 \"[LWESP IPD] Connection %u, setting tcp_available_bytes to zero\\r\\n\",\n                                 (unsigned)esp.msg->msg.conn_recv.conn->num);\n                }\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n#if LWESP_CFG_MODE_STATION\n            } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWLAP) && !strncmp(rcv->data, \"+CWLAP\", 6)) {\n                lwespi_parse_cwlap(rcv->data, esp.msg); /* Parse CWLAP entry */\n            } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWJAP) && !strncmp(rcv->data, \"+CWJAP\", 6)) {\n                const char* tmp = &rcv->data[7]; /* Go to the number position */\n                esp.msg->msg.sta_join.error_num = (uint8_t)lwespi_parse_number(&tmp);\n            } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWJAP_GET) && !strncmp(rcv->data, \"+CWJAP\", 6)) {\n                lwespi_parse_cwjap(rcv->data, esp.msg); /* Parse CWJAP */\n#endif                                                  /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_DNS\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPDOMAIN) && !strncmp(rcv->data, \"+CIPDOMAIN\", 10)) {\n                lwespi_parse_cipdomain(rcv->data, esp.msg); /* Parse CIPDOMAIN entry */\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPDNS_GET) && !strncmp(rcv->data, \"+CIPDNS\", 7)) {\n                const char* tmp = &rcv->data[8]; /* Go to the ip position */\n                lwesp_ip_t ip;\n                uint8_t index = lwespi_parse_number(&tmp);\n                esp.msg->msg.dns_getconf.dnsi = index;\n                lwespi_parse_ip(&tmp, &ip); /* Parse DNS address */\n                if (esp.msg->msg.dns_getconf.s1 != NULL) {\n                    *esp.msg->msg.dns_getconf.s1 = ip;\n                }\n                if (esp.msg->msg.dns_getconf.s2 != NULL && lwespi_parse_ip(&tmp, &ip)) {\n                    *esp.msg->msg.dns_getconf.s2 = ip;\n                }\n#endif /* LWESP_CFG_DNS */\n#if LWESP_CFG_PING\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_PING) && !strncmp(rcv->data, \"+PING\", 5)) {\n                lwespi_parse_ping_time(rcv->data, esp.msg); /* Parse ping time */\n#endif                                                      /* LWESP_CFG_PING */\n#if LWESP_CFG_SNTP\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSNTPTIME) && !strncmp(rcv->data, \"+CIPSNTPTIME\", 12)) {\n                lwespi_parse_cipsntptime(rcv->data, esp.msg); /* Parse CIPSNTPTIME entry */\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSNTPCFG_GET) && !strncmp(rcv->data, \"+CIPSNTPCFG\", 11)) {\n                lwespi_parse_sntp_cfg(rcv->data, esp.msg); /* Parse CIPSNTPTIME entry */\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSNTPINTV_GET) && !strncmp(rcv->data, \"+CIPSNTPINTV\", 12)) {\n                lwespi_parse_cipsntpintv(rcv->data, esp.msg); /* Parse CIPSNTPINTV entry */\n#endif                                                        /* LWESP_CFG_SNTP */\n#if LWESP_CFG_HOSTNAME\n            } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWHOSTNAME_GET) && !strncmp(rcv->data, \"+CWHOSTNAME\", 11)) {\n                lwespi_parse_hostname(rcv->data, esp.msg); /* Parse HOSTNAME entry */\n#endif                                                     /* LWESP_CFG_HOSTNAME */\n            } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWDHCP_GET) && !strncmp(rcv->data, \"+CWDHCP\", 7)) {\n                lwespi_parse_cwdhcp(rcv->data); /* Parse CWDHCP state */\n            } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWMODE_GET) && !strncmp(rcv->data, \"+CWMODE\", 7)) {\n                const char* tmp = &rcv->data[8]; /* Go to the number position */\n                *esp.msg->msg.wifi_mode.mode_get = (uint8_t)lwespi_parse_number(&tmp);\n#if LWESP_CFG_FLASH\n            } else if (CMD_IS_CUR(LWESP_CMD_SYSMFG_READ) && !strncmp(rcv->data, \"+SYSMFG\", 7)) {\n                const char* tmp = &rcv->data[8];\n                uint32_t length;\n\n                lwespi_parse_string(&tmp, NULL, 0, 1);\n                lwespi_parse_string(&tmp, NULL, 0, 1);\n                lwespi_parse_number(&tmp);\n                length = (uint32_t)lwespi_parse_number(&tmp);\n                esp.msg->msg.mfg_read.btr = length;\n                esp.msg->msg.mfg_read.read_mode = 1; /* Go into read mode */\n#endif                                               /* LWESP_CFG_FLASH */\n            } else if ((LWESP_CFG_MODE_STATION && CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTAMAC_GET)\n                        && !strncmp(rcv->data, \"+CIPSTAMAC\", 10))\n                       || (LWESP_CFG_MODE_ACCESS_POINT && CMD_IS_CUR(LWESP_CMD_WIFI_CIPAPMAC_GET)\n                           && !strncmp(rcv->data, \"+CIPAPMAC\", 9))) {\n                const char* tmp;\n                lwesp_mac_t mac;\n\n                if (rcv->data[9] == ':') {\n                    tmp = &rcv->data[10];\n                } else if (rcv->data[10] == ':') {\n                    tmp = &rcv->data[11];\n                }\n\n                lwespi_parse_mac(&tmp, &mac); /* Save as current MAC address */\n#if LWESP_CFG_MODE_STATION\n                if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTAMAC_GET)) {\n                    LWESP_MEMCPY(&esp.m.sta.mac, &mac, 6); /* Copy to current setup */\n                }\n#endif /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n                if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPAPMAC_GET)) {\n                    LWESP_MEMCPY(&esp.m.ap.mac, &mac, 6); /* Copy to current setup */\n                }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n                if (esp.msg->msg.sta_ap_getmac.mac != NULL && CMD_IS_CUR(CMD_GET_DEF())) {\n                    LWESP_MEMCPY(esp.msg->msg.sta_ap_getmac.mac, &mac, sizeof(mac)); /* Copy to current setup */\n                }\n            } else if ((LWESP_CFG_MODE_STATION && CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTA_GET)\n                        && !strncmp(rcv->data, \"+CIPSTA\", 7))\n                       || (LWESP_CFG_MODE_ACCESS_POINT && CMD_IS_CUR(LWESP_CMD_WIFI_CIPAP_GET)\n                           && !strncmp(rcv->data, \"+CIPAP\", 6))) {\n                const char *tmp = NULL, *ch_p2;\n                lwesp_ip_t ip, *a = NULL, *b = NULL;\n                lwesp_ip_mac_t* im;\n                uint8_t ch = 0;\n\n#if LWESP_CFG_MODE_STATION\n                if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTA_GET)) {\n                    im = &esp.m.sta; /* Get IP and MAC structure first */\n                }\n#endif /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n                if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPAP_GET)) {\n                    im = &esp.m.ap; /* Get IP and MAC structure first */\n                }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n\n                if (im != NULL) {\n                    /* We expect \"+CIPSTA:\" or \"+CIPAP:\" ... */\n                    if (rcv->data[6] == ':') {\n                        ch = rcv->data[7];\n                        ch_p2 = &rcv->data[9];\n                    } else if (rcv->data[7] == ':') {\n                        ch = rcv->data[8];\n                        ch_p2 = &rcv->data[10];\n                    }\n                    switch (ch) {\n                        case 'i':\n                            if (0) {\n#if LWESP_CFG_IPV6\n                                /* Check local IPv6 address */\n                            } else if (ch_p2[0] == '6' && ch_p2[1] == 'l') {\n                                tmp = &rcv->data[13];\n                                a = &im->ip6_ll;\n                                b = esp.msg->msg.sta_ap_getip.ip6_ll;\n                                /* Check global IPv6 address */\n                            } else if (ch_p2[0] == '6' && ch_p2[1] == 'g') {\n                                tmp = &rcv->data[13];\n                                a = &im->ip6_gl;\n                                b = esp.msg->msg.sta_ap_getip.ip6_gl;\n#endif /* LWESP_CFG_IPV6 */\n                            } else {\n                                tmp = &rcv->data[10];\n                                a = &im->ip;\n                                b = esp.msg->msg.sta_ap_getip.ip;\n                            }\n                            LWESP_UNUSED(ch_p2); /* May be unused */\n                            break;\n                        case 'g':\n                            tmp = &rcv->data[15];\n                            a = &im->gw;\n                            b = esp.msg->msg.sta_ap_getip.gw;\n                            break;\n                        case 'n':\n                            tmp = &rcv->data[15];\n                            a = &im->nm;\n                            b = esp.msg->msg.sta_ap_getip.nm;\n                            break;\n                        default:\n                            tmp = NULL;\n                            a = NULL;\n                            b = NULL;\n                            break;\n                    }\n                    if (tmp != NULL) { /* Do we have temporary string? */\n                        if (*tmp == ':' || *tmp == ',') {\n                            ++tmp;\n                        }\n                        lwespi_parse_ip(&tmp, &ip);                   /* Parse IP address */\n                        LWESP_MEMCPY(a, &ip, sizeof(ip));             /* Copy to current setup */\n                        if (b != NULL && CMD_IS_CUR(CMD_GET_DEF())) { /* Is current command the same as default one? */\n                            LWESP_MEMCPY(b, &ip, sizeof(ip));         /* Copy to user variable */\n                        }\n                    }\n                }\n            }\n        }\n#if LWESP_CFG_MODE_STATION\n    } else if (strlen(rcv->data) > 4 && !strncmp(rcv->data, \"WIFI\", 4)) {\n        if (!strncmp(&rcv->data[5], \"CONNECTED\", 9)) {\n            esp.m.sta.f.is_connected = 1;                         /* Wifi is connected */\n            lwespi_send_cb(LWESP_EVT_WIFI_CONNECTED);             /* Call user callback function */\n            if (!CMD_IS_CUR(LWESP_CMD_WIFI_CWJAP)) {              /* In case of auto connection */\n                lwesp_sta_getip(NULL, NULL, NULL, NULL, NULL, 0); /* Get new IP address */\n            }\n        } else if (!strncmp(&rcv->data[5], \"DISCONNECT\", 10)) {\n            esp.m.sta.f.is_connected = 0;                /* Wifi is disconnected */\n            LWESP_RESET_STA_HAS_IP();                    /* There is no valid IP */\n            lwespi_send_cb(LWESP_EVT_WIFI_DISCONNECTED); /* Call user callback function */\n        } else if (!strncmp(&rcv->data[5], \"GOT IP\", 6)) {\n            if (0) {\n#if LWESP_CFG_IPV6\n                /* Check if IPv6 IP received */\n            } else if (!strncmp(&rcv->data[11], \"v6 LL\", 5)) {\n                esp.m.sta.f.has_ipv6_ll = 1;\n            } else if (!strncmp(&rcv->data[11], \"v6 GL\", 5)) {\n                esp.m.sta.f.has_ipv6_gl = 1;\n#endif /* LWESP_CFG_IPV6 */\n            } else {\n                /* IP is for V4 (\\todo: Add specific status) */\n            }\n            esp.m.sta.f.has_ip = 1;                               /* Wifi got IP address */\n            lwespi_send_cb(LWESP_EVT_WIFI_GOT_IP);                /* Call user callback function */\n            if (!CMD_IS_CUR(LWESP_CMD_WIFI_CWJAP)) {              /* In case of auto connection */\n                lwesp_sta_getip(NULL, NULL, NULL, NULL, NULL, 0); /* Get new IP address */\n            }\n        }\n    } else if (CMD_IS_CUR(LWESP_CMD_GMR)) {\n        if (!strncmp(rcv->data, \"AT version\", 10)) {\n            uint32_t min_version = (uint32_t)-1;\n            uint8_t ok = 0;\n            lwespi_parse_at_sdk_version(&rcv->data[11], &esp.m.version_at);\n\n            /* Parse all objects */\n            for (size_t i = 0; i < sizeof(esp_device_descriptors) / sizeof(esp_device_descriptors[0]); ++i) {\n                const lwesp_esp_device_desc_t* desc = &esp_device_descriptors[i];\n\n                if ((desc->gmr_strid_1 != NULL && strstr(rcv->data, desc->gmr_strid_1) != NULL)\n                    || (desc->gmr_strid_2 != NULL && strstr(rcv->data, desc->gmr_strid_2) != NULL)) {\n                    esp.m.device = desc->device;\n                    min_version = desc->min_at_version;\n                    LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_TYPE_TRACE,\n                                 \"[LWESP GMR] Detected Espressif device is %s\\r\\n\", desc->gmr_strid_1);\n                    ok = 1;\n                    break;\n                }\n            }\n\n            if (!ok) {\n                LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_SEVERE,\n                             \"[LWESP GMR] Could not detect connected Espressif device: %.*s\\r\\n\", (int)rcv->len,\n                             rcv->data);\n            }\n            LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_TYPE_TRACE, \"[LWESP GMR] AT version minimum required: %08X\\r\\n\",\n                         (unsigned)min_version);\n            LWESP_DEBUGF(LWESP_CFG_DBG_INIT | LWESP_DBG_TYPE_TRACE,\n                         \"[LWESP GMR] AT version detected on device: %08X\\r\\n\", (int)esp.m.version_at.version);\n\n            /* Compare versions, but only if device is well detected */\n            if (ok) {\n                if (esp.m.version_at.version < min_version) {\n                    LWESP_DEBUGF(\n                        LWESP_CFG_DBG_INIT | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_SEVERE,\n                        \"[LWESP GMR] Minimum AT required is higher than the AT version running on the device\\r\\n\");\n                    ok = 0;\n                }\n            }\n\n            /* Send out version not supported information to system */\n            if (!ok) {\n                lwespi_send_cb(LWESP_EVT_AT_VERSION_NOT_SUPPORTED);\n            }\n        } else if (!strncmp(rcv->data, \"SDK version\", 11)) {\n            lwespi_parse_at_sdk_version(&rcv->data[12], &esp.m.version_sdk);\n        }\n#endif /* LWESP_CFG_MODE_STATION */\n    }\n\n    /* \n     * Process other received data, which may or may not\n     * start with the `+` sign -> command specific\n     */\n    if (esp.msg != NULL) { /* Do we have valid message? */\n        /* Start with received error code */\n        if (strncmp(rcv->data, \"ERR CODE:\", 9) == 0) {\n            /* Check for command not supported message */\n            if (strncmp(&rcv->data[9], \"0x01090000\", 10) == 0) {\n                esp.msg->res_err_code = lwespERRCMDNOTSUPPORTED;\n            }\n        } else if ((CMD_IS_CUR(LWESP_CMD_RESET) || CMD_IS_CUR(LWESP_CMD_RESTORE))\n                   && stat.is_ok) {                            /* Check for reset/restore command */\n            stat.is_ok = 0;                                    /* We must wait for \"ready\", not only \"OK\" */\n            esp.ll.uart.baudrate = LWESP_CFG_AT_PORT_BAUDRATE; /* Save user baudrate */\n            lwesp_ll_init(&esp.ll);                            /* Set new baudrate */\n        } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTATUS) || CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTATE)) {\n            size_t offset = 0;\n\n            if (0\n#if LWESP_CFG_ESP8266 || LWESP_CFG_ESP32\n                || (!strncmp(rcv->data, \"+CIPSTATUS\", 10)\n                    && (offset = 11) > 0) /* This is to check string and get offset in one shot */\n#endif                                    /* LWESP_CFG_ESP8266 || LWESP_CFG_ESP32 */\n                || (!strncmp(rcv->data, \"+CIPSTATE\", 9) && (offset = 10) > 0)) {\n                lwespi_parse_cipstatus_cipstate(rcv->data + offset); /* Parse +CIPSTATUS or +CIPSTATE response */\n            } else if (stat.is_ok) {\n                for (size_t i = 0; i < LWESP_CFG_MAX_CONNS; ++i) { /* Set current connection statuses */\n                    esp.m.conns[i].status.f.active = !!(esp.m.active_conns & (1 << i));\n                }\n            }\n#if LWESP_CFG_FLASH\n        } else if (CMD_IS_CUR(LWESP_CMD_SYSFLASH_WRITE)) {\n        } else if (CMD_IS_CUR(LWESP_CMD_SYSMFG_WRITE)) {\n            /* Primitive types are written in single shot */\n            if (!LWESP_MFG_VALTYPE_IS_PRIM(esp.msg->msg.mfg_write.valtype)) {\n                /* Non-primitive types will follow with \">\" afterwards */\n                if (stat.is_ok) {\n                    /* We react on second OK */\n                    if (!esp.msg->msg.mfg_write.wait_second_ok) {\n                        esp.msg->msg.mfg_write.wait_second_ok = 1;\n                        stat.is_ok = 0;\n                    }\n                }\n            }\n#endif /* LWESP_CFG_FLASH */\n        } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTART)) {\n            /* Do nothing, it is either OK or not OK */\n        } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSEND)) {\n            if (stat.is_ok) {   /* Check for OK and clear as we have to check for \"> \" statement after OK */\n                stat.is_ok = 0; /* Do not reach on OK */\n            }\n            if (esp.msg->msg.conn_send.wait_send_ok_err) {\n                if (!strncmp(\"SEND OK\", rcv->data, 7)) { /* Data were sent successfully */\n                    esp.msg->msg.conn_send.wait_send_ok_err = 0;\n                    stat.is_ok = lwespi_tcpip_process_data_sent(1); /* Process as data were sent */\n                    if (stat.is_ok && esp.msg->msg.conn_send.conn->status.f.active) {\n                        CONN_SEND_DATA_SEND_EVT(esp.msg, lwespOK);\n                    }\n                } else if (stat.is_error || !strncmp(\"SEND FAIL\", rcv->data, 9)) {\n                    esp.msg->msg.conn_send.wait_send_ok_err = 0;\n                    stat.is_error = lwespi_tcpip_process_data_sent(0);\n                    if (stat.is_error && esp.msg->msg.conn_send.conn->status.f.active) {\n                        CONN_SEND_DATA_SEND_EVT(esp.msg, lwespERR);\n                    }\n                }\n            } else if (stat.is_error) {\n                CONN_SEND_DATA_SEND_EVT(esp.msg, lwespERR);\n            }\n        } else if (CMD_IS_CUR(LWESP_CMD_UART)) {                   /* In case of UART command */\n            if (stat.is_ok) {                                      /* We have valid OK result */\n                esp.ll.uart.baudrate = esp.msg->msg.uart.baudrate; /* Save user baudrate */\n                lwesp_ll_init(&esp.ll);                            /* Set new baudrate */\n            }\n        }\n    }\n\n    /*\n     * Check if connection is just active (or closed).\n     *\n     * Check +LINK_CONN messages\n     */\n    if (rcv->len > 20 && (s = strstr(rcv->data, \"+LINK_CONN:\")) != NULL) {\n        /* Parse only valid connections, discard others */\n        if (lwespi_parse_link_conn(s) && esp.m.link_conn.num < LWESP_CFG_MAX_CONNS) {\n            lwesp_conn_t* conn = &esp.m.conns[esp.m.link_conn.num]; /* Get connection pointer */\n            if (esp.m.link_conn.failed && conn->status.f.active) {  /* Connection failed and now closed? */\n                conn->status.f.active = 0;                          /* Connection was just closed */\n\n                esp.evt.type = LWESP_EVT_CONN_CLOSE;\n                esp.evt.evt.conn_active_close.conn = conn;\n                esp.evt.evt.conn_active_close.client = conn->status.f.client; /* Set if it is client or not */\n                /** @todo: Check if we really tried to close connection which was just closed */\n                esp.evt.evt.conn_active_close.forced = CMD_IS_CUR(LWESP_CMD_TCPIP_CIPCLOSE);\n                esp.evt.evt.conn_active_close.client = conn->status.f.client;\n                lwespi_send_conn_cb(conn, NULL); /* Send event */\n\n                /* Check if write buffer is set */\n                if (conn->buff.buff != NULL) {\n                    LWESP_DEBUGF(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, \"[LWESP CONN] Free write buffer: %p\\r\\n\",\n                                 conn->buff.buff);\n                    lwesp_mem_free_s((void**)&conn->buff.buff);\n                }\n            } else if (!esp.m.link_conn.failed && !conn->status.f.active) {\n                LWESP_MEMSET(conn, 0x00, sizeof(*conn));         /* Reset connection parameters */\n                conn->num = esp.m.link_conn.num;                 /* Set connection number */\n                conn->status.f.active = !esp.m.link_conn.failed; /* Check if connection active */\n                conn->val_id = ++conn_val_id;                    /* Set new validation ID */\n                if (conn->val_id == 0) {                         /* Conn ID == 0 is invalid */\n                    conn->val_id = ++conn_val_id;\n                }\n\n                conn->type = esp.m.link_conn.type; /* Set connection type */\n                LWESP_MEMCPY(&conn->remote_ip, &esp.m.link_conn.remote_ip, sizeof(conn->remote_ip));\n                conn->remote_port = esp.m.link_conn.remote_port;\n                conn->local_port = esp.m.link_conn.local_port;\n                conn->status.f.client = !esp.m.link_conn.is_server;\n\n                /* Connection started as client? */\n                if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTART) && conn->status.f.client) {\n                    /* Use connection for user */\n                    if (esp.msg->msg.conn_start.conn != NULL) {\n                        *esp.msg->msg.conn_start.conn = conn;\n                    }\n                    conn->evt_func = esp.msg->msg.conn_start.evt_func; /* Set callback function */\n                    conn->arg = esp.msg->msg.conn_start.arg;           /* Set argument for function */\n                    esp.msg->msg.conn_start.success = 1;\n                } else {                             /* Server connection start */\n                    conn->evt_func = esp.evt_server; /* Set server default callback */\n                    conn->arg = NULL;\n                    conn->type =\n                        LWESP_CONN_TYPE_TCP; /* Set connection type to TCP. @todo: Wait for ESP team to upgrade AT commands to set other type */\n                }\n\n                esp.evt.type = LWESP_EVT_CONN_ACTIVE;                         /* Connection just active */\n                esp.evt.evt.conn_active_close.conn = conn;                    /* Set connection */\n                esp.evt.evt.conn_active_close.client = conn->status.f.client; /* Set if it is client or not */\n                esp.evt.evt.conn_active_close.forced =\n                    conn->status.f.client;       /* Set if action was forced = if client mode */\n                lwespi_send_conn_cb(conn, NULL); /* Send event */\n                lwespi_conn_start_timeout(conn); /* Start connection timeout timer */\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n                lwespi_conn_check_available_rx_data();\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n            }\n        }\n        /*\n        } else if (!strncmp(\",CLOSED\", &rcv->data[1], 7)) {\n            const char* tmp = rcv->data; */\n    } else if ((rcv->len > 9 && (s = strstr(rcv->data, \",CLOSED\" CRLF)) != NULL)\n               || (rcv->len > 15 && (s = strstr(rcv->data, \",CONNECT FAIL\" CRLF)) != NULL)) {\n        const char* tmp = s;\n        uint32_t num = 0;\n        while (tmp > rcv->data && LWESP_CHARISNUM(tmp[-1])) {\n            --tmp;\n        }\n        num = lwespi_parse_number(&tmp); /* Parse connection number */\n        if (num < LWESP_CFG_MAX_CONNS) {\n            lwesp_conn_t* conn = &esp.m.conns[num]; /* Parse received data */\n            conn->num = num;                        /* Set connection number */\n            if (conn->status.f.active) {            /* Is connection actually active? */\n                conn->status.f.active = 0;          /* Connection was just closed */\n\n                esp.evt.type = LWESP_EVT_CONN_CLOSE;\n                esp.evt.evt.conn_active_close.conn = conn;\n                esp.evt.evt.conn_active_close.client = conn->status.f.client; /* Set if it is client or not */\n                esp.evt.evt.conn_active_close.forced = CMD_IS_CUR(\n                    LWESP_CMD_TCPIP_CIPCLOSE); /* Set if action was forced = current action = close connection */\n                esp.evt.evt.conn_active_close.res = lwespOK;\n                lwespi_send_conn_cb(conn, NULL); /* Send event */\n\n                /*\n                 * In case we received x,CLOSED on connection we are currently sending data,\n                 * terminate sending of connection with failure\n                 */\n                if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSEND)) {\n                    if (esp.msg->msg.conn_send.conn == conn) {\n                        /** \\todo: Find better idea to handle what to do in this case */\n                        //is_error = 1;         /* Set as error to stop processing or waiting for connection */\n                    }\n                }\n            }\n\n            /* Check if write buffer is set */\n            if (conn->buff.buff != NULL) {\n                LWESP_DEBUGF(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE, \"[LWESP CONN] Free write buffer: %p\\r\\n\",\n                             conn->buff.buff);\n                lwesp_mem_free_s((void**)&conn->buff.buff);\n            }\n        }\n    } else if (stat.is_error && CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTART)) {\n        /*\n         * Notify user about failed connection,\n         * but only if connection callback is known.\n         *\n         * This will prevent notifying wrong connection\n         * in case connection is already active for some reason\n         * but new callback is not set by user\n         */\n        if (esp.msg->msg.conn_start.evt_func != NULL) { /* Connection must be closed */\n            lwespi_send_conn_error_cb(esp.msg, lwespERRCONNFAIL);\n        }\n    }\n\n    /*\n     * In case of any of these events, simply release semaphore\n     * and proceed with next command\n     */\n    if (stat.is_ok || stat.is_error || stat.is_ready) {\n        lwespr_t res = lwespOK;\n        if (esp.msg != NULL) { /* Do we have active message? */\n            res = lwespi_process_sub_cmd(esp.msg, &stat);\n            if (res != lwespCONT) {                /* Shall we continue with next subcommand under this one? */\n                if (stat.is_ok || stat.is_ready) { /* Check ready or ok status */\n                    res = esp.msg->res = lwespOK;\n                } else {                      /* Or error status */\n                    res = esp.msg->res = res; /* Set the error status */\n                }\n            } else {\n                ++esp.msg->i; /* Number of continue calls */\n            }\n\n            /*\n             * When the command is finished,\n             * release synchronization semaphore\n             * from user thread and start with next command\n             */\n            if (res != lwespCONT) {                   /* Do we have to continue to wait for command? */\n                lwesp_sys_sem_release(&esp.sem_sync); /* Release semaphore */\n            }\n        }\n    }\n}\n\n#if !LWESP_CFG_INPUT_USE_PROCESS || __DOXYGEN__\n/**\n * \\brief           Process data from input buffer\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwespi_process_buffer(void) {\n    void* data;\n    size_t len;\n\n    do {\n        /*\n         * Get length of linear memory in buffer\n         * we can process directly as memory\n         */\n        len = lwesp_buff_get_linear_block_read_length(&esp.buff);\n        if (len > 0) {\n            /*\n             * Get memory address of first element\n             * in linear block of data to process\n             */\n            data = lwesp_buff_get_linear_block_read_address(&esp.buff);\n\n            /* Process actual received data */\n            lwespi_process(data, len);\n\n            /*\n             * Once data is processed, simply skip\n             * the buffer memory and start over\n             */\n            lwesp_buff_skip(&esp.buff, len);\n        }\n    } while (len > 0);\n    return lwespOK;\n}\n#endif /* !LWESP_CFG_INPUT_USE_PROCESS || __DOXYGEN__ */\n\n/**\n * \\brief           Process input data received from ESP device\n * \\param[in]       data: Pointer to data to process\n * \\param[in]       data_len: Length of data to process in units of bytes\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwespi_process(const void* data, size_t data_len) {\n    uint8_t ch;\n    const uint8_t* d = data;\n    size_t d_len = data_len;\n    static uint8_t ch_prev1;\n    static lwesp_unicode_t unicode = {0};\n\n    /* Check status if device is available */\n    if (!esp.status.f.dev_present) {\n        return lwespERRNODEVICE;\n    }\n\n    while (d_len > 0) {\n        ch = *d;\n        ++d;\n        --d_len;\n\n        /*\n         * This is auto read for UDP connections,\n         * or if random connection sends data out w/o manual request!\n         * \n         * It is critual to support automatic mode too\n         */\n        if (esp.m.ipd.read) {\n            size_t len;\n\n            if (esp.m.ipd.buff != NULL) {\n                esp.m.ipd.buff->payload[esp.m.ipd.buff_ptr] = ch; /* Save data character */\n            }\n            ++esp.m.ipd.buff_ptr;\n            --esp.m.ipd.rem_len;\n\n            /* Get remaining data */\n            len = LWESP_MIN(d_len, LWESP_MIN(esp.m.ipd.rem_len, esp.m.ipd.buff != NULL\n                                                                    ? (esp.m.ipd.buff->len - esp.m.ipd.buff_ptr)\n                                                                    : esp.m.ipd.rem_len));\n            LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE, \"[LWESP IPD] New length to read: %d bytes\\r\\n\",\n                         (int)len);\n            if (len > 0) {\n                if (esp.m.ipd.buff != NULL) { /* Is buffer valid? */\n                    LWESP_MEMCPY(&esp.m.ipd.buff->payload[esp.m.ipd.buff_ptr], d, len);\n                }\n                d_len -= len;              /* Decrease effective length */\n                d += len;                  /* Skip remaining length */\n                esp.m.ipd.buff_ptr += len; /* Forward buffer pointer */\n                esp.m.ipd.rem_len -= len;  /* Decrease remaining length */\n\n                LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE, \"[LWESP IPD] Bytes %s: %d\\r\\n\",\n                             esp.m.ipd.buff != NULL ? \"read\" : \"skipped\", (int)len);\n            }\n\n            /* Did we reach end of buffer or no more data? */\n            if (esp.m.ipd.rem_len == 0 || (esp.m.ipd.buff != NULL && esp.m.ipd.buff_ptr == esp.m.ipd.buff->len)) {\n                lwespr_t res = lwespOK;\n\n                /* Call user callback function with received data */\n                if (esp.m.ipd.buff != NULL) { /* Do we have valid buffer? */\n                    size_t pbuf_len;\n\n                    pbuf_len = lwesp_pbuf_length(esp.m.ipd.buff, 1);\n                    esp.m.ipd.conn->tcp_not_ack_bytes += pbuf_len;\n                    esp.m.ipd.conn->total_recved += esp.m.ipd.buff->tot_len; /* Increase number of bytes received */\n\n                    /*\n                     * Send data buffer to upper layer\n                     *\n                     * From this moment, user is responsible for packet\n                     * buffer and must free it manually\n                     */\n                    esp.evt.type = LWESP_EVT_CONN_RECV;\n                    esp.evt.evt.conn_data_recv.buff = esp.m.ipd.buff;\n                    esp.evt.evt.conn_data_recv.conn = esp.m.ipd.conn;\n                    res = lwespi_send_conn_cb(esp.m.ipd.conn, NULL);\n\n                    lwesp_pbuf_free(esp.m.ipd.buff); /* Free packet buffer at this point */\n                    LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE, \"[LWESP IPD] Free packet buffer\\r\\n\");\n                    if (res == lwespOKIGNOREMORE) { /* We should ignore more data */\n                        LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE,\n                                     \"[LWESP IPD] Ignoring more data from this IPD if available\\r\\n\");\n                        esp.m.ipd.buff = NULL; /* Set to NULL to ignore more data if possibly available */\n                    }\n\n                    /*\n                     * Create new data packet if case if:\n                     *\n                     *  - Previous one was successful and more data to read and\n                     *  - Connection is not in closing state\n                     */\n                    if (esp.m.ipd.buff != NULL && esp.m.ipd.rem_len > 0 && !esp.m.ipd.conn->status.f.in_closing) {\n                        size_t new_len = LWESP_MIN(esp.m.ipd.rem_len,\n                                                   LWESP_CFG_CONN_MAX_RECV_BUFF_SIZE); /* Calculate new buffer length */\n\n                        LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE,\n                                     \"[LWESP IPD] Allocating new packet buffer of size: %d bytes\\r\\n\", (int)new_len);\n                        esp.m.ipd.buff = lwesp_pbuf_new(new_len); /* Allocate new packet buffer */\n\n                        LWESP_DEBUGW(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING,\n                                     esp.m.ipd.buff == NULL, \"[LWESP IPD] Buffer allocation failed for %d bytes\\r\\n\",\n                                     (int)new_len);\n\n                        if (esp.m.ipd.buff != NULL) {\n                            lwesp_pbuf_set_ip(esp.m.ipd.buff, &esp.m.ipd.ip,\n                                              esp.m.ipd.port); /* Set IP and port for received data */\n                        }\n                    } else {\n                        esp.m.ipd.buff = NULL; /* Reset it */\n                    }\n                }\n                if (esp.m.ipd.rem_len == 0) { /* Check if we read everything */\n                    esp.m.ipd.buff = NULL;    /* Reset buffer pointer */\n                    esp.m.ipd.read = 0;       /* Stop reading data */\n                }\n                esp.m.ipd.buff_ptr = 0; /* Reset input buffer pointer */\n                RECV_RESET();           /* Reset receive data */\n            }\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n            /*\n             * First check if we are in IPD mode and process plain data\n             * without checking for valid ASCII or unicode format\n             */\n        } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPRECVDATA) && esp.msg->msg.conn_recv.read) {\n            size_t len;\n\n            if (esp.msg->msg.conn_recv.buff != NULL) { /* Do we have active buffer? */\n                esp.msg->msg.conn_recv.buff->payload[esp.msg->msg.conn_recv.buff_ptr] = ch; /* Save data character */\n            }\n            ++esp.msg->msg.conn_recv.buff_ptr;\n\n            /* Try to read more data directly from buffer */\n            len = LWESP_MIN(d_len, esp.msg->msg.conn_recv.tot_len - esp.msg->msg.conn_recv.buff_ptr);\n            LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE, \"[LWESP IPD] New length to read: %d bytes\\r\\n\",\n                         (int)len);\n            if (len > 0) {\n                if (esp.msg->msg.conn_recv.buff != NULL) { /* Is buffer valid? */\n                    LWESP_MEMCPY(&esp.msg->msg.conn_recv.buff->payload[esp.msg->msg.conn_recv.buff_ptr], d, len);\n                }\n                d_len -= len;                           /* Decrease effective length */\n                d += len;                               /* Skip remaining length */\n                esp.msg->msg.conn_recv.buff_ptr += len; /* Forward buffer pointer */\n\n                LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE, \"[LWESP IPD] Bytes %s: %d\\r\\n\",\n                             esp.msg->msg.conn_recv.buff != NULL ? \"read\" : \"skipped\", (int)len);\n            }\n\n            /* Did we reach end of buffer or no more data? */\n            if (esp.msg->msg.conn_recv.buff_ptr == esp.msg->msg.conn_recv.tot_len) {\n                esp.msg->msg.conn_recv.read = 0; /* Stop reading data */\n\n                /* Call user callback function with received data */\n                if (esp.msg->msg.conn_recv.buff != NULL) { /* Do we have valid buffer? */\n                    esp.msg->msg.conn_recv.conn->tcp_not_ack_bytes += esp.msg->msg.conn_recv.tot_len;\n                    esp.msg->msg.conn_recv.conn->total_recved += esp.msg->msg.conn_recv.tot_len;\n\n                    /*\n                     * Send data buffer to upper layer\n                     *\n                     * From this moment, user is responsible for packet\n                     * buffer and must free it manually\n                     */\n                    esp.evt.type = LWESP_EVT_CONN_RECV;\n                    esp.evt.evt.conn_data_recv.conn = esp.msg->msg.conn_recv.conn;\n                    esp.evt.evt.conn_data_recv.buff = esp.msg->msg.conn_recv.buff;\n                    lwespi_send_conn_cb(esp.msg->msg.conn_recv.conn, NULL);\n                    lwesp_pbuf_free_s(&esp.msg->msg.conn_recv.buff); /* Free packet buffer at this point */\n                }\n            }\n\n            /*\n             * We are in command mode where we have to process byte by byte\n             * Simply check for ASCII and unicode format and process data accordingly\n             */\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n#if LWESP_CFG_FLASH\n        } else if (CMD_IS_CUR(LWESP_CMD_SYSMFG_READ) && esp.msg->msg.mfg_read.read_mode) {\n            size_t len;\n\n            /* Save current character */\n            esp.msg->msg.mfg_read.data_ptr[esp.msg->msg.mfg_read.buff_ptr++] = ch;\n\n            /* Try to do more in a loop */\n            len = LWESP_MIN(d_len, esp.msg->msg.mfg_read.btr - esp.msg->msg.mfg_read.buff_ptr);\n            if (len > 0) {\n                LWESP_MEMCPY(&esp.msg->msg.mfg_read.data_ptr[esp.msg->msg.mfg_read.buff_ptr], d, len);\n                d_len -= len;                          /* Decrease effective length */\n                d += len;                              /* Skip remaining length */\n                esp.msg->msg.mfg_read.buff_ptr += len; /* Forward buffer pointer */\n            }\n\n            /* Check for end of data */\n            if (esp.msg->msg.mfg_read.buff_ptr == esp.msg->msg.mfg_read.btr) {\n                esp.msg->msg.mfg_read.read_mode = 0;\n                if (esp.msg->msg.mfg_read.br != NULL) {\n                    *esp.msg->msg.mfg_read.br = esp.msg->msg.mfg_read.btr;\n                }\n            }\n#endif /* LWESP_CFG_FLASH */\n        } else {\n            lwespr_t res = lwespERR;\n            if (LWESP_ISVALIDASCII(ch)) { /* Manually check if valid ASCII character */\n                res = lwespOK;\n                unicode.t = 1;                             /* Manually set total to 1 */\n                unicode.r = 0;                             /* Reset remaining bytes */\n            } else if (ch >= 0x80) {                       /* Process only if more than ASCII can hold */\n                res = lwespi_unicode_decode(&unicode, ch); /* Try to decode unicode format */\n            }\n\n            if (res == lwespERR) { /* In case of an ERROR */\n                unicode.r = 0;\n            }\n            if (res == lwespOK) {     /* Can we process the character(s) */\n                if (unicode.t == 1) { /* Totally 1 character? */\n                    char* tmp_ptr = NULL;\n\n                    LWESP_UNUSED(tmp_ptr); /* May be unused */\n\n                    RECV_ADD(ch); /* Add character to input buffer */\n                    if (ch == '\\n') {\n                        lwespi_parse_received(&recv_buff); /* Parse received string */\n                        RECV_RESET();                      /* Reset received string */\n                    }\n\n                    /* If we are waiting for \"\\n> \" sequence when CIPSEND command is active */\n                    if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSEND)) {\n                        if (ch == '>' && ch_prev1 == '\\n') {\n                            RECV_RESET(); /* Reset received object */\n\n                            /* Now actually send the data prepared for TX before */\n                            AT_PORT_SEND_WITH_FLUSH(&esp.msg->msg.conn_send.data[esp.msg->msg.conn_send.ptr],\n                                                    esp.msg->msg.conn_send.sent);\n                            /* Now we are waiting for \"SEND OK\" or \"SEND ERROR\" */\n                            esp.msg->msg.conn_send.wait_send_ok_err = 1;\n                        }\n#if LWESP_CFG_FLASH\n                    } else if (CMD_IS_CUR(LWESP_CMD_SYSFLASH_WRITE)) {\n                        if (ch == '>' && ch_prev1 == '\\n') {\n                            RECV_RESET(); /* Reset received object */\n                            AT_PORT_SEND_WITH_FLUSH(esp.msg->msg.flash_write.data, esp.msg->msg.flash_write.length);\n                        }\n                    } else if (CMD_IS_CUR(LWESP_CMD_SYSMFG_WRITE)) {\n                        /* Only non-primitive types are written from here */\n                        if (!LWESP_MFG_VALTYPE_IS_PRIM(esp.msg->msg.mfg_write.valtype) && ch == '>'\n                            && ch_prev1 == '\\n') {\n                            RECV_RESET(); /* Reset received object */\n                            AT_PORT_SEND_WITH_FLUSH(esp.msg->msg.mfg_write.data_ptr, esp.msg->msg.mfg_write.length);\n                        }\n                    } else if (CMD_IS_CUR(LWESP_CMD_SYSMFG_READ)) {\n                        if (ch == ',' && RECV_LEN() > 7 && RECV_IDX(0) == '+' && !strncmp(recv_buff.data, \"+SYSMFG\", 7)\n                            && (tmp_ptr = strchr(recv_buff.data, ',')) != NULL /* Search for first comma */\n                            && (tmp_ptr = strchr(tmp_ptr + 1, ',')) != NULL    /* Search for second comma */\n                            && (tmp_ptr = strchr(tmp_ptr + 1, ',')) != NULL    /* Search for third comma */\n                            && (tmp_ptr = strchr(tmp_ptr + 1, ',')) != NULL /* Search for 4th comma */) {\n                            lwespi_parse_received(&recv_buff);\n                            RECV_RESET();\n                        }\n#endif /* LWESP_CFG_FLASH */\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n                        /*\n                         * This part handles the response of \"+CIPRECVDATA\",\n                         * that does not end with CRLF, rather string continues with user data.\n                         * \n                         * We cannot rely on line processing.\n                         *\n                         * +CIPRECVDATA:<len>,<IP>,<port>,data...\n                         *\n                         * We expect 3 colon characters, only then we can move forward.\n                         * Appropriate reset commands have to be sent in order for this to work properly,\n                         * to enable IP and port information\n                         */\n                    } else if (ch == ',' && RECV_LEN() > 13 && RECV_IDX(0) == '+'\n                               && !strncmp(recv_buff.data, \"+CIPRECVDATA\", 12)\n                               && (tmp_ptr = strchr(recv_buff.data, ',')) != NULL /* Search for first comma */\n                               && (tmp_ptr = strchr(tmp_ptr + 1, ',')) != NULL    /* Search for second comma */\n                               && (tmp_ptr = strchr(tmp_ptr + 1, ',')) != NULL) { /* Search for third comma */\n                        lwespi_parse_received(&recv_buff);                        /* Parse received string */\n                        RECV_RESET();\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n                    } else if (ch == ':' && RECV_LEN() > 4 && RECV_IDX(0) == '+'\n                               && strncmp(recv_buff.data, \"+IPD\", 4) == 0) {\n                        lwespi_parse_received(&recv_buff);\n                        if (esp.m.ipd.read) {\n                            size_t len;\n                            LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE,\n                                         \"[LWESP IPD] Data on connection %d with total size %d byte(s)\\r\\n\",\n                                         (int)esp.m.ipd.conn->num, (int)esp.m.ipd.tot_len);\n\n                            len = LWESP_MIN(esp.m.ipd.rem_len, LWESP_CFG_CONN_MAX_RECV_BUFF_SIZE);\n\n                            /*\n                             * Read received data in case of:\n                             *\n                             *  - Connection is active and\n                             *  - Connection is not in closing mode\n                             */\n                            if (esp.m.ipd.conn->status.f.active && !esp.m.ipd.conn->status.f.in_closing) {\n                                esp.m.ipd.buff = lwesp_pbuf_new(len); /* Allocate new packet buffer */\n                                if (esp.m.ipd.buff != NULL) {\n                                    /* Set IP and port for received data */\n                                    lwesp_pbuf_set_ip(esp.m.ipd.buff, &esp.m.ipd.ip, esp.m.ipd.port);\n                                }\n                                LWESP_DEBUGW(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING,\n                                             esp.m.ipd.buff == NULL,\n                                             \"[LWESP IPD] Buffer allocation failed for %d byte(s)\\r\\n\", (int)len);\n                            } else {\n                                esp.m.ipd.buff = NULL; /* Ignore reading on closed connection */\n                                LWESP_DEBUGF(LWESP_CFG_DBG_IPD | LWESP_DBG_TYPE_TRACE,\n                                             \"[LWESP IPD] Connection %d closed or in closing, skipping %d byte(s)\\r\\n\",\n                                             (int)esp.m.ipd.conn->num, (int)len);\n                            }\n                            esp.m.ipd.conn->status.f.data_received = 1; /* We have first received data */\n                            esp.m.ipd.buff_ptr = 0;                     /* Reset buffer write pointer */\n                        }\n                        RECV_RESET(); /* Reset received buffer */\n                    }\n                } else { /* We have sequence of unicode characters */\n                    /*\n                     * Unicode sequence characters are not \"meta\" characters\n                     * so it is safe to just add them to receive array without checking\n                     * what are the actual values\n                     */\n                    for (uint8_t i = 0; i < unicode.t; ++i) {\n                        RECV_ADD(unicode.ch[i]); /* Add character to receive array */\n                    }\n                }\n            } else if (res != lwespINPROG) { /* Not in progress? */\n                RECV_RESET();                /* Invalid character in sequence */\n            }\n        }\n        ch_prev1 = ch; /* Set current as previous */\n    }\n    return lwespOK;\n}\n\n/* Temporary macros, only available for inside gsmi_process_sub_cmd function */\n/* Set new command, but first check for error on previous */\n#define SET_NEW_CMD_CHECK_ERROR(new_cmd)                                                                               \\\n    do {                                                                                                               \\\n        if (!*(is_error)) {                                                                                            \\\n            n_cmd = (new_cmd);                                                                                         \\\n        }                                                                                                              \\\n    } while (0)\n\n/* Set new command, ignore result of previous */\n#define SET_NEW_CMD(new_cmd)                                                                                           \\\n    do {                                                                                                               \\\n        n_cmd = (new_cmd);                                                                                             \\\n    } while (0)\n\n/* Set new cmd if condition passes */\n#define SET_NEW_CMD_COND(new_cmd, cond)                                                                                \\\n    do {                                                                                                               \\\n        if ((cond)) {                                                                                                  \\\n            n_cmd = (new_cmd);                                                                                         \\\n        }                                                                                                              \\\n    } while (0)\n\n/**\n * \\brief           Get next sub command for reset or restore sequence\n * \\param[in]       msg: Pointer to current message\n * \\param[in]       is_ok: Status flags from command execution\n * \\return          Next command to execute\n */\nstatic lwesp_cmd_t\nlwespi_get_reset_sub_cmd(lwesp_msg_t* msg, lwesp_status_flags_t* stat) {\n    lwesp_cmd_t n_cmd = LWESP_CMD_IDLE;\n    switch (CMD_GET_CUR()) {\n        case LWESP_CMD_RESET:\n        case LWESP_CMD_RESTORE: SET_NEW_CMD(LWESP_CFG_AT_ECHO ? LWESP_CMD_ATE1 : LWESP_CMD_ATE0); break;\n        case LWESP_CMD_ATE0:\n        case LWESP_CMD_ATE1: SET_NEW_CMD(LWESP_CMD_GMR); break;\n        case LWESP_CMD_GMR:\n#if LWESP_CFG_LIST_CMD\n            SET_NEW_CMD(LWESP_CMD_CMD);\n            break;\n        case LWESP_CMD_CMD:\n#endif /* LWESP_CFG_LIST_CMD */\n            SET_NEW_CMD(LWESP_CMD_SYSMSG);\n            break;\n        case LWESP_CMD_SYSMSG:\n#if LWESP_CFG_FLASH && defined(LWESP_DEV)\n            SET_NEW_CMD(LWESP_CMD_SYSFLASH_GET);\n            break;\n        case LWESP_CMD_SYSFLASH_GET: SET_NEW_CMD(LWESP_CMD_SYSMFG_GET); break;\n        case LWESP_CMD_SYSMFG_GET:\n#endif /* LWESP_CFG_FLASH && defined(LWESP_DEV) */\n            SET_NEW_CMD(LWESP_CMD_SYSLOG);\n            break;\n        case LWESP_CMD_SYSLOG: SET_NEW_CMD(LWESP_CMD_RFPOWER); break;\n        case LWESP_CMD_RFPOWER: SET_NEW_CMD(LWESP_CMD_WIFI_CWMODE); break;\n        case LWESP_CMD_WIFI_CWMODE: SET_NEW_CMD(LWESP_CMD_WIFI_CWDHCP_GET); break;\n        case LWESP_CMD_WIFI_CWDHCP_GET: SET_NEW_CMD(LWESP_CMD_TCPIP_CIPMUX); break;\n        case LWESP_CMD_TCPIP_CIPMUX: SET_NEW_CMD(LWESP_CMD_TCPIP_CIPRECVMODE); break;\n        case LWESP_CMD_TCPIP_CIPRECVMODE:\n#if LWESP_CFG_IPV6\n            SET_NEW_CMD(LWESP_CMD_WIFI_IPV6);\n            break;\n        case LWESP_CMD_WIFI_IPV6:\n#endif /* LWESP_CFG_IPV6 */\n#if LWESP_CFG_MODE_STATION\n            SET_NEW_CMD(LWESP_CMD_WIFI_CWLAPOPT);\n            break; /* Set visible data for CWLAP command */\n        case LWESP_CMD_WIFI_CWLAPOPT: SET_NEW_CMD(LWESP_CMD_TCPIP_CIPSTATUS); break;  /* Get connection status */\n        case LWESP_CMD_TCPIP_CIPSTATUS: SET_NEW_CMD(LWESP_CMD_TCPIP_CIPSTATE); break; /* Get connection status */\n        case LWESP_CMD_TCPIP_CIPSTATE:\n#endif /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n            SET_NEW_CMD(LWESP_CMD_WIFI_CIPAP_GET);\n            break;                                                                      /* Get access point IP */\n        case LWESP_CMD_WIFI_CIPAP_GET: SET_NEW_CMD(LWESP_CMD_WIFI_CIPAPMAC_GET); break; /* Get access point MAC */\n        case LWESP_CMD_WIFI_CIPAPMAC_GET:\n#endif /* LWESP_CFG_MODE_STATION */\n            SET_NEW_CMD(LWESP_CMD_TCPIP_CIPDINFO);\n            break; /* Set visible data on +IPD */\n        default: break;\n    }\n    LWESP_UNUSED(msg);\n    LWESP_UNUSED(stat);\n    return n_cmd;\n}\n\n/**\n * \\brief           Process current command with known execution status and start another if necessary\n * \\param[in]       msg: Pointer to current message\n * \\param[in]       stat: Pointer to status flags\n * \\return          lwespCONT if you sent more data and we need to process more data, or lwespOK on success, or lwespERR on error\n */\nstatic lwespr_t\nlwespi_process_sub_cmd(lwesp_msg_t* msg, lwesp_status_flags_t* stat) {\n    lwesp_cmd_t n_cmd = LWESP_CMD_IDLE;\n    if (CMD_IS_DEF(LWESP_CMD_RESET)) { /* Device is in reset mode */\n        n_cmd = lwespi_get_reset_sub_cmd(msg, stat);\n        if (n_cmd == LWESP_CMD_IDLE) { /* Last command? */\n            RESET_SEND_EVT(msg, stat->is_ok ? lwespOK : lwespERR);\n        }\n    } else if (CMD_IS_DEF(LWESP_CMD_RESTORE)) {\n        if ((CMD_IS_CUR(LWESP_CMD_RESET)) && stat->is_ready) {\n            SET_NEW_CMD(LWESP_CMD_RESTORE);\n        } else if ((CMD_IS_CUR(LWESP_CMD_RESTORE) && stat->is_ready) || !CMD_IS_CUR(LWESP_CMD_RESTORE)) {\n            SET_NEW_CMD(lwespi_get_reset_sub_cmd(msg, stat));\n        }\n        if (n_cmd == LWESP_CMD_IDLE) {\n            RESTORE_SEND_EVT(msg, stat->is_ok ? lwespOK : lwespERR);\n        }\n#if LWESP_CFG_MODE_STATION\n    } else if (CMD_IS_DEF(LWESP_CMD_WIFI_CWJAP)) {      /* Is our intention to join to access point? */\n        if (CMD_IS_CUR(LWESP_CMD_WIFI_CWJAP)) {         /* Is the current command join? */\n            if (stat->is_ok) {                          /* Did we join successfully? */\n                SET_NEW_CMD(LWESP_CMD_WIFI_CWDHCP_GET); /* Check IP address status */\n            } else {\n                esp.m.sta.f.has_ip = 0;       /* Has NO IP */\n                esp.m.sta.f.is_connected = 0; /* Force disconnected status */\n#if LWESP_CFG_IPV6\n                esp.m.sta.f.has_ipv6_ll = 0;\n                esp.m.sta.f.has_ipv6_gl = 0;\n#endif /* LWESP_CFG_IPV6 */\n                /*\n                 * Parse received error message,\n                 * if final result was error, decide what type\n                 * of error should be returned for user\n                 */\n                if (msg->msg.sta_join.error_num == 1) {\n                    esp.evt.evt.sta_join_ap.res = lwespERRCONNTIMEOUT;\n                } else if (msg->msg.sta_join.error_num == 2) {\n                    esp.evt.evt.sta_join_ap.res = lwespERRPASS;\n                } else if (msg->msg.sta_join.error_num == 3) {\n                    esp.evt.evt.sta_join_ap.res = lwespERRNOAP;\n                } else if (msg->msg.sta_join.error_num == 4) {\n                    esp.evt.evt.sta_join_ap.res = lwespERRCONNFAIL;\n                } else {\n                    esp.evt.evt.sta_join_ap.res = lwespERR;\n                }\n                msg->res_err_code = esp.evt.evt.sta_join_ap.res;\n            }\n        } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWDHCP_GET)) {\n            SET_NEW_CMD(LWESP_CMD_WIFI_CIPSTA_GET); /* Get IP address */\n        } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTA_GET)) {\n            lwespi_send_cb(LWESP_EVT_WIFI_IP_ACQUIRED); /* Notify upper layer */\n            SET_NEW_CMD(LWESP_CMD_WIFI_CIPSTAMAC_GET);  /* Go to next command to get MAC address */\n        } else {\n            esp.evt.evt.sta_join_ap.res = lwespOK; /* Connected ok */\n        }\n\n        /* Check command finish */\n        if (n_cmd == LWESP_CMD_IDLE) {\n            STA_JOIN_AP_SEND_EVT(msg, esp.evt.evt.sta_join_ap.res);\n        }\n    } else if (CMD_IS_DEF(LWESP_CMD_WIFI_CWLAP)) {\n        STA_LIST_AP_SEND_EVT(msg, stat->is_ok ? lwespOK : lwespERR);\n    } else if (CMD_IS_DEF(LWESP_CMD_WIFI_CWJAP_GET)) {\n        STA_INFO_AP_SEND_EVT(msg, stat->is_ok ? lwespOK : lwespERR);\n    } else if (CMD_IS_DEF(LWESP_CMD_WIFI_CIPSTA_SET)) {\n        if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTA_SET)) {\n            SET_NEW_CMD(LWESP_CMD_WIFI_CWDHCP_GET);\n        } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWDHCP_GET)) {\n            SET_NEW_CMD(LWESP_CMD_WIFI_CIPSTA_GET);\n        } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTA_GET)) {\n            lwespi_send_cb(LWESP_EVT_WIFI_IP_ACQUIRED); /* Notify upper layer */\n        }\n    } else if (CMD_IS_DEF(LWESP_CMD_WIFI_CIPSTA_GET)) {\n        if (CMD_IS_CUR(LWESP_CMD_WIFI_CWDHCP_GET)) {\n            SET_NEW_CMD(LWESP_CMD_WIFI_CIPSTA_GET);\n        } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTA_GET)) {\n            lwespi_send_cb(LWESP_EVT_WIFI_IP_ACQUIRED);\n        }\n#endif /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n    } else if (CMD_IS_DEF(LWESP_CMD_WIFI_CWMODE)\n               && (msg->msg.wifi_mode.mode == LWESP_MODE_AP\n#if LWESP_CFG_MODE_STATION\n                   || msg->msg.wifi_mode.mode == LWESP_MODE_STA_AP\n#endif /* LWESP_CFG_MODE_STATION */\n                   )) {\n        if (CMD_IS_CUR(LWESP_CMD_WIFI_CWMODE)) {\n            SET_NEW_CMD_COND(LWESP_CMD_WIFI_CIPAP_GET, stat->is_ok);\n        } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPAP_GET)) {\n            SET_NEW_CMD_COND(LWESP_CMD_WIFI_CWDHCP_GET, stat->is_ok);\n        } else if (CMD_IS_CUR(LWESP_CMD_WIFI_CWDHCP_GET)) {\n            SET_NEW_CMD_COND(LWESP_CMD_WIFI_CIPAPMAC_GET, stat->is_ok);\n        }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n#if LWESP_CFG_DNS\n    } else if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPDOMAIN)) {\n        CIPDOMAIN_SEND_EVT(esp.msg, stat->is_ok ? lwespOK : lwespERR);\n#endif /* LWESP_CFG_DNS */\n#if LWESP_CFG_PING\n    } else if (CMD_IS_DEF(LWESP_CMD_TCPIP_PING)) {\n        PING_SEND_EVT(esp.msg, stat->is_ok ? lwespOK : lwespERR);\n#endif /* LWESP_CFG_PING */\n#if LWESP_CFG_SNTP\n    } else if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSNTPTIME)) {\n        SNTP_TIME_SEND_EVT(esp.msg, stat->is_ok ? lwespOK : lwespERR);\n#endif                                                 /* LWESP_CFG_SNTP */\n    } else if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSTART)) { /* Is our intention to join to access point? */\n        uint8_t is_status_check;\n\n        /*\n         * Check if current command is to get device connection status information.\n         *\n         * ESP8266 & ESP32 uses CIPSTATUS command\n         * ESP32-C2/C3/C6 has CIPSTATE already implemented (CIPSTATUS is deprecated)\n         */\n        is_status_check = CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTATUS) || CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTATE);\n\n        if (msg->i == 0 && is_status_check) {                        /* Was the current command status info? */\n            SET_NEW_CMD_COND(LWESP_CMD_TCPIP_CIPSTART, stat->is_ok); /* Now actually start connection */\n        } else if (msg->i == 1 && CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTART)) {\n            SET_NEW_CMD(lwespi_get_cipstatus_or_cipstate_cmd());\n        } else if (msg->i == 2 && is_status_check) {\n            /* Check if connect actually succeeded */\n            if (!msg->msg.conn_start.success) {\n                stat->is_ok = 0;\n                stat->is_error = 1;\n            }\n        }\n    } else if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPCLOSE)) {\n        if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPCLOSE) && stat->is_error) {\n            /* Notify upper layer about failed close event */\n            esp.evt.type = LWESP_EVT_CONN_CLOSE;\n            esp.evt.evt.conn_active_close.conn = msg->msg.conn_close.conn;\n            esp.evt.evt.conn_active_close.forced = 1;\n            esp.evt.evt.conn_active_close.res = lwespERR;\n            esp.evt.evt.conn_active_close.client =\n                msg->msg.conn_close.conn->status.f.active && msg->msg.conn_close.conn->status.f.client;\n            lwespi_send_conn_cb(msg->msg.conn_close.conn, NULL);\n        }\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n    } else if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPRECVDATA)) {\n        if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPRECVLEN) && msg->msg.conn_recv.is_last_check == 0) {\n            uint8_t set_error = 0;\n            LWESP_DEBUGW(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_SEVERE, stat->is_error,\n                         \"[LWESP CONN] CIPRECVLEN returned ERROR\\r\\n\");\n\n            if (stat->is_ok) {\n                /* Check if `+IPD` received during data length check */\n                if (esp.msg->msg.conn_recv.ipd_recv) {\n                    esp.msg->msg.conn_recv.ipd_recv = 0;\n                    SET_NEW_CMD(LWESP_CMD_TCPIP_CIPRECVLEN);\n                } else {\n                    size_t len;\n\n                    /* Number of bytes to read */\n                    len = LWESP_MIN(LWESP_CFG_CONN_MAX_DATA_LEN, msg->msg.conn_recv.conn->tcp_available_bytes);\n                    if (len > 0) {\n                        lwesp_pbuf_p p = NULL;\n\n                        /* Try to allocate packet buffer */\n                        do {\n                            p = lwesp_pbuf_new(len);\n                        } while (p == NULL && (len = (len >> 1)) >= LWESP_CFG_CONN_MIN_DATA_LEN);\n\n                        /* Start reading procedure */\n                        if (p != NULL) {\n                            msg->msg.conn_recv.buff = p;\n                            msg->msg.conn_recv.len = len;\n                            SET_NEW_CMD(LWESP_CMD_TCPIP_CIPRECVDATA);\n                        } else {\n                            set_error = 1;\n                            LWESP_DEBUGW(LWESP_CFG_DBG_CONN | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_SEVERE,\n                                         stat->is_error, \"[LWESP CONN] Failed to allocate pbuf for data receive\\r\\n\");\n                        }\n                    } else {\n                        /* No error if buffer empty */\n                    }\n                }\n            } else {\n                set_error = 1;\n            }\n            if (set_error) {\n                stat->is_ok = 0;\n                stat->is_error = 1;\n            }\n        } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPRECVDATA)) {\n            /* Read failed? Handle queue len */\n            if (stat->is_error) {\n                if (msg->msg.conn_recv.buff != NULL) {\n                    lwesp_pbuf_free_s(&msg->msg.conn_recv.buff);\n                }\n            }\n\n            /* This one is optional, to check for more data just at the end */\n            SET_NEW_CMD(LWESP_CMD_TCPIP_CIPRECVLEN); /* Inquiry for latest status on data */\n            msg->msg.conn_recv.is_last_check = 1;\n        } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPRECVLEN) && msg->msg.conn_recv.is_last_check == 1) {\n            /* Do nothing */\n            if (stat->is_error) {\n                stat->is_error = 0;\n                stat->is_ok = 1;\n            }\n        }\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n    } else if (CMD_IS_DEF(LWESP_CMD_WIFI_CWDHCP_SET)) {\n        if (CMD_IS_CUR(LWESP_CMD_WIFI_CWDHCP_SET)) {\n            SET_NEW_CMD(LWESP_CMD_WIFI_CWDHCP_GET);\n        }\n    }\n\n    /* Are we enabling server mode for some reason? */\n    if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSERVER)) {\n        if (msg->msg.tcpip_server.en) {\n            if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSERVERMAXCONN)) {\n                /* Since not all AT versions support CIPSERVERMAXCONN command, ignore result */\n                SET_NEW_CMD(LWESP_CMD_TCPIP_CIPSERVER);\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSERVER)) {\n                if (stat->is_ok) {\n                    esp.evt_server = msg->msg.tcpip_server.cb; /* Set server callback function */\n                    SET_NEW_CMD(LWESP_CMD_TCPIP_CIPSTO);\n                }\n            } else if (CMD_IS_CUR(LWESP_CMD_TCPIP_CIPSTO)) {\n                stat->is_ok = 1; /* Force to 1 */\n            }\n        }\n        if (n_cmd == LWESP_CMD_IDLE) { /* Do we still have execution? */\n            esp.evt.evt.server.res = stat->is_ok ? lwespOK : lwespERR;\n            esp.evt.evt.server.en = msg->msg.tcpip_server.en;\n            esp.evt.evt.server.port = msg->msg.tcpip_server.port;\n            lwespi_send_cb(LWESP_EVT_SERVER); /* Send to upper layer */\n        }\n    }\n\n    /* Check and start a new command */\n    if (n_cmd != LWESP_CMD_IDLE) {\n        lwespr_t res;\n        msg->cmd = n_cmd;\n        if ((res = msg->fn(msg)) == lwespOK) {\n            return lwespCONT;\n        } else {\n            stat->is_ok = 0;\n            stat->is_error = 1;\n            return res;\n        }\n    } else {\n        msg->cmd = LWESP_CMD_IDLE;\n    }\n    return stat->is_ok || stat->is_ready ? lwespOK : (msg->res_err_code != lwespOK ? msg->res_err_code : lwespERR);\n}\n\n/**\n * \\brief           Function to initialize every AT command\n * \\note            Never call this function directly. Set as initialization function for command and use `msg->fn(msg)`\n * \\param[in]       msg: Pointer to \\ref lwesp_msg_t with data\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwespi_initiate_cmd(lwesp_msg_t* msg) {\n    switch (CMD_GET_CUR()) {    /* Check current message we want to send over AT */\n        case LWESP_CMD_RESET: { /* Reset MCU with AT commands */\n            /* Try hardware reset first */\n            if (esp.ll.reset_fn != NULL && esp.ll.reset_fn(1)) {\n\n                /* Set baudrate to default one */\n                esp.ll.uart.baudrate = LWESP_CFG_AT_PORT_BAUDRATE;\n                lwesp_ll_init(&esp.ll); /* Set new baudrate */\n\n                lwesp_delay(10);    /* Wait some time */\n                esp.ll.reset_fn(0); /* Release reset */\n            } else {\n                AT_PORT_SEND_BEGIN_AT();\n                AT_PORT_SEND_CONST_STR(\"+RST\");\n                AT_PORT_SEND_END_AT();\n                /* Do not modify baudrate yet as we need \"OK\" or \"ERROR\" response first */\n            }\n            break;\n        }\n        case LWESP_CMD_RESTORE: { /* Reset MCU with AT commands */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+RESTORE\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_ATE0: { /* Disable AT echo mode */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"E0\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_ATE1: { /* Enable AT echo mode */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"E1\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_GMR: { /* Get AT version */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+GMR\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_RFPOWER: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+RFPOWER=40\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#if LWESP_CFG_FLASH\n        case LWESP_CMD_SYSFLASH_GET: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+SYSFLASH?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_SYSFLASH_ERASE: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+SYSFLASH=0\"); /* Erase operation */\n            if (msg->msg.flash_erase.partition < LWESP_FLASH_PARTITION_END) {\n                lwespi_send_string(flash_partitions[(size_t)msg->msg.flash_erase.partition], 0, 1, 1);\n            } else {\n                LWESP_DEBUGF(LWESP_CFG_DBG_ASSERT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                             \"[SYS FLASH] Unsupported partition!\\r\\n\");\n                return lwespERR; /* Hard error! */\n            }\n            if (msg->msg.flash_erase.offset > 0 || msg->msg.flash_erase.length > 0) {\n                lwespi_send_number(LWESP_U32(msg->msg.flash_erase.offset), 0, 1);\n                if (msg->msg.flash_erase.length > 0) {\n                    lwespi_send_number(LWESP_U32(msg->msg.flash_erase.length), 0, 1);\n                }\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_SYSFLASH_WRITE: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+SYSFLASH=1\"); /* Write operation */\n            if (msg->msg.flash_write.partition < LWESP_FLASH_PARTITION_END) {\n                lwespi_send_string(flash_partitions[(size_t)msg->msg.flash_write.partition], 0, 1, 1);\n            } else {\n                LWESP_DEBUGF(LWESP_CFG_DBG_ASSERT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                             \"[SYS FLASH] Unsupported partition!\\r\\n\");\n                return lwespERR; /* Hard error! */\n            }\n            lwespi_send_number(LWESP_U32(msg->msg.flash_write.offset), 0, 1);\n            lwespi_send_number(LWESP_U32(msg->msg.flash_write.length), 0, 1);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_SYSMFG_GET: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+SYSMFG?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_SYSMFG_WRITE: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+SYSMFG=2\"); /* Write operation */\n            if (msg->msg.mfg_write.namespace < LWESP_MFG_NAMESPACE_END) {\n                lwespi_send_string(mfg_namespaces[(size_t)msg->msg.mfg_write.namespace], 0, 1, 1);\n            } else {\n                LWESP_DEBUGF(LWESP_CFG_DBG_ASSERT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                             \"[SYS MFG] Unsupported namespace!\\r\\n\");\n                return lwespERR; /* Hard error! */\n            }\n            lwespi_send_string(msg->msg.mfg_write.key, 0, 1, 1);\n            lwespi_send_number(LWESP_U32(msg->msg.mfg_write.valtype), 0, 1);\n            if (LWESP_MFG_VALTYPE_IS_PRIM(msg->msg.mfg_write.valtype)) {\n                switch (msg->msg.mfg_write.valtype) {\n                    case LWESP_MFG_VALTYPE_U8:\n                        lwespi_send_number(LWESP_U32(msg->msg.mfg_write.data_prim.u8), 0, 1);\n                        break;\n                    case LWESP_MFG_VALTYPE_I8:\n                        lwespi_send_number(LWESP_U32(msg->msg.mfg_write.data_prim.i8), 0, 1);\n                        break;\n                    case LWESP_MFG_VALTYPE_U16:\n                        lwespi_send_number(LWESP_U32(msg->msg.mfg_write.data_prim.u16), 0, 1);\n                        break;\n                    case LWESP_MFG_VALTYPE_I16:\n                        lwespi_send_number(LWESP_U32(msg->msg.mfg_write.data_prim.i16), 0, 1);\n                        break;\n                    case LWESP_MFG_VALTYPE_U32:\n                        lwespi_send_number(LWESP_U32(msg->msg.mfg_write.data_prim.u32), 0, 1);\n                        break;\n                    case LWESP_MFG_VALTYPE_I32:\n                        lwespi_send_number(LWESP_U32(msg->msg.mfg_write.data_prim.i32), 0, 1);\n                        break;\n                    default:\n                        LWESP_DEBUGF(LWESP_CFG_DBG_ASSERT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                                     \"[SYS MFG] Unsupported primitive value type!\\r\\n\");\n                }\n            } else {\n                /* Send length, data is sent later */\n                lwespi_send_number(LWESP_U32(msg->msg.mfg_write.length), 0, 1);\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_SYSMFG_READ: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+SYSMFG=1\"); /* Read operation */\n            if (msg->msg.mfg_read.namespace < LWESP_MFG_NAMESPACE_END) {\n                lwespi_send_string(mfg_namespaces[(size_t)msg->msg.mfg_read.namespace], 0, 1, 1);\n            } else {\n                LWESP_DEBUGF(LWESP_CFG_DBG_ASSERT | LWESP_DBG_LVL_SEVERE | LWESP_DBG_TYPE_TRACE,\n                             \"[SYS MFG] Unsupported namespace!\\r\\n\");\n                return lwespERR; /* Hard error! */\n            }\n            lwespi_send_string(msg->msg.mfg_read.key, 1, 1, 1);\n            lwespi_send_number(msg->msg.mfg_read.offset, 0, 1);\n            lwespi_send_number(msg->msg.mfg_read.btr, 0, 1);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif\n#if LWESP_CFG_LIST_CMD\n        case LWESP_CMD_CMD: { /* Get CMD list */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CMD?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif                           /* LWESP_CFG_LIST_CMD */\n        case LWESP_CMD_SYSMSG: { /* Enable system messages */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+SYSMSG=7\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_SYSLOG: { /* Enable system error logs */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+SYSLOG=1\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_UART: { /* Change UART parameters for AT port */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+UART_CUR=\");\n            lwespi_send_number(LWESP_U32(msg->msg.uart.baudrate), 0, 0);\n            AT_PORT_SEND_CONST_STR(\",8,1,0,0\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWLAPOPT: { /* Set visible data on CWLAP command */\n            /*\n             * Ignore remaining parameters, use default value,\n             * that provides maximal result\n             */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWLAPOPT=1,0x7FF\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n\n        /* WiFi related commands */\n#if LWESP_CFG_IPV6\n        case LWESP_CMD_WIFI_IPV6: { /* Enable IPv6 */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPV6=1\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_IPV6 */\n#if LWESP_CFG_MODE_STATION\n        case LWESP_CMD_WIFI_CWJAP: { /* Try to join to access point */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWJAP=\");\n            lwespi_send_string(msg->msg.sta_join.name, 1, 1, 0);\n            lwespi_send_string(msg->msg.sta_join.pass, 1, 1, 1);\n            if (msg->msg.sta_join.mac != NULL) {\n                lwespi_send_mac(msg->msg.sta_join.mac, 1, 1);\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWRECONNCFG: { /* Set reconnect interval */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWRECONNCFG=\");\n            lwespi_send_number(msg->msg.sta_reconn_set.interval, 0, 0);\n            lwespi_send_number(msg->msg.sta_reconn_set.rep_cnt, 0, 1);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWJAP_GET: { /* Get the info of the connected access point */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWJAP?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWQAP: { /* Quit from access point */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWQAP\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWLAP: { /* List access points */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWLAP\");\n            if (msg->msg.ap_list.ssid != NULL) { /* Do we want to filter by SSID? */\n                AT_PORT_SEND_CONST_STR(\"=\");\n                lwespi_send_string(msg->msg.ap_list.ssid, 1, 1, 0);\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWAUTOCONN: { /* Set autoconnect feature */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWAUTOCONN=\");\n            lwespi_send_number(LWESP_U32(!!msg->msg.sta_autojoin.en), 0, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIUPDATE: { /* Update ESP software remotely */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIUPDATE\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif                                /* LWESP_CFG_MODE_STATION */\n        case LWESP_CMD_WIFI_CWMODE: { /* Set WIFI mode */\n            lwesp_mode_t m;\n\n            if (!CMD_IS_DEF(LWESP_CMD_WIFI_CWMODE)) { /* Is this command part of reset sequence? */\n#if LWESP_CFG_MODE_STATION_ACCESS_POINT\n                m = LWESP_MODE_STA_AP; /* Set station and access point mode */\n#elif LWESP_CFG_MODE_STATION\n                m = LWESP_MODE_STA; /* Set station mode */\n#else  /* LWESP_CFG_MODE_STATION */\n                m = LWESP_MODE_AP; /* Set access point mode */\n#endif /* !LWESP_CFG_MODE_STATION_ACCESS_POINT */\n            } else {\n                /* Use user setup */\n                m = msg->msg.wifi_mode.mode;\n            }\n\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWMODE=\");\n            lwespi_send_number(LWESP_U32(m), 0, 0);\n            lwespi_send_number(1, 0, 1);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWMODE_GET: { /* Get WIFI mode */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWMODE?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#if LWESP_CFG_MODE_STATION\n        case LWESP_CMD_WIFI_CIPSTA_GET: /* Get station IP address */\n#endif                                  /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n        case LWESP_CMD_WIFI_CIPAP_GET: /* Get access point IP address */\n#endif                                 /* LWESP_CFG_MODE_ACCESS_POINT */\n        {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIP\");\n#if LWESP_CFG_MODE_STATION\n            if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTA_GET)) {\n                AT_PORT_SEND_CONST_STR(\"STA\");\n            }\n#endif /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n            if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPAP_GET)) {\n                AT_PORT_SEND_CONST_STR(\"AP\");\n            }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n            AT_PORT_SEND_CONST_STR(\"?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#if LWESP_CFG_MODE_STATION\n        case LWESP_CMD_WIFI_CIPSTAMAC_GET: /* Get station MAC address */\n#endif                                     /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n        case LWESP_CMD_WIFI_CIPAPMAC_GET: /* Get access point MAC address */\n#endif                                    /* LWESP_CFG_MODE_ACCESS_POINT */\n        {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIP\");\n#if LWESP_CFG_MODE_STATION\n            if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTAMAC_GET)) {\n                AT_PORT_SEND_CONST_STR(\"STA\");\n            }\n#endif /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n            if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPAPMAC_GET)) {\n                AT_PORT_SEND_CONST_STR(\"AP\");\n            }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n            AT_PORT_SEND_CONST_STR(\"MAC?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#if LWESP_CFG_MODE_STATION\n        case LWESP_CMD_WIFI_CIPSTA_SET: /* Set station IP address */\n#endif                                  /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n        case LWESP_CMD_WIFI_CIPAP_SET: /* Set access point IP address */\n#endif                                 /* LWESP_CFG_MODE_ACCESS_POINT */\n        {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIP\");\n#if LWESP_CFG_MODE_STATION\n            if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTA_SET)) {\n                AT_PORT_SEND_CONST_STR(\"STA\");\n            }\n#endif /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n            if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPAP_SET)) {\n                AT_PORT_SEND_CONST_STR(\"AP\");\n            }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n            AT_PORT_SEND_CONST_STR(\"=\");\n            lwespi_send_ip(&msg->msg.sta_ap_setip.ip, 1, 0);            /* Send IP address */\n            if (lwesp_ip_is_valid(&msg->msg.sta_ap_setip.gw) > 0) {     /* Is gateway set? */\n                lwespi_send_ip(&msg->msg.sta_ap_setip.gw, 1, 1);        /* Send gateway address */\n                if (lwesp_ip_is_valid(&msg->msg.sta_ap_setip.nm) > 0) { /* Is netmask set ? */\n                    lwespi_send_ip(&msg->msg.sta_ap_setip.nm, 1, 1);    /* Send netmask address */\n                }\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#if LWESP_CFG_MODE_STATION\n        case LWESP_CMD_WIFI_CIPSTAMAC_SET: /* Set station MAC address */\n#endif                                     /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n        case LWESP_CMD_WIFI_CIPAPMAC_SET: /* Set access point MAC address */\n#endif                                    /* LWESP_CFG_MODE_ACCESS_POINT */\n        {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIP\");\n#if LWESP_CFG_MODE_STATION\n            if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPSTAMAC_SET)) {\n                AT_PORT_SEND_CONST_STR(\"STA\");\n            }\n#endif /* LWESP_CFG_MODE_STATION */\n#if LWESP_CFG_MODE_ACCESS_POINT\n            if (CMD_IS_CUR(LWESP_CMD_WIFI_CIPAPMAC_SET)) {\n                AT_PORT_SEND_CONST_STR(\"AP\");\n            }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n            AT_PORT_SEND_CONST_STR(\"MAC=\");\n            lwespi_send_mac(&msg->msg.sta_ap_setmac.mac, 1, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWDHCP_GET: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWDHCP?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWDHCP_SET: {\n            uint32_t num = 0;\n\n            /* Configure DHCP setup */\n            num |= (msg->msg.wifi_cwdhcp.sta > 0 ? 0x01 : 0x00);\n            num |= (msg->msg.wifi_cwdhcp.ap > 0 ? 0x02 : 0x00);\n\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWDHCP=\");\n            lwespi_send_number(LWESP_U32(msg->msg.wifi_cwdhcp.en > 0), 0, 0);\n            lwespi_send_number(num, 0, 1);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#if LWESP_CFG_MODE_ACCESS_POINT\n        case LWESP_CMD_WIFI_CWSAP_SET: { /* Set soft-access point parameters */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWSAP=\");\n            lwespi_send_string(msg->msg.ap_conf.ssid, 1, 1, 0);\n            lwespi_send_string(msg->msg.ap_conf.pwd, 1, 1, 1);\n            lwespi_send_number(LWESP_U32(msg->msg.ap_conf.ch), 0, 1);\n            lwespi_send_number(LWESP_U32(msg->msg.ap_conf.ecn), 0, 1);\n            lwespi_send_number(LWESP_U32(msg->msg.ap_conf.max_sta), 0, 1);\n            lwespi_send_number(LWESP_U32(!!msg->msg.ap_conf.hid), 0, 1);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWSAP_GET: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWSAP?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWLIF: { /* List stations connected on soft-access point */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWLIF\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWQIF: { /* Disconnect station from soft-access point */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWQIF\");\n            if (msg->msg.ap_disconn_sta.use_mac) {\n                AT_PORT_SEND_CONST_STR(\"=\");\n                lwespi_send_mac(&msg->msg.ap_disconn_sta.mac, 1, 0);\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n#if LWESP_CFG_WPS\n        case LWESP_CMD_WIFI_WPS: { /* Enable WPS function */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+WPS=\");\n            lwespi_send_number(LWESP_U32(!!msg->msg.wps_cfg.en), 0, 0);\n            if (msg->msg.wps_cfg.en) {\n                lwespi_send_number(LWESP_U32(msg->msg.wps_cfg.min_ecn), 0, 1);\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_WPS */\n#if LWESP_CFG_HOSTNAME\n        case LWESP_CMD_WIFI_CWHOSTNAME_SET: { /* List stations connected on access point */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWHOSTNAME=\");\n            lwespi_send_string(msg->msg.wifi_hostname.hostname_set, 1, 1, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_CWHOSTNAME_GET: { /* List stations connected on access point */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWHOSTNAME?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_HOSTNAME */\n#if LWESP_CFG_MDNS\n        case LWESP_CMD_WIFI_MDNS: { /* Set mDNS parameters */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+MDNS=\");\n            if (msg->msg.mdns.en) { /* Send the rest only in case mDNS should be enabled */\n                AT_PORT_SEND_CONST_STR(\"1\");\n                lwespi_send_string(msg->msg.mdns.host, 0, 1, 1);\n                lwespi_send_string(msg->msg.mdns.server, 0, 1, 1);\n                lwespi_send_port(msg->msg.mdns.port, 0, 1);\n            } else {\n                AT_PORT_SEND_CONST_STR(\"0\");\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_MDNS */\n\n        /* TCP/IP related commands */\n        case LWESP_CMD_TCPIP_CIPSERVER: { /* Enable or disable server */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSERVER=\");\n            if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSERVER) && msg->msg.tcpip_server.en) {\n                AT_PORT_SEND_CONST_STR(\"1\");\n                lwespi_send_port(msg->msg.tcpip_server.port, 0, 1);\n            } else { /* Disable server */\n                AT_PORT_SEND_CONST_STR(\"0\");\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSERVERMAXCONN: { /* Maximal number of connections */\n            uint16_t max_conn;\n            if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSERVER)) {\n                max_conn = LWESP_MIN(msg->msg.tcpip_server.max_conn, LWESP_CFG_MAX_CONNS);\n            } else {\n                max_conn = LWESP_CFG_MAX_CONNS;\n            }\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSERVERMAXCONN=\");\n            lwespi_send_number(LWESP_U32(max_conn), 0, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSTO: { /* Set server connection timeout */\n            uint16_t timeout;\n            if (CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSERVER)) {\n                timeout = msg->msg.tcpip_server.timeout;\n            } else {\n                timeout = 100;\n            }\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSTO=\");\n            lwespi_send_number(LWESP_U32(timeout), 0, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSTART: {\n            const char* conn_type_str;\n#if LWESP_CFG_CONN_ALLOW_START_STATION_NO_IP\n            /* \n             * Do not check IP status if starting a connection is allowed\n             * without being connected to access point.\n             * This allows ESP to act as a access point and get connected another station to it.\n             */\n            if (!lwesp_sta_has_ip()) {\n                return lwespERRNOIP;\n            }\n#endif /* LWESP_CFG_CONN_ALLOW_START_STATION_NO_IP */\n\n            if (msg->msg.conn_start.type == LWESP_CONN_TYPE_TCP) {\n                conn_type_str = \"TCP\";\n            } else if (msg->msg.conn_start.type == LWESP_CONN_TYPE_UDP) {\n                conn_type_str = \"UDP\";\n            } else if (msg->msg.conn_start.type == LWESP_CONN_TYPE_SSL) {\n                conn_type_str = \"SSL\";\n#if LWESP_CFG_IPV6\n            } else if (msg->msg.conn_start.type == LWESP_CONN_TYPE_TCPV6) {\n                conn_type_str = \"TCPV6\";\n            } else if (msg->msg.conn_start.type == LWESP_CONN_TYPE_UDPV6) {\n                conn_type_str = \"UDPV6\";\n            } else if (msg->msg.conn_start.type == LWESP_CONN_TYPE_SSLV6) {\n                conn_type_str = \"SSLV6\";\n#endif /* LWESP_CFG_IPV6 */\n            } else {\n                return lwespERRPAR;\n            }\n\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSTARTEX=\");\n            lwespi_send_string(conn_type_str, 0, 1, 0);\n            lwespi_send_string(msg->msg.conn_start.remote_host, 0, 1, 1);\n            lwespi_send_port(msg->msg.conn_start.remote_port, 0, 1);\n\n            /* Connection-type specific features */\n            if (!CONN_IS_UDP_V4_OR_V6(msg->msg.conn_start.type)) {\n                /* TCP or SSL */\n                lwespi_send_number(LWESP_U32(msg->msg.conn_start.tcp_ssl_keep_alive), 0, 1);\n            } else {\n                /* UDP */\n                if (msg->msg.conn_start.udp_local_port > 0) {\n                    lwespi_send_port(msg->msg.conn_start.udp_local_port, 0, 1);\n                } else {\n                    AT_PORT_SEND_CONST_STR(\",\");\n                }\n                lwespi_send_number(msg->msg.conn_start.udp_mode, 0, 1);\n            }\n            if (msg->msg.conn_start.local_ip != NULL) {\n                lwespi_send_string(msg->msg.conn_start.local_ip, 0, 1, 1);\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPCLOSE: { /* Close the connection */\n            lwesp_conn_p c = msg->msg.conn_close.conn;\n            if (c != NULL &&\n                /*\n                 * Is connection already closed or command\n                 * for this connection is not valid anymore?\n                 */\n                (!lwesp_conn_is_active(c) || c->val_id != msg->msg.conn_close.val_id)) {\n                return lwespERR;\n            }\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPCLOSE=\");\n            lwespi_send_number(\n                LWESP_U32(msg->msg.conn_close.conn ? msg->msg.conn_close.conn->num : LWESP_CFG_MAX_CONNS), 0, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSEND: {              /* Send data to connection */\n            return lwespi_tcpip_process_send_data(); /* Process send data */\n        }\n        case LWESP_CMD_TCPIP_CIPSTATUS: {                 /* Get status of device and all connections */\n            esp.m.active_conns_last = esp.m.active_conns; /* Save as last status */\n            esp.m.active_conns = 0;                       /* Reset new status before parsing starts */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSTATUS\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSTATE: {                  /* Get status of all connections */\n            esp.m.active_conns_last = esp.m.active_conns; /* Save as last status */\n            esp.m.active_conns = 0;                       /* Reset new status before parsing starts */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSTATE?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPDINFO: { /* Set info data on +IPD command */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPDINFO=1\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPMUX: { /* Set multiple connections */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPMUX=1\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSSLSIZE: { /* Set SSL size */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSSLSIZE=\");\n            lwespi_send_number(LWESP_U32(msg->msg.tcpip_sslsize.size), 0, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSSLCCONF: { /* Set SSL Configuration */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSSLCCONF=\");\n            lwespi_send_number(LWESP_U32(msg->msg.tcpip_ssl_cfg.link_id), 0, 0);\n            lwespi_send_number(LWESP_U32(msg->msg.tcpip_ssl_cfg.auth_mode), 0, 1);\n            lwespi_send_number(LWESP_U32(msg->msg.tcpip_ssl_cfg.pki_number), 0, 1);\n            lwespi_send_number(LWESP_U32(msg->msg.tcpip_ssl_cfg.ca_number), 0, 1);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPRECVMODE: { /* Set TCP data receive mode */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPRECVMODE=\");\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n            AT_PORT_SEND_CONST_STR(\"1\");\n#else\n            AT_PORT_SEND_CONST_STR(\"0\");\n#endif\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n        case LWESP_CMD_TCPIP_CIPRECVDATA: { /* Manually read data */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPRECVDATA=\");\n            lwespi_send_number(LWESP_U32(msg->msg.conn_recv.conn->num), 0, 0);\n            lwespi_send_number(LWESP_U32(msg->msg.conn_recv.len), 0, 1);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPRECVLEN: { /* Get length to read */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPRECVLEN?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n#if LWESP_CFG_DNS\n        case LWESP_CMD_TCPIP_CIPDOMAIN: { /* DNS function */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPDOMAIN=\");\n            lwespi_send_string(msg->msg.dns_getbyhostname.host, 1, 1, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPDNS_SET: { /* DNS set config */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPDNS=\");\n            lwespi_send_number(LWESP_U32(!!msg->msg.dns_setconfig.en), 0, 0);\n            if (msg->msg.dns_setconfig.en) {\n                if (msg->msg.dns_setconfig.s1 != NULL) {\n                    lwespi_send_string(msg->msg.dns_setconfig.s1, 0, 1, 1);\n                }\n                if (msg->msg.dns_setconfig.s2 != NULL) {\n                    lwespi_send_string(msg->msg.dns_setconfig.s2, 0, 1, 1);\n                }\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPDNS_GET: { /* DNS get config */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPDNS?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_DNS */\n#if LWESP_CFG_PING\n        case LWESP_CMD_TCPIP_PING: { /* Ping hostname or IP address */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+PING=\");\n            lwespi_send_string(msg->msg.tcpip_ping.host, 1, 1, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_PING */\n#if LWESP_CFG_SNTP\n        case LWESP_CMD_TCPIP_CIPSNTPCFG: { /* Configure SNTP */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSNTPCFG=\");\n            lwespi_send_number(LWESP_U32(msg->msg.tcpip_sntp_cfg.en > 0 ? 1 : 0), 0, 0);\n            lwespi_send_signed_number(LWESP_I32(msg->msg.tcpip_sntp_cfg.tz), 0, 1);\n            if (msg->msg.tcpip_sntp_cfg.h1 != NULL && strlen(msg->msg.tcpip_sntp_cfg.h1)) {\n                lwespi_send_string(msg->msg.tcpip_sntp_cfg.h1, 0, 1, 1);\n            }\n            if (msg->msg.tcpip_sntp_cfg.h2 != NULL && strlen(msg->msg.tcpip_sntp_cfg.h2)) {\n                lwespi_send_string(msg->msg.tcpip_sntp_cfg.h2, 0, 1, 1);\n            }\n            if (msg->msg.tcpip_sntp_cfg.h3 != NULL && strlen(msg->msg.tcpip_sntp_cfg.h3)) {\n                lwespi_send_string(msg->msg.tcpip_sntp_cfg.h3, 0, 1, 1);\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSNTPCFG_GET: { /* Get SNTP config */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSNTPCFG?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSNTPTIME: { /* Query time over SNTP */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSNTPTIME?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSNTPINTV: { /* Set SNTP sync interval */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSNTPINTV=\");\n            lwespi_send_number(LWESP_U32(msg->msg.tcpip_sntp_intv.interval), 0, 0);\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_TCPIP_CIPSNTPINTV_GET: { /* Query SNTP sync interval */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CIPSNTPINTV?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_SNTP */\n#if LWESP_CFG_SMART\n        case LWESP_CMD_WIFI_SMART_START: { /* Start smart config */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWSTARTSMART\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n        case LWESP_CMD_WIFI_SMART_STOP: { /* Stop smart config */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+CWSTOPSMART\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_SMART */\n#if LWESP_CFG_WEBSERVER\n        case LWESP_CMD_WEBSERVER: { /* Start Web Server */\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+WEBSERVER=\");\n            if (msg->msg.web_server.en) {\n                AT_PORT_SEND_CONST_STR(\"1\");\n                lwespi_send_port(msg->msg.web_server.port, 0, 1);\n                lwespi_send_number(msg->msg.web_server.timeout, 0, 1);\n            } else { /* Stop Web server */\n                AT_PORT_SEND_CONST_STR(\"0\");\n            }\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_WEBSERVER */\n#if LWESP_CFG_ESP32\n        case LWESP_CMD_BLEINIT_GET: {\n            AT_PORT_SEND_BEGIN_AT();\n            AT_PORT_SEND_CONST_STR(\"+BLEINIT?\");\n            AT_PORT_SEND_END_AT();\n            break;\n        }\n#endif /* LWESP_CFG_ESP32 */\n\n        default: return lwespERRCMDNOTSUPPORTED; /* Invalid command */\n    }\n    lwesp_delay(10);\n    return lwespOK; /* Valid command */\n}\n\n/**\n * \\brief           Checks if connection pointer has valid address\n * \\param[in]       conn: Address to check if valid connection ptr\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_is_valid_conn_ptr(lwesp_conn_p conn) {\n    for (size_t i = 0; i < LWESP_ARRAYSIZE(esp.m.conns); ++i) {\n        if (conn == &esp.m.conns[i]) {\n            return 1;\n        }\n    }\n    return 0;\n}\n\n/**\n * \\brief           Send message from API function to producer queue for further processing\n * \\param[in]       msg: New message to process\n * \\param[in]       process_fn: callback function used to process message\n * \\param[in]       max_block_time: Maximal time command can block in units of milliseconds\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwespi_send_msg_to_producer_mbox(lwesp_msg_t* msg, lwespr_t (*process_fn)(lwesp_msg_t*), uint32_t max_block_time) {\n    lwespr_t res = msg->res = msg->res_err_code = lwespOK;\n\n    lwesp_core_lock();\n\n    /*\n     * If locked more than 1 time, means we were called from callback or internally.\n     * It is not allowed to call command in blocking mode from stack itself (would end up in dead-lock)\n     */\n    if (esp.locked_cnt > 1 && msg->is_blocking) {\n        res = lwespERRBLOCKING;             /* Blocking mode not allowed */\n    } else if (!esp.status.f.dev_present) { /* Check device present */\n        res = lwespERRNODEVICE;             /* No device connected */\n    }\n    lwesp_core_unlock();\n    if (res != lwespOK) {\n        LWESP_MSG_VAR_FREE(msg);\n        return res;\n    }\n\n    if (msg->is_blocking) {                        /* In case message is blocking */\n        if (!lwesp_sys_sem_create(&msg->sem, 0)) { /* Create semaphore and lock it immediately */\n            LWESP_MSG_VAR_FREE(msg);               /* Release memory and return */\n            return lwespERRMEM;\n        }\n    }\n    if (!msg->cmd) {             /* Set start command if not set by user */\n        msg->cmd = msg->cmd_def; /* Set it as default */\n    }\n    msg->block_time = max_block_time; /* Set blocking status if necessary */\n    msg->fn = process_fn;             /* Save processing function to be called as callback */\n    if (msg->is_blocking) {\n        lwesp_sys_mbox_put(&esp.mbox_producer, msg); /* Write message to producer queue and wait forever */\n    } else {\n        if (!lwesp_sys_mbox_putnow(&esp.mbox_producer, msg)) { /* Write message to producer queue immediately */\n            LWESP_MSG_VAR_FREE(msg);                           /* Release message */\n            return lwespERRMEM;\n        }\n    }\n    if (res == lwespOK && msg->is_blocking) { /* In case we have blocking request */\n        uint32_t time;\n        time = lwesp_sys_sem_wait(&msg->sem, 0); /* Wait forever for semaphore */\n        if (time == LWESP_SYS_TIMEOUT) {         /* If semaphore was not accessed within given time */\n            res = lwespTIMEOUT;                  /* Semaphore not released in time */\n        } else {\n            res = msg->res; /* Set response status from message response */\n        }\n        LWESP_MSG_VAR_FREE(msg); /* Release message */\n    }\n    return res;\n}\n\n/**\n * \\brief           Process events in case of timeout on command or invalid message (if device is not present)\n *\n *                  Function is called from processing thread:\n *\n *                      - On command timeout error\n *                      - If command was sent to queue and before processed, device present status changed\n *\n * \\param[in]       msg: Current message\n * \\param[in]       err: Error message to send\n */\nvoid\nlwespi_process_events_for_timeout_or_error(lwesp_msg_t* msg, lwespr_t err) {\n    switch (msg->cmd_def) {\n        case LWESP_CMD_RESET: {\n            /* Error on reset */\n            RESET_SEND_EVT(msg, err);\n            break;\n        }\n\n        case LWESP_CMD_RESTORE: {\n            /* Error on restore */\n            RESTORE_SEND_EVT(msg, err);\n            break;\n        }\n\n        case LWESP_CMD_TCPIP_CIPSTART: {\n            /* Start connection error */\n            lwespi_send_conn_error_cb(msg, err);\n            break;\n        }\n\n        case LWESP_CMD_TCPIP_CIPSEND: {\n            /* Send data error */\n            CONN_SEND_DATA_SEND_EVT(msg, err);\n            break;\n        }\n\n#if LWESP_CFG_MODE_STATION\n        case LWESP_CMD_WIFI_CWJAP: {\n            /* Join access point error */\n            STA_JOIN_AP_SEND_EVT(msg, err);\n            break;\n        }\n\n        case LWESP_CMD_WIFI_CWLAP: {\n            /* List failed event */\n            STA_LIST_AP_SEND_EVT(msg, err);\n            break;\n        }\n\n        case LWESP_CMD_WIFI_CWJAP_GET: {\n            /* Info failed event */\n            STA_INFO_AP_SEND_EVT(msg, err);\n            break;\n        }\n#endif /* LWESP_CFG_MODE_STATION */\n\n#if LWESP_CFG_PING\n        case LWESP_CMD_TCPIP_PING: {\n            /* Ping error */\n            PING_SEND_EVT(msg, err);\n            break;\n        }\n#endif /* LWESP_CFG_PING */\n\n#if LWESP_CFG_DNS\n        case LWESP_CMD_TCPIP_CIPDOMAIN: {\n            /* DNS error */\n            CIPDOMAIN_SEND_EVT(msg, err);\n            break;\n        }\n#endif /* LWESP_CFG_DNS */\n\n#if LWESP_CFG_SNTP\n        case LWESP_CMD_TCPIP_CIPSNTPTIME: {\n            /* SNTP error */\n            SNTP_TIME_SEND_EVT(msg, err);\n            break;\n        }\n#endif /* LWESP_CFG_SNTP */\n\n        default: break;\n    }\n}\n\n/**\n * \\brief           Get internal ESP device descriptor information\n * \n * \\param           device: Required device ID\n * \\return          Pointer to device descriptor, or NULL if not device available \n */\nconst lwesp_esp_device_desc_t*\nlwespi_get_device_desc_for_device(lwesp_device_t device) {\n    for (size_t i = 0; i < sizeof(esp_device_descriptors) / sizeof(esp_device_descriptors[0]); ++i) {\n        if (esp_device_descriptors[i].device == device) {\n            return &esp_device_descriptors[i];\n        }\n    }\n    return NULL;\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_mdns.c",
    "content": "/**\n * \\file            lwesp_mdns.c\n * \\brief           mDNS API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_mdns.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_MDNS || __DOXYGEN__\n\n/**\n * \\brief           Configure mDNS parameters with hostname and server\n * \\param[in]       en: Status to enable `1` or disable `0` mDNS function\n * \\param[in]       host: mDNS host name\n * \\param[in]       server: mDNS server name\n * \\param[in]       port: mDNS server port number\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_mdns_set_config(uint8_t en, const char* host, const char* server, lwesp_port_t port,\n                      const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    if (en) {\n        LWESP_ASSERT(host != NULL);\n        LWESP_ASSERT(server != NULL);\n        LWESP_ASSERT(port > 0);\n    }\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_MDNS;\n    LWESP_MSG_VAR_REF(msg).msg.mdns.en = en;\n    LWESP_MSG_VAR_REF(msg).msg.mdns.host = host;\n    LWESP_MSG_VAR_REF(msg).msg.mdns.server = server;\n    LWESP_MSG_VAR_REF(msg).msg.mdns.port = port;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n#endif /* LWESP_CFG_MDNS || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_mem.c",
    "content": "/**\n * \\file            lwesp_mem.c\n * \\brief           Memory manager\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include <limits.h>\n#include \"lwesp/lwesp_mem.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if !LWESP_CFG_MEM_CUSTOM || __DOXYGEN__\n\n#if !__DOXYGEN__\ntypedef struct mem_block {\n    struct mem_block* next; /*!< Pointer to next free block */\n    size_t size;            /*!< Size of block */\n} mem_block_t;\n#endif /* !__DOXYGEN__ */\n\n/**\n * \\brief           Memory alignment bits and absolute number\n */\n#define MEM_ALIGN_BITS           LWESP_SZ(LWESP_CFG_MEM_ALIGNMENT - 1)\n#define MEM_ALIGN_NUM            LWESP_SZ(LWESP_CFG_MEM_ALIGNMENT)\n#define MEM_ALIGN(x)             LWESP_MEM_ALIGN(x)\n\n#define MEMBLOCK_METASIZE        MEM_ALIGN(sizeof(mem_block_t))\n\n#define MEM_ALLOC_BIT            ((size_t)((size_t)1 << (sizeof(size_t) * CHAR_BIT - 1)))\n#define MEM_BLOCK_FROM_PTR(ptr)  ((mem_block_t*)(((uint8_t*)(ptr)) - MEMBLOCK_METASIZE))\n#define MEM_BLOCK_USER_SIZE(ptr) ((MEM_BLOCK_FROM_PTR(ptr)->size & ~MEM_ALLOC_BIT) - MEMBLOCK_METASIZE)\n\nstatic mem_block_t start_block;    /*!< First block data for allocations */\nstatic mem_block_t* end_block;     /*!< Pointer to last block in linked list */\nstatic size_t mem_available_bytes; /*!< Number of available bytes for allocations */\n\n/**\n * \\brief           Insert a new block to linked list of free blocks\n * \\param[in]       nb: Pointer to new block to insert with known size\n */\nstatic void\nmem_insertfreeblock(mem_block_t* nb) {\n    mem_block_t* ptr;\n    uint8_t* addr;\n\n    /* Find block position to insert new block between */\n    for (ptr = &start_block; ptr != NULL && ptr->next < nb; ptr = ptr->next) {}\n\n    /* Check hard error on wrongly used memory */\n    if (ptr == NULL) {\n        return;\n    }\n\n    /*\n     * If the new inserted block and block before create a one big block (contiguous)\n     * then try to merge them together\n     */\n    addr = (void*)ptr;\n    if ((uint8_t*)(addr + ptr->size) == (uint8_t*)nb) {\n        ptr->size += nb->size; /* Expand size of block before new inserted */\n        nb = ptr;              /* Set new block pointer to block before (expanded block) */\n    }\n\n    /* Check if new block and its size is the same address as next free block newBlock points to */\n    addr = (void*)nb;\n    if ((uint8_t*)(addr + nb->size) == (uint8_t*)ptr->next) {\n        if (ptr->next == end_block) { /* Does it points to the end? */\n            nb->next = end_block;     /* Set end block pointer */\n        } else {\n            nb->size +=\n                ptr->next\n                    ->size; /* Expand of current block for size of next free block which is right behind new block */\n            nb->next = ptr->next->next; /* Next free is pointed to the next one of previous next */\n        }\n    } else {\n        nb->next = ptr->next; /* Our next element is now from pointer next element */\n    }\n\n    /*\n     * If merge with new block and block before was not made then there\n     * is a gap between free memory before and new free memory.\n     *\n     * We have to set block before to point to next free which is new block\n     */\n    if (ptr != nb) {\n        ptr->next = nb;\n    }\n}\n\n/**\n * \\brief           Assign memory for HEAP allocations\n * \\param[in]       regions: Pointer to list of regions.\n *                  Set regions in ascending order by address\n * \\param[in]       len: Number of regions to assign\n */\nstatic uint8_t\nmem_assignmem(const lwesp_mem_region_t* regions, size_t len) {\n    uint8_t* mem_start_addr;\n    size_t mem_size;\n    mem_block_t *first_block, *prev_end_block = NULL;\n\n    if (end_block != NULL) { /* Regions already defined */\n        return 0;\n    }\n\n    /* Check if region address are linear and rising */\n    mem_start_addr = (uint8_t*)0;\n    for (size_t i = 0; i < len; ++i) {\n        if (mem_start_addr >= (uint8_t*)regions[i].start_addr) { /* Check if previous greater than current */\n            return 0;                                            /* Return as invalid and failed */\n        }\n        mem_start_addr = (uint8_t*)regions[i].start_addr; /* Save as previous address */\n    }\n\n    for (; len > 0; --len, ++regions) {\n        /* Check minimum region size */\n        mem_size = regions->size;\n        if (mem_size < (MEM_ALIGN_NUM + MEMBLOCK_METASIZE)) {\n            continue;\n        }\n        /*\n         * Get start address and check memory alignment\n         * if necessary, decrease memory region size\n         */\n        mem_start_addr = (uint8_t*)regions->start_addr;  /* Actual heap memory address */\n        if (LWESP_SZ(mem_start_addr) & MEM_ALIGN_BITS) { /* Check alignment boundary */\n            mem_start_addr += MEM_ALIGN_NUM - (LWESP_SZ(mem_start_addr) & MEM_ALIGN_BITS);\n            mem_size -= mem_start_addr - (uint8_t*)regions->start_addr;\n        }\n\n        /* Check memory size alignment if match */\n        if (mem_size & MEM_ALIGN_BITS) {\n            mem_size &= ~MEM_ALIGN_BITS; /* Clear lower bits of memory size only */\n        }\n\n        /*\n         * start_block is fixed variable for start list of free blocks\n         *\n         * Set free blocks linked list on initialized\n         *\n         * Set Start block only if end block is not yet defined = first run\n         */\n        if (end_block == NULL) {\n            start_block.next = (mem_block_t*)mem_start_addr;\n            start_block.size = 0;\n        }\n\n        prev_end_block = end_block; /* Save previous end block to set next block later */\n\n        /*\n         * Set pointer to end of free memory - block region memory\n         * Calculate new end block in region\n         */\n        end_block = (mem_block_t*)((uint8_t*)mem_start_addr + mem_size - MEMBLOCK_METASIZE);\n        end_block->next = NULL; /* No more free blocks after end is reached */\n        end_block->size = 0;    /* Empty block */\n\n        /*\n         * Initialize start of region memory\n         * Create first block in region\n         */\n        first_block = (mem_block_t*)mem_start_addr;\n        first_block->size = mem_size - MEMBLOCK_METASIZE; /* Exclude end block in chain */\n        first_block->next = end_block;                    /* Last block is next free in chain */\n\n        /*\n         * If we have previous end block\n         * End block of previous region\n         *\n         * Set previous end block to start of next region\n         */\n        if (prev_end_block != NULL) {\n            prev_end_block->next = first_block;\n        }\n\n        /* Set number of free bytes available to allocate in region */\n        mem_available_bytes += first_block->size;\n    }\n\n    return 1; /* Regions set as expected */\n}\n\n/**\n * \\brief           Allocate memory of specific size\n * \\param[in]       size: Number of bytes to allocate\n * \\return          Memory address on success, `NULL` otherwise\n */\nstatic void*\nmem_alloc(size_t size) {\n    mem_block_t *prev, *curr, *next;\n    void* retval = NULL;\n\n    if (end_block == NULL) { /* If end block is not yet defined */\n        return NULL;         /* Invalid, not initialized */\n    }\n\n    if (size == 0 || size >= MEM_ALLOC_BIT) {\n        return NULL;\n    }\n\n    size = MEM_ALIGN(size) + MEMBLOCK_METASIZE; /* Increase size for metadata */\n    if (size > mem_available_bytes) {           /* Check if we have enough memory available */\n        return 0;\n    }\n\n    /*\n     * Try to find sufficient block for data\n     * Go through free blocks until enough memory is found\n     * or end block is reached (no next free block)\n     */\n    prev = &start_block; /* Set first first block as previous */\n    curr = prev->next;   /* Set next block as current */\n    while ((curr->size < size) && (curr->next != NULL)) {\n        prev = curr;\n        curr = curr->next;\n    }\n\n    /*\n     * Possible improvements\n     * Try to find smallest available block for desired amount of memory\n     *\n     * Feature may be very risky later because of fragmentation\n     */\n    if (curr != end_block) { /* We found empty block of enough memory available */\n        retval = (void*)((uint8_t*)prev->next + MEMBLOCK_METASIZE); /* Set return value */\n        prev->next = curr->next; /* Since block is now allocated, remove it from free chain */\n\n        /*\n         * If found free block is much bigger than required,\n         * then split big block by 2 blocks (one used, second available)\n         * There should be available memory for at least 2 metadata block size = 8 bytes of useful memory\n         */\n        if ((curr->size - size)\n            > (2\n               * MEMBLOCK_METASIZE)) { /* There is more available memory then required = split memory to one free block */\n            next = (mem_block_t*)(((uint8_t*)curr) + size); /* Create next memory block which is still free */\n            next->size = curr->size - size;                 /* Set new block size for remaining of before and used */\n            curr->size = size;                              /* Set block size for used block */\n\n            /*\n             * Add virtual block to list of free blocks.\n             * It is placed directly after currently allocated memory\n             */\n            mem_insertfreeblock(next); /* Insert free memory block to list of free memory blocks (linked list chain) */\n        }\n        curr->size |= MEM_ALLOC_BIT; /* Set allocated bit = memory is allocated */\n        curr->next = NULL;           /* Clear next free block pointer as there is no one */\n\n        mem_available_bytes -= size; /* Decrease available memory */\n    } else {\n        /* Allocation failed, no free blocks of required size */\n    }\n    return retval;\n}\n\n/**\n * \\brief           Free memory\n * \\param[in]       ptr: Pointer to memory previously returned using \\ref lwesp_mem_malloc,\n *                      \\ref lwesp_mem_calloc or \\ref lwesp_mem_realloc functions\n */\nstatic void\nmem_free(void* ptr) {\n    mem_block_t* block;\n\n    if (ptr == NULL) { /* To be in compliance with C free function */\n        return;\n    }\n\n    block = MEM_BLOCK_FROM_PTR(ptr); /* Get block data pointer from input pointer */\n\n    /*\n     * Check if block is even allocated by upper bit on size\n     * and next free block must be set to NULL in order to work properly\n     */\n    if ((block->size & MEM_ALLOC_BIT) && block->next == NULL) {\n        /*\n         * Clear allocated bit before entering back to free list\n         * List will automatically take care for fragmentation\n         */\n        block->size &= ~MEM_ALLOC_BIT;      /* Clear allocated bit */\n        mem_available_bytes += block->size; /* Increase available bytes back */\n        mem_insertfreeblock(block);         /* Insert block to list of free blocks */\n    }\n}\n\n/**\n * \\brief           Allocate memory of specific size\n * \\param[in]       num: Number of elements to allocate\n * \\param[in]       size: Size of element in units of bytes\n * \\return          Memory address on success, `NULL` otherwise\n */\nstatic void*\nmem_calloc(size_t num, size_t size) {\n    void* ptr;\n    size_t tot_len = num * size;\n\n    if ((ptr = mem_alloc(tot_len)) != NULL) { /* Try to allocate memory */\n        LWESP_MEMSET(ptr, 0x00, tot_len);     /* Reset entire memory */\n    }\n    return ptr;\n}\n\n/**\n * \\brief           Reallocate memory to specific size\n * \\note            After new memory is allocated, content of old one is copied to new memory\n * \\param[in]       ptr: Pointer to current allocated memory to resize, returned using\n *                      \\ref lwesp_mem_malloc, \\ref lwesp_mem_calloc or \\ref lwesp_mem_realloc functions\n * \\param[in]       size: Number of bytes to allocate on new memory\n * \\return          Memory address on success, `NULL` otherwise\n */\nstatic void*\nmem_realloc(void* ptr, size_t size) {\n    void* new_ptr;\n    size_t old_size;\n\n    if (ptr == NULL) {          /* If pointer is not valid */\n        return mem_alloc(size); /* Only allocate memory */\n    }\n\n    old_size = MEM_BLOCK_USER_SIZE(ptr); /* Get size of old pointer */\n    new_ptr = mem_alloc(size);           /* Try to allocate new memory block */\n    if (new_ptr != NULL) {\n        LWESP_MEMCPY(new_ptr, ptr, LWESP_MIN(size, old_size)); /* Copy old data to new array */\n        mem_free(ptr);                                         /* Free old pointer */\n    }\n    return new_ptr;\n}\n\n/**\n * \\brief           Allocate memory of specific size\n * \\param[in]       size: Number of bytes to allocate\n * \\return          Memory address on success, `NULL` otherwise\n * \\note            Function is not available when \\ref LWESP_CFG_MEM_CUSTOM is `1` and must be implemented by user\n */\nvoid*\nlwesp_mem_malloc(size_t size) {\n    void* ptr;\n    lwesp_core_lock();\n    ptr = mem_calloc(1, size); /* Allocate memory and return pointer */\n    lwesp_core_unlock();\n    LWESP_DEBUGW(LWESP_CFG_DBG_MEM | LWESP_DBG_TYPE_TRACE, ptr == NULL, \"[LWESP MEM] Allocation failed: %d bytes\\r\\n\",\n                 (int)size);\n    LWESP_DEBUGW(LWESP_CFG_DBG_MEM | LWESP_DBG_TYPE_TRACE, ptr != NULL,\n                 \"[LWESP MEM] Allocation OK: %d bytes, addr: %p\\r\\n\", (int)MEM_BLOCK_USER_SIZE(ptr), ptr);\n    return ptr;\n}\n\n/**\n * \\brief           Reallocate memory to specific size\n * \\note            After new memory is allocated, content of old one is copied to new memory\n * \\param[in]       ptr: Pointer to current allocated memory to resize, returned using \\ref lwesp_mem_malloc,\n *                      \\ref lwesp_mem_calloc or \\ref lwesp_mem_realloc functions\n * \\param[in]       size: Number of bytes to allocate on new memory\n * \\return          Memory address on success, `NULL` otherwise\n * \\note            Function is not available when \\ref LWESP_CFG_MEM_CUSTOM is `1` and must be implemented by user\n */\nvoid*\nlwesp_mem_realloc(void* ptr, size_t size) {\n    lwesp_core_lock();\n    ptr = mem_realloc(ptr, size); /* Reallocate and return pointer */\n    lwesp_core_unlock();\n    LWESP_DEBUGW(LWESP_CFG_DBG_MEM | LWESP_DBG_TYPE_TRACE, ptr == NULL, \"[LWESP MEM] Reallocation failed: %d bytes\\r\\n\",\n                 (int)size);\n    LWESP_DEBUGW(LWESP_CFG_DBG_MEM | LWESP_DBG_TYPE_TRACE, ptr != NULL,\n                 \"[LWESP MEM] Reallocation OK: %d bytes, addr: %p\\r\\n\", (int)MEM_BLOCK_USER_SIZE(ptr), ptr);\n    return ptr;\n}\n\n/**\n * \\brief           Allocate memory of specific size and set memory to zero\n * \\param[in]       num: Number of elements to allocate\n * \\param[in]       size: Size of each element\n * \\return          Memory address on success, `NULL` otherwise\n * \\note            Function is not available when \\ref LWESP_CFG_MEM_CUSTOM is `1` and must be implemented by user\n */\nvoid*\nlwesp_mem_calloc(size_t num, size_t size) {\n    void* ptr;\n    lwesp_core_lock();\n    ptr = mem_calloc(num, size); /* Allocate memory and clear it to 0. Then return pointer */\n    lwesp_core_unlock();\n    LWESP_DEBUGW(LWESP_CFG_DBG_MEM | LWESP_DBG_TYPE_TRACE, ptr == NULL, \"[LWESP MEM] Callocation failed: %d bytes\\r\\n\",\n                 (int)size * (int)num);\n    LWESP_DEBUGW(LWESP_CFG_DBG_MEM | LWESP_DBG_TYPE_TRACE, ptr != NULL,\n                 \"[LWESP MEM] Callocation OK: %d bytes, addr: %p\\r\\n\", (int)size * (int)num, ptr);\n    return ptr;\n}\n\n/**\n * \\brief           Free memory\n * \\param[in]       ptr: Pointer to memory previously returned using \\ref lwesp_mem_malloc,\n *                      \\ref lwesp_mem_calloc or \\ref lwesp_mem_realloc functions\n * \\note            Function is not available when \\ref LWESP_CFG_MEM_CUSTOM is `1` and must be implemented by user\n */\nvoid\nlwesp_mem_free(void* ptr) {\n    if (ptr == NULL) {\n        return;\n    }\n    LWESP_DEBUGF(LWESP_CFG_DBG_MEM | LWESP_DBG_TYPE_TRACE, \"[LWESP MEM] Free size: %d, address: %p\\r\\n\",\n                 (int)MEM_BLOCK_USER_SIZE(ptr), ptr);\n    lwesp_core_lock();\n    mem_free(ptr);\n    lwesp_core_unlock();\n}\n\n/**\n * \\brief           Assign memory region(s) for allocation functions\n * \\note            You can allocate multiple regions by assigning start address and region size in units of bytes\n * \\param[in]       regions: Pointer to list of regions to use for allocations\n * \\param[in]       len: Number of regions to use\n * \\return          `1` on success, `0` otherwise\n * \\note            Function is not available when \\ref LWESP_CFG_MEM_CUSTOM is `1`\n */\nuint8_t\nlwesp_mem_assignmemory(const lwesp_mem_region_t* regions, size_t len) {\n    uint8_t ret;\n    ret = mem_assignmem(regions, len); /* Assign memory */\n    return ret;\n}\n\n#endif /* !LWESP_CFG_MEM_CUSTOM || __DOXYGEN__ */\n\n/**\n * \\brief           Free memory in safe way by invalidating pointer after freeing\n * \\param[in]       ptr: Pointer to pointer to allocated memory to free\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_mem_free_s(void** ptr) {\n    if (ptr != NULL) {\n        lwesp_mem_free(*ptr);\n        *ptr = NULL;\n        return 1;\n    }\n    return 0;\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_parser.c",
    "content": "/**\n * \\file            lwesp_parser.c\n * \\brief           Parse incoming data from AT port\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_parser.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/* Increase pointer if matches character value */\n#define INC_IF_CHAR_EQUAL(p, ch)                                                                                       \\\n    if (*(p) == (ch)) {                                                                                                \\\n        ++(p);                                                                                                         \\\n    }\n\n/**\n * \\brief           Parse number from string\n * \\note            Input string pointer is changed and number is skipped\n * \\param[in,out]   str: Pointer to pointer to string to parse\n * \\return          Parsed number\n */\nint32_t\nlwespi_parse_number(const char** str) {\n    int32_t val = 0;\n    uint8_t minus = 0;\n    const char* p = *str; /*  */\n\n    INC_IF_CHAR_EQUAL(p, '\"'); /* Skip leading quotes */\n    INC_IF_CHAR_EQUAL(p, ','); /* Skip leading comma */\n    INC_IF_CHAR_EQUAL(p, '\"'); /* Skip leading quotes */\n    if (*p == '-') {           /* Check negative number */\n        minus = 1;\n        ++p;\n    }\n    while (LWESP_CHARISNUM(*p)) { /* Parse until character is valid number */\n        val = val * 10 + LWESP_CHARTONUM(*p);\n        ++p;\n    }\n    INC_IF_CHAR_EQUAL(p, ','); /* Go to next entry if possible */\n    *str = p;                  /* Save new pointer with new offset */\n\n    return minus ? -val : val;\n}\n\n/**\n * \\brief           Parse port from string\n * \\note            Input string pointer is changed and number is skipped\n * \\param[in,out]   str: Pointer to pointer to string to parse\n * \\return          Parsed port number\n */\nlwesp_port_t\nlwespi_parse_port(const char** str) {\n    lwesp_port_t p;\n\n    p = (lwesp_port_t)lwespi_parse_number(str); /* Parse port */\n    return p;\n}\n\n/**\n * \\brief           Parse number from string as hex\n * \\note            Input string pointer is changed and number is skipped\n * \\param[in,out]   str: Pointer to pointer to string to parse\n * \\return          Parsed number\n */\nuint32_t\nlwespi_parse_hexnumber(const char** str) {\n    int32_t val = 0;\n    const char* p = *str; /*  */\n\n    INC_IF_CHAR_EQUAL(p, '\"');       /* Skip leading quotes */\n    INC_IF_CHAR_EQUAL(p, ',');       /* Skip leading comma */\n    INC_IF_CHAR_EQUAL(p, '\"');       /* Skip leading quotes */\n    while (LWESP_CHARISHEXNUM(*p)) { /* Parse until character is valid number */\n        val = val * 16 + LWESP_CHARHEXTONUM(*p);\n        ++p;\n    }\n    INC_IF_CHAR_EQUAL(p, ','); /* Go to next entry if possible */\n    *str = p;                  /* Save new pointer with new offset */\n    return val;\n}\n\n/**\n * \\brief           Parse input string as string part of AT command\n * \\param[in,out]   src: Pointer to pointer to string to parse from\n * \\param[in]       dst: Destination pointer.\n *                      Set to `NULL` in case you want to skip string in source\n * \\param[in]       dst_len: Length of destination buffer,\n *                      including memory for `NULL` termination\n * \\param[in]       trim: Set to `1` to process entire string,\n *                      even if no memory anymore\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_string(const char** src, char* dst, size_t dst_len, uint8_t trim) {\n    const char* p = *src;\n    size_t i;\n\n    INC_IF_CHAR_EQUAL(p, ','); /* Skip leading comma */\n    INC_IF_CHAR_EQUAL(p, '\"'); /* Skip leading quotes */\n    i = 0;\n    if (dst_len > 0) {\n        --dst_len;\n    }\n    while (*p) {\n        if ((*p == '\"' && (p[1] == ',' || p[1] == '\\r' || p[1] == '\\n')) || (*p == '\\r' || *p == '\\n')) {\n            ++p;\n            break;\n        }\n        if (dst != NULL) {\n            if (i < dst_len) {\n                *dst++ = *p;\n                ++i;\n            } else if (!trim) {\n                break;\n            }\n        }\n        ++p;\n    }\n    if (dst != NULL) {\n        *dst = 0;\n    }\n    *src = p;\n    return 1;\n}\n\n#if LWESP_CFG_IPV6\n\n/**\n * \\brief           Parses IP V6 only, w/o possibility to append IP v4 to it.\n * \n * \\param           ip_str_iterator: Pointer to pointer to string\n * \\param           ip: IP structure\n * \\return          `1` if IP well parsed, `0` otherwise\n */\nuint8_t\nlwespi_parse_ipv6(const char** ip_str_iterator, lwesp_ip_t* ip) {\n    int8_t index_with_zeros = -1; /* Not found! */\n    uint8_t index;\n\n    memset(ip, 0x00, sizeof(*ip));\n    for (index = 0; index < 8 && !(**ip_str_iterator == '\\0' || **ip_str_iterator == '\"'); ++index) {\n        const char* ip_str_before = *ip_str_iterator;\n        uint16_t seg_value = lwespi_parse_hexnumber(ip_str_iterator);\n        const char* ip_str_after = *ip_str_iterator;\n\n        if (**ip_str_iterator == ':') {\n            ++(*ip_str_iterator);\n        }\n\n        /* If these are equal, a 0 break was detected */\n        if (ip_str_before == ip_str_after) {\n            /* We cannot have more than 1 separator */\n            if (index_with_zeros >= 0) {\n                return 0;\n            } else {\n                /* Save where break was detected */\n                index_with_zeros = (int8_t)index;\n            }\n            if (index == 0) {\n                ++(*ip_str_iterator);\n            }\n        } else {\n            ip->addr.ip6.addr[index] = seg_value;\n        }\n    }\n\n    /*\n     * Did we find zeros separator?\n     * Now we need to find where it was and compare to\n     * number of processed tokens.\n     *\n     * All is to be shifted, if segment is at the beginning or in the middle\n     */\n    if (index_with_zeros >= 0) {\n        uint8_t segments_to_move = index - (uint8_t)index_with_zeros - 1;\n        uint8_t index_start = (uint8_t)index_with_zeros + 1;\n        uint8_t index_end = (uint8_t)8 - segments_to_move;\n\n        if (segments_to_move > 0) {\n            memmove(&ip->addr.ip6.addr[index_end],                    /* TO */\n                    &ip->addr.ip6.addr[index_start],                  /* FROM */\n                    (segments_to_move) * sizeof(ip->addr.ip6.addr[0]) /* Count */\n            );\n            memset(&ip->addr.ip6.addr[index_with_zeros + 1], 0x00,\n                   (index_end - index_start) * sizeof(ip->addr.ip6.addr[0]));\n        }\n    }\n    return 1;\n}\n\n#endif /* LWESP_CFG_IPV6 */\n\n/**\n * \\brief           Parse string as IP address\n * \\param[in,out]   src: Pointer to pointer to string to parse from\n * \\param[out]      ip: Pointer to IP memory\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_ip(const char** src, lwesp_ip_t* ip) {\n    const char* p = *src;\n#if LWESP_CFG_IPV6\n    char c;\n#endif /* LWESP_CFG_IPV6 */\n\n    INC_IF_CHAR_EQUAL(p, '\"'); /* Skip leading quotes */\n\n#if LWESP_CFG_IPV6\n    /* Find first separator */\n    c = 0;\n    for (size_t i = 0; i < 6; ++i) {\n        if (p[i] == ':' || p[i] == ',') {\n            c = p[i];\n            break;\n        }\n    }\n#endif /* LWESP_CFG_IPV6 */\n\n    /* Go to original value */\n    if (0) {\n#if LWESP_CFG_IPV6\n    } else if (c == ':') {\n        ip->type = LWESP_IPTYPE_V6;\n\n        /* Parse IP address as separate function  */\n        memset(&ip->addr, 0x00, sizeof(ip->addr));\n        lwespi_parse_ipv6(&p, ip);\n#endif /* LWESP_CFG_IPV6 */\n    } else {\n        ip->type = LWESP_IPTYPE_V4;\n        for (size_t i = 0; i < LWESP_ARRAYSIZE(ip->addr.ip4.addr); ++i, ++p) {\n            ip->addr.ip4.addr[i] = lwespi_parse_number(&p);\n            if (*p != '.') {\n                break;\n            }\n        }\n    }\n    INC_IF_CHAR_EQUAL(p, '\"'); /* Skip trailing quotes */\n\n    *src = p; /* Set new pointer */\n    return 1;\n}\n\n/**\n * \\brief           Parse string as MAC address\n * \\param[in,out]   src: Pointer to pointer to string to parse from\n * \\param[out]      mac: Pointer to MAC memory\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_mac(const char** src, lwesp_mac_t* mac) {\n    const char* p = *src;\n\n    INC_IF_CHAR_EQUAL(p, '\"'); /* Skip leading quotes */\n    mac->mac[0] = lwespi_parse_hexnumber(&p);\n    ++p;\n    mac->mac[1] = lwespi_parse_hexnumber(&p);\n    ++p;\n    mac->mac[2] = lwespi_parse_hexnumber(&p);\n    ++p;\n    mac->mac[3] = lwespi_parse_hexnumber(&p);\n    ++p;\n    mac->mac[4] = lwespi_parse_hexnumber(&p);\n    ++p;\n    mac->mac[5] = lwespi_parse_hexnumber(&p);\n    INC_IF_CHAR_EQUAL(p, '\"'); /* Skip trailing quotes */\n    INC_IF_CHAR_EQUAL(p, ','); /* Go to next entry if possible */\n    *src = p;                  /* Set new pointer */\n    return 1;\n}\n\n/**\n * \\brief           Parse +CIPSTATUS or +CIPSTATE response from ESP device\n * \\param[in]       str: Input string to parse\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwespi_parse_cipstatus_cipstate(const char* str) {\n    uint8_t cn_num = 0;\n\n    cn_num = lwespi_parse_number(&str); /* Parse connection number */\n    esp.m.active_conns |= 1 << cn_num;  /* Set flag as active */\n\n    /*\n     * If connection looks \"alive\" in the \n     * cipstatus result, but not alive in internal\n     * structure, then force connection close ASAP\n     */\n    if (!esp.m.conns[cn_num].status.f.active) {\n        lwesp_conn_close(&esp.m.conns[cn_num], 0);\n    }\n\n    lwespi_parse_string(&str, NULL, 0, 1); /* Parse string and ignore result */\n    lwespi_parse_ip(&str, &esp.m.conns[cn_num].remote_ip);\n    esp.m.conns[cn_num].remote_port = lwespi_parse_number(&str);\n    esp.m.conns[cn_num].local_port = lwespi_parse_number(&str);\n    esp.m.conns[cn_num].status.f.client = !lwespi_parse_number(&str);\n\n    return lwespOK;\n}\n\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n\n/**\n * \\brief           Parse +CIPRECVLEN statement\n * \\param[in]       str: Input string to parse\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwespr_t\nlwespi_parse_ciprecvlen(const char* str) {\n    int32_t len;\n\n    if (*str == '+') {\n        str += 12;\n    }\n    for (size_t i = 0; i < LWESP_CFG_MAX_CONNS; ++i) {\n        len = lwespi_parse_number(&str);\n        if (len < 0) {\n            continue;\n        }\n        esp.m.conns[i].tcp_available_bytes = len;\n    }\n    return lwespOK;\n}\n\n#endif /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n\n/**\n * \\brief           Parse +IPD statement\n * \\param[in]       str: Input string to parse\n * \\return          Member of \\ref lwespr_t enumeration\n */\nlwesp_conn_p\nlwespi_parse_ipd(const char* str) {\n    lwesp_conn_p c;\n    uint8_t conn, is_data_ipd;\n    size_t len;\n\n    if (*str == '+') {\n        str += 5;\n    }\n\n    conn = lwespi_parse_number(&str); /* Parse number for connection number */\n    len = lwespi_parse_number(&str);  /* Parse number for number of available_bytes/bytes_to_read */\n    c = conn < LWESP_CFG_MAX_CONNS ? &esp.m.conns[conn] : NULL;\n    if (c == NULL) {\n        return NULL;\n    }\n\n    /*\n     * First check if this string is \"notification only\" or actual \"data packet\".\n     *\n     * Take decision based on ':' character before data. We can expect 3 types of format:\n     *\n     * +IPD,conn_num,available_bytes<CR><LF>                    : Notification only, for TCP connection\n     * +IPD,conn_num,bytes_in_packet:data                       : Data packet w/o remote ip/port,\n     *                                                              as response on manual TCP read or if AT+CIPDINFO=0\n     * +IPD,conn_num,bytes_in_packet,remote_ip,remote_port:data : Data packet w/ remote ip/port,\n     *                                                              as response on automatic read of all connection types\n     */\n    is_data_ipd = strchr(str, ':') != NULL; /* Check if we have ':' in string */\n\n    if (0) {\n#if LWESP_CFG_CONN_MANUAL_TCP_RECEIVE\n        /*\n     * Check if +IPD is only notification and not actual data packet\n     * +IPD should always be only\n     * notification message and never include data.\n     * \n     * Actual data read shall be done with different command\n     */\n    } else if (!is_data_ipd) {        /* If not data packet */\n        c->tcp_available_bytes = len; /* Set new value for number of bytes available to read from device */\n#endif                                /* LWESP_CFG_CONN_MANUAL_TCP_RECEIVE */\n\n        /*\n         * If additional information are enabled (IP and PORT),\n         * parse them and save.\n         *\n         * Even if information is enabled, in case of manual TCP\n         * receive, these information are not present.\n         *\n         * Check for ':' character if it is end of string and determine how to proceed\n         */\n    } else if (*str != ':') {\n        lwespi_parse_ip(&str, &esp.m.ipd.ip);     /* Parse incoming packet IP */\n        esp.m.ipd.port = lwespi_parse_port(&str); /* Get port on IPD data */\n\n        LWESP_MEMCPY(&esp.m.conns[conn].remote_ip, &esp.m.ipd.ip, sizeof(esp.m.ipd.ip));\n        LWESP_MEMCPY(&esp.m.conns[conn].remote_port, &esp.m.ipd.port, sizeof(esp.m.ipd.port));\n    }\n\n    if (is_data_ipd) {           /* Shall we start IPD read procedure? */\n        esp.m.ipd.tot_len = len; /* Total number of bytes in this received packet or notification message */\n        esp.m.ipd.conn = c;      /* Pointer to connection we have data for or notification message */\n        esp.m.ipd.read = 1;      /* Start reading network data */\n        esp.m.ipd.rem_len = len; /* Number of remaining bytes to read */\n    }\n    return c;\n}\n\n/**\n * \\brief           Parse AT and SDK versions from AT+GMR response\n * \\param[in]       str: String starting with version numbers\n * \\param[out]      version_out: Output variable to save version\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_at_sdk_version(const char* str, lwesp_sw_version_t* version_out) {\n    uint32_t version = 0;\n\n    version |= ((uint8_t)lwespi_parse_number(&str)) << 24;\n    ++str;\n    version |= ((uint8_t)lwespi_parse_number(&str)) << 16;\n    ++str;\n    version |= ((uint8_t)lwespi_parse_number(&str)) << 8;\n    version_out->version = version;\n    return 1;\n}\n\n/**\n * \\brief           Parse +LINK_CONN received string for new connection active\n * \\param[in]       str: Pointer to input string starting with +LINK_CONN\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_link_conn(const char* str) {\n    if (str == NULL) {\n        return 0;\n    }\n    if (*str == '+') {\n        str += 11;\n    }\n    esp.m.link_conn.failed = lwespi_parse_number(&str);\n    esp.m.link_conn.num = lwespi_parse_number(&str);\n    if (!strncmp(str, \"\\\"TCP\\\"\", 5)) {\n        esp.m.link_conn.type = LWESP_CONN_TYPE_TCP;\n        str += 6;\n    } else if (!strncmp(str, \"\\\"UDP\\\"\", 5)) {\n        esp.m.link_conn.type = LWESP_CONN_TYPE_UDP;\n        str += 6;\n    } else if (!strncmp(str, \"\\\"SSL\\\"\", 5)) {\n        esp.m.link_conn.type = LWESP_CONN_TYPE_SSL;\n        str += 6;\n#if LWESP_CFG_IPV6\n    } else if (!strncmp(str, \"\\\"TCPv6\\\"\", 7)) {\n        esp.m.link_conn.type = LWESP_CONN_TYPE_TCPV6;\n        str += 8;\n    } else if (!strncmp(str, \"\\\"UDPv6\\\"\", 7)) {\n        esp.m.link_conn.type = LWESP_CONN_TYPE_UDPV6;\n        str += 8;\n    } else if (!strncmp(str, \"\\\"SSLv6\\\"\", 7)) {\n        esp.m.link_conn.type = LWESP_CONN_TYPE_SSLV6;\n        str += 8;\n#endif /* LWESP_CFG_IPV6 */\n    } else {\n        return 0;\n    }\n    esp.m.link_conn.is_server = lwespi_parse_number(&str);\n    lwespi_parse_ip(&str, &esp.m.link_conn.remote_ip);\n    esp.m.link_conn.remote_port = lwespi_parse_port(&str);\n    esp.m.link_conn.local_port = lwespi_parse_port(&str);\n    return 1;\n}\n\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n/**\n * \\brief           Parse received message for list access points\n * \\param[in]       str: Pointer to input string starting with +CWLAP\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_cwlap(const char* str, lwesp_msg_t* msg) {\n    if (!CMD_IS_DEF(LWESP_CMD_WIFI_CWLAP) || /* Do we have valid message here and enough memory to save everything? */\n        msg->msg.ap_list.aps == NULL || msg->msg.ap_list.apsi >= msg->msg.ap_list.apsl) {\n        return 0;\n    }\n    if (*str == '+') { /* Does string contain '+' as first character */\n        str += 7;      /* Skip this part */\n    }\n    if (*str != '(') { /* We must start with opening bracket */\n        return 0;\n    }\n    ++str;\n\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].ecn = (lwesp_ecn_t)lwespi_parse_number(&str);\n    lwespi_parse_string(&str, msg->msg.ap_list.aps[msg->msg.ap_list.apsi].ssid,\n                        sizeof(msg->msg.ap_list.aps[msg->msg.ap_list.apsi].ssid), 1);\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].rssi = (int16_t)lwespi_parse_number(&str);\n    lwespi_parse_mac(&str, &msg->msg.ap_list.aps[msg->msg.ap_list.apsi].mac);\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].ch = (uint8_t)lwespi_parse_number(&str);\n#if LWESP_CFG_ACCESS_POINT_STRUCT_FULL_FIELDS\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].scan_type = (uint8_t)lwespi_parse_number(&str); /* Scan type */\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].scan_time_min =\n        (uint16_t)lwespi_parse_number(&str); /* Scan time minimum */\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].scan_time_max =\n        (uint16_t)lwespi_parse_number(&str); /* Scan time maximum */\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].freq_offset = (int16_t)lwespi_parse_number(&str); /* Freq offset */\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].freq_cal = (int16_t)lwespi_parse_number(&str);    /* Freqcal value */\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].pairwise_cipher =\n        (lwesp_ap_cipher_t)lwespi_parse_number(&str); /* Pairwise cipher */\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].group_cipher =\n        (lwesp_ap_cipher_t)lwespi_parse_number(&str); /* Group cipher */\n#else\n    /* Read and ignore values */\n    lwespi_parse_number(&str);\n    lwespi_parse_number(&str);\n    lwespi_parse_number(&str);\n    lwespi_parse_number(&str);\n    lwespi_parse_number(&str);\n    lwespi_parse_number(&str);\n    lwespi_parse_number(&str);\n#endif /* !LWESP_CFG_ACCESS_POINT_STRUCT_FULL_FIELDS */\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].bgn = lwespi_parse_number(&str);\n    msg->msg.ap_list.aps[msg->msg.ap_list.apsi].wps = lwespi_parse_number(&str);\n\n    /* Go to next entry */\n    ++msg->msg.ap_list.apsi;            /* Increase number of found elements */\n    if (msg->msg.ap_list.apf != NULL) { /* Set pointer if necessary */\n        *msg->msg.ap_list.apf = msg->msg.ap_list.apsi;\n    }\n    return 1;\n}\n\n/**\n * \\brief           Parse received message for current AP information\n * \\param[in]       str: Pointer to input string starting with +CWJAP\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_cwjap(const char* str, lwesp_msg_t* msg) {\n    if (!CMD_IS_DEF(\n            LWESP_CMD_WIFI_CWJAP_GET)) { /* Do we have valid message here and enough memory to save everything? */\n        return 0;\n    }\n    if (*str == '+') { /* Does string contain '+' as first character */\n        str += 7;      /* Skip this part */\n    }\n    if (*str != '\"') { /* We must start with quotation mark */\n        return 0;\n    }\n    lwespi_parse_string(&str, esp.msg->msg.sta_info_ap.info->ssid, LWESP_CFG_MAX_SSID_LENGTH, 1);\n    lwespi_parse_mac(&str, &esp.msg->msg.sta_info_ap.info->mac);\n    esp.msg->msg.sta_info_ap.info->ch = lwespi_parse_number(&str);\n    esp.msg->msg.sta_info_ap.info->rssi = lwespi_parse_number(&str);\n\n    LWESP_UNUSED(msg);\n\n    return 1;\n}\n\n#endif /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n\n#if LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__\n/**\n * \\brief           Parse received message for list stations\n * \\param[in]       str: Pointer to input string starting with +CWLAP\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_cwlif(const char* str, lwesp_msg_t* msg) {\n    if (!CMD_IS_DEF(LWESP_CMD_WIFI_CWLIF) /* Do we have valid message here and enough memory to save everything? */\n        || msg->msg.sta_list.stas == NULL || msg->msg.sta_list.stai >= msg->msg.sta_list.stal) {\n        return 0;\n    }\n\n    if (*str == '+') {\n        str += 7;\n    }\n\n    lwespi_parse_ip(&str, &msg->msg.sta_list.stas[msg->msg.sta_list.stai].ip);\n    lwespi_parse_mac(&str, &msg->msg.sta_list.stas[msg->msg.sta_list.stai].mac);\n\n    ++msg->msg.sta_list.stai;             /* Increase number of found elements */\n    if (msg->msg.sta_list.staf != NULL) { /* Set pointer if necessary */\n        *msg->msg.sta_list.staf = msg->msg.sta_list.stai;\n    }\n    return 1;\n}\n\n/**\n * \\brief           Parse MAC address and send to user layer\n * \\param[in]       str: Input string excluding `+DIST_STA_IP:` part\n * \\param[in]       is_conn: Set to `1` if station connected or `0` if station disconnected\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_ap_conn_disconn_sta(const char* str, uint8_t is_conn) {\n    lwesp_mac_t mac;\n\n    lwespi_parse_mac(&str, &mac); /* Parse MAC address */\n\n    esp.evt.evt.ap_conn_disconn_sta.mac = &mac;\n    lwespi_send_cb(is_conn ? LWESP_EVT_AP_CONNECTED_STA : LWESP_EVT_AP_DISCONNECTED_STA); /* Send event function */\n    return 1;\n}\n\n/**\n * \\brief           Parse received string \"+DIST_STA_IP\" and send notification to user layer\n * \\param[in]       str: Input string excluding \"+DIST_STA_IP:\" part\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_ap_ip_sta(const char* str) {\n    lwesp_mac_t mac;\n    lwesp_ip_t ip;\n\n    lwespi_parse_mac(&str, &mac); /* Parse MAC address */\n    lwespi_parse_ip(&str, &ip);   /* Parse IP address */\n\n    esp.evt.evt.ap_ip_sta.mac = &mac;\n    esp.evt.evt.ap_ip_sta.ip = &ip;\n    lwespi_send_cb(LWESP_EVT_AP_IP_STA); /* Send event function */\n    return 1;\n}\n\n/**\n * \\brief           Parse received message for current AP information\n * \\param[in]       str: Pointer to input string starting with +CWSAP\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_cwsap(const char* str, lwesp_msg_t* msg) {\n    if (!CMD_IS_DEF(\n            LWESP_CMD_WIFI_CWSAP_GET)) { /* Do we have valid message here and enough memory to save everything? */\n        return 0;\n    }\n    if (*str == '+') { /* Does string contain '+' as first character */\n        str += 7;      /* Skip this part */\n    }\n    if (*str != '\"') { /* We must start with quotation mark */\n        return 0;\n    }\n    lwespi_parse_string(&str, esp.msg->msg.ap_conf_get.ap_conf->ssid, LWESP_CFG_MAX_SSID_LENGTH, 1);\n    lwespi_parse_string(&str, esp.msg->msg.ap_conf_get.ap_conf->pwd, LWESP_CFG_MAX_PWD_LENGTH, 1);\n    esp.msg->msg.ap_conf_get.ap_conf->ch = lwespi_parse_number(&str);\n    esp.msg->msg.ap_conf_get.ap_conf->ecn = lwespi_parse_number(&str);\n    esp.msg->msg.ap_conf_get.ap_conf->max_cons = lwespi_parse_number(&str);\n    esp.msg->msg.ap_conf_get.ap_conf->hidden = lwespi_parse_number(&str);\n\n    LWESP_UNUSED(msg);\n\n    return 1;\n}\n#endif /* LWESP_CFG_MODE_ACCESS_POINT || __DOXYGEN__ */\n\n#if LWESP_CFG_PING || __DOXYGEN__\n\n/**\n * \\brief           Parse received time for ping\n * \\param[in]       str: Pointer to input string starting with +time\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_ping_time(const char* str, lwesp_msg_t* msg) {\n    if (!CMD_IS_DEF(LWESP_CMD_TCPIP_PING)) {\n        return 0;\n    }\n    if (*str == '+') {\n        str += 6;\n    }\n    msg->msg.tcpip_ping.time = lwespi_parse_number(&str);\n    if (msg->msg.tcpip_ping.time_out != NULL) {\n        *msg->msg.tcpip_ping.time_out = msg->msg.tcpip_ping.time;\n    }\n    return 1;\n}\n\n#endif /* LWESP_CFG_PING || __DOXYGEN__ */\n\n#if LWESP_CFG_DNS || __DOXYGEN__\n\n/**\n * \\brief           Parse received message domain DNS name\n * \\param[in]       str: Pointer to input string starting with +CWLAP\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_cipdomain(const char* str, lwesp_msg_t* msg) {\n    if (!CMD_IS_DEF(LWESP_CMD_TCPIP_CIPDOMAIN)) {\n        return 0;\n    }\n    if (*str == '+') {\n        str += 11;\n    }\n    lwespi_parse_ip(&str, msg->msg.dns_getbyhostname.ip); /* Parse IP address */\n    return 1;\n}\n\n#endif /* LWESP_CFG_DNS || __DOXYGEN__ */\n\n#if LWESP_CFG_SNTP || __DOXYGEN__\n\n/**\n * \\brief           Parse received message for SNTP configuration\n * \\param[in]       str: Pointer to input string starting with +CIPSNTPCFG\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_sntp_cfg(const char* str, lwesp_msg_t* msg) {\n    int32_t num;\n    if (!CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSNTPCFG_GET)) {\n        return 0;\n    }\n    if (*str == '+') { /* Check input string */\n        str += 12;\n    }\n    num = lwespi_parse_number(&str);\n    if (msg->msg.tcpip_sntp_cfg_get.en != NULL) {\n        *msg->msg.tcpip_sntp_cfg_get.en = num;\n    }\n    num = lwespi_parse_number(&str);\n    if (msg->msg.tcpip_sntp_cfg_get.tz != NULL) {\n        *msg->msg.tcpip_sntp_cfg_get.tz = (int16_t)num;\n    }\n    /* TODO: Parse hostnames... */\n    return 1;\n}\n\n/**\n * \\brief           Parse received message for SNTP sync interval\n * \\param[in]       str: Pointer to input string starting with +CIPSNTPINTV\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_cipsntpintv(const char* str, lwesp_msg_t* msg) {\n    int32_t num;\n    if (!CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSNTPINTV_GET)) {\n        return 0;\n    }\n    if (*str == '+') { /* Check input string */\n        str += 13;\n    }\n    num = lwespi_parse_number(&str);\n    if (msg->msg.tcpip_sntp_intv_get.interval != NULL) {\n        *msg->msg.tcpip_sntp_intv_get.interval = (uint32_t)num;\n    }\n    return 1;\n}\n\n/**\n * \\brief           Parse received message for SNTP time\n * \\param[in]       str: Pointer to input string starting with +CIPSNTPTIME\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_cipsntptime(const char* str, lwesp_msg_t* msg) {\n    const char* days[] = {\"Sun\", \"Mon\", \"Tue\", \"Wed\", \"Thu\", \"Fri\", \"Sat\"};\n    const char* months[] = {\"Jan\", \"Feb\", \"Mar\", \"Apr\", \"May\", \"Jun\", \"Jul\", \"Aug\", \"Sep\", \"Oct\", \"Nov\", \"Dec\"};\n\n    if (!CMD_IS_DEF(LWESP_CMD_TCPIP_CIPSNTPTIME)) {\n        return 0;\n    }\n    if (*str == '+') { /* Check input string */\n        str += 13;\n    }\n\n    /* Scan for day in a week */\n    for (size_t i = 0; i < LWESP_ARRAYSIZE(days); ++i) {\n        if (!strncmp(str, days[i], 3)) {\n            msg->msg.tcpip_sntp_time.dt->tm_wday = (int)i;\n            break;\n        }\n    }\n    str += 4;\n\n    /* Scan for month in a year */\n    for (size_t i = 0; i < LWESP_ARRAYSIZE(months); ++i) {\n        if (!strncmp(str, months[i], 3)) {\n            msg->msg.tcpip_sntp_time.dt->tm_mon = (int)i;\n            break;\n        }\n    }\n    str += 4;\n    if (*str == ' ') { /* Numbers < 10 could have one more space */\n        ++str;\n    }\n    msg->msg.tcpip_sntp_time.dt->tm_mday = (int)lwespi_parse_number(&str);\n    ++str;\n    msg->msg.tcpip_sntp_time.dt->tm_hour = (int)lwespi_parse_number(&str);\n    ++str;\n    msg->msg.tcpip_sntp_time.dt->tm_min = (int)lwespi_parse_number(&str);\n    ++str;\n    msg->msg.tcpip_sntp_time.dt->tm_sec = (int)lwespi_parse_number(&str);\n    ++str;\n    msg->msg.tcpip_sntp_time.dt->tm_year = (int)lwespi_parse_number(&str) - 1900;\n    return 1;\n}\n\n#endif /* LWESP_CFG_SNTP || __DOXYGEN__ */\n\n#if LWESP_CFG_HOSTNAME || __DOXYGEN__\n\n/**\n * \\brief           Parse received message for HOSTNAME\n * \\param[in]       str: Pointer to input string starting with +CWHOSTNAME\n * \\param[in]       msg: Pointer to message\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_hostname(const char* str, lwesp_msg_t* msg) {\n    size_t i;\n    if (!CMD_IS_DEF(LWESP_CMD_WIFI_CWHOSTNAME_GET)) {\n        return 0;\n    }\n    if (*str == '+') { /* Check input string */\n        str += 12;\n    }\n    msg->msg.wifi_hostname.hostname_get[0] = 0;\n    if (*str != '\\r') {\n        i = 0;\n        for (; i < (msg->msg.wifi_hostname.length - 1) && *str && *str != '\\r'; ++i, ++str) {\n            msg->msg.wifi_hostname.hostname_get[i] = *str;\n        }\n        msg->msg.wifi_hostname.hostname_get[i] = '\\0';\n    }\n    return 1;\n}\n\n#endif /* LWESP_CFG_HOSTNAME || __DOXYGEN__ */\n\n/**\n * \\brief           Parse received message for DHCP\n * \\param[in]       str: Pointer to input string starting with +CWDHCP\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwespi_parse_cwdhcp(const char* str) {\n    uint8_t val;\n\n    if (!CMD_IS_CUR(LWESP_CMD_WIFI_CWDHCP_GET)) {\n        return 0;\n    }\n    if (*str == '+') {\n        str += 8;\n    }\n\n    val = lwespi_parse_number(&str);\n\n#if LWESP_CFG_MODE_ACCESS_POINT\n    esp.m.ap.dhcp = (val & 0x01) == 0x01;\n#endif /* LWESP_CFG_MODE_ACCESS_POINT */\n#if LWESP_CFG_MODE_STATION\n    esp.m.sta.dhcp = (val & 0x02) == 0x02;\n#endif /* LWESP_CFG_MODE_STATION */\n\n    return 1;\n}\n\n#if LWESP_CFG_WEBSERVER || __DOXYGEN__\n\n/**\n * \\brief           Parse +WEBSERVER response from ESP device\n * \\param[in]       str: Input string to parse\n * \\return          Member of \\ref lwespr_t enumeration\n */\nuint8_t\nlwespi_parse_webserver(const char* str) {\n\n    esp.evt.evt.ws_status.code = lwespi_parse_number(&str);\n    lwespi_send_cb(LWESP_EVT_WEBSERVER); /* Send event function */\n    return 1;\n}\n\n#endif /* LWESP_CFG_WEBSERVER || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_pbuf.c",
    "content": "/**\n * \\file            lwesp_pbuf.c\n * \\brief           Packet buffer manager\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_pbuf.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/* Set size of pbuf structure */\n#define SIZEOF_PBUF_STRUCT LWESP_MEM_ALIGN(sizeof(lwesp_pbuf_t))\n#define SET_NEW_LEN(v, len)                                                                                            \\\n    do {                                                                                                               \\\n        if ((v) != NULL) {                                                                                             \\\n            *(v) = (len);                                                                                              \\\n        }                                                                                                              \\\n    } while (0)\n\n/**\n * \\brief           Skip pbufs for desired offset\n * \\param[in]       p: Source pbuf to skip\n * \\param[in]       off: Offset in units of bytes to skip\n * \\param[out]      new_off: New offset on new returned pbuf\n * \\return          New pbuf where offset was found, `NULL` if offset too big for pbuf chain\n */\nstatic lwesp_pbuf_p\npbuf_skip(lwesp_pbuf_p p, size_t off, size_t* new_off) {\n    if (p == NULL || p->tot_len < off) { /* Check valid parameters */\n        SET_NEW_LEN(new_off, 0);         /* Set output value */\n        return NULL;\n    }\n\n    /* Skip pbufs until we reach offset */\n    for (; p != NULL && p->len <= off; p = p->next) {\n        off -= p->len; /* Decrease offset by current pbuf length */\n    }\n\n    SET_NEW_LEN(new_off, off); /* Set output value */\n    return p;\n}\n\n/**\n * \\brief           Allocate packet buffer for network data of specific size\n * \\param[in]       len: Length of payload memory to allocate\n * \\return          Pointer to allocated memory, `NULL` otherwise\n */\nlwesp_pbuf_p\nlwesp_pbuf_new(size_t len) {\n    lwesp_pbuf_p p;\n\n    p = lwesp_mem_malloc(SIZEOF_PBUF_STRUCT + sizeof(*p->payload) * len);\n    LWESP_DEBUGW(LWESP_CFG_DBG_PBUF | LWESP_DBG_TYPE_TRACE, p == NULL, \"[LWESP PBUF] Failed to allocate %u bytes\\r\\n\",\n                 (unsigned)len);\n    LWESP_DEBUGW(LWESP_CFG_DBG_PBUF | LWESP_DBG_TYPE_TRACE, p != NULL, \"[LWESP PBUF] Allocated %u bytes on %p\\r\\n\",\n                 (unsigned)len, (void*)p);\n    if (p != NULL) {\n        p->next = NULL;                                        /* No next element in chain */\n        p->tot_len = len;                                      /* Set total length of pbuf chain */\n        p->len = len;                                          /* Set payload length */\n        p->payload = (void*)(((char*)p) + SIZEOF_PBUF_STRUCT); /* Set pointer to payload data */\n        p->ref = 1;                                            /* Single reference is used on this pbuf */\n    }\n    return p;\n}\n\n/**\n * \\brief           Free previously allocated packet buffer\n * \\note            Application must not use reference to pbuf after the call to this function.\n *                  It is advised to immediately set pointer to `NULL` or to call.\n *                  Alternatively, call \\ref lwesp_pbuf_free_s, which will reset the pointer\n *                  after free operation has been completed\n *                  \n * \\param[in]       pbuf: Packet buffer to free\n * \\return          Number of freed pbufs from head\n * \\sa              lwesp_pbuf_free_s\n */\nsize_t\nlwesp_pbuf_free(lwesp_pbuf_p pbuf) {\n    lwesp_pbuf_p p, pn;\n    size_t ref, cnt;\n\n    LWESP_ASSERT0(pbuf != NULL);\n\n    /*\n     * Free all pbufs until first ->ref > 1 is reached\n     * which means somebody has reference to part of pbuf and we have to keep it as is\n     */\n    cnt = 0;\n    for (p = pbuf; p != NULL;) {\n        lwesp_core_lock();\n        ref = --p->ref; /* Decrease current value and save it */\n        lwesp_core_unlock();\n        if (ref == 0) { /* Did we reach 0 and are ready to free it? */\n            LWESP_DEBUGF(LWESP_CFG_DBG_PBUF | LWESP_DBG_TYPE_TRACE,\n                         \"[LWESP PBUF] Deallocating %p with len/tot_len: %u/%u\\r\\n\", (void*)p, (unsigned)p->len,\n                         (unsigned)p->tot_len);\n            pn = p->next;                 /* Save next entry */\n            lwesp_mem_free_s((void**)&p); /* Free memory for pbuf */\n            p = pn;                       /* Restore with next entry */\n            ++cnt;                        /* Increase number of freed pbufs */\n        } else {\n            break;\n        }\n    }\n    return cnt;\n}\n\n/**\n * \\brief           Free previously allocated packet buffer in safe way.\n *                  Function accepts pointer to pointer and will set the pointer to `NULL`\n *                  after the successful allocation\n * \n * \\param[in,out]   pbuf_ptr: Pointer to pointer to packet buffer\n * \\return          Number of packet buffers freed in the chain\n */\nsize_t\nlwesp_pbuf_free_s(lwesp_pbuf_p* pbuf_ptr) {\n    size_t cnt = 0;\n\n    LWESP_ASSERT0(pbuf_ptr != NULL);\n\n    if (*pbuf_ptr != NULL) {\n        cnt = lwesp_pbuf_free(*pbuf_ptr);\n        *pbuf_ptr = NULL;\n    }\n    return cnt;\n}\n\n/**\n * \\brief           Concatenate `2` packet buffers together to one big packet\n * \\note            After `tail` pbuf has been added to `head` pbuf chain,\n *                  it must not be referenced by user anymore as it is now completely controlled by `head` pbuf.\n *                  In simple words, when user calls this function, it should not call \\ref lwesp_pbuf_free function anymore,\n *                  as it might make memory undefined for `head` pbuf.\n * \\param[in]       head: Head packet buffer to append new pbuf to\n * \\param[in]       tail: Tail packet buffer to append to head pbuf\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n * \\sa              lwesp_pbuf_cat_s\n * \\sa              lwesp_pbuf_chain\n */\nlwespr_t\nlwesp_pbuf_cat(lwesp_pbuf_p head, const lwesp_pbuf_p tail) {\n    LWESP_ASSERT(head != NULL);\n    LWESP_ASSERT(tail != NULL);\n\n    /*\n     * For all pbuf packets in head,\n     * increase total length parameter of all next entries\n     */\n    for (; head->next != NULL; head = head->next) {\n        head->tot_len += tail->tot_len; /* Increase total length of packet */\n    }\n    head->tot_len += tail->tot_len; /* Increase total length of last packet in chain */\n    head->next = tail;              /* Set next packet buffer as next one */\n\n    return lwespOK;\n}\n\n/**\n * \\brief           Concatenate `2` packet buffers together to one big packet with safe pointer management\n * \\note            After `tail` pbuf has been added to `head` pbuf chain,\n *                  `tail` pointer will be set to `NULL`\n * \\param[in]       head: Head packet buffer to append new pbuf to\n * \\param[in]       tail: Pointer to pointer to tail packet buffer to append to head pbuf.\n *                      Pointed memory will be set to `NULL` after successful concatenation\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n * \\sa              lwesp_pbuf_cat\n * \\sa              lwesp_pbuf_chain\n */\nlwespr_t\nlwesp_pbuf_cat_s(lwesp_pbuf_p head, lwesp_pbuf_p* tail) {\n    lwespr_t res = lwespOK;\n\n    LWESP_ASSERT(head != NULL);\n    LWESP_ASSERT(tail != NULL);\n\n    if (*tail != NULL && (res = lwesp_pbuf_cat(head, *tail)) == lwespOK) {\n        *tail = NULL;\n    }\n    return res;\n}\n\n/**\n * \\brief           Chain 2 pbufs together. Similar to \\ref lwesp_pbuf_cat\n *                  but now new reference is done from head pbuf to tail pbuf.\n * \\note            After this function call, user must call \\ref lwesp_pbuf_free to remove\n *                  its reference to tail pbuf and allow control to head pbuf: `lwesp_pbuf_free(tail)`\n * \\param[in]       head: Head packet buffer to append new pbuf to\n * \\param[in]       tail: Tail packet buffer to append to head pbuf\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n * \\sa              lwesp_pbuf_cat\n * \\sa              lwesp_pbuf_cat_s\n * \\sa              lwesp_pbuf_chain_s\n */\nlwespr_t\nlwesp_pbuf_chain(lwesp_pbuf_p head, lwesp_pbuf_p tail) {\n    lwespr_t res;\n\n    LWESP_ASSERT(head != NULL);\n    LWESP_ASSERT(tail != NULL);\n\n    /*\n     * To prevent issues with multi-thread access,\n     * first reference pbuf and increase counter\n     */\n    lwesp_pbuf_ref(tail);                                /* Reference tail pbuf by head pbuf now */\n    if ((res = lwesp_pbuf_cat(head, tail)) != lwespOK) { /* Did we concatenate them together successfully? */\n        lwesp_pbuf_free(tail);                           /* Call free to decrease reference counter */\n    }\n    return res;\n}\n\n/**\n * \\brief           Unchain first pbuf from list and return second one\n *\n * `tot_len` and `len` fields are adjusted to reflect new values and reference counter is `as is`\n *\n * \\note            After unchain, user must take care of both pbufs (`head` and `new returned one`)\n * \\param[in]       head: First pbuf in chain to remove from chain\n * \\return          Next pbuf after `head`\n */\nlwesp_pbuf_p\nlwesp_pbuf_unchain(lwesp_pbuf_p head) {\n    lwesp_pbuf_p r = NULL;\n    if (head != NULL && head->next != NULL) { /* Check for valid pbuf */\n        r = head->next;                       /* Set return value as next pbuf */\n\n        head->next = NULL;         /* Clear next pbuf */\n        head->tot_len = head->len; /* Set new length of head pbuf */\n    }\n    return r;\n}\n\n/**\n * \\brief           Increment reference count on pbuf\n * \\param[in]       pbuf: pbuf to increase reference\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_pbuf_ref(lwesp_pbuf_p pbuf) {\n    LWESP_ASSERT(pbuf != NULL);\n\n    ++pbuf->ref; /* Increase reference count for pbuf */\n    return lwespOK;\n}\n\n/**\n * \\brief           Copy user data to chain of pbufs\n * \\param[in]       pbuf: First pbuf in chain to start copying to\n * \\param[in]       data: Input data to copy to pbuf memory\n * \\param[in]       len: Length of input data to copy\n * \\param[in]       offset: Start offset in pbuf where to start copying\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_pbuf_take(lwesp_pbuf_p pbuf, const void* data, size_t len, size_t offset) {\n    const uint8_t* d = data;\n    size_t copy_len;\n\n    LWESP_ASSERT(pbuf != NULL);\n    LWESP_ASSERT(data != NULL);\n    LWESP_ASSERT(len > 0);\n    LWESP_ASSERT(pbuf->tot_len >= len);\n\n    /* Skip if necessary and check if we are in valid range */\n    if (offset > 0) {\n        pbuf = pbuf_skip(pbuf, offset, &offset); /* Offset and check for new length */\n        if (pbuf == NULL) {\n            return lwespERR;\n        }\n    }\n\n    if (pbuf->tot_len < (len + offset)) {\n        return lwespERRPAR;\n    }\n\n    /* First only copy in case we have some offset from first pbuf */\n    if (offset > 0) {\n        copy_len = LWESP_MIN(pbuf->len - offset, len);     /* Get length to copy to current pbuf */\n        LWESP_MEMCPY(pbuf->payload + offset, d, copy_len); /* Copy to memory with offset */\n        len -= copy_len;                                   /* Decrease remaining bytes to copy */\n        d += copy_len;                                     /* Increase data pointer */\n        pbuf = pbuf->next;                                 /* Go to next pbuf */\n    }\n\n    /* Copy user memory to sequence of pbufs */\n    for (; len; pbuf = pbuf->next) {\n        copy_len = LWESP_MIN(len, pbuf->len);     /* Get copy length */\n        LWESP_MEMCPY(pbuf->payload, d, copy_len); /* Copy memory to pbuf payload */\n        len -= copy_len;                          /* Decrease number of remaining bytes to send */\n        d += copy_len;                            /* Increase data pointer */\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Copy memory from pbuf to user linear memory\n * \\param[in]       pbuf: Pbuf to copy from\n * \\param[out]      data: User linear memory to copy to\n * \\param[in]       len: Length of data in units of bytes\n * \\param[in]       offset: Possible start offset in pbuf\n * \\return          Number of bytes copied\n */\nsize_t\nlwesp_pbuf_copy(lwesp_pbuf_p pbuf, void* data, size_t len, size_t offset) {\n    size_t tot, tc;\n    uint8_t* d = data;\n\n    if (pbuf == NULL || data == NULL || len == 0 || pbuf->tot_len < offset) {\n        return 0;\n    }\n\n    /*\n     * In case user wants offset,\n     * skip to necessary pbuf\n     */\n    if (offset > 0) {\n        pbuf = pbuf_skip(pbuf, offset, &offset); /* Skip offset if necessary */\n        if (pbuf == NULL) {\n            return 0;\n        }\n    }\n\n    /*\n     * Copy data from pbufs to memory\n     * with checking for initial offset (only one can have offset)\n     */\n    tot = 0;\n    for (; pbuf != NULL && len; pbuf = pbuf->next) {\n        tc = LWESP_MIN(pbuf->len - offset, len);     /* Get length of data to copy */\n        LWESP_MEMCPY(d, pbuf->payload + offset, tc); /* Copy data from pbuf */\n        d += tc;\n        len -= tc;\n        tot += tc;\n        offset = 0; /* No more offset in this case */\n    }\n    return tot;\n}\n\n/**\n * \\brief           Get value from pbuf at specific position\n * \\param[in]       pbuf: Pbuf used to get data from\n * \\param[in]       pos: Position at which to get element\n * \\param[out]      el: Output variable to save element value at desired position\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_pbuf_get_at(const lwesp_pbuf_p pbuf, size_t pos, uint8_t* el) {\n    lwesp_pbuf_p p;\n\n    if (pbuf != NULL) {\n        p = pbuf_skip(pbuf, pos, &pos); /* Skip pbufs to desired position and get new offset from new pbuf */\n        if (p != NULL) {                /* Do we have new pbuf? */\n            *el = p->payload[pos];      /* Return memory at desired new offset from latest pbuf */\n            return 1;\n        }\n    }\n    return 0; /* Invalid character */\n}\n\n/**\n * \\brief           Find desired needle in a haystack\n * \\param[in]       pbuf: Pbuf used as haystack\n * \\param[in]       needle: Data memory used as needle\n * \\param[in]       len: Length of needle memory\n * \\param[in]       off: Starting offset in pbuf memory\n * \\return          `LWESP_SIZET_MAX` if no match or position where in pbuf we have a match\n * \\sa              lwesp_pbuf_strfind\n */\nsize_t\nlwesp_pbuf_memfind(const lwesp_pbuf_p pbuf, const void* needle, size_t len, size_t off) {\n    if (pbuf != NULL && needle != NULL && pbuf->tot_len >= (len + off)) { /* Check if valid entries */\n        /*\n         * Try entire buffer element by element\n         * and in case we have a match, report it\n         */\n        for (size_t i = off; i <= pbuf->tot_len - len; ++i) {\n            if (!lwesp_pbuf_memcmp(pbuf, needle, len, i)) { /* Check if identical */\n                return i;                                   /* We have a match! */\n            }\n        }\n    }\n    return LWESP_SIZET_MAX; /* Return maximal value of size_t variable to indicate error */\n}\n\n/**\n * \\brief           Find desired needle (str) in a haystack (pbuf)\n * \\param[in]       pbuf: Pbuf used as haystack\n * \\param[in]       str: String to search for in pbuf\n * \\param[in]       off: Starting offset in pbuf memory\n * \\return          `LWESP_SIZET_MAX` if no match or position where in pbuf we have a match\n * \\sa              lwesp_pbuf_memfind\n */\nsize_t\nlwesp_pbuf_strfind(const lwesp_pbuf_p pbuf, const char* str, size_t off) {\n    return lwesp_pbuf_memfind(pbuf, str, strlen(str), off);\n}\n\n/**\n * \\brief           Compare pbuf memory with memory from data\n * \\note            Compare is done on entire pbuf chain\n * \\param[in]       pbuf: Pbuf used to compare with data memory\n * \\param[in]       data: Actual data to compare with\n * \\param[in]       len: Length of input data in units of bytes\n * \\param[in]       offset: Start offset to use when comparing data\n * \\return          `0` if equal, `LWESP_SIZET_MAX` if memory/offset too big or anything between if not equal\n * \\sa              lwesp_pbuf_strcmp\n */\nsize_t\nlwesp_pbuf_memcmp(const lwesp_pbuf_p pbuf, const void* data, size_t len, size_t offset) {\n    lwesp_pbuf_p p;\n    uint8_t el;\n    const uint8_t* d = data;\n\n    if (pbuf == NULL || data == NULL || len == 0 /* Input parameters check */\n        || pbuf->tot_len < (offset + len)) {     /* Check of valid ranges */\n        return LWESP_SIZET_MAX;                  /* Invalid check here */\n    }\n\n    /*\n     * Find start pbuf to have more optimized search at the end\n     * Since we had a check on beginning, we must pass this for loop without any problems\n     */\n    for (p = pbuf; p != NULL && p->len <= offset; p = p->next) {\n        offset -= p->len; /* Decrease offset by length of pbuf */\n    }\n\n    /*\n     * We have known starting pbuf.\n     * Now it is time to check byte by byte from pbuf and memory\n     *\n     * Use byte by byte read function to inspect bytes separatelly\n     */\n    for (size_t i = 0; i < len; ++i) {\n        if (!lwesp_pbuf_get_at(p, offset + i, &el) || el != d[i]) { /* Get value from pbuf at specific offset */\n            return offset + 1;                                      /* Return value from offset where it failed */\n        }\n    }\n    return 0; /* Memory matches at this point */\n}\n\n/**\n * \\brief           Compare pbuf memory with input string\n * \\note            Compare is done on entire pbuf chain\n * \\param[in]       pbuf: Pbuf used to compare with data memory\n * \\param[in]       str: String to be compared with pbuf\n * \\param[in]       offset: Start memory offset in pbuf\n * \\return          `0` if equal, `LWESP_SIZET_MAX` if memory/offset too big or anything between if not equal\n * \\sa              lwesp_pbuf_memcmp\n */\nsize_t\nlwesp_pbuf_strcmp(const lwesp_pbuf_p pbuf, const char* str, size_t offset) {\n    return lwesp_pbuf_memcmp(pbuf, str, strlen(str), offset);\n}\n\n/**\n * \\brief           Get linear offset address for pbuf from specific offset\n * \\note            Since pbuf memory can be fragmented in chain,\n *                  you may need to call function multiple times to get memory for entire pbuf chain\n * \\param[in]       pbuf: Pbuf to get linear address\n * \\param[in]       offset: Start offset from where to start\n * \\param[out]      new_len: Length of memory returned by function\n * \\return          Pointer to memory on success, `NULL` otherwise\n */\nvoid*\nlwesp_pbuf_get_linear_addr(const lwesp_pbuf_p pbuf, size_t offset, size_t* new_len) {\n    lwesp_pbuf_p p = pbuf;\n\n    if (pbuf == NULL || pbuf->tot_len < offset) { /* Check input parameters */\n        SET_NEW_LEN(new_len, 0);\n        return NULL;\n    }\n    if (offset > 0) {                         /* Is there any offset? */\n        p = pbuf_skip(pbuf, offset, &offset); /* Skip pbuf to desired length */\n        if (p == NULL) {\n            SET_NEW_LEN(new_len, 0);\n            return NULL;\n        }\n    }\n\n    SET_NEW_LEN(new_len, p->len - offset);\n    return &p->payload[offset]; /* Return memory at desired offset */\n}\n\n/**\n * \\brief           Get data pointer from packet buffer\n * \\param[in]       pbuf: Packet buffer\n * \\return          Pointer to data buffer on success, `NULL` otherwise\n */\nvoid*\nlwesp_pbuf_data(const lwesp_pbuf_p pbuf) {\n    return pbuf != NULL ? pbuf->payload : NULL;\n}\n\n/**\n * \\brief           Get length of packet buffer\n * \\param[in]       pbuf: Packet buffer to get length for\n * \\param[in]       tot: Set to `1` to return total packet chain length or `0` to get only first packet length\n * \\return          Length of data in units of bytes\n */\nsize_t\nlwesp_pbuf_length(const lwesp_pbuf_p pbuf, uint8_t tot) {\n    return pbuf != NULL ? (tot ? pbuf->tot_len : pbuf->len) : 0;\n}\n\n/**\n * \\brief           Set new length of pbuf\n * \\note            New length can only be smaller than existing one. It has no effect when greater than existing one\n * \\note            This function can be used on single-chain pbufs only, without `next` pbuf in chain\n * \\param[in]       pbuf: Pbuf to make it smaller\n * \\param[in]       new_len: New length in units of bytes\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_pbuf_set_length(lwesp_pbuf_p pbuf, size_t new_len) {\n    if (pbuf == NULL || pbuf->tot_len != pbuf->len || new_len > pbuf->len || new_len == 0 || pbuf->next != NULL) {\n        return 0;\n    }\n\n    /* Works only on single-chain pbuf */\n    pbuf->tot_len = new_len;\n    pbuf->len = new_len;\n\n    return 1;\n}\n\n/**\n * \\brief           Set IP address and port number for received data\n * \\param[in]       pbuf: Packet buffer\n * \\param[in]       ip: IP to assing to packet buffer\n * \\param[in]       port: Port number to assign to packet buffer\n */\nvoid\nlwesp_pbuf_set_ip(lwesp_pbuf_p pbuf, const lwesp_ip_t* ip, lwesp_port_t port) {\n    if (pbuf != NULL && ip != NULL) {\n        LWESP_MEMCPY(&pbuf->ip, ip, sizeof(*ip));\n        pbuf->port = port;\n    }\n}\n\n/**\n * \\brief           Advance pbuf payload pointer by number of len bytes.\n *                  It can only advance single pbuf in a chain\n *\n * \\note            When other pbufs are referencing current one,\n *                  they are not adjusted in length and total length\n *\n * \\param[in]       pbuf: Pbuf to advance\n * \\param[in]       len: Number of bytes to advance.\n *                      when negative is used, buffer size is increased only if it was decreased before\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_pbuf_advance(lwesp_pbuf_p pbuf, int len) {\n    uint8_t process = 0;\n    if (pbuf == NULL || len == 0) {\n        return 0;\n    }\n    if (len > 0) {                      /* When we want to decrease size */\n        if ((size_t)len <= pbuf->len) { /* Is there space to decrease? */\n            process = 1;\n        }\n    } else {\n        /* Is current payload + new len still higher than pbuf structure? */\n        if (((uint8_t*)pbuf + SIZEOF_PBUF_STRUCT) < (pbuf->payload + len)) {\n            process = 1;\n        }\n    }\n    if (process) {\n        pbuf->payload += len; /* Increase payload pointer */\n        pbuf->tot_len -= len; /* Decrease length of pbuf chain */\n        pbuf->len -= len;     /* Decrease length of current pbuf */\n    }\n    return process;\n}\n\n/**\n * \\brief           Skip a list of pbufs for desired offset\n * \\note            Reference is not changed after return and user must not free the memory of new pbuf directly\n * \\param[in]       pbuf: Start of pbuf chain\n * \\param[in]       offset: Offset in units of bytes to skip\n * \\param[out]      new_offset: Pointer to output variable to save new offset in returned pbuf\n * \\return          New pbuf on success, `NULL` otherwise\n */\nlwesp_pbuf_p\nlwesp_pbuf_skip(lwesp_pbuf_p pbuf, size_t offset, size_t* new_offset) {\n    return pbuf_skip(pbuf, offset, new_offset); /* Skip pbufs with internal function */\n}\n\n/**\n * \\brief           Dump and debug pbuf chain\n * \\param[in]       p: Head pbuf to dump\n * \\param[in]       seq: Set to `1` to dump all `pbufs` in linked list or `0` to dump first one only\n */\nvoid\nlwesp_pbuf_dump(lwesp_pbuf_p p, uint8_t seq) {\n    if (p != NULL) {\n        LWESP_DEBUGF(LWESP_CFG_DBG_PBUF | LWESP_DBG_TYPE_TRACE, \"[LWESP PBUF] Dump start: %p\\r\\n\", (void*)p);\n        for (; p != NULL; p = p->next) {\n            LWESP_DEBUGF(LWESP_CFG_DBG_PBUF | LWESP_DBG_TYPE_TRACE,\n                         \"[LWESP PBUF] Dump %p; ref: %u; len: %u; tot_len: %u, next: %p\\r\\n\", (void*)p,\n                         (unsigned)p->ref, (unsigned)p->len, (unsigned)p->tot_len, (void*)p->next);\n            if (!seq) {\n                break;\n            }\n        }\n        LWESP_DEBUGF(LWESP_CFG_DBG_PBUF | LWESP_DBG_TYPE_TRACE, \"[LWESP PBUF] Dump end\\r\\n\");\n    }\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_ping.c",
    "content": "/**\n * \\file            lwesp_ping.c\n * \\brief           Ping API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_ping.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_PING || __DOXYGEN__\n\n/**\n * \\brief           Ping server and get response time from it\n * \\param[in]       host: Host name to ping\n * \\param[out]      time: Pointer to output variable to save ping time in units of milliseconds\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_ping(const char* host, uint32_t* time, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n           const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(host != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_PING;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_ping.host = host;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_ping.time_out = time;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 30000);\n}\n\n#endif /* LWESP_CFG_PING || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_server.c",
    "content": "/**\n * \\file            lwesp.c\n * \\brief           LwESP core file\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_server.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/**\n * \\brief           Enables or disables server mode\n * \\param[in]       en: Set to `1` to enable server, `0` otherwise\n * \\param[in]       port: Port number used to listen on. Must also be used when disabling server mode\n * \\param[in]       max_conn: Number of maximal connections populated by server\n * \\param[in]       timeout: Time used to automatically close the connection in units of seconds.\n *                      Set to `0` to disable timeout feature (not recommended)\n * \\param[in]       server_evt_fn: Connection callback function for new connections started as server\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_set_server(uint8_t en, lwesp_port_t port, uint16_t max_conn, uint16_t timeout, lwesp_evt_fn server_evt_fn,\n                 const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(port > 0);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSERVER;\n    if (en) {\n        LWESP_MSG_VAR_REF(msg).cmd =\n            LWESP_CMD_TCPIP_CIPSERVERMAXCONN; /* First command is to set maximal number of connections for server */\n    }\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_server.en = en;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_server.port = port;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_server.max_conn = max_conn;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_server.timeout = timeout;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_server.cb = server_evt_fn;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_smart.c",
    "content": "/**\n * \\file            lwesp_smart.c\n * \\brief           SMART API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n * Copyright (c) 2020 Seeed Technology\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_smart.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_SMART || __DOXYGEN__\n\n/**\n * \\brief           Configure SMART function on ESP device\n * \\param[in]       en: Set to `1` to start SMART or `0` to stop SMART\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_smart_set_config(uint8_t en, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = en ? LWESP_CMD_WIFI_SMART_START : LWESP_CMD_WIFI_SMART_STOP;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 10000);\n}\n\n#endif /* LWESP_CFG_SMART || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_sntp.c",
    "content": "/**\n * \\file            lwesp_sntp.c\n * \\brief           Connection API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_sntp.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_SNTP || __DOXYGEN__\n\n/**\n * \\brief           Configure SNTP mode parameters.\n * It must be called prior any \\ref lwesp_sntp_gettime can be used,\n * otherwise wrong data will be received back\n * \\param[in]       en: Status whether SNTP mode is enabled or disabled on ESP device\n * \\param[in]       tz: Timezone to use when SNTP acquires time, between `-12` and `14`\n * \\param[in]       h1: Optional first SNTP server for time. Set to `NULL` if not used\n * \\param[in]       h2: Optional second SNTP server for time. Set to `NULL` if not used\n * \\param[in]       h3: Optional third SNTP server for time. Set to `NULL` if not used\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sntp_set_config(uint8_t en, int16_t tz, const char* h1, const char* h2, const char* h3,\n                      const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSNTPCFG;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg.en = en;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg.tz = tz;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg.h1 = h1;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg.h2 = h2;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg.h3 = h3;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get current SNTP configuration.\n * \\todo            Parse response for hostnames, which is not done at the moment\n * \n * \\param[in]       en: Pointer to status variable\n * \\param[in]       tz: Pointer to timezone\n * \\param[in]       h1: Optional first SNTP server for time. Set to `NULL` if not used,\n *                      otherwise value is copied into the pointer. Must be sufficient enough\n * \\param[in]       h2: Optional second SNTP server for time. Set to `NULL` if not used\n *                      otherwise value is copied into the pointer. Must be sufficient enough\n * \\param[in]       h3: Optional third SNTP server for time. Set to `NULL` if not used\n *                      otherwise value is copied into the pointer. Must be sufficient enough\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sntp_get_config(uint8_t* en, int16_t* tz, char* h1, char* h2, char* h3, const lwesp_api_cmd_evt_fn evt_fn,\n                      void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSNTPCFG_GET;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg_get.en = en;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg_get.tz = tz;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg_get.h1 = h1;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg_get.h2 = h2;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_cfg_get.h3 = h3;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Set SNTP synchronization interval on Espressif device\n * SNTP must be configured using \\ref lwesp_sntp_set_config before you can use this function.\n *\n * \\note            This command is not available for all Espressif devices using AT commands\n *                      and will return error when this is the case.\n * \\param[in]       interval: Synchronization interval in units of seconds.\n *                      Value can be set between `15` and `4294967` included\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sntp_set_interval(uint32_t interval, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                        const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(interval >= 15 && interval <= 4294967);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSNTPINTV;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_intv.interval = interval;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get SNTP synchronization interval on Espressif device\n * SNTP must be configured using \\ref lwesp_sntp_set_config before you can use this function.\n *\n * \\note            This command is not available for all Espressif devices using AT commands\n *                      and will return error when this is the case.\n * \\param[in]       interval: Pointer to variable to write interval.\n *                      It is value in seconds. It must not be `NULL`\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sntp_get_interval(uint32_t* interval, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                        const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(interval != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSNTPINTV_GET;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_intv_get.interval = interval;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get time from SNTP servers\n * SNTP must be configured using \\ref lwesp_sntp_set_config before you can use this function\n * \\param[out]      dt: Pointer to struct tm structure to fill with date and time values\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sntp_gettime(struct tm* dt, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_TCPIP_CIPSNTPTIME;\n    LWESP_MSG_VAR_REF(msg).msg.tcpip_sntp_time.dt = dt;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 10000);\n}\n\n#endif /* LWESP_CFG_SNTP || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_sta.c",
    "content": "/**\n * \\file            lwesp_sta.c\n * \\brief           Station API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_sta.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_MODE_STATION || __DOXYGEN__\n\n/**\n * \\brief           Quit (disconnect) from access point\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_quit(const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWQAP;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Join as station to access point\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\param[in]       name: SSID of access point to connect to\n * \\param[in]       pass: Password of access point. Use `NULL` if AP does not have password\n * \\param[in]       mac: Pointer to MAC address of AP.\n *                      If multiple APs with same name exist, MAC may help to select proper one.\n *                      Set to `NULL` if not needed\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_join(const char* name, const char* pass, const lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn,\n               void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(name != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWJAP;\n    LWESP_MSG_VAR_REF(msg).msg.sta_join.name = name;\n    LWESP_MSG_VAR_REF(msg).msg.sta_join.pass = pass;\n    LWESP_MSG_VAR_REF(msg).msg.sta_join.mac = mac;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 30000);\n}\n\n/**\n * \\brief           Configure auto join to access point on startup\n * \\note            For auto join feature, you need to do a join to access point with default mode.\n *                  Check \\ref lwesp_sta_join for more information\n * \\param[in]       en: Set to `1` to enable or `0` to disable\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_autojoin(uint8_t en, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWAUTOCONN;\n    LWESP_MSG_VAR_REF(msg).msg.sta_autojoin.en = en;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 30000);\n}\n\n/**\n * \\brief           Set reconnect interval and maximum tries when connection drops\n * \\param[in]       interval: Interval in units of seconds. Valid numbers are `1-7200` or `0` to disable reconnect feature\n * \\param[in]       rep_cnt: Repeat counter. Number of maximum tries for reconnect.\n *                      Valid entries are `1-1000` or `0` to always try.\n *                      This parameter is only valid if interval is not `0`\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_reconnect_set_config(uint16_t interval, uint16_t rep_cnt, const lwesp_api_cmd_evt_fn evt_fn,\n                               void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(interval <= 7200);\n    LWESP_ASSERT(rep_cnt <= 1000);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWRECONNCFG;\n    LWESP_MSG_VAR_REF(msg).msg.sta_reconn_set.interval = interval;\n    LWESP_MSG_VAR_REF(msg).msg.sta_reconn_set.rep_cnt = rep_cnt;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get current access point information (name, mac, channel, rssi)\n * \\note            Access point station is currently connected to\n * \\param[in]       info: Pointer to connected access point information\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_get_ap_info(lwesp_sta_info_ap_t* info, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                      const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    if (!lwesp_sta_is_joined()) {\n        return lwespERRWIFINOTCONNECTED;\n    }\n    LWESP_ASSERT(info != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWJAP_GET;\n    LWESP_MSG_VAR_REF(msg).msg.sta_info_ap.info = info;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get station IP address\n * \\param[out]      ip: Pointer to variable to save IP address\n * \\param[out]      gw: Pointer to output variable to save gateway address\n * \\param[out]      nm: Pointer to output variable to save netmask address\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_getip(lwesp_ip_t* ip, lwesp_ip_t* gw, lwesp_ip_t* nm, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CIPSTA_GET;\n    LWESP_MSG_VAR_REF(msg).cmd = LWESP_CMD_WIFI_CWDHCP_GET;\n    LWESP_MSG_VAR_REF(msg).msg.sta_ap_getip.ip = ip;\n    LWESP_MSG_VAR_REF(msg).msg.sta_ap_getip.gw = gw;\n    LWESP_MSG_VAR_REF(msg).msg.sta_ap_getip.nm = nm;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Set station IP address\n *\n * Application may manually set IP address.\n * When this happens, stack will check for DHCP settings and will read actual IP address from device.\n * Once procedure is finished, \\ref LWESP_EVT_WIFI_IP_ACQUIRED event will be sent to application where\n * user may read the actual new IP and DHCP settings.\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\note            DHCP is automatically disabled when using static IP address\n *\n * \\param[in]       ip: Pointer to IP address\n * \\param[in]       gw: Pointer to gateway address. Set to `NULL` to use default gateway\n * \\param[in]       nm: Pointer to netmask address. Set to `NULL` to use default netmask\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_setip(const lwesp_ip_t* ip, const lwesp_ip_t* gw, const lwesp_ip_t* nm, const lwesp_api_cmd_evt_fn evt_fn,\n                void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(ip != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CIPSTA_SET;\n    LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.sta_ap_setip.ip, ip, sizeof(*ip));\n    LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.sta_ap_setip.gw, gw, sizeof(*gw));\n    LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.sta_ap_setip.nm, nm, sizeof(*nm));\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Get station MAC address\n * \\param[out]      mac: Pointer to output variable to save MAC address\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_getmac(lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CIPSTAMAC_GET;\n    LWESP_MSG_VAR_REF(msg).msg.sta_ap_getmac.mac = mac;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Set station MAC address\n *\n * Configuration changes will be saved in the NVS area of ESP device.\n *\n * \\param[in]       mac: Pointer to variable with MAC address\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_setmac(const lwesp_mac_t* mac, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                 const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(mac != NULL);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CIPSTAMAC_SET;\n    LWESP_MEMCPY(&LWESP_MSG_VAR_REF(msg).msg.sta_ap_setmac.mac, mac, sizeof(*mac));\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n/**\n * \\brief           Check if ESP got IP from access point\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_sta_has_ip(void) {\n    uint8_t res;\n    lwesp_core_lock();\n    res = LWESP_U8(esp.m.sta.f.has_ip);\n    lwesp_core_unlock();\n    return res;\n}\n\n#if LWESP_CFG_IPV6 || __DOXYGEN__\n\n/**\n * \\brief           Check if station has local IPV6 IP\n * Local IP is used between station and router\n * \\note            Defined as macro with `0` constant if \\ref LWESP_CFG_IPV6 is disabled\n * \\return          `1` if local IPv6 is available, `0` otherwise\n */\nuint8_t\nlwesp_sta_has_ipv6_local(void) {\n    uint8_t res;\n    lwesp_core_lock();\n    res = LWESP_U8(esp.m.sta.f.has_ipv6_ll);\n    lwesp_core_unlock();\n    return res;\n}\n\n/**\n * \\brief           Check if station has global IPV6 IP\n * Global IP is used router and outside network\n * \\note            Defined as macro with `0` constant if \\ref LWESP_CFG_IPV6 is disabled\n * \\return          `1` if global IPv6 is available, `0` otherwise\n */\nuint8_t\nlwesp_sta_has_ipv6_global(void) {\n    uint8_t res;\n    lwesp_core_lock();\n    res = LWESP_U8(esp.m.sta.f.has_ipv6_gl);\n    lwesp_core_unlock();\n    return res;\n}\n\n#endif /* LWESP_CFG_IPV6 || __DOXYGEN__ */\n\n/**\n * \\brief           Check if station is connected to WiFi network\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_sta_is_joined(void) {\n    return lwesp_sta_has_ip();\n}\n\n/**\n * \\brief           Copy IP address from internal value to user variable\n * \\note            Use \\ref lwesp_sta_getip to refresh actual IP value from device\n * \\param[out]      ip: Pointer to output IP variable. Set to `NULL` if not interested in IP address\n * \\param[out]      gw: Pointer to output gateway variable. Set to `NULL` if not interested in gateway address\n * \\param[out]      nm: Pointer to output netmask variable. Set to `NULL` if not interested in netmask address\n * \\param[out]      is_dhcp: Pointer to output DHCP status variable. Set to `NULL` if not interested\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_copy_ip(lwesp_ip_t* ip, lwesp_ip_t* gw, lwesp_ip_t* nm, uint8_t* is_dhcp) {\n    lwespr_t res = lwespERR;\n    if ((ip != NULL || gw != NULL || nm != NULL || is_dhcp != NULL)\n        && lwesp_sta_has_ip()) { /* Do we have a valid IP address? */\n        lwesp_core_lock();\n        if (ip != NULL) {\n            LWESP_MEMCPY(ip, &esp.m.sta.ip, sizeof(esp.m.sta.ip));\n        }\n        if (gw != NULL) {\n            LWESP_MEMCPY(gw, &esp.m.sta.gw, sizeof(esp.m.sta.gw));\n        }\n        if (nm != NULL) {\n            LWESP_MEMCPY(nm, &esp.m.sta.nm, sizeof(esp.m.sta.nm));\n        }\n        if (is_dhcp != NULL) {\n            *is_dhcp = esp.m.sta.dhcp;\n        }\n        res = lwespOK;\n        lwesp_core_unlock();\n    }\n    return res;\n}\n\n/**\n * \\brief           List for available access points ESP can connect to\n * \\param[in]       ssid: Optional SSID name to search for. Set to `NULL` to disable filter\n * \\param[in]       aps: Pointer to array of available access point parameters\n * \\param[in]       apsl: Length of aps array\n * \\param[out]      apf: Pointer to output variable to save number of access points found\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_sta_list_ap(const char* ssid, lwesp_ap_t* aps, size_t apsl, size_t* apf, const lwesp_api_cmd_evt_fn evt_fn,\n                  void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    if (apf != NULL) {\n        *apf = 0;\n    }\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_CWLAP;\n    LWESP_MSG_VAR_REF(msg).msg.ap_list.ssid = ssid;\n    LWESP_MSG_VAR_REF(msg).msg.ap_list.aps = aps;\n    LWESP_MSG_VAR_REF(msg).msg.ap_list.apsl = apsl;\n    LWESP_MSG_VAR_REF(msg).msg.ap_list.apf = apf;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 30000);\n}\n\n/**\n * \\brief           Check if access point is `802.11b` compatible\n * \\param[in]       ap: Access point detailes acquired by \\ref lwesp_sta_list_ap\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_sta_is_ap_802_11b(lwesp_ap_t* ap) {\n    return LWESP_U8((ap->bgn & 0x01) == 0x01); /* Bit 0 is for b check */\n}\n\n/**\n * \\brief           Check if access point is `802.11g` compatible\n * \\param[in]       ap: Access point detailes acquired by \\ref lwesp_sta_list_ap\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_sta_is_ap_802_11g(lwesp_ap_t* ap) {\n    return LWESP_U8((ap->bgn & 0x02) == 0x02); /* Bit 1 is for g check */\n}\n\n/**\n * \\brief           Check if access point is `802.11n` compatible\n * \\param[in]       ap: Access point detailes acquired by \\ref lwesp_sta_list_ap\n * \\return          `1` on success, `0` otherwise\n */\nuint8_t\nlwesp_sta_is_ap_802_11n(lwesp_ap_t* ap) {\n    return LWESP_U8((ap->bgn & 0x04) == 0x04); /* Bit 2 is for n check */\n}\n\n#endif /* LWESP_CFG_MODE_STATION || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_threads.c",
    "content": "/**\n * \\file            lwesp_threads.c\n * \\brief           OS threads implementations\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_threads.h\"\n#include \"lwesp/lwesp_int.h\"\n#include \"lwesp/lwesp_private.h\"\n#include \"lwesp/lwesp_timeout.h\"\n#include \"system/lwesp_sys.h\"\n\n/**\n * \\brief           User thread to process input packets from API functions\n * \\param[in]       arg: User argument. Semaphore to release when thread starts\n */\nvoid\nlwesp_thread_produce(void* const arg) {\n    lwesp_sys_sem_t* sem = arg;\n    lwesp_t* e = &esp;\n    lwesp_msg_t* msg;\n    lwespr_t res;\n    uint32_t time;\n\n    LWESP_DEBUGF(LWESP_CFG_DBG_THREAD | LWESP_DBG_TYPE_TRACE, \"[LWESP THREAD] Producer thread started\\r\\n\");\n\n    /*\n     * Thread parameter is semaphore handle object\n     *\n     * Semaphore must be released, indicating thread successful startup\n     */\n    if (lwesp_sys_sem_isvalid(sem)) {\n        lwesp_sys_sem_release(sem);\n    }\n\n    lwesp_core_lock();\n    while (1) {\n        lwesp_core_unlock();\n        do {\n            time = lwesp_sys_mbox_get(&e->mbox_producer, (void**)&msg, 0); /* Get message from queue */\n        } while (time == LWESP_SYS_TIMEOUT || msg == NULL);\n        LWESP_THREAD_PRODUCER_HOOK(); /* Execute producer thread hook */\n        lwesp_core_lock();\n\n        res = lwespOK; /* Start with OK */\n        e->msg = msg;  /* Set message handle */\n\n        /*\n         * This check is performed when adding command to queue\n         * Do it again here to prevent long timeouts,\n         * if device present flag changes\n         */\n        if (!e->status.f.dev_present) {\n            LWESP_DEBUGF(LWESP_CFG_DBG_THREAD | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_WARNING,\n                         \"[LWESP THREAD] Device is not present\\r\\n\");\n            res = lwespERRNODEVICE;\n        }\n\n        /* For reset message, we can have delay! */\n        if (res == lwespOK && msg->cmd_def == LWESP_CMD_RESET) {\n            if (msg->msg.reset.delay > 0) {\n                lwesp_delay(msg->msg.reset.delay);\n            }\n            lwespi_reset_everything(1); /* Reset stack before trying to reset */\n        }\n\n        /*\n         * Try to call function to process this message\n         * Usually it should be function to transmit data to AT port\n         */\n        if (res == lwespOK && msg->fn != NULL) { /* Check for callback processing function */\n            /*\n             * Obtain semaphore\n             * This code should not block at any point.\n             * If it blocks, severe problems occurred and program should\n             * immediate terminate\n             */\n            lwesp_core_unlock();\n            lwesp_sys_sem_wait(&e->sem_sync, 0); /* First call */\n            lwesp_core_lock();\n            res = msg->fn(msg);        /* Process this message, check if command started at least */\n            time = ~LWESP_SYS_TIMEOUT; /* Reset time */\n            if (res == lwespOK) {      /* We have valid data and data were sent */\n                lwesp_core_unlock();\n                time = lwesp_sys_sem_wait(\n                    &e->sem_sync,\n                    msg->block_time); /* Second call; Wait for synchronization semaphore from processing thread or timeout */\n                lwesp_core_lock();\n                if (time == LWESP_SYS_TIMEOUT) { /* Sync timeout occurred? */\n                    res = lwespTIMEOUT;          /* Timeout on command */\n                }\n            }\n\n            /* Notify application on command timeout */\n            if (res == lwespTIMEOUT) {\n                lwespi_send_cb(LWESP_EVT_CMD_TIMEOUT);\n            }\n\n            LWESP_DEBUGW(\n                LWESP_CFG_DBG_THREAD | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_SEVERE, res == lwespTIMEOUT,\n                \"[LWESP THREAD] Timeout in produce thread waiting for command to finish in process thread\\r\\n\");\n            LWESP_DEBUGW(LWESP_CFG_DBG_THREAD | LWESP_DBG_TYPE_TRACE | LWESP_DBG_LVL_SEVERE,\n                         res != lwespOK && res != lwespTIMEOUT,\n                         \"[LWESP THREAD] Could not start execution for command %d\\r\\n\", (int)msg->cmd);\n\n            /*\n             * Manually release semaphore in all cases:\n             *\n             * Case 1: msg->fn function fails, command did not start,\n             *           application needs to release previously acquired semaphore\n             * Case 2: If time == TIMEOUT, acquiring on second call was not successful,\n             *           application has to manually release semaphore, taken on first call\n             * Case 3: If time != TIMEOUT, acquiring on second call was successful,\n             *           which effectively means that another thread successfully released semaphore,\n             *           application has to release semaphore, now taken on second call\n             *\n             * If application would not manually release semaphore,\n             * and if command would return with timeout (or fail),\n             * it would not be possible to start a new command after,\n             * because semaphore would be still locked\n             */\n            lwesp_sys_sem_release(&e->sem_sync);\n        } else {\n            if (res == lwespOK) {\n                res = lwespERR; /* Simply set error message */\n            }\n        }\n        if (res != lwespOK) {\n            /* Process global callbacks */\n            lwespi_process_events_for_timeout_or_error(msg, res);\n\n            msg->res = res; /* Save response */\n        }\n\n#if LWESP_CFG_USE_API_FUNC_EVT\n        /* Send event function to user */\n        if (msg->evt_fn != NULL) {\n            msg->evt_fn(msg->res, msg->evt_arg); /* Send event with user argument */\n        }\n#endif /* LWESP_CFG_USE_API_FUNC_EVT */\n\n        /*\n         * In case message is blocking,\n         * release semaphore and notify finished with processing\n         * otherwise directly free memory of message structure\n         */\n        if (msg->is_blocking) {\n            lwesp_sys_sem_release(&msg->sem);\n        } else {\n            LWESP_MSG_VAR_FREE(msg);\n        }\n        e->msg = NULL;\n    }\n}\n\n/**\n * \\brief           Thread for processing received data from device\n *\n *                  This thread is also used to handle timeout events\n *                  in correct time order as it is never blocked by user command\n *\n * \\param[in]       arg: User argument. Semaphore to release when thread starts\n * \\sa              LWESP_CFG_INPUT_USE_PROCESS\n */\nvoid\nlwesp_thread_process(void* const arg) {\n    lwesp_sys_sem_t* sem = arg;\n    lwesp_t* e = &esp;\n    lwesp_msg_t* msg;\n    uint32_t time;\n\n    LWESP_DEBUGF(LWESP_CFG_DBG_THREAD | LWESP_DBG_TYPE_TRACE, \"[LWESP THREAD] Process thread started\\r\\n\");\n\n    /*\n     * Thread parameter is semaphore handle object\n     *\n     * Semaphore must be released, indicating thread successful startup\n     */\n    if (lwesp_sys_sem_isvalid(sem)) {\n        lwesp_sys_sem_release(sem);\n    }\n\n#if !LWESP_CFG_INPUT_USE_PROCESS\n    lwesp_core_lock();\n    while (1) {\n        lwesp_core_unlock();\n        time = lwespi_get_from_mbox_with_timeout_checks(&e->mbox_process, (void**)&msg, 10);\n        LWESP_THREAD_PROCESS_HOOK(); /* Execute process thread hook */\n        lwesp_core_lock();\n\n        if (time == LWESP_SYS_TIMEOUT || msg == NULL) {\n            LWESP_UNUSED(time); /* Unused variable */\n        }\n        lwespi_process_buffer(); /* Process input data */\n#else                            /* LWESP_CFG_INPUT_USE_PROCESS */\n    while (1) {\n        /*\n         * Check for next timeout event only here\n         *\n         * If there are no timeouts to process, we can wait unlimited time.\n         * In case new timeout occurs, thread will wake up by writing new element to mbox process queue\n         */\n        time = lwespi_get_from_mbox_with_timeout_checks(&e->mbox_process, (void**)&msg, 0);\n        LWESP_THREAD_PROCESS_HOOK(); /* Execute process thread hook */\n        LWESP_UNUSED(time);\n#endif                           /* !LWESP_CFG_INPUT_USE_PROCESS */\n    }\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_timeout.c",
    "content": "/**\n * \\file            lwesp_timeout.c\n * \\brief           Timeout manager\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_timeout.h\"\n#include \"lwesp/lwesp_private.h\"\n\nstatic lwesp_timeout_t* first_timeout;\nstatic uint32_t last_timeout_time;\n\n/**\n * \\brief           Get time we have to wait before we can process next timeout\n * \\return          Time in units of milliseconds to wait\n */\nstatic uint32_t\nget_next_timeout_diff(void) {\n    uint32_t diff;\n    if (first_timeout == NULL) {\n        return 0xFFFFFFFF;\n    }\n    diff = lwesp_sys_now() - last_timeout_time; /* Get difference between current time and last process time */\n    if (diff >= first_timeout->time) {          /* Are we over already? */\n        return 0;                               /* We have to immediately process this timeout */\n    }\n    return first_timeout->time - diff; /* Return remaining time for sleep */\n}\n\n/**\n * \\brief           Process next timeout in a linked list\n */\nstatic void\nprocess_next_timeout(void) {\n    uint32_t time;\n\n    time = lwesp_sys_now();\n\n    /*\n     * Before calling timeout callback, update variable\n     * to make sure we have correct timing in case\n     * callback creates timeout value again\n     */\n    last_timeout_time = time; /* Reset variable when we were last processed */\n\n    if (first_timeout != NULL) {\n        lwesp_timeout_t* to = first_timeout;\n\n        /*\n         * Before calling callback remove current timeout from list\n         * to make sure we are safe in case callback function\n         * adds a new timeout entry to list\n         */\n        first_timeout = first_timeout->next; /* Set next timeout on a list as first timeout */\n        to->fn(to->arg);                     /* Call user callback function */\n        lwesp_mem_free_s((void**)&to);\n    }\n}\n\n/**\n * \\brief           Get next entry from message queue\n * \\param[in]       b: Pointer to message queue to get element\n * \\param[out]      m: Pointer to pointer to output variable\n * \\param[in]       timeout: Maximal time to wait for message (0 = wait until message received)\n * \\return          Time in milliseconds required for next message\n */\nuint32_t\nlwespi_get_from_mbox_with_timeout_checks(lwesp_sys_mbox_t* b, void** m, uint32_t timeout) {\n    uint32_t wait_time;\n    do {\n        if (first_timeout == NULL) {                  /* We have no timeouts ready? */\n            return lwesp_sys_mbox_get(b, m, timeout); /* Get entry from message queue */\n        }\n        wait_time = get_next_timeout_diff(); /* Get time to wait for next timeout execution */\n        if (wait_time == 0 || lwesp_sys_mbox_get(b, m, wait_time) == LWESP_SYS_TIMEOUT) {\n            lwesp_core_lock();\n            process_next_timeout(); /* Process with next timeout */\n            lwesp_core_unlock();\n        }\n        break;\n    } while (1);\n    return wait_time;\n}\n\n/**\n * \\brief           Add new timeout to processing list\n * \\param[in]       time: Time in units of milliseconds for timeout execution\n * \\param[in]       fn: Callback function to call when timeout expires\n * \\param[in]       arg: Pointer to user specific argument to call when timeout callback function is executed\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_timeout_add(uint32_t time, lwesp_timeout_fn fn, void* arg) {\n    lwesp_timeout_t* to;\n    uint32_t now;\n\n    LWESP_ASSERT(fn != NULL);\n\n    /* Allocate memory for timeout structure */\n    if ((to = lwesp_mem_calloc(1, sizeof(*to))) == NULL) {\n        return lwespERRMEM;\n    }\n\n    lwesp_core_lock();\n    now = lwesp_sys_now(); /* Get current time */\n    if (first_timeout != NULL) {\n        /*\n         * Since we want timeout value to start from NOW,\n         * we have to add time when we last processed our timeouts\n         */\n        time += now - last_timeout_time; /* Add difference between now and last processed time */\n    }\n    to->time = time;\n    to->arg = arg;\n    to->fn = fn;\n\n    /*\n     * Add new timeout to proper place on linked list\n     * and align times to have correct values between timeouts\n     */\n    if (first_timeout == NULL) {\n        first_timeout = to;      /* Set as first element */\n        last_timeout_time = now; /* Reset last timeout time to current time */\n    } else {                     /* Find where to place a new timeout */\n        /*\n         * First check if we have to put new timeout\n         * to beginning of linked list.\n         * In this case just align new value for current first element\n         */\n        if (first_timeout->time > to->time) {\n            first_timeout->time -= time; /* Decrease first timeout value to match difference */\n            to->next = first_timeout;    /* Set first timeout as next of new one */\n            first_timeout = to;          /* Set new timeout as first */\n        } else {                         /* Go somewhere in between current list */\n            for (lwesp_timeout_t* t = first_timeout; t != NULL; t = t->next) {\n                to->time -= t->time; /* Decrease new timeout time by time in a linked list */\n                /*\n                 * Enter between 2 entries on a list in case:\n                 *\n                 * - We reached end of linked list\n                 * - Our time is less than diff between 2 entries in list\n                 */\n                if (t->next == NULL || t->next->time > to->time) {\n                    if (t->next != NULL) {         /* Check if there is next element */\n                        t->next->time -= to->time; /* Decrease difference time to next one */\n                    } else if (to->time > time) {  /* Overflow of time check */\n                        to->time = time + first_timeout->time;\n                    }\n                    to->next = t->next; /* Change order of elements */\n                    t->next = to;       /* Add new element to linked list */\n                    break;\n                }\n            }\n        }\n    }\n    lwesp_core_unlock();\n    lwesp_sys_mbox_putnow(&esp.mbox_process,\n                          NULL); /* Write message to process queue to wakeup process thread and to start */\n    return lwespOK;\n}\n\n/**\n * \\brief           Remove callback from timeout list\n * \\param[in]       fn: Callback function to identify timeout to remove\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_timeout_remove(lwesp_timeout_fn fn) {\n    uint8_t success = 0;\n\n    lwesp_core_lock();\n    for (lwesp_timeout_t *t = first_timeout, *t_prev = NULL; t != NULL;\n         t_prev = t, t = t->next) { /* Check all entries */\n        if (t->fn == fn) {          /* Do we have a match from callback point of view? */\n\n            /*\n             * We have to first increase\n             * difference time between current and next one\n             * to be aligned for correct wait time\n             */\n            if (t->next != NULL) {        /* Do we have next element? */\n                t->next->time += t->time; /* Increase timeout time for next element */\n            }\n\n            /*\n             * In case we have previous element on a list,\n             * set next element of previous to next of current one\n             * otherwise we were first element so simply set\n             * next of current as first one\n             */\n            if (t_prev != NULL) {\n                t_prev->next = t->next;\n            } else {\n                first_timeout = t->next;\n            }\n            lwesp_mem_free_s((void**)&t);\n            success = 1;\n            break;\n        }\n    }\n    lwesp_core_unlock();\n    return success ? lwespOK : lwespERR;\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_unicode.c",
    "content": "/**\n * \\file            lwesp_unicode.c\n * \\brief           Unicode support\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_unicode.h\"\n#include \"lwesp/lwesp_private.h\"\n\n/**\n * \\brief           Decode single character for unicode (UTF-8 only) format\n * \\param[in,out]   s: Pointer to unicode decode control structure\n * \\param[in]       c: UTF-8 character sequence to test for device\n * \\return          \\ref lwespOK Function succedded, there is a valid UTF-8 sequence\n * \\return          \\ref lwespINPROG Function continues well but expects some more data to finish sequence\n * \\return          \\ref lwespERR Error in UTF-8 sequence\n */\nlwespr_t\nlwespi_unicode_decode(lwesp_unicode_t* s, uint8_t c) {\n    if (s->r == 0) {    /* Are we expecting a first character? */\n        s->t = 0;       /* Reset sequence */\n        s->ch[0] = c;   /* Save current character */\n        if (c < 0x80) { /* One byte only in UTF-8 representation */\n            s->r = 0;   /* Remaining bytes */\n            s->t = 1;\n            return lwespOK;\n        }\n        if ((c & 0xE0) == 0xC0) { /* 1 additional byte in a row = 110x xxxx */\n            s->r = 1;\n        } else if ((c & 0xF0) == 0xE0) { /* 2 additional bytes in a row = 1110 xxxx */\n            s->r = 2;\n        } else if ((c & 0xF8) == 0xF0) { /* 3 additional bytes in a row = 1111 0xxx */\n            s->r = 3;\n        } else {\n            return lwespERR; /* Error parsing unicode byte */\n        }\n        s->t = s->r + 1;             /* Number of bytes is 1 byte more than remaining in sequence */\n        return lwespINPROG;          /* Return in progress status */\n    } else if ((c & 0xC0) == 0x80) { /* Next character in sequence */\n        --s->r;                      /* Decrease character */\n        s->ch[s->t - s->r - 1] = c;  /* Save character to array */\n        if (s->r == 0) {             /* Did we finish? */\n            return lwespOK;          /* Return OK, we are ready to proceed */\n        }\n        return lwespINPROG; /* Still in progress */\n    }\n    return lwespERR; /* An error, unknown UTF-8 character entered */\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_utils.c",
    "content": "/**\n * \\file            lwesp_utils.c\n * \\brief           Utilities\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include <stdint.h>\n#include \"lwesp/lwesp_private.h\"\n#include \"lwesp/lwesp_utils.h\"\n\n/**\n * \\brief           Convert `unsigned 32-bit` number to string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\param[in]       is_hex: Set to `1` to output hex, 0 otherwise\n * \\param[in]       width: Width of output string.\n *                      When number is shorter than width, leading `0` characters will apply.\n *                      This parameter is valid only when formatting hex numbers\n * \\return          Pointer to output variable\n */\nchar*\nlwesp_u32_to_gen_str(uint32_t num, char* out, uint8_t is_hex, uint8_t width) {\n    char* tmp = out;\n    uint8_t i, y;\n\n    /* Convert number to string */\n    i = 0;\n    tmp[0] = '0';\n    if (num == 0) {\n        ++i;\n    } else {\n        if (is_hex) {\n            uint8_t mod;\n            while (num > 0) {\n                mod = num & 0x0F;\n                if (mod < 10) {\n                    tmp[i] = mod + '0';\n                } else {\n                    tmp[i] = mod - 10 + 'A';\n                }\n                num >>= 4;\n                ++i;\n            }\n        } else {\n            while (num > 0) {\n                tmp[i] = (num % 10) + '0';\n                num /= 10;\n                ++i;\n            }\n        }\n    }\n    if (is_hex) {\n        while (i < width) {\n            tmp[i] = '0';\n            ++i;\n        }\n    }\n    tmp[i] = 0;\n\n    /* Rotate string */\n    y = 0;\n    while (y < ((i + 1) / 2)) {\n        char t = out[i - y - 1];\n        out[i - y - 1] = tmp[y];\n        tmp[y] = t;\n        ++y;\n    }\n    out[i] = 0;\n    return out;\n}\n\n/**\n * \\brief           Convert `signed 32-bit` number to string\n * \\param[in]       num: Number to convert\n * \\param[out]      out: Output variable to save string\n * \\return          Pointer to output variable\n */\nchar*\nlwesp_i32_to_gen_str(int32_t num, char* out) {\n    if (num < 0) {\n        *out = '-';\n        ++out;\n        return lwesp_u32_to_gen_str(LWESP_U32(-num), out, 0, 0) - 1;\n    } else {\n        return lwesp_u32_to_gen_str(LWESP_U32(num), out, 0, 0);\n    }\n}\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_webserver.c",
    "content": "/**\n * \\file            lwesp_webserver.c\n * \\brief           Web Server API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Neo Xiong <xiongyu0523@gmail.com>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_webserver.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_WEBSERVER || __DOXYGEN__\n\n/**\n * \\brief           Enables or disables Web Server\n * \\param[in]       en: Set to `1` to enable web server, `0` to disable web server.\n * \\param[in]       port: The web server port number.\n * \\param[in]       timeout: The timeout for the every connection. Unit: second. Range:[21,60].\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_set_webserver(uint8_t en, lwesp_port_t port, uint16_t timeout, const lwesp_api_cmd_evt_fn evt_fn,\n                    void* const evt_arg, const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    LWESP_ASSERT(port > 0);\n\n    if (timeout < 21) {\n        timeout = 21;\n    } else if (timeout > 60) {\n        timeout = 60;\n    }\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WEBSERVER;\n    LWESP_MSG_VAR_REF(msg).msg.web_server.en = en;\n    LWESP_MSG_VAR_REF(msg).msg.web_server.port = port;\n    LWESP_MSG_VAR_REF(msg).msg.web_server.timeout = timeout;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 1000);\n}\n\n#endif /* LWESP_CFG_PING || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/lwesp/lwesp_wps.c",
    "content": "/**\n * \\file            lwesp_wps.c\n * \\brief           WPS API\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_wps.h\"\n#include \"lwesp/lwesp_private.h\"\n\n#if LWESP_CFG_WPS || __DOXYGEN__\n\n/**\n * \\brief           Configure WPS function on ESP device\n * \\note            WPS does not support WEP encryption\n * \\param[in]       en: Set to `1` to enable WPS or `0` to disable WPS\n * \\param[in]       min_ecn: Minimum security level ESP will look for.\n *                      It will not connect to the level below selected parameter\n * \\param[in]       evt_fn: Callback function called when command has finished. Set to `NULL` when not used\n * \\param[in]       evt_arg: Custom argument for event callback function\n * \\param[in]       blocking: Status whether command should be blocking or not\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nlwesp_wps_set_config(uint8_t en, lwesp_ecn_t min_ecn, const lwesp_api_cmd_evt_fn evt_fn, void* const evt_arg,\n                     const uint32_t blocking) {\n    LWESP_MSG_VAR_DEFINE(msg);\n\n    /* Check valid entries */\n    LWESP_ASSERT(min_ecn <= LWESP_ECN_WPA2_WPA3_PSK);\n\n    LWESP_MSG_VAR_ALLOC(msg, blocking);\n    LWESP_MSG_VAR_SET_EVT(msg, evt_fn, evt_arg);\n    LWESP_MSG_VAR_REF(msg).cmd_def = LWESP_CMD_WIFI_WPS;\n    LWESP_MSG_VAR_REF(msg).msg.wps_cfg.en = en;\n    LWESP_MSG_VAR_REF(msg).msg.wps_cfg.min_ecn = min_ecn;\n\n    return lwespi_send_msg_to_producer_mbox(&LWESP_MSG_VAR_REF(msg), lwespi_initiate_cmd, 10000);\n}\n\n#endif /* LWESP_CFG_WPS || __DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_posix.c",
    "content": "/**\n * \\file            lwesp_ll_posix.c\n * \\brief           Low-level communication with ESP device for WIN32\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          imi415 <imi415.public@gmail.com>\n * Version:         v1.1.2-dev\n */\n\n#include <fcntl.h>\n#include <stdio.h>\n#include <termios.h>\n#include <unistd.h>\n\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_input.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"system/lwesp_ll.h\"\n\n#if !__DOXYGEN__\n\nstatic uint8_t initialized = 0;\n\nstatic int uart_fd;\n\n#define LOG_BUFFER_LEN 4096\n\nstatic uint32_t data_buffer_ptr = 0;\nstatic uint8_t data_buffer[LOG_BUFFER_LEN];\n\nstatic lwesp_sys_thread_t uart_thread_handle;\n\nstatic void uart_thread(void* param);\n\n#define UART_FILE \"/dev/ttyUSB0\"\n\nstatic size_t\nsend_data(const void* data, size_t len) {\n    if (uart_fd <= 0) {\n        return 0;\n    }\n    int ret = write(uart_fd, data, len);\n    return ret;\n}\n\nstatic void\nconfigure_uart(uint32_t baudrate) {\n    if (!initialized) {\n        uart_fd = open(UART_FILE, O_RDWR);\n        if (uart_fd < 0) {\n            fprintf(stderr, \"Open serial device failed\\n\");\n            return;\n        }\n    }\n\n    /* Set UART parameters here. */\n    struct termios tio;\n    if (tcgetattr(uart_fd, &tio) != 0) {\n        fprintf(stderr, \"Get serial attr failed.\\n\");\n        return;\n    }\n\n    /* Only common baud rates are added. */\n    int tio_baudrate;\n    switch (baudrate) {\n        case 9600: tio_baudrate = B9600; break;\n        case 38400: tio_baudrate = B38400; break;\n        case 57600: tio_baudrate = B57600; break;\n        case 115200: tio_baudrate = B115200; break;\n        case 921600: tio_baudrate = B921600; break;\n        default: tio_baudrate = B115200; break;\n    }\n\n    cfsetispeed(&tio, tio_baudrate);\n    cfsetospeed(&tio, tio_baudrate);\n\n    tio.c_cflag = (tio.c_cflag & ~CSIZE) | CS8;\n    tio.c_iflag &= ~IGNBRK;\n    tio.c_oflag &= ~OPOST;\n\n    tio.c_cc[VMIN] = 1;\n    tio.c_cc[VTIME] = 10;\n\n    tio.c_iflag &= ~(IXON | IXOFF | IXANY);\n    tio.c_iflag &= ~(ICANON | ECHO | ECHOE | ISIG);\n    tio.c_cflag |= (CLOCAL | CREAD);\n    tio.c_cflag &= ~(PARENB | PARODD);\n    tio.c_cflag &= ~CSTOPB;\n\n    tio.c_cflag &= ~CRTSCTS;      /* Without hardware flow control */\n    /* tio.c_cflag |= CRTSCTS; */ /* With hardware flow control */\n\n    cfmakeraw(&tio);\n\n    if (tcsetattr(uart_fd, TCSANOW, &tio) != 0) {\n        fprintf(stderr, \"Set serial attr failed.\\n\");\n        return;\n    }\n\n    tcflush(uart_fd, TCIOFLUSH);\n\n    /* On first function call, create a thread to read data from COM port */\n    if (!initialized) {\n        lwesp_sys_thread_create(&uart_thread_handle, \"lwesp_ll_thread\", uart_thread, NULL, 0, 0);\n    }\n}\n\nstatic void\nlog_command(uint8_t new_byte) {\n    /* Log buffer not full */\n    if (data_buffer_ptr < LOG_BUFFER_LEN - 1) {\n        data_buffer[data_buffer_ptr] = new_byte;\n        data_buffer_ptr++;\n    }\n\n    if (data_buffer_ptr > 0 && data_buffer[data_buffer_ptr - 1] == '\\n') {\n        data_buffer[data_buffer_ptr] = '\\0';\n\n        fprintf(stderr, \"[AT <]: \\e[32m%s\\e[0m\", data_buffer);\n        data_buffer_ptr = 0;\n    }\n}\n\nstatic void\nuart_thread(void* param) {\n    uint8_t data_byte;\n    for (;;) {\n        if (read(uart_fd, &data_byte, 1) > 0) {\n            log_command(data_byte);\n            /* Send received data to input processing module */\n#if LWESP_CFG_INPUT_USE_PROCESS\n            lwesp_input_process(&data_byte, 1);\n#else  /* LWESP_CFG_INPUT_USE_PROCESS */\n            lwesp_input(data_byte, 1);\n#endif /* LWESP_CFG_INPUT_USE_PROCESS */\n        }\n    }\n}\n\nstatic uint8_t\nreset_device(uint8_t state) {\n    return 0;\n}\n\nlwespr_t\nlwesp_ll_init(lwesp_ll_t* ll) {\n#if !LWESP_CFG_MEM_CUSTOM\n    /* Step 1: Configure memory for dynamic allocations */\n    static uint8_t memory[0x10000]; /* Create memory for dynamic allocations with specific size */\n\n    /*\n     * Create memory region(s) of memory.\n     * If device has internal/external memory available,\n     * multiple memories may be used\n     */\n    lwesp_mem_region_t mem_regions[] = {{memory, sizeof(memory)}};\n    if (!initialized) {\n        lwesp_mem_assignmemory(mem_regions,\n                               LWESP_ARRAYSIZE(mem_regions)); /* Assign memory for allocations to ESP library */\n    }\n#endif /* !LWESP_CFG_MEM_CUSTOM */\n\n    /* Step 2: Set AT port send function to use when we have data to transmit */\n    if (!initialized) {\n        ll->send_fn = send_data; /* Set callback function to send data */\n        ll->reset_fn = reset_device;\n    }\n\n    /* Step 3: Configure AT port to be able to send/receive data to/from ESP device */\n    configure_uart(ll->uart.baudrate); /* Initialize UART for communication */\n    initialized = 1;\n\n    return lwespOK;\n}\n\n/**\n * \\brief           Callback function to de-init low-level communication part\n */\nlwespr_t\nlwesp_ll_deinit(lwesp_ll_t* ll) {\n    if (uart_thread_handle != NULL) {\n        lwesp_sys_thread_terminate(&uart_thread_handle);\n        uart_thread_handle = NULL;\n    }\n    initialized = 0; /* Clear initialized flag */\n    return lwespOK;\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32.c",
    "content": "/**\n * \\file            lwesp_ll_stm32.c\n * \\brief           Generic STM32 driver, included in various STM32 driver variants\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n\n/*\n * How it works\n *\n * On first call to \\ref lwesp_ll_init, new thread is created and processed in usart_ll_thread function.\n * USART is configured in RX DMA mode and any incoming bytes are processed inside thread function.\n * DMA and USART implement interrupt handlers to notify main thread about new data ready to send to upper layer.\n *\n * More about UART + RX DMA: https://github.com/MaJerle/stm32-usart-dma-rx-tx\n *\n * \\ref LWESP_CFG_INPUT_USE_PROCESS must be enabled in `lwesp_config.h` to use this driver.\n */\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_input.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"system/lwesp_ll.h\"\n\n#if !__DOXYGEN__\n\n#if !LWESP_CFG_INPUT_USE_PROCESS\n#error \"LWESP_CFG_INPUT_USE_PROCESS must be enabled in `lwesp_config.h` to use this driver.\"\n#endif /* LWESP_CFG_INPUT_USE_PROCESS */\n\n#if !defined(LWESP_USART_DMA_RX_BUFF_SIZE)\n#define LWESP_USART_DMA_RX_BUFF_SIZE 0x1000\n#endif /* !defined(LWESP_USART_DMA_RX_BUFF_SIZE) */\n\n#if !defined(LWESP_MEM_SIZE)\n#define LWESP_MEM_SIZE 0x4000\n#endif /* !defined(LWESP_MEM_SIZE) */\n\n#if !defined(LWESP_USART_RDR_NAME)\n#define LWESP_USART_RDR_NAME RDR\n#endif /* !defined(LWESP_USART_RDR_NAME) */\n\n/* USART memory */\nstatic uint8_t usart_mem[LWESP_USART_DMA_RX_BUFF_SIZE];\nstatic uint8_t is_running, initialized;\nstatic size_t old_pos;\n\n/* USART thread */\nstatic void usart_ll_thread(void* arg);\nstatic osThreadId_t usart_ll_thread_id;\n\n/* Message queue */\nstatic osMessageQueueId_t usart_ll_mbox_id;\n\n/**\n * \\brief           USART data processing\n */\nstatic void\nusart_ll_thread(void* arg) {\n    size_t pos;\n\n    LWESP_UNUSED(arg);\n\n    while (1) {\n        void* d;\n        /* Wait for the event message from DMA or USART */\n        osMessageQueueGet(usart_ll_mbox_id, &d, NULL, osWaitForever);\n\n        /* Read data */\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        pos = sizeof(usart_mem) - LL_DMA_GetDataLength(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n#else\n        pos = sizeof(usart_mem) - LL_DMA_GetDataLength(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n        if (pos != old_pos && is_running) {\n            if (pos > old_pos) {\n                lwesp_input_process(&usart_mem[old_pos], pos - old_pos);\n            } else {\n                lwesp_input_process(&usart_mem[old_pos], sizeof(usart_mem) - old_pos);\n                if (pos > 0) {\n                    lwesp_input_process(&usart_mem[0], pos);\n                }\n            }\n            old_pos = pos;\n        }\n    }\n}\n\n/**\n * \\brief           Configure UART using DMA for receive in double buffer mode and IDLE line detection\n */\nstatic void\nprv_configure_uart(uint32_t baudrate) {\n    static LL_USART_InitTypeDef usart_init;\n    static LL_DMA_InitTypeDef dma_init;\n    LL_GPIO_InitTypeDef gpio_init;\n\n    if (!initialized) {\n        /* Enable peripheral clocks */\n        LWESP_USART_CLK;\n        LWESP_USART_DMA_CLK;\n        LWESP_USART_TX_PORT_CLK;\n        LWESP_USART_RX_PORT_CLK;\n\n#if defined(LWESP_RESET_PIN)\n        LWESP_RESET_PORT_CLK;\n#endif /* defined(LWESP_RESET_PIN) */\n\n#if defined(LWESP_GPIO0_PIN)\n        LWESP_GPIO0_PORT_CLK;\n#endif /* defined(LWESP_GPIO0_PIN) */\n\n#if defined(LWESP_GPIO2_PIN)\n        LWESP_GPIO2_PORT_CLK;\n#endif /* defined(LWESP_GPIO2_PIN) */\n\n#if defined(LWESP_CH_PD_PIN)\n        LWESP_CH_PD_PORT_CLK;\n#endif /* defined(LWESP_CH_PD_PIN) */\n\n        /* Global pin configuration */\n        LL_GPIO_StructInit(&gpio_init);\n        gpio_init.OutputType = LL_GPIO_OUTPUT_PUSHPULL;\n        gpio_init.Pull = LL_GPIO_PULL_UP;\n        gpio_init.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;\n        gpio_init.Mode = LL_GPIO_MODE_OUTPUT;\n\n#if defined(LWESP_RESET_PIN)\n        /* Configure RESET pin */\n        gpio_init.Pin = LWESP_RESET_PIN;\n        LL_GPIO_Init(LWESP_RESET_PORT, &gpio_init);\n#endif /* defined(LWESP_RESET_PIN) */\n\n#if defined(LWESP_GPIO0_PIN)\n        /* Configure GPIO0 pin */\n        gpio_init.Pin = LWESP_GPIO0_PIN;\n        LL_GPIO_Init(LWESP_GPIO0_PORT, &gpio_init);\n        LL_GPIO_SetOutputPin(LWESP_GPIO0_PORT, LWESP_GPIO0_PIN);\n#endif /* defined(LWESP_GPIO0_PIN) */\n\n#if defined(LWESP_GPIO2_PIN)\n        /* Configure GPIO2 pin */\n        gpio_init.Pin = LWESP_GPIO2_PIN;\n        LL_GPIO_Init(LWESP_GPIO2_PORT, &gpio_init);\n        LL_GPIO_SetOutputPin(LWESP_GPIO2_PORT, LWESP_GPIO2_PIN);\n#endif /* defined(LWESP_GPIO2_PIN) */\n\n#if defined(LWESP_CH_PD_PIN)\n        /* Configure CH_PD pin */\n        gpio_init.Pin = LWESP_CH_PD_PIN;\n        LL_GPIO_Init(LWESP_CH_PD_PORT, &gpio_init);\n        LL_GPIO_SetOutputPin(LWESP_CH_PD_PORT, LWESP_CH_PD_PIN);\n#endif /* defined(LWESP_CH_PD_PIN) */\n\n        /* Configure USART pins */\n        gpio_init.Mode = LL_GPIO_MODE_ALTERNATE;\n\n        /* TX PIN */\n        gpio_init.Alternate = LWESP_USART_TX_PIN_AF;\n        gpio_init.Pin = LWESP_USART_TX_PIN;\n        LL_GPIO_Init(LWESP_USART_TX_PORT, &gpio_init);\n\n        /* RX PIN */\n        gpio_init.Alternate = LWESP_USART_RX_PIN_AF;\n        gpio_init.Pin = LWESP_USART_RX_PIN;\n        LL_GPIO_Init(LWESP_USART_RX_PORT, &gpio_init);\n\n        /* Configure UART */\n        LL_USART_DeInit(LWESP_USART);\n        LL_USART_StructInit(&usart_init);\n        usart_init.BaudRate = baudrate;\n        usart_init.DataWidth = LL_USART_DATAWIDTH_8B;\n        usart_init.HardwareFlowControl = LL_USART_HWCONTROL_NONE;\n        usart_init.OverSampling = LL_USART_OVERSAMPLING_16;\n        usart_init.Parity = LL_USART_PARITY_NONE;\n        usart_init.StopBits = LL_USART_STOPBITS_1;\n        usart_init.TransferDirection = LL_USART_DIRECTION_TX_RX;\n        LL_USART_Init(LWESP_USART, &usart_init);\n\n        /* Enable USART interrupts and DMA request */\n        LL_USART_EnableIT_IDLE(LWESP_USART);\n        LL_USART_EnableIT_PE(LWESP_USART);\n        LL_USART_EnableIT_ERROR(LWESP_USART);\n        LL_USART_EnableDMAReq_RX(LWESP_USART);\n\n        /* Enable USART interrupts */\n        NVIC_SetPriority(LWESP_USART_IRQ, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x07, 0x00));\n        NVIC_EnableIRQ(LWESP_USART_IRQ);\n\n        /* Configure DMA */\n        is_running = 0;\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        LL_DMA_DeInit(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n#if defined(LWESP_USART_DMA_RX_CH)\n        dma_init.Channel = LWESP_USART_DMA_RX_CH;\n#else\n        dma_init.PeriphRequest = LWESP_USART_DMA_RX_REQ_NUM;\n#endif /* !defined(STM32F4xx) && !defined(STM32F7xx) && !defined(STM32F2xx) */\n#else\n        LL_DMA_DeInit(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n        dma_init.PeriphRequest = LWESP_USART_DMA_RX_REQ_NUM;\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n        dma_init.PeriphOrM2MSrcAddress = (uint32_t)&LWESP_USART->LWESP_USART_RDR_NAME;\n        dma_init.MemoryOrM2MDstAddress = (uint32_t)usart_mem;\n        dma_init.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;\n        dma_init.Mode = LL_DMA_MODE_CIRCULAR;\n        dma_init.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;\n        dma_init.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;\n        dma_init.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;\n        dma_init.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;\n        dma_init.NbData = sizeof(usart_mem);\n        dma_init.Priority = LL_DMA_PRIORITY_MEDIUM;\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        LL_DMA_Init(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM, &dma_init);\n#else\n        LL_DMA_Init(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH, &dma_init);\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n\n        /* Enable DMA interrupts */\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        LL_DMA_EnableIT_HT(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_TC(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_TE(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_FE(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_DME(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n#else\n        LL_DMA_EnableIT_HT(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n        LL_DMA_EnableIT_TC(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n        LL_DMA_EnableIT_TE(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n\n        /* Enable DMA interrupts */\n        NVIC_SetPriority(LWESP_USART_DMA_RX_IRQ, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x07, 0x00));\n        NVIC_EnableIRQ(LWESP_USART_DMA_RX_IRQ);\n\n        old_pos = 0;\n        is_running = 1;\n\n        /* Start DMA and USART */\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        LL_DMA_EnableStream(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n#else\n        LL_DMA_EnableChannel(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n        LL_USART_Enable(LWESP_USART);\n    } else {\n        osDelay(10);\n        LL_USART_Disable(LWESP_USART);\n        usart_init.BaudRate = baudrate;\n        LL_USART_Init(LWESP_USART, &usart_init);\n        LL_USART_Enable(LWESP_USART);\n    }\n\n    /* Create mbox and start thread */\n    if (usart_ll_mbox_id == NULL) {\n        usart_ll_mbox_id = osMessageQueueNew(10, sizeof(void*), NULL);\n    }\n    if (usart_ll_thread_id == NULL) {\n        const osThreadAttr_t attr = {.stack_size = 1536};\n        usart_ll_thread_id = osThreadNew(usart_ll_thread, usart_ll_mbox_id, &attr);\n    }\n}\n\n#if defined(LWESP_RESET_PIN)\n/**\n * \\brief           Hardware reset callback\n */\nstatic uint8_t\nprv_reset_device(uint8_t state) {\n    if (state) { /* Activate reset line */\n        LL_GPIO_ResetOutputPin(LWESP_RESET_PORT, LWESP_RESET_PIN);\n    } else {\n        LL_GPIO_SetOutputPin(LWESP_RESET_PORT, LWESP_RESET_PIN);\n    }\n    return 1;\n}\n#endif /* defined(LWESP_RESET_PIN) */\n\n/**\n * \\brief           Send data to ESP device\n * \\param[in]       data: Pointer to data to send\n * \\param[in]       len: Number of bytes to send\n * \\return          Number of bytes sent\n */\nstatic size_t\nprv_send_data(const void* data, size_t len) {\n    const uint8_t* d = data;\n\n    for (size_t i = 0; i < len; ++i, ++d) {\n        LL_USART_TransmitData8(LWESP_USART, *d);\n        while (!LL_USART_IsActiveFlag_TXE(LWESP_USART)) {}\n    }\n    return len;\n}\n\n/**\n * \\brief           Callback function called from initialization process\n */\nlwespr_t\nlwesp_ll_init(lwesp_ll_t* ll) {\n#if !LWESP_CFG_MEM_CUSTOM\n    static uint8_t memory[LWESP_MEM_SIZE];\n    const lwesp_mem_region_t mem_regions[] = {{memory, sizeof(memory)}};\n\n    if (!initialized) {\n        lwesp_mem_assignmemory(mem_regions, LWESP_ARRAYSIZE(mem_regions)); /* Assign memory for allocations */\n    }\n#endif /* !LWESP_CFG_MEM_CUSTOM */\n\n    if (!initialized) {\n        ll->send_fn = prv_send_data; /* Set callback function to send data */\n#if defined(LWESP_RESET_PIN)\n        ll->reset_fn = prv_reset_device; /* Set callback for hardware reset */\n#endif                                   /* defined(LWESP_RESET_PIN) */\n    }\n\n    prv_configure_uart(ll->uart.baudrate); /* Initialize UART for communication */\n    initialized = 1;\n    return lwespOK;\n}\n\n/**\n * \\brief           Callback function to de-init low-level communication part\n */\nlwespr_t\nlwesp_ll_deinit(lwesp_ll_t* ll) {\n    if (usart_ll_mbox_id != NULL) {\n        osMessageQueueId_t tmp = usart_ll_mbox_id;\n        usart_ll_mbox_id = NULL;\n        osMessageQueueDelete(tmp);\n    }\n    if (usart_ll_thread_id != NULL) {\n        osThreadId_t tmp = usart_ll_thread_id;\n        usart_ll_thread_id = NULL;\n        osThreadTerminate(tmp);\n    }\n    initialized = 0;\n    LWESP_UNUSED(ll);\n    return lwespOK;\n}\n\n/**\n * \\brief           UART global interrupt handler\n */\nvoid\nLWESP_USART_IRQHANDLER(void) {\n    LL_USART_ClearFlag_IDLE(LWESP_USART);\n    LL_USART_ClearFlag_PE(LWESP_USART);\n    LL_USART_ClearFlag_FE(LWESP_USART);\n    LL_USART_ClearFlag_ORE(LWESP_USART);\n    LL_USART_ClearFlag_NE(LWESP_USART);\n\n    if (usart_ll_mbox_id != NULL) {\n        void* d = (void*)1;\n        osMessageQueuePut(usart_ll_mbox_id, &d, 0, 0);\n    }\n}\n\n/**\n * \\brief           UART DMA stream/channel handler\n */\nvoid\nLWESP_USART_DMA_RX_IRQHANDLER(void) {\n    LWESP_USART_DMA_RX_CLEAR_TC;\n    LWESP_USART_DMA_RX_CLEAR_HT;\n\n    if (usart_ll_mbox_id != NULL) {\n        void* d = (void*)1;\n        osMessageQueuePut(usart_ll_mbox_id, &d, 0, 0);\n    }\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32_threadx.c",
    "content": "/**\n * \\file            lwesp_ll_stm32_threadx.c\n * \\brief           Generic STM32 driver for ThreadX, included in various STM32 driver variants\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Neo Xiong <xiongyu0523@gmail.com>\n * Version:         v1.1.2-dev\n */\n\n/*\n * How it works\n *\n * On first call to \\ref lwesp_ll_init, new thread is created and processed in usart_ll_thread function.\n * USART is configured in RX DMA mode and any incoming bytes are processed inside thread function.\n * DMA and USART implement interrupt handlers to notify main thread about new data ready to send to upper layer.\n *\n * More about UART + RX DMA: https://github.com/MaJerle/stm32-usart-dma-rx-tx\n *\n * \\ref LWESP_CFG_INPUT_USE_PROCESS must be enabled in `lwesp_config.h` to use this driver.\n */\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_input.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"system/lwesp_ll.h\"\n#include \"tx_api.h\"\n\n#if !__DOXYGEN__\n\n#if !LWESP_CFG_INPUT_USE_PROCESS\n#error \"LWESP_CFG_INPUT_USE_PROCESS must be enabled in `lwesp_config.h` to use this driver.\"\n#endif /* LWESP_CFG_INPUT_USE_PROCESS */\n\n#if !defined(LWESP_USART_DMA_RX_BUFF_SIZE)\n#define LWESP_USART_DMA_RX_BUFF_SIZE 0x1000\n#endif /* !defined(LWESP_USART_DMA_RX_BUFF_SIZE) */\n\n#if !defined(LWESP_USART_RDR_NAME)\n#define LWESP_USART_RDR_NAME RDR\n#endif /* !defined(LWESP_USART_RDR_NAME) */\n\n#define LL_QUEUE_NUM_OF_ENTRY 10\nstatic UCHAR ll_queue[LL_QUEUE_NUM_OF_ENTRY * sizeof(void*)];\n\n/* USART memory */\nstatic uint8_t usart_mem[LWESP_USART_DMA_RX_BUFF_SIZE];\nstatic uint8_t is_running, initialized;\nstatic size_t old_pos;\n\n/* USART thread */\nstatic void usart_ll_thread_entry(ULONG arg);\nstatic TX_THREAD usart_ll_thread;\nstatic UCHAR usart_ll_thread_stack[LWESP_SYS_THREAD_SS];\n\n/* Message queue */\nstatic TX_QUEUE usart_ll_mbox;\n\n/**\n * \\brief           USART data processing\n */\nstatic void\nusart_ll_thread_entry(ULONG arg) {\n    size_t pos;\n\n    LWESP_UNUSED(arg);\n\n    while (1) {\n        void* d;\n        /* Wait for the event message from DMA or USART */\n        tx_queue_receive(&usart_ll_mbox, &d, TX_WAIT_FOREVER);\n\n        /* Read data */\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        pos = sizeof(usart_mem) - LL_DMA_GetDataLength(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n#else\n        pos = sizeof(usart_mem) - LL_DMA_GetDataLength(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n        if (pos != old_pos && is_running) {\n            if (pos > old_pos) {\n                lwesp_input_process(&usart_mem[old_pos], pos - old_pos);\n            } else {\n                lwesp_input_process(&usart_mem[old_pos], sizeof(usart_mem) - old_pos);\n                if (pos > 0) {\n                    lwesp_input_process(&usart_mem[0], pos);\n                }\n            }\n            old_pos = pos;\n            if (old_pos == sizeof(usart_mem)) {\n                old_pos = 0;\n            }\n        }\n    }\n}\n\n/**\n * \\brief           Configure UART using DMA for receive in double buffer mode and IDLE line detection\n */\nstatic void\nconfigure_uart(uint32_t baudrate) {\n    static LL_USART_InitTypeDef usart_init;\n    static LL_DMA_InitTypeDef dma_init;\n    LL_GPIO_InitTypeDef gpio_init;\n\n    if (!initialized) {\n        /* Enable peripheral clocks */\n        LWESP_USART_CLK;\n#if defined(LWESP_USART_DMAMUX)\n        LWESP_USART_DMAMUX_CLK;\n#endif\n        LWESP_USART_DMA_CLK;\n        LWESP_USART_TX_PORT_CLK;\n        LWESP_USART_RX_PORT_CLK;\n\n#if defined(LWESP_RESET_PIN)\n        LWESP_RESET_PORT_CLK;\n#endif /* defined(LWESP_RESET_PIN) */\n\n#if defined(LWESP_GPIO0_PIN)\n        LWESP_GPIO0_PORT_CLK;\n#endif /* defined(LWESP_GPIO0_PIN) */\n\n#if defined(LWESP_GPIO2_PIN)\n        LWESP_GPIO2_PORT_CLK;\n#endif /* defined(LWESP_GPIO2_PIN) */\n\n#if defined(LWESP_CH_PD_PIN)\n        LWESP_CH_PD_PORT_CLK;\n#endif /* defined(LWESP_CH_PD_PIN) */\n\n        /* Global pin configuration */\n        LL_GPIO_StructInit(&gpio_init);\n        gpio_init.OutputType = LL_GPIO_OUTPUT_PUSHPULL;\n        gpio_init.Pull = LL_GPIO_PULL_UP;\n        gpio_init.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;\n        gpio_init.Mode = LL_GPIO_MODE_OUTPUT;\n\n#if defined(LWESP_RESET_PIN)\n        /* Configure RESET pin */\n        gpio_init.Pin = LWESP_RESET_PIN;\n        LL_GPIO_Init(LWESP_RESET_PORT, &gpio_init);\n#endif /* defined(LWESP_RESET_PIN) */\n\n#if defined(LWESP_GPIO0_PIN)\n        /* Configure GPIO0 pin */\n        gpio_init.Pin = LWESP_GPIO0_PIN;\n        LL_GPIO_Init(LWESP_GPIO0_PORT, &gpio_init);\n        LL_GPIO_SetOutputPin(LWESP_GPIO0_PORT, LWESP_GPIO0_PIN);\n#endif /* defined(LWESP_GPIO0_PIN) */\n\n#if defined(LWESP_GPIO2_PIN)\n        /* Configure GPIO2 pin */\n        gpio_init.Pin = LWESP_GPIO2_PIN;\n        LL_GPIO_Init(LWESP_GPIO2_PORT, &gpio_init);\n        LL_GPIO_SetOutputPin(LWESP_GPIO2_PORT, LWESP_GPIO2_PIN);\n#endif /* defined(LWESP_GPIO2_PIN) */\n\n#if defined(LWESP_CH_PD_PIN)\n        /* Configure CH_PD pin */\n        gpio_init.Pin = LWESP_CH_PD_PIN;\n        LL_GPIO_Init(LWESP_CH_PD_PORT, &gpio_init);\n        LL_GPIO_SetOutputPin(LWESP_CH_PD_PORT, LWESP_CH_PD_PIN);\n#endif /* defined(LWESP_CH_PD_PIN) */\n\n        /* Configure USART pins */\n        gpio_init.Mode = LL_GPIO_MODE_ALTERNATE;\n\n        /* TX PIN */\n        gpio_init.Alternate = LWESP_USART_TX_PIN_AF;\n        gpio_init.Pin = LWESP_USART_TX_PIN;\n        LL_GPIO_Init(LWESP_USART_TX_PORT, &gpio_init);\n\n        /* RX PIN */\n        gpio_init.Alternate = LWESP_USART_RX_PIN_AF;\n        gpio_init.Pin = LWESP_USART_RX_PIN;\n        LL_GPIO_Init(LWESP_USART_RX_PORT, &gpio_init);\n\n        /* Configure UART */\n        LL_USART_DeInit(LWESP_USART);\n        LL_USART_StructInit(&usart_init);\n        usart_init.BaudRate = baudrate;\n        usart_init.DataWidth = LL_USART_DATAWIDTH_8B;\n        usart_init.HardwareFlowControl = LL_USART_HWCONTROL_NONE;\n        usart_init.OverSampling = LL_USART_OVERSAMPLING_16;\n        usart_init.Parity = LL_USART_PARITY_NONE;\n        usart_init.StopBits = LL_USART_STOPBITS_1;\n        usart_init.TransferDirection = LL_USART_DIRECTION_TX_RX;\n        LL_USART_Init(LWESP_USART, &usart_init);\n\n        /* Enable USART interrupts and DMA request */\n        LL_USART_EnableIT_IDLE(LWESP_USART);\n        LL_USART_EnableIT_PE(LWESP_USART);\n        LL_USART_EnableIT_ERROR(LWESP_USART);\n        LL_USART_EnableDMAReq_RX(LWESP_USART);\n\n        /* Enable USART interrupts */\n        NVIC_SetPriority(LWESP_USART_IRQ, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x07, 0x00));\n        NVIC_EnableIRQ(LWESP_USART_IRQ);\n\n        /* Configure DMA */\n        is_running = 0;\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        LL_DMA_DeInit(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        dma_init.Channel = LWESP_USART_DMA_RX_CH;\n#else\n        LL_DMA_DeInit(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n        dma_init.PeriphRequest = LWESP_USART_DMA_RX_REQ_NUM;\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n        dma_init.PeriphOrM2MSrcAddress = (uint32_t)&LWESP_USART->LWESP_USART_RDR_NAME;\n        dma_init.MemoryOrM2MDstAddress = (uint32_t)usart_mem;\n        dma_init.Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;\n        dma_init.Mode = LL_DMA_MODE_CIRCULAR;\n        dma_init.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;\n        dma_init.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;\n        dma_init.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;\n        dma_init.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;\n        dma_init.NbData = sizeof(usart_mem);\n        dma_init.Priority = LL_DMA_PRIORITY_MEDIUM;\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        LL_DMA_Init(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM, &dma_init);\n#else\n        LL_DMA_Init(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH, &dma_init);\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n\n        /* Enable DMA interrupts */\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        LL_DMA_EnableIT_HT(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_TC(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_TE(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_FE(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_DME(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n#else\n        LL_DMA_EnableIT_HT(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n        LL_DMA_EnableIT_TC(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n        LL_DMA_EnableIT_TE(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n\n        /* Enable DMA interrupts */\n        NVIC_SetPriority(LWESP_USART_DMA_RX_IRQ, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x07, 0x00));\n        NVIC_EnableIRQ(LWESP_USART_DMA_RX_IRQ);\n\n        old_pos = 0;\n        is_running = 1;\n\n        /* Start DMA and USART */\n#if defined(LWESP_USART_DMA_RX_STREAM)\n        LL_DMA_EnableStream(LWESP_USART_DMA, LWESP_USART_DMA_RX_STREAM);\n#else\n        LL_DMA_EnableChannel(LWESP_USART_DMA, LWESP_USART_DMA_RX_CH);\n#endif /* defined(LWESP_USART_DMA_RX_STREAM) */\n        LL_USART_Enable(LWESP_USART);\n    } else {\n        tx_thread_sleep(10);\n        LL_USART_Disable(LWESP_USART);\n        usart_init.BaudRate = baudrate;\n        LL_USART_Init(LWESP_USART, &usart_init);\n        LL_USART_Enable(LWESP_USART);\n    }\n\n    /* Create mbox and start thread */\n    if (usart_ll_mbox.tx_queue_id == TX_CLEAR_ID) {\n        (VOID) tx_queue_create(&usart_ll_mbox, \"ll queue\", sizeof(void*) / sizeof(ULONG), ll_queue, sizeof(ll_queue));\n    }\n\n    if (usart_ll_thread.tx_thread_id == TX_CLEAR_ID) {\n        (VOID) tx_thread_create(&usart_ll_thread, \"ll thread\", usart_ll_thread_entry, 0, usart_ll_thread_stack,\n                                LWESP_SYS_THREAD_SS, 0, 0, TX_NO_TIME_SLICE, TX_AUTO_START);\n    }\n}\n\n#if defined(LWESP_RESET_PIN)\n/**\n * \\brief           Hardware reset callback\n */\nstatic uint8_t\nreset_device(uint8_t state) {\n    if (state) { /* Activate reset line */\n        LL_GPIO_ResetOutputPin(LWESP_RESET_PORT, LWESP_RESET_PIN);\n    } else {\n        LL_GPIO_SetOutputPin(LWESP_RESET_PORT, LWESP_RESET_PIN);\n    }\n    return 1;\n}\n#endif /* defined(LWESP_RESET_PIN) */\n\n/**\n * \\brief           Send data to ESP device\n * \\param[in]       data: Pointer to data to send\n * \\param[in]       len: Number of bytes to send\n * \\return          Number of bytes sent\n */\nstatic size_t\nsend_data(const void* data, size_t len) {\n    const uint8_t* d = data;\n\n    for (size_t i = 0; i < len; ++i, ++d) {\n        LL_USART_TransmitData8(LWESP_USART, *d);\n        while (!LL_USART_IsActiveFlag_TXE(LWESP_USART)) {}\n    }\n    return len;\n}\n\n/**\n * \\brief           Callback function called from initialization process\n */\nlwespr_t\nlwesp_ll_init(lwesp_ll_t* ll) {\n\n    if (!initialized) {\n        ll->send_fn = send_data; /* Set callback function to send data */\n#if defined(LWESP_RESET_PIN)\n        ll->reset_fn = reset_device; /* Set callback for hardware reset */\n#endif                               /* defined(LWESP_RESET_PIN) */\n    }\n\n    configure_uart(ll->uart.baudrate); /* Initialize UART for communication */\n    initialized = 1;\n    return lwespOK;\n}\n\n/**\n * \\brief           Callback function to de-init low-level communication part\n */\nlwespr_t\nlwesp_ll_deinit(lwesp_ll_t* ll) {\n\n    (VOID) tx_queue_delete(&usart_ll_mbox);\n    (VOID) tx_thread_delete(&usart_ll_thread);\n\n    initialized = 0;\n    LWESP_UNUSED(ll);\n    return lwespOK;\n}\n\n/**\n * \\brief           UART global interrupt handler\n */\nvoid\nLWESP_USART_IRQHANDLER(void) {\n    LL_USART_ClearFlag_IDLE(LWESP_USART);\n    LL_USART_ClearFlag_PE(LWESP_USART);\n    LL_USART_ClearFlag_FE(LWESP_USART);\n    LL_USART_ClearFlag_ORE(LWESP_USART);\n    LL_USART_ClearFlag_NE(LWESP_USART);\n\n    if (usart_ll_mbox.tx_queue_id != TX_CLEAR_ID) {\n        void* d = (void*)1;\n        tx_queue_send(&usart_ll_mbox, &d, TX_NO_WAIT);\n    }\n}\n\n/**\n * \\brief           UART DMA stream/channel handler\n */\nvoid\nLWESP_USART_DMA_RX_IRQHANDLER(void) {\n    LWESP_USART_DMA_RX_CLEAR_TC;\n    LWESP_USART_DMA_RX_CLEAR_HT;\n    LWESP_USART_DMA_RX_CLEAR_TE;\n\n    if (usart_ll_mbox.tx_queue_id != TX_CLEAR_ID) {\n        void* d = (void*)1;\n        tx_queue_send(&usart_ll_mbox, &d, TX_NO_WAIT);\n    }\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32f429zi_nucleo.c",
    "content": "/**\n * \\file            lwesp_ll_stm32f429zi_nucleo.c\n * \\brief           Low-level communication with ESP device for STM32F429ZI-Nucleo using DMA\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n\n/*\n * Default UART configuration is:\n *\n * UART:                USART2\n * STM32 TX (ESP RX):   GPIOD, GPIO_PIN_5\n * STM32 RX (ESP TX):   GPIOD, GPIO_PIN_6\n * RESET:               GPIOD, GPIO_PIN_1\n * GPIO0:               GPIOD, GPIO_PIN_4\n * GPIO2:               GPIOD, GPIO_PIN_7\n * CH_PD:               GPIOD, GPIO_PIN_3\n *\n * USART_DMA:           DMA1\n * USART_DMA_STREAM:    DMA_STREAM_5\n * USART_DMA_CHANNEL:   DMA_CHANNEL_4\n */\n\n#if !__DOXYGEN__\n\n#include \"stm32f4xx_ll_bus.h\"\n#include \"stm32f4xx_ll_dma.h\"\n#include \"stm32f4xx_ll_gpio.h\"\n#include \"stm32f4xx_ll_rcc.h\"\n#include \"stm32f4xx_ll_usart.h\"\n\n/* USART */\n#define LWESP_USART                   USART2\n#define LWESP_USART_CLK               LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2)\n#define LWESP_USART_IRQ               USART2_IRQn\n#define LWESP_USART_IRQHANDLER        USART2_IRQHandler\n#define LWESP_USART_RDR_NAME          DR\n\n/* DMA settings */\n#define LWESP_USART_DMA               DMA1\n#define LWESP_USART_DMA_CLK           LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)\n#define LWESP_USART_DMA_RX_STREAM     LL_DMA_STREAM_5\n#define LWESP_USART_DMA_RX_CH         LL_DMA_CHANNEL_4\n#define LWESP_USART_DMA_RX_IRQ        DMA1_Stream5_IRQn\n#define LWESP_USART_DMA_RX_IRQHANDLER DMA1_Stream5_IRQHandler\n\n/* DMA flags management */\n#define LWESP_USART_DMA_RX_IS_TC      LL_DMA_IsActiveFlag_TC5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_IS_HT      LL_DMA_IsActiveFlag_HT5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_TC   LL_DMA_ClearFlag_TC5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_HT   LL_DMA_ClearFlag_HT5(LWESP_USART_DMA)\n\n/* USART TX PIN */\n#define LWESP_USART_TX_PORT_CLK       LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_USART_TX_PORT           GPIOD\n#define LWESP_USART_TX_PIN            LL_GPIO_PIN_5\n#define LWESP_USART_TX_PIN_AF         LL_GPIO_AF_7\n\n/* USART RX PIN */\n#define LWESP_USART_RX_PORT_CLK       LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_USART_RX_PORT           GPIOD\n#define LWESP_USART_RX_PIN            LL_GPIO_PIN_6\n#define LWESP_USART_RX_PIN_AF         LL_GPIO_AF_7\n\n/* RESET PIN */\n#define LWESP_RESET_PORT_CLK          LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_RESET_PORT              GPIOD\n#define LWESP_RESET_PIN               LL_GPIO_PIN_1\n\n/* GPIO0 PIN */\n#define LWESP_GPIO0_PORT_CLK          LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_GPIO0_PORT              GPIOD\n#define LWESP_GPIO0_PIN               LL_GPIO_PIN_4\n\n/* GPIO2 PIN */\n#define LWESP_GPIO2_PORT_CLK          LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_GPIO2_PORT              GPIOD\n#define LWESP_GPIO2_PIN               LL_GPIO_PIN_7\n\n/* CH_PD PIN */\n#define LWESP_CH_PD_PORT_CLK          LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_CH_PD_PORT              GPIOD\n#define LWESP_CH_PD_PIN               LL_GPIO_PIN_3\n\n/* Include STM32 generic driver */\n#include \"../system/lwesp_ll_stm32.c\"\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32f723e_discovery.c",
    "content": "/**\n * \\file            lwesp_ll_stm32f723e_discovery.c\n * \\brief           Low-level communication with ESP device for STM32F723E-Discovery using DMA\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n\n/*\n * Default UART configuration is (Connector CN14 on board):\n *\n * UART:                UART5\n * STM32 TX (ESP RX):   GPIOC, GPIO_PIN_12\n * STM32 RX (ESP TX):   GPIOD, GPIO_PIN_2\n * RESET:               GPIOG, GPIO_PIN_14\n * GPIO2:               GPIOD, GPIO_PIN_6\n * CH_PD:               GPIOD, GPIO_PIN_3\n *\n * UART_DMA:            DMA1\n * UART_DMA_STREAM:     DMA_STREAM_0\n * UART_DMA_CHANNEL:    DMA_CHANNEL_4\n */\n\n#if !__DOXYGEN__\n\n#include \"stm32f7xx_ll_bus.h\"\n#include \"stm32f7xx_ll_dma.h\"\n#include \"stm32f7xx_ll_gpio.h\"\n#include \"stm32f7xx_ll_rcc.h\"\n#include \"stm32f7xx_ll_usart.h\"\n\n/* USART */\n#define LWESP_USART                   UART5\n#define LWESP_USART_CLK               LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART5)\n#define LWESP_USART_IRQ               UART5_IRQn\n#define LWESP_USART_IRQHANDLER        UART5_IRQHandler\n\n/* DMA settings */\n#define LWESP_USART_DMA               DMA1\n#define LWESP_USART_DMA_CLK           LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)\n#define LWESP_USART_DMA_RX_STREAM     LL_DMA_STREAM_0\n#define LWESP_USART_DMA_RX_CH         LL_DMA_CHANNEL_4\n#define LWESP_USART_DMA_RX_IRQ        DMA1_Stream0_IRQn\n#define LWESP_USART_DMA_RX_IRQHANDLER DMA1_Stream0_IRQHandler\n\n/* DMA flags management */\n#define LWESP_USART_DMA_RX_IS_TC      LL_DMA_IsActiveFlag_TC0(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_IS_HT      LL_DMA_IsActiveFlag_HT0(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_TC   LL_DMA_ClearFlag_TC0(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_HT   LL_DMA_ClearFlag_HT0(LWESP_USART_DMA)\n\n/* USART TX PIN */\n#define LWESP_USART_TX_PORT_CLK       LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOC)\n#define LWESP_USART_TX_PORT           GPIOC\n#define LWESP_USART_TX_PIN            LL_GPIO_PIN_12\n#define LWESP_USART_TX_PIN_AF         LL_GPIO_AF_8\n\n/* USART RX PIN */\n#define LWESP_USART_RX_PORT_CLK       LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_USART_RX_PORT           GPIOD\n#define LWESP_USART_RX_PIN            LL_GPIO_PIN_2\n#define LWESP_USART_RX_PIN_AF         LL_GPIO_AF_8\n\n/* RESET PIN */\n#define LWESP_RESET_PORT_CLK          LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOG)\n#define LWESP_RESET_PORT              GPIOG\n#define LWESP_RESET_PIN               LL_GPIO_PIN_14\n\n/* GPIO2 PIN */\n#define LWESP_GPIO2_PORT_CLK          LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_GPIO2_PORT              GPIOD\n#define LWESP_GPIO2_PIN               LL_GPIO_PIN_6\n\n/* CH_PD PIN */\n#define LWESP_CH_PD_PORT_CLK          LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_CH_PD_PORT              GPIOD\n#define LWESP_CH_PD_PIN               LL_GPIO_PIN_3\n\n/* Include STM32 generic driver */\n#include \"../system/lwesp_ll_stm32.c\"\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32f769i_discovery.c",
    "content": "/**\n * \\file            lwesp_ll_stm32f769i_discovery.c\n * \\brief           Low-level communication with ESP device for STM32F769I-Discovery using DMA\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n\n/*\n * Default UART configuration is (Connector CN2 on board):\n *\n * UART:                UART5\n * STM32 TX (ESP RX):   GPIOC, GPIO_PIN_12\n * STM32 RX (ESP TX):   GPIOD, GPIO_PIN_2\n * RESET:               GPIOJ, GPIO_PIN_14\n *\n * UART_DMA:            DMA1\n * UART_DMA_STREAM:     DMA_STREAM_0\n * UART_DMA_CHANNEL:    DMA_CHANNEL_4\n */\n\n#if !__DOXYGEN__\n\n#include \"stm32f7xx_ll_bus.h\"\n#include \"stm32f7xx_ll_dma.h\"\n#include \"stm32f7xx_ll_gpio.h\"\n#include \"stm32f7xx_ll_rcc.h\"\n#include \"stm32f7xx_ll_usart.h\"\n\n/* USART */\n#define LWESP_USART                   UART5\n#define LWESP_USART_CLK               LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART5)\n#define LWESP_USART_IRQ               UART5_IRQn\n#define LWESP_USART_IRQHANDLER        UART5_IRQHandler\n\n/* DMA settings */\n#define LWESP_USART_DMA               DMA1\n#define LWESP_USART_DMA_CLK           LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)\n#define LWESP_USART_DMA_RX_STREAM     LL_DMA_STREAM_0\n#define LWESP_USART_DMA_RX_CH         LL_DMA_CHANNEL_4\n#define LWESP_USART_DMA_RX_IRQ        DMA1_Stream0_IRQn\n#define LWESP_USART_DMA_RX_IRQHANDLER DMA1_Stream0_IRQHandler\n\n/* DMA flags management */\n#define LWESP_USART_DMA_RX_IS_TC      LL_DMA_IsActiveFlag_TC0(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_IS_HT      LL_DMA_IsActiveFlag_HT0(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_TC   LL_DMA_ClearFlag_TC0(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_HT   LL_DMA_ClearFlag_HT0(LWESP_USART_DMA)\n\n/* USART TX PIN */\n#define LWESP_USART_TX_PORT_CLK       LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOC)\n#define LWESP_USART_TX_PORT           GPIOC\n#define LWESP_USART_TX_PIN            LL_GPIO_PIN_12\n#define LWESP_USART_TX_PIN_AF         LL_GPIO_AF_8\n\n/* USART RX PIN */\n#define LWESP_USART_RX_PORT_CLK       LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOD)\n#define LWESP_USART_RX_PORT           GPIOD\n#define LWESP_USART_RX_PIN            LL_GPIO_PIN_2\n#define LWESP_USART_RX_PIN_AF         LL_GPIO_AF_8\n\n/* RESET PIN */\n#define LWESP_RESET_PORT_CLK          LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_GPIOJ)\n#define LWESP_RESET_PORT              GPIOJ\n#define LWESP_RESET_PIN               LL_GPIO_PIN_14\n\n/* Include STM32 generic driver */\n#include \"../system/lwesp_ll_stm32.c\"\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32h735g_dk_threadx.c",
    "content": "/**\n * \\file            lwesp_ll_stm32h735g_dk_threadx.c\n * \\brief           STM32H735-DK driver with ThreadX\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n\n/*\n * This is special driver for STM32H735G-DK utilizing ThreadX operating system\n * and full DMA support for TX and RX operation.\n */\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_input.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"lwrb/lwrb.h\"\n#include \"mcu.h\"\n#include \"system/lwesp_ll.h\"\n#include \"tx_api.h\"\n\n#if !__DOXYGEN__\n\n#include \"stm32h7xx_ll_bus.h\"\n#include \"stm32h7xx_ll_dma.h\"\n#include \"stm32h7xx_ll_gpio.h\"\n#include \"stm32h7xx_ll_rcc.h\"\n#include \"stm32h7xx_ll_usart.h\"\n\n#if !LWESP_CFG_INPUT_USE_PROCESS\n#error \"LWESP_CFG_INPUT_USE_PROCESS must be enabled in `lwesp_opts.h` to use this driver.\"\n#endif /* LWESP_CFG_INPUT_USE_PROCESS */\n#if !LWESP_CFG_MEM_CUSTOM\n#error \"LWESP_CFG_MEM_CUSTOM must be used instead. This driver does not set memory regions for LwESP.\"\n#endif /* !LWESP_CFG_MEM_CUSTOM */\n\n/*\n * USART setup\n *\n * PB14 and PB15 are used together with Arduino connector\n * and extension board with ESP32-C3\n */\n#define LWESP_USART                    USART1\n#define LWESP_USART_CLK_EN             LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)\n#define LWESP_USART_IRQ                USART1_IRQn\n#define LWESP_USART_IRQ_HANDLER        USART1_IRQHandler\n\n/* TX DMA */\n#define LWESP_USART_DMA_TX             DMA1\n#define LWESP_USART_DMA_TX_STREAM      LL_DMA_STREAM_5\n#define LWESP_USART_DMA_TX_REQUEST     LL_DMAMUX1_REQ_USART1_TX\n#define LWESP_USART_DMA_TX_CLK_EN      LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)\n#define LWESP_USART_DMA_TX_IRQ         DMA1_Stream5_IRQn\n#define LWESP_USART_DMA_TX_IRQ_HANDLER DMA1_Stream5_IRQHandler\n#define LWESP_USART_DMA_TX_IS_TC       LL_DMA_IsActiveFlag_TC5(LWESP_USART_DMA_TX)\n#define LWESP_USART_DMA_TX_CLEAR_TC    LL_DMA_ClearFlag_TC5(LWESP_USART_DMA_TX)\n#define LWESP_USART_DMA_TX_CLEAR_HT    LL_DMA_ClearFlag_HT5(LWESP_USART_DMA_TX)\n#define LWESP_USART_DMA_TX_CLEAR_TE    LL_DMA_ClearFlag_TE5(LWESP_USART_DMA_TX)\n\n/* RX DMA */\n#define LWESP_USART_DMA_RX             DMA1\n#define LWESP_USART_DMA_RX_STREAM      LL_DMA_STREAM_4\n#define LWESP_USART_DMA_RX_REQUEST     LL_DMAMUX1_REQ_USART1_RX\n#define LWESP_USART_DMA_RX_CLK_EN      LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)\n#define LWESP_USART_DMA_RX_IRQ         DMA1_Stream4_IRQn\n#define LWESP_USART_DMA_RX_IRQ_HANDLER DMA1_Stream4_IRQHandler\n#define LWESP_USART_DMA_RX_IS_TC       LL_DMA_IsActiveFlag_TC4(LWESP_USART_DMA_RX)\n#define LWESP_USART_DMA_RX_IS_HT       LL_DMA_IsActiveFlag_HT4(LWESP_USART_DMA_RX)\n#define LWESP_USART_DMA_RX_IS_TE       LL_DMA_IsActiveFlag_TE4(LWESP_USART_DMA_RX)\n#define LWESP_USART_DMA_RX_CLEAR_TC    LL_DMA_ClearFlag_TC4(LWESP_USART_DMA_RX)\n#define LWESP_USART_DMA_RX_CLEAR_HT    LL_DMA_ClearFlag_HT4(LWESP_USART_DMA_RX)\n#define LWESP_USART_DMA_RX_CLEAR_TE    LL_DMA_ClearFlag_TE4(LWESP_USART_DMA_RX)\n\n/* GPIO configuration */\n#define LWESP_USART_TX_PORT            GPIOB\n#define LWESP_USART_TX_PIN             LL_GPIO_PIN_14\n#define LWESP_USART_TX_PORT_CLK_EN     LL_AHB1_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB)\n#define LWESP_USART_TX_PIN_AF          LL_GPIO_AF_4\n#define LWESP_USART_RX_PORT            GPIOB\n#define LWESP_USART_RX_PIN             LL_GPIO_PIN_15\n#define LWESP_USART_RX_PORT_CLK_EN     LL_AHB1_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB)\n#define LWESP_USART_RX_PIN_AF          LL_GPIO_AF_4\n\n/* TX data buffers, must be 32-bytes aligned (cache) and in dma buffer section to make sure DMA has access to the memory region */\nALIGN_32BYTES(static uint8_t __attribute__((section(\".dma_buffer\"))) lwesp_tx_rb_data[2048]);\nstatic lwrb_t lwesp_tx_rb;\nvolatile size_t lwesp_tx_len;\n\n/*\n * Max number of bytes to transmit in one DMA transfer\n *\n * See https://github.com/MaJerle/stm32-usart-uart-dma-rx-tx\n * for detailed explanation about impact of this number\n */\n#define LWESP_LL_MAX_TX_LEN 64\n\n/* Raw DMA memory for UART received data */\nALIGN_32BYTES(static uint8_t __attribute__((section(\".dma_buffer\"))) lwesp_usart_rx_dma_buffer[256]);\n\n/* USART thread for read and data processing */\nstatic void prv_lwesp_read_thread_entry(ULONG arg);\nstatic TX_THREAD lwesp_read_thread;\nstatic UCHAR lwesp_read_thread_stack[4 * LWESP_SYS_THREAD_SS];\nstatic volatile size_t lwesp_read_old_pos = 0;\nstatic TX_EVENT_FLAGS_GROUP lwesp_ll_event_group;\n\n/* List of flags for read */\n#define LWESP_LL_FLAG_DATA ((ULONG)0x000000001)\n\n/* Status variables */\nstatic uint8_t lwesp_is_running = 0;\nstatic uint8_t lwesp_initialized = 0;\n\n/**\n * \\brief           USART data processing thread\n * This is the thread used to enter received data from UART to the LwESP stack for further processing\n * \\param[in]       arg: User argument\n */\nstatic void\nprv_lwesp_read_thread_entry(ULONG arg) {\n    size_t pos;\n\n    LWESP_UNUSED(arg);\n\n    while (1) {\n        ULONG flags;\n\n        /* Wait for any flag from either DMA or UART interrupts */\n        tx_event_flags_get(&lwesp_ll_event_group, (ULONG)-1, TX_OR_CLEAR, &flags, TX_WAIT_FOREVER);\n\n        /* Read data */\n        pos = sizeof(lwesp_usart_rx_dma_buffer) - LL_DMA_GetDataLength(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM);\n        if (pos != lwesp_read_old_pos && lwesp_is_running) {\n            SCB_InvalidateDCache_by_Addr(lwesp_usart_rx_dma_buffer, sizeof(lwesp_usart_rx_dma_buffer));\n            if (pos > lwesp_read_old_pos) {\n                lwesp_input_process(&lwesp_usart_rx_dma_buffer[lwesp_read_old_pos], pos - lwesp_read_old_pos);\n            } else {\n                lwesp_input_process(&lwesp_usart_rx_dma_buffer[lwesp_read_old_pos],\n                                    sizeof(lwesp_usart_rx_dma_buffer) - lwesp_read_old_pos);\n                if (pos > 0) {\n                    lwesp_input_process(&lwesp_usart_rx_dma_buffer[0], pos);\n                }\n            }\n            lwesp_read_old_pos = pos;\n        }\n    }\n}\n\n/**\n * \\brief           Try to send more data with DMA\n */\nstatic void\nprv_start_tx_transfer(void) {\n    uint32_t primask = __get_PRIMASK();\n    __disable_irq();\n    if (lwesp_tx_len == 0 && (lwesp_tx_len = lwrb_get_linear_block_read_length(&lwesp_tx_rb)) > 0) {\n        const void* d = lwrb_get_linear_block_read_address(&lwesp_tx_rb);\n\n        /* Limit tx len up to some size to optimize buffer read/write process */\n        lwesp_tx_len = LWESP_MIN(lwesp_tx_len, LWESP_LL_MAX_TX_LEN);\n\n        /* Cleanup cache to make sure we have latest data in memory visible by DMA */\n        SCB_CleanDCache_by_Addr((void*)d, lwesp_tx_len);\n\n        /* Clear all DMA flags prior transfer */\n        LWESP_USART_DMA_TX_CLEAR_TC;\n        LWESP_USART_DMA_TX_CLEAR_HT;\n        LWESP_USART_DMA_TX_CLEAR_TE;\n\n        /* Configure DMA */\n        LL_DMA_SetMemoryAddress(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, (uint32_t)d);\n        LL_DMA_SetDataLength(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, lwesp_tx_len);\n\n        /* Enable instances */\n        LL_DMA_EnableStream(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM);\n    }\n    __set_PRIMASK(primask);\n}\n\n/**\n * \\brief           Configure UART using DMA for receive in double buffer mode and IDLE line detection\n * \\param[in]       baudrate: Baudrate for UART communication\n */\nstatic void\nprv_configure_uart(uint32_t baudrate) {\n    LL_GPIO_InitTypeDef gpio_init = {0};\n    LL_USART_InitTypeDef usart_init = {0};\n\n    if (!lwesp_initialized) {\n        /* Enable peripheral clocks */\n        LWESP_USART_CLK_EN;\n        LWESP_USART_DMA_RX_CLK_EN;\n        LWESP_USART_DMA_TX_CLK_EN;\n        LWESP_USART_TX_PORT_CLK_EN;\n        LWESP_USART_RX_PORT_CLK_EN;\n\n        /* Global pin configuration */\n        LL_GPIO_StructInit(&gpio_init);\n        gpio_init.OutputType = LL_GPIO_OUTPUT_PUSHPULL;\n        gpio_init.Pull = LL_GPIO_PULL_UP;\n        gpio_init.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;\n        gpio_init.Mode = LL_GPIO_MODE_ALTERNATE;\n\n        /* TX PIN */\n        gpio_init.Pin = LWESP_USART_TX_PIN;\n        gpio_init.Alternate = LWESP_USART_TX_PIN_AF;\n        LL_GPIO_Init(LWESP_USART_TX_PORT, &gpio_init);\n\n        /* RX PIN */\n        gpio_init.Pin = LWESP_USART_RX_PIN;\n        gpio_init.Alternate = LWESP_USART_RX_PIN_AF;\n        LL_GPIO_Init(LWESP_USART_RX_PORT, &gpio_init);\n\n        /*******************/\n        /*** UART RX DMA ***/\n        /*******************/\n\n        /* Enable DMA interrupts */\n        NVIC_SetPriority(LWESP_USART_DMA_RX_IRQ, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x05, 0x00));\n        NVIC_EnableIRQ(LWESP_USART_DMA_RX_IRQ);\n\n        /* Configure DMA */\n        LL_DMA_SetPeriphRequest(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, LWESP_USART_DMA_RX_REQUEST);\n        LL_DMA_SetDataTransferDirection(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM,\n                                        LL_DMA_DIRECTION_PERIPH_TO_MEMORY);\n        LL_DMA_SetStreamPriorityLevel(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, LL_DMA_PRIORITY_MEDIUM);\n        LL_DMA_SetMode(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, LL_DMA_MODE_CIRCULAR);\n        LL_DMA_SetPeriphIncMode(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, LL_DMA_PERIPH_NOINCREMENT);\n        LL_DMA_SetMemoryIncMode(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, LL_DMA_MEMORY_INCREMENT);\n        LL_DMA_SetPeriphSize(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, LL_DMA_PDATAALIGN_BYTE);\n        LL_DMA_SetMemorySize(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, LL_DMA_MDATAALIGN_BYTE);\n        LL_DMA_DisableFifoMode(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_SetPeriphAddress(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM,\n                                LL_USART_DMA_GetRegAddr(LWESP_USART, LL_USART_DMA_REG_DATA_RECEIVE));\n        LL_DMA_SetMemoryAddress(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, (uint32_t)lwesp_usart_rx_dma_buffer);\n        LL_DMA_SetDataLength(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM, sizeof(lwesp_usart_rx_dma_buffer));\n\n        /* Enable DMA interrupts */\n        LL_DMA_EnableIT_HT(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_TC(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_TE(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_FE(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM);\n        LL_DMA_EnableIT_DME(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM);\n\n        /*******************/\n        /*** UART TX DMA ***/\n        /*******************/\n\n        /* Enable DMA interrupts */\n        NVIC_SetPriority(LWESP_USART_DMA_TX_IRQ, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x05, 0x00));\n        NVIC_EnableIRQ(LWESP_USART_DMA_TX_IRQ);\n\n        /* Configure DMA */\n        LL_DMA_SetPeriphRequest(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, LWESP_USART_DMA_TX_REQUEST);\n        LL_DMA_SetDataTransferDirection(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM,\n                                        LL_DMA_DIRECTION_MEMORY_TO_PERIPH);\n        LL_DMA_SetStreamPriorityLevel(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, LL_DMA_PRIORITY_MEDIUM);\n        LL_DMA_SetMode(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, LL_DMA_MODE_NORMAL);\n        LL_DMA_SetPeriphIncMode(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, LL_DMA_PERIPH_NOINCREMENT);\n        LL_DMA_SetMemoryIncMode(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, LL_DMA_MEMORY_INCREMENT);\n        LL_DMA_SetPeriphSize(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, LL_DMA_PDATAALIGN_BYTE);\n        LL_DMA_SetMemorySize(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM, LL_DMA_MDATAALIGN_BYTE);\n        LL_DMA_DisableFifoMode(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM);\n        LL_DMA_SetPeriphAddress(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM,\n                                LL_USART_DMA_GetRegAddr(LWESP_USART, LL_USART_DMA_REG_DATA_TRANSMIT));\n\n        /* Enable DMA interrupts */\n        LL_DMA_EnableIT_TC(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM);\n        LL_DMA_EnableIT_TE(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM);\n\n        /*******************/\n        /***    UART     ***/\n        /*******************/\n\n        /* Enable USART interrupts */\n        NVIC_SetPriority(LWESP_USART_IRQ, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0x05, 0x00));\n        NVIC_EnableIRQ(LWESP_USART_IRQ);\n\n        /* Configure UART */\n        LL_USART_DeInit(LWESP_USART);\n        LL_USART_StructInit(&usart_init);\n        usart_init.BaudRate = baudrate;\n        usart_init.DataWidth = LL_USART_DATAWIDTH_8B;\n        usart_init.HardwareFlowControl = LL_USART_HWCONTROL_NONE;\n        usart_init.OverSampling = LL_USART_OVERSAMPLING_16;\n        usart_init.Parity = LL_USART_PARITY_NONE;\n        usart_init.StopBits = LL_USART_STOPBITS_1;\n        usart_init.TransferDirection = LL_USART_DIRECTION_TX_RX;\n        LL_USART_Init(LWESP_USART, &usart_init);\n\n        /* Enable USART interrupts and DMA request */\n        LL_USART_EnableIT_IDLE(LWESP_USART);\n        LL_USART_EnableIT_ERROR(LWESP_USART);\n        LL_USART_EnableDMAReq_RX(LWESP_USART);\n        LL_USART_EnableDMAReq_TX(LWESP_USART);\n\n        /* Reset DMA position */\n        lwesp_read_old_pos = 0;\n\n        /* Start DMA and USART */\n        LL_DMA_EnableStream(LWESP_USART_DMA_RX, LWESP_USART_DMA_RX_STREAM);\n        LL_USART_Enable(LWESP_USART);\n\n        /* Create mbox and read threads */\n        tx_event_flags_create(&lwesp_ll_event_group, \"lwesp_ll_group\");\n        tx_thread_create(&lwesp_read_thread, \"lwesp_read_thread\", prv_lwesp_read_thread_entry, 0,\n                         lwesp_read_thread_stack, sizeof(lwesp_read_thread_stack), TX_MAX_PRIORITIES / 2 - 1,\n                         TX_MAX_PRIORITIES / 2 - 1, TX_NO_TIME_SLICE, TX_AUTO_START);\n\n        lwesp_is_running = 1;\n    } else {\n        //tx_thread_sleep(10);\n        //LL_USART_Disable(LWESP_USART);\n        //usart_init.BaudRate = baudrate;\n        //LL_USART_Init(LWESP_USART, &usart_init);\n        //LL_USART_Enable(LWESP_USART);\n    }\n}\n\n#if defined(LWESP_RST_PIN)\n\n/**\n * \\brief           Hardware reset callback\n * \\param[in]       state: Set to `1` to enable reset, `0` to release\n */\nstatic uint8_t\nprv_reset_device(uint8_t state) {\n    if (state) { /* Activate reset line */\n        //LL_GPIO_ResetOutputPin(LWESP_RESET_PORT, LWESP_RESET_PIN);\n    } else {\n        //LL_GPIO_SetOutputPin(LWESP_RESET_PORT, LWESP_RESET_PIN);\n    }\n    return 1;\n}\n\n#endif /* defined(LWESP_RST_PIN) */\n\n/**\n * \\brief           Send data to ESP device over UART\n * \\param[in]       data: Pointer to data to send\n * \\param[in]       len: Number of bytes to send\n * \\return          Number of bytes sent\n */\nstatic size_t\nprv_send_data(const void* data, size_t len) {\n    const uint8_t* d = data;\n    uint8_t use_dma = 1;\n\n    /*\n     * When in DMA TX mode, application writes\n     * TX data to ring buffer for which DMA certainly has access to.\n     *\n     * As it is a non-blocking TX (we don't wait for finish),\n     * writing to buffer is faster than writing over UART hence\n     * we need to find a mechanism to be able to still write as much as fast,\n     * if such event happens.\n     *\n     * Writes to buffer are checked, and when no memory is available to write full data:\n     * - Try to force transfer (if not already on-going)\n     * - Yield thread and wait for next-time run\n     *\n     * In the meantime, DMA will trigger TC complete interrupt\n     * and clean-up used memory, ready for next transfers.\n     *\n     * To avoid such complications, allocate > 1kB memory for buffer\n     */\n    if (use_dma) {\n        size_t written = 0;\n        do {\n            written += lwrb_write(&lwesp_tx_rb, &d[written], len - written);\n            if (written < len) {\n                prv_start_tx_transfer();\n                tx_thread_relinquish();\n            }\n        } while (written < len);\n        prv_start_tx_transfer();\n    } else {\n        for (size_t i = 0; i < len; ++i, ++d) {\n            LL_USART_TransmitData8(LWESP_USART, *d);\n            while (!LL_USART_IsActiveFlag_TXE(LWESP_USART)) {}\n        }\n    }\n    return len;\n}\n\n/**\n * \\brief           Callback function called from initialization process\n */\nlwespr_t\nlwesp_ll_init(lwesp_ll_t* ll) {\n    if (!lwesp_initialized) {\n        ll->send_fn = prv_send_data; /* Set callback function to send data */\n#if defined(LWESP_RST_PIN)\n        ll->reset_fn = prv_reset_device; /* Set callback for hardware reset */\n#endif                                   /* defined(LWESP_RST_PIN) */\n\n        /* Initialize buffer for TX */\n        lwesp_tx_len = 0;\n        lwrb_init(&lwesp_tx_rb, lwesp_tx_rb_data, sizeof(lwesp_tx_rb_data));\n    }\n    prv_configure_uart(ll->uart.baudrate); /* Initialize UART for communication */\n    lwesp_initialized = 1;\n    return lwespOK;\n}\n\n/**\n * \\brief           Callback function to de-init low-level communication part\n */\nlwespr_t\nlwesp_ll_deinit(lwesp_ll_t* ll) {\n    LL_USART_Disable(LWESP_USART);\n    tx_event_flags_delete(&lwesp_ll_event_group);\n    tx_thread_delete(&lwesp_read_thread);\n\n    lwesp_initialized = 0;\n    LWESP_UNUSED(ll);\n    return lwespOK;\n}\n\n/**\n * \\brief           UART global interrupt handler\n */\nvoid\nLWESP_USART_IRQ_HANDLER(void) {\n    /* Clear all potential flags */\n    LL_USART_ClearFlag_IDLE(LWESP_USART);\n    LL_USART_ClearFlag_PE(LWESP_USART);\n    LL_USART_ClearFlag_FE(LWESP_USART);\n    LL_USART_ClearFlag_ORE(LWESP_USART);\n    LL_USART_ClearFlag_NE(LWESP_USART);\n\n    /* Set flag to wakeup thread */\n    if (lwesp_ll_event_group.tx_event_flags_group_id != TX_CLEAR_ID) {\n        tx_event_flags_set(&lwesp_ll_event_group, LWESP_LL_FLAG_DATA, TX_OR);\n    }\n}\n\n/**\n * \\brief           UART DMA RX stream handler\n */\nvoid\nLWESP_USART_DMA_RX_IRQ_HANDLER(void) {\n    LWESP_USART_DMA_RX_CLEAR_TC;\n    LWESP_USART_DMA_RX_CLEAR_HT;\n    LWESP_USART_DMA_RX_CLEAR_TE;\n\n    /* Set flag to wakeup thread */\n    if (lwesp_ll_event_group.tx_event_flags_group_id != TX_CLEAR_ID) {\n        tx_event_flags_set(&lwesp_ll_event_group, LWESP_LL_FLAG_DATA, TX_OR);\n    }\n}\n\n/**\n * \\brief           UART DMA RX stream handler\n */\nvoid\nLWESP_USART_DMA_TX_IRQ_HANDLER(void) {\n    /* React on TC event only */\n    if (LL_DMA_IsEnabledIT_TC(LWESP_USART_DMA_TX, LWESP_USART_DMA_TX_STREAM) && LWESP_USART_DMA_TX_IS_TC) {\n        LWESP_USART_DMA_TX_CLEAR_TC;\n\n        lwrb_skip(&lwesp_tx_rb, lwesp_tx_len);\n        lwesp_tx_len = 0;\n        prv_start_tx_transfer();\n    }\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32l432kc_nucleo.c",
    "content": "/**\n * \\file            lwesp_ll_stm32l432kc_nucleo.c\n * \\brief           Low-level communication with ESP device for STM32L432KC-Nucleo using DMA\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Miha CESNIK <>\n * Version:         v1.1.2-dev\n */\n\n/*\n * Default UART configuration is:\n *\n * UART:                USART1\n * STM32 TX (ESP RX):   GPIOA, GPIO_PIN_9\n * STM32 RX (ESP TX):   GPIOA, GPIO_PIN_10;\n * RESET:               GPIOA, GPIO_PIN_12\n * CH_PD:               GPIOB, GPIO_PIN_0\n * GPIO0:               GPIOA, GPIO_PIN_7\n * GPIO2:               GPIOA, GPIO_PIN_6\n *\n * USART_DMA:           DMA1\n * USART_DMA_CHANNEL:   DMA_CHANNEL_5\n * USART_DMA_REQ_NUM:   2\n */\n\n#if !__DOXYGEN__\n\n#include \"stm32l4xx_ll_bus.h\"\n#include \"stm32l4xx_ll_dma.h\"\n#include \"stm32l4xx_ll_gpio.h\"\n#include \"stm32l4xx_ll_pwr.h\"\n#include \"stm32l4xx_ll_rcc.h\"\n#include \"stm32l4xx_ll_usart.h\"\n\n/* USART */\n#define LWESP_USART                   USART1\n#define LWESP_USART_CLK               LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)\n#define LWESP_USART_IRQ               USART1_IRQn\n#define LWESP_USART_IRQHANDLER        USART1_IRQHandler\n\n/* DMA settings */\n#define LWESP_USART_DMA               DMA1\n#define LWESP_USART_DMA_CLK           LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)\n#define LWESP_USART_DMA_RX_CH         LL_DMA_CHANNEL_5\n#define LWESP_USART_DMA_RX_REQ_NUM    LL_DMA_REQUEST_2\n#define LWESP_USART_DMA_RX_IRQ        DMA1_Channel5_IRQn\n#define LWESP_USART_DMA_RX_IRQHANDLER DMA1_Channel5_IRQHandler\n\n/* DMA flags management */\n#define LWESP_USART_DMA_RX_IS_TC      LL_DMA_IsActiveFlag_TC5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_IS_HT      LL_DMA_IsActiveFlag_HT5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_TC   LL_DMA_ClearFlag_TC5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_HT   LL_DMA_ClearFlag_HT5(LWESP_USART_DMA)\n\n/* USART TX PIN */\n#define LWESP_USART_TX_PORT_CLK       LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_USART_TX_PORT           GPIOA\n#define LWESP_USART_TX_PIN            LL_GPIO_PIN_9\n#define LWESP_USART_TX_PIN_AF         LL_GPIO_AF_7\n\n/* USART RX PIN */\n#define LWESP_USART_RX_PORT_CLK       LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_USART_RX_PORT           GPIOA\n#define LWESP_USART_RX_PIN            LL_GPIO_PIN_10\n#define LWESP_USART_RX_PIN_AF         LL_GPIO_AF_7\n\n/* RESET PIN */\n#define LWESP_RESET_PORT_CLK          LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_RESET_PORT              GPIOA\n#define LWESP_RESET_PIN               LL_GPIO_PIN_12\n\n/* GPIO0 PIN */\n#define LWESP_GPIO0_PORT_CLK          LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_GPIO0_PORT              GPIOA\n#define LWESP_GPIO0_PIN               LL_GPIO_PIN_7\n\n/* GPIO2 PIN */\n#define LWESP_GPIO2_PORT_CLK          LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_GPIO2_PORT              GPIOA\n#define LWESP_GPIO2_PIN               LL_GPIO_PIN_6\n\n/* CH_PD PIN */\n#define LWESP_CH_PD_PORT_CLK          LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)\n#define LWESP_CH_PD_PORT              GPIOB\n#define LWESP_CH_PD_PIN               LL_GPIO_PIN_0\n\n/* Include STM32 generic driver */\n#include \"../system/lwesp_ll_stm32.c\"\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32l496g_discovery.c",
    "content": "/**\n * \\file            lwesp_ll_stm32l496g_discovery.c\n * \\brief           Low-level communication with ESP device for STM32L496G-Discovery using DMA\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n\n/*\n * Default UART configuration is:\n *\n * UART:                USART1\n * STM32 TX (ESP RX):   GPIOB, GPIO_PIN_6\n * STM32 RX (ESP TX):   GPIOG, GPIO_PIN_10; Note: VDDIO2 must be enabled in PWR register\n * RESET:               GPIOB, GPIO_PIN_2\n * GPIO0:               GPIOH, GPIO_PIN_2\n * GPIO2:               GPIOA, GPIO_PIN_0\n * CH_PD:               GPIOA, GPIO_PIN_4\n *\n * USART_DMA:           DMA1\n * USART_DMA_CHANNEL:   DMA_CHANNEL_5\n * USART_DMA_REQ_NUM:   2\n */\n\n#if !__DOXYGEN__\n\n#include \"stm32l4xx_ll_bus.h\"\n#include \"stm32l4xx_ll_dma.h\"\n#include \"stm32l4xx_ll_gpio.h\"\n#include \"stm32l4xx_ll_pwr.h\"\n#include \"stm32l4xx_ll_rcc.h\"\n#include \"stm32l4xx_ll_usart.h\"\n\n/* USART */\n#define LWESP_USART                   USART1\n#define LWESP_USART_CLK               LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)\n#define LWESP_USART_IRQ               USART1_IRQn\n#define LWESP_USART_IRQHANDLER        USART1_IRQHandler\n\n/* DMA settings */\n#define LWESP_USART_DMA               DMA1\n#define LWESP_USART_DMA_CLK           LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)\n#define LWESP_USART_DMA_RX_CH         LL_DMA_CHANNEL_5\n#define LWESP_USART_DMA_RX_REQ_NUM    LL_DMA_REQUEST_2\n#define LWESP_USART_DMA_RX_IRQ        DMA1_Channel5_IRQn\n#define LWESP_USART_DMA_RX_IRQHANDLER DMA1_Channel5_IRQHandler\n\n/* DMA flags management */\n#define LWESP_USART_DMA_RX_IS_TC      LL_DMA_IsActiveFlag_TC5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_IS_HT      LL_DMA_IsActiveFlag_HT5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_TC   LL_DMA_ClearFlag_TC5(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_HT   LL_DMA_ClearFlag_HT5(LWESP_USART_DMA)\n\n/* USART TX PIN */\n#define LWESP_USART_TX_PORT_CLK       LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)\n#define LWESP_USART_TX_PORT           GPIOB\n#define LWESP_USART_TX_PIN            LL_GPIO_PIN_6\n#define LWESP_USART_TX_PIN_AF         LL_GPIO_AF_7\n\n/* USART RX PIN */\n/* Since GPIOG.10 is on VDDIO2, we have to enable VDDIO2 in power management */\n#define LWESP_USART_RX_PORT_CLK                                                                                        \\\n    do {                                                                                                               \\\n        LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOG);                                                           \\\n        LL_PWR_EnableVddIO2();                                                                                         \\\n    } while (0)\n#define LWESP_USART_RX_PORT   GPIOG\n#define LWESP_USART_RX_PIN    LL_GPIO_PIN_10\n#define LWESP_USART_RX_PIN_AF LL_GPIO_AF_7\n\n/* RESET PIN */\n#define LWESP_RESET_PORT_CLK  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)\n#define LWESP_RESET_PORT      GPIOB\n#define LWESP_RESET_PIN       LL_GPIO_PIN_2\n\n/* GPIO0 PIN */\n#define LWESP_GPIO0_PORT_CLK  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_GPIO0_PORT      GPIOA\n#define LWESP_GPIO0_PIN       LL_GPIO_PIN_0\n\n/* GPIO2 PIN */\n#define LWESP_GPIO2_PORT_CLK  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH)\n#define LWESP_GPIO2_PORT      GPIOH\n#define LWESP_GPIO2_PIN       LL_GPIO_PIN_2\n\n/* CH_PD PIN */\n#define LWESP_CH_PD_PORT_CLK  LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_CH_PD_PORT      GPIOA\n#define LWESP_CH_PD_PIN       LL_GPIO_PIN_4\n\n/* Include STM32 generic driver */\n#include \"../system/lwesp_ll_stm32.c\"\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_stm32l4s5_discovery.c",
    "content": "/**\n * \\file            lwesp_ll_stm32l4s5_discovery.c\n * \\brief           Low-level communication with ESP device for B-L4S5I-IOT01A using DMA\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Neo Xiong <xiongyu0523@gmail.com>\n * Version:         v1.1.2-dev\n */\n\n/*\n * Default UART configuration is:\n *\n * UART:                UART4\n * STM32 TX (ESP RX):   GPIOA, GPIO_PIN_0\n * STM32 RX (ESP TX):   GPIOA, GPIO_PIN_1\n * RESET:               GPIOD, GPIO_PIN_14\n *\n * USART_DMA:           DMA1\n * USART_DMA_CHANNEL:   DMA_CHANNEL_6\n * USART_DMA_REQ_NUM:   LL_DMAMUX_REQ_UART4_RX\n */\n\n#if !__DOXYGEN__\n\n#define USE_FULL_LL_DRIVER\n#include \"stm32l4xx_ll_bus.h\"\n#include \"stm32l4xx_ll_dma.h\"\n#include \"stm32l4xx_ll_dmamux.h\"\n#include \"stm32l4xx_ll_gpio.h\"\n#include \"stm32l4xx_ll_pwr.h\"\n#include \"stm32l4xx_ll_rcc.h\"\n#include \"stm32l4xx_ll_usart.h\"\n\n/* UART */\n#define LWESP_USART                   UART4\n#define LWESP_USART_CLK               LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART4)\n#define LWESP_USART_IRQ               UART4_IRQn\n#define LWESP_USART_IRQHANDLER        UART4_IRQHandler\n\n/* DMAMUX settings */\n#define LWESP_USART_DMAMUX            DMAMUX1\n#define LWESP_USART_DMAMUX_CLK        LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)\n\n/* DMA settings */\n#define LWESP_USART_DMA               DMA1\n#define LWESP_USART_DMA_CLK           LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)\n#define LWESP_USART_DMA_RX_CH         LL_DMA_CHANNEL_6\n#define LWESP_USART_DMA_RX_REQ_NUM    LL_DMAMUX_REQ_UART4_RX\n#define LWESP_USART_DMA_RX_IRQ        DMA1_Channel6_IRQn\n#define LWESP_USART_DMA_RX_IRQHANDLER DMA1_Channel6_IRQHandler\n\n/* DMA flags management */\n#define LWESP_USART_DMA_RX_IS_TC      LL_DMA_IsActiveFlag_TC6(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_IS_HT      LL_DMA_IsActiveFlag_HT6(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_TC   LL_DMA_ClearFlag_TC6(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_HT   LL_DMA_ClearFlag_HT6(LWESP_USART_DMA)\n#define LWESP_USART_DMA_RX_CLEAR_TE   LL_DMA_ClearFlag_TE6(LWESP_USART_DMA)\n\n/* USART TX PIN */\n#define LWESP_USART_TX_PORT_CLK       LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_USART_TX_PORT           GPIOA\n#define LWESP_USART_TX_PIN            LL_GPIO_PIN_0\n#define LWESP_USART_TX_PIN_AF         LL_GPIO_AF_8\n\n/* USART RX PIN */\n#define LWESP_USART_RX_PORT_CLK       LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)\n#define LWESP_USART_RX_PORT           GPIOA\n#define LWESP_USART_RX_PIN            LL_GPIO_PIN_1\n#define LWESP_USART_RX_PIN_AF         LL_GPIO_AF_8\n\n/* RESET PIN */\n#define LWESP_RESET_PORT_CLK          LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD)\n#define LWESP_RESET_PORT              GPIOD\n#define LWESP_RESET_PIN               LL_GPIO_PIN_14\n\n/* Include STM32 generic driver */\n#include \"../system/lwesp_ll_stm32_threadx.c\"\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_ll_win32.c",
    "content": "/**\n * \\file            lwesp_ll_win32.c\n * \\brief           Low-level communication with ESP device for WIN32\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_input.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"system/lwesp_ll.h\"\n\n#if !__DOXYGEN__\n\nvolatile uint8_t lwesp_ll_win32_driver_ignore_data;\nstatic uint8_t initialized = 0;\nstatic HANDLE thread_handle;\nstatic volatile HANDLE com_port;    /*!< COM port handle */\nstatic uint8_t data_buffer[0x1000]; /*!< Received data array */\n\nstatic void uart_thread(void* param);\n\n/**\n * \\brief           Send data to ESP device, function called from ESP stack when we have data to send\n */\nstatic size_t\nsend_data(const void* data, size_t len) {\n    DWORD written;\n    if (com_port != NULL) {\n#if !LWESP_CFG_AT_ECHO && 0\n        const uint8_t* d = data;\n        HANDLE hConsole;\n\n        hConsole = GetStdHandle(STD_OUTPUT_HANDLE);\n        SetConsoleTextAttribute(hConsole, FOREGROUND_RED);\n        for (DWORD i = 0; i < len; ++i) {\n            printf(\"%c\", d[i]);\n        }\n        SetConsoleTextAttribute(hConsole, FOREGROUND_RED | FOREGROUND_GREEN | FOREGROUND_BLUE);\n#endif /* !LWESP_CFG_AT_ECHO */\n\n        WriteFile(com_port, data, len, &written, NULL);\n        FlushFileBuffers(com_port);\n        return written;\n    }\n    return 0;\n}\n\n/**\n * \\brief           Configure UART (USB to UART)\n * \\return          `1` if initialized, `0` otherwise\n */\nstatic uint8_t\nconfigure_uart(uint32_t baudrate) {\n    size_t i;\n    DCB dcb = {.DCBlength = sizeof(dcb)};\n\n    /*\n     * List of COM ports to probe for ESP devices\n     * This may be different on your computer\n     */\n    static const char* com_port_names[] = {\"\\\\\\\\.\\\\COM7\", \"\\\\\\\\.\\\\COM60\", \"\\\\\\\\.\\\\COM4\", \"\\\\\\\\.\\\\COM8\",\n                                           \"\\\\\\\\.\\\\COM9\", \"\\\\\\\\.\\\\COM10\", \"\\\\\\\\.\\\\COM17\"};\n\n    /* Try to open one of listed COM ports */\n    if (!initialized) {\n        printf(\"Initializing COM port first time\\r\\n\");\n        for (i = 0; i < LWESP_ARRAYSIZE(com_port_names); ++i) {\n            printf(\"Trying to open COM port %s\\r\\n\", com_port_names[i]);\n            com_port = CreateFileA(com_port_names[i], GENERIC_READ | GENERIC_WRITE, 0, 0, OPEN_EXISTING, 0, NULL);\n            if (GetCommState(com_port, &dcb)) {\n                printf(\"Successfully received info for COM port %s. Using this one..\\r\\n\", com_port_names[i]);\n                break;\n            } else {\n                printf(\"Could not get info for COM port %s\\r\\n\", com_port_names[i]);\n            }\n        }\n        if (i == LWESP_ARRAYSIZE(com_port_names)) {\n            printf(\"Could not get info for any COM port. Entering while loop\\r\\n\");\n            while (1) {\n                Sleep(1000);\n            }\n        }\n    }\n\n    /* Configure COM port parameters */\n    if (GetCommState(com_port, &dcb)) {\n        COMMTIMEOUTS timeouts;\n\n        /* Set port config */\n        dcb.BaudRate = baudrate;\n        dcb.ByteSize = 8;\n        dcb.Parity = NOPARITY;\n        dcb.StopBits = ONESTOPBIT;\n        if (SetCommState(com_port, &dcb)) {\n            /* Set timeouts config */\n            if (GetCommTimeouts(com_port, &timeouts)) {\n                /* Set timeout to return immediately from ReadFile function */\n                timeouts.ReadIntervalTimeout = MAXDWORD;\n                timeouts.ReadTotalTimeoutConstant = 0;\n                timeouts.ReadTotalTimeoutMultiplier = 0;\n                if (SetCommTimeouts(com_port, &timeouts)) {\n                    GetCommTimeouts(com_port, &timeouts);\n                } else {\n                    printf(\"[LWESP LL] Could not set port timeout config\\r\\n\");\n                }\n            } else {\n                printf(\"[LWESP LL] Could not get port timeout config\\r\\n\");\n            }\n        } else {\n            printf(\"[LWESP LL] Could not set port config\\r\\n\");\n        }\n    } else {\n        printf(\"[LWESP LL] Could not get port info\\r\\n\");\n    }\n\n    /* On first function call, create a thread to read data from COM port */\n    if (!initialized) {\n        lwesp_sys_thread_create(&thread_handle, \"lwesp_ll_thread\", uart_thread, NULL, 0, 0);\n    }\n    return 1;\n}\n\n/**\n * \\brief           UART thread\n */\nstatic void\nuart_thread(void* param) {\n    DWORD bytes_read;\n    lwesp_sys_sem_t sem;\n    FILE* file = NULL;\n\n    LWESP_UNUSED(param);\n\n    lwesp_sys_sem_create(&sem, 0); /* Create semaphore for delay functions */\n    while (com_port == NULL) {\n        lwesp_sys_sem_wait(&sem, 1); /* Add some delay with yield */\n    }\n\n    fopen_s(&file, \"log_file.txt\", \"w+\"); /* Open debug file in write mode */\n    while (1) {\n        while (com_port == NULL) {\n            lwesp_sys_sem_wait(&sem, 1);\n        }\n\n        /*\n         * Try to read data from COM port\n         * and send it to upper layer for processing\n         */\n        do {\n            ReadFile(com_port, data_buffer, sizeof(data_buffer), &bytes_read, NULL);\n            if (bytes_read > 0) {\n                HANDLE hConsole;\n                hConsole = GetStdHandle(STD_OUTPUT_HANDLE);\n#if 0\n                SetConsoleTextAttribute(hConsole, FOREGROUND_GREEN);\n                for (DWORD i = 0; i < bytes_read; ++i) {\n                    printf(\"%c\", data_buffer[i]);\n                }\n                SetConsoleTextAttribute(hConsole, FOREGROUND_RED | FOREGROUND_GREEN | FOREGROUND_BLUE);\n#endif\n\n                if (lwesp_ll_win32_driver_ignore_data) {\n                    printf(\"IGNORING..\\r\\n\");\n                    continue;\n                }\n\n                /* Send received data to input processing module */\n#if LWESP_CFG_INPUT_USE_PROCESS\n                lwesp_input_process(data_buffer, (size_t)bytes_read);\n#else  /* LWESP_CFG_INPUT_USE_PROCESS */\n                lwesp_input(data_buffer, (size_t)bytes_read);\n#endif /* !LWESP_CFG_INPUT_USE_PROCESS */\n\n                /* Write received data to output debug file */\n                if (file != NULL) {\n                    fwrite(data_buffer, 1, bytes_read, file);\n                    fflush(file);\n                }\n            }\n        } while (bytes_read == (DWORD)sizeof(data_buffer));\n\n        /* Implement delay to allow other tasks processing */\n        lwesp_sys_sem_wait(&sem, 1);\n    }\n}\n\n/**\n * \\brief           Reset device GPIO management\n */\nstatic uint8_t\nreset_device(uint8_t state) {\n    LWESP_UNUSED(state);\n    return 0; /* Hardware reset was not successful */\n}\n\n/**\n * \\brief           Callback function called from initialization process\n */\nlwespr_t\nlwesp_ll_init(lwesp_ll_t* ll) {\n#if !LWESP_CFG_MEM_CUSTOM\n    /* Step 1: Configure memory for dynamic allocations */\n    static uint8_t memory[0x10000]; /* Create memory for dynamic allocations with specific size */\n\n    /*\n     * Create memory region(s) of memory.\n     * If device has internal/external memory available,\n     * multiple memories may be used\n     */\n    lwesp_mem_region_t mem_regions[] = {{memory, sizeof(memory)}};\n    if (!initialized) {\n        lwesp_mem_assignmemory(mem_regions,\n                               LWESP_ARRAYSIZE(mem_regions)); /* Assign memory for allocations to ESP library */\n    }\n#endif /* !LWESP_CFG_MEM_CUSTOM */\n\n    /* Step 2: Set AT port send function to use when we have data to transmit */\n    if (!initialized) {\n        ll->send_fn = send_data; /* Set callback function to send data */\n        ll->reset_fn = reset_device;\n    }\n\n    /* Step 3: Configure AT port to be able to send/receive data to/from ESP device */\n    if (!configure_uart(ll->uart.baudrate)) { /* Initialize UART for communication */\n        return lwespERR;\n    }\n    initialized = 1;\n    return lwespOK;\n}\n\n/**\n * \\brief           Callback function to de-init low-level communication part\n */\nlwespr_t\nlwesp_ll_deinit(lwesp_ll_t* ll) {\n    LWESP_UNUSED(ll);\n    if (thread_handle != NULL) {\n        lwesp_sys_thread_terminate(&thread_handle);\n        thread_handle = NULL;\n    }\n    initialized = 0; /* Clear initialized flag */\n    return lwespOK;\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_mem_lwmem.c",
    "content": "/**\n * \\file            lwesp_mem_lwmem.c\n * \\brief           Dynamic memory manager implemented with LwMEM\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp.h\"\n\n/* See lwesp_mem.c file for function documentation on parameters and return values */\n\n#if LWESP_CFG_MEM_CUSTOM && !__DOXYGEN__\n\n/*\n * Before this driver can be used, user must:\n *\n *  - Configure LwMEM for thread-safety mode by enabling operating system features\n *  - Set memory regions during start of application\n */\n\n#include \"lwmem/lwmem.h\"\n\nvoid*\nlwesp_mem_malloc(size_t size) {\n    return lwmem_malloc(size);\n}\n\nvoid*\nlwesp_mem_realloc(void* ptr, size_t size) {\n    return lwmem_realloc(ptr, size);\n}\n\nvoid*\nlwesp_mem_calloc(size_t num, size_t size) {\n    return lwmem_calloc(num, size);\n}\n\nvoid\nlwesp_mem_free(void* ptr) {\n    lwmem_free(ptr);\n}\n\n#endif /* LWESP_CFG_MEM_CUSTOM && !__DOXYGEN__ */"
  },
  {
    "path": "lwesp/src/system/lwesp_mem_posix.c",
    "content": "/**\n * \\file            lwesp_mem_lwmem.c\n * \\brief           Dynamic memory manager implemented with LwMEM\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          imi415 <imi415.public@gmail.com>\n * Version:         v1.1.1-dev\n */\n#include \"lwesp/lwesp.h\"\n\n/* See lwesp_mem.c file for function documentation on parameters and return values */\n\n#if LWESP_CFG_MEM_CUSTOM && !__DOXYGEN__\n\n/*\n * Before this driver can be used, user must:\n *\n *  - Configure LwMEM for thread-safety mode by enabling operating system features\n *  - Set memory regions during start of application\n */\n\n#include <stdlib.h>\n\nvoid*\nlwesp_mem_malloc(size_t size) {\n    return malloc(size);\n}\n\nvoid*\nlwesp_mem_realloc(void* ptr, size_t size) {\n    return realloc(ptr, size);\n}\n\nvoid*\nlwesp_mem_calloc(size_t num, size_t size) {\n    return calloc(num, size);\n}\n\nvoid\nlwesp_mem_free(void* ptr) {\n    free(ptr);\n}\n\n#endif /* LWESP_CFG_MEM_CUSTOM && !__DOXYGEN__ */"
  },
  {
    "path": "lwesp/src/system/lwesp_mem_threadx.c",
    "content": "/**\n * \\file            lwesp_mem_lwmem.c\n * \\brief           Dynamic memory manager implemented with LwMEM\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp.h\"\n#include \"tx_api.h\"\n\n#if !__DOXYGEN__\n\n/* Byte pool is defined externally, in the lwesp_sys_threadx.c file */\nextern TX_BYTE_POOL* lwesp_threadx_byte_pool;\n\nvoid*\nlwesp_mem_malloc(size_t size) {\n    void* pointer;\n    return tx_byte_allocate(lwesp_threadx_byte_pool, &pointer, size, TX_NO_WAIT) == TX_SUCCESS ? pointer : NULL;\n}\n\nvoid*\nlwesp_mem_realloc(void* ptr, size_t size) {\n    /* No need to support it */\n    return NULL;\n}\n\nvoid*\nlwesp_mem_calloc(size_t num, size_t size) {\n    size_t total = num * size;\n    void* pointer = lwesp_mem_malloc(total);\n    TX_MEMSET(pointer, 0, total);\n    return pointer;\n}\n\nvoid\nlwesp_mem_free(void* ptr) {\n    (VOID) tx_byte_release(ptr);\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_sys_cmsis_os.c",
    "content": "/**\n * \\file            lwesp_sys_cmsis_os.c\n * \\brief           System dependent functions for CMSIS based operating system\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include \"cmsis_os.h\"\n#include \"system/lwesp_sys.h\"\n\n#if !__DOXYGEN__\n\nstatic osMutexId_t sys_mutex;\n\nuint8_t\nlwesp_sys_init(void) {\n    lwesp_sys_mutex_create(&sys_mutex);\n    return 1;\n}\n\nuint32_t\nlwesp_sys_now(void) {\n    return osKernelGetTickCount();\n}\n\nuint8_t\nlwesp_sys_protect(void) {\n    lwesp_sys_mutex_lock(&sys_mutex);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_unprotect(void) {\n    lwesp_sys_mutex_unlock(&sys_mutex);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_create(lwesp_sys_mutex_t* p) {\n    const osMutexAttr_t attr = {\n        .attr_bits = osMutexRecursive,\n        .name = \"lwesp_mutex\",\n    };\n    return (*p = osMutexNew(&attr)) != NULL;\n}\n\nuint8_t\nlwesp_sys_mutex_delete(lwesp_sys_mutex_t* p) {\n    return osMutexDelete(*p) == osOK;\n}\n\nuint8_t\nlwesp_sys_mutex_lock(lwesp_sys_mutex_t* p) {\n    return osMutexAcquire(*p, osWaitForever) == osOK;\n}\n\nuint8_t\nlwesp_sys_mutex_unlock(lwesp_sys_mutex_t* p) {\n    return osMutexRelease(*p) == osOK;\n}\n\nuint8_t\nlwesp_sys_mutex_isvalid(lwesp_sys_mutex_t* p) {\n    return p != NULL && *p != NULL;\n}\n\nuint8_t\nlwesp_sys_mutex_invalid(lwesp_sys_mutex_t* p) {\n    *p = LWESP_SYS_MUTEX_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_sem_create(lwesp_sys_sem_t* p, uint8_t cnt) {\n    const osSemaphoreAttr_t attr = {\n        .name = \"lwesp_sem\",\n    };\n    return (*p = osSemaphoreNew(1, cnt > 0 ? 1 : 0, &attr)) != NULL;\n}\n\nuint8_t\nlwesp_sys_sem_delete(lwesp_sys_sem_t* p) {\n    return osSemaphoreDelete(*p) == osOK;\n}\n\nuint32_t\nlwesp_sys_sem_wait(lwesp_sys_sem_t* p, uint32_t timeout) {\n    uint32_t tick = osKernelSysTick();\n    return (osSemaphoreAcquire(*p, timeout == 0 ? osWaitForever : timeout) == osOK) ? (osKernelSysTick() - tick)\n                                                                                    : LWESP_SYS_TIMEOUT;\n}\n\nuint8_t\nlwesp_sys_sem_release(lwesp_sys_sem_t* p) {\n    return osSemaphoreRelease(*p) == osOK;\n}\n\nuint8_t\nlwesp_sys_sem_isvalid(lwesp_sys_sem_t* p) {\n    return p != NULL && *p != NULL;\n}\n\nuint8_t\nlwesp_sys_sem_invalid(lwesp_sys_sem_t* p) {\n    *p = LWESP_SYS_SEM_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_create(lwesp_sys_mbox_t* b, size_t size) {\n    const osMessageQueueAttr_t attr = {\n        .name = \"lwesp_mbox\",\n    };\n    return (*b = osMessageQueueNew(size, sizeof(void*), &attr)) != NULL;\n}\n\nuint8_t\nlwesp_sys_mbox_delete(lwesp_sys_mbox_t* b) {\n    if (osMessageQueueGetCount(*b) > 0) {\n        return 0;\n    }\n    return osMessageQueueDelete(*b) == osOK;\n}\n\nuint32_t\nlwesp_sys_mbox_put(lwesp_sys_mbox_t* b, void* m) {\n    uint32_t tick = osKernelSysTick();\n    return osMessageQueuePut(*b, &m, 0, osWaitForever) == osOK ? (osKernelSysTick() - tick) : LWESP_SYS_TIMEOUT;\n}\n\nuint32_t\nlwesp_sys_mbox_get(lwesp_sys_mbox_t* b, void** m, uint32_t timeout) {\n    uint32_t tick = osKernelSysTick();\n    return (osMessageQueueGet(*b, m, NULL, timeout == 0 ? osWaitForever : timeout) == osOK) ? (osKernelSysTick() - tick)\n                                                                                            : LWESP_SYS_TIMEOUT;\n}\n\nuint8_t\nlwesp_sys_mbox_putnow(lwesp_sys_mbox_t* b, void* m) {\n    return osMessageQueuePut(*b, &m, 0, 0) == osOK;\n}\n\nuint8_t\nlwesp_sys_mbox_getnow(lwesp_sys_mbox_t* b, void** m) {\n    return osMessageQueueGet(*b, m, NULL, 0) == osOK;\n}\n\nuint8_t\nlwesp_sys_mbox_isvalid(lwesp_sys_mbox_t* b) {\n    return b != NULL && *b != NULL;\n}\n\nuint8_t\nlwesp_sys_mbox_invalid(lwesp_sys_mbox_t* b) {\n    *b = LWESP_SYS_MBOX_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_create(lwesp_sys_thread_t* t, const char* name, lwesp_sys_thread_fn thread_func, void* const arg,\n                        size_t stack_size, lwesp_sys_thread_prio_t prio) {\n    lwesp_sys_thread_t id;\n    const osThreadAttr_t thread_attr = {.name = (char*)name,\n                                        .priority = (osPriority)prio,\n                                        .stack_size = stack_size > 0 ? stack_size : LWESP_SYS_THREAD_SS};\n\n    id = osThreadNew(thread_func, arg, &thread_attr);\n    if (t != NULL) {\n        *t = id;\n    }\n    return id != NULL;\n}\n\nuint8_t\nlwesp_sys_thread_terminate(lwesp_sys_thread_t* t) {\n    if (t != NULL) {\n        osThreadTerminate(*t);\n    } else {\n        osThreadExit();\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_yield(void) {\n    osThreadYield();\n    return 1;\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_sys_freertos.c",
    "content": "/**\n * \\file            lwesp_sys_freertos.c\n * \\brief           System dependant functions for FreeRTOS\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Adrian Carpenter (FreeRTOS port)\n * Version:         v1.1.2-dev\n */\n#include \"FreeRTOS.h\"\n#include \"semphr.h\"\n#include \"system/lwesp_sys.h\"\n#include \"task.h\"\n\n#if !__DOXYGEN__\n\n/* Mutex ID for main protection */\nstatic SemaphoreHandle_t sys_mutex;\n\ntypedef struct {\n    void* d;\n} freertos_mbox_t;\n\nuint8_t\nlwesp_sys_init(void) {\n    sys_mutex = xSemaphoreCreateMutex();\n    return sys_mutex == NULL ? 0 : 1;\n}\n\nuint32_t\nlwesp_sys_now(void) {\n    return xTaskGetTickCount() * portTICK_PERIOD_MS;\n}\n\nuint8_t\nlwesp_sys_protect(void) {\n    lwesp_sys_mutex_lock(&sys_mutex);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_unprotect(void) {\n    lwesp_sys_mutex_unlock(&sys_mutex);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_create(lwesp_sys_mutex_t* p) {\n    *p = xSemaphoreCreateRecursiveMutex();\n    return *p != NULL;\n}\n\nuint8_t\nlwesp_sys_mutex_delete(lwesp_sys_mutex_t* p) {\n    vSemaphoreDelete(*p);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_lock(lwesp_sys_mutex_t* p) {\n    return xSemaphoreTakeRecursive(*p, portMAX_DELAY) == pdPASS;\n}\n\nuint8_t\nlwesp_sys_mutex_unlock(lwesp_sys_mutex_t* p) {\n    return xSemaphoreGiveRecursive(*p) == pdPASS;\n}\n\nuint8_t\nlwesp_sys_mutex_isvalid(lwesp_sys_mutex_t* p) {\n    return p != NULL && *p != NULL;\n}\n\nuint8_t\nlwesp_sys_mutex_invalid(lwesp_sys_mutex_t* p) {\n    *p = LWESP_SYS_MUTEX_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_sem_create(lwesp_sys_sem_t* p, uint8_t cnt) {\n    *p = xSemaphoreCreateBinary();\n\n    if (*p != NULL && cnt) {\n        xSemaphoreGive(*p);\n    }\n    return *p != NULL;\n}\n\nuint8_t\nlwesp_sys_sem_delete(lwesp_sys_sem_t* p) {\n    vSemaphoreDelete(*p);\n    return 1;\n}\n\nuint32_t\nlwesp_sys_sem_wait(lwesp_sys_sem_t* p, uint32_t timeout) {\n    uint32_t t = xTaskGetTickCount();\n    return xSemaphoreTake(*p, !timeout ? portMAX_DELAY : pdMS_TO_TICKS(timeout)) == pdPASS\n               ? ((xTaskGetTickCount() - t) * portTICK_PERIOD_MS)\n               : LWESP_SYS_TIMEOUT;\n}\n\nuint8_t\nlwesp_sys_sem_release(lwesp_sys_sem_t* p) {\n    return xSemaphoreGive(*p) == pdPASS;\n}\n\nuint8_t\nlwesp_sys_sem_isvalid(lwesp_sys_sem_t* p) {\n    return p != NULL && *p != NULL;\n}\n\nuint8_t\nlwesp_sys_sem_invalid(lwesp_sys_sem_t* p) {\n    *p = LWESP_SYS_SEM_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_create(lwesp_sys_mbox_t* b, size_t size) {\n    *b = xQueueCreate(size, sizeof(freertos_mbox_t));\n    return *b != NULL;\n}\n\nuint8_t\nlwesp_sys_mbox_delete(lwesp_sys_mbox_t* b) {\n    if (uxQueueMessagesWaiting(*b)) {\n        return 0;\n    }\n    vQueueDelete(*b);\n    return 1;\n}\n\nuint32_t\nlwesp_sys_mbox_put(lwesp_sys_mbox_t* b, void* m) {\n    freertos_mbox_t mb;\n    uint32_t t = xTaskGetTickCount();\n\n    mb.d = m;\n    xQueueSend(*b, &mb, portMAX_DELAY);\n    return xTaskGetTickCount() - t;\n}\n\nuint32_t\nlwesp_sys_mbox_get(lwesp_sys_mbox_t* b, void** m, uint32_t timeout) {\n    freertos_mbox_t mb;\n    uint32_t t = xTaskGetTickCount();\n\n    if (xQueueReceive(*b, &mb, !timeout ? portMAX_DELAY : pdMS_TO_TICKS(timeout))) {\n        *m = mb.d;\n        return (xTaskGetTickCount() - t) * portTICK_PERIOD_MS;\n    }\n    return LWESP_SYS_TIMEOUT;\n}\n\nuint8_t\nlwesp_sys_mbox_putnow(lwesp_sys_mbox_t* b, void* m) {\n    freertos_mbox_t mb;\n\n    mb.d = m;\n    return xQueueSendFromISR(*b, &mb, 0) == pdPASS;\n}\n\nuint8_t\nlwesp_sys_mbox_getnow(lwesp_sys_mbox_t* b, void** m) {\n    freertos_mbox_t mb;\n\n    if (xQueueReceive(*b, &mb, 0)) {\n        *m = mb.d;\n        return 1;\n    }\n    return 0;\n}\n\nuint8_t\nlwesp_sys_mbox_isvalid(lwesp_sys_mbox_t* b) {\n    return b != NULL && *b != NULL;\n}\n\nuint8_t\nlwesp_sys_mbox_invalid(lwesp_sys_mbox_t* b) {\n    *b = LWESP_SYS_MBOX_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_create(lwesp_sys_thread_t* t, const char* name, lwesp_sys_thread_fn thread_func, void* const arg,\n                        size_t stack_size, lwesp_sys_thread_prio_t prio) {\n    return xTaskCreate(thread_func, name, stack_size / sizeof(portSTACK_TYPE), arg, prio, t) == pdPASS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_thread_terminate(lwesp_sys_thread_t* t) {\n    vTaskDelete(*t);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_yield(void) {\n    taskYIELD();\n    return 1;\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_sys_posix.c",
    "content": "/**\n * \\file            lwesp_sys_posix.c\n * \\brief           System dependant functions for WIN32\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          imi415 <imi415.public@gmail.com>\n * Version:         v1.1.2-dev\n */\n#include <errno.h>\n#include <pthread.h>\n#include <semaphore.h>\n#include <time.h>\n\n#include \"system/lwesp_sys.h\"\n\n#if !__DOXYGEN__\n\ntypedef void* (*lwesp_sys_posix_thread_fn)(void*);\n\n/**\n * \\brief           Custom message queue implementation for WIN32\n */\ntypedef struct {\n    lwesp_sys_sem_t sem_not_empty; /*!< Semaphore indicates not empty */\n    lwesp_sys_sem_t sem_not_full;  /*!< Semaphore indicates not full */\n    lwesp_sys_sem_t sem;           /*!< Semaphore to lock access */\n    size_t in, out, size;\n    void* entries[1];\n} posix_mbox_t;\n\n/* Mutex ID for main protection */\nstatic pthread_mutex_t sys_mutex;\nstatic pthread_mutexattr_t sys_mutex_attr;\n\n/**\n * \\brief           Check if message box is full\n * \\param[in]       m: Message box handle\n * \\return          1 if full, 0 otherwise\n */\nstatic uint8_t\nmbox_is_full(posix_mbox_t* m) {\n    size_t size = 0;\n    if (m->in > m->out) {\n        size = (m->in - m->out);\n    } else if (m->out > m->in) {\n        size = m->size - m->out + m->in;\n    }\n    return size == m->size - 1;\n}\n\n/**\n * \\brief           Check if message box is empty\n * \\param[in]       m: Message box handle\n * \\return          1 if empty, 0 otherwise\n */\nstatic uint8_t\nmbox_is_empty(posix_mbox_t* m) {\n    return m->in == m->out;\n}\n\nuint8_t\nlwesp_sys_init(void) {\n    if (pthread_mutexattr_init(&sys_mutex_attr) != 0) {\n        return 0;\n    }\n\n    if (pthread_mutexattr_settype(&sys_mutex_attr, PTHREAD_MUTEX_RECURSIVE) != 0) {\n        return 0;\n    }\n\n    /* pthread_mutex_init return 0 on success */\n    if (pthread_mutex_init(&sys_mutex, &sys_mutex_attr) != 0) {\n        return 0;\n    }\n\n    return 1;\n}\n\nuint32_t\nlwesp_sys_now(void) {\n    struct timespec tp;\n    if (clock_gettime(CLOCK_MONOTONIC, &tp) != 0) {\n        return 0;\n    }\n    uint32_t msec = (tp.tv_sec * 1000 + tp.tv_nsec / 1000000) & 0xFFFFFFFFU;\n\n    return msec;\n}\n\n#if LWESP_CFG_OS\n\nuint8_t\nlwesp_sys_protect(void) {\n    pthread_mutex_lock(&sys_mutex);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_unprotect(void) {\n    pthread_mutex_unlock(&sys_mutex);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_create(lwesp_sys_mutex_t* p) {\n    *p = malloc(sizeof(pthread_mutex_t));\n    if (*p == NULL) {\n        return 0;\n    }\n\n    if (pthread_mutex_init(*p, NULL) != 0) {\n        free(*p);\n        return 0;\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_delete(lwesp_sys_mutex_t* p) {\n    if (pthread_mutex_destroy(*p) != 0) {\n        return 0;\n    }\n\n    free(*p);\n\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_lock(lwesp_sys_mutex_t* p) {\n    if (pthread_mutex_lock(*p) != 0) {\n        return 0;\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_unlock(lwesp_sys_mutex_t* p) {\n    if (pthread_mutex_unlock(*p) != 0) {\n        return 0;\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_isvalid(lwesp_sys_mutex_t* p) {\n    if (p == NULL || *p == NULL) {\n        return 0;\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_invalid(lwesp_sys_mutex_t* p) {\n    *p = NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_sem_create(lwesp_sys_sem_t* p, uint8_t cnt) {\n    *p = malloc(sizeof(sem_t));\n    if (*p == NULL) {\n        return 0;\n    }\n\n    /* sem_init returns 0 on success\n    * This function assumes a binary semaphore\n    * should be created in some ports.\n    */\n    if (sem_init(*p, 0, !!cnt) != 0) {\n        free(*p);\n        return 0;\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_sem_delete(lwesp_sys_sem_t* p) {\n    if (sem_destroy(*p) != 0) {\n        return 0;\n    }\n\n    free(*p);\n\n    return 1;\n}\n\nuint32_t\nlwesp_sys_sem_wait(lwesp_sys_sem_t* p, uint32_t timeout) {\n    struct timespec ts;\n    int ret;\n\n    uint32_t t_start = lwesp_sys_now();\n\n    /* Note that timedwait requires CLOCK_REALTIME, not CLOCK_MONOTONIC. */\n    if (clock_gettime(CLOCK_REALTIME, &ts) != 0) {\n        return 0;\n    }\n\n    if (timeout == 0) {\n        ret = sem_wait(*p);\n    } else {\n        /* Calculate new timespec values based on timeout. */\n        time_t timeout_sec = timeout / 1000;\n        time_t timeout_nsec = (timeout % 1000) * 1000000; /* 1E6 */\n        ts.tv_sec += timeout_sec;\n        ts.tv_nsec += timeout_nsec;\n        if (ts.tv_nsec > 1000000000) { /* 1E9 */\n            ts.tv_sec += 1;\n            ts.tv_nsec -= 1000000000;\n        }\n\n        ret = sem_timedwait(*p, &ts);\n    }\n\n    if (ret != 0) {\n        return LWESP_SYS_TIMEOUT;\n    }\n    return lwesp_sys_now() - t_start;\n}\n\nuint8_t\nlwesp_sys_sem_release(lwesp_sys_sem_t* p) {\n    if (sem_post(*p) != 0) {\n        return 0;\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_sem_isvalid(lwesp_sys_sem_t* p) {\n    if (p == NULL || *p == NULL) {\n        return 0;\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_sem_invalid(lwesp_sys_sem_t* p) {\n    *p = NULL;\n\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_create(lwesp_sys_mbox_t* b, size_t size) {\n    posix_mbox_t* mbox;\n\n    *b = 0;\n\n    mbox = malloc(sizeof(*mbox) + size * sizeof(void*));\n    if (mbox != NULL) {\n        memset(mbox, 0x00, sizeof(*mbox));\n        mbox->size = size + 1; /* Set it to 1 more as cyclic buffer has only one less than size */\n        lwesp_sys_sem_create(&mbox->sem, 1);\n        lwesp_sys_sem_create(&mbox->sem_not_empty, 0);\n        lwesp_sys_sem_create(&mbox->sem_not_full, 0);\n        *b = mbox;\n    }\n    return *b != NULL;\n}\n\nuint8_t\nlwesp_sys_mbox_delete(lwesp_sys_mbox_t* b) {\n    posix_mbox_t* mbox = *b;\n    lwesp_sys_sem_delete(&mbox->sem);\n    lwesp_sys_sem_delete(&mbox->sem_not_full);\n    lwesp_sys_sem_delete(&mbox->sem_not_empty);\n    free(mbox);\n    return 1;\n}\n\nuint32_t\nlwesp_sys_mbox_put(lwesp_sys_mbox_t* b, void* m) {\n    posix_mbox_t* mbox = *b;\n    uint32_t time = lwesp_sys_now(); /* Get start time */\n\n    lwesp_sys_sem_wait(&mbox->sem, 0); /* Wait for access */\n\n    /*\n     * Since function is blocking until ready to write something to queue,\n     * wait and release the semaphores to allow other threads\n     * to process the queue before we can write new value.\n     */\n    while (mbox_is_full(mbox)) {\n        lwesp_sys_sem_release(&mbox->sem);          /* Release semaphore */\n        lwesp_sys_sem_wait(&mbox->sem_not_full, 0); /* Wait for semaphore indicating not full */\n        lwesp_sys_sem_wait(&mbox->sem, 0);          /* Wait availability again */\n    }\n    mbox->entries[mbox->in] = m;\n    if (++mbox->in >= mbox->size) {\n        mbox->in = 0;\n    }\n    lwesp_sys_sem_release(&mbox->sem_not_empty); /* Signal non-empty state */\n    lwesp_sys_sem_release(&mbox->sem);           /* Release access for other threads */\n    return lwesp_sys_now() - time;\n}\n\nuint32_t\nlwesp_sys_mbox_get(lwesp_sys_mbox_t* b, void** m, uint32_t timeout) {\n    posix_mbox_t* mbox = *b;\n    uint32_t time;\n\n    time = lwesp_sys_now();\n\n    /* Get exclusive access to message queue */\n    if (lwesp_sys_sem_wait(&mbox->sem, timeout) == LWESP_SYS_TIMEOUT) {\n        return LWESP_SYS_TIMEOUT;\n    }\n    while (mbox_is_empty(mbox)) {\n        lwesp_sys_sem_release(&mbox->sem);\n        if (lwesp_sys_sem_wait(&mbox->sem_not_empty, timeout) == LWESP_SYS_TIMEOUT) {\n            return LWESP_SYS_TIMEOUT;\n        }\n        lwesp_sys_sem_wait(&mbox->sem, timeout);\n    }\n    *m = mbox->entries[mbox->out];\n    if (++mbox->out >= mbox->size) {\n        mbox->out = 0;\n    }\n    lwesp_sys_sem_release(&mbox->sem_not_full);\n    lwesp_sys_sem_release(&mbox->sem);\n\n    return lwesp_sys_now() - time;\n}\n\nuint8_t\nlwesp_sys_mbox_putnow(lwesp_sys_mbox_t* b, void* m) {\n    posix_mbox_t* mbox = *b;\n\n    lwesp_sys_sem_wait(&mbox->sem, 0);\n    if (mbox_is_full(mbox)) {\n        lwesp_sys_sem_release(&mbox->sem);\n        return 0;\n    }\n    mbox->entries[mbox->in] = m;\n    if (mbox->in == mbox->out) {\n        lwesp_sys_sem_release(&mbox->sem_not_empty);\n    }\n    if (++mbox->in >= mbox->size) {\n        mbox->in = 0;\n    }\n    lwesp_sys_sem_release(&mbox->sem);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_getnow(lwesp_sys_mbox_t* b, void** m) {\n    posix_mbox_t* mbox = *b;\n\n    lwesp_sys_sem_wait(&mbox->sem, 0); /* Wait exclusive access */\n    if (mbox->in == mbox->out) {\n        lwesp_sys_sem_release(&mbox->sem); /* Release access */\n        return 0;\n    }\n\n    *m = mbox->entries[mbox->out];\n    if (++mbox->out >= mbox->size) {\n        mbox->out = 0;\n    }\n    lwesp_sys_sem_release(&mbox->sem_not_full); /* Queue not full anymore */\n    lwesp_sys_sem_release(&mbox->sem);          /* Release semaphore */\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_isvalid(lwesp_sys_mbox_t* b) {\n    return b != NULL && *b != NULL;\n}\n\nuint8_t\nlwesp_sys_mbox_invalid(lwesp_sys_mbox_t* b) {\n    *b = LWESP_SYS_MBOX_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_create(lwesp_sys_thread_t* t, const char* name, lwesp_sys_thread_fn thread_func, void* const arg,\n                        size_t stack_size, lwesp_sys_thread_prio_t prio) {\n\n    pthread_t* new_thread = malloc(sizeof(pthread_t));\n    if (new_thread == NULL) {\n        return 0;\n    }\n\n    if (pthread_create(new_thread, NULL, (lwesp_sys_posix_thread_fn)thread_func, arg) != 0) {\n        free(*t);\n        return 0;\n    };\n\n    if (t != NULL) {\n        *t = new_thread;\n    } else {\n        free(new_thread);\n    }\n\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_terminate(lwesp_sys_thread_t* t) {\n    if (t != NULL && *t != NULL) {\n        if (pthread_cancel(**t) != 0) {\n            return 0;\n        }\n\n        free(*t);\n    }\n\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_yield(void) {\n    /* Not implemented. */\n    return 1;\n}\n\n#endif /* LWESP_CFG_OS */\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_sys_threadx.c",
    "content": "/**\n * \\file            lwesp_sys_threadx.c\n * \\brief           System dependant functions\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the follwing conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Author:          Neo Xiong <xiongyu0523@gmail.com>\n * Version:         v1.1.2-dev\n */\n#include \"lwesp/lwesp_mem.h\"\n#include \"system/lwesp_sys.h\"\n#include \"tx_api.h\"\n\n/* Custom memory ThreadX implementation must be done to use this feature */\n#if LWESP_CFG_THREADX_IDLE_THREAD_EXTENSION && !LWESP_CFG_MEM_CUSTOM\n#error \"LWESP_CFG_MEM_CUSTOM must be enabled to use LWESP_CFG_THREADX_IDLE_THREAD_EXTENSION feature\"\n#endif\n\n#if !__DOXYGEN__\n\n/* Main LwESP byte pool handle */\nTX_BYTE_POOL* lwesp_threadx_byte_pool;\n\n/* If user will not provide its own byte pool from app, create one here */\n#if !LWESP_CFG_THREADX_CUSTOM_MEM_BYTE_POOL\n\n/* ThreadX memory pool definition */\n#if !defined(LWESP_MEM_SIZE)\n#define LWESP_MEM_SIZE 0x2000\n#endif\nstatic UCHAR byte_pool_mem[LWESP_MEM_SIZE];\nstatic TX_BYTE_POOL byte_pool;\n\n#else\n\n/**\n * \\brief           Set byte pool handle for memory allocation\n * Byte pools are usually externally created by users\n *\n * This function shall be called before \\ref lwesp_init\n *\n * \\param[in]       bp: Handle to external byte pool\n */\nvoid\nlwesp_sys_preinit_threadx_set_bytepool_handle(TX_BYTE_POOL* bp) {\n    lwesp_threadx_byte_pool = bp;\n}\n\n#endif\n\n/* Module private variables */\nstatic TX_MUTEX sys_mutex;\n\n/* Macros to convert from milliseconds to ticks and opposite */\n#define TICKS_TO_MS(ticks) ((ticks) * (1000 / TX_TIMER_TICKS_PER_SECOND))\n#define MS_TO_TICKS(ms)    ((ms)*TX_TIMER_TICKS_PER_SECOND / 1000)\n\nuint8_t\nlwesp_sys_init(void) {\n    UINT status = TX_SUCCESS;\n\n#if !LWESP_CFG_THREADX_CUSTOM_MEM_BYTE_POOL\n    status = tx_byte_pool_create(&byte_pool, \"lwesp_byte_pool\", byte_pool_mem, LWESP_MEM_SIZE);\n    if (status == TX_SUCCESS) {\n        status = lwesp_sys_mutex_create(&sys_mutex) ? TX_SUCCESS : TX_NO_MEMORY;\n    }\n    lwesp_threadx_byte_pool = &byte_pool;\n#else  /* LWESP_CFG_THREADX_CUSTOM_MEM_BYTE_POOL */\n    lwesp_sys_mutex_create(&sys_mutex);\n#endif /* !LWESP_CFG_THREADX_CUSTOM_MEM_BYTE_POOL */\n    return status == TX_SUCCESS ? 1 : 0;\n}\n\nuint32_t\nlwesp_sys_now(void) {\n    return TICKS_TO_MS(tx_time_get());\n}\n\nuint8_t\nlwesp_sys_protect(void) {\n    return lwesp_sys_mutex_lock(&sys_mutex);\n}\n\nuint8_t\nlwesp_sys_unprotect(void) {\n    return lwesp_sys_mutex_unlock(&sys_mutex);\n}\n\nuint8_t\nlwesp_sys_mutex_create(lwesp_sys_mutex_t* p) {\n    return tx_mutex_create(p, TX_NULL, TX_INHERIT) == TX_SUCCESS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_mutex_delete(lwesp_sys_mutex_t* p) {\n    return tx_mutex_delete(p) == TX_SUCCESS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_mutex_lock(lwesp_sys_mutex_t* p) {\n    return tx_mutex_get(p, TX_WAIT_FOREVER) == TX_SUCCESS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_mutex_unlock(lwesp_sys_mutex_t* p) {\n    return tx_mutex_put(p) == TX_SUCCESS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_mutex_isvalid(lwesp_sys_mutex_t* p) {\n    return p->tx_mutex_id != TX_CLEAR_ID ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_mutex_invalid(lwesp_sys_mutex_t* p) {\n    /* No need actions since all invalid are following delete, and delete make sure it is invalid */\n    return 1;\n}\n\nuint8_t\nlwesp_sys_sem_create(lwesp_sys_sem_t* p, uint8_t cnt) {\n    return tx_semaphore_create(p, \"lwesp_sem\", cnt) == TX_SUCCESS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_sem_delete(lwesp_sys_sem_t* p) {\n    return tx_semaphore_delete(p) == TX_SUCCESS ? 1 : 0;\n}\n\nuint32_t\nlwesp_sys_sem_wait(lwesp_sys_sem_t* p, uint32_t timeout) {\n    ULONG start = tx_time_get();\n    return tx_semaphore_get(p, !timeout ? TX_WAIT_FOREVER : MS_TO_TICKS(timeout)) == TX_SUCCESS\n               ? TICKS_TO_MS(tx_time_get() - start)\n               : LWESP_SYS_TIMEOUT;\n}\n\nuint8_t\nlwesp_sys_sem_release(lwesp_sys_sem_t* p) {\n    return tx_semaphore_put(p) == TX_SUCCESS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_sem_isvalid(lwesp_sys_sem_t* p) {\n    return p->tx_semaphore_id != TX_CLEAR_ID ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_sem_invalid(lwesp_sys_sem_t* p) {\n    /* No need actions since all invalid are following delete, and delete make sure it is invalid */\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_create(lwesp_sys_mbox_t* b, size_t size) {\n    uint8_t rt = 0;\n    ULONG queue_total_size = size * sizeof(void*);\n    void* queue_mem = lwesp_mem_malloc(queue_total_size);\n    if (queue_mem != NULL) {\n        if (tx_queue_create(b, TX_NULL, sizeof(void*) / sizeof(ULONG), queue_mem, queue_total_size) == TX_SUCCESS) {\n            rt = 1;\n        } else {\n            lwesp_mem_free(queue_mem);\n        }\n    }\n    return rt;\n}\n\nuint8_t\nlwesp_sys_mbox_delete(lwesp_sys_mbox_t* b) {\n    (VOID) tx_queue_delete(b);\n    lwesp_mem_free(b->tx_queue_start);\n    return 1;\n}\n\nuint32_t\nlwesp_sys_mbox_put(lwesp_sys_mbox_t* b, void* m) {\n    ULONG start = tx_time_get();\n    (VOID) tx_queue_send(b, &m, TX_WAIT_FOREVER);\n    return tx_time_get() - start;\n}\n\nuint32_t\nlwesp_sys_mbox_get(lwesp_sys_mbox_t* b, void** m, uint32_t timeout) {\n    ULONG start = tx_time_get();\n    return tx_queue_receive(b, m, !timeout ? TX_WAIT_FOREVER : MS_TO_TICKS(timeout)) == TX_SUCCESS\n               ? TICKS_TO_MS(tx_time_get() - start)\n               : LWESP_SYS_TIMEOUT;\n}\n\nuint8_t\nlwesp_sys_mbox_putnow(lwesp_sys_mbox_t* b, void* m) {\n    return tx_queue_send(b, &m, TX_NO_WAIT) == TX_SUCCESS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_mbox_getnow(lwesp_sys_mbox_t* b, void** m) {\n    return tx_queue_receive(b, m, TX_NO_WAIT) == TX_SUCCESS ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_mbox_isvalid(lwesp_sys_mbox_t* b) {\n    return b->tx_queue_id != TX_CLEAR_ID ? 1 : 0;\n}\n\nuint8_t\nlwesp_sys_mbox_invalid(lwesp_sys_mbox_t* b) {\n    /* No need actions since all invalid are following delete, and delete make sure it is invalid */\n    return 1;\n}\n\n#if LWESP_CFG_THREADX_IDLE_THREAD_EXTENSION\n\nuint8_t\nlwesp_sys_thread_create(lwesp_sys_thread_t* t, const char* name, lwesp_sys_thread_fn thread_func, void* const arg,\n                        size_t stack_size, lwesp_sys_thread_prio_t prio) {\n    void* stack_ptr = NULL;\n    lwesp_sys_thread_t* t_handle;\n    uint8_t t_handle_dynamic = 0;\n\n    /* First process thread object */\n    if (t != NULL) {\n        t_handle = t; /* Use static handle from parameter */\n    } else if (tx_byte_allocate(lwesp_threadx_byte_pool, (void*)&t_handle, sizeof(*t_handle), TX_NO_WAIT)\n               == TX_SUCCESS) {\n        t_handle_dynamic = 1; /* Handle has been dynamically allocated */\n    } else {\n        goto cleanup;\n    }\n\n    /* Allocate memory for stack */\n    if (tx_byte_allocate(lwesp_threadx_byte_pool, &stack_ptr, stack_size, TX_NO_WAIT) != TX_SUCCESS) {\n        goto cleanup;\n    }\n\n    /* Allocate thread stack */\n    if (tx_thread_create(t_handle, (CHAR*)name, (VOID(*)(ULONG))(thread_func), (ULONG)arg, stack_ptr, stack_size, prio,\n                         0, TX_NO_TIME_SLICE, TX_AUTO_START)\n        != TX_SUCCESS) {\n        goto cleanup;\n    }\n\n    /*\n     * ThreadX does not allow self-termination feature,\n     * hence dynamic thread creation or termination isn't supported.\n     *\n     * To overcome this \"problem\", application can create an idle thread,\n     * with lowest priority, being involved only when no other threads are being used.\n     *\n     * Idle thread is then in charge to check every thread in terminated or completed state\n     * and can cleanup dynamically allocated memory\n     *\n     * User must add below code to the \"tx_user.h\" file\n     *\n     * #define TX_THREAD_USER_EXTENSION         UINT tx_thread_user_is_handle_alloc_dynamic; \\\n     *                                          UINT tx_thread_user_is_stack_alloc_dynamic;\n     *\n     * And later for sure create idle thread in charge of ThreadX cleanup process\n     */\n    t_handle->tx_thread_user_is_handle_alloc_dynamic = t_handle_dynamic;\n    t_handle->tx_thread_user_is_stack_alloc_dynamic = 1;\n    return 1;\n\ncleanup:\n    if (t_handle_dynamic && t_handle != NULL) {\n        tx_byte_release(t_handle);\n    }\n    if (stack_ptr != NULL) {\n        tx_byte_release(stack_ptr);\n    }\n    return 0;\n}\n\nuint8_t\nlwesp_sys_thread_terminate(lwesp_sys_thread_t* t) {\n    uint8_t rt = 0;\n\n    /*\n     * See thread creation feature to understand this properly\n     *\n     * We only need to terminate thread and let idle thread to do the things for us\n     * with memory cleanups. ThreadX extension at user side must be provided\n     */\n    rt = tx_thread_terminate(t != NULL ? t : tx_thread_identify()) == TX_SUCCESS;\n    return rt;\n}\n\n#else /* LWESP_CFG_THREADX_IDLE_THREAD_EXTENSION */\n\nuint8_t\nlwesp_sys_thread_create(lwesp_sys_thread_t* t, const char* name, lwesp_sys_thread_fn thread_func, void* const arg,\n                        size_t stack_size, lwesp_sys_thread_prio_t prio) {\n\n    typedef VOID (*threadx_entry_t)(ULONG);\n    uint8_t rt = 0;\n\n    void* stack_mem = lwesp_mem_malloc(stack_size);\n    if (stack_mem != NULL) {\n        if (tx_thread_create(t, (CHAR*)name, (VOID(*)(ULONG))(thread_func), (ULONG)arg, stack_mem, stack_size, prio,\n                             prio, TX_NO_TIME_SLICE, TX_AUTO_START)\n            == TX_SUCCESS) {\n            rt = 1;\n        } else {\n            lwesp_mem_free(stack_mem);\n        }\n    }\n    return rt;\n}\n\nuint8_t\nlwesp_sys_thread_terminate(lwesp_sys_thread_t* t) {\n    uint8_t rt = 0;\n\n    /*  t == NULL means temrinate itself.\n        Here termination of a thread requires deleting thread (free RCB) and releasing stack memory\n        ThreadX does not support deleting itself, so I left this feature not supported (when t == NULL) */\n\n    if ((t != NULL) && (t != tx_thread_identify())) {\n        if (tx_thread_terminate(t) == TX_SUCCESS) {\n            if (tx_thread_delete(t) == TX_SUCCESS) {\n                lwesp_mem_free(t->tx_thread_stack_start);\n                rt = 1;\n            }\n        }\n    }\n    return rt;\n}\n\n#endif /* !LWESP_CFG_THREADX_IDLE_THREAD_EXTENSION */\n\nuint8_t\nlwesp_sys_thread_yield(void) {\n    tx_thread_relinquish();\n    return 0;\n}\n\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "lwesp/src/system/lwesp_sys_win32.c",
    "content": "/**\n * \\file            lwesp_sys_win32.c\n * \\brief           System dependant functions for WIN32\n */\n\n/*\n * Copyright (c) 2024 Tilen MAJERLE\n *\n * Permission is hereby granted, free of charge, to any person\n * obtaining a copy of this software and associated documentation\n * files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge,\n * publish, distribute, sublicense, and/or sell copies of the Software,\n * and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE\n * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n * OTHER DEALINGS IN THE SOFTWARE.\n *\n * This file is part of LwESP - Lightweight ESP-AT parser library.\n *\n * Author:          Tilen MAJERLE <tilen@majerle.eu>\n * Version:         v1.1.2-dev\n */\n#include <stdlib.h>\n#include <string.h>\n#include \"lwesp/lwesp_private.h\"\n#include \"system/lwesp_sys.h\"\n#include \"windows.h\"\n\n#if !__DOXYGEN__\n\n/**\n * \\brief           Custom message queue implementation for WIN32\n */\ntypedef struct {\n    lwesp_sys_sem_t sem_not_empty; /*!< Semaphore indicates not empty */\n    lwesp_sys_sem_t sem_not_full;  /*!< Semaphore indicates not full */\n    lwesp_sys_sem_t sem;           /*!< Semaphore to lock access */\n    size_t in, out, size;\n    void* entries[1];\n} win32_mbox_t;\n\nstatic LARGE_INTEGER freq, sys_start_time;\nstatic lwesp_sys_mutex_t sys_mutex; /* Mutex ID for main protection */\n\n/**\n * \\brief           Check if message box is full\n * \\param[in]       m: Message box handle\n * \\return          1 if full, 0 otherwise\n */\nstatic uint8_t\nmbox_is_full(win32_mbox_t* m) {\n    size_t size = 0;\n    if (m->in > m->out) {\n        size = (m->in - m->out);\n    } else if (m->out > m->in) {\n        size = m->size - m->out + m->in;\n    }\n    return size == m->size - 1;\n}\n\n/**\n * \\brief           Check if message box is empty\n * \\param[in]       m: Message box handle\n * \\return          1 if empty, 0 otherwise\n */\nstatic uint8_t\nmbox_is_empty(win32_mbox_t* m) {\n    return m->in == m->out;\n}\n\n/**\n * \\brief           Get current kernel time in units of milliseconds\n */\nstatic uint32_t\nosKernelSysTick(void) {\n    LONGLONG ret;\n    LARGE_INTEGER now;\n\n    QueryPerformanceFrequency(&freq); /* Get frequency */\n    QueryPerformanceCounter(&now);    /* Get current time */\n    ret = now.QuadPart - sys_start_time.QuadPart;\n    return (uint32_t)(((ret)*1000) / freq.QuadPart);\n}\n\nuint8_t\nlwesp_sys_init(void) {\n    QueryPerformanceFrequency(&freq);\n    QueryPerformanceCounter(&sys_start_time);\n\n    lwesp_sys_mutex_create(&sys_mutex);\n    return 1;\n}\n\nuint32_t\nlwesp_sys_now(void) {\n    return osKernelSysTick();\n}\n\n#if LWESP_CFG_OS\nuint8_t\nlwesp_sys_protect(void) {\n    lwesp_sys_mutex_lock(&sys_mutex);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_unprotect(void) {\n    lwesp_sys_mutex_unlock(&sys_mutex);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_create(lwesp_sys_mutex_t* p) {\n    *p = CreateMutex(NULL, FALSE, NULL);\n    return *p != NULL;\n}\n\nuint8_t\nlwesp_sys_mutex_delete(lwesp_sys_mutex_t* p) {\n    return CloseHandle(*p);\n}\n\nuint8_t\nlwesp_sys_mutex_lock(lwesp_sys_mutex_t* p) {\n    DWORD ret;\n    ret = WaitForSingleObject(*p, INFINITE);\n    if (ret != WAIT_OBJECT_0) {\n        return 0;\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mutex_unlock(lwesp_sys_mutex_t* p) {\n    return ReleaseMutex(*p);\n}\n\nuint8_t\nlwesp_sys_mutex_isvalid(lwesp_sys_mutex_t* p) {\n    return p != NULL && *p != NULL;\n}\n\nuint8_t\nlwesp_sys_mutex_invalid(lwesp_sys_mutex_t* p) {\n    *p = LWESP_SYS_MUTEX_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_sem_create(lwesp_sys_sem_t* p, uint8_t cnt) {\n    HANDLE h;\n    h = CreateSemaphore(NULL, !!cnt, 1, NULL);\n    *p = h;\n    return *p != NULL;\n}\n\nuint8_t\nlwesp_sys_sem_delete(lwesp_sys_sem_t* p) {\n    return CloseHandle(*p);\n}\n\nuint32_t\nlwesp_sys_sem_wait(lwesp_sys_sem_t* p, uint32_t timeout) {\n    DWORD ret;\n\n    if (timeout == 0) {\n        ret = WaitForSingleObject(*p, INFINITE);\n        return 1;\n    } else {\n        ret = WaitForSingleObject(*p, timeout);\n        if (ret == WAIT_OBJECT_0) {\n            return 1;\n        } else {\n            return LWESP_SYS_TIMEOUT;\n        }\n    }\n}\n\nuint8_t\nlwesp_sys_sem_release(lwesp_sys_sem_t* p) {\n    return ReleaseSemaphore(*p, 1, NULL);\n}\n\nuint8_t\nlwesp_sys_sem_isvalid(lwesp_sys_sem_t* p) {\n    return p != NULL && *p != NULL;\n}\n\nuint8_t\nlwesp_sys_sem_invalid(lwesp_sys_sem_t* p) {\n    *p = LWESP_SYS_SEM_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_create(lwesp_sys_mbox_t* b, size_t size) {\n    win32_mbox_t* mbox;\n\n    *b = 0;\n\n    mbox = malloc(sizeof(*mbox) + size * sizeof(void*));\n    if (mbox != NULL) {\n        memset(mbox, 0x00, sizeof(*mbox));\n        mbox->size = size + 1; /* Set it to 1 more as cyclic buffer has only one less than size */\n        lwesp_sys_sem_create(&mbox->sem, 1);\n        lwesp_sys_sem_create(&mbox->sem_not_empty, 0);\n        lwesp_sys_sem_create(&mbox->sem_not_full, 0);\n        *b = mbox;\n    }\n    return *b != NULL;\n}\n\nuint8_t\nlwesp_sys_mbox_delete(lwesp_sys_mbox_t* b) {\n    win32_mbox_t* mbox = *b;\n    lwesp_sys_sem_delete(&mbox->sem);\n    lwesp_sys_sem_delete(&mbox->sem_not_full);\n    lwesp_sys_sem_delete(&mbox->sem_not_empty);\n    free(mbox);\n    return 1;\n}\n\nuint32_t\nlwesp_sys_mbox_put(lwesp_sys_mbox_t* b, void* m) {\n    win32_mbox_t* mbox = *b;\n    uint32_t time = osKernelSysTick(); /* Get start time */\n\n    lwesp_sys_sem_wait(&mbox->sem, 0); /* Wait for access */\n\n    /*\n     * Since function is blocking until ready to write something to queue,\n     * wait and release the semaphores to allow other threads\n     * to process the queue before we can write new value.\n     */\n    while (mbox_is_full(mbox)) {\n        lwesp_sys_sem_release(&mbox->sem);          /* Release semaphore */\n        lwesp_sys_sem_wait(&mbox->sem_not_full, 0); /* Wait for semaphore indicating not full */\n        lwesp_sys_sem_wait(&mbox->sem, 0);          /* Wait availability again */\n    }\n    mbox->entries[mbox->in] = m;\n    if (++mbox->in >= mbox->size) {\n        mbox->in = 0;\n    }\n    lwesp_sys_sem_release(&mbox->sem_not_empty); /* Signal non-empty state */\n    lwesp_sys_sem_release(&mbox->sem);           /* Release access for other threads */\n    return osKernelSysTick() - time;\n}\n\nuint32_t\nlwesp_sys_mbox_get(lwesp_sys_mbox_t* b, void** m, uint32_t timeout) {\n    win32_mbox_t* mbox = *b;\n    uint32_t time;\n\n    time = osKernelSysTick();\n\n    /* Get exclusive access to message queue */\n    if (lwesp_sys_sem_wait(&mbox->sem, timeout) == LWESP_SYS_TIMEOUT) {\n        return LWESP_SYS_TIMEOUT;\n    }\n    while (mbox_is_empty(mbox)) {\n        lwesp_sys_sem_release(&mbox->sem);\n        if (lwesp_sys_sem_wait(&mbox->sem_not_empty, timeout) == LWESP_SYS_TIMEOUT) {\n            return LWESP_SYS_TIMEOUT;\n        }\n        lwesp_sys_sem_wait(&mbox->sem, timeout);\n    }\n    *m = mbox->entries[mbox->out];\n    if (++mbox->out >= mbox->size) {\n        mbox->out = 0;\n    }\n    lwesp_sys_sem_release(&mbox->sem_not_full);\n    lwesp_sys_sem_release(&mbox->sem);\n\n    return osKernelSysTick() - time;\n}\n\nuint8_t\nlwesp_sys_mbox_putnow(lwesp_sys_mbox_t* b, void* m) {\n    win32_mbox_t* mbox = *b;\n\n    lwesp_sys_sem_wait(&mbox->sem, 0);\n    if (mbox_is_full(mbox)) {\n        lwesp_sys_sem_release(&mbox->sem);\n        return 0;\n    }\n    mbox->entries[mbox->in] = m;\n    if (mbox->in == mbox->out) {\n        lwesp_sys_sem_release(&mbox->sem_not_empty);\n    }\n    if (++mbox->in >= mbox->size) {\n        mbox->in = 0;\n    }\n    lwesp_sys_sem_release(&mbox->sem);\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_getnow(lwesp_sys_mbox_t* b, void** m) {\n    win32_mbox_t* mbox = *b;\n\n    lwesp_sys_sem_wait(&mbox->sem, 0); /* Wait exclusive access */\n    if (mbox->in == mbox->out) {\n        lwesp_sys_sem_release(&mbox->sem); /* Release access */\n        return 0;\n    }\n\n    *m = mbox->entries[mbox->out];\n    if (++mbox->out >= mbox->size) {\n        mbox->out = 0;\n    }\n    lwesp_sys_sem_release(&mbox->sem_not_full); /* Queue not full anymore */\n    lwesp_sys_sem_release(&mbox->sem);          /* Release semaphore */\n    return 1;\n}\n\nuint8_t\nlwesp_sys_mbox_isvalid(lwesp_sys_mbox_t* b) {\n    return b != NULL && *b != NULL;\n}\n\nuint8_t\nlwesp_sys_mbox_invalid(lwesp_sys_mbox_t* b) {\n    *b = LWESP_SYS_MBOX_NULL;\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_create(lwesp_sys_thread_t* t, const char* name, lwesp_sys_thread_fn thread_func, void* const arg,\n                        size_t stack_size, lwesp_sys_thread_prio_t prio) {\n    HANDLE h;\n    DWORD id;\n\n    LWESP_UNUSED(name);\n    LWESP_UNUSED(stack_size);\n    LWESP_UNUSED(prio);\n    h = CreateThread(0, 0, (LPTHREAD_START_ROUTINE)thread_func, arg, 0, &id);\n    if (t != NULL) {\n        *t = h;\n    }\n    return h != NULL;\n}\n\nuint8_t\nlwesp_sys_thread_terminate(lwesp_sys_thread_t* t) {\n    if (t == NULL) { /* Shall we terminate ourself? */\n        ExitThread(0);\n    } else {\n        /* We have known thread, find handle by looking at ID */\n        TerminateThread(*t, 0);\n    }\n    return 1;\n}\n\nuint8_t\nlwesp_sys_thread_yield(void) {\n    /* Not implemented */\n    return 1;\n}\n\n#endif /* LWESP_CFG_OS */\n#endif /* !__DOXYGEN__ */\n"
  },
  {
    "path": "snippets/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 3.22)\n\n# Setup generic source files\nset(lwesp_snippets_SRCS\n    ${CMAKE_CURRENT_LIST_DIR}/telnet_server.c\n    ${CMAKE_CURRENT_LIST_DIR}/utils.c\n    ${CMAKE_CURRENT_LIST_DIR}/client.c\n    ${CMAKE_CURRENT_LIST_DIR}/dns.c\n    ${CMAKE_CURRENT_LIST_DIR}/http_server.c\n    ${CMAKE_CURRENT_LIST_DIR}/mqtt_client.c\n    ${CMAKE_CURRENT_LIST_DIR}/mqtt_client_api.c\n    ${CMAKE_CURRENT_LIST_DIR}/mqtt_client_api_ha.c\n    ${CMAKE_CURRENT_LIST_DIR}/netconn_client.c\n    ${CMAKE_CURRENT_LIST_DIR}/netconn_client_ssl.c\n    ${CMAKE_CURRENT_LIST_DIR}/netconn_server.c\n    ${CMAKE_CURRENT_LIST_DIR}/netconn_server_1thread.c\n    ${CMAKE_CURRENT_LIST_DIR}/sntp.c\n    ${CMAKE_CURRENT_LIST_DIR}/station_manager.c\n)\n\n# Setup include directories\nset(lwesp_snippets_include_DIRS\n    ${CMAKE_CURRENT_LIST_DIR}/include\n)\n\n# Register library to the system\nadd_library(lwesp_snippets INTERFACE)\ntarget_sources(lwesp_snippets PUBLIC ${lwesp_snippets_SRCS})\ntarget_include_directories(lwesp_snippets INTERFACE ${lwesp_snippets_include_DIRS})\n"
  },
  {
    "path": "snippets/client.c",
    "content": "#include \"client.h\"\n#include \"lwesp/lwesp.h\"\n\n/* Host parameter */\n#define CONN_HOST           \"example.com\"\n#define CONN_PORT           80\n\nstatic lwespr_t   conn_callback_func(lwesp_evt_t* evt);\n\n/**\n * \\brief           Request data for connection\n */\nstatic const\nuint8_t req_data[] = \"\"\n                     \"GET / HTTP/1.1\\r\\n\"\n                     \"Host: \" CONN_HOST \"\\r\\n\"\n                     \"Connection: close\\r\\n\"\n                     \"\\r\\n\";\n\n/**\n * \\brief           Start a new connection(s) as client\n */\nvoid\nclient_connect(void) {\n    lwespr_t res;\n\n    /* Start a new connection as client in non-blocking mode */\n    if ((res = lwesp_conn_start(NULL, LWESP_CONN_TYPE_TCP, \"example.com\", 80, NULL, conn_callback_func, 0)) == lwespOK) {\n        printf(\"Connection to \" CONN_HOST \" started...\\r\\n\");\n    } else {\n        printf(\"Cannot start connection to \" CONN_HOST \"!\\r\\n\");\n    }\n\n    /* Start 2 more */\n    lwesp_conn_start(NULL, LWESP_CONN_TYPE_TCP, CONN_HOST, CONN_PORT, NULL, conn_callback_func, 0);\n\n    /*\n     * An example of connection which should fail in connecting.\n     * When this is the case, \\ref LWESP_EVT_CONN_ERROR event should be triggered\n     * in callback function processing\n     */\n    lwesp_conn_start(NULL, LWESP_CONN_TYPE_TCP, CONN_HOST, 10, NULL, conn_callback_func, 0);\n}\n\n/**\n * \\brief           Event callback function for connection-only\n * \\param[in]       evt: Event information with data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nconn_callback_func(lwesp_evt_t* evt) {\n    lwesp_conn_p conn;\n    lwespr_t res;\n    uint8_t conn_num;\n\n    conn = lwesp_conn_get_from_evt(evt);          /* Get connection handle from event */\n    if (conn == NULL) {\n        return lwespERR;\n    }\n    conn_num = lwesp_conn_getnum(conn);           /* Get connection number for identification */\n    switch (lwesp_evt_get_type(evt)) {\n        case LWESP_EVT_CONN_ACTIVE: {             /* Connection just active */\n            printf(\"Connection %d active!\\r\\n\", (int)conn_num);\n            res = lwesp_conn_send(conn, req_data, sizeof(req_data) - 1, NULL, 0); /* Start sending data in non-blocking mode */\n            if (res == lwespOK) {\n                printf(\"Sending request data to server...\\r\\n\");\n            } else {\n                printf(\"Cannot send request data to server. Closing connection manually...\\r\\n\");\n                lwesp_conn_close(conn, 0);        /* Close the connection */\n            }\n            break;\n        }\n        case LWESP_EVT_CONN_CLOSE: {              /* Connection closed */\n            if (lwesp_evt_conn_close_is_forced(evt)) {\n                printf(\"Connection %d closed by client!\\r\\n\", (int)conn_num);\n            } else {\n                printf(\"Connection %d closed by remote side!\\r\\n\", (int)conn_num);\n            }\n            break;\n        }\n        case LWESP_EVT_CONN_SEND: {               /* Data send event */\n            lwespr_t res = lwesp_evt_conn_send_get_result(evt);\n            if (res == lwespOK) {\n                printf(\"Data sent successfully on connection %d...waiting to receive data from remote side...\\r\\n\", (int)conn_num);\n            } else {\n                printf(\"Error while sending data on connection %d!\\r\\n\", (int)conn_num);\n            }\n            break;\n        }\n        case LWESP_EVT_CONN_RECV: {               /* Data received from remote side */\n            lwesp_pbuf_p pbuf = lwesp_evt_conn_recv_get_buff(evt);\n            lwesp_conn_recved(conn, pbuf);        /* Notify stack about received pbuf */\n            printf(\"Received %d bytes on connection %d..\\r\\n\", (int)lwesp_pbuf_length(pbuf, 1), (int)conn_num);\n            break;\n        }\n        case LWESP_EVT_CONN_ERROR: {              /* Error connecting to server */\n            const char* host = lwesp_evt_conn_error_get_host(evt);\n            lwesp_port_t port = lwesp_evt_conn_error_get_port(evt);\n            printf(\"Error connecting to %s:%d\\r\\n\", host, (int)port);\n            break;\n        }\n        default:\n            break;\n    }\n    return lwespOK;\n}\n"
  },
  {
    "path": "snippets/dns.c",
    "content": "/*\n * This snippet shows how to use ESP's DNS module to \n * obtain IP address from domain name\n */\n#include \"dns.h\"\n#include \"lwesp/lwesp.h\"\n\n/* Host to resolve */\n#define DNS_HOST1           \"example.com\"\n#define DNS_HOST2           \"example.net\"\n\n/**\n * \\brief           Variable to hold result of DNS resolver\n */\nstatic lwesp_ip_t ip;\n\n/**\n * \\brief           Function to print actual resolved IP address\n */\nstatic void\nprv_print_ip(void) {\n    if (0) {\n#if LWESP_CFG_IPV6\n    } else if (ip.type == LWESP_IPTYPE_V6) {\n        printf(\"IPv6: %04X:%04X:%04X:%04X:%04X:%04X:%04X:%04X\\r\\n\",\n            (unsigned)ip.addr.ip6.addr[0], (unsigned)ip.addr.ip6.addr[1], (unsigned)ip.addr.ip6.addr[2],\n            (unsigned)ip.addr.ip6.addr[3], (unsigned)ip.addr.ip6.addr[4], (unsigned)ip.addr.ip6.addr[5],\n            (unsigned)ip.addr.ip6.addr[6], (unsigned)ip.addr.ip6.addr[7]);\n#endif /* LWESP_CFG_IPV6 */\n    } else {\n        printf(\"IPv4: %d.%d.%d.%d\\r\\n\",\n            (int)ip.addr.ip4.addr[0], (int)ip.addr.ip4.addr[1], (int)ip.addr.ip4.addr[2], (int)ip.addr.ip4.addr[3]);\n    }\n}\n\n/**\n * \\brief           Event callback function for API call,\n *                  called when API command finished with execution\n */\nstatic void\nprv_dns_resolve_evt(lwespr_t res, void* arg) {\n    LWESP_UNUSED(arg);\n    /* Check result of command */\n    if (res == lwespOK) {\n        /* Print actual resolved IP */\n        prv_print_ip();\n    }\n}\n\n/**\n * \\brief           Start DNS resolver\n */\nvoid\ndns_start(void) {\n    /* Use DNS protocol to get IP address of domain name */\n\n    /* Get IP with non-blocking mode */\n    if (lwesp_dns_gethostbyname(DNS_HOST2, &ip, prv_dns_resolve_evt, DNS_HOST2, 0) == lwespOK) {\n        printf(\"Request for DNS record for \" DNS_HOST2 \" has started\\r\\n\");\n    } else {\n        printf(\"Could not start command for DNS\\r\\n\");\n    }\n\n    /* Get IP with blocking mode */\n    if (lwesp_dns_gethostbyname(DNS_HOST1, &ip, prv_dns_resolve_evt, DNS_HOST1, 1) == lwespOK) {\n        /* Print actual resolved IP */\n        prv_print_ip();\n    } else {\n        printf(\"Could not retrieve IP address for \" DNS_HOST1 \"\\r\\n\");\n    }\n}\n"
  },
  {
    "path": "snippets/examples_common_lwesp_callback_func.c",
    "content": "#include <stdio.h>\n#include \"examples_common_lwesp_callback_func.h\"\n#include \"lwesp/lwesp.h\"\n\n/**\n * \\brief           Core LwESP callback function for all examples in the repository.\n * \n * This reduces redundancy of the same code being written multiple times.\n * \n * \\param[in]       evt: Event data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nexamples_common_lwesp_callback_func(lwesp_evt_t* evt) {\n    switch (lwesp_evt_get_type(evt)) {\n        case LWESP_EVT_AT_VERSION_NOT_SUPPORTED: {\n            lwesp_sw_version_t v_min, v_curr;\n\n            lwesp_get_min_at_fw_version(&v_min);\n            lwesp_get_current_at_fw_version(&v_curr);\n\n            printf(\"Current ESP[8266/32[-C3]] AT version is not supported by the library\\r\\n\");\n            printf(\"Minimum required AT version is: %08X\\r\\n\", (unsigned)v_min.version);\n            printf(\"Current AT version is: %08X\\r\\n\", (unsigned)v_curr.version);\n            break;\n        }\n        case LWESP_EVT_INIT_FINISH: {\n            printf(\"Library initialized!\\r\\n\");\n            break;\n        }\n        case LWESP_EVT_RESET_DETECTED: {\n            printf(\"Device reset detected!\\r\\n\");\n            break;\n        }\n        default: break;\n    }\n    return lwespOK;\n}\n"
  },
  {
    "path": "snippets/http_server.c",
    "content": "/*\n * HTTP server example implementation\n *\n * It shows how to define user-specific http paths and respond to different\n * HTTP GET or POST command and populate CGI tags with actual data.\n * \n * This is very lightweight example, and is not necessarly full working at the moment\n */\n#include \"http_server.h\"\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/apps/lwesp_http_server.h\"\n#include \"lwesp/apps/lwesp_http_server_fs.h\"\n\nstatic size_t   http_ssi_cb(http_state_t* hs, const char* tag_name, size_t tag_len);\n#if HTTP_SUPPORT_POST\nstatic lwespr_t   http_post_start_cb(http_state_t* hs, const char* uri, uint32_t content_len);\nstatic lwespr_t   http_post_data_cb(http_state_t* hs, lwesp_pbuf_p pbuf);\nstatic lwespr_t   http_post_end_cb(http_state_t* hs);\n#endif /* HTTP_SUPPORT_POST */\n\nstatic char*    led_cgi_handler(http_param_t* params, size_t params_len);\nstatic char*    usart_cgi_handler(http_param_t* params, size_t params_len);\n\n/**\n * \\brief           List of CGI handlers\n * \n * Defines HTTP path and callback function,\n * called when specific path matches in HTTP request\n */\nconst http_cgi_t\ncgi_handlers[] = {\n    { \"/led.cgi\", led_cgi_handler },\n    { \"/usart.cgi\", usart_cgi_handler },\n};\n\n/**\n * \\brief           HTTP init structure\n * \n * Structure between HTTP LwESP module and application specific part\n */\nconst http_init_t\nhttp_init = {\n#if HTTP_SUPPORT_POST\n    .post_start_fn = http_post_start_cb,\n    .post_data_fn = http_post_data_cb,\n    .post_end_fn = http_post_end_cb,\n#endif /* HTTP_SUPPORT_POST */\n    .cgi = cgi_handlers,\n    .cgi_count = LWESP_ARRAYSIZE(cgi_handlers),\n    .ssi_fn = http_ssi_cb,\n\n#if WIN32\n    /*\n     * Use native WIN32 file system API\n     */\n    .fs_open = http_fs_open,\n    .fs_read = http_fs_read,\n    .fs_close = http_fs_close,\n#endif /* WIN32 */\n};\n\n/**\n * \\brief           Start HTTP server on port 80\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nhttp_server_start(void) {\n    lwespr_t res;\n    printf(\"Starting HTTP server on port 80...\\r\\n\");\n    if ((res = lwesp_http_server_init(&http_init, 80)) == lwespOK) {\n        printf(\"HTTP server ready!\\r\\n\");\n    } else {\n        printf(\"Cannot start HTTP server\\r\\n\");\n    }\n    return res;\n}\n\n#if HTTP_SUPPORT_POST\n\n/**\n * \\brief           Callback function indicating post request method started\n * \\param[in]       hs: HTTP state\n * \\param[in]       uri: NULL-terminated uri string for POST request\n * \\param[in]       content_len: Total content length received by \"Content-Length\" header\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nhttp_post_start_cb(http_state_t* hs, const char* uri, uint32_t content_len) {\n    LWESP_UNUSED(hs);\n    printf(\"POST started with %d length on URI: %s\\r\\n\", (int)content_len, uri);\n    return lwespOK;\n}\n\n/**\n * \\brief           Callback function indicating post request data received\n * \\param[in]       hs: HTTP state\n * \\param[in]       pbuf: New chunk of received data\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nhttp_post_data_cb(http_state_t* hs, lwesp_pbuf_p pbuf) {\n    LWESP_UNUSED(hs);\n    printf(\"POST data received: %d bytes\\r\\n\", (int)lwesp_pbuf_length(pbuf, 1));\n    return lwespOK;\n}\n\n/**\n * \\brief           Callback function indicating post request finished\n * \\param[in]       hs: HTTP state\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nhttp_post_end_cb(http_state_t* hs) {\n    LWESP_UNUSED(hs);\n    printf(\"POST finished!\\r\\n\");\n    return lwespOK;\n}\n\n#endif /* HTTP_SUPPORT_POST */\n\n/**\n * \\brief           Global SSI callback function\n *\n *                  Called in case SSI tag was found and ready to be replaced by custom data\n *\n * \\param[in]       hs: HTTP state\n * \\param[in]       tag_name: Name of tag\n * \\param[in]       tag_len: Length of tag\n * \\return          1 if more data to write on this tag or 0 if everything written for specific tag\n */\nstatic size_t\nhttp_ssi_cb(http_state_t* hs, const char* tag_name, size_t tag_len) {\n    static char ssi_buffer[32];\n    static uint32_t cnt;\n\n    cnt++;\n\n    LWESP_UNUSED(ssi_buffer);\n    if (!strncmp(tag_name, \"title\", tag_len)) {\n        lwesp_http_server_write_string(hs, \"ESP8266 SSI TITLE\");\n        return cnt % 3;\n    } else if (!strncmp(tag_name, \"led_status\", tag_len)) {\n        lwesp_http_server_write_string(hs, \"Led is on\");\n    } else if (!strncmp(tag_name, \"wifi_list\", tag_len)) {\n        size_t i = 0;\n\n        LWESP_UNUSED(i);\n        lwesp_http_server_write_string(hs, \"<table class=\\\"table\\\">\");\n        lwesp_http_server_write_string(hs, \"<thead><tr><th>#</th><th>SSID</th><th>MAC</th><th>RSSI</th></tr></thead><tbody>\");\n\n        //for (i = 0; i < apf; i++) {\n        //    lwesp_http_server_write_string(hs, \"<tr><td>\");\n        //    sprintf(ssi_buffer, \"%d\", (int)i);\n        //    lwesp_http_server_write_string(hs, ssi_buffer);\n        //    lwesp_http_server_write_string(hs, \"</td><td>\");\n        //    lwesp_http_server_write_string(hs, aps[i].ssid);\n        //    lwesp_http_server_write_string(hs, \"</td><td>\");\n        //    sprintf(ssi_buffer, \"%02X:%02X:%02X:%02X:%02X:%02X\", aps[i].mac[0], aps[i].mac[1], aps[i].mac[2], aps[i].mac[3], aps[i].mac[4], aps[i].mac[5]);\n        //    lwesp_http_server_write_string(hs, ssi_buffer);\n        //    lwesp_http_server_write_string(hs, \"</td><td>\");\n        //    sprintf(ssi_buffer, \"%d\", (int)aps[i].rssi);\n        //    lwesp_http_server_write_string(hs, ssi_buffer);\n        //    lwesp_http_server_write_string(hs, \"</td></tr>\");\n        //}\n        lwesp_http_server_write_string(hs, \"</tbody></table>\");\n    }\n    return 1;\n}\n\n/**\n * \\brief           CGI handler function when user connects to \"http://ip/led.cgi?param1=value1&param2=value2\"\n * \\param[in]       params: Pointer to list of parameters with URI\n * \\param[in]       params_len: Number of parameters\n * \\return          URI string to return to user\n */\nchar*\nled_cgi_handler(http_param_t* params, size_t params_len) {\n    printf(\"LED CGI HANDLER\\r\\n\");\n    while (params_len--) {\n        printf(\"Param: name = %s, value = %s\\r\\n\", params->name, params->value);\n        params++;\n    }\n    return \"/index.shtml\";\n}\n\n/**\n * \\brief           CGI handler function when user connects to \"http://ip/usart.cgi?param1=value1&param2=value2\"\n * \\param[in]       params: Pointer to list of parameters with URI\n * \\param[in]       params_len: Number of parameters\n * \\return          URI string to return to user\n */\nchar*\nusart_cgi_handler(http_param_t* params, size_t params_len) {\n    printf(\"USART CGI HANDLER!\\r\\n\");\n    while (params_len--) {\n        printf(\"Param: name = %s, value = %s\\r\\n\", params->name, params->value);\n        params++;\n    }\n    return \"/index.html\";\n}\n"
  },
  {
    "path": "snippets/include/client.h",
    "content": "#ifndef SNIPPET_HDR_CLIENT_H\n#define SNIPPET_HDR_CLIENT_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid client_connect(void);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n"
  },
  {
    "path": "snippets/include/dns.h",
    "content": "#ifndef SNIPPET_HDR_DNS_H\n#define SNIPPET_HDR_DNS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid dns_start(void);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_DNS_H */\n"
  },
  {
    "path": "snippets/include/examples_common_lwesp_callback_func.h",
    "content": "#ifndef EXAMPLES_COMMON_LWESP_CALLBACK_FUNC\n#define EXAMPLES_COMMON_LWESP_CALLBACK_FUNC\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#include \"lwesp/lwesp.h\"\n\nlwespr_t examples_common_lwesp_callback_func(lwesp_evt_t* evt);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* EXAMPLES_COMMON_LWESP_CALLBACK_FUNC */\n"
  },
  {
    "path": "snippets/include/http_server.h",
    "content": "#ifndef SNIPPET_HDR_HTTP_SERVER_H\n#define SNIPPET_HDR_HTTP_SERVER_H\n\n#include \"lwesp/lwesp.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nlwespr_t  http_server_start(void);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_HTTP_SERVER_H */\n"
  },
  {
    "path": "snippets/include/mqtt_client.h",
    "content": "#ifndef SNIPPET_HDR_MQTT_CLIENT_H\n#define SNIPPET_HDR_MQTT_CLIENT_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid mqtt_client_thread(void const* arg);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_MQTT_CLIENT_H */\n"
  },
  {
    "path": "snippets/include/mqtt_client_api.h",
    "content": "#ifndef SNIPPET_HDR_MQTT_CLIENT_API_H\n#define SNIPPET_HDR_MQTT_CLIENT_API_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid lwesp_mqtt_client_api_thread(void const* arg);\nvoid lwesp_mqtt_client_api_ha_thread(void const* arg);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_MQTT_CLIENT_API_H */\n"
  },
  {
    "path": "snippets/include/netconn_client.h",
    "content": "#ifndef SNIPPET_HDR_NETCONN_CLIENT_H\n#define SNIPPET_HDR_NETCONN_CLIENT_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid netconn_client_thread(void const* arg);\nvoid netconn_client_ssl_thread(void const* arg);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_NETCONN_CLIENT_H */\n"
  },
  {
    "path": "snippets/include/netconn_server.h",
    "content": "#ifndef SNIPPET_HDR_NETCONN_SERVER_H\n#define SNIPPET_HDR_NETCONN_SERVER_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid netconn_server_thread(void const* arg);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_NETCONN_SERVER_H */\n"
  },
  {
    "path": "snippets/include/netconn_server_1thread.h",
    "content": "#ifndef SNIPPET_HDR_NETCONN_SERVER_1THREAD_H\n#define SNIPPET_HDR_NETCONN_SERVER_1THREAD_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid netconn_server_1thread_thread(void* arg);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_NETCONN_SERVER_1THREAD_H */\n"
  },
  {
    "path": "snippets/include/sntp.h",
    "content": "#ifndef SNIPPET_HDR_SNTP_H\n#define SNIPPET_HDR_SNTP_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid sntp_gettime(void);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_SNTP_H */\n"
  },
  {
    "path": "snippets/include/station_manager.h",
    "content": "#ifndef SNIPPET_HDR_STATION_MANAGER_H\n#define SNIPPET_HDR_STATION_MANAGER_H\n\n#include <stdint.h>\n#include \"lwesp/lwesp.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n/**\n * \\brief           Lookup table for preferred SSIDs with password for auto connect feature\n */\ntypedef struct {\n    const char* ssid;\n    const char* pass;\n} ap_entry_t;\n\n/* Connect to preferred access point blocking mode */\nlwespr_t    station_manager_connect_to_preferred_access_point(uint8_t unlimited);\n\n/* Initialize asynchronous connection mode in background */\nlwespr_t    station_manager_connect_to_access_point_async_init(void);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_STATION_MANAGER_H */\n"
  },
  {
    "path": "snippets/include/telnet_server.h",
    "content": "#ifndef SNIPPET_HDR_TELNET_SERVER_H\n#define SNIPPET_HDR_TELNET_SERVER_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\nvoid telnet_server_thread(void const* arg);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* SNIPPET_HDR_TELNET_SERVER_H */\n"
  },
  {
    "path": "snippets/include/utils.h",
    "content": "#ifndef SNIPPET_HDR_UTILS_H\n#define SNIPPET_HDR_UTILS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif /* __cplusplus */\n\n#include \"lwesp/lwesp.h\"\n\nvoid    utils_print_ip(const char* str_b, const lwesp_ip_t* ip, const char* str_a);\nvoid    utils_print_mac(const char* str_b, const lwesp_mac_t* mac, const char* str_a);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif\n"
  },
  {
    "path": "snippets/mqtt_client.c",
    "content": "/*\n * MQTT client example with ESP device using asynchronous callbacks\n *\n * Once device is connected to network,\n * it will try to connect to mosquitto test server and start the MQTT.\n *\n * If successfully connected, it will publish data to \"lwesp_topic\" topic every x seconds.\n *\n * To check if data are sent, you can use mqtt-spy PC software to inspect\n * test.mosquitto.org server and subscribe to publishing topic\n */\n#include \"lwesp/apps/lwesp_mqtt_client.h\"\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_timeout.h\"\n#include \"mqtt_client.h\"\n\nstatic lwesp_mqtt_client_p  mqtt_client;    /*!< MQTT client structure */\nstatic char mqtt_client_id[13];             /*!< Client ID is structured from ESP station MAC address */\n\n/**\n * \\brief           Connection information for MQTT CONNECT packet\n */\nstatic const lwesp_mqtt_client_info_t\nmqtt_client_info = {\n    .id = mqtt_client_id,                       /* The only required field for connection! */\n\n    .keep_alive = 10,\n    // .user = \"test_username\",\n    // .pass = \"test_password\",\n};\n\nstatic void prv_mqtt_cb(lwesp_mqtt_client_p client, lwesp_mqtt_evt_t* evt);\nstatic void prv_example_do_connect(lwesp_mqtt_client_p client);\nstatic uint32_t retries = 0;\n\n/**\n * \\brief           Custom callback function for ESP events\n * \\param[in]       evt: ESP event callback function\n */\nstatic lwespr_t\nprv_mqtt_lwesp_cb(lwesp_evt_t* evt) {\n    switch (lwesp_evt_get_type(evt)) {\n#if LWESP_CFG_MODE_STATION\n        case LWESP_EVT_WIFI_GOT_IP: {\n            prv_example_do_connect(mqtt_client);/* Start connection after we have a connection to network client */\n            break;\n        }\n#endif /* LWESP_CFG_MODE_STATION */\n        default:\n            break;\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           MQTT client thread\n * \\param[in]       arg: User argument\n */\nvoid\nmqtt_client_thread(void const* arg) {\n    lwesp_mac_t mac;\n\n    LWESP_UNUSED(arg);\n\n    /* Register new callback for general events from ESP stack */\n    lwesp_evt_register(prv_mqtt_lwesp_cb);\n\n    /* Get station MAC to format client ID */\n    if (lwesp_sta_getmac(&mac, NULL, NULL, 1) == lwespOK) {\n        snprintf(mqtt_client_id, sizeof(mqtt_client_id), \"%02X%02X%02X%02X%02X%02X\",\n                 (unsigned)mac.mac[0], (unsigned)mac.mac[1], (unsigned)mac.mac[2],\n                 (unsigned)mac.mac[3], (unsigned)mac.mac[4], (unsigned)mac.mac[5]\n                );\n    } else {\n        strcpy(mqtt_client_id, \"unknown\");\n    }\n    printf(\"MQTT Client ID: %s\\r\\n\", mqtt_client_id);\n\n    /*\n     * Create a new client with 256 bytes of RAW TX data\n     * and 128 bytes of RAW incoming data\n     * \n     * If station is already connected to access point,\n     * try to connect immediately, otherwise it\n     * will get connected from callback function instead \n     */\n    mqtt_client = lwesp_mqtt_client_new(256, 128);  /* Create new MQTT client */\n    if (lwesp_sta_is_joined()) {                /* If ESP is already joined to network */\n        prv_example_do_connect(mqtt_client);    /* Start connection to MQTT server */\n    }                                           \n\n    /* Make dummy delay of thread */\n    while (1) {\n        lwesp_delay(1000);\n    }\n}\n\n/**\n * \\brief           Timeout callback for MQTT events\n * \\param[in]       arg: User argument\n */\nstatic void\nprv_mqtt_timeout_cb(void* arg) {\n    static char tx_data[20];\n    static uint32_t num = 10;\n    lwesp_mqtt_client_p client = arg;\n    lwespr_t res;\n    \n    if (lwesp_mqtt_client_is_connected(client)) {\n        sprintf(tx_data, \"R: %u, N: %u\", (unsigned)retries, (unsigned)num);\n        if ((res = lwesp_mqtt_client_publish(client, \"lwesp_topic\", tx_data, LWESP_U16(strlen(tx_data)), LWESP_MQTT_QOS_EXACTLY_ONCE, 0, (void*)((uintptr_t)num))) == lwespOK) {\n            printf(\"Publishing %d...\\r\\n\", (int)num);\n            num++;\n        } else {\n            printf(\"Cannot publish...: %d\\r\\n\", (int)res);\n        }\n    }\n    lwesp_timeout_add(10000, prv_mqtt_timeout_cb, arg);\n}\n\n/**\n * \\brief           MQTT event callback function\n * \\param[in]       client: MQTT client where event occurred\n * \\param[in]       evt: Event type and data\n */\nstatic void\nprv_mqtt_cb(lwesp_mqtt_client_p client, lwesp_mqtt_evt_t* evt) {\n    switch (lwesp_mqtt_client_evt_get_type(client, evt)) {\n        /*\n         * Connect event\n         * Called if user successfully connected to MQTT server\n         * or even if connection failed for some reason\n         */\n        case LWESP_MQTT_EVT_CONNECT: {            /* MQTT connect event occurred */\n            lwesp_mqtt_conn_status_t status = lwesp_mqtt_client_evt_connect_get_status(client, evt);\n\n            if (status == LWESP_MQTT_CONN_STATUS_ACCEPTED) {\n                printf(\"MQTT accepted!\\r\\n\");\n                /*\n                 * Once we are accepted by server,\n                 * it is time to subscribe to different topics\n                 * We will subscrive to \"mqtt_lwesp_example_topic\" topic,\n                 * and will also set the same name as subscribe argument for callback later\n                 */\n                lwesp_mqtt_client_subscribe(client, \"lwesp_topic\", LWESP_MQTT_QOS_EXACTLY_ONCE, \"lwesp_topic\");\n\n                /* Start timeout timer after 5000ms and call mqtt_timeout_cb function */\n                lwesp_timeout_add(5000, prv_mqtt_timeout_cb, client);\n            } else {\n                printf(\"MQTT server connection was not successful: %d\\r\\n\", (int)status);\n\n                /* Try to connect all over again */\n                prv_example_do_connect(client);\n            }\n            break;\n        }\n\n        /*\n         * Subscribe event just happened.\n         * Here it is time to check if it was successful or failed attempt\n         */\n        case LWESP_MQTT_EVT_SUBSCRIBE: {\n            const char* arg = lwesp_mqtt_client_evt_subscribe_get_argument(client, evt);  /* Get user argument */\n            lwespr_t res = lwesp_mqtt_client_evt_subscribe_get_result(client, evt); /* Get result of subscribe event */\n\n            if (res == lwespOK) {\n                printf(\"Successfully subscribed to %s topic\\r\\n\", arg);\n                if (!strcmp(arg, \"lwesp_topic\")) {   /* Check topic name we were subscribed */\n                    /* Subscribed to \"lwesp_topic\" topic */\n\n                    /*\n                     * Now publish an even on example topic\n                     * and set QoS to minimal value which does not guarantee message delivery to received\n                     */\n                    lwesp_mqtt_client_publish(client, \"lwesp_topic\", \"test_data\", 9, LWESP_MQTT_QOS_AT_MOST_ONCE, 0, (void*)1);\n                }\n            }\n            break;\n        }\n\n        /* Message published event occurred */\n        case LWESP_MQTT_EVT_PUBLISH: {\n            uint32_t val = (uint32_t)(uintptr_t)lwesp_mqtt_client_evt_publish_get_argument(client, evt);/* Get user argument, which is in fact our custom number */\n\n            printf(\"Publish event, user argument on message was: %d\\r\\n\", (int)val);\n            break;\n        }\n\n        /*\n         * A new message was published to us\n         * and now it is time to read the data\n         */\n        case LWESP_MQTT_EVT_PUBLISH_RECV: {\n            const char* topic = lwesp_mqtt_client_evt_publish_recv_get_topic(client, evt);\n            size_t topic_len = lwesp_mqtt_client_evt_publish_recv_get_topic_len(client, evt);\n            const uint8_t* payload = lwesp_mqtt_client_evt_publish_recv_get_payload(client, evt);\n            size_t payload_len = lwesp_mqtt_client_evt_publish_recv_get_payload_len(client, evt);\n\n            LWESP_UNUSED(payload);\n            LWESP_UNUSED(payload_len);\n            LWESP_UNUSED(topic);\n            LWESP_UNUSED(topic_len);\n            break;\n        }\n\n        /* Client is fully disconnected from MQTT server */\n        case LWESP_MQTT_EVT_DISCONNECT: {\n            printf(\"MQTT client disconnected!\\r\\n\");\n            prv_example_do_connect(client);         /* Connect to server all over again */\n            break;\n        }\n\n        default:\n            break;\n    }\n}\n\n/**\n * \\brief           Make a connection to MQTT server in non-blocking mode\n * Act only if client ready to connect and not already connected \n */\nstatic void\nprv_example_do_connect(lwesp_mqtt_client_p client) {\n    if (client == NULL\n        || lwesp_mqtt_client_is_connected(client)) {\n        return;\n    }\n    printf(\"Trying to connect to MQTT server\\r\\n\");\n\n    /*\n     * Start a simple connection to open source\n     * MQTT server on mosquitto.org\n     */\n    retries++;\n    lwesp_timeout_remove(prv_mqtt_timeout_cb);\n    lwesp_mqtt_client_connect(mqtt_client, \"test.mosquitto.org\", 1883, prv_mqtt_cb, &mqtt_client_info);\n}\n"
  },
  {
    "path": "snippets/mqtt_client_api.c",
    "content": "/*\n * MQTT client API example with ESP device to test server.\n * It utilizes sequential mode without callbacks in one user thread\n *\n * Once device is connected to network,\n * it will try to connect to mosquitto test server and start the MQTT.\n *\n * If successfully connected, it will publish data to \"lwesp_mqtt_topic\" topic every x seconds.\n *\n * To check if data are sent, you can use mqtt-spy PC software to inspect\n * test.mosquitto.org server and subscribe to publishing topic\n */\n\n#include \"mqtt_client_api.h\"\n#include \"lwesp/apps/lwesp_mqtt_client_api.h\"\n#include \"lwesp/lwesp_mem.h\"\n\n/**\n * \\brief           Connection information for MQTT CONNECT packet\n */\nstatic const lwesp_mqtt_client_info_t mqtt_client_info = {\n    .keep_alive = 10,\n\n    /* Server login data */\n    .user = \"8a215f70-a644-11e8-ac49-e932ed599553\",\n    .pass = \"26aa943f702e5e780f015cd048a91e8fb54cca28\",\n\n    /* Device identifier address */\n    .id = \"869f5a20-af9c-11e9-b01f-db5cf74e7fb7\",\n};\n\nstatic char mqtt_topic_str[256];  /*!< Topic string */\nstatic char mqtt_topic_data[256]; /*!< Data string */\n\n/**\n * \\brief           Generate random number and write it to string\n * It utilizes simple pseudo random generator, super simple one\n * \\param[out]      str: Output string with new number\n */\nstatic void\nprv_generate_random(char* str) {\n    static uint32_t random_beg = 0x8916;\n    random_beg = random_beg * 0x00123455 + 0x85654321;\n    sprintf(str, \"%u\", (unsigned)((random_beg >> 8) & 0xFFFF));\n}\n\n/**\n * \\brief           MQTT client API thread\n * \\param[in]       arg: User argument\n */\nvoid\nlwesp_mqtt_client_api_thread(void const* arg) {\n    lwesp_mqtt_client_api_p client;\n    lwesp_mqtt_conn_status_t conn_status;\n    lwesp_mqtt_client_api_buf_p buf;\n    lwespr_t res;\n    char random_str[10];\n\n    LWESP_UNUSED(arg);\n\n    /* Create new MQTT API */\n    if ((client = lwesp_mqtt_client_api_new(256, 128)) == NULL) {\n        goto terminate;\n    }\n\n    while (1) {\n        /* Make a connection */\n        printf(\"Joining MQTT server\\r\\n\");\n\n        /* Try to join */\n        conn_status = lwesp_mqtt_client_api_connect(client, \"mqtt.mydevices.com\", 1883, &mqtt_client_info);\n        if (conn_status == LWESP_MQTT_CONN_STATUS_ACCEPTED) {\n            printf(\"Connected and accepted!\\r\\n\");\n            printf(\"Client is ready to subscribe and publish to new messages\\r\\n\");\n        } else {\n            printf(\"Connect API response: %d\\r\\n\", (int)conn_status);\n            lwesp_delay(5000);\n            continue;\n        }\n\n        /* Subscribe to topics */\n        sprintf(mqtt_topic_str, \"v1/%s/things/%s/cmd/#\", mqtt_client_info.user, mqtt_client_info.id);\n        if (lwesp_mqtt_client_api_subscribe(client, mqtt_topic_str, LWESP_MQTT_QOS_AT_LEAST_ONCE) == lwespOK) {\n            printf(\"Subscribed to topic\\r\\n\");\n        } else {\n            printf(\"Problem subscribing to topic!\\r\\n\");\n        }\n\n        while (1) {\n            /* Receive MQTT packet with 1000ms timeout */\n            if ((res = lwesp_mqtt_client_api_receive(client, &buf, 5000)) == lwespOK) {\n                if (buf != NULL) {\n                    printf(\"Publish received!\\r\\n\");\n                    printf(\"Topic: %s, payload: %s\\r\\n\", buf->topic, buf->payload);\n                    lwesp_mqtt_client_api_buf_free(buf);\n                    buf = NULL;\n                }\n            } else if (res == lwespCLOSED) {\n                printf(\"MQTT connection closed!\\r\\n\");\n                break;\n            } else if (res == lwespTIMEOUT) {\n                printf(\"Timeout on MQTT receive function. Manually publishing.\\r\\n\");\n\n                /* Publish data on channel 1 */\n                prv_generate_random(random_str);\n                sprintf(mqtt_topic_str, \"v1/%s/things/%s/data/1\", mqtt_client_info.user, mqtt_client_info.id);\n                sprintf(mqtt_topic_data, \"temp,c=%s\", random_str);\n                lwesp_mqtt_client_api_publish(client, mqtt_topic_str, mqtt_topic_data, strlen(mqtt_topic_data),\n                                              LWESP_MQTT_QOS_AT_LEAST_ONCE, 0);\n            }\n        }\n        //goto terminate;\n    }\n\nterminate:\n    lwesp_mqtt_client_api_delete(client);\n    printf(\"MQTT client thread terminate\\r\\n\");\n    lwesp_sys_thread_terminate(NULL);\n}\n"
  },
  {
    "path": "snippets/mqtt_client_api_ha.c",
    "content": "/*\n * Home assistant sensor and switch control demo\n */\n#include \"lwesp/apps/lwesp_mqtt_client_api.h\"\n#include \"lwesp/lwesp_mem.h\"\n#include \"math.h\"\n#include \"mqtt_client_api.h\"\n\n#define ASZ(x) (sizeof(x) / sizeof((x)[0]))\n#define RUN_LWESP_API(api_call)                                                                                        \\\n    do {                                                                                                               \\\n        lwespr_t err = (api_call);                                                                                     \\\n        if (err != lwespOK) {                                                                                          \\\n            printf(\"API CALL on line %u did not return OK. Err code: %u\\r\\n\", (unsigned)__LINE__, (unsigned)err);      \\\n        }                                                                                                              \\\n    } while (0)\n\n/* Setup device information */\n#define DEVICE_MODEL                       \"8R-1L-1TS\"\n#define DEVICE_UNIQUE_ID                   \"123498DB\"\n#define DEVICE_UNIQUE_TOPIC_ID             DEVICE_MODEL \"-\" DEVICE_UNIQUE_ID\n#define DEVICE_SERIAL_NUMBER               \"ABCDEF-2321312-32143432-432424324324\"\n#define PREFIX_DISCOVERY                   \"homeassistant\"\n#define DEVICE_OP_TOPIC_PREFIX             \"ha/tm/\" DEVICE_UNIQUE_TOPIC_ID\n\n#define SENSOR_DESC_TOPIC_DISCOVERY_CONFIG PREFIX_DISCOVERY \"/sensor/\" DEVICE_UNIQUE_TOPIC_ID \"/ts_%02u/config\"\n#define SENSOR_DESC_TOPIC_PREFIX           DEVICE_OP_TOPIC_PREFIX \"/ts/%02u\"\n#define SENSOR_DESC_TOPIC_STATE            SENSOR_DESC_TOPIC_PREFIX \"/s/stat\"\n#define SENSOR_DESC_CONFIG                                                                                             \\\n    \"{\"                                                                                                                \\\n    \"    \\\"~\\\": \\\"\" SENSOR_DESC_TOPIC_PREFIX \"\\\",\"                                                                     \\\n    \"    \\\"name\\\": \\\"Temp sens %02u\\\",\"                                                                                \\\n    \"    \\\"object_id\\\": \\\"temperature_%02u\\\",\"                                                                         \\\n    \"    \\\"unique_id\\\": \\\"ts_\" DEVICE_UNIQUE_ID \"_%02u\\\",\"                                                             \\\n    \"    \\\"device_class\\\": \\\"temperature\\\",\"                                                                           \\\n    \"    \\\"stat_t\\\": \\\"~/s/stat\\\",\"                                                                                    \\\n    \"    \\\"unit_of_measurement\\\": \\\"°C\\\",\"                                                                            \\\n    \"    \\\"value_template\\\": \\\"{{ value_json.temperature }}\\\",\"                                                        \\\n    \"    \\\"device\\\": {\"                                                                                                \\\n    \"        \\\"identifiers\\\": [\"                                                                                       \\\n    \"            \\\"switch_unit_DEADBEEF\\\"\"                                                                             \\\n    \"        ],\"                                                                                                       \\\n    \"        \\\"name\\\": \\\"\" DEVICE_MODEL \"-\" DEVICE_UNIQUE_ID \"\\\",\"                                                     \\\n    \"        \\\"model\\\": \\\"\" DEVICE_MODEL \"\\\",\"                                                                         \\\n    \"        \\\"manufacturer\\\": \\\"MaJerle\\\",\"                                                                           \\\n    \"        \\\"serial_number\\\": \\\"\" DEVICE_SERIAL_NUMBER \"\\\",\"                                                         \\\n    \"        \\\"sw_version\\\": \\\"1.2.3-\" __DATE__ \"-\" __TIME__ \"\\\",\"                                                     \\\n    \"        \\\"hw_version\\\": \\\"4.5.6\\\"\"                                                                                \\\n    \"    }\"                                                                                                            \\\n    \"}\"\n\n#define SWITCH_DESC_TOPIC_DISCOVERY_CONFIG PREFIX_DISCOVERY \"/switch/\" DEVICE_UNIQUE_TOPIC_ID \"/switch_%02u/config\"\n#define SWITCH_DESC_TOPIC_PREFIX           DEVICE_OP_TOPIC_PREFIX \"/switch/%02u\"\n#define SWITCH_DESC_TOPIC_COMMAND          SWITCH_DESC_TOPIC_PREFIX \"/c/cmd\"\n#define SWITCH_DESC_TOPIC_STATE            SWITCH_DESC_TOPIC_PREFIX \"/s/stat\"\n#define SWITCH_DESC_CONFIG                                                                                             \\\n    \"{\"                                                                                                                \\\n    \"    \\\"~\\\": \\\"\" SWITCH_DESC_TOPIC_PREFIX \"\\\",\"                                                                     \\\n    \"    \\\"name\\\": \\\"Switch %02u\\\",\"                                                                                   \\\n    \"    \\\"object_id\\\": \\\"switch_%02u\\\",\"                                                                              \\\n    \"    \\\"unique_id\\\": \\\"switch_\" DEVICE_UNIQUE_ID \"_%02u\\\",\"                                                         \\\n    \"    \\\"device_class\\\": \\\"switch\\\",\"                                                                                \\\n    \"    \\\"cmd_t\\\": \\\"~/c/cmd\\\",\"                                                                                      \\\n    \"    \\\"stat_t\\\": \\\"~/s/stat\\\",\"                                                                                    \\\n    \"    \\\"device\\\": {\"                                                                                                \\\n    \"        \\\"identifiers\\\": [\"                                                                                       \\\n    \"            \\\"switch_unit_DEADBEEF\\\"\"                                                                             \\\n    \"        ]\"                                                                                                        \\\n    \"    }\"                                                                                                            \\\n    \"}\"\n\n#define TRIAC_DESC_TOPIC_DISCOVERY_CONFIG PREFIX_DISCOVERY \"/light/\" DEVICE_UNIQUE_TOPIC_ID \"/triac_%02u/config\"\n#define TRIAC_DESC_TOPIC_PREFIX           DEVICE_OP_TOPIC_PREFIX \"/triac/%02u\"\n#define TRIAC_DESC_TOPIC_COMMAND          TRIAC_DESC_TOPIC_PREFIX \"/c/cmd\"\n#define TRIAC_DESC_TOPIC_STATE            TRIAC_DESC_TOPIC_PREFIX \"/s/stat\"\n#define TRIAC_DESC_TOPIC_BRIGHTNESS       TRIAC_DESC_TOPIC_PREFIX \"/c/bri\"\n#define TRIAC_DESC_TOPIC_BRIGHTNESS_STATE TRIAC_DESC_TOPIC_PREFIX \"/s/bri\"\n#define TRIAC_DESC_CONFIG                                                                                              \\\n    \"{\"                                                                                                                \\\n    \"    \\\"~\\\": \\\"\" TRIAC_DESC_TOPIC_PREFIX \"\\\",\"                                                                      \\\n    \"    \\\"name\\\": \\\"Triac %02u\\\",\"                                                                                    \\\n    \"    \\\"object_id\\\": \\\"triac_%02u\\\",\"                                                                               \\\n    \"    \\\"unique_id\\\": \\\"triac_\" DEVICE_UNIQUE_ID \"_%02u\\\",\"                                                          \\\n    \"    \\\"device_class\\\": \\\"light\\\",\"                                                                                 \\\n    \"    \\\"cmd_t\\\": \\\"~/c/cmd\\\",\"                                                                                      \\\n    \"    \\\"stat_t\\\": \\\"~/s/stat\\\",\"                                                                                    \\\n    \"    \\\"bri_cmd_t\\\": \\\"~/c/bri\\\",\"                                                                                  \\\n    \"    \\\"bri_stat_t\\\": \\\"~/s/bri\\\",\"                                                                                 \\\n    \"    \\\"brightness_value_template\\\": \\\"{{ value_json.brightness }}\\\",\"                                              \\\n    \"    \\\"icon\\\": \\\"mdi:lightbulb-on-50\\\",\"                                                                           \\\n    \"    \\\"device\\\": {\"                                                                                                \\\n    \"        \\\"identifiers\\\": [\"                                                                                       \\\n    \"            \\\"switch_unit_DEADBEEF\\\"\"                                                                             \\\n    \"        ]\"                                                                                                        \\\n    \"    }\"                                                                                                            \\\n    \"}\"\n\n#define RGBSTRIP_DESC_TOPIC_DISCOVERY_CONFIG PREFIX_DISCOVERY \"/light/\" DEVICE_UNIQUE_TOPIC_ID \"/rgbstrip_%02u/config\"\n#define RGBSTRIP_DESC_TOPIC_PREFIX           DEVICE_OP_TOPIC_PREFIX \"/rgbstrip/%02u\"\n#define RGBSTRIP_DESC_TOPIC_COMMAND          RGBSTRIP_DESC_TOPIC_PREFIX \"/c/cmd\"\n#define RGBSTRIP_DESC_TOPIC_STATE            RGBSTRIP_DESC_TOPIC_PREFIX \"/s/stat\"\n#define RGBSTRIP_DESC_TOPIC_BRIGHTNESS       RGBSTRIP_DESC_TOPIC_PREFIX \"/c/bri\"\n#define RGBSTRIP_DESC_TOPIC_BRIGHTNESS_STATE RGBSTRIP_DESC_TOPIC_PREFIX \"/s/bri\"\n#define RGBSTRIP_DESC_TOPIC_COLOR_TEMP       RGBSTRIP_DESC_TOPIC_PREFIX \"/c/clr_temp\"\n#define RGBSTRIP_DESC_TOPIC_COLOR_TEMP_STATE RGBSTRIP_DESC_TOPIC_PREFIX \"/s/clr_temp\"\n#define RGBSTRIP_DESC_TOPIC_COLOR_MODE       RGBSTRIP_DESC_TOPIC_PREFIX \"/c/clrm\"\n#define RGBSTRIP_DESC_TOPIC_COLOR_MODE_STATE RGBSTRIP_DESC_TOPIC_PREFIX \"/s/clrm\"\n#define RGBSTRIP_DESC_TOPIC_RGB              RGBSTRIP_DESC_TOPIC_PREFIX \"/c/rgb\"\n#define RGBSTRIP_DESC_TOPIC_RGB_STATE        RGBSTRIP_DESC_TOPIC_PREFIX \"/s/rgb\"\n#define RGBSTRIP_DESC_TOPIC_EFFECT           RGBSTRIP_DESC_TOPIC_PREFIX \"/c/effect\"\n#define RGBSTRIP_DESC_TOPIC_EFFECT_STATE     RGBSTRIP_DESC_TOPIC_PREFIX \"/s/effect\"\n#define RGBSTRIP_DESC_CONFIG                                                                                           \\\n    \"{\"                                                                                                                \\\n    \"    \\\"~\\\": \\\"\" RGBSTRIP_DESC_TOPIC_PREFIX \"\\\",\"                                                                   \\\n    \"    \\\"name\\\": \\\"RGB strip %02u\\\",\"                                                                                \\\n    \"    \\\"object_id\\\": \\\"rgbstrip_%02u\\\",\"                                                                            \\\n    \"    \\\"unique_id\\\": \\\"rgbstrip_\" DEVICE_UNIQUE_ID \"_%02u\\\",\"                                                       \\\n    \"    \\\"device_class\\\": \\\"light\\\",\"                                                                                 \\\n    \"\" /* \"    \\\"schema\\\": \\\"json\\\",\"  - enabled if you want everything in a single command  */                        \\\n    \"    \\\"cmd_t\\\": \\\"~/c/cmd\\\",\"                                                                                      \\\n    \"    \\\"stat_t\\\": \\\"~/s/stat\\\",\"                                                                                    \\\n    \"    \\\"bri_cmd_t\\\": \\\"~/c/bri\\\",\"                                                                                  \\\n    \"    \\\"bri_stat_t\\\": \\\"~/s/bri\\\",\"                                                                                 \\\n    \"    \\\"brightness_value_template\\\": \\\"{{ value_json.brightness }}\\\",\"                                              \\\n    \"    \\\"clr_temp_cmd_t\\\": \\\"~/c/clr_temp\\\",\"                                                                        \\\n    \"    \\\"clr_temp_stat_t\\\": \\\"~/s/clr_temp\\\",\"                                                                       \\\n    \"    \\\"rgb_cmd_t\\\": \\\"~/c/rgb\\\",\"                                                                                  \\\n    \"    \\\"rgb_stat_t\\\": \\\"~/s/rgb\\\",\"                                                                                 \\\n    \"    \\\"sup_clrm\\\": [\\\"color_temp\\\",\\\"rgb\\\",\\\"white\\\"],\"                                                            \\\n    \"    \\\"effect_command_topic\\\": \\\"~/c/effect\\\",\"                                                                    \\\n    \"    \\\"effect_state_topic\\\": \\\"~/s/effect\\\",\"                                                                      \\\n    \"    \\\"effect\\\": true,\"                                                                                            \\\n    \"    \\\"effect_list\\\": [\"                                                                                           \\\n    \"        \\\"Static\\\",\"                                                                                              \\\n    \"        \\\"Blink\\\",\"                                                                                               \\\n    \"        \\\"Breath\\\",\"                                                                                              \\\n    \"        \\\"Color Wipe\\\"\"                                                                                           \\\n    \"    ],\"                                                                                                           \\\n    \"    \\\"device\\\": {\"                                                                                                \\\n    \"        \\\"identifiers\\\": [\"                                                                                       \\\n    \"            \\\"switch_unit_DEADBEEF\\\"\"                                                                             \\\n    \"        ]\"                                                                                                        \\\n    \"    }\"                                                                                                            \\\n    \"}\"\n\n#define LOCK_DESC_TOPIC_DISCOVERY_CONFIG PREFIX_DISCOVERY \"/lock/\" DEVICE_UNIQUE_TOPIC_ID \"/lock_%02u/config\"\n#define LOCK_DESC_TOPIC_PREFIX           DEVICE_OP_TOPIC_PREFIX \"/lock/%02u\"\n#define LOCK_DESC_TOPIC_COMMAND          LOCK_DESC_TOPIC_PREFIX \"/c/cmd\"\n#define LOCK_DESC_TOPIC_STATE            LOCK_DESC_TOPIC_PREFIX \"/s/stat\"\n#define LOCK_DESC_CONFIG                                                                                               \\\n    \"{\"                                                                                                                \\\n    \"    \\\"~\\\": \\\"\" LOCK_DESC_TOPIC_PREFIX \"\\\",\"                                                                       \\\n    \"    \\\"name\\\": \\\"Lock %02u\\\",\"                                                                                     \\\n    \"    \\\"object_id\\\": \\\"lock_%02u\\\",\"                                                                                \\\n    \"    \\\"unique_id\\\": \\\"lock_\" DEVICE_UNIQUE_ID \"_%02u\\\",\"                                                           \\\n    \"    \\\"device_class\\\": \\\"lock\\\",\"                                                                                  \\\n    \"    \\\"cmd_t\\\": \\\"~/c/cmd\\\",\"                                                                                      \\\n    \"    \\\"stat_t\\\": \\\"~/s/stat\\\",\"                                                                                    \\\n    \"    \\\"code_format\\\": \\\"^\\\\\\\\d{4}$\\\",\"                                                                             \\\n    \"    \\\"command_template\\\": \\\"{ \\\\\\\"action\\\\\\\": \\\\\\\"{{ value }}\\\\\\\", \\\\\\\"code\\\\\\\":\\\\\\\"{{ code }}\\\\\\\" }\\\",\"          \\\n    \"    \\\"device\\\": {\"                                                                                                \\\n    \"        \\\"identifiers\\\": [\"                                                                                       \\\n    \"            \\\"switch_unit_DEADBEEF\\\"\"                                                                             \\\n    \"        ]\"                                                                                                        \\\n    \"    }\"                                                                                                            \\\n    \"}\"\n\n/**\n * \\brief           Kelvin to RGB conversion structure\n * \n */\ntypedef struct {\n    uint16_t mired;\n    uint16_t kelvin;\n    uint8_t r, g, b;\n} mired_kelvin_rgb_pair_t;\n\n/* mired * kelvin = 10000000 */\n#define MIRED_KELVIN_TO_RGB_ENTRY(_mired, _kelvin, _r, _g, _b)                                                         \\\n    { .mired = _mired, .kelvin = _kelvin, .r = _r, .g = _g, .b = _b }\nstatic const mired_kelvin_rgb_pair_t mired_kelvin_rgb_pairs[] = {\n    MIRED_KELVIN_TO_RGB_ENTRY(100, 10000, 201, 218, 255), MIRED_KELVIN_TO_RGB_ENTRY(101, 9900, 202, 218, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(102, 9803, 203, 218, 255),  MIRED_KELVIN_TO_RGB_ENTRY(103, 9708, 203, 219, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(104, 9615, 204, 219, 255),  MIRED_KELVIN_TO_RGB_ENTRY(105, 9523, 205, 220, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(106, 9433, 205, 220, 255),  MIRED_KELVIN_TO_RGB_ENTRY(107, 9345, 206, 221, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(108, 9259, 207, 221, 255),  MIRED_KELVIN_TO_RGB_ENTRY(109, 9174, 208, 221, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(110, 9090, 208, 222, 255),  MIRED_KELVIN_TO_RGB_ENTRY(111, 9009, 209, 222, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(112, 8928, 210, 223, 255),  MIRED_KELVIN_TO_RGB_ENTRY(113, 8849, 211, 223, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(114, 8771, 211, 224, 255),  MIRED_KELVIN_TO_RGB_ENTRY(115, 8695, 212, 224, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(116, 8620, 213, 225, 255),  MIRED_KELVIN_TO_RGB_ENTRY(117, 8547, 214, 225, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(118, 8474, 215, 226, 255),  MIRED_KELVIN_TO_RGB_ENTRY(119, 8403, 215, 226, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(120, 8333, 216, 227, 255),  MIRED_KELVIN_TO_RGB_ENTRY(121, 8264, 217, 227, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(122, 8196, 218, 228, 255),  MIRED_KELVIN_TO_RGB_ENTRY(123, 8130, 219, 228, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(124, 8064, 220, 229, 255),  MIRED_KELVIN_TO_RGB_ENTRY(125, 8000, 221, 229, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(126, 7936, 222, 230, 255),  MIRED_KELVIN_TO_RGB_ENTRY(127, 7874, 223, 230, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(128, 7812, 224, 231, 255),  MIRED_KELVIN_TO_RGB_ENTRY(129, 7751, 225, 232, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(130, 7692, 226, 232, 255),  MIRED_KELVIN_TO_RGB_ENTRY(131, 7633, 227, 233, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(132, 7575, 228, 233, 255),  MIRED_KELVIN_TO_RGB_ENTRY(133, 7518, 229, 234, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(134, 7462, 230, 235, 255),  MIRED_KELVIN_TO_RGB_ENTRY(135, 7407, 231, 235, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(136, 7352, 233, 236, 255),  MIRED_KELVIN_TO_RGB_ENTRY(137, 7299, 234, 237, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(138, 7246, 235, 238, 255),  MIRED_KELVIN_TO_RGB_ENTRY(139, 7194, 236, 238, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(140, 7142, 238, 239, 255),  MIRED_KELVIN_TO_RGB_ENTRY(141, 7092, 239, 240, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(142, 7042, 241, 241, 255),  MIRED_KELVIN_TO_RGB_ENTRY(143, 6993, 242, 242, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(144, 6944, 244, 243, 255),  MIRED_KELVIN_TO_RGB_ENTRY(145, 6896, 246, 244, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(146, 6849, 247, 245, 255),  MIRED_KELVIN_TO_RGB_ENTRY(147, 6802, 249, 246, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(148, 6756, 251, 247, 255),  MIRED_KELVIN_TO_RGB_ENTRY(149, 6711, 253, 248, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(150, 6666, 255, 249, 255),  MIRED_KELVIN_TO_RGB_ENTRY(151, 6622, 255, 250, 255),\n    MIRED_KELVIN_TO_RGB_ENTRY(152, 6578, 255, 255, 251),  MIRED_KELVIN_TO_RGB_ENTRY(153, 6535, 255, 254, 250),\n    MIRED_KELVIN_TO_RGB_ENTRY(154, 6493, 255, 254, 249),  MIRED_KELVIN_TO_RGB_ENTRY(155, 6451, 255, 253, 248),\n    MIRED_KELVIN_TO_RGB_ENTRY(156, 6410, 255, 252, 247),  MIRED_KELVIN_TO_RGB_ENTRY(157, 6369, 255, 252, 246),\n    MIRED_KELVIN_TO_RGB_ENTRY(158, 6329, 255, 251, 245),  MIRED_KELVIN_TO_RGB_ENTRY(159, 6289, 255, 250, 244),\n    MIRED_KELVIN_TO_RGB_ENTRY(160, 6250, 255, 250, 243),  MIRED_KELVIN_TO_RGB_ENTRY(161, 6211, 255, 249, 242),\n    MIRED_KELVIN_TO_RGB_ENTRY(162, 6172, 255, 248, 241),  MIRED_KELVIN_TO_RGB_ENTRY(163, 6134, 255, 248, 240),\n    MIRED_KELVIN_TO_RGB_ENTRY(164, 6097, 255, 247, 239),  MIRED_KELVIN_TO_RGB_ENTRY(165, 6060, 255, 247, 238),\n    MIRED_KELVIN_TO_RGB_ENTRY(166, 6024, 255, 246, 237),  MIRED_KELVIN_TO_RGB_ENTRY(167, 5988, 255, 245, 236),\n    MIRED_KELVIN_TO_RGB_ENTRY(168, 5952, 255, 245, 235),  MIRED_KELVIN_TO_RGB_ENTRY(169, 5917, 255, 244, 234),\n    MIRED_KELVIN_TO_RGB_ENTRY(170, 5882, 255, 244, 233),  MIRED_KELVIN_TO_RGB_ENTRY(171, 5847, 255, 243, 232),\n    MIRED_KELVIN_TO_RGB_ENTRY(172, 5813, 255, 242, 231),  MIRED_KELVIN_TO_RGB_ENTRY(173, 5780, 255, 242, 230),\n    MIRED_KELVIN_TO_RGB_ENTRY(174, 5747, 255, 241, 229),  MIRED_KELVIN_TO_RGB_ENTRY(175, 5714, 255, 241, 228),\n    MIRED_KELVIN_TO_RGB_ENTRY(176, 5681, 255, 240, 227),  MIRED_KELVIN_TO_RGB_ENTRY(177, 5649, 255, 240, 226),\n    MIRED_KELVIN_TO_RGB_ENTRY(178, 5617, 255, 239, 225),  MIRED_KELVIN_TO_RGB_ENTRY(179, 5586, 255, 239, 224),\n    MIRED_KELVIN_TO_RGB_ENTRY(180, 5555, 255, 238, 223),  MIRED_KELVIN_TO_RGB_ENTRY(181, 5524, 255, 237, 222),\n    MIRED_KELVIN_TO_RGB_ENTRY(182, 5494, 255, 237, 222),  MIRED_KELVIN_TO_RGB_ENTRY(183, 5464, 255, 236, 221),\n    MIRED_KELVIN_TO_RGB_ENTRY(184, 5434, 255, 236, 220),  MIRED_KELVIN_TO_RGB_ENTRY(185, 5405, 255, 235, 219),\n    MIRED_KELVIN_TO_RGB_ENTRY(186, 5376, 255, 235, 218),  MIRED_KELVIN_TO_RGB_ENTRY(187, 5347, 255, 234, 217),\n    MIRED_KELVIN_TO_RGB_ENTRY(188, 5319, 255, 234, 216),  MIRED_KELVIN_TO_RGB_ENTRY(189, 5291, 255, 233, 215),\n    MIRED_KELVIN_TO_RGB_ENTRY(190, 5263, 255, 233, 214),  MIRED_KELVIN_TO_RGB_ENTRY(191, 5235, 255, 232, 213),\n    MIRED_KELVIN_TO_RGB_ENTRY(192, 5208, 255, 232, 212),  MIRED_KELVIN_TO_RGB_ENTRY(193, 5181, 255, 231, 212),\n    MIRED_KELVIN_TO_RGB_ENTRY(194, 5154, 255, 231, 211),  MIRED_KELVIN_TO_RGB_ENTRY(195, 5128, 255, 230, 210),\n    MIRED_KELVIN_TO_RGB_ENTRY(196, 5102, 255, 230, 209),  MIRED_KELVIN_TO_RGB_ENTRY(197, 5076, 255, 229, 208),\n    MIRED_KELVIN_TO_RGB_ENTRY(198, 5050, 255, 229, 207),  MIRED_KELVIN_TO_RGB_ENTRY(199, 5025, 255, 228, 206),\n    MIRED_KELVIN_TO_RGB_ENTRY(200, 5000, 255, 228, 205),  MIRED_KELVIN_TO_RGB_ENTRY(201, 4975, 255, 227, 205),\n    MIRED_KELVIN_TO_RGB_ENTRY(202, 4950, 255, 227, 204),  MIRED_KELVIN_TO_RGB_ENTRY(203, 4926, 255, 226, 203),\n    MIRED_KELVIN_TO_RGB_ENTRY(204, 4901, 255, 226, 202),  MIRED_KELVIN_TO_RGB_ENTRY(205, 4878, 255, 225, 201),\n    MIRED_KELVIN_TO_RGB_ENTRY(206, 4854, 255, 225, 200),  MIRED_KELVIN_TO_RGB_ENTRY(207, 4830, 255, 224, 199),\n    MIRED_KELVIN_TO_RGB_ENTRY(208, 4807, 255, 224, 199),  MIRED_KELVIN_TO_RGB_ENTRY(209, 4784, 255, 223, 198),\n    MIRED_KELVIN_TO_RGB_ENTRY(210, 4761, 255, 223, 197),  MIRED_KELVIN_TO_RGB_ENTRY(211, 4739, 255, 222, 196),\n    MIRED_KELVIN_TO_RGB_ENTRY(212, 4716, 255, 222, 195),  MIRED_KELVIN_TO_RGB_ENTRY(213, 4694, 255, 221, 194),\n    MIRED_KELVIN_TO_RGB_ENTRY(214, 4672, 255, 221, 194),  MIRED_KELVIN_TO_RGB_ENTRY(215, 4651, 255, 220, 193),\n    MIRED_KELVIN_TO_RGB_ENTRY(216, 4629, 255, 220, 192),  MIRED_KELVIN_TO_RGB_ENTRY(217, 4608, 255, 219, 191),\n    MIRED_KELVIN_TO_RGB_ENTRY(218, 4587, 255, 219, 190),  MIRED_KELVIN_TO_RGB_ENTRY(219, 4566, 255, 218, 190),\n    MIRED_KELVIN_TO_RGB_ENTRY(220, 4545, 255, 218, 189),  MIRED_KELVIN_TO_RGB_ENTRY(221, 4524, 255, 218, 188),\n    MIRED_KELVIN_TO_RGB_ENTRY(222, 4504, 255, 217, 187),  MIRED_KELVIN_TO_RGB_ENTRY(223, 4484, 255, 217, 186),\n    MIRED_KELVIN_TO_RGB_ENTRY(224, 4464, 255, 216, 186),  MIRED_KELVIN_TO_RGB_ENTRY(225, 4444, 255, 216, 185),\n    MIRED_KELVIN_TO_RGB_ENTRY(226, 4424, 255, 215, 184),  MIRED_KELVIN_TO_RGB_ENTRY(227, 4405, 255, 215, 183),\n    MIRED_KELVIN_TO_RGB_ENTRY(228, 4385, 255, 214, 182),  MIRED_KELVIN_TO_RGB_ENTRY(229, 4366, 255, 214, 182),\n    MIRED_KELVIN_TO_RGB_ENTRY(230, 4347, 255, 214, 181),  MIRED_KELVIN_TO_RGB_ENTRY(231, 4329, 255, 213, 180),\n    MIRED_KELVIN_TO_RGB_ENTRY(232, 4310, 255, 213, 179),  MIRED_KELVIN_TO_RGB_ENTRY(233, 4291, 255, 212, 178),\n    MIRED_KELVIN_TO_RGB_ENTRY(234, 4273, 255, 212, 178),  MIRED_KELVIN_TO_RGB_ENTRY(235, 4255, 255, 211, 177),\n    MIRED_KELVIN_TO_RGB_ENTRY(236, 4237, 255, 211, 176),  MIRED_KELVIN_TO_RGB_ENTRY(237, 4219, 255, 211, 175),\n    MIRED_KELVIN_TO_RGB_ENTRY(238, 4201, 255, 210, 175),  MIRED_KELVIN_TO_RGB_ENTRY(239, 4184, 255, 210, 174),\n    MIRED_KELVIN_TO_RGB_ENTRY(240, 4166, 255, 209, 173),  MIRED_KELVIN_TO_RGB_ENTRY(241, 4149, 255, 209, 172),\n    MIRED_KELVIN_TO_RGB_ENTRY(242, 4132, 255, 209, 172),  MIRED_KELVIN_TO_RGB_ENTRY(243, 4115, 255, 208, 171),\n    MIRED_KELVIN_TO_RGB_ENTRY(244, 4098, 255, 208, 170),  MIRED_KELVIN_TO_RGB_ENTRY(245, 4081, 255, 207, 169),\n    MIRED_KELVIN_TO_RGB_ENTRY(246, 4065, 255, 207, 169),  MIRED_KELVIN_TO_RGB_ENTRY(247, 4048, 255, 207, 168),\n    MIRED_KELVIN_TO_RGB_ENTRY(248, 4032, 255, 206, 167),  MIRED_KELVIN_TO_RGB_ENTRY(249, 4016, 255, 206, 166),\n    MIRED_KELVIN_TO_RGB_ENTRY(250, 4000, 255, 205, 166),  MIRED_KELVIN_TO_RGB_ENTRY(251, 3984, 255, 205, 165),\n    MIRED_KELVIN_TO_RGB_ENTRY(252, 3968, 255, 205, 164),  MIRED_KELVIN_TO_RGB_ENTRY(253, 3952, 255, 204, 163),\n    MIRED_KELVIN_TO_RGB_ENTRY(254, 3937, 255, 204, 163),  MIRED_KELVIN_TO_RGB_ENTRY(255, 3921, 255, 203, 162),\n    MIRED_KELVIN_TO_RGB_ENTRY(256, 3906, 255, 203, 161),  MIRED_KELVIN_TO_RGB_ENTRY(257, 3891, 255, 203, 160),\n    MIRED_KELVIN_TO_RGB_ENTRY(258, 3875, 255, 202, 160),  MIRED_KELVIN_TO_RGB_ENTRY(259, 3861, 255, 202, 159),\n    MIRED_KELVIN_TO_RGB_ENTRY(260, 3846, 255, 201, 158),  MIRED_KELVIN_TO_RGB_ENTRY(261, 3831, 255, 201, 158),\n    MIRED_KELVIN_TO_RGB_ENTRY(262, 3816, 255, 201, 157),  MIRED_KELVIN_TO_RGB_ENTRY(263, 3802, 255, 200, 156),\n    MIRED_KELVIN_TO_RGB_ENTRY(264, 3787, 255, 200, 155),  MIRED_KELVIN_TO_RGB_ENTRY(265, 3773, 255, 200, 155),\n    MIRED_KELVIN_TO_RGB_ENTRY(266, 3759, 255, 199, 154),  MIRED_KELVIN_TO_RGB_ENTRY(267, 3745, 255, 199, 153),\n    MIRED_KELVIN_TO_RGB_ENTRY(268, 3731, 255, 198, 153),  MIRED_KELVIN_TO_RGB_ENTRY(269, 3717, 255, 198, 152),\n    MIRED_KELVIN_TO_RGB_ENTRY(270, 3703, 255, 198, 151),  MIRED_KELVIN_TO_RGB_ENTRY(271, 3690, 255, 197, 150),\n    MIRED_KELVIN_TO_RGB_ENTRY(272, 3676, 255, 197, 150),  MIRED_KELVIN_TO_RGB_ENTRY(273, 3663, 255, 197, 149),\n    MIRED_KELVIN_TO_RGB_ENTRY(274, 3649, 255, 196, 148),  MIRED_KELVIN_TO_RGB_ENTRY(275, 3636, 255, 196, 148),\n    MIRED_KELVIN_TO_RGB_ENTRY(276, 3623, 255, 195, 147),  MIRED_KELVIN_TO_RGB_ENTRY(277, 3610, 255, 195, 146),\n    MIRED_KELVIN_TO_RGB_ENTRY(278, 3597, 255, 195, 146),  MIRED_KELVIN_TO_RGB_ENTRY(279, 3584, 255, 194, 145),\n    MIRED_KELVIN_TO_RGB_ENTRY(280, 3571, 255, 194, 144),  MIRED_KELVIN_TO_RGB_ENTRY(281, 3558, 255, 194, 144),\n    MIRED_KELVIN_TO_RGB_ENTRY(282, 3546, 255, 193, 143),  MIRED_KELVIN_TO_RGB_ENTRY(283, 3533, 255, 193, 142),\n    MIRED_KELVIN_TO_RGB_ENTRY(284, 3521, 255, 193, 141),  MIRED_KELVIN_TO_RGB_ENTRY(285, 3508, 255, 192, 141),\n    MIRED_KELVIN_TO_RGB_ENTRY(286, 3496, 255, 192, 140),  MIRED_KELVIN_TO_RGB_ENTRY(287, 3484, 255, 192, 139),\n    MIRED_KELVIN_TO_RGB_ENTRY(288, 3472, 255, 191, 139),  MIRED_KELVIN_TO_RGB_ENTRY(289, 3460, 255, 191, 138),\n    MIRED_KELVIN_TO_RGB_ENTRY(290, 3448, 255, 191, 137),  MIRED_KELVIN_TO_RGB_ENTRY(291, 3436, 255, 190, 137),\n    MIRED_KELVIN_TO_RGB_ENTRY(292, 3424, 255, 190, 136),  MIRED_KELVIN_TO_RGB_ENTRY(293, 3412, 255, 190, 135),\n    MIRED_KELVIN_TO_RGB_ENTRY(294, 3401, 255, 189, 135),  MIRED_KELVIN_TO_RGB_ENTRY(295, 3389, 255, 189, 134),\n    MIRED_KELVIN_TO_RGB_ENTRY(296, 3378, 255, 189, 133),  MIRED_KELVIN_TO_RGB_ENTRY(297, 3367, 255, 188, 133),\n    MIRED_KELVIN_TO_RGB_ENTRY(298, 3355, 255, 188, 132),  MIRED_KELVIN_TO_RGB_ENTRY(299, 3344, 255, 187, 131),\n    MIRED_KELVIN_TO_RGB_ENTRY(300, 3333, 255, 187, 131),  MIRED_KELVIN_TO_RGB_ENTRY(301, 3322, 255, 187, 130),\n    MIRED_KELVIN_TO_RGB_ENTRY(302, 3311, 255, 187, 129),  MIRED_KELVIN_TO_RGB_ENTRY(303, 3300, 255, 186, 129),\n    MIRED_KELVIN_TO_RGB_ENTRY(304, 3289, 255, 186, 128),  MIRED_KELVIN_TO_RGB_ENTRY(305, 3278, 255, 186, 127),\n    MIRED_KELVIN_TO_RGB_ENTRY(306, 3267, 255, 185, 127),  MIRED_KELVIN_TO_RGB_ENTRY(307, 3257, 255, 185, 126),\n    MIRED_KELVIN_TO_RGB_ENTRY(308, 3246, 255, 185, 125),  MIRED_KELVIN_TO_RGB_ENTRY(309, 3236, 255, 184, 125),\n    MIRED_KELVIN_TO_RGB_ENTRY(310, 3225, 255, 184, 124),  MIRED_KELVIN_TO_RGB_ENTRY(311, 3215, 255, 184, 124),\n    MIRED_KELVIN_TO_RGB_ENTRY(312, 3205, 255, 183, 123),  MIRED_KELVIN_TO_RGB_ENTRY(313, 3194, 255, 183, 122),\n    MIRED_KELVIN_TO_RGB_ENTRY(314, 3184, 255, 183, 122),  MIRED_KELVIN_TO_RGB_ENTRY(315, 3174, 255, 182, 121),\n    MIRED_KELVIN_TO_RGB_ENTRY(316, 3164, 255, 182, 120),  MIRED_KELVIN_TO_RGB_ENTRY(317, 3154, 255, 182, 120),\n    MIRED_KELVIN_TO_RGB_ENTRY(318, 3144, 255, 181, 119),  MIRED_KELVIN_TO_RGB_ENTRY(319, 3134, 255, 181, 118),\n    MIRED_KELVIN_TO_RGB_ENTRY(320, 3125, 255, 181, 118),  MIRED_KELVIN_TO_RGB_ENTRY(321, 3115, 255, 180, 117),\n    MIRED_KELVIN_TO_RGB_ENTRY(322, 3105, 255, 180, 117),  MIRED_KELVIN_TO_RGB_ENTRY(323, 3095, 255, 180, 116),\n    MIRED_KELVIN_TO_RGB_ENTRY(324, 3086, 255, 180, 115),  MIRED_KELVIN_TO_RGB_ENTRY(325, 3076, 255, 179, 115),\n    MIRED_KELVIN_TO_RGB_ENTRY(326, 3067, 255, 179, 114),  MIRED_KELVIN_TO_RGB_ENTRY(327, 3058, 255, 179, 113),\n    MIRED_KELVIN_TO_RGB_ENTRY(328, 3048, 255, 178, 113),  MIRED_KELVIN_TO_RGB_ENTRY(329, 3039, 255, 178, 112),\n    MIRED_KELVIN_TO_RGB_ENTRY(330, 3030, 255, 178, 111),  MIRED_KELVIN_TO_RGB_ENTRY(331, 3021, 255, 177, 111),\n    MIRED_KELVIN_TO_RGB_ENTRY(332, 3012, 255, 177, 110),  MIRED_KELVIN_TO_RGB_ENTRY(333, 3003, 255, 177, 110),\n    MIRED_KELVIN_TO_RGB_ENTRY(334, 2994, 255, 177, 109),  MIRED_KELVIN_TO_RGB_ENTRY(335, 2985, 255, 176, 108),\n    MIRED_KELVIN_TO_RGB_ENTRY(336, 2976, 255, 176, 108),  MIRED_KELVIN_TO_RGB_ENTRY(337, 2967, 255, 176, 107),\n    MIRED_KELVIN_TO_RGB_ENTRY(338, 2958, 255, 175, 106),  MIRED_KELVIN_TO_RGB_ENTRY(339, 2949, 255, 175, 106),\n    MIRED_KELVIN_TO_RGB_ENTRY(340, 2941, 255, 175, 105),  MIRED_KELVIN_TO_RGB_ENTRY(341, 2932, 255, 174, 105),\n    MIRED_KELVIN_TO_RGB_ENTRY(342, 2923, 255, 174, 104),  MIRED_KELVIN_TO_RGB_ENTRY(343, 2915, 255, 174, 103),\n    MIRED_KELVIN_TO_RGB_ENTRY(344, 2906, 255, 174, 103),  MIRED_KELVIN_TO_RGB_ENTRY(345, 2898, 255, 173, 102),\n    MIRED_KELVIN_TO_RGB_ENTRY(346, 2890, 255, 173, 102),  MIRED_KELVIN_TO_RGB_ENTRY(347, 2881, 255, 173, 101),\n    MIRED_KELVIN_TO_RGB_ENTRY(348, 2873, 255, 172, 100),  MIRED_KELVIN_TO_RGB_ENTRY(349, 2865, 255, 172, 100),\n    MIRED_KELVIN_TO_RGB_ENTRY(350, 2857, 255, 172, 99),   MIRED_KELVIN_TO_RGB_ENTRY(351, 2849, 255, 172, 99),\n    MIRED_KELVIN_TO_RGB_ENTRY(352, 2840, 255, 171, 98),   MIRED_KELVIN_TO_RGB_ENTRY(353, 2832, 255, 171, 97),\n    MIRED_KELVIN_TO_RGB_ENTRY(354, 2824, 255, 171, 97),   MIRED_KELVIN_TO_RGB_ENTRY(355, 2816, 255, 170, 96),\n    MIRED_KELVIN_TO_RGB_ENTRY(356, 2808, 255, 170, 95),   MIRED_KELVIN_TO_RGB_ENTRY(357, 2801, 255, 170, 95),\n    MIRED_KELVIN_TO_RGB_ENTRY(358, 2793, 255, 170, 94),   MIRED_KELVIN_TO_RGB_ENTRY(359, 2785, 255, 169, 94),\n    MIRED_KELVIN_TO_RGB_ENTRY(360, 2777, 255, 169, 93),   MIRED_KELVIN_TO_RGB_ENTRY(361, 2770, 255, 169, 92),\n    MIRED_KELVIN_TO_RGB_ENTRY(362, 2762, 255, 168, 92),   MIRED_KELVIN_TO_RGB_ENTRY(363, 2754, 255, 168, 91),\n    MIRED_KELVIN_TO_RGB_ENTRY(364, 2747, 255, 168, 91),   MIRED_KELVIN_TO_RGB_ENTRY(365, 2739, 255, 168, 90),\n    MIRED_KELVIN_TO_RGB_ENTRY(366, 2732, 255, 167, 89),   MIRED_KELVIN_TO_RGB_ENTRY(367, 2724, 255, 167, 89),\n    MIRED_KELVIN_TO_RGB_ENTRY(368, 2717, 255, 167, 88),   MIRED_KELVIN_TO_RGB_ENTRY(369, 2710, 255, 167, 88),\n    MIRED_KELVIN_TO_RGB_ENTRY(370, 2702, 255, 166, 87),   MIRED_KELVIN_TO_RGB_ENTRY(371, 2695, 255, 166, 86),\n    MIRED_KELVIN_TO_RGB_ENTRY(372, 2688, 255, 166, 86),   MIRED_KELVIN_TO_RGB_ENTRY(373, 2680, 255, 165, 85),\n    MIRED_KELVIN_TO_RGB_ENTRY(374, 2673, 255, 165, 85),   MIRED_KELVIN_TO_RGB_ENTRY(375, 2666, 255, 165, 84),\n    MIRED_KELVIN_TO_RGB_ENTRY(376, 2659, 255, 165, 84),   MIRED_KELVIN_TO_RGB_ENTRY(377, 2652, 255, 164, 83),\n    MIRED_KELVIN_TO_RGB_ENTRY(378, 2645, 255, 164, 82),   MIRED_KELVIN_TO_RGB_ENTRY(379, 2638, 255, 164, 82),\n    MIRED_KELVIN_TO_RGB_ENTRY(380, 2631, 255, 164, 81),   MIRED_KELVIN_TO_RGB_ENTRY(381, 2624, 255, 163, 81),\n    MIRED_KELVIN_TO_RGB_ENTRY(382, 2617, 255, 163, 80),   MIRED_KELVIN_TO_RGB_ENTRY(383, 2610, 255, 163, 79),\n    MIRED_KELVIN_TO_RGB_ENTRY(384, 2604, 255, 163, 79),   MIRED_KELVIN_TO_RGB_ENTRY(385, 2597, 255, 162, 78),\n    MIRED_KELVIN_TO_RGB_ENTRY(386, 2590, 255, 162, 78),   MIRED_KELVIN_TO_RGB_ENTRY(387, 2583, 255, 162, 77),\n    MIRED_KELVIN_TO_RGB_ENTRY(388, 2577, 255, 162, 77),   MIRED_KELVIN_TO_RGB_ENTRY(389, 2570, 255, 161, 76),\n    MIRED_KELVIN_TO_RGB_ENTRY(390, 2564, 255, 161, 75),   MIRED_KELVIN_TO_RGB_ENTRY(391, 2557, 255, 161, 75),\n    MIRED_KELVIN_TO_RGB_ENTRY(392, 2551, 255, 161, 74),   MIRED_KELVIN_TO_RGB_ENTRY(393, 2544, 255, 160, 74),\n    MIRED_KELVIN_TO_RGB_ENTRY(394, 2538, 255, 160, 73),   MIRED_KELVIN_TO_RGB_ENTRY(395, 2531, 255, 160, 72),\n    MIRED_KELVIN_TO_RGB_ENTRY(396, 2525, 255, 160, 72),   MIRED_KELVIN_TO_RGB_ENTRY(397, 2518, 255, 159, 71),\n    MIRED_KELVIN_TO_RGB_ENTRY(398, 2512, 255, 159, 71),   MIRED_KELVIN_TO_RGB_ENTRY(399, 2506, 255, 159, 70),\n    MIRED_KELVIN_TO_RGB_ENTRY(400, 2500, 255, 159, 70),   MIRED_KELVIN_TO_RGB_ENTRY(401, 2493, 255, 158, 69),\n    MIRED_KELVIN_TO_RGB_ENTRY(402, 2487, 255, 158, 68),   MIRED_KELVIN_TO_RGB_ENTRY(403, 2481, 255, 158, 68),\n    MIRED_KELVIN_TO_RGB_ENTRY(404, 2475, 255, 158, 67),   MIRED_KELVIN_TO_RGB_ENTRY(405, 2469, 255, 157, 67),\n    MIRED_KELVIN_TO_RGB_ENTRY(406, 2463, 255, 157, 66),   MIRED_KELVIN_TO_RGB_ENTRY(407, 2457, 255, 157, 66),\n    MIRED_KELVIN_TO_RGB_ENTRY(408, 2450, 255, 157, 65),   MIRED_KELVIN_TO_RGB_ENTRY(409, 2444, 255, 156, 64),\n    MIRED_KELVIN_TO_RGB_ENTRY(410, 2439, 255, 156, 64),   MIRED_KELVIN_TO_RGB_ENTRY(411, 2433, 255, 156, 63),\n    MIRED_KELVIN_TO_RGB_ENTRY(412, 2427, 255, 156, 63),   MIRED_KELVIN_TO_RGB_ENTRY(413, 2421, 255, 155, 62),\n    MIRED_KELVIN_TO_RGB_ENTRY(414, 2415, 255, 155, 61),   MIRED_KELVIN_TO_RGB_ENTRY(415, 2409, 255, 155, 61),\n    MIRED_KELVIN_TO_RGB_ENTRY(416, 2403, 255, 155, 60),   MIRED_KELVIN_TO_RGB_ENTRY(417, 2398, 255, 154, 60),\n    MIRED_KELVIN_TO_RGB_ENTRY(418, 2392, 255, 154, 59),   MIRED_KELVIN_TO_RGB_ENTRY(419, 2386, 255, 154, 59),\n    MIRED_KELVIN_TO_RGB_ENTRY(420, 2380, 255, 154, 58),   MIRED_KELVIN_TO_RGB_ENTRY(421, 2375, 255, 153, 58),\n    MIRED_KELVIN_TO_RGB_ENTRY(422, 2369, 255, 153, 57),   MIRED_KELVIN_TO_RGB_ENTRY(423, 2364, 255, 153, 56),\n    MIRED_KELVIN_TO_RGB_ENTRY(424, 2358, 255, 153, 56),   MIRED_KELVIN_TO_RGB_ENTRY(425, 2352, 255, 152, 55),\n    MIRED_KELVIN_TO_RGB_ENTRY(426, 2347, 255, 152, 55),   MIRED_KELVIN_TO_RGB_ENTRY(427, 2341, 255, 152, 54),\n    MIRED_KELVIN_TO_RGB_ENTRY(428, 2336, 255, 152, 54),   MIRED_KELVIN_TO_RGB_ENTRY(429, 2331, 255, 152, 53),\n    MIRED_KELVIN_TO_RGB_ENTRY(430, 2325, 255, 151, 52),   MIRED_KELVIN_TO_RGB_ENTRY(431, 2320, 255, 151, 52),\n    MIRED_KELVIN_TO_RGB_ENTRY(432, 2314, 255, 151, 51),   MIRED_KELVIN_TO_RGB_ENTRY(433, 2309, 255, 151, 51),\n    MIRED_KELVIN_TO_RGB_ENTRY(434, 2304, 255, 150, 50),   MIRED_KELVIN_TO_RGB_ENTRY(435, 2298, 255, 150, 50),\n    MIRED_KELVIN_TO_RGB_ENTRY(436, 2293, 255, 150, 49),   MIRED_KELVIN_TO_RGB_ENTRY(437, 2288, 255, 150, 48),\n    MIRED_KELVIN_TO_RGB_ENTRY(438, 2283, 255, 150, 48),   MIRED_KELVIN_TO_RGB_ENTRY(439, 2277, 255, 149, 47),\n    MIRED_KELVIN_TO_RGB_ENTRY(440, 2272, 255, 149, 47),   MIRED_KELVIN_TO_RGB_ENTRY(441, 2267, 255, 149, 46),\n    MIRED_KELVIN_TO_RGB_ENTRY(442, 2262, 255, 149, 46),   MIRED_KELVIN_TO_RGB_ENTRY(443, 2257, 255, 148, 45),\n    MIRED_KELVIN_TO_RGB_ENTRY(444, 2252, 255, 148, 45),   MIRED_KELVIN_TO_RGB_ENTRY(445, 2247, 255, 148, 44),\n    MIRED_KELVIN_TO_RGB_ENTRY(446, 2242, 255, 148, 43),   MIRED_KELVIN_TO_RGB_ENTRY(447, 2237, 255, 148, 43),\n    MIRED_KELVIN_TO_RGB_ENTRY(448, 2232, 255, 147, 42),   MIRED_KELVIN_TO_RGB_ENTRY(449, 2227, 255, 147, 42),\n    MIRED_KELVIN_TO_RGB_ENTRY(450, 2222, 255, 147, 41),   MIRED_KELVIN_TO_RGB_ENTRY(451, 2217, 255, 147, 41),\n    MIRED_KELVIN_TO_RGB_ENTRY(452, 2212, 255, 146, 40),   MIRED_KELVIN_TO_RGB_ENTRY(453, 2207, 255, 146, 39),\n    MIRED_KELVIN_TO_RGB_ENTRY(454, 2202, 255, 146, 39),   MIRED_KELVIN_TO_RGB_ENTRY(455, 2197, 255, 146, 38),\n    MIRED_KELVIN_TO_RGB_ENTRY(456, 2192, 255, 145, 38),   MIRED_KELVIN_TO_RGB_ENTRY(457, 2188, 255, 145, 37),\n    MIRED_KELVIN_TO_RGB_ENTRY(458, 2183, 255, 145, 37),   MIRED_KELVIN_TO_RGB_ENTRY(459, 2178, 255, 145, 36),\n    MIRED_KELVIN_TO_RGB_ENTRY(460, 2173, 255, 145, 36),   MIRED_KELVIN_TO_RGB_ENTRY(461, 2169, 255, 144, 35),\n    MIRED_KELVIN_TO_RGB_ENTRY(462, 2164, 255, 144, 34),   MIRED_KELVIN_TO_RGB_ENTRY(463, 2159, 255, 144, 34),\n    MIRED_KELVIN_TO_RGB_ENTRY(464, 2155, 255, 144, 33),   MIRED_KELVIN_TO_RGB_ENTRY(465, 2150, 255, 144, 33),\n    MIRED_KELVIN_TO_RGB_ENTRY(466, 2145, 255, 143, 32),   MIRED_KELVIN_TO_RGB_ENTRY(467, 2141, 255, 143, 32),\n    MIRED_KELVIN_TO_RGB_ENTRY(468, 2136, 255, 143, 31),   MIRED_KELVIN_TO_RGB_ENTRY(469, 2132, 255, 143, 31),\n    MIRED_KELVIN_TO_RGB_ENTRY(470, 2127, 255, 142, 30),   MIRED_KELVIN_TO_RGB_ENTRY(471, 2123, 255, 142, 29),\n    MIRED_KELVIN_TO_RGB_ENTRY(472, 2118, 255, 142, 29),   MIRED_KELVIN_TO_RGB_ENTRY(473, 2114, 255, 142, 28),\n    MIRED_KELVIN_TO_RGB_ENTRY(474, 2109, 255, 142, 28),   MIRED_KELVIN_TO_RGB_ENTRY(475, 2105, 255, 141, 27),\n    MIRED_KELVIN_TO_RGB_ENTRY(476, 2100, 255, 141, 27),   MIRED_KELVIN_TO_RGB_ENTRY(477, 2096, 255, 141, 26),\n    MIRED_KELVIN_TO_RGB_ENTRY(478, 2092, 255, 141, 26),   MIRED_KELVIN_TO_RGB_ENTRY(479, 2087, 255, 141, 25),\n    MIRED_KELVIN_TO_RGB_ENTRY(480, 2083, 255, 140, 24),   MIRED_KELVIN_TO_RGB_ENTRY(481, 2079, 255, 140, 24),\n    MIRED_KELVIN_TO_RGB_ENTRY(482, 2074, 255, 140, 23),   MIRED_KELVIN_TO_RGB_ENTRY(483, 2070, 255, 140, 23),\n    MIRED_KELVIN_TO_RGB_ENTRY(484, 2066, 255, 140, 22),   MIRED_KELVIN_TO_RGB_ENTRY(485, 2061, 255, 139, 22),\n    MIRED_KELVIN_TO_RGB_ENTRY(486, 2057, 255, 139, 21),   MIRED_KELVIN_TO_RGB_ENTRY(487, 2053, 255, 139, 21),\n    MIRED_KELVIN_TO_RGB_ENTRY(488, 2049, 255, 139, 20),   MIRED_KELVIN_TO_RGB_ENTRY(489, 2044, 255, 139, 19),\n    MIRED_KELVIN_TO_RGB_ENTRY(490, 2040, 255, 138, 19),   MIRED_KELVIN_TO_RGB_ENTRY(491, 2036, 255, 138, 18),\n    MIRED_KELVIN_TO_RGB_ENTRY(492, 2032, 255, 138, 18),   MIRED_KELVIN_TO_RGB_ENTRY(493, 2028, 255, 138, 17),\n    MIRED_KELVIN_TO_RGB_ENTRY(494, 2024, 255, 138, 17),   MIRED_KELVIN_TO_RGB_ENTRY(495, 2020, 255, 137, 16),\n    MIRED_KELVIN_TO_RGB_ENTRY(496, 2016, 255, 137, 16),   MIRED_KELVIN_TO_RGB_ENTRY(497, 2012, 255, 137, 15),\n    MIRED_KELVIN_TO_RGB_ENTRY(498, 2008, 255, 137, 15),   MIRED_KELVIN_TO_RGB_ENTRY(499, 2004, 255, 137, 14),\n    MIRED_KELVIN_TO_RGB_ENTRY(500, 2000, 255, 136, 13),   MIRED_KELVIN_TO_RGB_ENTRY(501, 1996, 255, 136, 13),\n    MIRED_KELVIN_TO_RGB_ENTRY(502, 1992, 255, 136, 12),   MIRED_KELVIN_TO_RGB_ENTRY(503, 1988, 255, 136, 12),\n    MIRED_KELVIN_TO_RGB_ENTRY(504, 1984, 255, 136, 11),   MIRED_KELVIN_TO_RGB_ENTRY(505, 1980, 255, 135, 11),\n    MIRED_KELVIN_TO_RGB_ENTRY(506, 1976, 255, 135, 10),   MIRED_KELVIN_TO_RGB_ENTRY(507, 1972, 255, 135, 9),\n    MIRED_KELVIN_TO_RGB_ENTRY(508, 1968, 255, 135, 9),    MIRED_KELVIN_TO_RGB_ENTRY(509, 1964, 255, 135, 8),\n    MIRED_KELVIN_TO_RGB_ENTRY(510, 1960, 255, 134, 8),    MIRED_KELVIN_TO_RGB_ENTRY(511, 1956, 255, 134, 7),\n    MIRED_KELVIN_TO_RGB_ENTRY(512, 1953, 255, 134, 7),    MIRED_KELVIN_TO_RGB_ENTRY(513, 1949, 255, 134, 6),\n    MIRED_KELVIN_TO_RGB_ENTRY(514, 1945, 255, 134, 6),    MIRED_KELVIN_TO_RGB_ENTRY(515, 1941, 255, 133, 5),\n    MIRED_KELVIN_TO_RGB_ENTRY(516, 1937, 255, 133, 4),    MIRED_KELVIN_TO_RGB_ENTRY(517, 1934, 255, 133, 4),\n    MIRED_KELVIN_TO_RGB_ENTRY(518, 1930, 255, 133, 3),    MIRED_KELVIN_TO_RGB_ENTRY(519, 1926, 255, 133, 3),\n    MIRED_KELVIN_TO_RGB_ENTRY(520, 1923, 255, 132, 2),    MIRED_KELVIN_TO_RGB_ENTRY(521, 1919, 255, 132, 2),\n    MIRED_KELVIN_TO_RGB_ENTRY(522, 1915, 255, 132, 1),    MIRED_KELVIN_TO_RGB_ENTRY(523, 1912, 255, 132, 1),\n    MIRED_KELVIN_TO_RGB_ENTRY(524, 1908, 255, 132, 0),    MIRED_KELVIN_TO_RGB_ENTRY(525, 1904, 255, 131, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(526, 1901, 255, 131, 0),    MIRED_KELVIN_TO_RGB_ENTRY(527, 1897, 255, 131, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(528, 1893, 255, 131, 0),    MIRED_KELVIN_TO_RGB_ENTRY(529, 1890, 255, 131, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(530, 1886, 255, 131, 0),    MIRED_KELVIN_TO_RGB_ENTRY(531, 1883, 255, 130, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(532, 1879, 255, 130, 0),    MIRED_KELVIN_TO_RGB_ENTRY(533, 1876, 255, 130, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(534, 1872, 255, 130, 0),    MIRED_KELVIN_TO_RGB_ENTRY(535, 1869, 255, 130, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(536, 1865, 255, 129, 0),    MIRED_KELVIN_TO_RGB_ENTRY(537, 1862, 255, 129, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(538, 1858, 255, 129, 0),    MIRED_KELVIN_TO_RGB_ENTRY(539, 1855, 255, 129, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(540, 1851, 255, 129, 0),    MIRED_KELVIN_TO_RGB_ENTRY(541, 1848, 255, 129, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(542, 1845, 255, 128, 0),    MIRED_KELVIN_TO_RGB_ENTRY(543, 1841, 255, 128, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(544, 1838, 255, 128, 0),    MIRED_KELVIN_TO_RGB_ENTRY(545, 1834, 255, 128, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(546, 1831, 255, 128, 0),    MIRED_KELVIN_TO_RGB_ENTRY(547, 1828, 255, 127, 0),\n    MIRED_KELVIN_TO_RGB_ENTRY(548, 1824, 255, 127, 0),    MIRED_KELVIN_TO_RGB_ENTRY(549, 1821, 255, 127, 0),\n};\n\n/* Argument data... */\ntypedef enum {\n    ARG_GROUP_1 = 0x01, /*!< Must start with non-zero, which indicates \"NULL\" */\n    ARG_GROUP_2,\n    ARG_GROUP_3,\n    ARG_GROUP_4,\n    ARG_GROUP_5,\n    ARG_GROUP_6,\n} arg_groups_t;\n\ntypedef enum {\n    /* The three commands we can receive */\n    LOCK_STATE_LOCK = 0,\n    LOCK_STATE_UNLOCK,\n    LOCK_STATE_OPEN,\n\n    /* Then states we have later */\n    LOCK_STATE_OK,\n    LOCK_STATE_LOCKED,\n    LOCK_STATE_LOCKING,\n    LOCK_STATE_UNLOCKED,\n    LOCK_STATE_UNLOCKING,\n    LOCK_STATE_JAMMED,\n} lock_state_t;\n\n/* List of commands in string, much match the enumeration sequence */\nstatic const char* lock_state_strings[] = {\n    /* Command from server */\n    \"LOCK\",\n    \"UNLOCK\",\n    \"OPEN\",\n    /* States */\n    \"OK\",\n    \"LOCKED\",\n    \"LOCKING\",\n    \"UNLOCKED\",\n    \"UNLOCKING\",\n    \"JAMMED\",\n};\n\n/**\n * \\brief           Connection information for MQTT CONNECT packet\n */\nstatic const lwesp_mqtt_client_info_t mqtt_client_info = {\n    .keep_alive = 10,\n\n    /* Server login data */\n    //.user = \"8a215f70-a644-11e8-ac49-e932ed599553\",\n    //.pass = \"26aa943f702e5e780f015cd048a91e8fb54cca28\",\n\n    /* Device identifier address */\n    .id = \"123869f5a20-af9c-11e9-b01f-db5cf74e7fb7\",\n};\n\nstatic char mqtt_topic_str[1024];  /*!< Topic string */\nstatic char mqtt_topic_data[1024]; /*!< Data string */\nstatic volatile uint8_t mqtt_is_connected, mqtt_connection_trial_failed, immediate_update = 0;\n\ntypedef struct user_data {\n    /* Switch */\n    uint8_t switch_states[4];\n    uint8_t switch_states_update[4];\n    /* Triac */\n    uint8_t triac_states[4];\n    uint8_t triac_states_update[4];\n    uint8_t triac_brightness[4];\n    uint8_t triac_brightness_update[4];\n    /* Sensor */\n    float ts_data[4];\n    uint8_t ts_data_update[4];\n    /* RGB */\n    uint8_t rgb_states[4];\n    uint8_t rgb_states_update[4];\n    uint8_t rgb_colors[4][3];\n    uint8_t rgb_colors_update[4];\n    uint8_t rgb_brightness[4];\n    uint8_t rgb_brightness_update[4];\n    uint16_t rgb_temp[4];\n    uint8_t rgb_temp_update[4];\n    char rgb_effect[4][32];\n    uint8_t rgb_effect_update[4];\n    /* Lock */\n    lock_state_t lock_states[4];\n    uint8_t lock_states_update[4];\n    uint32_t lock_states_last_updated[4];\n} user_data_t;\n\nstatic user_data_t app_io_data;\n\n/**\n * \\brief           Parse the number until characters are valid\n * \n * \\param           pptr: Pointer to pointer to string. It will modify the output variable after reading the data\n * \\param[in]       ptr: String pointer to parse\n * \\param[in]       count: Pointer to an initialized variable where function can modify number of bytes read\n * \\param[in]       max_count: Total length of the string in bytes\n * \\param[in]       check_comma: If set to `1`, it checks for comma and advances the string one step further\n * \\return          Return the parsed number\n */\nstatic uint32_t\nprv_parse_number(const char* ptr, uint32_t* count, uint32_t max_count, uint8_t check_comma) {\n    uint32_t number = 0;\n\n    if (check_comma && *count < max_count && ptr[*count] == ',') {\n        ++(*count);\n    }\n    for (; *count < max_count && ptr[*count] >= '0' && ptr[*count] <= '9'; ++(*count)) {\n        number = 10 * number + (ptr[*count] - '0');\n    }\n    if (check_comma && *count < max_count && ptr[*count] == ',') {\n        ++(*count);\n    }\n    return number;\n}\n\n/**\n * \\brief           Custom publish function, a wrapper for \\ref lwesp_mqtt_client_publish with print functionatlity\n * \n * \\param           client \n * \\param           topic \n * \\param           payload \n * \\param           payload_len \n * \\param           qos \n * \\param           retain \n * \\param           arg \n * \\return          lwespr_t \n */\nstatic lwespr_t\nlwesp_mqtt_client_publish_custom(lwesp_mqtt_client_p client, const char* topic, const void* payload,\n                                 uint16_t payload_len, lwesp_mqtt_qos_t qos, uint8_t retain, void* arg) {\n    lwespr_t res = lwesp_mqtt_client_publish(client, topic, payload, payload_len, qos, retain, arg);\n    printf(\"Publishing. Topic: %s, data: %.*s, res: %u\\r\\n\", topic, (int)payload_len, (const char*)payload,\n           (unsigned)res);\n\n    return res;\n}\n\n/**\n * \\brief           MQTT connection event function\n * \n * \\param           client: MQTT client instance\n * \\param           evt: Event with data\n */\nstatic void\nprv_mqtt_evt_fn(lwesp_mqtt_client_p client, lwesp_mqtt_evt_t* evt) {\n    switch (evt->type) {\n        case LWESP_MQTT_EVT_CONNECT: {\n            if (evt->evt.connect.status == LWESP_MQTT_CONN_STATUS_ACCEPTED) {\n                printf(\"Device accepted\\r\\n\");\n\n                /* Subscribe to necessary topics... */\n                RUN_LWESP_API(\n                    lwesp_mqtt_client_subscribe(client, \"homeassistant/status\", LWESP_MQTT_QOS_AT_LEAST_ONCE, NULL));\n                RUN_LWESP_API(lwesp_mqtt_client_subscribe(client, DEVICE_OP_TOPIC_PREFIX \"/+/+/c/#\",\n                                                          LWESP_MQTT_QOS_AT_LEAST_ONCE, NULL));\n                RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, \"homeassistant/status\", \"ON\", 2,\n                                                               LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, (void*)ARG_GROUP_1));\n            } else {\n                mqtt_connection_trial_failed = 1;\n                printf(\"MQTT device not connected\\r\\n\");\n            }\n            break;\n        }\n        case LWESP_MQTT_EVT_DISCONNECT: {\n            printf(\"MQTT disconnect event\\r\\n\");\n            mqtt_is_connected = 0;\n            RUN_LWESP_API(lwesp_mqtt_client_connect(client, \"192.168.1.16\", 1883, prv_mqtt_evt_fn, &mqtt_client_info));\n            break;\n        }\n        case LWESP_MQTT_EVT_PUBLISH_RECV: {\n            const char* topic_name = (const void*)evt->evt.publish_recv.topic;\n            const size_t topic_len = evt->evt.publish_recv.topic_len;\n            const char* payload = (const void*)evt->evt.publish_recv.payload;\n            const size_t payload_len = evt->evt.publish_recv.payload_len;\n            static char command_topic_string[128];\n            uint8_t found = 0;\n\n            printf(\"Publish received. Topic: %.*s, payload: %.*s\\r\\n\", (int)topic_len, topic_name, (int)payload_len,\n                   payload);\n\n            /* Check switches */\n            if (!found) {\n                for (size_t i = 0; i < ASZ(app_io_data.switch_states); ++i) {\n                    sprintf(command_topic_string, SWITCH_DESC_TOPIC_COMMAND, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n                        uint8_t state = strncmp(evt->evt.publish_recv.payload, \"ON\", 2) == 0;\n                        if (state != app_io_data.switch_states[i]) {\n                            app_io_data.switch_states[i] = state;\n                            app_io_data.switch_states_update[i] = 1;\n                        }\n                        printf(\"Switch command: id=%u, value=%u\\r\\n\", (unsigned)(i + 1),\n                               (unsigned)app_io_data.switch_states[i]);\n                        found = 1;\n                        break;\n                    }\n                }\n            }\n\n            /* Check Triacs */\n            if (!found) {\n                for (size_t i = 0; i < ASZ(app_io_data.triac_states); ++i) {\n                    /* Check set command */\n                    sprintf(command_topic_string, TRIAC_DESC_TOPIC_COMMAND, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n                        uint8_t state = strncmp(evt->evt.publish_recv.payload, \"ON\", 2) == 0;\n                        if (state != app_io_data.triac_states[i]) {\n                            app_io_data.triac_states[i] = state;\n                            app_io_data.triac_states_update[i] = 1;\n                        }\n                        printf(\"Triac command: id=%u, value=%u\\r\\n\", (unsigned)(i + 1),\n                               (unsigned)app_io_data.triac_states[i]);\n                        found = 1;\n                        break;\n                    }\n\n                    /* Check brightness command */\n                    sprintf(command_topic_string, TRIAC_DESC_TOPIC_BRIGHTNESS, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n                        uint32_t cnt = 0, number;\n\n                        number = prv_parse_number(payload, &cnt, payload_len, 1);\n                        if (number != app_io_data.triac_brightness[i]) {\n                            app_io_data.triac_brightness[i] = number;\n                            app_io_data.triac_brightness_update[i] = 1;\n                        }\n                        printf(\"Triac brightness: id=%u, value=%u\\r\\n\", (unsigned)(i + 1),\n                               (unsigned)app_io_data.triac_brightness[i]);\n                        found = 1;\n                        break;\n                    }\n                }\n            }\n\n            /* Check RGB strip */\n            if (!found) {\n                for (size_t i = 0; i < ASZ(app_io_data.rgb_states); ++i) {\n                    /* Check set command */\n                    sprintf(command_topic_string, RGBSTRIP_DESC_TOPIC_COMMAND, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n                        uint8_t state = strncmp(evt->evt.publish_recv.payload, \"ON\", 2) == 0;\n                        if (state != app_io_data.rgb_states[i]) {\n                            app_io_data.rgb_states[i] = state;\n                            app_io_data.rgb_states_update[i] = 1;\n                        }\n                        printf(\"Light command: id=%u, value=%u\\r\\n\", (unsigned)(i + 1),\n                               (unsigned)app_io_data.rgb_states[i]);\n                        found = 1;\n                        break;\n                    }\n\n                    /* Check brightness command */\n                    sprintf(command_topic_string, RGBSTRIP_DESC_TOPIC_BRIGHTNESS, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n                        uint32_t cnt = 0, number;\n\n                        number = prv_parse_number(payload, &cnt, payload_len, 1);\n                        if (number != app_io_data.rgb_brightness[i]) {\n                            app_io_data.rgb_brightness[i] = number;\n                            app_io_data.rgb_brightness_update[i] = 1;\n                        }\n                        printf(\"Light brightness command: id=%u, value=%u\\r\\n\", (unsigned)(i + 1),\n                               (unsigned)app_io_data.rgb_brightness[i]);\n                        found = 1;\n                        break;\n                    }\n\n                    /* Check color temperature command */\n                    sprintf(command_topic_string, RGBSTRIP_DESC_TOPIC_COLOR_TEMP, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n                        uint32_t cnt = 0, number;\n\n                        number = prv_parse_number(payload, &cnt, payload_len, 1);\n                        if (number != app_io_data.rgb_temp[i]) {\n                            app_io_data.rgb_temp[i] = number;\n                            app_io_data.rgb_temp_update[i] = 1;\n\n                            /* Save RGB color now, since it has changed */\n                            for (size_t keypair_idx = 0; keypair_idx < ASZ(mired_kelvin_rgb_pairs); ++keypair_idx) {\n                                if (mired_kelvin_rgb_pairs[keypair_idx].mired == number) {\n                                    app_io_data.rgb_colors[i][0] = mired_kelvin_rgb_pairs[keypair_idx].r;\n                                    app_io_data.rgb_colors[i][1] = mired_kelvin_rgb_pairs[keypair_idx].g;\n                                    app_io_data.rgb_colors[i][2] = mired_kelvin_rgb_pairs[keypair_idx].b;\n                                    printf(\"Light RGB set from color temp command: id=%u, value=%u,%u,%u\\r\\n\",\n                                           (unsigned)(i + 1), (unsigned)app_io_data.rgb_colors[i][0],\n                                           (unsigned)app_io_data.rgb_colors[i][1],\n                                           (unsigned)app_io_data.rgb_colors[i][2]);\n                                    break;\n                                }\n                            }\n                        }\n                        printf(\"Light temperature command: id=%u, value=%u\\r\\n\", (unsigned)(i + 1),\n                               (unsigned)app_io_data.rgb_temp[i]);\n                        found = 1;\n                        break;\n                    }\n\n                    /* Check RGB command */\n                    sprintf(command_topic_string, RGBSTRIP_DESC_TOPIC_RGB, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n                        uint32_t cnt = 0, number;\n\n                        /* We parse up to 3 characters */\n                        number = prv_parse_number(payload, &cnt, payload_len, 1);\n                        if (number != app_io_data.rgb_colors[i][0]) {\n                            app_io_data.rgb_colors[i][0] = number;\n                            app_io_data.rgb_colors_update[i] = 1;\n                        }\n                        number = prv_parse_number(payload, &cnt, payload_len, 1);\n                        if (number != app_io_data.rgb_colors[i][1]) {\n                            app_io_data.rgb_colors[i][1] = number;\n                            app_io_data.rgb_colors_update[i] = 1;\n                        }\n                        number = prv_parse_number(payload, &cnt, payload_len, 1);\n                        if (number != app_io_data.rgb_colors[i][2]) {\n                            app_io_data.rgb_colors[i][2] = number;\n                            app_io_data.rgb_colors_update[i] = 1;\n                        }\n                        found = 1;\n                        printf(\"Light RGB command: id=%u, value=%u,%u,%u\\r\\n\", (unsigned)(i + 1),\n                               (unsigned)app_io_data.rgb_colors[i][0], (unsigned)app_io_data.rgb_colors[i][1],\n                               (unsigned)app_io_data.rgb_colors[i][2]);\n                        break;\n                    }\n\n                    /* Check effect command */\n                    sprintf(command_topic_string, RGBSTRIP_DESC_TOPIC_EFFECT, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n                        if (strncmp(payload, app_io_data.rgb_effect[i], payload_len) != 0) {\n                            strncpy(app_io_data.rgb_effect[i], payload, sizeof(app_io_data.rgb_effect[0]));\n                            app_io_data.rgb_effect[i][sizeof(app_io_data.rgb_effect[0]) - 1] = '\\0';\n                            app_io_data.rgb_effect_update[i] = 1;\n                        }\n                        printf(\"Light effect command: id=%u, value=%s\\r\\n\", (unsigned)(i + 1),\n                               app_io_data.rgb_effect[i]);\n                        found = 1;\n                        break;\n                    }\n                }\n            }\n\n            /* Check locks */\n            if (!found) {\n                for (size_t i = 0; i < ASZ(app_io_data.lock_states); ++i) {\n                    sprintf(command_topic_string, LOCK_DESC_TOPIC_COMMAND, (unsigned)(i + 1));\n                    if (strncmp(command_topic_string, topic_name, topic_len) == 0) {\n\n                        /* Check if string in strings array match, then use the index as a state from enumeration */\n                        for (size_t strings_index = 0; strings_index < ASZ(lock_state_strings); ++strings_index) {\n                            if (strncmp(payload, lock_state_strings[strings_index], payload_len) == 0) {\n                                /* We found a state, check if indexes match now */\n                                if ((lock_state_t)strings_index != app_io_data.lock_states[i]) {\n                                    app_io_data.lock_states[i] = (lock_state_t)strings_index;\n                                    /* We do not update immediately - it will be handled in the processing function */\n                                }\n                                found = 1;\n                                break;\n                            }\n                        }\n                    }\n                }\n            }\n\n            if (found) {\n                immediate_update = 1;\n            }\n            break;\n        }\n        case LWESP_MQTT_EVT_SUBSCRIBE: {\n            break;\n        }\n        case LWESP_MQTT_EVT_PUBLISH: {\n\n            if (evt->evt.publish.arg == (void*)ARG_GROUP_1) {\n                /* Update sensors */\n                for (size_t i = 0; i < ASZ(app_io_data.ts_data); ++i) {\n                    uint32_t id = (i + 1);\n\n                    sprintf(mqtt_topic_str, SENSOR_DESC_TOPIC_DISCOVERY_CONFIG, (unsigned)id);\n                    sprintf(mqtt_topic_data, SENSOR_DESC_CONFIG, (unsigned)id, (unsigned)id, (unsigned)id,\n                            (unsigned)id);\n                    RUN_LWESP_API(lwesp_mqtt_client_publish_custom(\n                        client, mqtt_topic_str, mqtt_topic_data, strlen(mqtt_topic_data), LWESP_MQTT_QOS_AT_LEAST_ONCE,\n                        0, i == 3 ? (void*)ARG_GROUP_2 : NULL));\n                }\n            } else if (evt->evt.publish.arg == (void*)ARG_GROUP_2) {\n                /* Send RGB strips */\n                for (size_t i = 0; i < ASZ(app_io_data.rgb_states); ++i) {\n                    uint32_t id = (i + 1);\n\n                    sprintf(mqtt_topic_str, RGBSTRIP_DESC_TOPIC_DISCOVERY_CONFIG, (unsigned)id);\n                    sprintf(mqtt_topic_data, RGBSTRIP_DESC_CONFIG, (unsigned)id, (unsigned)id, (unsigned)id,\n                            (unsigned)id);\n                    RUN_LWESP_API(lwesp_mqtt_client_publish_custom(\n                        client, mqtt_topic_str, mqtt_topic_data, strlen(mqtt_topic_data), LWESP_MQTT_QOS_AT_LEAST_ONCE,\n                        0, i == 3 ? (void*)ARG_GROUP_3 : NULL));\n                }\n            } else if (evt->evt.publish.arg == (void*)ARG_GROUP_3) {\n                /* Send switch entities */\n                for (size_t i = 0; i < ASZ(app_io_data.switch_states); ++i) {\n                    uint32_t id = (i + 1);\n\n                    sprintf(mqtt_topic_str, SWITCH_DESC_TOPIC_DISCOVERY_CONFIG, (unsigned)id);\n                    sprintf(mqtt_topic_data, SWITCH_DESC_CONFIG, (unsigned)id, (unsigned)id, (unsigned)id,\n                            (unsigned)id);\n                    RUN_LWESP_API(lwesp_mqtt_client_publish_custom(\n                        client, mqtt_topic_str, mqtt_topic_data, strlen(mqtt_topic_data), LWESP_MQTT_QOS_AT_LEAST_ONCE,\n                        0, i == 3 ? (void*)ARG_GROUP_4 : NULL));\n                }\n            } else if (evt->evt.publish.arg == (void*)ARG_GROUP_4) {\n                /* Send triac entities */\n                for (size_t i = 0; i < ASZ(app_io_data.triac_states); ++i) {\n                    uint32_t id = (i + 1);\n\n                    sprintf(mqtt_topic_str, TRIAC_DESC_TOPIC_DISCOVERY_CONFIG, (unsigned)id);\n                    sprintf(mqtt_topic_data, TRIAC_DESC_CONFIG, (unsigned)id, (unsigned)id, (unsigned)id, (unsigned)id);\n                    RUN_LWESP_API(lwesp_mqtt_client_publish_custom(\n                        client, mqtt_topic_str, mqtt_topic_data, strlen(mqtt_topic_data), LWESP_MQTT_QOS_AT_LEAST_ONCE,\n                        0, i == 3 ? (void*)ARG_GROUP_5 : NULL));\n                }\n            } else if (evt->evt.publish.arg == (void*)ARG_GROUP_5) {\n                /* Send lock entities */\n                for (size_t i = 0; i < ASZ(app_io_data.lock_states); ++i) {\n                    uint32_t id = (i + 1);\n\n                    sprintf(mqtt_topic_str, LOCK_DESC_TOPIC_DISCOVERY_CONFIG, (unsigned)id);\n                    sprintf(mqtt_topic_data, LOCK_DESC_CONFIG, (unsigned)id, (unsigned)id, (unsigned)id, (unsigned)id);\n                    RUN_LWESP_API(lwesp_mqtt_client_publish_custom(\n                        client, mqtt_topic_str, mqtt_topic_data, strlen(mqtt_topic_data), LWESP_MQTT_QOS_AT_LEAST_ONCE,\n                        0, i == 3 ? (void*)ARG_GROUP_6 : NULL));\n                }\n            } else if (evt->evt.publish.arg == (void*)ARG_GROUP_6) {\n                printf(\"All groups published...\\r\\n\");\n                mqtt_is_connected = 1;\n            }\n            break;\n        }\n        case LWESP_MQTT_EVT_CONN_POLL: {\n            static uint32_t sin_counter = 0;\n            static uint32_t poll_counter;\n\n            if ((++poll_counter & 0x07) != 0) {\n                break;\n            }\n\n#if 1\n            /* Publish data temperature */\n            for (size_t i = 0; i < ASZ(app_io_data.ts_data); ++i) {\n                uint32_t id = i + 1;\n\n                /* Calculate data */\n                app_io_data.ts_data[i] = 21.0f + (float)2.0f * sinf(2.0f * 3.14f * (float)++sin_counter * 100.0f);\n\n                sprintf(mqtt_topic_str, SENSOR_DESC_TOPIC_STATE, (unsigned)id);\n                sprintf(mqtt_topic_data, \"{\\\"temperature\\\":%.3f}\", app_io_data.ts_data[i]);\n                RUN_LWESP_API(lwesp_mqtt_client_publish(client, mqtt_topic_str, mqtt_topic_data,\n                                                        strlen(mqtt_topic_data), LWESP_MQTT_QOS_AT_MOST_ONCE, 0, NULL));\n            }\n#endif\n            break;\n        }\n        default: break;\n    }\n}\n\n/**\n * \\brief           MQTT client API thread\n * \\param[in]       arg: User argument\n */\nvoid\nlwesp_mqtt_client_api_ha_thread(void const* arg) {\n    lwesp_mqtt_client_p client;\n\n    LWESP_UNUSED(arg);\n\n    if ((client = lwesp_mqtt_client_new(4096, 2048)) == NULL) {\n        goto terminate;\n    }\n\n    while (1) {\n        lwespr_t res;\n\n        /* Make a connection */\n        printf(\"Joining MQTT server\\r\\n\");\n\n        /* Connect to client */\n        mqtt_is_connected = 0;\n    try_again:\n        mqtt_connection_trial_failed = 0;\n\n        res = lwesp_mqtt_client_connect(client, \"192.168.1.16\", 1883, prv_mqtt_evt_fn, &mqtt_client_info);\n        if (res == lwespOK) {\n            printf(\"Connecting...\\r\\n\");\n            while (!mqtt_is_connected) {\n                Sleep(1000);\n                if (mqtt_connection_trial_failed) {\n                    goto try_again;\n                }\n            }\n        } else {\n            printf(\"Failed to connect: %u. Trying again\\r\\n\", (unsigned)res);\n            Sleep(1000);\n\n            goto try_again;\n        }\n        printf(\"Mqtt is now connected\\r\\n\");\n\n        /* Initialize default values before we connect -> simulate data already ON */\n        for (size_t i = 0; i < ASZ(app_io_data.rgb_states); ++i) {\n            app_io_data.rgb_states[i] = i & 1;\n            app_io_data.rgb_brightness[i] = 0x07 << i;\n            app_io_data.rgb_colors[i][0] = i << 5;\n            app_io_data.rgb_colors[i][1] = i << 0;\n            app_io_data.rgb_colors[i][2] = i << 2;\n            app_io_data.rgb_temp[i] = 1300;\n        }\n        for (size_t i = 0; i < ASZ(app_io_data.triac_states); ++i) {\n            app_io_data.triac_states[i] = i & 1;\n            app_io_data.triac_brightness[i] = 0x03 << i;\n        }\n        for (size_t i = 0; i < ASZ(app_io_data.switch_states); ++i) {\n            app_io_data.switch_states[i] = i & 1;\n        }\n\n        uint8_t first_time = 1;\n        uint32_t time_last_states_update = lwesp_sys_now();\n        while (mqtt_is_connected) {\n            uint32_t time_now = lwesp_sys_now();\n\n            if (immediate_update || (time_now - time_last_states_update) >= 5000) {\n                immediate_update = 0;\n                time_last_states_update = time_now;\n\n                /* Publish switch states */\n                for (size_t i = 0; i < ASZ(app_io_data.switch_states); ++i) {\n                    uint32_t id = i + 1;\n\n                    if (app_io_data.switch_states_update[i] || first_time) {\n                        app_io_data.switch_states_update[i] = 0;\n\n                        sprintf(mqtt_topic_str, SWITCH_DESC_TOPIC_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"%s\", app_io_data.switch_states[i] ? \"ON\" : \"OFF\");\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n                }\n\n                /* Publish RGB strip states */\n                for (size_t i = 0; i < ASZ(app_io_data.rgb_states); ++i) {\n                    uint32_t id = i + 1;\n\n                    if (app_io_data.rgb_states_update[i] || first_time) {\n                        app_io_data.rgb_states_update[i] = 0;\n\n                        /* Publish state */\n                        sprintf(mqtt_topic_str, RGBSTRIP_DESC_TOPIC_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"%s\", app_io_data.rgb_states[i] ? \"ON\" : \"OFF\");\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n\n                    if (app_io_data.rgb_brightness_update[i] || first_time) {\n                        app_io_data.rgb_brightness_update[i] = 0;\n\n                        /* Publish brightness */\n                        sprintf(mqtt_topic_str, RGBSTRIP_DESC_TOPIC_BRIGHTNESS_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"{\\\"brightness\\\":%u}\", (unsigned)app_io_data.rgb_brightness[i]);\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n\n                    if (app_io_data.rgb_temp_update[i] || first_time) {\n                        app_io_data.rgb_temp_update[i] = 0;\n\n                        /* Publish brightness */\n                        sprintf(mqtt_topic_str, RGBSTRIP_DESC_TOPIC_COLOR_TEMP_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"%u\", (unsigned)app_io_data.rgb_temp[i]);\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n\n                    if (app_io_data.rgb_colors_update[i] || first_time) {\n                        app_io_data.rgb_colors_update[i] = 0;\n\n                        /* Publish RGB color */\n                        sprintf(mqtt_topic_str, RGBSTRIP_DESC_TOPIC_RGB_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"%u,%u,%u\", (unsigned)app_io_data.rgb_colors[i][0],\n                                (unsigned)app_io_data.rgb_colors[i][1], (unsigned)app_io_data.rgb_colors[i][2]);\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n\n                    if (app_io_data.rgb_effect_update[i] || first_time) {\n                        app_io_data.rgb_effect_update[i] = 0;\n\n                        /* Publish RGB color */\n                        sprintf(mqtt_topic_str, RGBSTRIP_DESC_TOPIC_EFFECT_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"%s\", app_io_data.rgb_effect[i]);\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n                }\n\n                /* Publish triac states */\n                for (size_t i = 0; i < ASZ(app_io_data.triac_states); ++i) {\n                    uint32_t id = i + 1;\n\n                    if (app_io_data.triac_states_update[i] || first_time) {\n                        app_io_data.triac_states_update[i] = 0;\n\n                        sprintf(mqtt_topic_str, TRIAC_DESC_TOPIC_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"%s\", app_io_data.triac_states[i] ? \"ON\" : \"OFF\");\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n\n                    if (app_io_data.triac_brightness_update[i] || first_time) {\n                        app_io_data.triac_brightness_update[i] = 0;\n\n                        sprintf(mqtt_topic_str, TRIAC_DESC_TOPIC_BRIGHTNESS_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"{\\\"brightness\\\":%u}\", (unsigned)app_io_data.triac_brightness[i]);\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n                }\n\n                /* Publish lock states */\n                for (size_t i = 0; i < ASZ(app_io_data.lock_states); ++i) {\n                    uint32_t id = i + 1;\n\n                    /* Handle states... */\n\n                    if (app_io_data.lock_states_update[i] || first_time) {\n                        app_io_data.lock_states_update[i] = 0;\n\n                        sprintf(mqtt_topic_str, LOCK_DESC_TOPIC_STATE, (unsigned)id);\n                        sprintf(mqtt_topic_data, \"%s\", lock_state_strings[app_io_data.lock_states[i]]);\n                        RUN_LWESP_API(lwesp_mqtt_client_publish_custom(client, mqtt_topic_str, mqtt_topic_data,\n                                                                       strlen(mqtt_topic_data),\n                                                                       LWESP_MQTT_QOS_AT_LEAST_ONCE, 0, NULL));\n                    }\n                }\n            }\n\n            /* Handle lock states here */\n            lwesp_sys_protect();\n            for (size_t i = 0; i < ASZ(app_io_data.lock_states); ++i) {\n                switch (app_io_data.lock_states[i]) {\n                    /* Commands we can receive from the cloud */\n                    case LOCK_STATE_LOCK: {\n                        /* Let's start the locking procedure */\n                        app_io_data.lock_states[i] = LOCK_STATE_LOCKING;\n                        app_io_data.lock_states_update[i] = 1;\n                        app_io_data.lock_states_last_updated[i] = time_now;\n                        immediate_update = 1;\n                        printf(\"Locking starting\\r\\n\");\n                        break;\n                    }\n                    case LOCK_STATE_UNLOCK:\n                    case LOCK_STATE_OPEN: {\n                        /* Let's start the locking procedure */\n                        app_io_data.lock_states[i] = LOCK_STATE_UNLOCKING;\n                        app_io_data.lock_states_update[i] = 1;\n                        app_io_data.lock_states_last_updated[i] = time_now;\n                        immediate_update = 1;\n                        printf(\"Unlocking starting\\r\\n\");\n                        break;\n                    }\n\n                    /* States we can operate in... */\n                    case LOCK_STATE_LOCKING: {\n                        /* Stay in locking for some time */\n                        if (time_now - app_io_data.lock_states_last_updated[i] >= (i + 1) * 1000) {\n                            app_io_data.lock_states[i] = LOCK_STATE_LOCKED;\n                            app_io_data.lock_states_update[i] = 1;\n                            app_io_data.lock_states_last_updated[i] = time_now;\n                            immediate_update = 1;\n                            printf(\"Device is now locked\\r\\n\");\n                        }\n                        break;\n                    }\n                    case LOCK_STATE_LOCKED: {\n                        /* Nothing to do here, wait for a new command to start unlocking or opening... */\n                        break;\n                    }\n                    case LOCK_STATE_UNLOCKING: {\n                        /* Stay in locking for some time */\n                        if (time_now - app_io_data.lock_states_last_updated[i] >= (i + 1) * 1000) {\n                            app_io_data.lock_states[i] = LOCK_STATE_UNLOCKED;\n                            app_io_data.lock_states_update[i] = 1;\n                            app_io_data.lock_states_last_updated[i] = time_now;\n                            immediate_update = 1;\n                            printf(\"Unlocked!\\r\\n\");\n                        }\n                        break;\n                    }\n                    case LOCK_STATE_UNLOCKED: {\n                        /* Stay in unlocked for some time then go back to locking state */\n                        if (time_now - app_io_data.lock_states_last_updated[i] >= (i + 1) * 1000) {\n                            app_io_data.lock_states[i] = LOCK_STATE_LOCKING;\n                            app_io_data.lock_states_update[i] = 1;\n                            app_io_data.lock_states_last_updated[i] = time_now;\n                            immediate_update = 1;\n                            printf(\"Locking starting\\r\\n\");\n                        }\n                        break;\n                    }\n                    default: {\n                        app_io_data.lock_states[i] = LOCK_STATE_LOCK;\n                        break;\n                    }\n                }\n            }\n            lwesp_sys_unprotect();\n\n            first_time = 0;\n            lwesp_delay(50);\n        }\n        printf(\"Mqtt is not connected anymore\\r\\n\");\n    }\n\nterminate:\n    lwesp_mqtt_client_delete(client);\n    printf(\"MQTT client thread terminate\\r\\n\");\n    lwesp_sys_thread_terminate(NULL);\n}\n"
  },
  {
    "path": "snippets/netconn_client.c",
    "content": "/*\n * Netconn client demonstrates how to connect as a client to server\n * using sequential API from separate thread.\n * \n * it does not use callbacks to obtain connection status.\n * \n * Demo connects to NETCONN_HOST at NETCONN_PORT and sends GET request header,\n * then waits for respond and expects server to close the connection accordingly.\n */\n#include \"netconn_client.h\"\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_netconn.h\"\n\n/**\n * \\brief           Host and port settings\n */\n#define NETCONN_HOST \"example.com\"\n#define NETCONN_PORT 80\n\n/**\n * \\brief           Request header to send on successful connection\n */\nstatic const char request_header[] = \"\"\n                                     \"GET / HTTP/1.1\\r\\n\"\n                                     \"Host: \" NETCONN_HOST \"\\r\\n\"\n                                     \"Connection: close\\r\\n\"\n                                     \"\\r\\n\";\n\n/**\n * \\brief           Netconn client thread implementation\n * \\param[in]       arg: User argument\n */\nvoid\nnetconn_client_thread(void const* arg) {\n    lwespr_t res;\n    lwesp_pbuf_p pbuf;\n    lwesp_netconn_p client;\n    lwesp_sys_sem_t* sem = (void*)arg;\n\n    /* Make sure we are connected to access point first */\n    while (!lwesp_sta_has_ip()) {\n        lwesp_delay(1000);\n    }\n\n    /*\n     * First create a new instance of netconn\n     * connection and initialize system message boxes\n     * to accept received packet buffers\n     */\n    client = lwesp_netconn_new(LWESP_NETCONN_TYPE_TCP);\n    if (client != NULL) {\n\n        /*\n         * Connect to external server as client\n         * with custom NETCONN_CONN_HOST and CONN_PORT values\n         *\n         * Function will block thread until we are successfully connected (or not) to server\n         */\n        res = lwesp_netconn_connect(client, NETCONN_HOST, NETCONN_PORT);\n        if (res == lwespOK) { /* Are we successfully connected? */\n            printf(\"Connected to \" NETCONN_HOST \"\\r\\n\");\n            res = lwesp_netconn_write(client, request_header, sizeof(request_header) - 1); /* Send data to server */\n            if (res == lwespOK) {\n                res = lwesp_netconn_flush(client); /* Flush data to output */\n            }\n            if (res == lwespOK) { /* Were data sent? */\n                printf(\"Data were successfully sent to server\\r\\n\");\n\n                /*\n                 * Since we sent HTTP request,\n                 * we are expecting some data from server\n                 * or at least forced connection close from remote side\n                 */\n                do {\n                    /*\n                     * Receive single packet of data\n                     *\n                     * Function will block thread until new packet\n                     * is ready to be read from remote side\n                     *\n                     * After function returns, don't forgot the check value.\n                     * Returned status will give you info in case connection\n                     * was closed too early from remote side\n                     */\n                    res = lwesp_netconn_receive(client, &pbuf);\n                    if (res\n                        == lwespCLOSED) { /* Was the connection closed? This can be checked by return status of receive function */\n                        printf(\"Connection closed by remote side...\\r\\n\");\n                        break;\n                    } else if (res == lwespTIMEOUT) {\n                        printf(\"Netconn timeout while receiving data. You may try multiple readings before deciding to \"\n                               \"close manually\\r\\n\");\n                    }\n\n                    if (res == lwespOK && pbuf != NULL) { /* Make sure we have valid packet buffer */\n                        /*\n                         * At this point, read and manipulate\n                         * with received buffer and check if you expect more data\n                         *\n                         * After you are done using it, it is important\n                         * you free the memory, or memory leaks will appear\n                         */\n                        printf(\"Received new data packet of %d bytes\\r\\n\", (int)lwesp_pbuf_length(pbuf, 1));\n                        lwesp_pbuf_free_s(&pbuf); /* Free the memory after usage */\n                    }\n                } while (1);\n            } else {\n                printf(\"Error writing data to remote host!\\r\\n\");\n            }\n\n            /*\n             * Check if connection was closed by remote server\n             * and in case it wasn't, close it manually\n             */\n            if (res != lwespCLOSED) {\n                lwesp_netconn_close(client);\n            }\n        } else {\n            printf(\"Cannot connect to remote host %s:%d!\\r\\n\", NETCONN_HOST, NETCONN_PORT);\n        }\n        lwesp_netconn_delete(client); /* Delete netconn structure */\n    }\n\n    printf(\"Terminating thread\\r\\n\");\n    if (lwesp_sys_sem_isvalid(sem)) {\n        lwesp_sys_sem_release(sem);\n    }\n    lwesp_sys_thread_terminate(NULL); /* Terminate current thread */\n}\n"
  },
  {
    "path": "snippets/netconn_client_ssl.c",
    "content": "/*\n * Netconn client demonstrates how to connect as a client to server\n * using sequential API from separate thread.\n * \n * it does not use callbacks to obtain connection status.\n * \n * Demo connects to NETCONN_HOST at NETCONN_PORT and sends GET request header,\n * then waits for respond and expects server to close the connection accordingly.\n */\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_netconn.h\"\n#include \"netconn_client.h\"\n\n/* Certificates, ready to be loaded to the flash */\nstatic uint8_t client_ca[] = {\n#include \"../certificates/client_ca_generated_atpki.hex\"\n};\nstatic uint8_t client_cert[] = {\n#include \"../certificates/client_cert_generated_atpki.hex\"\n};\nstatic uint8_t client_key[] = {\n#include \"../certificates/client_key_generated_atpki.hex\"\n};\n\n/**\n * \\brief           Host and port settings\n */\n#define NETCONN_HOST \"example.com\"\n#define NETCONN_PORT 443\n\n/**\n * \\brief           Request header to send on successful connection\n */\nstatic const char request_header[] = \"\"\n                                     \"GET / HTTP/1.1\\r\\n\"\n                                     \"Host: \" NETCONN_HOST \"\\r\\n\"\n                                     \"Connection: close\\r\\n\"\n                                     \"\\r\\n\";\n\n/**\n * \\brief           Netconn client thread implementation\n * \\param[in]       arg: User argument\n */\nvoid\nnetconn_client_ssl_thread(void const* arg) {\n    lwespr_t res;\n    lwesp_pbuf_p pbuf;\n    lwesp_netconn_p client;\n    lwesp_sys_sem_t* sem = (void*)arg;\n\n    /* Make sure we are connected to access point first */\n    while (!lwesp_sta_has_ip()) {\n        lwesp_delay(1000);\n    }\n\n    /*\n     * First create a new instance of netconn\n     * connection and initialize system message boxes\n     * to accept received packet buffers\n     */\n    client = lwesp_netconn_new(LWESP_NETCONN_TYPE_SSL);\n    if (client != NULL) {\n        struct tm dt;\n        uint32_t sntp_interval = 0;\n        uint8_t sntp_en = 0;\n\n        /* Write data to coresponding manuf NVS */\n        res = lwesp_mfg_write(LWESP_MFG_NAMESPACE_CLIENT_CA, \"client_ca.0\", LWESP_MFG_VALTYPE_BLOB, client_ca,\n                              sizeof(client_ca), NULL, NULL, 1);\n        res = lwesp_mfg_write(LWESP_MFG_NAMESPACE_CLIENT_CERT, \"client_cert.0\", LWESP_MFG_VALTYPE_BLOB, client_cert,\n                              sizeof(client_cert), NULL, NULL, 1);\n        res = lwesp_mfg_write(LWESP_MFG_NAMESPACE_CLIENT_KEY, \"client_key.0\", LWESP_MFG_VALTYPE_BLOB, client_key,\n                              sizeof(client_key), NULL, NULL, 1);\n\n        /* Configure SSL for all connections */\n        for (size_t i = 0; i < LWESP_CFG_MAX_CONNS; ++i) {\n            lwesp_conn_ssl_set_config(i, 1, 0, 0, NULL, NULL, 1);\n        }\n\n        /* Ensure SNTP is enabled, time is required for SSL */\n        if (lwesp_sntp_get_config(&sntp_en, NULL, NULL, NULL, NULL, NULL, NULL, 1) == lwespOK) {\n            if (!sntp_en) {\n                lwesp_sntp_set_config(1, 2, NULL, NULL, NULL, NULL, NULL, 1);\n            }\n            lwesp_sntp_get_interval(&sntp_interval, NULL, NULL, 1);\n            printf(\"SNTP interval: %u seconds\\r\\n\", (unsigned)sntp_interval);\n            do {\n                lwesp_sntp_gettime(&dt, NULL, NULL, 1);\n                if (dt.tm_year > 100) {\n                    break;\n                }\n                lwesp_delay(1000);\n            } while (1);\n        }\n\n        /*\n         * Connect to external server as client\n         * with custom NETCONN_CONN_HOST and CONN_PORT values\n         *\n         * Function will block thread until we are successfully connected (or not) to server\n         */\n        res = lwesp_netconn_connect(client, NETCONN_HOST, NETCONN_PORT);\n        if (res == lwespOK) { /* Are we successfully connected? */\n            printf(\"Connected to \" NETCONN_HOST \"\\r\\n\");\n            res = lwesp_netconn_write(client, request_header, sizeof(request_header) - 1); /* Send data to server */\n            if (res == lwespOK) {\n                res = lwesp_netconn_flush(client); /* Flush data to output */\n            }\n            if (res == lwespOK) { /* Were data sent? */\n                printf(\"Data were successfully sent to server\\r\\n\");\n\n                /*\n                 * Since we sent HTTP request,\n                 * we are expecting some data from server\n                 * or at least forced connection close from remote side\n                 */\n                do {\n                    /*\n                     * Receive single packet of data\n                     *\n                     * Function will block thread until new packet\n                     * is ready to be read from remote side\n                     *\n                     * After function returns, don't forgot the check value.\n                     * Returned status will give you info in case connection\n                     * was closed too early from remote side\n                     */\n                    res = lwesp_netconn_receive(client, &pbuf);\n                    if (res\n                        == lwespCLOSED) { /* Was the connection closed? This can be checked by return status of receive function */\n                        printf(\"Connection closed by remote side...\\r\\n\");\n                        break;\n                    } else if (res == lwespTIMEOUT) {\n                        printf(\"Netconn timeout while receiving data. You may try multiple readings before deciding to \"\n                               \"close manually\\r\\n\");\n                    }\n\n                    if (res == lwespOK && pbuf != NULL) { /* Make sure we have valid packet buffer */\n                        /*\n                         * At this point, read and manipulate\n                         * with received buffer and check if you expect more data\n                         *\n                         * After you are done using it, it is important\n                         * you free the memory, or memory leaks will appear\n                         */\n                        printf(\"Received new data packet of %d bytes\\r\\n\", (int)lwesp_pbuf_length(pbuf, 1));\n                        lwesp_pbuf_free_s(&pbuf); /* Free the memory after usage */\n                    }\n                } while (1);\n            } else {\n                printf(\"Error writing data to remote host!\\r\\n\");\n            }\n\n            /*\n             * Check if connection was closed by remote server\n             * and in case it wasn't, close it manually\n             */\n            if (res != lwespCLOSED) {\n                lwesp_netconn_close(client);\n            }\n        } else {\n            printf(\"Cannot connect to remote host %s:%d!\\r\\n\", NETCONN_HOST, NETCONN_PORT);\n        }\n        lwesp_netconn_delete(client); /* Delete netconn structure */\n    }\n\n    printf(\"Terminating thread\\r\\n\");\n    if (lwesp_sys_sem_isvalid(sem)) {\n        lwesp_sys_sem_release(sem);\n    }\n    lwesp_sys_thread_terminate(NULL); /* Terminate current thread */\n}\n"
  },
  {
    "path": "snippets/netconn_server.c",
    "content": "/*\n * Netconn server example is based on single \"user\" thread\n * which listens for new connections and accepts them.\n *\n * When a new client is accepted by server,\n * a new thread gets spawned and processes client request \n * separately. When multiple users are connected,\n * they can be processed simultaneously, hence no such latency as in single thread mode.\n * \n * As a drawback, more memory is consumed for multiple parallel threads being potentially\n * used at the same period of time.\n */\n#include \"netconn_server.h\"\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_netconn.h\"\n\nstatic void netconn_server_processing_thread(void* const arg);\n\n/**\n * \\brief           Main page response file\n */\nstatic const uint8_t rlwesp_data_mainpage_top[] =\n    \"\"\n    \"HTTP/1.1 200 OK\\r\\n\"\n    \"Content-Type: text/html\\r\\n\"\n    \"\\r\\n\"\n    \"<html>\"\n    \"   <head>\"\n    \"       <link rel=\\\"stylesheet\\\" href=\\\"style.css\\\" type=\\\"text/css\\\" />\"\n    \"       <meta http-equiv=\\\"refresh\\\" content=\\\"1\\\" />\"\n    \"   </head>\"\n    \"   <body>\"\n    \"       <p>Netconn driven website!</p>\"\n    \"       <p>Total system up time: <b>\";\n\n/**\n * \\brief           Bottom part of main page\n */\nstatic const uint8_t rlwesp_data_mainpage_bottom[] = \"\"\n                                                     \"       </b></p>\"\n                                                     \"   </body>\"\n                                                     \"</html>\";\n\n/**\n * \\brief           Style file response\n */\nstatic const uint8_t rlwesp_data_style[] = \"\"\n                                           \"HTTP/1.1 200 OK\\r\\n\"\n                                           \"Content-Type: text/css\\r\\n\"\n                                           \"\\r\\n\"\n                                           \"body { color: red; font-family: Tahoma, Arial; };\";\n\n/**\n * \\brief           404 error response\n */\nstatic const uint8_t rlwesp_error_404[] = \"\"\n                                          \"HTTP/1.1 404 Not Found\\r\\n\"\n                                          \"\\r\\n\"\n                                          \"Error 404\";\n\n/**\n * \\brief           Netconn server thread implementation\n * \\param[in]       arg: User argument\n */\nvoid\nnetconn_server_thread(void const* arg) {\n    lwespr_t res;\n    lwesp_netconn_p server, client;\n\n    LWESP_UNUSED(arg);\n\n    /*\n     * First create a new instance of netconn\n     * connection and initialize system message boxes\n     * to accept clients and packet buffers\n     */\n    server = lwesp_netconn_new(LWESP_NETCONN_TYPE_TCP);\n    if (server != NULL) {\n        printf(\"Server netconn created\\r\\n\");\n\n        /* Bind network connection to port 80 */\n        res = lwesp_netconn_bind(server, 80);\n        if (res == lwespOK) {\n            printf(\"Server netconn listens on port 80\\r\\n\");\n            /*\n             * Start listening for incoming connections\n             * on previously binded port\n             */\n            res = lwesp_netconn_listen(server);\n\n            while (1) {\n                /*\n                 * Wait and accept new client connection\n                 *\n                 * Function will block thread until\n                 * new client is connected to server\n                 */\n                res = lwesp_netconn_accept(server, &client);\n                if (res == lwespOK) {\n                    printf(\"Netconn new client connected. Starting new thread...\\r\\n\");\n                    /*\n                     * Start new thread for this request.\n                     *\n                     * Read and write back data to user in separated thread\n                     * to allow processing of multiple requests at the same time\n                     */\n                    if (lwesp_sys_thread_create(NULL, \"client\", (lwesp_sys_thread_fn)netconn_server_processing_thread,\n                                                client, 512, LWESP_SYS_THREAD_PRIO)) {\n                        printf(\"Netconn client thread created\\r\\n\");\n                    } else {\n                        printf(\"Netconn client thread creation failed!\\r\\n\");\n\n                        /* Force close & delete */\n                        lwesp_netconn_close(client);\n                        lwesp_netconn_delete(client);\n                    }\n                } else {\n                    printf(\"Netconn connection accept error!\\r\\n\");\n                    break;\n                }\n            }\n        } else {\n            printf(\"Netconn server cannot bind to port\\r\\n\");\n        }\n    } else {\n        printf(\"Cannot create server netconn\\r\\n\");\n    }\n\n    printf(\"Terminating thread\\r\\n\");\n    lwesp_netconn_delete(server);     /* Delete netconn structure */\n    lwesp_sys_thread_terminate(NULL); /* Terminate current thread */\n}\n\n/**\n * \\brief           Thread to process single active connection\n * \\param[in]       arg: Thread argument\n */\nstatic void\nnetconn_server_processing_thread(void* const arg) {\n    lwesp_netconn_p client = arg;\n    lwesp_pbuf_p pbuf, p = NULL;\n    lwespr_t res;\n    char strt[20];\n\n    printf(\"A new connection accepted!\\r\\n\"); /* Print simple message */\n\n    do {\n        /*\n         * Client was accepted, we are now\n         * expecting client will send to us some data\n         *\n         * Wait for data and block thread for that time\n         */\n        res = lwesp_netconn_receive(client, &pbuf);\n\n        if (res == lwespOK) {\n            printf(\"Netconn data received, %d bytes\\r\\n\", (int)lwesp_pbuf_length(pbuf, 1));\n            /* Check reception of all header bytes */\n            if (p == NULL) {\n                p = pbuf; /* Set as first buffer */\n            } else {\n                lwesp_pbuf_cat(p, pbuf); /* Concatenate buffers together */\n            }\n            /*\n             * Search for end of request section, that is supposed\n             * to end with line, followed by another fully empty line.\n             */\n            if (lwesp_pbuf_strfind(pbuf, \"\\r\\n\\r\\n\", 0) != LWESP_SIZET_MAX) {\n                if (lwesp_pbuf_strfind(pbuf, \"GET / \", 0) != LWESP_SIZET_MAX) {\n                    uint32_t now;\n                    printf(\"Main page request\\r\\n\");\n                    now = lwesp_sys_now(); /* Get current time */\n                    sprintf(strt, \"%u ms; %d s\", (unsigned)now, (unsigned)(now / 1000));\n                    lwesp_netconn_write(client, rlwesp_data_mainpage_top, sizeof(rlwesp_data_mainpage_top) - 1);\n                    lwesp_netconn_write(client, strt, strlen(strt));\n                    lwesp_netconn_write(client, rlwesp_data_mainpage_bottom, sizeof(rlwesp_data_mainpage_bottom) - 1);\n                } else if (lwesp_pbuf_strfind(pbuf, \"GET /style.css \", 0) != LWESP_SIZET_MAX) {\n                    printf(\"Style page request\\r\\n\");\n                    lwesp_netconn_write(client, rlwesp_data_style, sizeof(rlwesp_data_style) - 1);\n                } else {\n                    printf(\"404 error not found\\r\\n\");\n                    lwesp_netconn_write(client, rlwesp_error_404, sizeof(rlwesp_error_404) - 1);\n                }\n                lwesp_netconn_close(client); /* Close netconn connection */\n                lwesp_pbuf_free_s(&p);       /* Do not forget to free memory after usage! */\n                break;\n            }\n        }\n    } while (res == lwespOK);\n\n    if (p != NULL) { /* Free received data */\n        lwesp_pbuf_free_s(&p);\n    }\n    lwesp_netconn_delete(client);     /* Destroy client memory */\n    lwesp_sys_thread_terminate(NULL); /* Terminate this thread */\n}\n"
  },
  {
    "path": "snippets/netconn_server_1thread.c",
    "content": "/*\n * Netconn server example is based on single thread\n * and it listens for single client only on port 23.\n * \n * When new client connects, application processes client in the same thread.\n * When multiple clients get connected at the same time, \n * each of them waits all previous to be processed first, hence it may\n * introduce latency, in some cases even clearly visible in (for example) user browser \n */\n#include \"netconn_server_1thread.h\"\n#include \"lwesp/lwesp_netconn.h\"\n#include \"lwesp/lwesp.h\"\n\n/**\n * \\brief           Basic thread for netconn server to test connections\n * \\param[in]       arg: User argument\n */\nvoid\nnetconn_server_1thread_thread(void* arg) {\n    lwespr_t res;\n    lwesp_netconn_p server, client;\n    lwesp_pbuf_p p;\n\n    LWESP_UNUSED(arg);\n\n    /* Create netconn for server */\n    server = lwesp_netconn_new(LWESP_NETCONN_TYPE_TCP);\n    if (server == NULL) {\n        printf(\"Cannot create server netconn!\\r\\n\");\n    }\n\n    /* Bind it to port 23 */\n    res = lwesp_netconn_bind(server, 23);\n    if (res != lwespOK) {\n        printf(\"Cannot bind server\\r\\n\");\n        goto out;\n    }\n\n    /* Start listening for incoming connections with maximal 1 client */\n    res = lwesp_netconn_listen_with_max_conn(server, 1);\n    if (res != lwespOK) {\n        goto out;\n    }\n\n    /* Unlimited loop */\n    while (1) {\n        /* Accept new client */\n        res = lwesp_netconn_accept(server, &client);\n        if (res != lwespOK) {\n            break;\n        }\n        printf(\"New client accepted!\\r\\n\");\n        while (1) {\n            /* Receive data */\n            res = lwesp_netconn_receive(client, &p);\n            if (res == lwespOK) {\n                printf(\"Data received!\\r\\n\");\n                lwesp_pbuf_free_s(&p);\n            } else {\n                printf(\"Netconn receive returned: %d\\r\\n\", (int)res);\n                if (res == lwespCLOSED) {\n                    printf(\"Connection closed by client\\r\\n\");\n                    break;\n                }\n            }\n        }\n        /* Delete client */\n        if (client != NULL) {\n            lwesp_netconn_delete(client);\n            client = NULL;\n        }\n    }\n    /* Delete client */\n    if (client != NULL) {\n        lwesp_netconn_delete(client);\n        client = NULL;\n    }\n\nout:\n    printf(\"Terminating netconn thread!\\r\\n\");\n    if (server != NULL) {\n        lwesp_netconn_delete(server);\n    }\n    lwesp_sys_thread_terminate(NULL);\n}\n"
  },
  {
    "path": "snippets/sntp.c",
    "content": "/*\n * A simple example to get current time using SNTP protocol\n * thanks to AT commands being supported by Espressif\n */\n#include \"sntp.h\"\n#include \"lwesp/lwesp.h\"\n\n/**\n * \\brief           Run SNTP\n */\nvoid\nsntp_gettime(void) {\n    struct tm dt;\n\n    /* Enable SNTP with default configuration for NTP servers */\n    if (lwesp_sntp_set_config(1, 1, NULL, NULL, NULL, NULL, NULL, 1) == lwespOK) {\n        lwesp_delay(5000);\n\n        /* Get actual time and print it */\n        if (lwesp_sntp_gettime(&dt, NULL, NULL, 1) == lwespOK) {\n            printf(\"Date & time: %d.%d.%d, %d:%d:%d\\r\\n\", (int)dt.tm_mday, (int)(dt.tm_mon + 1),\n                   (int)(dt.tm_year + 1900), (int)dt.tm_hour, (int)dt.tm_min, (int)dt.tm_sec);\n        }\n    }\n}\n"
  },
  {
    "path": "snippets/station_manager.c",
    "content": "/*\n * Station manager to connect station to access point.\n *\n * It is consider as a utility module, simple set of helper functions\n * to quickly connect to access point.\n * \n * It utilizes 2 different modes, sequential or asynchronous.\n * \n * Sequential:\n * ==========\n * Call station_manager_connect_to_preferred_access_point function to connect to access point\n * in blocking mode until being ready to move forward.\n * \n * Asynchronous:\n * ============\n * Call station_manager_connect_to_access_point_async_init to initialize\n * asynchronous connect mode and activity will react upon received LwESP events to application.\n * \n * Define list of access points:\n * ============================\n * Have a look at \"ap_list_preferred\" variable and define\n * list of preferred access point's SSID and password.\n * Ordered by \"most preferred\" at the lower array index.\n */\n#include \"station_manager.h\"\n#include \"lwesp/lwesp.h\"\n#include \"utils.h\"\n\n/**\n * \\brief           Private access-point and station management system\n * \n * This is used for asynchronous connection to access point\n */\ntypedef struct {\n    size_t index_preferred_list; /*!< Current index position of preferred array */\n    size_t index_scanned_list;   /*!< Current index position in array of scanned APs */\n\n    uint8_t command_is_running; /*!< Indicating if command is currently in progress */\n} prv_ap_data_t;\n\n/* Arguments for callback function */\n#define ARG_SCAN    (void*)1\n#define ARG_CONNECT (void*)2\n\n/* Function declaration */\nstatic void prv_cmd_event_fn(lwespr_t status, void* arg);\nstatic void prv_try_next_access_point(void);\n\n/*\n * List of preferred access points for ESP device\n * SSID and password\n *\n * ESP will try to scan for access points\n * and then compare them with the one on the list below\n */\nstatic const ap_entry_t ap_list_preferred[] = {\n    //{ .ssid = \"SSID name\", .pass = \"SSID password\" },\n    {.ssid = \"TilenM_ST\", .pass = \"its private\"},\n    {.ssid = \"404WiFiNotFound\", .pass = \"its private\"},\n    {.ssid = \"Majerle WIFI\", .pass = \"majerle_internet_private\"},\n    {.ssid = \"Majerle AMIS\", .pass = \"majerle_internet_private\"},\n};\nstatic lwesp_ap_t ap_list_scanned[100]; /* Scanned access points information */\nstatic size_t ap_list_scanned_len = 0;  /* Number of scanned access points */\nstatic prv_ap_data_t ap_async_data;     /* Asynchronous data structure */\n\n/* Command to execute to start scanning access points */\n#define prv_scan_ap_command_ex(blocking)                                                                               \\\n    lwesp_sta_list_ap(NULL, ap_list_scanned, LWESP_ARRAYSIZE(ap_list_scanned), &ap_list_scanned_len, NULL, NULL,       \\\n                      (blocking))\n#define prv_scan_ap_command()                                                                                          \\\n    do {                                                                                                               \\\n        if (!ap_async_data.command_is_running) {                                                                       \\\n            ap_async_data.command_is_running =                                                                         \\\n                lwesp_sta_list_ap(NULL, ap_list_scanned, LWESP_ARRAYSIZE(ap_list_scanned), &ap_list_scanned_len,       \\\n                                  prv_cmd_event_fn, ARG_SCAN, 0)                                                       \\\n                == lwespOK;                                                                                            \\\n        }                                                                                                              \\\n    } while (0)\n\n/**\n * \\brief           Every internal command execution callback\n * \\param[in]       status: Execution status result\n * \\param[in]       arg: Custom user argument\n */\nstatic void\nprv_cmd_event_fn(lwespr_t status, void* arg) {\n    LWESP_UNUSED(status);\n    /*\n     * Command has now successfully finish\n     * and callbacks have been properly processed\n     */\n    ap_async_data.command_is_running = 0;\n\n    if (arg == ARG_SCAN) {\n        /* Immediately try to connect to access point after successful scan */\n        prv_try_next_access_point();\n    }\n}\n\n/**\n * \\brief           Try to connect to next access point on a list \n */\nstatic void\nprv_try_next_access_point(void) {\n    uint8_t tried = 0;\n\n    /* No action to be done if command is currently in progress or already connected to network */\n    if (ap_async_data.command_is_running || lwesp_sta_has_ip()) {\n        return;\n    }\n\n    /*\n     * Process complete list and try to find suitable match\n     *\n     * Use global variable for indexes to be able to call function multiple times\n     * and continue where it finished previously\n     */\n\n    /* List all preferred access points */\n    for (; ap_async_data.index_preferred_list < LWESP_ARRAYSIZE(ap_list_preferred);\n         ap_async_data.index_preferred_list++, ap_async_data.index_scanned_list = 0) {\n\n        /* List all scanned access points */\n        for (; ap_async_data.index_scanned_list < ap_list_scanned_len; ap_async_data.index_scanned_list++) {\n\n            /* Find a match if available */\n            if (strncmp(ap_list_scanned[ap_async_data.index_scanned_list].ssid,\n                        ap_list_preferred[ap_async_data.index_preferred_list].ssid,\n                        strlen(ap_list_preferred[ap_async_data.index_preferred_list].ssid))\n                == 0) {\n\n                /* Try to connect to the network */\n                if (!ap_async_data.command_is_running\n                    && lwesp_sta_join(ap_list_preferred[ap_async_data.index_preferred_list].ssid,\n                                      ap_list_preferred[ap_async_data.index_preferred_list].pass, NULL,\n                                      prv_cmd_event_fn, ARG_CONNECT, 0)\n                           == lwespOK) {\n                    ap_async_data.command_is_running = 1;\n\n                    /* Go to next index for sub-for loop and exit */\n                    ap_async_data.index_scanned_list++;\n                    tried = 1;\n                    goto stp;\n                } else {\n                    /* We have a problem, needs to resume action in next run */\n                }\n            }\n        }\n    }\n\n    /* Restart scan operation if there was no try to connect and station has no IP */\n    if (!tried && !lwesp_sta_has_ip()) {\n        prv_scan_ap_command();\n    }\nstp:\n    return;\n}\n\n/**\n * \\brief           Private event function for asynchronous scanning\n * \\param[in]       evt: Event information\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nstatic lwespr_t\nprv_evt_fn(lwesp_evt_t* evt) {\n    switch (evt->type) {\n        case LWESP_EVT_KEEP_ALIVE:\n        case LWESP_EVT_WIFI_DISCONNECTED: {\n            /* Try to connect to next access point */\n            prv_try_next_access_point();\n            break;\n        }\n        case LWESP_EVT_STA_LIST_AP: {\n            /*\n             * After scanning gets completed\n             * manually reset all indexes for comparison purposes\n             */\n            ap_async_data.index_scanned_list = 0;\n            ap_async_data.index_preferred_list = 0;\n\n            /* Actual connection try is done in function callback */\n            break;\n        }\n        default: break;\n    }\n    return lwespOK;\n}\n\n/**\n * \\brief           Initialize asynchronous mode to connect to preferred access point\n *\n * Asynchronous mode relies on system events received by the application,\n * to determine current device status if station is being, or not, connected to access point.\n *\n * When used, async acts only upon station connection change through callbacks,\n * therefore it does not require additional system thread or user code,\n * to be able to properly handle preferred access points.\n * This certainly decreases memory consumption of the complete system.\n *\n * \\ref LWESP_CFG_KEEP_ALIVE feature must be enable to properly handle all events\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t otherwise\n */\nlwespr_t\nstation_manager_connect_to_access_point_async_init(void) {\n    /* Register system event function */\n    lwesp_evt_register(prv_evt_fn);\n\n    /*\n     * Start scanning process in non-blocking mode\n     *\n     * This is the only command being executed from non-callback mode,\n     * therefore it must be protected against other threads trying to access the same core\n     */\n    lwesp_core_lock();\n    prv_scan_ap_command();\n    lwesp_core_unlock();\n\n    /* Return all good, things will progress (from now-on) asynchronously */\n    return lwespOK;\n}\n\n/**\n * \\brief           Connect to preferred access point in blocking mode\n * \n * This functionality can only be used if non-blocking approach is not used\n * \n * \\note            List of access points should be set by user in \\ref ap_list structure\n * \\param[in]       unlimited: When set to 1, function will block until SSID is found and connected\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nlwespr_t\nstation_manager_connect_to_preferred_access_point(uint8_t unlimited) {\n    lwespr_t eres;\n    uint8_t tried;\n\n    /*\n     * Scan for network access points\n     * In case we have access point,\n     * try to connect to known AP\n     */\n    do {\n        if (lwesp_sta_has_ip()) {\n            return lwespOK;\n        }\n\n        /* Scan for access points visible to ESP device */\n        printf(\"Scanning access points...\\r\\n\");\n        if ((eres = prv_scan_ap_command_ex(1)) == lwespOK) {\n            tried = 0;\n\n            /* Print all access points found by ESP */\n            for (size_t i = 0; i < ap_list_scanned_len; i++) {\n                printf(\"AP found: %s, CH: %d, RSSI: %d\\r\\n\", ap_list_scanned[i].ssid, ap_list_scanned[i].ch,\n                       ap_list_scanned[i].rssi);\n            }\n\n            /* Process array of preferred access points with array of found points */\n            for (size_t j = 0; j < LWESP_ARRAYSIZE(ap_list_preferred); j++) {\n\n                /* Go through all scanned list */\n                for (size_t i = 0; i < ap_list_scanned_len; i++) {\n\n                    /* Try to find a match between preferred and scanned */\n                    if (strncmp(ap_list_scanned[i].ssid, ap_list_preferred[j].ssid, strlen(ap_list_scanned[i].ssid))\n                        == 0) {\n                        tried = 1;\n                        printf(\"Connecting to \\\"%s\\\" network...\\r\\n\", ap_list_preferred[j].ssid);\n\n                        /* Try to join to access point */\n                        if ((eres = lwesp_sta_join(ap_list_preferred[j].ssid, ap_list_preferred[j].pass, NULL, NULL,\n                                                   NULL, 1))\n                            == lwespOK) {\n                            lwesp_ip_t ip;\n                            uint8_t is_dhcp;\n\n                            printf(\"Connected to %s network!\\r\\n\", ap_list_preferred[j].ssid);\n\n                            lwesp_sta_copy_ip(&ip, NULL, NULL, &is_dhcp);\n                            utils_print_ip(\"Station IP address: \", &ip, \"\\r\\n\");\n                            printf(\"; Is DHCP: %d\\r\\n\", (int)is_dhcp);\n                            return lwespOK;\n                        } else {\n                            printf(\"Connection error: %d\\r\\n\", (int)eres);\n                        }\n                    }\n                }\n            }\n            if (!tried) {\n                printf(\"No access points available with preferred SSID!\\r\\nPlease check station_manager.c file and \"\n                       \"edit preferred SSID access points!\\r\\n\");\n            }\n        } else if (eres == lwespERRNODEVICE) {\n            printf(\"Device is not present!\\r\\n\");\n            break;\n        } else {\n            printf(\"Error on WIFI scan procedure!\\r\\n\");\n        }\n        if (!unlimited) {\n            break;\n        }\n    } while (1);\n    return lwespERR;\n}\n"
  },
  {
    "path": "snippets/telnet_server.c",
    "content": "/*\n * Telnet server example is based on single \"user\" thread\n * which listens for new connections and accept it.\n *\n * Only one connection is allowed for Telnet server\n */\n\n#include <stdarg.h> /* Required for printf */\n#include <stdbool.h>\n#include \"cli/cli.h\"\n#include \"cli/cli_input.h\"\n#include \"lwesp/lwesp.h\"\n#include \"lwesp/lwesp_cli.h\"\n#include \"lwesp/lwesp_netconn.h\"\n\nstatic lwesp_netconn_p client;\nstatic bool close_conn = false;\n\nstatic void telnet_cli_exit(cli_printf cliprintf, int argc, char** argv);\n\nstatic const cli_command_t telnet_commands[] = {\n    {\"exit\", \"Close/Exit the terminal\", telnet_cli_exit},\n    {\"close\", \"Close/Exit the terminal\", telnet_cli_exit},\n};\n\n/**\n * \\brief           Telnet CLI to terminate the telnet connection\n * \\param[in]       cliprintf: Pointer to CLI printf function\n * \\param[in]       argc: Number fo arguments in argv\n * \\param[in]       argv: Pointer to the commands arguments\n */\nstatic void\ntelnet_cli_exit(cli_printf cliprintf, int argc, char** argv) {\n    LWESP_UNUSED(cliprintf);\n    LWESP_UNUSED(argc);\n    LWESP_UNUSED(argv);\n    close_conn = true;\n}\n\n/**\n * \\brief           Telnet CLI printf, used for CLI commands\n * \\param[in]       fmt: Format for the printf\n */\nstatic void\ntelnet_cli_printf(const char* fmt, ...) {\n    static char tempStr[128];\n    va_list argptr;\n    int len = 1;\n\n    memset(&tempStr, 0x00, sizeof(tempStr));\n    va_start(argptr, fmt);\n    len = vsprintf(tempStr, fmt, argptr);\n    va_end(argptr);\n\n    if (len > 0 && len < 128) {\n        lwesp_netconn_write(client, (uint8_t*)tempStr, len);\n        lwesp_netconn_flush(client);\n    }\n}\n\n/**\n * \\brief           Telnet client config (disable ECHO and LINEMOD)\n * \\param[in]       nc: Netconn handle used to write data to\n * \\return          \\ref lwespOK on success, member of \\ref lwespr_t enumeration otherwise\n */\nstatic lwespr_t\ntelnet_client_config(lwesp_netconn_p nc) {\n    lwespr_t res;\n    uint8_t cfg_data[12];\n\n    /* do echo 'I will echo your chars' (RFC 857) */\n    cfg_data[0] = 0xFF;\n    cfg_data[1] = 0xFD;\n    cfg_data[2] = 0x01;\n    /* will echo */\n    cfg_data[3] = 0xFF;\n    cfg_data[4] = 0xFB;\n    cfg_data[5] = 0x01;\n    /* will SGA */\n    cfg_data[6] = 0xFF;\n    cfg_data[7] = 0xFB;\n    cfg_data[8] = 0x03;\n    /* don't LINEMODE 'Send each char as you get it' (RFC 1184) */\n    cfg_data[9] = 0xFF;\n    cfg_data[10] = 0xFE;\n    cfg_data[11] = 0x22;\n\n    if ((res = lwesp_netconn_write(nc, cfg_data, sizeof(cfg_data))) != lwespOK) {\n        return res;\n    }\n    return lwesp_netconn_flush(nc);\n}\n\n/**\n * \\brief           Telnet command sequence check\n * \\param[in]       ch: input byte from telnet\n * \\ref             true when command sequence is active, else false\n */\nstatic bool\ntelnet_command_sequence_check(unsigned char ch) {\n    static uint32_t telnet_command_sequence = 0;\n    bool command_sequence_found = false;\n\n    if (!telnet_command_sequence && ch == 0xFF) {\n        command_sequence_found = true;\n        telnet_command_sequence = 1;\n        printf(\"AIC   \");\n    } else if (telnet_command_sequence == 1) {\n        command_sequence_found = true;\n        telnet_command_sequence = 2;\n        if (ch == 251) {\n            printf(\"%-8s \", \"WILL\");\n        } else if (ch == 252) {\n            printf(\"%-8s \", \"WON'T\");\n        } else if (ch == 253) {\n            printf(\"%-8s \", \"DO\");\n        } else if (ch == 254) {\n            printf(\"%-8s \", \"DON'T\");\n        } else {\n            printf(\"%-8s \", \"UNKNOWN\");\n        }\n    } else if (telnet_command_sequence == 2) {\n        command_sequence_found = true;\n        telnet_command_sequence = 0;\n        switch (ch) {\n            case 0: printf(\"Binary Transmission 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 1: printf(\"Echo 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 2: printf(\"Reconnection 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 3: printf(\"Suppress Go Ahead 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 4: printf(\"Approx Message Size Negotiation 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 5: printf(\"Status 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 6: printf(\"Timing Mark 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 7: printf(\"Remote Controlled Trans and Echo 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 8: printf(\"Output Line Width 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 9: printf(\"Output Page Size 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 10: printf(\"Output Carriage-Return Disposition 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 11: printf(\"Output Horizontal Tab Stops 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 12: printf(\"Output Horizontal Tab Disposition 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 13: printf(\"Output Formfeed Disposition 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 14: printf(\"Output Vertical Tabstops 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 15: printf(\"Output Vertical Tab Disposition 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 16: printf(\"Output Linefeed Disposition 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 17: printf(\"Extended ASCII 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 18: printf(\"Logout 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 19: printf(\"Byte Macro 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 20: printf(\"Data Entry Terminal 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 21: printf(\"SUPDUP 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 22: printf(\"SUPDUP Output 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 23: printf(\"Send Location 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 24: printf(\"Terminal Type 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 25: printf(\"End of Record 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 26: printf(\"TACACS User Identification 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 27: printf(\"Output Marking 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 28: printf(\"Terminal Location Number 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 29: printf(\"Telnet 3270 Regime 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 30: printf(\"X.3 PAD 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 31: printf(\"Negotiate About Window Size 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 32: printf(\"Terminal Speed 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 33: printf(\"Remote Flow Control 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 34: printf(\"Linemode 0x%02x-%d\\r\\n\", ch, ch); break;\n            case 35: printf(\"X Display Location 0x%02x-%d\\r\\n\", ch, ch); break;\n            default: printf(\"UNKNOWN 0x%02x-%d \\n\\r\", ch, ch);\n        }\n    }\n\n    return command_sequence_found;\n}\n\n/**\n * \\brief           Telnet server thread implementation\n * \\param[in]       arg: User argument\n */\nvoid\ntelnet_server_thread(void const* arg) {\n    lwespr_t res;\n    lwesp_pbuf_p pbuf;\n    lwesp_netconn_p server;\n\n    LWESP_UNUSED(arg);\n\n    /*\n     * First create a new instance of netconn\n     * connection and initialize system message boxes\n     * to accept clients and packet buffers\n     */\n    if ((server = lwesp_netconn_new(LWESP_NETCONN_TYPE_TCP)) == NULL) {\n        printf(\"Cannot create Telnet server\\r\\n\");\n        return;\n    }\n    printf(\"Server telnet created\\r\\n\");\n\n    /* Bind network connection to port 23 */\n    if ((res = lwesp_netconn_bind(server, 23)) != lwespOK) {\n        printf(\"Telnet server cannot bind to port\\r\\n\");\n        lwesp_netconn_delete(server);\n        return;\n    }\n    printf(\"Server telnet listens on port 23\\r\\n\");\n\n    /* Init command line interface and add telnet commands */\n    cli_init();\n    cli_register_commands(telnet_commands, LWESP_ARRAYSIZE(telnet_commands));\n    lwesp_cli_register_commands();\n\n    /*\n     * Start listening for incoming connections\n     * on previously binded port\n     */\n    res = lwesp_netconn_listen_with_max_conn(server, 1);\n    while (1) {\n        /*\n         * Wait and accept new client connection\n         *\n         * Function will block thread until\n         * new client is connected to server\n         */\n        if ((res = lwesp_netconn_accept(server, &client)) != lwespOK) {\n            printf(\"Telnet connection accept error!\\r\\n\");\n            break;\n        }\n\n        printf(\"Telnet new client connected.\\r\\n\");\n\n        /*\n         * Inform telnet client that it should disable LINEMODE\n         * and that we will echo for him.\n         */\n        if ((res = telnet_client_config(client)) != lwespOK) {\n            break;\n        }\n\n        while (1) {\n            const uint8_t* in_data;\n            size_t length;\n\n            if ((res = lwesp_netconn_receive(client, &pbuf)) == lwespCLOSED) {\n                break;\n            }\n\n            in_data = lwesp_pbuf_data(pbuf);\n            length = lwesp_pbuf_length(pbuf, 1); /* Get length of received packet */\n            for (size_t i = 0; i < length; ++i) {\n                if (!telnet_command_sequence_check(in_data[i])) {\n                    cli_in_data(telnet_cli_printf, in_data[i]);\n                }\n            }\n\n            lwesp_pbuf_free_s(&pbuf);\n            lwesp_netconn_flush(client);\n\n            if (close_conn) {\n                close_conn = false;\n                lwesp_netconn_close(client); /* Close netconn connection */\n                break;\n            }\n        }\n        if (client != NULL) {\n            lwesp_netconn_delete(client); /* Delete netconn connection */\n            client = NULL;\n        }\n    }\n    if (client != NULL) {\n        lwesp_netconn_delete(client); /* Delete netconn connection */\n        client = NULL;\n    }\n\n    lwesp_netconn_delete(server);     /* Delete netconn structure */\n    lwesp_sys_thread_terminate(NULL); /* Terminate current thread */\n}\n"
  },
  {
    "path": "snippets/utils.c",
    "content": "#include \"utils.h\"\n#include \"lwesp/lwesp.h\"\n\n#if WIN32\n#define utils_printf            printf\n#else\n#define utils_printf            printf\n#endif /* WIN32 */\n\n/**\n * \\brief           Print IP string to the output\n * \\param[in]       str_b: Text to print before IP address\n * \\param[in]       ip: IP to print\n * \\param[in]       str_a: Text to print after IP address\n */\nvoid\nutils_print_ip(const char* str_b, const lwesp_ip_t* ip, const char* str_a) {\n    if (str_b != NULL) {\n        utils_printf(\"%s\", str_b);\n    }\n\n    if (0) {\n#if LWESP_CFG_IPV6\n    } else if (ip->type == LWESP_IPTYPE_V6) {\n        utils_printf(\"%04X:%04X:%04X:%04X:%04X:%04X:%04X:%04X\\r\\n\",\n            (unsigned)ip->addr.ip6.addr[0], (unsigned)ip->addr.ip6.addr[1], (unsigned)ip->addr.ip6.addr[2],\n            (unsigned)ip->addr.ip6.addr[3], (unsigned)ip->addr.ip6.addr[4], (unsigned)ip->addr.ip6.addr[5],\n            (unsigned)ip->addr.ip6.addr[6], (unsigned)ip->addr.ip6.addr[7]);\n#endif /* LWESP_CFG_IPV6 */\n    } else {\n        utils_printf(\"%d.%d.%d.%d\\r\\n\",\n            (int)ip->addr.ip4.addr[0], (int)ip->addr.ip4.addr[1],\n            (int)ip->addr.ip4.addr[2], (int)ip->addr.ip4.addr[3]);\n    }\n    if (str_a != NULL) {\n        utils_printf(\"%s\", str_a);\n    }\n}\n\n/**\n * \\brief           Print MAC string to the output\n * \\param[in]       str_b: Text to print before MAC address\n * \\param[in]       mac: MAC to print\n * \\param[in]       str_a: Text to print after MAC address\n */\nvoid\nutils_print_mac(const char* str_b, const lwesp_mac_t* mac, const char* str_a) {\n    if (str_b != NULL) {\n        utils_printf(\"%s\", str_b);\n    }\n    utils_printf(\"%02X:%02X:%02X:%02X:%02X:%02X\\r\\n\",\n        (unsigned)mac->mac[0], (unsigned)mac->mac[1], (unsigned)mac->mac[2],\n        (unsigned)mac->mac[3], (unsigned)mac->mac[4], (unsigned)mac->mac[5]\n    );\n    if (str_a != NULL) {\n        utils_printf(\"%s\", str_a);\n    }\n}\n"
  },
  {
    "path": "www/css/style.css",
    "content": "body { \n\tcolor: red;\n}\n"
  },
  {
    "path": "www/index.shtml",
    "content": "<html>\n   <head>\n       <title><!--#title--></title>\n       <meta http-equiv=\"Refresh\" content=\"1\" />\n       <script src=\"https://ajax.googleapis.com/ajax/libs/jquery/3.2.1/jquery.min.js\"></script>\n       <script src=\"/js/js.js\" type=\"text/javascript\"></script>\n       <link rel=\"stylesheet\" href=\"https://maxcdn.bootstrapcdn.com/bootstrap/4.0.0-beta.2/css/bootstrap.min.css\" />\n       <link rel=\"stylesheet\" type=\"text/css\" href=\"/css/style.css\" />\n    </head>\n    <body>\n        <div class=\"container\">\n            <h1>Welcome to web server hosted by ESP Wi-Fi module!</h1>\n        </div>\n        <footer>\n            <div class=\"container\">\n                Copyright &copy; 2019. All rights reserved. Webserver is hosted on ESP module.\n            </div>\n        </footer>\n    </body>\n</html>"
  }
]